From 60b67c31fcad6d0dc9603a034994a12efe3d5202 Mon Sep 17 00:00:00 2001 From: John Hubbard Date: Sun, 21 Apr 2019 17:09:24 -0700 Subject: Open doc files, version 1 of everything This copies over files from: http://download.nvidia.com/open-gpu-doc/ with a few overrides from local, as-yet-to-be-published files (generally just a file suffix and licensing tweak). Here's the script that was used to create this commit: wget -r http://download.nvidia.com/open-gpu-doc/ mv download.nvidia.com/open-gpu-doc/* . rm -rf download.nvidia.com/ find . -name index.html | xargs rm -f find . -name Thumbs.db | xargs rm -f find . -type f | grep -v \.git | xargs file | grep CRLF | cut -f1 -d: | xargs dos2unix for f in `find . -name 1 | cut -f2 -d "/"`; do pushd $f; mv 1/* .; popd; done find . -name 1 | xargs rmdir rm -rf Host-Fifo/volta/gv100 mkdir -p Host-Fifo/volta/gv100 cp $sw/docs/Public_Devel_Docs/release/Host-Fifo/volta/gv100/* Host-Fifo/volta/gv100/ rm Display-Ref-Manuals/gv100/dev_display.ref cp $sw/docs/Public_Devel_Docs/release/Display-Ref-Manuals/1/gv100/dev_display.ref \ Display-Ref-Manuals/gv100/dev_display.ref.txt git add . git mv DCB/DCB-4.0-Specification.html DCB/DCB-4.x-Specification.html git reset HEAD Display-Class-Methods/2 git reset HEAD DCB/2 git commit Reviewed-by: Andy Ritger --- BIOS-Information-Table/BIOS-Information-Table.html | 2575 ++++++ Compute-Class-Methods/cl50c0.h | 741 ++ Compute-Class-Methods/cl85c0.h | 747 ++ Compute-Class-Methods/cl90c0.h | 1033 +++ Compute-Class-Methods/cl91c0.h | 1049 +++ Compute-Class-Methods/cla0c0.h | 836 ++ Compute-Class-Methods/cla1c0.h | 866 ++ Compute-Class-Methods/clb0c0.h | 931 ++ Compute-Class-Methods/clb1c0.h | 968 ++ Compute-Class-Methods/clc0c0.h | 1006 ++ Compute-Class-Methods/clc1c0.h | 1026 +++ Compute-Class-Methods/clc3c0.h | 912 ++ Compute-Class-Methods/clc5c0.h | 942 ++ Compute-QMD/clc3c0qmd.h | 245 + Compute-QMD/clc5c0qmd.h | 247 + DCB/DCB-4.x-Specification.html | 9712 ++++++++++++++++++++ DCB/Stall_lock_dcb.jpg | Bin 0 -> 41976 bytes DCB/ThermalPower.gif | Bin 0 -> 1401 bytes DCB/ThermalPowerDisable.gif | Bin 0 -> 1812 bytes Devinit/devinit.css | 222 + Devinit/devinit.xml | 6876 ++++++++++++++ Devinit/devinit.xsl | 384 + Display-Class-Methods/README.txt | 142 + Display-Class-Methods/cl507a.h | 56 + Display-Class-Methods/cl507b.h | 59 + Display-Class-Methods/cl507c.h | 194 + Display-Class-Methods/cl507d.h | 676 ++ Display-Class-Methods/cl507e.h | 173 + Display-Class-Methods/cl827a.h | 56 + Display-Class-Methods/cl827b.h | 59 + Display-Class-Methods/cl827c.h | 181 + Display-Class-Methods/cl827d.h | 678 ++ Display-Class-Methods/cl827e.h | 183 + Display-Class-Methods/cl837c.h | 181 + Display-Class-Methods/cl837d.h | 709 ++ Display-Class-Methods/cl837e.h | 195 + Display-Class-Methods/cl857a.h | 56 + Display-Class-Methods/cl857b.h | 59 + Display-Class-Methods/cl857c.h | 188 + Display-Class-Methods/cl857d.h | 1121 +++ Display-Class-Methods/cl857e.h | 195 + Display-Class-Methods/cl887d.h | 1078 +++ Display-Class-Methods/cl907a.h | 56 + Display-Class-Methods/cl907b.h | 59 + Display-Class-Methods/cl907c.h | 254 + Display-Class-Methods/cl907d.h | 1140 +++ Display-Class-Methods/cl907e.h | 255 + Display-Class-Methods/cl917a.h | 56 + Display-Class-Methods/cl917b.h | 60 + Display-Class-Methods/cl917c.h | 290 + Display-Class-Methods/cl917d.h | 1176 +++ Display-Class-Methods/cl917e.h | 257 + Display-Class-Methods/cl927c.h | 291 + Display-Class-Methods/cl927d.h | 1181 +++ Display-Class-Methods/cl947d.h | 1189 +++ Display-Class-Methods/cl957d.h | 1185 +++ Display-Ref-Manuals/gv100/dev_display.ref.txt | 6028 ++++++++++++ Falcon-Security/Falcon-Security.html | 840 ++ Host-Fifo/volta/gv100/dev_bus.ref.txt | 316 + Host-Fifo/volta/gv100/dev_fifo.ref.txt | 639 ++ Host-Fifo/volta/gv100/dev_master.ref.txt | 363 + Host-Fifo/volta/gv100/dev_pbdma.ref.txt | 4261 +++++++++ Host-Fifo/volta/gv100/dev_ram.ref.txt | 1269 +++ Host-Fifo/volta/gv100/dev_timer.ref.txt | 79 + Host-Fifo/volta/gv100/dev_usermode.ref.txt | 134 + MemoryClockTable/MemoryClockTable.html | 711 ++ MemoryTweakTable/MemoryTweakTable.html | 763 ++ Shader-Program-Header/Shader-Program-Header.html | 2550 +++++ .../gk104-disable-graphics-power-gating.txt | 113 + .../gk104-disable-underflow-reporting.txt | 89 + pascal/BIT_DISPLAY_PTRS-U-BIT_DP_PTRS-d.pdf | Bin 0 -> 686639 bytes pascal/gp100-fbpa.txt | 92 + pascal/gp100-mmu-format.pdf | Bin 0 -> 399871 bytes pascal/gp100-msi-intr.txt | 76 + qmd/cla0c0qmd.h | 660 ++ qmd/cla1c0qmd.h | 451 + qmd/clb0c0qmd.h | 454 + qmd/clb1c0qmd.h | 454 + qmd/clc0c0qmd.h | 665 ++ qmd/clc1c0qmd.h | 665 ++ virtual-p-state-table/virtual-P-state-table.html | 1004 ++ 81 files changed, 67682 insertions(+) create mode 100644 BIOS-Information-Table/BIOS-Information-Table.html create mode 100644 Compute-Class-Methods/cl50c0.h create mode 100644 Compute-Class-Methods/cl85c0.h create mode 100644 Compute-Class-Methods/cl90c0.h create mode 100644 Compute-Class-Methods/cl91c0.h create mode 100644 Compute-Class-Methods/cla0c0.h create mode 100644 Compute-Class-Methods/cla1c0.h create mode 100644 Compute-Class-Methods/clb0c0.h create mode 100644 Compute-Class-Methods/clb1c0.h create mode 100644 Compute-Class-Methods/clc0c0.h create mode 100644 Compute-Class-Methods/clc1c0.h create mode 100644 Compute-Class-Methods/clc3c0.h create mode 100644 Compute-Class-Methods/clc5c0.h create mode 100644 Compute-QMD/clc3c0qmd.h create mode 100644 Compute-QMD/clc5c0qmd.h create mode 100644 DCB/DCB-4.x-Specification.html create mode 100644 DCB/Stall_lock_dcb.jpg create mode 100644 DCB/ThermalPower.gif create mode 100644 DCB/ThermalPowerDisable.gif create mode 100644 Devinit/devinit.css create mode 100644 Devinit/devinit.xml create mode 100644 Devinit/devinit.xsl create mode 100644 Display-Class-Methods/README.txt create mode 100644 Display-Class-Methods/cl507a.h create mode 100644 Display-Class-Methods/cl507b.h create mode 100644 Display-Class-Methods/cl507c.h create mode 100644 Display-Class-Methods/cl507d.h create mode 100644 Display-Class-Methods/cl507e.h create mode 100644 Display-Class-Methods/cl827a.h create mode 100644 Display-Class-Methods/cl827b.h create mode 100644 Display-Class-Methods/cl827c.h create mode 100644 Display-Class-Methods/cl827d.h create mode 100644 Display-Class-Methods/cl827e.h create mode 100644 Display-Class-Methods/cl837c.h create mode 100644 Display-Class-Methods/cl837d.h create mode 100644 Display-Class-Methods/cl837e.h create mode 100644 Display-Class-Methods/cl857a.h create mode 100644 Display-Class-Methods/cl857b.h create mode 100644 Display-Class-Methods/cl857c.h create mode 100644 Display-Class-Methods/cl857d.h create mode 100644 Display-Class-Methods/cl857e.h create mode 100644 Display-Class-Methods/cl887d.h create mode 100644 Display-Class-Methods/cl907a.h create mode 100644 Display-Class-Methods/cl907b.h create mode 100644 Display-Class-Methods/cl907c.h create mode 100644 Display-Class-Methods/cl907d.h create mode 100644 Display-Class-Methods/cl907e.h create mode 100644 Display-Class-Methods/cl917a.h create mode 100644 Display-Class-Methods/cl917b.h create mode 100644 Display-Class-Methods/cl917c.h create mode 100644 Display-Class-Methods/cl917d.h create mode 100644 Display-Class-Methods/cl917e.h create mode 100644 Display-Class-Methods/cl927c.h create mode 100644 Display-Class-Methods/cl927d.h create mode 100644 Display-Class-Methods/cl947d.h create mode 100644 Display-Class-Methods/cl957d.h create mode 100644 Display-Ref-Manuals/gv100/dev_display.ref.txt create mode 100644 Falcon-Security/Falcon-Security.html create mode 100644 Host-Fifo/volta/gv100/dev_bus.ref.txt create mode 100644 Host-Fifo/volta/gv100/dev_fifo.ref.txt create mode 100644 Host-Fifo/volta/gv100/dev_master.ref.txt create mode 100644 Host-Fifo/volta/gv100/dev_pbdma.ref.txt create mode 100644 Host-Fifo/volta/gv100/dev_ram.ref.txt create mode 100644 Host-Fifo/volta/gv100/dev_timer.ref.txt create mode 100644 Host-Fifo/volta/gv100/dev_usermode.ref.txt create mode 100644 MemoryClockTable/MemoryClockTable.html create mode 100644 MemoryTweakTable/MemoryTweakTable.html create mode 100644 Shader-Program-Header/Shader-Program-Header.html create mode 100644 gk104-disable-graphics-power-gating/gk104-disable-graphics-power-gating.txt create mode 100644 gk104-disable-underflow-reporting/gk104-disable-underflow-reporting.txt create mode 100644 pascal/BIT_DISPLAY_PTRS-U-BIT_DP_PTRS-d.pdf create mode 100644 pascal/gp100-fbpa.txt create mode 100644 pascal/gp100-mmu-format.pdf create mode 100644 pascal/gp100-msi-intr.txt create mode 100644 qmd/cla0c0qmd.h create mode 100644 qmd/cla1c0qmd.h create mode 100644 qmd/clb0c0qmd.h create mode 100644 qmd/clb1c0qmd.h create mode 100644 qmd/clc0c0qmd.h create mode 100644 qmd/clc1c0qmd.h create mode 100644 virtual-p-state-table/virtual-P-state-table.html diff --git a/BIOS-Information-Table/BIOS-Information-Table.html b/BIOS-Information-Table/BIOS-Information-Table.html new file mode 100644 index 0000000..73800ec --- /dev/null +++ b/BIOS-Information-Table/BIOS-Information-Table.html @@ -0,0 +1,2575 @@ + + + + + +NVIDIA BIOS Information Table Specification + + + + +
+
+
+
+

Purpose

+
+

This document describes the BIOS Information Table (BIT), the +top-level description table in the NVIDIA VBIOS.

+

The BIT points to various code sections and data tables used by both the +BIOS and driver software. The tables typically contain GPU and +board-specific information.

+

VBIOS pointers may point to data beyond the end of the PC-compatible (legacy BIOS, Code Type 00h) image. If a UEFI (Code Type 03h) image follows the PC-compatible image, then the pointer must be adjusted to be an offset into the data following the UEFi Image.

+

If (pointer > PC-compatible image length) { + adjusted_pointer = pointer + UEFI image length +}

+

A GPU firmware file (.ROM) may contain data for HW consumption preceding the PCI Expansion ROM contents. The start of the PCI Expansion ROM can be found by checking 512 byte boundaries for the {055h,0AAh} PCI Expansion ROM signature. Additionally, the pointer to the PCI Data Structure should be followed and checked for the "PCIR" PCI Data Structure signature to confirm a valid PCI Expansion ROM has been found. +When reading the firmware in a system using MMIO the PCI Expansion ROM will begin at PCI Expansion ROM BAR + offset 0.

+

BIOS Information Table Structure

+

The BIT is a series of tokenized structures, beginning with a BIT +definition structure, and a series of BIT tokens and data pointers. The +data pointers point to a grouping of data items that are used by +NVIDIA software to locate, use, and/or modify device-specific data.

+

BIT Header

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values Meaning

ID

16

0xB8FF

BIT Header Identifier

Signature

32

"BIT\0"

BIT Header Signature

BCD Version

16

0x0100

BCD Version 1.00 (major version in the upper byte, minor version in the lower byte)

Header Size

8

12

Size of BIT Header (in bytes)

Token Size

8

6

Size of BIT Tokens (in bytes)

Token Entries

8

?

Number of token entries that follow

Checksum

8

0

BIT Header Checksum

+
+
+

BIT Token Structure

+
+

Each BIT token has the same format and length. Prior knowledge of the +data format, based on the data version indicated, is necessary to access +the actual data.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

ID

8

Unique identifier indicating what data is pointed to by the Data Pointer

Data Version

8

Version of the data structure pointed to by the Data Pointer

Data Size

16

Size of data structure pointed to by the Data Pointer (in bytes)

Data Pointer

16

Pointer (offset) to the actual data structure. A NULL (0) pointer indicates no data exists for this token, and that it can be treated as a BIT_NOP.

+
+

BIT Tokens

+

Deprecated tokens and data structure versions are highlighted in red.

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name ID Meaning Corresponding Data Structure

BIT_TOKEN_I2C_PTRS

0x32 (‘2’)

I2C Script Pointers

BIT_I2C_PTRS

BIT_TOKEN_DAC_PTRS

0x41 (‘A’)

DAC Data Pointers

BIT_DAC_PTRS

BIT_TOKEN_BIOSDATA

0x42 (‘B’)

BIOS Data

BIOSDATA (Version 1) (Version 2)

BIT_TOKEN_CLOCK_PTRS

0x43 (‘C’)

Clock Script Pointers

CLK PTRS (version 1) (version 2)

BIT_TOKEN_DFP_PTRS

0x44 (‘D’)

DFP/Panel Data Pointers

BIT_DFP_PTRS

BIT_TOKEN_NVINIT_PTRS

0x49 (‘I’)

Initialization Table Pointers

BIT_NVINIT_PTRS

BIT_TOKEN_LVDS_PTRS

0x4C (‘L’)

LVDS Table Pointers

BIT_LVDS_PTRS

BIT_TOKEN_MEMORY_PTRS

0x4D (‘M’)

Memory Control/Programming Pointers

BIT_MEMORY_PTRS (Version 1) (Version 2)

BIT_TOKEN_NOP

0x4E (‘N’)

No Operation

BIT_NOP

BIT_TOKEN_PERF_PTRS

0x50 (‘P’)

Performance Table Pointers

BIT_PERF_PTRS (Version 1) (Version 2)

BIT_TOKEN_STRING_PTRS

0x53 (‘S’)

String Pointers

BIT_STRING_PTRS (Version 1) (Version 2)

BIT_TOKEN_TMDS_PTRS

0x54 (‘T’)

TMDS Table Pointers

BIT_TMDS_PTRS

BIT_TOKEN_DISPLAY_PTRS

0x55 (‘U’)

Display Control/Programming Pointers

BIT_DISPLAY_PTRS

BIT_TOKEN_VIRTUAL_PTRS

0x56 (‘V’)

Virtual Field Pointers

BIT_VIRTUAL_PTRS

BIT_TOKEN_32BIT_PTRS

0x63 (‘c’)

32-bit Pointer Data

BIT_32BIT_PTRS

BIT_TOKEN_DP_PTRS

0x64 (‘d’)

DP Table Pointers

BIT_DP_PTRS

BIT_TOKEN_FALCON_DATA

0x70 (‘p’)

Falcon Ucode Data

PMU Table Pointers: BIT_FALCON_DATA or BIT_PMU_PTRS

BIT_TOKEN_UEFI_DATA

0x75 (‘u’)

UEFI Driver Data

BIT_UEFI_DATA

BIT_TOKEN_MXM_DATA

0x78 (‘x’)

MXM Configuration Data

BIT_MXM_DATA

BIT_TOKEN_BRIDGE_FW_DATA

0x52 (‘R’)

Bridge Firmware Data

BIT_BRIDGE_FW_DATA

+
+
+

Parsing Rules

+
+

The BIT header should be searched for as follows:

+
    +
  • +

    +ID plus Signature should be used to locate the BIT structure. Once + found, the data immediately following the BIT header is the first + token. +

    +
    • +
  • +

    +HeaderChecksum is a 0 checksum of the entire BIT header. The correct + checksum can be found by adding BIT_Header.HeaderSize consecutive + bytes together, starting with the first byte of the BIT header. A + valid BIT will provide a byte sum of 00h. +

    +
    • +
  • +

    +HeaderSize contains a value that indicates how big the actual BIT + header is. The first token can be found by adding this value to the + start address of the BIT header. +

    +
    • +
  • +

    +TokenSize indicates how big each token entry is. All tokens are the + same size. +

    +
    • +
  • +

    +TokenEntries indicates how many tokens are contained in the list and + should be processed by software. +

    +
    • +
+
+

BIT Data Structures

+
+

Deprecated data structure versions are highlighted in red.

+

BIT_I2C_PTRS

+

This data structure contains I2C scripting data.

+
+ ++++ + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

I2CScripts

16

Pointer to the I2C Scripts table

ExtHWMonInit

16

Pointer to an I2C script used to initialize an external hardware monitor

+
+

BIT_DAC_PTRS

+

This data structure contains DAC related data.

+
+ ++++ + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

DACDataPtr

16

Pointer to DAC related data

DACFlags

8

DAC Flags

+
+
DACFlags
    +
  • +

    +Bit 0:0 - DAC Sleep Mode Support (via NV_PDISP_DAC_TEST). Possible values are: +

    +
      +
    • +

      +0x0 - Not Supported +

      +
      • +
    • +

      +0x1 - Supported +

      +
      • +
    +
    • +
  • +

    +Bits 7:1 - Reserved +

    +
    • +
+

BIT_BIOSDATA (Version 1)

+

This data structure has been deprecated. It contains BIOS related data.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

BIOS Version

32

BIOS Binary Version

BIOS OEM Version

8

BIOS OEM Version Number

BIOS Checksum

8

BIOS 0 Checksum inserted during the build

INT15 POST Callbacks

16

INT15 Callbacks issued during POST

INT15 SYSTEM Callbacks

16

General INT15 Callbacks

BIOS Board ID

16

Board ID

Frame Count

16

Number of frames to display the SignOn Message

BIOSMOD Date

24

Date BIOSMod was last run (in MMDDYY format)

+
+
INT15 POST Callbacks
    +
  • +

    +Bit 0:0 - Get Panel ID +

    +
    • +
  • +

    +Bit 1:1 - Get TV Format (NTSC/PAL/NTSC-J/etc.) +

    +
    • +
  • +

    +Bit 2:2 - Get Boot Device +

    +
    • +
  • +

    +Bit 3:3 - Get Panel Expansion/Centering +

    +
    • +
  • +

    +Bit 4:4 - Perform POST Complete Callback +

    +
    • +
  • +

    +Bit 5:5 - Get RAM Configuration (OEM Specific, deprecated) +

    +
    • +
  • +

    +Bit 6:6 - Get TV Connection Type (SVIDEO/Composite/etc.) +

    +
    • +
  • +

    +Bit 7:7 - OEM External Initialization +

    +
    • +
  • +

    +Bits 15:8 - Reserved +

    +
    • +
+
INT15 SYSTEM Callbacks
    +
  • +

    +Bit 0:0 - Make DPMS Bypass Callback +

    +
    • +
  • +

    +Bit 1:1 - Get TV Format Callback (NTSC/PAL/etc.) +

    +
    • +
  • +

    +Bit 2:2 - Make Spread Spectrum Bypass Callback +

    +
    • +
  • +

    +Bit 3:3 - Make Display Switch Bypass Callback +

    +
    • +
  • +

    +Bit 4:4 - Make Device Control Setting Bypass Callback +

    +
    • +
  • +

    +Bit 5:5 - Make DDC Call Bypass Callback +

    +
    • +
  • +

    +Bit 6:6 - Make DFP Center/Expand Bypass Callback +

    +
    • +
  • +

    +Bits 15:7 - Reserved +

    +
    • +
+

BIT_BIOSDATA (Version 2)

+

This data structure contains BIOS related data.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

BIOS Version

32

BIOS Binary Version

BIOS OEM Version

8

BIOS OEM Version Number

BIOS Checksum

8

BIOS 0 Checksum inserted during the build

INT15 POST Callbacks

16

INT15 Callbacks during POST

INT15 SYSTEM Callbacks

16

General INT15 Callbacks

Frame Count

16

Number of frames to display SignOn Message

Reserved

32

Reserved

Max Heads at POST

8

Max number of heads to boot at POST

Memory Size Report (MSR)

8

Scheme for computing memory size displayed in Control Panel. Does not affect functionality in any way

hScale Factor

8

Horizontal Scale Factor

vScale Factor

8

Vertical Scale Factor

Data Range Table Pointer

16

Pointer to the table of pointers identifying where all data in the VGA BIOS image is located that the OS or EFI GPU driver need

ROMpacks Pointer

16

Pointer to any ROMpacks. A NULL (0) pointer indicates that no run-time ROMpacks are present

Applied ROMpacks Pointer

16

Pointer to a list of indexes of applied run-time ROMpacks

Applied ROMpack Max

8

Maximum number of stored indexes in the list pointed to by the Applied ROMpacks pointer

Applied ROMpack Count

8

Number of applied run-time ROMpacks
+NOTE: Count can be higher than amount stored at the AppliedROMpacksPtr array, if more than the value at AppliedROMpackMax were applied

Module Map External 0

8

Module Map External 0 byte. Indicates whether modules outside of the BIT and not at fixed addresses are included in the binary

Compression Info Pointer

32

Pointer to compression information structure (for use only by stage0 build script and decompression run-time code)

+
+
INT15 POST Callbacks
    +
  • +

    +Bit 0:0 - Get Panel ID +

    +
    • +
  • +

    +Bit 1:1 - Get TV Format (NTSC/PAL/NTSC-J/etc.) +

    +
    • +
  • +

    +Bit 2:2 - Get Boot Device +

    +
    • +
  • +

    +Bit 3:3 - Get Panel Expansion/Centering +

    +
    • +
  • +

    +Bit 4:4 - Perform POST Complete Callback +

    +
    • +
  • +

    +Bit 5:5 - Get RAM Configuration (OEM Specific – should be obsolete) +

    +
    • +
  • +

    +Bit 6:6 - Get TV Connection Type (SVIDEO/Composite/etc.) +

    +
    • +
  • +

    +Bit 7:7 - OEM External Initialization +

    +
    • +
  • +

    +Bits 15:8 - Reserved +

    +
    • +
+
INT15 SYSTEM Callbacks
    +
  • +

    +Bit 0:0 - Make DPMS Bypass Callback +

    +
    • +
  • +

    +Bit 1:1 - Get TV Format Callback (NTSC/PAL/etc.) +

    +
    • +
  • +

    +Bit 2:2 - Make Spread Spectrum Bypass Callback +

    +
    • +
  • +

    +Bit 3:3 - Make Display Switch Bypass Callback +

    +
    • +
  • +

    +Bit 4:4 - Make Device Control Setting Bypass Callback +

    +
    • +
  • +

    +Bit 5:5 - Make DDC Call Bypass Callback +

    +
    • +
  • +

    +Bit 6:6 - Make DFP Center/Expand Bypass Callback +

    +
    • +
  • +

    +Bits 15:7 - Reserved +

    +
    • +
+
Module Map External 0
    +
  • +

    +Bit 0:0 - Underflow and Error Reporting. This mode enables HW to red-fill the screen on display pipe underflow, and causes the VBIOS to make the overscan border red on poll timeouts, as well as FB pattern test failures. +This mode should never be enabled on production VBIOSes! +

    +
    • +
  • +

    +Bit 1:1 - Coproc Build. Set when a VBIOS is intended to work as a coprocessor and does not support any displays
    +

    +
    • +
  • +

    +Bit 2:2 - Reserved +

    +
    • +
  • +

    +Bit 3:3 - Reserved +

    +
    • +
  • +

    +Bit 4:4 - Reserved +

    +
    • +
+

Data Range Table

+

The Data Table contains pointers identifying where all data in the VGA +BIOS image are located that the OS GPU drivers or EFI GPU driver needs.

+
    +
  • +

    +Only data in the x86 code type PCI firmware block are included in the + Data Range Table. +

    +
    • +
  • +

    +Any other PCI firmware blocks present are defined to be "all data" (or + in the case of an EFI PCI firmware block, all code). +

    +
    • +
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Image Start

16

Pointer to the start of the binary image (0x0000)

BIT End

16

Pointer to the end of the BIOS Information Table

Data Resident Start

16

Pointer to the start of the resident data section

Data Resident End

16

Pointer to the end of the resident data section

Data Discard Start

16

Pointer to the start of the discardable data section

Data Discard End

16

Pointer to the end of the discardable data section

End of List

32

End of the list (0x0000, 0x0000)

+
+

BIT_CLOCK_PTRS (Version 1)===

+

THIS STRUCTURE VERSION IS NOW DEPRECATED. PLEASE REFER TO VERSION 2 BELOW.

+

This data structure contains data related to clock programming.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

PLL Register Table Pointer

32

Pointer to the table of PLL registers

Clock Script

32

Pointer to a script to run after changing clocks

PLL Info Table Pointer

16

Pointer to the PLL info table

Clock Frequency Table

32

Pointer to the fixed clock frequency table

FIFO Table

16

Pointer to the DAC/CRTC FIFO settings table

Noise-Aware PLL Table

16

Pointer to the noise-aware PLL yable

+
+

BIT_CLOCK_PTRS (Version 2)===

+

This data structure contains Clock Programming related data.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PLL Info Table Pointer 32 Pointer to PLL Info Table

VBE Mode PCLK table

32

Pointer to VBE Mode PCLK Table

Clocks Table Pointer

32

Pointer to Clocks Table

Clock Programming Table Pointer

32

Pointer to Clock Programming Table

NAFLL Table Pointer

32

Pointer to NAFLL Table

ADC Table Pointer

32

Pointer to ADC Table

Frequency Controller Table Pointer

32

Pointer to Frequency Controller Table

+
+

BIT_DFP_PTRS

+

This data structure contains data related to DFP programming.

+
+ ++++ + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

FP Established

16

Pointer to a table of VESA Established Timing tables

FP Table Pointer

16

Pointer to the VBIOS-internal flat panel tables

+
+

BIT_NVINIT_PTRS

+

This data structure contains initialization table pointers.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Init Script Table Pointer

16

Pointer to the table of Devinit script pointers

Macro Index Table Pointer

16

Pointer to the macro index table

Macro Table Pointer

16

Pointer to the macro table

Condition Table Pointer

16

Pointer to a table of Devinit conditionals used with the INIT_CONDITION opcode

I/O Condition Table Pointer

16

Pointer to a table of Devinit I/O conditionals used with the INIT_IO_CONDITION opcode

I/O Flag Condition Table Pointer

16

Pointer to a table of Devinit I/O conditionals used with the INIT_IO_FLAG_CONDITION opcode

Init Function Table Pointer

16

Pointer to the init function table

VBIOS Private Boot Script Pointer

16

Pointer to the VBIOS private boot script

Data Arrays Table Pointer

16

Pointer to the data arrays table

PCIe Settings Script Pointer

16

Pointer to the PCIe settings script

Devinit Tables Pointer

16

Pointer to the contiguous segment containing tables required by Devinit opcodes

Devinit Tables Size

16

Size of the contiguous segment containing tables required by Devinit opcodes

Boot Scripts Pointer

16

Pointer to the contiguous segment containing Devinit boot scripts

Boot Scripts Size

16

Size of the contiguous segment containing Devinit boot scripts

NVLink Configuration Data Pointer

16

Pointer to NVLink Configuration Data

Boot Scripts Non-GC6 Pointer

16

Pointer to the continuous section of devinit that is not required on GC6 exit

Boot Scripts Size Non-GC6

16

Size of contiguous section containing devinit that is not required on GC6 exit

+
+

BIT_LVDS_PTRS

+

This data structure contains LVDS Initialization table pointers.

+
+ ++++ + + + + + + + + + + + + + +
Name Bit width Values and Meaning

LVDS Info Table Pointer

16

Pointer to the LVDS info table

+
+

BIT_MEMORY_PTRS (Version 1)

+

Version 1 of this data structure has been deprecated.

+

This data structure contains memory control/programming related pointers

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Memory Reset Table Pointer

16

Pointer to the memory reset script

Memory Strap Data Count

8

Memory strap data Count

Memory Strap Translation Table Pointer

16

Pointer to the memory strap translation table

Memory Data VREF On Pointer

16

Pointer to the data VREF on script

Memory Data DQS On Pointer

16

Pointer to the data DQS on script

Memory Data DLCELL On Pointer

16

Pointer to the data DLCELL on script

Memory Data DLCELL Off Pointer

16

Pointer to the data DLCELL off script

+
+

BIT_MEMORY_PTRS (Version 2)

+

This data structure contains pointers related to memory control and programming.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Memory Strap Data Count

8

Memory strap data count

Memory Strap Translation Table Pointer

16

Pointer to the memory strap translation table

Memory Information Table Pointer

16

Pointer to the memory information table

Reserved

64

Memory Partition Information Table

32

Pointer to the memory partition information table

Memory Script List Pointer

32

Pointer to Memory Script List, a list of 32-bit pointers to devinit scripts used to program FB register set.

+
+

BIT_NOP

+

This data structure is a "no operation" indicator and contains no +data. BIT_TOKEN_NOP should be skipped by processing software, and +processing should continue at the next token.

+

BIT_PERF_PTRS (Version 1)

+

Version 1 of this data structure has been deprecated.

+

This data structure contains performance table pointers, which are stored as +32-bit offsets to the data.

+
    +
  • +

    +These pointers are only used by system software, and may point + at data outside the base 64K ROM image. +

    +
    • +
  • +

    +A conversion from Real Mode segment:offset format is done using the + following algorithm: + (((16bit)SEGMENT) << 4) + ((16bit)OFFSET) +

    +
    • +
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Performance Table Pointer

32

Pointer to the performance table

Memory Tweak Table Pointer

32

Pointer to the memory tweak table

Drive/Slew Table Pointer

32

Pointer to the drive/slew table

Board Temperature Control Pointer

32

Pointer to board temperature control limits

GPIO Voltage Select Table Pointer

32

Pointer to the GPIO voltage select table

AGP Clock Frequency

8

AGP clock frequency used for PCIe bus speed (in MHz)
+TODO: is this AGP or PCIe?

NVCLK Performance Table Pointer

32

Pointer to the NVCLK performance table

+
+

BIT_PERF_PTRS (Version 2)

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Performance Table Pointer

32

Pointer to the performance table

Memory Clock Table Pointer

32

Pointer to the memory clock table

Memory Tweak Table Pointer

32

Pointer to the memory tweak table

Power Control Table Pointer

32

Pointer to the power control table

Thermal Control Table Pointer

32

Pointer to the thermal control table

Thermal Device Table Pointer

32

Pointer to the thermal device table

Thermal Coolers Table Pointer

32

Pointer to the thermal coolers table

Performance Settings Script Pointer

32

Pointer to a Devinit script containing performance-related settings
+See Note 1.

Continuous Virtual Binning Table Pointer

32

Pointer to the continuous virtual binning table

Ventura Table Pointer

32

Pointer to the Ventura table

Power Sensors Table Pointer

32

Pointer to the power sensors table

Power Policy Table Pointer

32

Pointer to the power policy table

P-State Clock Range Table Pointer

32

Pointer to the P-State clock range table

Voltage Frequency Table Pointer

32

Pointer to the voltage frequency table

Virtual P-State Table Pointer

32

Pointer to the virtual P-State table

Power Topology Table Pointer

32

Pointer to the power topology table

Power Leakage Table Pointer

32

Pointer to the power leakage table

Performance Test Specifications Table Pointer

32

Pointer to the performance test specifications table

Thermal Channel Table Pointer

32

Pointer to the thermal channel table

Thermal Adjustment Table Pointer

32

Pointer to the thermal adjustment table

Thermal Policy Table Pointer

32

Pointer to the thermal policy table

P-State Memory Clock Frequency Table Pointer

32

Pointer to the P-State memory clock frequency table

Fan Cooler Table Pointer

32

Pointer to the fan cooler table

Fan Policy Table Pointer

32

Pointer to the fan policy table

DI/DT Table Pointer

32

Pointer to DI/DT Table

Fan Test Table Pointer

32

Pointer to Fan Test Table

Voltage Rail Table Pointer

32

Pointer to Voltage Rail Table

Voltage Device Table Pointer

32

Pointer to Voltage Device Table

Voltage Policy Table Pointer

32

Pointer to Voltage Policy Table

LowPower Table Pointer

32

Pointer to LowPower Table

LowPower PCIe Table Pointer

32

Pointer to LowPower PCIe Table

LowPower PCIe-Platform Table Pointer

32

Pointer to LowPower PCIe-Platform Table

LowPower GR Table Pointer

32

Pointer to LowPower GR Table

LowPower MS Table Pointer

32

Pointer to LowPower MS Table

LowPower DI Table Pointer

32

Pointer to LowPower DI Table

LowPower GC6 Table Pointer

32

Pointer to LowPower GC6 Table

LowPower PSI Table Pointer

32

Pointer to LowPower PSI Table

Thermal Monitor Table Pointer

32

Pointer to Thermal Monitor Table

Overclocking Table Pointer

32

Pointer to Overclocking Table

LowPower NVLINK Table Pointer

32

Pointer to LPWR NVLINK Table

+
+

Note 1: Notes on the Performance Settings Script Pointer:

+
    +
  • +

    +Intended to be parsed by system software to directly obtain register settings for a particular P-state, typically P0. +

    +
    • +
  • +

    +May be called as a subscript from the primary device initialization script + so that it can be used both for initialization and to provide data for + P-state changes. +

    +
    • +
  • +

    +Must not contain any conditions or opcodes that require reading hardware, + with the exception of INIT_XMEMSEL* opcodes that only need to read the + memory strap, which may be cached by system software. +

    +
    • +
  • +

    +System software is only required to parse up to the first occurrence of the desired register. +

    +
    • +
  • +

    +Parsing should terminate at the INIT_DONE opcode.
    +

    +
    • +
+

BIT_STRING_PTRS (Version 1)

+

This data structure has been deprecated.

+

This data structure contains pointers to strings in the VBIOS image

+
    +
  • +

    +All of the strings in this structure are ‘0’ terminated. +

    +
    • +
  • +

    +The “Size” bytes indicate the maximum length available for storing the string, non-inclusive of the terminating 0. +

    +
    • +
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Sign On Message Poitner

16

Pointer to Sign On Message

Sign On Message Maximum Length

8

Maximum length of Sign On Message

OEM String

16

OEM String to identify graphics controller chip or product family. This is the last radix in the combined version string, e.g. 25 in 70.18.01.00.25

OEM String Size

8

Maximum length of OEM string

OEM Vendor Name

16

Name of the vendor that produced the display controller board product

OEM Vendor Name Size

8

Maximum length of OEM Vendor Name

OEM Product Name

16

Product name of the controller board

OEM Product Name Size

8

Maximum length of OEM Product Name

OEM Product Revision

16

Revision of manufacturing level of the display controller board

OEM Product Revision Size

8

Maximum length of OEM Product Revision

+
+

BIT_STRING_PTRS (Version 2)

+

This data structure contains pointers to strings in the VBIOS image

+
    +
  • +

    +All of the strings in this structure are ‘0’ terminated. +

    +
    • +
  • +

    +The “Size” bytes indicate the maximum length available for storing the string, non-inclusive of the terminating 0. +

    +
    • +
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Sign On Message Poitner

16

Pointer to Sign On Message

Sign On Message Maximum Length

8

Maximum length of Sign On Message

Version String

16

Pointer to the "Version ww.xx.yy.zz" string

Version String Size

8

Maximum length of the version string

Copyright String

16

Pointer to the copyright string

Copyright String Size

8

Maximum length of the copyright string

OEM String

16

OEM String to identify graphics controller chip or product family. This is the last radix in the combined version string, e.g. 25 in 70.18.01.00.25

OEM String Size

8

Maximum length of OEM string

OEM Vendor Name

16

Name of the vendor that produced the display controller board product

OEM Vendor Name Size

8

Maximum length of OEM Vendor Name

OEM Product Name

16

Product name of the controller board

OEM Product Name Size

8

Maximum length of OEM Product Name

OEM Product Revision

16

Revision of manufacturing level of the display controller board

OEM Product Revision Size

8

Maximum length of OEM Product Revision

+
+

BIT_TMDS_PTRS

+

This data structure contains TMDS Initialization table pointers.

+
+ ++++ + + + + + + + + + + + + + +
Name Bit width Values and Meaning

TMDS Info Table Pointer

16

Pointer to TMDS Info Table

+
+

BIT_DISPLAY_PTRS

+

This data structure contains Display Control/Programming related pointers.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Display Scripting Table Pointer

16

Pointer to Display Scripting Table

Display Control Flags

8

Display Control Flags byte +: [0:0] = Enable white overscan border for diagnostic purposes +: [1:1] = NO_DISPLAY_SUBSYSTEM: Display subsystem isn’t included in the GPU (used for displayless coproc) +: [2:2] = DISPLAY_FPGA: Display subsystem is on an FPGA (used for pre-SI testing). +: [3:3] = VBIOS avoids touching mempool while drivers running +: [4:4] = Offset PCLK between 2 heads +: [5:5] = Boot with DP Hotplug disabled +: [6:6] = Allow detection of DP sinks by doing a DPCD register read +: [7:7] = Reserved

SLI Table Header Pointer

16

Pointer to the SLI Table Header

+
+

BIT_VIRTUAL_PTRS

+

This data structure contains Virtual Field pointers.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Virtual Strap Field Table Pointer

16

Pointer to Virtual Strap Field Table

Virtual Strap Field Register

16

Virtual STrap Field Register

Translation Table Pointer

16

Pointer to translation table so virtual straps can be sparse

+
+

BIT_32BIT_PTRS

+

This data structure contains BIOS related data that is located outside +the 64K ROM image.

+
    +
  • +

    +It is used by the VBIOS to access tables during POST that need to be copied into the runtime image. +

    +
    • +
  • +

    +No data structure is currently defined. +

    +
    • +
+

BIT_DP_PTRS

+

This data structure contains the DP Info Table.

+
+ ++++ + + + + + + + + + + + + + +
Name Bit width Values and Meaning

DP Info Table Pointer

16

Pointer to DP Info Table

+
+

BIT_PMU_PTRS (Version 1)

+

This data structure has been deprecated. It is superseded by BIT_FALCON_DATA (Version 2).

+

This data structure contains PMU-related pointers

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

PMU Function Table Pointer

16

Pointer to PMU Function Table (Deprecated)

PMU Function Table Pointer (32-bit)

32

Pointer to PMU Function Table (32-bit)

PMU Init-From-Rom Code Image Pointer

32

core80-: Pointer to PMU IFR code image in Kepler format +core82+: Pointer to IFR IMEM image in raw format

PMU Init-From-Rom Code Image Size

32

core80-: Size of PMU IFR code image in Kepler format +core82+: Size of IFR IMEM image in raw format

PMU Init-From-Rom Code Image ID

8

ID of PMU IFR code image

PMU Init-From-Rom Code Image Info Ptr

32

Pointer to info struct for IFR code image

PMU Init-From-Rom Data Image Ptr

32

core82+: Pointer to IFR DMEM image in raw format

PMU Init-From-Rom Data Image Size

32

core82+: Size of IFR DMEM image in raw format

+
+

BIT_FALCON_DATA (Version 2)

+

This data structure contains Falcon-related data and pointers. It +supersedes BIT_PMU_PTRS (Version 1). +The name was changed for version 2 to better reflect the scope of +associated data.

+
+ ++++ + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Falcon Ucode Table Pointer

32

Pointer to Falcon Ucode Table

+
+

BIT_UEFI_DATA

+

This data structure contains the UEFI Driver Data structure

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Minimum UEFI Driver Version

32

Minimum UEFI driver version that is required when merging with the legacy VBIOS image

UEFI Compatibility Level

8

Specifies the legacy VBIOS UEFI compatibility level which can be used to prevent the legacy VBIOS from being merged with an incompatible UEFI driver

UEFI Flags

64

UEFI Flags +: [0:0] Display switch support +:: 0 = Enabled +:: 1 = Disabled +: [1:1] LCD diagnostics support +:: 0 = Disabled +:: 1 = Enabled +: [2:2] Glitchless support +:: 0 = Enabled +:: 1 = Disabled +: [63:3] Reserved (defaults to 0)

+
+

BIT_MXM_DATA

+

This data structure contains the MXM Configuration Data structure

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Module Spec Version

8

The BCD version of the Thermal Electromechanical Specification the module was designed for

Module Flags 0

8

Module Flags 0 byte +: [3:0] - Form Factor +:: 0x0 = Not MXM +:: 0x1 = Type-I +:: 0x2 = Type-II +:: 0x3 = Type-III +:: 0x4 = Type-IV +:: 0x5-0xE = Reserved +:: 0xF = Undefined +: [7:4] - Reserved

Config Flags 0

8

Configuration Flags 0 byte +: [0:0] = MXM Structure Required +: [1:1] = MXM Structure validation failed +: [3:2] = DCB modification status +:: 0 = VBIOS modification complete +:: 1-2 = Reserved +:: 3 = MXM Default DCB +: [7:4] – Chip package type of GPU on the MXM module +:: 0x0 = Package older than G3 type +:: 0x1 = G3 package +:: 0x2 = GB1-128/256 package +:: 0x3 = GB1-64 package +:: 0x4 = GB4-256 package +:: 0x5-0xF = Reserved

DP Drive Strength Scale

8

Used to modify the DP Drive Strength for DP in MXM30

MXM Digital Connector Table Pointer

16

Pointer to table for mapping MXM Digital Connection number into SOR/Sublinks config

MXM DDC/Aux to CCB Table Pointer

16

Pointer to table for mapping MXM DDC/Aux number CCB port number

+
+

BIT_BRIDGE_FW_DATA

+

This data structure contains the Bridge Firmware Data structure

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Firmare Version

32

Firmware Binary Version

Firmware OEM Version

8

Firmware OEM Verison Number

Firmware Image Length

16

Firmware Image Length in increments of 512 bytes

BIOSMOD Date

64

Date of Last BIOSMod Modification

Firmware Flags

32

Firmware Flags +: [0:0] Build +:: 0 = Release +:: 1 = Engineering +: [1:1] I2C +:: 0 = Master (possible I2C slave connected) +:: 1 = Not Master

Engineering Product Name

16

Pointer to the Engineering Product Name

Engineering Product Name Size

8

Maximum length of the Engineering Product Name string

+
+
+ + + diff --git a/Compute-Class-Methods/cl50c0.h b/Compute-Class-Methods/cl50c0.h new file mode 100644 index 0000000..e22fed8 --- /dev/null +++ b/Compute-Class-Methods/cl50c0.h @@ -0,0 +1,741 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_nv50_compute_h_ +#define _cl_nv50_compute_h_ + +/* This file is generated - do not edit. */ + +#include "nvtypes.h" + +#define NV50_COMPUTE 0x50C0 + +typedef volatile struct _cl50c0_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 Notify; + NvU32 Reserved_0x108[0x2]; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0xB]; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0xF]; + NvU32 SetContextDmaNotify; + NvU32 Reserved_0x184[0x7]; + NvU32 SetCtxDmaGlobalMem; + NvU32 SetCtxDmaSemaphore; + NvU32 Reserved_0x1A8[0x4]; + NvU32 SetCtxDmaShaderThreadMemory; + NvU32 SetCtxDmaShaderThreadStack; + NvU32 SetCtxDmaShaderProgram; + NvU32 SetCtxDmaTextureSampler; + NvU32 SetCtxDmaTextureHeaders; + NvU32 SetCtxDmaTexture; + NvU32 Reserved_0x1D0[0xC]; + struct { + NvU32 Control; + NvU32 QuerySessionKey; + NvU32 GetSessionKey; + NvU32 SetEncryption; + } Decryption[0x1]; + NvU32 SetCtaProgramA; + NvU32 SetCtaProgramB; + NvU32 SetShaderThreadStackA; + NvU32 SetShaderThreadStackB; + NvU32 SetShaderThreadStackC; + NvU32 SetApiCallLimit; + NvU32 SetShaderL1CacheControl; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 LoadConstantSelector; + NvU32 LoadConstant[0x10]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 Reserved_0x284[0x1]; + NvU32 SetSmTimeoutInterval; + NvU32 TestForCompute; + NvU32 SetShaderScheduling; + NvU32 SetShaderThreadMemoryA; + NvU32 SetShaderThreadMemoryB; + NvU32 SetShaderThreadMemoryC; + NvU32 SetWorkDistribution; + NvU32 LoadConstantBufferTableA; + NvU32 LoadConstantBufferTableB; + NvU32 LoadConstantBufferTableC; + NvU32 SetShaderErrorTrapControl; + NvU32 SetCtaResourceAllocation; + NvU32 SetCtaThreadControl; + NvU32 SetPhaseIdControl; + NvU32 SetCtaRegisterCount; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 SetShaderPerformanceCounterValue[0x4]; + NvU32 SetShaderPerformanceCounterControl[0x4]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 ResetCtaTrackingRam; + NvU32 Initialize; + NvU32 SetShaderThreadMemoryThrottle; + NvU32 SetShaderThreadMemoryThrottleControl; + NvU32 SetShaderThreadStackThrottle; + NvU32 SetShaderThreadStackThrottleControl; + NvU32 PrefetchShaderInstructions; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 SetLaunchEnableA; + NvU32 SetLaunchEnableB; + NvU32 SetLaunchEnableC; + NvU32 SetCubemapAddressModeOverride; + NvU32 PipeNop; + NvU32 Reserved_0x334[0x3]; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x350[0x2]; + NvU32 SetGlobalColorKey; + NvU32 ResetRefCount; + NvU32 WaitRefCount; + NvU32 SetRefCountValue; + NvU32 Launch; + NvU32 SetLaunchId; + NvU32 SetLaunchControl; + NvU32 SetParameterSize; + NvU32 SetSamplerBinding; + NvU32 SetShaderControl; + NvU32 InvalidateShaderCache; + NvU32 SetRasterControl; + NvU32 SetCtaFlags; + NvU32 Reserved_0x38C[0x6]; + NvU32 SetCtaRasterSize; + NvU32 SetCtaGrfSize; + NvU32 SetCtaThreadDimensionA; + NvU32 SetCtaThreadDimensionB; + NvU32 SetCtaProgramStart; + NvU32 SetCtaRegisterAllocation; + NvU32 SetCtaTexture; + NvU32 BindCtaTextureSampler; + NvU32 BindCtaTextureHeader; + NvU32 BindConstantBuffer; + NvU32 PrefetchTextureSampler; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x3D4[0x6]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x3F0[0x4]; + struct { + NvU32 A; + NvU32 B; + NvU32 Size; + NvU32 Limit; + NvU32 Format; + NvU32 Reserved_0x14[0x3]; + } SetGlobalMem[0x10]; + NvU32 Parameter[0x40]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; +} nv50_compute_t; + + +#define NV50C0_SET_OBJECT 0x0000 +#define NV50C0_SET_OBJECT_POINTER 15:0 + +#define NV50C0_NO_OPERATION 0x0100 +#define NV50C0_NO_OPERATION_V 31:0 + +#define NV50C0_NOTIFY 0x0104 +#define NV50C0_NOTIFY_TYPE 31:0 +#define NV50C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV50C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV50C0_WAIT_FOR_IDLE 0x0110 +#define NV50C0_WAIT_FOR_IDLE_V 31:0 + +#define NV50C0_PM_TRIGGER 0x0140 +#define NV50C0_PM_TRIGGER_V 31:0 + +#define NV50C0_SET_CONTEXT_DMA_NOTIFY 0x0180 +#define NV50C0_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_GLOBAL_MEM 0x01a0 +#define NV50C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_SEMAPHORE 0x01a4 +#define NV50C0_SET_CTX_DMA_SEMAPHORE_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY 0x01b8 +#define NV50C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK 0x01bc +#define NV50C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM 0x01c0 +#define NV50C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER 0x01c4 +#define NV50C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS 0x01c8 +#define NV50C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE 31:0 + +#define NV50C0_SET_CTX_DMA_TEXTURE 0x01cc +#define NV50C0_SET_CTX_DMA_TEXTURE_HANDLE 31:0 + +#define NV50C0_DECRYPTION_CONTROL(j) (0x0200+(j)*16) +#define NV50C0_DECRYPTION_CONTROL_ALGORITHM 15:0 +#define NV50C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE 0x00000000 +#define NV50C0_DECRYPTION_CONTROL_KEY_COUNT 23:16 + +#define NV50C0_DECRYPTION_QUERY_SESSION_KEY(j) (0x0204+(j)*16) +#define NV50C0_DECRYPTION_QUERY_SESSION_KEY_V 31:0 + +#define NV50C0_DECRYPTION_GET_SESSION_KEY(j) (0x0208+(j)*16) +#define NV50C0_DECRYPTION_GET_SESSION_KEY_V 31:0 + +#define NV50C0_DECRYPTION_SET_ENCRYPTION(j) (0x020c+(j)*16) +#define NV50C0_DECRYPTION_SET_ENCRYPTION_V 31:0 + +#define NV50C0_SET_CTA_PROGRAM_A 0x0210 +#define NV50C0_SET_CTA_PROGRAM_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_CTA_PROGRAM_B 0x0214 +#define NV50C0_SET_CTA_PROGRAM_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_SHADER_THREAD_STACK_A 0x0218 +#define NV50C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_SHADER_THREAD_STACK_B 0x021c +#define NV50C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_SHADER_THREAD_STACK_C 0x0220 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE 3:0 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__0 0x00000000 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1 0x00000001 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2 0x00000002 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4 0x00000003 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__8 0x00000004 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__16 0x00000005 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__32 0x00000006 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__64 0x00000007 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__128 0x00000008 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__256 0x00000009 +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__512 0x0000000A +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__1024 0x0000000B +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__2048 0x0000000C +#define NV50C0_SET_SHADER_THREAD_STACK_C_SIZE__4096 0x0000000D + +#define NV50C0_SET_API_CALL_LIMIT 0x0224 +#define NV50C0_SET_API_CALL_LIMIT_CTA 3:0 +#define NV50C0_SET_API_CALL_LIMIT_CTA__0 0x00000000 +#define NV50C0_SET_API_CALL_LIMIT_CTA__1 0x00000001 +#define NV50C0_SET_API_CALL_LIMIT_CTA__2 0x00000002 +#define NV50C0_SET_API_CALL_LIMIT_CTA__4 0x00000003 +#define NV50C0_SET_API_CALL_LIMIT_CTA__8 0x00000004 +#define NV50C0_SET_API_CALL_LIMIT_CTA__16 0x00000005 +#define NV50C0_SET_API_CALL_LIMIT_CTA__32 0x00000006 +#define NV50C0_SET_API_CALL_LIMIT_CTA__64 0x00000007 +#define NV50C0_SET_API_CALL_LIMIT_CTA__128 0x00000008 +#define NV50C0_SET_API_CALL_LIMIT_CTA_NO_CHECK 0x0000000F + +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL 0x0228 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY 7:4 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY 11:8 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY 15:12 +#define NV50C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY 19:16 + +#define NV50C0_SET_TEX_SAMPLER_POOL_A 0x022c +#define NV50C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_TEX_SAMPLER_POOL_B 0x0230 +#define NV50C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_TEX_SAMPLER_POOL_C 0x0234 +#define NV50C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV50C0_LOAD_CONSTANT_SELECTOR 0x0238 +#define NV50C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX 7:0 +#define NV50C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX 23:8 + +#define NV50C0_LOAD_CONSTANT(i) (0x023c+(i)*4) +#define NV50C0_LOAD_CONSTANT_V 31:0 + +#define NV50C0_INVALIDATE_SAMPLER_CACHE 0x027c +#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV50C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV50C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x0280 +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV50C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV50C0_SET_SM_TIMEOUT_INTERVAL 0x0288 +#define NV50C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV50C0_TEST_FOR_COMPUTE 0x028c +#define NV50C0_TEST_FOR_COMPUTE_V 31:0 + +#define NV50C0_SET_SHADER_SCHEDULING 0x0290 +#define NV50C0_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV50C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV50C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_A 0x0294 +#define NV50C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_B 0x0298 +#define NV50C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_C 0x029c +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE 3:0 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0 0x00000000 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1 0x00000001 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2 0x00000002 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4 0x00000003 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8 0x00000004 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16 0x00000005 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32 0x00000006 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64 0x00000007 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128 0x00000008 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256 0x00000009 +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512 0x0000000A +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024 0x0000000B +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048 0x0000000C +#define NV50C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096 0x0000000D + +#define NV50C0_SET_WORK_DISTRIBUTION 0x02a0 +#define NV50C0_SET_WORK_DISTRIBUTION_V 3:0 +#define NV50C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY 0x00000000 +#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC 0x00000001 +#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC 0x00000002 +#define NV50C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED 0x00000003 +#define NV50C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED 0x00000004 +#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC 0x00000005 +#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC 0x00000006 +#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED 0x00000007 +#define NV50C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED 0x00000008 + +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A 0x02a4 +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER 7:0 + +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B 0x02a8 +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER 31:0 + +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C 0x02ac +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE 15:0 +#define NV50C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY 23:16 + +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL 0x02b0 +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK 0:0 +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE 0x00000000 +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE 0x00000001 +#define NV50C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK 31:1 + +#define NV50C0_SET_CTA_RESOURCE_ALLOCATION 0x02b4 +#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT 15:0 +#define NV50C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT 23:16 + +#define NV50C0_SET_CTA_THREAD_CONTROL 0x02b8 +#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH 0:0 +#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE 0x00000000 +#define NV50C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE 0x00000001 + +#define NV50C0_SET_PHASE_ID_CONTROL 0x02bc +#define NV50C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE 2:0 +#define NV50C0_SET_PHASE_ID_CONTROL_LOCK_PHASE 6:4 + +#define NV50C0_SET_CTA_REGISTER_COUNT 0x02c0 +#define NV50C0_SET_CTA_REGISTER_COUNT_V 7:0 + +#define NV50C0_SET_TEX_HEADER_POOL_A 0x02c4 +#define NV50C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_TEX_HEADER_POOL_B 0x02c8 +#define NV50C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_TEX_HEADER_POOL_C 0x02cc +#define NV50C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x02d0+(i)*4) +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i) (0x02e0+(i)*4) +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE 0:0 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK 6:4 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE 0x00000000 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS 0x00000001 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM 0x00000002 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC 0x00000003 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP 0x00000004 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU 0x00000005 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC 23:8 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT 31:24 + +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x02f0 +#define NV50C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 3:0 + +#define NV50C0_RESET_CTA_TRACKING_RAM 0x02f4 +#define NV50C0_RESET_CTA_TRACKING_RAM_V 31:0 + +#define NV50C0_INITIALIZE 0x02f8 +#define NV50C0_INITIALIZE_INIT_CTA_SHAPE 0:0 +#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_FALSE 0x00000000 +#define NV50C0_INITIALIZE_INIT_CTA_SHAPE_TRUE 0x00000001 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE 0x02fc +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM 2:0 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 + +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL 0x0300 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V 2:0 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 +#define NV50C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 + +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE 0x0304 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM 2:0 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 + +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL 0x0308 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V 2:0 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 +#define NV50C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 + +#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS 0x030c +#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA 0:0 +#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE 0x00000000 +#define NV50C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE 0x00000001 + +#define NV50C0_SET_REPORT_SEMAPHORE_A 0x0310 +#define NV50C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_REPORT_SEMAPHORE_B 0x0314 +#define NV50C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_REPORT_SEMAPHORE_C 0x0318 +#define NV50C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV50C0_SET_REPORT_SEMAPHORE_D 0x031c +#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV50C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE 2:2 +#define NV50C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE 3:3 +#define NV50C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 7:4 +#define NV50C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON 8:8 +#define NV50C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 9:9 +#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT 14:10 +#define NV50C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 15:15 +#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV50C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 + +#define NV50C0_SET_LAUNCH_ENABLE_A 0x0320 +#define NV50C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_LAUNCH_ENABLE_B 0x0324 +#define NV50C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_LAUNCH_ENABLE_C 0x0328 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE 2:0 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_FALSE 0x00000000 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_TRUE 0x00000001 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV50C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE 0x032c +#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE 31:0 +#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NV50C0_PIPE_NOP 0x0330 +#define NV50C0_PIPE_NOP_V 31:0 + +#define NV50C0_SET_SPARE00 0x0340 +#define NV50C0_SET_SPARE00_V 31:0 + +#define NV50C0_SET_SPARE01 0x0344 +#define NV50C0_SET_SPARE01_V 31:0 + +#define NV50C0_SET_SPARE02 0x0348 +#define NV50C0_SET_SPARE02_V 31:0 + +#define NV50C0_SET_SPARE03 0x034c +#define NV50C0_SET_SPARE03_V 31:0 + +#define NV50C0_SET_GLOBAL_COLOR_KEY 0x0358 +#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE 31:0 +#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV50C0_RESET_REF_COUNT 0x035c +#define NV50C0_RESET_REF_COUNT_REF_CNT 3:0 + +#define NV50C0_WAIT_REF_COUNT 0x0360 +#define NV50C0_WAIT_REF_COUNT_COMPARE 7:4 +#define NV50C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT 0x00000000 +#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL 0x00000001 +#define NV50C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND 0x00000002 +#define NV50C0_WAIT_REF_COUNT_REF_CNT 11:8 + +#define NV50C0_SET_REF_COUNT_VALUE 0x0364 +#define NV50C0_SET_REF_COUNT_VALUE_V 31:0 + +#define NV50C0_LAUNCH 0x0368 +#define NV50C0_LAUNCH_V 31:0 + +#define NV50C0_SET_LAUNCH_ID 0x036c +#define NV50C0_SET_LAUNCH_ID_REF_CNT 3:0 + +#define NV50C0_SET_LAUNCH_CONTROL 0x0370 +#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH 7:0 +#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH 0x00000000 +#define NV50C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH 0x00000001 + +#define NV50C0_SET_PARAMETER_SIZE 0x0374 +#define NV50C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX 7:0 +#define NV50C0_SET_PARAMETER_SIZE_COUNT 15:8 + +#define NV50C0_SET_SAMPLER_BINDING 0x0378 +#define NV50C0_SET_SAMPLER_BINDING_V 0:0 +#define NV50C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV50C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV50C0_SET_SHADER_CONTROL 0x037c +#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV50C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV50C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV50C0_INVALIDATE_SHADER_CACHE 0x0380 +#define NV50C0_INVALIDATE_SHADER_CACHE_V 1:0 +#define NV50C0_INVALIDATE_SHADER_CACHE_V_ALL 0x00000000 +#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1 0x00000001 +#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_DATA 0x00000002 +#define NV50C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION 0x00000003 + +#define NV50C0_SET_RASTER_CONTROL 0x0384 +#define NV50C0_SET_RASTER_CONTROL_PROGRAM 7:0 +#define NV50C0_SET_RASTER_CONTROL_PROGRAM_DISABLE 0x00000000 +#define NV50C0_SET_RASTER_CONTROL_FIXED 15:8 +#define NV50C0_SET_RASTER_CONTROL_FIXED_DISABLE 0x00000000 +#define NV50C0_SET_RASTER_CONTROL_FIXED_SIMPLE 0x00000001 +#define NV50C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED 0x00000002 +#define NV50C0_SET_RASTER_CONTROL_DECRYPTION 23:16 +#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE 0x00000000 +#define NV50C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE 0x00000001 + +#define NV50C0_SET_CTA_FLAGS 0x0388 +#define NV50C0_SET_CTA_FLAGS_V 15:0 + +#define NV50C0_SET_CTA_RASTER_SIZE 0x03a4 +#define NV50C0_SET_CTA_RASTER_SIZE_WIDTH 15:0 +#define NV50C0_SET_CTA_RASTER_SIZE_HEIGHT 31:16 + +#define NV50C0_SET_CTA_GRF_SIZE 0x03a8 +#define NV50C0_SET_CTA_GRF_SIZE_V 31:0 + +#define NV50C0_SET_CTA_THREAD_DIMENSION_A 0x03ac +#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 +#define NV50C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 + +#define NV50C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 +#define NV50C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 + +#define NV50C0_SET_CTA_PROGRAM_START 0x03b4 +#define NV50C0_SET_CTA_PROGRAM_START_OFFSET 23:0 + +#define NV50C0_SET_CTA_REGISTER_ALLOCATION 0x03b8 +#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V 31:0 +#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THICK 0x00000001 +#define NV50C0_SET_CTA_REGISTER_ALLOCATION_V_THIN 0x00000002 + +#define NV50C0_SET_CTA_TEXTURE 0x03bc +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV50C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER 0x03c0 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID 0:0 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV50C0_BIND_CTA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV50C0_BIND_CTA_TEXTURE_HEADER 0x03c4 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID 0:0 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV50C0_BIND_CTA_TEXTURE_HEADER_INDEX 30:9 + +#define NV50C0_BIND_CONSTANT_BUFFER 0x03c8 +#define NV50C0_BIND_CONSTANT_BUFFER_VALID 3:0 +#define NV50C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV50C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE 7:4 +#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA 0x00000000 +#define NV50C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 11:8 +#define NV50C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY 19:12 + +#define NV50C0_PREFETCH_TEXTURE_SAMPLER 0x03cc +#define NV50C0_PREFETCH_TEXTURE_SAMPLER_INDEX 21:0 + +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE 0x03d0 +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 5:4 +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY 0x00000001 +#define NV50C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2 0x00000002 + +#define NV50C0_SET_SHADER_EXCEPTIONS 0x03ec +#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV50C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV50C0_SET_GLOBAL_MEM_A(j) (0x0400+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_A_OFFSET_UPPER 7:0 + +#define NV50C0_SET_GLOBAL_MEM_B(j) (0x0404+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_B_OFFSET_LOWER 31:0 + +#define NV50C0_SET_GLOBAL_MEM_SIZE(j) (0x0408+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH 31:0 + +#define NV50C0_SET_GLOBAL_MEM_LIMIT(j) (0x040c+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_LIMIT_MAX 31:0 + +#define NV50C0_SET_GLOBAL_MEM_FORMAT(j) (0x0410+(j)*32) +#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT 0:0 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH 0x00000001 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH 7:4 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB 0x00000000 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT 11:8 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB 0x00000000 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS 0x00000001 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS 0x00000002 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV50C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV50C0_PARAMETER(i) (0x0600+(i)*4) +#define NV50C0_PARAMETER_V 31:0 + +#define NV50C0_SET_SPARE_NOOP00 0x0700 +#define NV50C0_SET_SPARE_NOOP00_V 31:0 + +#define NV50C0_SET_SPARE_NOOP01 0x0704 +#define NV50C0_SET_SPARE_NOOP01_V 31:0 + +#define NV50C0_SET_SPARE_NOOP02 0x0708 +#define NV50C0_SET_SPARE_NOOP02_V 31:0 + +#define NV50C0_SET_SPARE_NOOP03 0x070c +#define NV50C0_SET_SPARE_NOOP03_V 31:0 + +#define NV50C0_SET_SPARE_NOOP04 0x0710 +#define NV50C0_SET_SPARE_NOOP04_V 31:0 + +#define NV50C0_SET_SPARE_NOOP05 0x0714 +#define NV50C0_SET_SPARE_NOOP05_V 31:0 + +#define NV50C0_SET_SPARE_NOOP06 0x0718 +#define NV50C0_SET_SPARE_NOOP06_V 31:0 + +#define NV50C0_SET_SPARE_NOOP07 0x071c +#define NV50C0_SET_SPARE_NOOP07_V 31:0 + +#define NV50C0_SET_SPARE_NOOP08 0x0720 +#define NV50C0_SET_SPARE_NOOP08_V 31:0 + +#define NV50C0_SET_SPARE_NOOP09 0x0724 +#define NV50C0_SET_SPARE_NOOP09_V 31:0 + +#define NV50C0_SET_SPARE_NOOP10 0x0728 +#define NV50C0_SET_SPARE_NOOP10_V 31:0 + +#define NV50C0_SET_SPARE_NOOP11 0x072c +#define NV50C0_SET_SPARE_NOOP11_V 31:0 + +#define NV50C0_SET_SPARE_NOOP12 0x0730 +#define NV50C0_SET_SPARE_NOOP12_V 31:0 + +#define NV50C0_SET_SPARE_NOOP13 0x0734 +#define NV50C0_SET_SPARE_NOOP13_V 31:0 + +#define NV50C0_SET_SPARE_NOOP14 0x0738 +#define NV50C0_SET_SPARE_NOOP14_V 31:0 + +#define NV50C0_SET_SPARE_NOOP15 0x073c +#define NV50C0_SET_SPARE_NOOP15_V 31:0 + +#endif /* _cl_nv50_compute_h_ */ diff --git a/Compute-Class-Methods/cl85c0.h b/Compute-Class-Methods/cl85c0.h new file mode 100644 index 0000000..4234fd0 --- /dev/null +++ b/Compute-Class-Methods/cl85c0.h @@ -0,0 +1,747 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_gt214_compute_h_ +#define _cl_gt214_compute_h_ + +/* This file is generated - do not edit. */ + +#include "nvtypes.h" + +#define GT214_COMPUTE 0x85C0 + +typedef volatile struct _cl85c0_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 Notify; + NvU32 Reserved_0x108[0x2]; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0xB]; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0xF]; + NvU32 SetContextDmaNotify; + NvU32 Reserved_0x184[0x7]; + NvU32 SetCtxDmaGlobalMem; + NvU32 SetCtxDmaSemaphore; + NvU32 Reserved_0x1A8[0x4]; + NvU32 SetCtxDmaShaderThreadMemory; + NvU32 SetCtxDmaShaderThreadStack; + NvU32 SetCtxDmaShaderProgram; + NvU32 SetCtxDmaTextureSampler; + NvU32 SetCtxDmaTextureHeaders; + NvU32 SetCtxDmaTexture; + NvU32 Reserved_0x1D0[0xC]; + struct { + NvU32 Control; + NvU32 QuerySessionKey; + NvU32 GetSessionKey; + NvU32 SetEncryption; + } Decryption[0x1]; + NvU32 SetCtaProgramA; + NvU32 SetCtaProgramB; + NvU32 SetShaderThreadStackA; + NvU32 SetShaderThreadStackB; + NvU32 SetShaderThreadStackC; + NvU32 SetApiCallLimit; + NvU32 SetShaderL1CacheControl; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 LoadConstantSelector; + NvU32 LoadConstant[0x10]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 Reserved_0x284[0x1]; + NvU32 SetSmTimeoutInterval; + NvU32 TestForCompute; + NvU32 SetShaderScheduling; + NvU32 SetShaderThreadMemoryA; + NvU32 SetShaderThreadMemoryB; + NvU32 SetShaderThreadMemoryC; + NvU32 SetWorkDistribution; + NvU32 LoadConstantBufferTableA; + NvU32 LoadConstantBufferTableB; + NvU32 LoadConstantBufferTableC; + NvU32 SetShaderErrorTrapControl; + NvU32 SetCtaResourceAllocation; + NvU32 SetCtaThreadControl; + NvU32 SetPhaseIdControl; + NvU32 SetCtaRegisterCount; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 SetShaderPerformanceCounterValue[0x4]; + NvU32 SetShaderPerformanceCounterControl[0x4]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 ResetCtaTrackingRam; + NvU32 Initialize; + NvU32 SetShaderThreadMemoryThrottle; + NvU32 SetShaderThreadMemoryThrottleControl; + NvU32 SetShaderThreadStackThrottle; + NvU32 SetShaderThreadStackThrottleControl; + NvU32 PrefetchShaderInstructions; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 SetLaunchEnableA; + NvU32 SetLaunchEnableB; + NvU32 SetLaunchEnableC; + NvU32 SetCubemapAddressModeOverride; + NvU32 PipeNop; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop10; + NvU32 SetGlobalColorKey; + NvU32 ResetRefCount; + NvU32 WaitRefCount; + NvU32 SetRefCountValue; + NvU32 Launch; + NvU32 SetLaunchId; + NvU32 SetLaunchControl; + NvU32 SetParameterSize; + NvU32 SetSamplerBinding; + NvU32 SetShaderControl; + NvU32 InvalidateShaderCache; + NvU32 SetRasterControl; + NvU32 SetCtaFlags; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop15; + NvU32 SetSpareNoop11; + NvU32 SetSpare02; + NvU32 SetSpareNoop02; + NvU32 SetSpare03; + NvU32 SetCtaRasterSize; + NvU32 SetCtaGrfSize; + NvU32 SetCtaThreadDimensionA; + NvU32 SetCtaThreadDimensionB; + NvU32 SetCtaProgramStart; + NvU32 SetCtaRegisterAllocation; + NvU32 SetCtaTexture; + NvU32 BindCtaTextureSampler; + NvU32 BindCtaTextureHeader; + NvU32 BindConstantBuffer; + NvU32 PrefetchTextureSampler; + NvU32 InvalidateTextureDataCache; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop12; + NvU32 SetCubemapInterFaceFiltering; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x3F0[0x4]; + struct { + NvU32 A; + NvU32 B; + NvU32 Size; + NvU32 Limit; + NvU32 Format; + NvU32 Reserved_0x14[0x3]; + } SetGlobalMem[0x10]; + NvU32 Parameter[0x40]; +} gt214_compute_t; + + +#define NV85C0_SET_OBJECT 0x0000 +#define NV85C0_SET_OBJECT_POINTER 15:0 + +#define NV85C0_NO_OPERATION 0x0100 +#define NV85C0_NO_OPERATION_V 31:0 + +#define NV85C0_NOTIFY 0x0104 +#define NV85C0_NOTIFY_TYPE 31:0 +#define NV85C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV85C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV85C0_WAIT_FOR_IDLE 0x0110 +#define NV85C0_WAIT_FOR_IDLE_V 31:0 + +#define NV85C0_PM_TRIGGER 0x0140 +#define NV85C0_PM_TRIGGER_V 31:0 + +#define NV85C0_SET_CONTEXT_DMA_NOTIFY 0x0180 +#define NV85C0_SET_CONTEXT_DMA_NOTIFY_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_GLOBAL_MEM 0x01a0 +#define NV85C0_SET_CTX_DMA_GLOBAL_MEM_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_SEMAPHORE 0x01a4 +#define NV85C0_SET_CTX_DMA_SEMAPHORE_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY 0x01b8 +#define NV85C0_SET_CTX_DMA_SHADER_THREAD_MEMORY_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK 0x01bc +#define NV85C0_SET_CTX_DMA_SHADER_THREAD_STACK_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM 0x01c0 +#define NV85C0_SET_CTX_DMA_SHADER_PROGRAM_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER 0x01c4 +#define NV85C0_SET_CTX_DMA_TEXTURE_SAMPLER_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS 0x01c8 +#define NV85C0_SET_CTX_DMA_TEXTURE_HEADERS_HANDLE 31:0 + +#define NV85C0_SET_CTX_DMA_TEXTURE 0x01cc +#define NV85C0_SET_CTX_DMA_TEXTURE_HANDLE 31:0 + +#define NV85C0_DECRYPTION_CONTROL(j) (0x0200+(j)*16) +#define NV85C0_DECRYPTION_CONTROL_ALGORITHM 15:0 +#define NV85C0_DECRYPTION_CONTROL_ALGORITHM_NV17_COMPATIBLE 0x00000000 +#define NV85C0_DECRYPTION_CONTROL_KEY_COUNT 23:16 + +#define NV85C0_DECRYPTION_QUERY_SESSION_KEY(j) (0x0204+(j)*16) +#define NV85C0_DECRYPTION_QUERY_SESSION_KEY_V 31:0 + +#define NV85C0_DECRYPTION_GET_SESSION_KEY(j) (0x0208+(j)*16) +#define NV85C0_DECRYPTION_GET_SESSION_KEY_V 31:0 + +#define NV85C0_DECRYPTION_SET_ENCRYPTION(j) (0x020c+(j)*16) +#define NV85C0_DECRYPTION_SET_ENCRYPTION_V 31:0 + +#define NV85C0_SET_CTA_PROGRAM_A 0x0210 +#define NV85C0_SET_CTA_PROGRAM_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_CTA_PROGRAM_B 0x0214 +#define NV85C0_SET_CTA_PROGRAM_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_SHADER_THREAD_STACK_A 0x0218 +#define NV85C0_SET_SHADER_THREAD_STACK_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_SHADER_THREAD_STACK_B 0x021c +#define NV85C0_SET_SHADER_THREAD_STACK_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_SHADER_THREAD_STACK_C 0x0220 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE 3:0 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__0 0x00000000 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1 0x00000001 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2 0x00000002 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4 0x00000003 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__8 0x00000004 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__16 0x00000005 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__32 0x00000006 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__64 0x00000007 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__128 0x00000008 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__256 0x00000009 +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__512 0x0000000A +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__1024 0x0000000B +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__2048 0x0000000C +#define NV85C0_SET_SHADER_THREAD_STACK_C_SIZE__4096 0x0000000D + +#define NV85C0_SET_API_CALL_LIMIT 0x0224 +#define NV85C0_SET_API_CALL_LIMIT_CTA 3:0 +#define NV85C0_SET_API_CALL_LIMIT_CTA__0 0x00000000 +#define NV85C0_SET_API_CALL_LIMIT_CTA__1 0x00000001 +#define NV85C0_SET_API_CALL_LIMIT_CTA__2 0x00000002 +#define NV85C0_SET_API_CALL_LIMIT_CTA__4 0x00000003 +#define NV85C0_SET_API_CALL_LIMIT_CTA__8 0x00000004 +#define NV85C0_SET_API_CALL_LIMIT_CTA__16 0x00000005 +#define NV85C0_SET_API_CALL_LIMIT_CTA__32 0x00000006 +#define NV85C0_SET_API_CALL_LIMIT_CTA__64 0x00000007 +#define NV85C0_SET_API_CALL_LIMIT_CTA__128 0x00000008 +#define NV85C0_SET_API_CALL_LIMIT_CTA_NO_CHECK 0x0000000F + +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL 0x0228 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_PIXEL_ASSOCIATIVITY 7:4 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_ICACHE_NONPIXEL_ASSOCIATIVITY 11:8 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_PIXEL_ASSOCIATIVITY 15:12 +#define NV85C0_SET_SHADER_L1_CACHE_CONTROL_DCACHE_NONPIXEL_ASSOCIATIVITY 19:16 + +#define NV85C0_SET_TEX_SAMPLER_POOL_A 0x022c +#define NV85C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_TEX_SAMPLER_POOL_B 0x0230 +#define NV85C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_TEX_SAMPLER_POOL_C 0x0234 +#define NV85C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV85C0_LOAD_CONSTANT_SELECTOR 0x0238 +#define NV85C0_LOAD_CONSTANT_SELECTOR_TABLE_INDEX 7:0 +#define NV85C0_LOAD_CONSTANT_SELECTOR_CONSTANT_INDEX 23:8 + +#define NV85C0_LOAD_CONSTANT(i) (0x023c+(i)*4) +#define NV85C0_LOAD_CONSTANT_V 31:0 + +#define NV85C0_INVALIDATE_SAMPLER_CACHE 0x027c +#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV85C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV85C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x0280 +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV85C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV85C0_SET_SM_TIMEOUT_INTERVAL 0x0288 +#define NV85C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV85C0_TEST_FOR_COMPUTE 0x028c +#define NV85C0_TEST_FOR_COMPUTE_V 31:0 + +#define NV85C0_SET_SHADER_SCHEDULING 0x0290 +#define NV85C0_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV85C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV85C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_A 0x0294 +#define NV85C0_SET_SHADER_THREAD_MEMORY_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_B 0x0298 +#define NV85C0_SET_SHADER_THREAD_MEMORY_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_C 0x029c +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE 3:0 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__0 0x00000000 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1 0x00000001 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2 0x00000002 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4 0x00000003 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__8 0x00000004 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__16 0x00000005 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__32 0x00000006 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__64 0x00000007 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__128 0x00000008 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__256 0x00000009 +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__512 0x0000000A +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__1024 0x0000000B +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__2048 0x0000000C +#define NV85C0_SET_SHADER_THREAD_MEMORY_C_SIZE__4096 0x0000000D + +#define NV85C0_SET_WORK_DISTRIBUTION 0x02a0 +#define NV85C0_SET_WORK_DISTRIBUTION_V 3:0 +#define NV85C0_SET_WORK_DISTRIBUTION_V_HARDWARE_POLICY 0x00000000 +#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_DYNAMIC 0x00000001 +#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_DYNAMIC 0x00000002 +#define NV85C0_SET_WORK_DISTRIBUTION_V_WIDE_FIXED 0x00000003 +#define NV85C0_SET_WORK_DISTRIBUTION_V_DEEP_FIXED 0x00000004 +#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_DYNAMIC 0x00000005 +#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_DYNAMIC 0x00000006 +#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_WIDE_FIXED 0x00000007 +#define NV85C0_SET_WORK_DISTRIBUTION_V_FILL_DEEP_FIXED 0x00000008 + +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A 0x02a4 +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_A_OFFSET_UPPER 7:0 + +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B 0x02a8 +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_B_OFFSET_LOWER 31:0 + +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C 0x02ac +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_SIZE 15:0 +#define NV85C0_LOAD_CONSTANT_BUFFER_TABLE_C_ENTRY 23:16 + +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL 0x02b0 +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK 0:0 +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_FALSE 0x00000000 +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_MASTER_MASK_TRUE 0x00000001 +#define NV85C0_SET_SHADER_ERROR_TRAP_CONTROL_SUBSET_MASK 31:1 + +#define NV85C0_SET_CTA_RESOURCE_ALLOCATION 0x02b4 +#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_THREAD_COUNT 15:0 +#define NV85C0_SET_CTA_RESOURCE_ALLOCATION_BARRIER_COUNT 23:16 + +#define NV85C0_SET_CTA_THREAD_CONTROL 0x02b8 +#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH 0:0 +#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_FALSE 0x00000000 +#define NV85C0_SET_CTA_THREAD_CONTROL_ALLOW_CONVOY_LAUNCH_TRUE 0x00000001 + +#define NV85C0_SET_PHASE_ID_CONTROL 0x02bc +#define NV85C0_SET_PHASE_ID_CONTROL_WINDOW_SIZE 2:0 +#define NV85C0_SET_PHASE_ID_CONTROL_LOCK_PHASE 6:4 + +#define NV85C0_SET_CTA_REGISTER_COUNT 0x02c0 +#define NV85C0_SET_CTA_REGISTER_COUNT_V 7:0 + +#define NV85C0_SET_TEX_HEADER_POOL_A 0x02c4 +#define NV85C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_TEX_HEADER_POOL_B 0x02c8 +#define NV85C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_TEX_HEADER_POOL_C 0x02cc +#define NV85C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x02d0+(i)*4) +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL(i) (0x02e0+(i)*4) +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EDGE 0:0 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK 6:4 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_ACE 0x00000000 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DIS 0x00000001 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_DSM 0x00000002 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_PIC 0x00000003 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_STP 0x00000004 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_BLOCK_XIU 0x00000005 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_FUNC 23:8 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_EVENT 31:24 + +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x02f0 +#define NV85C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 3:0 + +#define NV85C0_RESET_CTA_TRACKING_RAM 0x02f4 +#define NV85C0_RESET_CTA_TRACKING_RAM_V 31:0 + +#define NV85C0_INITIALIZE 0x02f8 +#define NV85C0_INITIALIZE_INIT_CTA_SHAPE 0:0 +#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_FALSE 0x00000000 +#define NV85C0_INITIALIZE_INIT_CTA_SHAPE_TRUE 0x00000001 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE 0x02fc +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM 2:0 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM__24 0x00000005 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 + +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL 0x0300 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V 2:0 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 +#define NV85C0_SET_SHADER_THREAD_MEMORY_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 + +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE 0x0304 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM 2:0 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__1 0x00000000 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__2 0x00000001 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__4 0x00000002 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__8 0x00000003 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__16 0x00000004 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM__24 0x00000005 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_MAX_TIDS_PER_SM_HW_MAX 0x00000007 + +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL 0x0308 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V 2:0 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_THROTTLE_MAX 0x00000000 +#define NV85C0_SET_SHADER_THREAD_STACK_THROTTLE_CONTROL_V_USE_HW_MAX 0x00000001 + +#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS 0x030c +#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA 0:0 +#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_FALSE 0x00000000 +#define NV85C0_PREFETCH_SHADER_INSTRUCTIONS_CTA_TRUE 0x00000001 + +#define NV85C0_SET_REPORT_SEMAPHORE_A 0x0310 +#define NV85C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_REPORT_SEMAPHORE_B 0x0314 +#define NV85C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_REPORT_SEMAPHORE_C 0x0318 +#define NV85C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV85C0_SET_REPORT_SEMAPHORE_D 0x031c +#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV85C0_SET_REPORT_SEMAPHORE_D_OPERATION_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE 2:2 +#define NV85C0_SET_REPORT_SEMAPHORE_D_RELEASE_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE 3:3 +#define NV85C0_SET_REPORT_SEMAPHORE_D_ACQUIRE_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION 7:4 +#define NV85C0_SET_REPORT_SEMAPHORE_D_PIPELINE_LOCATION_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON 8:8 +#define NV85C0_SET_REPORT_SEMAPHORE_D_COMPARISON_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 9:9 +#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT 14:10 +#define NV85C0_SET_REPORT_SEMAPHORE_D_REPORT_UNUSED 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 15:15 +#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV85C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 + +#define NV85C0_SET_LAUNCH_ENABLE_A 0x0320 +#define NV85C0_SET_LAUNCH_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_LAUNCH_ENABLE_B 0x0324 +#define NV85C0_SET_LAUNCH_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_LAUNCH_ENABLE_C 0x0328 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE 2:0 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_FALSE 0x00000000 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_TRUE 0x00000001 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV85C0_SET_LAUNCH_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE 0x032c +#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE 31:0 +#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_CUBEMAP_ADDRESS_MODE_OVERRIDE_ENABLE_TRUE 0x00000001 + +#define NV85C0_PIPE_NOP 0x0330 +#define NV85C0_PIPE_NOP_V 31:0 + +#define NV85C0_SET_SPARE_NOOP13 0x0334 +#define NV85C0_SET_SPARE_NOOP13_V 31:0 + +#define NV85C0_SET_SPARE_NOOP09 0x0338 +#define NV85C0_SET_SPARE_NOOP09_V 31:0 + +#define NV85C0_SET_SPARE_NOOP14 0x033c +#define NV85C0_SET_SPARE_NOOP14_V 31:0 + +#define NV85C0_SET_SPARE_NOOP00 0x0340 +#define NV85C0_SET_SPARE_NOOP00_V 31:0 + +#define NV85C0_SET_SPARE_NOOP01 0x0344 +#define NV85C0_SET_SPARE_NOOP01_V 31:0 + +#define NV85C0_SET_SPARE00 0x0348 +#define NV85C0_SET_SPARE00_V 31:0 + +#define NV85C0_SET_SPARE01 0x034c +#define NV85C0_SET_SPARE01_V 31:0 + +#define NV85C0_SET_SPARE_NOOP05 0x0350 +#define NV85C0_SET_SPARE_NOOP05_V 31:0 + +#define NV85C0_SET_SPARE_NOOP10 0x0354 +#define NV85C0_SET_SPARE_NOOP10_V 31:0 + +#define NV85C0_SET_GLOBAL_COLOR_KEY 0x0358 +#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE 31:0 +#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV85C0_RESET_REF_COUNT 0x035c +#define NV85C0_RESET_REF_COUNT_REF_CNT 3:0 + +#define NV85C0_WAIT_REF_COUNT 0x0360 +#define NV85C0_WAIT_REF_COUNT_COMPARE 7:4 +#define NV85C0_WAIT_REF_COUNT_COMPARE_COUNT_QUIESENT 0x00000000 +#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_EQUAL 0x00000001 +#define NV85C0_WAIT_REF_COUNT_COMPARE_VALUE_CLOCKHAND 0x00000002 +#define NV85C0_WAIT_REF_COUNT_REF_CNT 11:8 + +#define NV85C0_SET_REF_COUNT_VALUE 0x0364 +#define NV85C0_SET_REF_COUNT_VALUE_V 31:0 + +#define NV85C0_LAUNCH 0x0368 +#define NV85C0_LAUNCH_V 31:0 + +#define NV85C0_SET_LAUNCH_ID 0x036c +#define NV85C0_SET_LAUNCH_ID_REF_CNT 3:0 + +#define NV85C0_SET_LAUNCH_CONTROL 0x0370 +#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH 7:0 +#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_MANUAL_LAUNCH 0x00000000 +#define NV85C0_SET_LAUNCH_CONTROL_LAUNCH_AUTO_LAUNCH 0x00000001 + +#define NV85C0_SET_PARAMETER_SIZE 0x0374 +#define NV85C0_SET_PARAMETER_SIZE_AUTO_LAUNCH_INDEX 7:0 +#define NV85C0_SET_PARAMETER_SIZE_COUNT 15:8 + +#define NV85C0_SET_SAMPLER_BINDING 0x0378 +#define NV85C0_SET_SAMPLER_BINDING_V 0:0 +#define NV85C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV85C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV85C0_SET_SHADER_CONTROL 0x037c +#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV85C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV85C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV85C0_INVALIDATE_SHADER_CACHE 0x0380 +#define NV85C0_INVALIDATE_SHADER_CACHE_V 1:0 +#define NV85C0_INVALIDATE_SHADER_CACHE_V_ALL 0x00000000 +#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1 0x00000001 +#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_DATA 0x00000002 +#define NV85C0_INVALIDATE_SHADER_CACHE_V_L1_INSTRUCTION 0x00000003 + +#define NV85C0_SET_RASTER_CONTROL 0x0384 +#define NV85C0_SET_RASTER_CONTROL_PROGRAM 7:0 +#define NV85C0_SET_RASTER_CONTROL_PROGRAM_DISABLE 0x00000000 +#define NV85C0_SET_RASTER_CONTROL_FIXED 15:8 +#define NV85C0_SET_RASTER_CONTROL_FIXED_DISABLE 0x00000000 +#define NV85C0_SET_RASTER_CONTROL_FIXED_SIMPLE 0x00000001 +#define NV85C0_SET_RASTER_CONTROL_FIXED_DXVA_RUN_CODED 0x00000002 +#define NV85C0_SET_RASTER_CONTROL_DECRYPTION 23:16 +#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_DISABLE 0x00000000 +#define NV85C0_SET_RASTER_CONTROL_DECRYPTION_ENABLE 0x00000001 + +#define NV85C0_SET_CTA_FLAGS 0x0388 +#define NV85C0_SET_CTA_FLAGS_V 15:0 + +#define NV85C0_SET_SPARE_NOOP06 0x038c +#define NV85C0_SET_SPARE_NOOP06_V 31:0 + +#define NV85C0_SET_SPARE_NOOP15 0x0390 +#define NV85C0_SET_SPARE_NOOP15_V 31:0 + +#define NV85C0_SET_SPARE_NOOP11 0x0394 +#define NV85C0_SET_SPARE_NOOP11_V 31:0 + +#define NV85C0_SET_SPARE02 0x0398 +#define NV85C0_SET_SPARE02_V 31:0 + +#define NV85C0_SET_SPARE_NOOP02 0x039c +#define NV85C0_SET_SPARE_NOOP02_V 31:0 + +#define NV85C0_SET_SPARE03 0x03a0 +#define NV85C0_SET_SPARE03_V 31:0 + +#define NV85C0_SET_CTA_RASTER_SIZE 0x03a4 +#define NV85C0_SET_CTA_RASTER_SIZE_WIDTH 15:0 +#define NV85C0_SET_CTA_RASTER_SIZE_HEIGHT 31:16 + +#define NV85C0_SET_CTA_GRF_SIZE 0x03a8 +#define NV85C0_SET_CTA_GRF_SIZE_V 31:0 + +#define NV85C0_SET_CTA_THREAD_DIMENSION_A 0x03ac +#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 +#define NV85C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 + +#define NV85C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 +#define NV85C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 + +#define NV85C0_SET_CTA_PROGRAM_START 0x03b4 +#define NV85C0_SET_CTA_PROGRAM_START_OFFSET 23:0 + +#define NV85C0_SET_CTA_REGISTER_ALLOCATION 0x03b8 +#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V 31:0 +#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THICK 0x00000001 +#define NV85C0_SET_CTA_REGISTER_ALLOCATION_V_THIN 0x00000002 + +#define NV85C0_SET_CTA_TEXTURE 0x03bc +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV85C0_SET_CTA_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER 0x03c0 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID 0:0 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV85C0_BIND_CTA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV85C0_BIND_CTA_TEXTURE_HEADER 0x03c4 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID 0:0 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV85C0_BIND_CTA_TEXTURE_HEADER_INDEX 30:9 + +#define NV85C0_BIND_CONSTANT_BUFFER 0x03c8 +#define NV85C0_BIND_CONSTANT_BUFFER_VALID 3:0 +#define NV85C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV85C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE 7:4 +#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_TYPE_CTA 0x00000000 +#define NV85C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 11:8 +#define NV85C0_BIND_CONSTANT_BUFFER_TABLE_ENTRY 19:12 + +#define NV85C0_PREFETCH_TEXTURE_SAMPLER 0x03cc +#define NV85C0_PREFETCH_TEXTURE_SAMPLER_INDEX 21:0 + +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE 0x03d0 +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 5:4 +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L2_ONLY 0x00000001 +#define NV85C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_AND_L2 0x00000002 + +#define NV85C0_SET_SPARE_NOOP03 0x03d4 +#define NV85C0_SET_SPARE_NOOP03_V 31:0 + +#define NV85C0_SET_SPARE_NOOP07 0x03d8 +#define NV85C0_SET_SPARE_NOOP07_V 31:0 + +#define NV85C0_SET_SPARE_NOOP04 0x03dc +#define NV85C0_SET_SPARE_NOOP04_V 31:0 + +#define NV85C0_SET_SPARE_NOOP08 0x03e0 +#define NV85C0_SET_SPARE_NOOP08_V 31:0 + +#define NV85C0_SET_SPARE_NOOP12 0x03e4 +#define NV85C0_SET_SPARE_NOOP12_V 31:0 + +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x03e8 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV85C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV85C0_SET_SHADER_EXCEPTIONS 0x03ec +#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV85C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV85C0_SET_GLOBAL_MEM_A(j) (0x0400+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_A_OFFSET_UPPER 7:0 + +#define NV85C0_SET_GLOBAL_MEM_B(j) (0x0404+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_B_OFFSET_LOWER 31:0 + +#define NV85C0_SET_GLOBAL_MEM_SIZE(j) (0x0408+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_SIZE_BLOCK_PITCH 31:0 + +#define NV85C0_SET_GLOBAL_MEM_LIMIT(j) (0x040c+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_LIMIT_MAX 31:0 + +#define NV85C0_SET_GLOBAL_MEM_FORMAT(j) (0x0410+(j)*32) +#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT 0:0 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_BLOCKLINEAR 0x00000000 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_MEM_LAYOUT_PITCH 0x00000001 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH 7:4 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_WIDTH_ONE_GOB 0x00000000 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT 11:8 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_ONE_GOB 0x00000000 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_TWO_GOBS 0x00000001 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_FOUR_GOBS 0x00000002 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV85C0_SET_GLOBAL_MEM_FORMAT_BLOCK_LINEAR_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV85C0_PARAMETER(i) (0x0600+(i)*4) +#define NV85C0_PARAMETER_V 31:0 + +#endif /* _cl_gt214_compute_h_ */ diff --git a/Compute-Class-Methods/cl90c0.h b/Compute-Class-Methods/cl90c0.h new file mode 100644 index 0000000..d49ab75 --- /dev/null +++ b/Compute-Class-Methods/cl90c0.h @@ -0,0 +1,1033 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_compute_a_h_ +#define _cl_fermi_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_compute_a */ + +#include "nvtypes.h" + +#define FERMI_COMPUTE_A 0x90C0 + +typedef volatile struct _cl90c0_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 LoadMmeInstructionRamPointer; + NvU32 LoadMmeInstructionRam; + NvU32 LoadMmeStartAddressRamPointer; + NvU32 LoadMmeStartAddressRam; + NvU32 SetMmeShadowRamControl; + NvU32 Reserved_0x128[0x2]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0x3]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0x2B]; + NvU32 SetShaderLocalMemoryLowSize; + NvU32 SetShaderLocalMemoryHighSize; + NvU32 SetShaderLocalMemoryCrsSize; + NvU32 SetBindingControlTexture; + NvU32 SetShaderSharedMemoryWindow; + NvU32 Reserved_0x218[0x1]; + NvU32 InvalidateShaderCaches; + NvU32 Reserved_0x220[0x2]; + NvU32 BindTextureSampler; + NvU32 BindTextureHeader; + NvU32 BindExtraTextureSampler; + NvU32 BindExtraTextureHeader; + NvU32 SetCtaRasterSizeA; + NvU32 SetCtaRasterSizeB; + NvU32 Reserved_0x240[0x1]; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 Reserved_0x248[0x1]; + NvU32 SetShaderSharedMemorySize; + NvU32 SetCtaThreadCount; + NvU32 SetCtaBarrierCount; + NvU32 Reserved_0x258[0xD]; + NvU32 TestForCompute; + NvU32 Reserved_0x290[0x3]; + NvU32 BeginGrid; + NvU32 SetWorkDistribution; + NvU32 Reserved_0x2A4[0x7]; + NvU32 SetCtaRegisterCount; + NvU32 SetGaToVaMappingMode; + NvU32 LoadGaToVaMappingEntry; + NvU32 Reserved_0x2CC[0xF]; + NvU32 SetL1Configuration; + NvU32 SetRenderEnableControl; + NvU32 Reserved_0x310[0x14]; + NvU32 WaitRefCount; + NvU32 Reserved_0x364[0x1]; + NvU32 Launch; + NvU32 SetLaunchId; + NvU32 Reserved_0x370[0xF]; + NvU32 SetCtaThreadDimensionA; + NvU32 SetCtaThreadDimensionB; + NvU32 SetCtaProgramStart; + NvU32 Reserved_0x3B8[0x52]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x76]; + NvU32 SetMaxSmCount; + NvU32 Reserved_0x75C[0x8]; + NvU32 SetShaderLocalMemoryWindow; + NvU32 SetGridParam; + NvU32 Reserved_0x784[0x3]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 SetShaderLocalMemoryC; + NvU32 SetShaderLocalMemoryD; + NvU32 SetShaderLocalMemoryE; + NvU32 Reserved_0x7A4[0x98]; + NvU32 EndGrid; + NvU32 SetLaunchSize; + NvU32 Reserved_0xA0C[0xD6]; + NvU32 SetApiVisibleCallLimit; + NvU32 Reserved_0xD68[0xB]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x57]; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; + NvU32 Reserved_0xF54[0x2C]; + NvU32 SetForceOneTextureUnit; + NvU32 Reserved_0x1008[0xE]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 Reserved_0x1070[0x21]; + NvU32 UnbindAll; + NvU32 Reserved_0x10F8[0x4F]; + NvU32 SetSamplerBinding; + NvU32 Reserved_0x1238[0x14]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x8]; + NvU32 SetShaderScheduling; + NvU32 Reserved_0x12B0[0x20]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x6]; + NvU32 SetGlobalColorKey; + NvU32 Reserved_0x1358[0x33]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x3F]; + NvU32 PerfmonTransfer; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x22]; + NvU32 SetProgramRegionA; + NvU32 SetProgramRegionB; + NvU32 Reserved_0x1610[0x15]; + NvU32 SetCubemapInterFaceFiltering; + NvU32 Reserved_0x1668[0xA]; + NvU32 SetShaderControl; + NvU32 BindConstantBuffer; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xA5]; + NvU32 InvalidateConstantBufferCache; + NvU32 Reserved_0x1934[0x4]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A24[0x1]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x21C]; + NvU32 SetConstantBufferSelectorA; + NvU32 SetConstantBufferSelectorB; + NvU32 SetConstantBufferSelectorC; + NvU32 LoadConstantBufferOffset; + NvU32 LoadConstantBuffer[0x10]; + NvU32 Reserved_0x23D0[0xCC]; + struct { + NvU32 A; + NvU32 B; + NvU32 C; + NvU32 D; + NvU32 Format; + NvU32 BlockSize; + NvU32 Reserved_0x18[0x2]; + } SetSuLdStTarget[0x8]; + NvU32 Reserved_0x2800[0x2D7]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 Reserved_0x33E0[0x8]; + NvU32 SetMmeShadowScratch[0x80]; + NvU32 Reserved_0x3600[0x80]; + struct { + NvU32 Macro; + NvU32 Data; + } CallMme[0x80]; +} fermi_compute_a_t; + + +#define NV90C0_SET_OBJECT 0x0000 +#define NV90C0_SET_OBJECT_CLASS_ID 15:0 +#define NV90C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NV90C0_NO_OPERATION 0x0100 +#define NV90C0_NO_OPERATION_V 31:0 + +#define NV90C0_SET_NOTIFY_A 0x0104 +#define NV90C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV90C0_SET_NOTIFY_B 0x0108 +#define NV90C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV90C0_NOTIFY 0x010c +#define NV90C0_NOTIFY_TYPE 31:0 +#define NV90C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV90C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV90C0_WAIT_FOR_IDLE 0x0110 +#define NV90C0_WAIT_FOR_IDLE_V 31:0 + +#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV90C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV90C0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV90C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV90C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV90C0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV90C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV90C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV90C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV90C0_SEND_GO_IDLE 0x013c +#define NV90C0_SEND_GO_IDLE_V 31:0 + +#define NV90C0_PM_TRIGGER 0x0140 +#define NV90C0_PM_TRIGGER_V 31:0 + +#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV90C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV90C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE 0x0204 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V 23:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE 0x0208 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V 23:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE 0x020c +#define NV90C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V 20:0 + +#define NV90C0_SET_BINDING_CONTROL_TEXTURE 0x0210 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV90C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NV90C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV90C0_INVALIDATE_SHADER_CACHES 0x021c +#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 +#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NV90C0_BIND_TEXTURE_SAMPLER 0x0228 +#define NV90C0_BIND_TEXTURE_SAMPLER_VALID 0:0 +#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV90C0_BIND_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV90C0_BIND_TEXTURE_HEADER 0x022c +#define NV90C0_BIND_TEXTURE_HEADER_VALID 0:0 +#define NV90C0_BIND_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV90C0_BIND_TEXTURE_HEADER_INDEX 30:9 + +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER 0x0230 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID 0:0 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV90C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER 0x0234 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID 0:0 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV90C0_BIND_EXTRA_TEXTURE_HEADER_INDEX 30:9 + +#define NV90C0_SET_CTA_RASTER_SIZE_A 0x0238 +#define NV90C0_SET_CTA_RASTER_SIZE_A_WIDTH 15:0 +#define NV90C0_SET_CTA_RASTER_SIZE_A_HEIGHT 31:16 + +#define NV90C0_SET_CTA_RASTER_SIZE_B 0x023c +#define NV90C0_SET_CTA_RASTER_SIZE_B_DEPTH 15:0 + +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE 0x024c +#define NV90C0_SET_SHADER_SHARED_MEMORY_SIZE_V 17:0 + +#define NV90C0_SET_CTA_THREAD_COUNT 0x0250 +#define NV90C0_SET_CTA_THREAD_COUNT_V 15:0 + +#define NV90C0_SET_CTA_BARRIER_COUNT 0x0254 +#define NV90C0_SET_CTA_BARRIER_COUNT_V 7:0 + +#define NV90C0_TEST_FOR_COMPUTE 0x028c +#define NV90C0_TEST_FOR_COMPUTE_V 31:0 + +#define NV90C0_BEGIN_GRID 0x029c +#define NV90C0_BEGIN_GRID_V 0:0 + +#define NV90C0_SET_WORK_DISTRIBUTION 0x02a0 +#define NV90C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE 16:13 +#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE 4:4 +#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE 0x00000000 +#define NV90C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE 0x00000001 +#define NV90C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS 12:5 + +#define NV90C0_SET_CTA_REGISTER_COUNT 0x02c0 +#define NV90C0_SET_CTA_REGISTER_COUNT_V 7:0 + +#define NV90C0_SET_GA_TO_VA_MAPPING_MODE 0x02c4 +#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V 0:0 +#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 +#define NV90C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 + +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 +#define NV90C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 + +#define NV90C0_SET_L1_CONFIGURATION 0x0308 +#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NV90C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NV90C0_SET_RENDER_ENABLE_CONTROL 0x030c +#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NV90C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NV90C0_WAIT_REF_COUNT 0x0360 +#define NV90C0_WAIT_REF_COUNT_REF_CNT 9:8 +#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM 0:0 +#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE 0x00000000 +#define NV90C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE 0x00000001 + +#define NV90C0_LAUNCH 0x0368 +#define NV90C0_LAUNCHCTA_PARAM 31:0 + +#define NV90C0_SET_LAUNCH_ID 0x036c +#define NV90C0_SET_LAUNCH_ID_REF_CNT 1:0 + +#define NV90C0_SET_CTA_THREAD_DIMENSION_A 0x03ac +#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 +#define NV90C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 + +#define NV90C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 +#define NV90C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 + +#define NV90C0_SET_CTA_PROGRAM_START 0x03b4 +#define NV90C0_SET_CTA_PROGRAM_START_OFFSET 31:0 + +#define NV90C0_SET_FALCON00 0x0500 +#define NV90C0_SET_FALCON00_V 31:0 + +#define NV90C0_SET_FALCON01 0x0504 +#define NV90C0_SET_FALCON01_V 31:0 + +#define NV90C0_SET_FALCON02 0x0508 +#define NV90C0_SET_FALCON02_V 31:0 + +#define NV90C0_SET_FALCON03 0x050c +#define NV90C0_SET_FALCON03_V 31:0 + +#define NV90C0_SET_FALCON04 0x0510 +#define NV90C0_SET_FALCON04_V 31:0 + +#define NV90C0_SET_FALCON05 0x0514 +#define NV90C0_SET_FALCON05_V 31:0 + +#define NV90C0_SET_FALCON06 0x0518 +#define NV90C0_SET_FALCON06_V 31:0 + +#define NV90C0_SET_FALCON07 0x051c +#define NV90C0_SET_FALCON07_V 31:0 + +#define NV90C0_SET_FALCON08 0x0520 +#define NV90C0_SET_FALCON08_V 31:0 + +#define NV90C0_SET_FALCON09 0x0524 +#define NV90C0_SET_FALCON09_V 31:0 + +#define NV90C0_SET_FALCON10 0x0528 +#define NV90C0_SET_FALCON10_V 31:0 + +#define NV90C0_SET_FALCON11 0x052c +#define NV90C0_SET_FALCON11_V 31:0 + +#define NV90C0_SET_FALCON12 0x0530 +#define NV90C0_SET_FALCON12_V 31:0 + +#define NV90C0_SET_FALCON13 0x0534 +#define NV90C0_SET_FALCON13_V 31:0 + +#define NV90C0_SET_FALCON14 0x0538 +#define NV90C0_SET_FALCON14_V 31:0 + +#define NV90C0_SET_FALCON15 0x053c +#define NV90C0_SET_FALCON15_V 31:0 + +#define NV90C0_SET_FALCON16 0x0540 +#define NV90C0_SET_FALCON16_V 31:0 + +#define NV90C0_SET_FALCON17 0x0544 +#define NV90C0_SET_FALCON17_V 31:0 + +#define NV90C0_SET_FALCON18 0x0548 +#define NV90C0_SET_FALCON18_V 31:0 + +#define NV90C0_SET_FALCON19 0x054c +#define NV90C0_SET_FALCON19_V 31:0 + +#define NV90C0_SET_FALCON20 0x0550 +#define NV90C0_SET_FALCON20_V 31:0 + +#define NV90C0_SET_FALCON21 0x0554 +#define NV90C0_SET_FALCON21_V 31:0 + +#define NV90C0_SET_FALCON22 0x0558 +#define NV90C0_SET_FALCON22_V 31:0 + +#define NV90C0_SET_FALCON23 0x055c +#define NV90C0_SET_FALCON23_V 31:0 + +#define NV90C0_SET_FALCON24 0x0560 +#define NV90C0_SET_FALCON24_V 31:0 + +#define NV90C0_SET_FALCON25 0x0564 +#define NV90C0_SET_FALCON25_V 31:0 + +#define NV90C0_SET_FALCON26 0x0568 +#define NV90C0_SET_FALCON26_V 31:0 + +#define NV90C0_SET_FALCON27 0x056c +#define NV90C0_SET_FALCON27_V 31:0 + +#define NV90C0_SET_FALCON28 0x0570 +#define NV90C0_SET_FALCON28_V 31:0 + +#define NV90C0_SET_FALCON29 0x0574 +#define NV90C0_SET_FALCON29_V 31:0 + +#define NV90C0_SET_FALCON30 0x0578 +#define NV90C0_SET_FALCON30_V 31:0 + +#define NV90C0_SET_FALCON31 0x057c +#define NV90C0_SET_FALCON31_V 31:0 + +#define NV90C0_SET_MAX_SM_COUNT 0x0758 +#define NV90C0_SET_MAX_SM_COUNT_V 8:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NV90C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV90C0_SET_GRID_PARAM 0x0780 +#define NV90C0_SET_GRID_PARAM_V 31:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NV90C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NV90C0_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NV90C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NV90C0_END_GRID 0x0a04 +#define NV90C0_END_GRID_V 0:0 + +#define NV90C0_SET_LAUNCH_SIZE 0x0a08 +#define NV90C0_SET_LAUNCH_SIZE_V 31:0 + +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA 3:0 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0 0x00000000 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1 0x00000001 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2 0x00000002 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4 0x00000003 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8 0x00000004 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16 0x00000005 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32 0x00000006 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64 0x00000007 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128 0x00000008 +#define NV90C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK 0x0000000F + +#define NV90C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NV90C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NV90C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV90C0_SET_SPARE_NOOP12 0x0f44 +#define NV90C0_SET_SPARE_NOOP12_V 31:0 + +#define NV90C0_SET_SPARE_NOOP13 0x0f48 +#define NV90C0_SET_SPARE_NOOP13_V 31:0 + +#define NV90C0_SET_SPARE_NOOP14 0x0f4c +#define NV90C0_SET_SPARE_NOOP14_V 31:0 + +#define NV90C0_SET_SPARE_NOOP15 0x0f50 +#define NV90C0_SET_SPARE_NOOP15_V 31:0 + +#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 +#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 +#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 + +#define NV90C0_SET_SPARE_NOOP00 0x1040 +#define NV90C0_SET_SPARE_NOOP00_V 31:0 + +#define NV90C0_SET_SPARE_NOOP01 0x1044 +#define NV90C0_SET_SPARE_NOOP01_V 31:0 + +#define NV90C0_SET_SPARE_NOOP02 0x1048 +#define NV90C0_SET_SPARE_NOOP02_V 31:0 + +#define NV90C0_SET_SPARE_NOOP03 0x104c +#define NV90C0_SET_SPARE_NOOP03_V 31:0 + +#define NV90C0_SET_SPARE_NOOP04 0x1050 +#define NV90C0_SET_SPARE_NOOP04_V 31:0 + +#define NV90C0_SET_SPARE_NOOP05 0x1054 +#define NV90C0_SET_SPARE_NOOP05_V 31:0 + +#define NV90C0_SET_SPARE_NOOP06 0x1058 +#define NV90C0_SET_SPARE_NOOP06_V 31:0 + +#define NV90C0_SET_SPARE_NOOP07 0x105c +#define NV90C0_SET_SPARE_NOOP07_V 31:0 + +#define NV90C0_SET_SPARE_NOOP08 0x1060 +#define NV90C0_SET_SPARE_NOOP08_V 31:0 + +#define NV90C0_SET_SPARE_NOOP09 0x1064 +#define NV90C0_SET_SPARE_NOOP09_V 31:0 + +#define NV90C0_SET_SPARE_NOOP10 0x1068 +#define NV90C0_SET_SPARE_NOOP10_V 31:0 + +#define NV90C0_SET_SPARE_NOOP11 0x106c +#define NV90C0_SET_SPARE_NOOP11_V 31:0 + +#define NV90C0_UNBIND_ALL 0x10f4 +#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS 0:0 +#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 +#define NV90C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 +#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 +#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 +#define NV90C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 +#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NV90C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NV90C0_SET_SAMPLER_BINDING 0x1234 +#define NV90C0_SET_SAMPLER_BINDING_V 0:0 +#define NV90C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV90C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NV90C0_SET_SHADER_SCHEDULING 0x12ac +#define NV90C0_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV90C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV90C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV90C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 +#define NV90C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 + +#define NV90C0_SET_GLOBAL_COLOR_KEY 0x1354 +#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV90C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NV90C0_PERFMON_TRANSFER 0x1524 +#define NV90C0_PERFMON_TRANSFER_V 31:0 + +#define NV90C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV90C0_SET_RENDER_ENABLE_A 0x1550 +#define NV90C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_RENDER_ENABLE_B 0x1554 +#define NV90C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_RENDER_ENABLE_C 0x1558 +#define NV90C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV90C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV90C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NV90C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NV90C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NV90C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV90C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NV90C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NV90C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_TEX_HEADER_POOL_C 0x157c +#define NV90C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV90C0_SET_PROGRAM_REGION_A 0x1608 +#define NV90C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NV90C0_SET_PROGRAM_REGION_B 0x160c +#define NV90C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV90C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV90C0_SET_SHADER_CONTROL 0x1690 +#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV90C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV90C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 + +#define NV90C0_BIND_CONSTANT_BUFFER 0x1694 +#define NV90C0_BIND_CONSTANT_BUFFER_VALID 0:0 +#define NV90C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV90C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV90C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 12:8 + +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM 8:8 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE 0x00000001 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NV90C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NV90C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV90C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV90C0_PIPE_NOP 0x1a2c +#define NV90C0_PIPE_NOP_V 31:0 + +#define NV90C0_SET_SPARE00 0x1a30 +#define NV90C0_SET_SPARE00_V 31:0 + +#define NV90C0_SET_SPARE01 0x1a34 +#define NV90C0_SET_SPARE01_V 31:0 + +#define NV90C0_SET_SPARE02 0x1a38 +#define NV90C0_SET_SPARE02_V 31:0 + +#define NV90C0_SET_SPARE03 0x1a3c +#define NV90C0_SET_SPARE03_V 31:0 + +#define NV90C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NV90C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NV90C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NV90C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV90C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NV90C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV90C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV90C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NV90C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 + +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NV90C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NV90C0_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NV90C0_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NV90C0_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NV90C0_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 + +#define NV90C0_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 + +#define NV90C0_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 + +#define NV90C0_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 +#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 +#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 + +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F +#define NV90C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT 25:17 + +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV90C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NV90C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NV90C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV90C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV90C0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV90C0_CALL_MME_MACRO_V 31:0 + +#define NV90C0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV90C0_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_compute_a_h_ */ diff --git a/Compute-Class-Methods/cl91c0.h b/Compute-Class-Methods/cl91c0.h new file mode 100644 index 0000000..b83f4aa --- /dev/null +++ b/Compute-Class-Methods/cl91c0.h @@ -0,0 +1,1049 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_fermi_compute_b_h_ +#define _cl_fermi_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl fermi_compute_b */ + +#include "nvtypes.h" + +#define FERMI_COMPUTE_B 0x91C0 + +typedef volatile struct _cl91c0_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 LoadMmeInstructionRamPointer; + NvU32 LoadMmeInstructionRam; + NvU32 LoadMmeStartAddressRamPointer; + NvU32 LoadMmeStartAddressRam; + NvU32 SetMmeShadowRamControl; + NvU32 Reserved_0x128[0x2]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 Reserved_0x144[0x3]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0x2B]; + NvU32 SetShaderLocalMemoryLowSize; + NvU32 SetShaderLocalMemoryHighSize; + NvU32 SetShaderLocalMemoryCrsSize; + NvU32 SetBindingControlTexture; + NvU32 SetShaderSharedMemoryWindow; + NvU32 Reserved_0x218[0x1]; + NvU32 InvalidateShaderCaches; + NvU32 Reserved_0x220[0x2]; + NvU32 BindTextureSampler; + NvU32 BindTextureHeader; + NvU32 BindExtraTextureSampler; + NvU32 BindExtraTextureHeader; + NvU32 SetCtaRasterSizeA; + NvU32 SetCtaRasterSizeB; + NvU32 Reserved_0x240[0x1]; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 Reserved_0x248[0x1]; + NvU32 SetShaderSharedMemorySize; + NvU32 SetCtaThreadCount; + NvU32 SetCtaBarrierCount; + NvU32 Reserved_0x258[0xD]; + NvU32 TestForCompute; + NvU32 Reserved_0x290[0x3]; + NvU32 BeginGrid; + NvU32 SetWorkDistribution; + NvU32 Reserved_0x2A4[0x7]; + NvU32 SetCtaRegisterCount; + NvU32 SetGaToVaMappingMode; + NvU32 LoadGaToVaMappingEntry; + NvU32 Reserved_0x2CC[0x5]; + NvU32 SetTexHeaderExtendedDimensions; + NvU32 Reserved_0x2E4[0x9]; + NvU32 SetL1Configuration; + NvU32 SetRenderEnableControl; + NvU32 Reserved_0x310[0x14]; + NvU32 WaitRefCount; + NvU32 Reserved_0x364[0x1]; + NvU32 Launch; + NvU32 SetLaunchId; + NvU32 Reserved_0x370[0xF]; + NvU32 SetCtaThreadDimensionA; + NvU32 SetCtaThreadDimensionB; + NvU32 SetCtaProgramStart; + NvU32 Reserved_0x3B8[0x52]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x76]; + NvU32 SetMaxSmCount; + NvU32 Reserved_0x75C[0x8]; + NvU32 SetShaderLocalMemoryWindow; + NvU32 SetGridParam; + NvU32 Reserved_0x784[0x3]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 SetShaderLocalMemoryC; + NvU32 SetShaderLocalMemoryD; + NvU32 SetShaderLocalMemoryE; + NvU32 Reserved_0x7A4[0x98]; + NvU32 EndGrid; + NvU32 SetLaunchSize; + NvU32 Reserved_0xA0C[0xD6]; + NvU32 SetApiVisibleCallLimit; + NvU32 Reserved_0xD68[0xB]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x57]; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; + NvU32 Reserved_0xF54[0x2C]; + NvU32 SetForceOneTextureUnit; + NvU32 Reserved_0x1008[0xE]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 Reserved_0x1070[0x21]; + NvU32 UnbindAll; + NvU32 Reserved_0x10F8[0x4F]; + NvU32 SetSamplerBinding; + NvU32 Reserved_0x1238[0x14]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x8]; + NvU32 SetShaderScheduling; + NvU32 Reserved_0x12B0[0x20]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x6]; + NvU32 SetGlobalColorKey; + NvU32 Reserved_0x1358[0x33]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x3F]; + NvU32 PerfmonTransfer; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x22]; + NvU32 SetProgramRegionA; + NvU32 SetProgramRegionB; + NvU32 Reserved_0x1610[0x15]; + NvU32 SetCubemapInterFaceFiltering; + NvU32 Reserved_0x1668[0xA]; + NvU32 SetShaderControl; + NvU32 BindConstantBuffer; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xA5]; + NvU32 InvalidateConstantBufferCache; + NvU32 Reserved_0x1934[0x4]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A24[0x1]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x21C]; + NvU32 SetConstantBufferSelectorA; + NvU32 SetConstantBufferSelectorB; + NvU32 SetConstantBufferSelectorC; + NvU32 LoadConstantBufferOffset; + NvU32 LoadConstantBuffer[0x10]; + NvU32 Reserved_0x23D0[0xCC]; + struct { + NvU32 A; + NvU32 B; + NvU32 C; + NvU32 D; + NvU32 Format; + NvU32 BlockSize; + NvU32 Reserved_0x18[0x2]; + } SetSuLdStTarget[0x8]; + NvU32 Reserved_0x2800[0x2D7]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 Reserved_0x33E0[0x8]; + NvU32 SetMmeShadowScratch[0x80]; + NvU32 Reserved_0x3600[0x80]; + struct { + NvU32 Macro; + NvU32 Data; + } CallMme[0x80]; +} fermi_compute_b_t; + + +#define NV91C0_SET_OBJECT 0x0000 +#define NV91C0_SET_OBJECT_CLASS_ID 15:0 +#define NV91C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NV91C0_NO_OPERATION 0x0100 +#define NV91C0_NO_OPERATION_V 31:0 + +#define NV91C0_SET_NOTIFY_A 0x0104 +#define NV91C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NV91C0_SET_NOTIFY_B 0x0108 +#define NV91C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NV91C0_NOTIFY 0x010c +#define NV91C0_NOTIFY_TYPE 31:0 +#define NV91C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NV91C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NV91C0_WAIT_FOR_IDLE 0x0110 +#define NV91C0_WAIT_FOR_IDLE_V 31:0 + +#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER 0x0114 +#define NV91C0_LOAD_MME_INSTRUCTION_RAM_POINTER_V 31:0 + +#define NV91C0_LOAD_MME_INSTRUCTION_RAM 0x0118 +#define NV91C0_LOAD_MME_INSTRUCTION_RAM_V 31:0 + +#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER 0x011c +#define NV91C0_LOAD_MME_START_ADDRESS_RAM_POINTER_V 31:0 + +#define NV91C0_LOAD_MME_START_ADDRESS_RAM 0x0120 +#define NV91C0_LOAD_MME_START_ADDRESS_RAM_V 31:0 + +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL 0x0124 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE 1:0 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK 0x00000000 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_TRACK_WITH_FILTER 0x00000001 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_PASSTHROUGH 0x00000002 +#define NV91C0_SET_MME_SHADOW_RAM_CONTROL_MODE_METHOD_REPLAY 0x00000003 + +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV91C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV91C0_SEND_GO_IDLE 0x013c +#define NV91C0_SEND_GO_IDLE_V 31:0 + +#define NV91C0_PM_TRIGGER 0x0140 +#define NV91C0_PM_TRIGGER_V 31:0 + +#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NV91C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NV91C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE 0x0204 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_LOW_SIZE_V 23:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE 0x0208 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_HIGH_SIZE_V 23:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE 0x020c +#define NV91C0_SET_SHADER_LOCAL_MEMORY_CRS_SIZE_V 20:0 + +#define NV91C0_SET_BINDING_CONTROL_TEXTURE 0x0210 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS 3:0 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__1 0x00000000 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__2 0x00000001 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__4 0x00000002 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__8 0x00000003 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_SAMPLERS__16 0x00000004 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS 7:4 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__1 0x00000000 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__2 0x00000001 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__4 0x00000002 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__8 0x00000003 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__16 0x00000004 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__32 0x00000005 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__64 0x00000006 +#define NV91C0_SET_BINDING_CONTROL_TEXTURE_MAX_ACTIVE_HEADERS__128 0x00000007 + +#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NV91C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV91C0_INVALIDATE_SHADER_CACHES 0x021c +#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM 8:8 +#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_UNIFORM_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NV91C0_BIND_TEXTURE_SAMPLER 0x0228 +#define NV91C0_BIND_TEXTURE_SAMPLER_VALID 0:0 +#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV91C0_BIND_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV91C0_BIND_TEXTURE_HEADER 0x022c +#define NV91C0_BIND_TEXTURE_HEADER_VALID 0:0 +#define NV91C0_BIND_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV91C0_BIND_TEXTURE_HEADER_INDEX 30:9 + +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER 0x0230 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID 0:0 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_SAMPLER_SLOT 11:4 +#define NV91C0_BIND_EXTRA_TEXTURE_SAMPLER_INDEX 24:12 + +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER 0x0234 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID 0:0 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_TEXTURE_SLOT 8:1 +#define NV91C0_BIND_EXTRA_TEXTURE_HEADER_INDEX 30:9 + +#define NV91C0_SET_CTA_RASTER_SIZE_A 0x0238 +#define NV91C0_SET_CTA_RASTER_SIZE_A_WIDTH 15:0 +#define NV91C0_SET_CTA_RASTER_SIZE_A_HEIGHT 31:16 + +#define NV91C0_SET_CTA_RASTER_SIZE_B 0x023c +#define NV91C0_SET_CTA_RASTER_SIZE_B_DEPTH 15:0 +#define NV91C0_SET_CTA_RASTER_SIZE_B_WIDTH_UPPER 31:16 + +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE 0x024c +#define NV91C0_SET_SHADER_SHARED_MEMORY_SIZE_V 17:0 + +#define NV91C0_SET_CTA_THREAD_COUNT 0x0250 +#define NV91C0_SET_CTA_THREAD_COUNT_V 15:0 + +#define NV91C0_SET_CTA_BARRIER_COUNT 0x0254 +#define NV91C0_SET_CTA_BARRIER_COUNT_V 7:0 + +#define NV91C0_TEST_FOR_COMPUTE 0x028c +#define NV91C0_TEST_FOR_COMPUTE_V 31:0 + +#define NV91C0_BEGIN_GRID 0x029c +#define NV91C0_BEGIN_GRID_V 0:0 + +#define NV91C0_SET_WORK_DISTRIBUTION 0x02a0 +#define NV91C0_SET_WORK_DISTRIBUTION_MAX_BATCH_SIZE 16:13 +#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE 4:4 +#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_FALSE 0x00000000 +#define NV91C0_SET_WORK_DISTRIBUTION_FIXED_MODE_TRUE 0x00000001 +#define NV91C0_SET_WORK_DISTRIBUTION_MAX_STANDBY_CTAS 12:5 + +#define NV91C0_SET_CTA_REGISTER_COUNT 0x02c0 +#define NV91C0_SET_CTA_REGISTER_COUNT_V 7:0 + +#define NV91C0_SET_GA_TO_VA_MAPPING_MODE 0x02c4 +#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V 0:0 +#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_DISABLE 0x00000000 +#define NV91C0_SET_GA_TO_VA_MAPPING_MODE_V_ENABLE 0x00000001 + +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY 0x02c8 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_VIRTUAL_ADDRESS_UPPER 7:0 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_GENERIC_ADDRESS_UPPER 23:16 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE 30:30 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_FALSE 0x00000000 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_READ_ENABLE_TRUE 0x00000001 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE 31:31 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_FALSE 0x00000000 +#define NV91C0_LOAD_GA_TO_VA_MAPPING_ENTRY_WRITE_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS 0x02e0 +#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE 0:0 +#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_TEX_HEADER_EXTENDED_DIMENSIONS_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_L1_CONFIGURATION 0x0308 +#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY 2:0 +#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NV91C0_SET_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 + +#define NV91C0_SET_RENDER_ENABLE_CONTROL 0x030c +#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER 0:0 +#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_FALSE 0x00000000 +#define NV91C0_SET_RENDER_ENABLE_CONTROL_CONDITIONAL_LOAD_CONSTANT_BUFFER_TRUE 0x00000001 + +#define NV91C0_WAIT_REF_COUNT 0x0360 +#define NV91C0_WAIT_REF_COUNT_REF_CNT 11:8 +#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM 0:0 +#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_FALSE 0x00000000 +#define NV91C0_WAIT_REF_COUNT_FLUSH_SYS_MEM_TRUE 0x00000001 + +#define NV91C0_LAUNCH 0x0368 +#define NV91C0_LAUNCHCTA_PARAM 31:0 + +#define NV91C0_SET_LAUNCH_ID 0x036c +#define NV91C0_SET_LAUNCH_ID_REF_CNT 3:0 + +#define NV91C0_SET_CTA_THREAD_DIMENSION_A 0x03ac +#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D0 15:0 +#define NV91C0_SET_CTA_THREAD_DIMENSION_A_D1 31:16 + +#define NV91C0_SET_CTA_THREAD_DIMENSION_B 0x03b0 +#define NV91C0_SET_CTA_THREAD_DIMENSION_B_D2 15:0 + +#define NV91C0_SET_CTA_PROGRAM_START 0x03b4 +#define NV91C0_SET_CTA_PROGRAM_START_OFFSET 31:0 + +#define NV91C0_SET_FALCON00 0x0500 +#define NV91C0_SET_FALCON00_V 31:0 + +#define NV91C0_SET_FALCON01 0x0504 +#define NV91C0_SET_FALCON01_V 31:0 + +#define NV91C0_SET_FALCON02 0x0508 +#define NV91C0_SET_FALCON02_V 31:0 + +#define NV91C0_SET_FALCON03 0x050c +#define NV91C0_SET_FALCON03_V 31:0 + +#define NV91C0_SET_FALCON04 0x0510 +#define NV91C0_SET_FALCON04_V 31:0 + +#define NV91C0_SET_FALCON05 0x0514 +#define NV91C0_SET_FALCON05_V 31:0 + +#define NV91C0_SET_FALCON06 0x0518 +#define NV91C0_SET_FALCON06_V 31:0 + +#define NV91C0_SET_FALCON07 0x051c +#define NV91C0_SET_FALCON07_V 31:0 + +#define NV91C0_SET_FALCON08 0x0520 +#define NV91C0_SET_FALCON08_V 31:0 + +#define NV91C0_SET_FALCON09 0x0524 +#define NV91C0_SET_FALCON09_V 31:0 + +#define NV91C0_SET_FALCON10 0x0528 +#define NV91C0_SET_FALCON10_V 31:0 + +#define NV91C0_SET_FALCON11 0x052c +#define NV91C0_SET_FALCON11_V 31:0 + +#define NV91C0_SET_FALCON12 0x0530 +#define NV91C0_SET_FALCON12_V 31:0 + +#define NV91C0_SET_FALCON13 0x0534 +#define NV91C0_SET_FALCON13_V 31:0 + +#define NV91C0_SET_FALCON14 0x0538 +#define NV91C0_SET_FALCON14_V 31:0 + +#define NV91C0_SET_FALCON15 0x053c +#define NV91C0_SET_FALCON15_V 31:0 + +#define NV91C0_SET_FALCON16 0x0540 +#define NV91C0_SET_FALCON16_V 31:0 + +#define NV91C0_SET_FALCON17 0x0544 +#define NV91C0_SET_FALCON17_V 31:0 + +#define NV91C0_SET_FALCON18 0x0548 +#define NV91C0_SET_FALCON18_V 31:0 + +#define NV91C0_SET_FALCON19 0x054c +#define NV91C0_SET_FALCON19_V 31:0 + +#define NV91C0_SET_FALCON20 0x0550 +#define NV91C0_SET_FALCON20_V 31:0 + +#define NV91C0_SET_FALCON21 0x0554 +#define NV91C0_SET_FALCON21_V 31:0 + +#define NV91C0_SET_FALCON22 0x0558 +#define NV91C0_SET_FALCON22_V 31:0 + +#define NV91C0_SET_FALCON23 0x055c +#define NV91C0_SET_FALCON23_V 31:0 + +#define NV91C0_SET_FALCON24 0x0560 +#define NV91C0_SET_FALCON24_V 31:0 + +#define NV91C0_SET_FALCON25 0x0564 +#define NV91C0_SET_FALCON25_V 31:0 + +#define NV91C0_SET_FALCON26 0x0568 +#define NV91C0_SET_FALCON26_V 31:0 + +#define NV91C0_SET_FALCON27 0x056c +#define NV91C0_SET_FALCON27_V 31:0 + +#define NV91C0_SET_FALCON28 0x0570 +#define NV91C0_SET_FALCON28_V 31:0 + +#define NV91C0_SET_FALCON29 0x0574 +#define NV91C0_SET_FALCON29_V 31:0 + +#define NV91C0_SET_FALCON30 0x0578 +#define NV91C0_SET_FALCON30_V 31:0 + +#define NV91C0_SET_FALCON31 0x057c +#define NV91C0_SET_FALCON31_V 31:0 + +#define NV91C0_SET_MAX_SM_COUNT 0x0758 +#define NV91C0_SET_MAX_SM_COUNT_V 8:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NV91C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NV91C0_SET_GRID_PARAM 0x0780 +#define NV91C0_SET_GRID_PARAM_V 31:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_C 0x0798 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_C_SIZE_UPPER 5:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_D 0x079c +#define NV91C0_SET_SHADER_LOCAL_MEMORY_D_SIZE_LOWER 31:0 + +#define NV91C0_SET_SHADER_LOCAL_MEMORY_E 0x07a0 +#define NV91C0_SET_SHADER_LOCAL_MEMORY_E_DEFAULT_SIZE_PER_WARP 25:0 + +#define NV91C0_END_GRID 0x0a04 +#define NV91C0_END_GRID_V 0:0 + +#define NV91C0_SET_LAUNCH_SIZE 0x0a08 +#define NV91C0_SET_LAUNCH_SIZE_V 31:0 + +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT 0x0d64 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA 3:0 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__0 0x00000000 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__1 0x00000001 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__2 0x00000002 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__4 0x00000003 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__8 0x00000004 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__16 0x00000005 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__32 0x00000006 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__64 0x00000007 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA__128 0x00000008 +#define NV91C0_SET_API_VISIBLE_CALL_LIMIT_CTA_NO_CHECK 0x0000000F + +#define NV91C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NV91C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NV91C0_SET_SPARE_NOOP12 0x0f44 +#define NV91C0_SET_SPARE_NOOP12_V 31:0 + +#define NV91C0_SET_SPARE_NOOP13 0x0f48 +#define NV91C0_SET_SPARE_NOOP13_V 31:0 + +#define NV91C0_SET_SPARE_NOOP14 0x0f4c +#define NV91C0_SET_SPARE_NOOP14_V 31:0 + +#define NV91C0_SET_SPARE_NOOP15 0x0f50 +#define NV91C0_SET_SPARE_NOOP15_V 31:0 + +#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT 0x1004 +#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE 0:0 +#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_FORCE_ONE_TEXTURE_UNIT_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_SPARE_NOOP00 0x1040 +#define NV91C0_SET_SPARE_NOOP00_V 31:0 + +#define NV91C0_SET_SPARE_NOOP01 0x1044 +#define NV91C0_SET_SPARE_NOOP01_V 31:0 + +#define NV91C0_SET_SPARE_NOOP02 0x1048 +#define NV91C0_SET_SPARE_NOOP02_V 31:0 + +#define NV91C0_SET_SPARE_NOOP03 0x104c +#define NV91C0_SET_SPARE_NOOP03_V 31:0 + +#define NV91C0_SET_SPARE_NOOP04 0x1050 +#define NV91C0_SET_SPARE_NOOP04_V 31:0 + +#define NV91C0_SET_SPARE_NOOP05 0x1054 +#define NV91C0_SET_SPARE_NOOP05_V 31:0 + +#define NV91C0_SET_SPARE_NOOP06 0x1058 +#define NV91C0_SET_SPARE_NOOP06_V 31:0 + +#define NV91C0_SET_SPARE_NOOP07 0x105c +#define NV91C0_SET_SPARE_NOOP07_V 31:0 + +#define NV91C0_SET_SPARE_NOOP08 0x1060 +#define NV91C0_SET_SPARE_NOOP08_V 31:0 + +#define NV91C0_SET_SPARE_NOOP09 0x1064 +#define NV91C0_SET_SPARE_NOOP09_V 31:0 + +#define NV91C0_SET_SPARE_NOOP10 0x1068 +#define NV91C0_SET_SPARE_NOOP10_V 31:0 + +#define NV91C0_SET_SPARE_NOOP11 0x106c +#define NV91C0_SET_SPARE_NOOP11_V 31:0 + +#define NV91C0_UNBIND_ALL 0x10f4 +#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS 0:0 +#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_FALSE 0x00000000 +#define NV91C0_UNBIND_ALL_TEXTURE_HEADERS_TRUE 0x00000001 +#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS 4:4 +#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_FALSE 0x00000000 +#define NV91C0_UNBIND_ALL_TEXTURE_SAMPLERS_TRUE 0x00000001 +#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS 8:8 +#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_FALSE 0x00000000 +#define NV91C0_UNBIND_ALL_CONSTANT_BUFFERS_TRUE 0x00000001 + +#define NV91C0_SET_SAMPLER_BINDING 0x1234 +#define NV91C0_SET_SAMPLER_BINDING_V 0:0 +#define NV91C0_SET_SAMPLER_BINDING_V_INDEPENDENTLY 0x00000000 +#define NV91C0_SET_SAMPLER_BINDING_V_VIA_HEADER_BINDING 0x00000001 + +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NV91C0_SET_SHADER_SCHEDULING 0x12ac +#define NV91C0_SET_SHADER_SCHEDULING_MODE 0:0 +#define NV91C0_SET_SHADER_SCHEDULING_MODE_OLDEST_THREAD_FIRST 0x00000000 +#define NV91C0_SET_SHADER_SCHEDULING_MODE_ROUND_ROBIN 0x00000001 + +#define NV91C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS 2:1 +#define NV91C0_INVALIDATE_TEXTURE_DATA_CACHE_LEVELS_L1_ONLY 0x00000000 + +#define NV91C0_SET_GLOBAL_COLOR_KEY 0x1354 +#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE 0:0 +#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_GLOBAL_COLOR_KEY_ENABLE_TRUE 0x00000001 + +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NV91C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NV91C0_PERFMON_TRANSFER 0x1524 +#define NV91C0_PERFMON_TRANSFER_V 31:0 + +#define NV91C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NV91C0_SET_RENDER_ENABLE_A 0x1550 +#define NV91C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_RENDER_ENABLE_B 0x1554 +#define NV91C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_RENDER_ENABLE_C 0x1558 +#define NV91C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NV91C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NV91C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NV91C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NV91C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NV91C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NV91C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NV91C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NV91C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_TEX_HEADER_POOL_C 0x157c +#define NV91C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NV91C0_SET_PROGRAM_REGION_A 0x1608 +#define NV91C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NV91C0_SET_PROGRAM_REGION_B 0x160c +#define NV91C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING 0x1664 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE 1:0 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_USE_WRAP 0x00000000 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_OVERRIDE_WRAP 0x00000001 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_SPAN_SEAM 0x00000002 +#define NV91C0_SET_CUBEMAP_INTER_FACE_FILTERING_MODE_AUTO_CROSS_SEAM 0x00000003 + +#define NV91C0_SET_SHADER_CONTROL 0x1690 +#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NV91C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 +#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO 16:16 +#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_FALSE 0x00000000 +#define NV91C0_SET_SHADER_CONTROL_ZERO_TIMES_ANYTHING_IS_ZERO_TRUE 0x00000001 +#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR 1:1 +#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NV91C0_SET_SHADER_CONTROL_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR 2:2 +#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NV91C0_SET_SHADER_CONTROL_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 + +#define NV91C0_BIND_CONSTANT_BUFFER 0x1694 +#define NV91C0_BIND_CONSTANT_BUFFER_VALID 0:0 +#define NV91C0_BIND_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NV91C0_BIND_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NV91C0_BIND_CONSTANT_BUFFER_SHADER_SLOT 12:8 + +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM 8:8 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_UNIFORM_TRUE 0x00000001 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NV91C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE 0x1930 +#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2 0:0 +#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_FALSE 0x00000000 +#define NV91C0_INVALIDATE_CONSTANT_BUFFER_CACHE_THRU_L2_TRUE 0x00000001 + +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NV91C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NV91C0_PIPE_NOP 0x1a2c +#define NV91C0_PIPE_NOP_V 31:0 + +#define NV91C0_SET_SPARE00 0x1a30 +#define NV91C0_SET_SPARE00_V 31:0 + +#define NV91C0_SET_SPARE01 0x1a34 +#define NV91C0_SET_SPARE01_V 31:0 + +#define NV91C0_SET_SPARE02 0x1a38 +#define NV91C0_SET_SPARE02_V 31:0 + +#define NV91C0_SET_SPARE03 0x1a3c +#define NV91C0_SET_SPARE03_V 31:0 + +#define NV91C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NV91C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NV91C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NV91C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NV91C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NV91C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NV91C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NV91C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NV91C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 + +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A 0x2380 +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_A_SIZE 16:0 + +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B 0x2384 +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_B_ADDRESS_UPPER 7:0 + +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C 0x2388 +#define NV91C0_SET_CONSTANT_BUFFER_SELECTOR_C_ADDRESS_LOWER 31:0 + +#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET 0x238c +#define NV91C0_LOAD_CONSTANT_BUFFER_OFFSET_V 15:0 + +#define NV91C0_LOAD_CONSTANT_BUFFER(i) (0x2390+(i)*4) +#define NV91C0_LOAD_CONSTANT_BUFFER_V 31:0 + +#define NV91C0_SET_SU_LD_ST_TARGET_A(j) (0x2700+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_A_OFFSET_UPPER 7:0 + +#define NV91C0_SET_SU_LD_ST_TARGET_B(j) (0x2704+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_B_OFFSET_LOWER 31:0 + +#define NV91C0_SET_SU_LD_ST_TARGET_C(j) (0x2708+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_C_WIDTH 31:0 + +#define NV91C0_SET_SU_LD_ST_TARGET_D(j) (0x270c+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_D_HEIGHT 16:0 +#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY 20:20 +#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_BLOCKLINEAR 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_D_LAYOUT_IN_MEMORY_PITCH 0x00000001 + +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT(j) (0x2710+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE 0:0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_COLOR 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_TYPE_ZETA 0x00000001 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR 11:4 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_DISABLED 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_AF32 0x000000C0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_AS32 0x000000C1 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_AU32 0x000000C2 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32_BF32_X32 0x000000C3 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32_BS32_X32 0x000000C4 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32_BU32_X32 0x000000C5 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16_B16_A16 0x000000C6 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16_BN16_AN16 0x000000C7 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16_BS16_AS16 0x000000C8 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16_BU16_AU16 0x000000C9 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_AF16 0x000000CA +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_GF32 0x000000CB +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32_GS32 0x000000CC +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32_GU32 0x000000CD +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16_BF16_X16 0x000000CE +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8G8B8 0x000000CF +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8RL8GL8BL8 0x000000D0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2B10G10R10 0x000000D1 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU2BU10GU10RU10 0x000000D2 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8B8G8R8 0x000000D5 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8BL8GL8RL8 0x000000D6 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AN8BN8GN8RN8 0x000000D7 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AS8BS8GS8RS8 0x000000D8 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AU8BU8GU8RU8 0x000000D9 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_G16 0x000000DA +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16_GN16 0x000000DB +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16_GS16 0x000000DC +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16_GU16 0x000000DD +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_GF16 0x000000DE +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A2R10G10B10 0x000000DF +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_BF10GF11RF11 0x000000E0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS32 0x000000E3 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU32 0x000000E4 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32 0x000000E5 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8R8G8B8 0x000000E6 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8RL8GL8BL8 0x000000E7 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R5G6B5 0x000000E8 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A1R5G5B5 0x000000E9 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_G8R8 0x000000EA +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GN8RN8 0x000000EB +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GS8RS8 0x000000EC +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_GU8RU8 0x000000ED +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16 0x000000EE +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN16 0x000000EF +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS16 0x000000F0 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU16 0x000000F1 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16 0x000000F2 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R8 0x000000F3 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RN8 0x000000F4 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RS8 0x000000F5 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RU8 0x000000F6 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8 0x000000F7 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X1R5G5B5 0x000000F8 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8B8G8R8 0x000000F9 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_X8BL8GL8RL8 0x000000FA +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z1R5G5B5 0x000000FB +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O1R5G5B5 0x000000FC +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_Z8R8G8B8 0x000000FD +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_O8R8G8B8 0x000000FE +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R32 0x000000FF +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A16 0x00000040 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF16 0x00000041 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_AF32 0x00000042 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_A8R8 0x00000043 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_R16_A16 0x00000044 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF16_AF16 0x00000045 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_RF32_AF32 0x00000046 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_COLOR_B8G8R8A8 0x00000047 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA 16:12 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z16 0x00000013 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_Z24S8 0x00000014 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24 0x00000015 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_S8Z24 0x00000016 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_V8Z24 0x00000018 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32 0x0000000A +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X24S8 0x00000019 +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_X8Z24_X16V8S8 0x0000001D +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8X8 0x0000001E +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_ZETA_ZF32_X16V8S8 0x0000001F +#define NV91C0_SET_SU_LD_ST_TARGET_FORMAT_SUQ_PIXFMT 25:17 + +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE(j) (0x2714+(j)*32) +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH 3:0 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT 7:4 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NV91C0_SET_SU_LD_ST_TARGET_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 2:0 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 6:4 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 10:8 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 14:12 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 18:16 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 22:20 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 26:24 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 30:28 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NV91C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NV91C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NV91C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#define NV91C0_CALL_MME_MACRO(j) (0x3800+(j)*8) +#define NV91C0_CALL_MME_MACRO_V 31:0 + +#define NV91C0_CALL_MME_DATA(j) (0x3804+(j)*8) +#define NV91C0_CALL_MME_DATA_V 31:0 + +#endif /* _cl_fermi_compute_b_h_ */ diff --git a/Compute-Class-Methods/cla0c0.h b/Compute-Class-Methods/cla0c0.h new file mode 100644 index 0000000..e8677ad --- /dev/null +++ b/Compute-Class-Methods/cla0c0.h @@ -0,0 +1,836 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_a_h_ +#define _cl_kepler_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_a */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_A 0xA0C0 + +typedef volatile struct _cla0c0_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0x7]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 PmTriggerWfi; + NvU32 Reserved_0x148[0x2]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0xA]; + NvU32 LineLengthIn; + NvU32 LineCount; + NvU32 OffsetOutUpper; + NvU32 OffsetOut; + NvU32 PitchOut; + NvU32 SetDstBlockSize; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstOriginBytesX; + NvU32 SetDstOriginSamplesY; + NvU32 LaunchDma; + NvU32 LoadInlineData; + NvU32 Reserved_0x1B8[0x9]; + NvU32 SetI2mSemaphoreA; + NvU32 SetI2mSemaphoreB; + NvU32 SetI2mSemaphoreC; + NvU32 Reserved_0x1E8[0x2]; + NvU32 SetI2mSpareNoop00; + NvU32 SetI2mSpareNoop01; + NvU32 SetI2mSpareNoop02; + NvU32 SetI2mSpareNoop03; + NvU32 Reserved_0x200[0x4]; + NvU32 PerfmonTransfer; + NvU32 SetShaderSharedMemoryWindow; + NvU32 Reserved_0x218[0x1]; + NvU32 InvalidateShaderCaches; + NvU32 Reserved_0x220[0x8]; + NvU32 SetCwdControl; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 SetCwdRefCounter; + NvU32 Reserved_0x24C[0xA]; + NvU32 InvalidateConstantBufferCacheA; + NvU32 InvalidateConstantBufferCacheB; + NvU32 InvalidateConstantBufferCacheC; + NvU32 SetComputeClassVersion; + NvU32 CheckComputeClassVersion; + NvU32 SetQmdVersion; + NvU32 Reserved_0x28C[0x1]; + NvU32 CheckQmdVersion; + NvU32 Reserved_0x294[0x7]; + NvU32 SetCwdSlotCount; + NvU32 SendPcasA; + NvU32 SendPcasB; + NvU32 SendSignalingPcasB; + NvU32 Reserved_0x2C0[0x9]; + NvU32 SetShaderLocalMemoryNonThrottledA; + NvU32 SetShaderLocalMemoryNonThrottledB; + NvU32 SetShaderLocalMemoryNonThrottledC; + NvU32 SetShaderLocalMemoryThrottledA; + NvU32 SetShaderLocalMemoryThrottledB; + NvU32 SetShaderLocalMemoryThrottledC; + NvU32 Reserved_0x2FC[0x5]; + NvU32 SetSpaVersion; + NvU32 Reserved_0x314[0x7B]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x7F]; + NvU32 SetShaderLocalMemoryWindow; + NvU32 Reserved_0x780[0x4]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 Reserved_0x798[0x17F]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x57]; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; + NvU32 Reserved_0xF54[0x3B]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 Reserved_0x1070[0x86]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x29]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x3A]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x40]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x22]; + NvU32 SetProgramRegionA; + NvU32 SetProgramRegionB; + NvU32 Reserved_0x1610[0x20]; + NvU32 SetShaderControl; + NvU32 Reserved_0x1694[0x1]; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xAA]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A24[0x1]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x2BE]; + NvU32 SetBindlessTexture; + NvU32 SetTrapHandler; + NvU32 Reserved_0x2610[0x353]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 Reserved_0x33E0[0x8]; + NvU32 SetMmeShadowScratch[0x8]; +} kepler_compute_a_t; + + +#define NVA0C0_SET_OBJECT 0x0000 +#define NVA0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA0C0_NO_OPERATION 0x0100 +#define NVA0C0_NO_OPERATION_V 31:0 + +#define NVA0C0_SET_NOTIFY_A 0x0104 +#define NVA0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_NOTIFY_B 0x0108 +#define NVA0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_NOTIFY 0x010c +#define NVA0C0_NOTIFY_TYPE 31:0 +#define NVA0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA0C0_WAIT_FOR_IDLE 0x0110 +#define NVA0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SEND_GO_IDLE 0x013c +#define NVA0C0_SEND_GO_IDLE_V 31:0 + +#define NVA0C0_PM_TRIGGER 0x0140 +#define NVA0C0_PM_TRIGGER_V 31:0 + +#define NVA0C0_PM_TRIGGER_WFI 0x0144 +#define NVA0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA0C0_LINE_LENGTH_IN 0x0180 +#define NVA0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA0C0_LINE_COUNT 0x0184 +#define NVA0C0_LINE_COUNT_VALUE 31:0 + +#define NVA0C0_OFFSET_OUT_UPPER 0x0188 +#define NVA0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA0C0_OFFSET_OUT 0x018c +#define NVA0C0_OFFSET_OUT_VALUE 31:0 + +#define NVA0C0_PITCH_OUT 0x0190 +#define NVA0C0_PITCH_OUT_VALUE 31:0 + +#define NVA0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA0C0_SET_DST_WIDTH 0x0198 +#define NVA0C0_SET_DST_WIDTH_V 31:0 + +#define NVA0C0_SET_DST_HEIGHT 0x019c +#define NVA0C0_SET_DST_HEIGHT_V 31:0 + +#define NVA0C0_SET_DST_DEPTH 0x01a0 +#define NVA0C0_SET_DST_DEPTH_V 31:0 + +#define NVA0C0_SET_DST_LAYER 0x01a4 +#define NVA0C0_SET_DST_LAYER_V 31:0 + +#define NVA0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA0C0_LAUNCH_DMA 0x01b0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA0C0_LOAD_INLINE_DATA 0x01b4 +#define NVA0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA0C0_PERFMON_TRANSFER 0x0210 +#define NVA0C0_PERFMON_TRANSFER_V 31:0 + +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA0C0_SET_CWD_CONTROL 0x0240 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_QMD_VERSION 0x0288 +#define NVA0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_CHECK_QMD_VERSION 0x0290 +#define NVA0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA0C0_SEND_PCAS_A 0x02b4 +#define NVA0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA0C0_SEND_PCAS_B 0x02b8 +#define NVA0C0_SEND_PCAS_B_FROM 23:0 +#define NVA0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA0C0_SET_SPA_VERSION 0x0310 +#define NVA0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA0C0_SET_FALCON00 0x0500 +#define NVA0C0_SET_FALCON00_V 31:0 + +#define NVA0C0_SET_FALCON01 0x0504 +#define NVA0C0_SET_FALCON01_V 31:0 + +#define NVA0C0_SET_FALCON02 0x0508 +#define NVA0C0_SET_FALCON02_V 31:0 + +#define NVA0C0_SET_FALCON03 0x050c +#define NVA0C0_SET_FALCON03_V 31:0 + +#define NVA0C0_SET_FALCON04 0x0510 +#define NVA0C0_SET_FALCON04_V 31:0 + +#define NVA0C0_SET_FALCON05 0x0514 +#define NVA0C0_SET_FALCON05_V 31:0 + +#define NVA0C0_SET_FALCON06 0x0518 +#define NVA0C0_SET_FALCON06_V 31:0 + +#define NVA0C0_SET_FALCON07 0x051c +#define NVA0C0_SET_FALCON07_V 31:0 + +#define NVA0C0_SET_FALCON08 0x0520 +#define NVA0C0_SET_FALCON08_V 31:0 + +#define NVA0C0_SET_FALCON09 0x0524 +#define NVA0C0_SET_FALCON09_V 31:0 + +#define NVA0C0_SET_FALCON10 0x0528 +#define NVA0C0_SET_FALCON10_V 31:0 + +#define NVA0C0_SET_FALCON11 0x052c +#define NVA0C0_SET_FALCON11_V 31:0 + +#define NVA0C0_SET_FALCON12 0x0530 +#define NVA0C0_SET_FALCON12_V 31:0 + +#define NVA0C0_SET_FALCON13 0x0534 +#define NVA0C0_SET_FALCON13_V 31:0 + +#define NVA0C0_SET_FALCON14 0x0538 +#define NVA0C0_SET_FALCON14_V 31:0 + +#define NVA0C0_SET_FALCON15 0x053c +#define NVA0C0_SET_FALCON15_V 31:0 + +#define NVA0C0_SET_FALCON16 0x0540 +#define NVA0C0_SET_FALCON16_V 31:0 + +#define NVA0C0_SET_FALCON17 0x0544 +#define NVA0C0_SET_FALCON17_V 31:0 + +#define NVA0C0_SET_FALCON18 0x0548 +#define NVA0C0_SET_FALCON18_V 31:0 + +#define NVA0C0_SET_FALCON19 0x054c +#define NVA0C0_SET_FALCON19_V 31:0 + +#define NVA0C0_SET_FALCON20 0x0550 +#define NVA0C0_SET_FALCON20_V 31:0 + +#define NVA0C0_SET_FALCON21 0x0554 +#define NVA0C0_SET_FALCON21_V 31:0 + +#define NVA0C0_SET_FALCON22 0x0558 +#define NVA0C0_SET_FALCON22_V 31:0 + +#define NVA0C0_SET_FALCON23 0x055c +#define NVA0C0_SET_FALCON23_V 31:0 + +#define NVA0C0_SET_FALCON24 0x0560 +#define NVA0C0_SET_FALCON24_V 31:0 + +#define NVA0C0_SET_FALCON25 0x0564 +#define NVA0C0_SET_FALCON25_V 31:0 + +#define NVA0C0_SET_FALCON26 0x0568 +#define NVA0C0_SET_FALCON26_V 31:0 + +#define NVA0C0_SET_FALCON27 0x056c +#define NVA0C0_SET_FALCON27_V 31:0 + +#define NVA0C0_SET_FALCON28 0x0570 +#define NVA0C0_SET_FALCON28_V 31:0 + +#define NVA0C0_SET_FALCON29 0x0574 +#define NVA0C0_SET_FALCON29_V 31:0 + +#define NVA0C0_SET_FALCON30 0x0578 +#define NVA0C0_SET_FALCON30_V 31:0 + +#define NVA0C0_SET_FALCON31 0x057c +#define NVA0C0_SET_FALCON31_V 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA0C0_SET_SPARE_NOOP12 0x0f44 +#define NVA0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP13 0x0f48 +#define NVA0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP14 0x0f4c +#define NVA0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP15 0x0f50 +#define NVA0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP00 0x1040 +#define NVA0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP01 0x1044 +#define NVA0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP02 0x1048 +#define NVA0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP03 0x104c +#define NVA0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP04 0x1050 +#define NVA0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP05 0x1054 +#define NVA0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP06 0x1058 +#define NVA0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP07 0x105c +#define NVA0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP08 0x1060 +#define NVA0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP09 0x1064 +#define NVA0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP10 0x1068 +#define NVA0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA0C0_SET_SPARE_NOOP11 0x106c +#define NVA0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA0C0_SET_PROGRAM_REGION_B 0x160c +#define NVA0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA0C0_SET_SHADER_CONTROL 0x1690 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA0C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA0C0_PIPE_NOP 0x1a2c +#define NVA0C0_PIPE_NOP_V 31:0 + +#define NVA0C0_SET_SPARE00 0x1a30 +#define NVA0C0_SET_SPARE00_V 31:0 + +#define NVA0C0_SET_SPARE01 0x1a34 +#define NVA0C0_SET_SPARE01_V 31:0 + +#define NVA0C0_SET_SPARE02 0x1a38 +#define NVA0C0_SET_SPARE02_V 31:0 + +#define NVA0C0_SET_SPARE03 0x1a3c +#define NVA0C0_SET_SPARE03_V 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA0C0_SET_TRAP_HANDLER 0x260c +#define NVA0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_a_h_ */ diff --git a/Compute-Class-Methods/cla1c0.h b/Compute-Class-Methods/cla1c0.h new file mode 100644 index 0000000..37462b1 --- /dev/null +++ b/Compute-Class-Methods/cla1c0.h @@ -0,0 +1,866 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_kepler_compute_b_h_ +#define _cl_kepler_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../class/bin/sw_header.pl kepler_compute_b */ + +#include "nvtypes.h" + +#define KEPLER_COMPUTE_B 0xA1C0 + +typedef volatile struct _cla1c0_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0x7]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 PmTriggerWfi; + NvU32 Reserved_0x148[0x2]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0xA]; + NvU32 LineLengthIn; + NvU32 LineCount; + NvU32 OffsetOutUpper; + NvU32 OffsetOut; + NvU32 PitchOut; + NvU32 SetDstBlockSize; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstOriginBytesX; + NvU32 SetDstOriginSamplesY; + NvU32 LaunchDma; + NvU32 LoadInlineData; + NvU32 Reserved_0x1B8[0x9]; + NvU32 SetI2mSemaphoreA; + NvU32 SetI2mSemaphoreB; + NvU32 SetI2mSemaphoreC; + NvU32 Reserved_0x1E8[0x2]; + NvU32 SetI2mSpareNoop00; + NvU32 SetI2mSpareNoop01; + NvU32 SetI2mSpareNoop02; + NvU32 SetI2mSpareNoop03; + NvU32 SetValidSpanOverflowAreaA; + NvU32 SetValidSpanOverflowAreaB; + NvU32 SetValidSpanOverflowAreaC; + NvU32 SetCoalesceWaitingPeriodUnit; + NvU32 PerfmonTransfer; + NvU32 SetShaderSharedMemoryWindow; + NvU32 Reserved_0x218[0x1]; + NvU32 InvalidateShaderCaches; + NvU32 Reserved_0x220[0x8]; + NvU32 SetCwdControl; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 SetCwdRefCounter; + NvU32 Reserved_0x24C[0xA]; + NvU32 InvalidateConstantBufferCacheA; + NvU32 InvalidateConstantBufferCacheB; + NvU32 InvalidateConstantBufferCacheC; + NvU32 SetComputeClassVersion; + NvU32 CheckComputeClassVersion; + NvU32 SetQmdVersion; + NvU32 Reserved_0x28C[0x1]; + NvU32 CheckQmdVersion; + NvU32 Reserved_0x294[0x7]; + NvU32 SetCwdSlotCount; + NvU32 SendPcasA; + NvU32 SendPcasB; + NvU32 SendSignalingPcasB; + NvU32 Reserved_0x2C0[0x1]; + NvU32 SetGlobalLoadViaTexture; + NvU32 Reserved_0x2C8[0x7]; + NvU32 SetShaderLocalMemoryNonThrottledA; + NvU32 SetShaderLocalMemoryNonThrottledB; + NvU32 SetShaderLocalMemoryNonThrottledC; + NvU32 SetShaderLocalMemoryThrottledA; + NvU32 SetShaderLocalMemoryThrottledB; + NvU32 SetShaderLocalMemoryThrottledC; + NvU32 Reserved_0x2FC[0x5]; + NvU32 SetSpaVersion; + NvU32 Reserved_0x314[0x7B]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x7F]; + NvU32 SetShaderLocalMemoryWindow; + NvU32 Reserved_0x780[0x4]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 Reserved_0x798[0x17F]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x57]; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; + NvU32 Reserved_0xF54[0x3B]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 Reserved_0x1070[0x86]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x7]; + NvU32 ActivatePerfSettingsForComputeContext; + NvU32 Reserved_0x12AC[0x21]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x3A]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x40]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x22]; + NvU32 SetProgramRegionA; + NvU32 SetProgramRegionB; + NvU32 Reserved_0x1610[0x20]; + NvU32 SetShaderControl; + NvU32 Reserved_0x1694[0x1]; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xAA]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A24[0x1]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x2BE]; + NvU32 SetBindlessTexture; + NvU32 SetTrapHandler; + NvU32 Reserved_0x2610[0x353]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 Reserved_0x33E0[0x8]; + NvU32 SetMmeShadowScratch[0x8]; +} kepler_compute_b_t; + + +#define NVA1C0_SET_OBJECT 0x0000 +#define NVA1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVA1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVA1C0_NO_OPERATION 0x0100 +#define NVA1C0_NO_OPERATION_V 31:0 + +#define NVA1C0_SET_NOTIFY_A 0x0104 +#define NVA1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_NOTIFY_B 0x0108 +#define NVA1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_NOTIFY 0x010c +#define NVA1C0_NOTIFY_TYPE 31:0 +#define NVA1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVA1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVA1C0_WAIT_FOR_IDLE 0x0110 +#define NVA1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SEND_GO_IDLE 0x013c +#define NVA1C0_SEND_GO_IDLE_V 31:0 + +#define NVA1C0_PM_TRIGGER 0x0140 +#define NVA1C0_PM_TRIGGER_V 31:0 + +#define NVA1C0_PM_TRIGGER_WFI 0x0144 +#define NVA1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVA1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVA1C0_LINE_LENGTH_IN 0x0180 +#define NVA1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVA1C0_LINE_COUNT 0x0184 +#define NVA1C0_LINE_COUNT_VALUE 31:0 + +#define NVA1C0_OFFSET_OUT_UPPER 0x0188 +#define NVA1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVA1C0_OFFSET_OUT 0x018c +#define NVA1C0_OFFSET_OUT_VALUE 31:0 + +#define NVA1C0_PITCH_OUT 0x0190 +#define NVA1C0_PITCH_OUT_VALUE 31:0 + +#define NVA1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVA1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVA1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVA1C0_SET_DST_WIDTH 0x0198 +#define NVA1C0_SET_DST_WIDTH_V 31:0 + +#define NVA1C0_SET_DST_HEIGHT 0x019c +#define NVA1C0_SET_DST_HEIGHT_V 31:0 + +#define NVA1C0_SET_DST_DEPTH 0x01a0 +#define NVA1C0_SET_DST_DEPTH_V 31:0 + +#define NVA1C0_SET_DST_LAYER 0x01a4 +#define NVA1C0_SET_DST_LAYER_V 31:0 + +#define NVA1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVA1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVA1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVA1C0_LAUNCH_DMA 0x01b0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVA1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVA1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVA1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVA1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVA1C0_LOAD_INLINE_DATA 0x01b4 +#define NVA1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVA1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVA1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVA1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVA1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVA1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVA1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVA1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVA1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVA1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVA1C0_PERFMON_TRANSFER 0x0210 +#define NVA1C0_PERFMON_TRANSFER_V 31:0 + +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVA1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVA1C0_SET_CWD_CONTROL 0x0240 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVA1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVA1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVA1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVA1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_QMD_VERSION 0x0288 +#define NVA1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_CHECK_QMD_VERSION 0x0290 +#define NVA1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVA1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVA1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVA1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVA1C0_SEND_PCAS_A 0x02b4 +#define NVA1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVA1C0_SEND_PCAS_B 0x02b8 +#define NVA1C0_SEND_PCAS_B_FROM 23:0 +#define NVA1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVA1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVA1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE 0x02c4 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE 0:0 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_GLOBAL_LOAD_VIA_TEXTURE_HEADER_INDEX 23:4 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVA1C0_SET_SPA_VERSION 0x0310 +#define NVA1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVA1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVA1C0_SET_FALCON00 0x0500 +#define NVA1C0_SET_FALCON00_V 31:0 + +#define NVA1C0_SET_FALCON01 0x0504 +#define NVA1C0_SET_FALCON01_V 31:0 + +#define NVA1C0_SET_FALCON02 0x0508 +#define NVA1C0_SET_FALCON02_V 31:0 + +#define NVA1C0_SET_FALCON03 0x050c +#define NVA1C0_SET_FALCON03_V 31:0 + +#define NVA1C0_SET_FALCON04 0x0510 +#define NVA1C0_SET_FALCON04_V 31:0 + +#define NVA1C0_SET_FALCON05 0x0514 +#define NVA1C0_SET_FALCON05_V 31:0 + +#define NVA1C0_SET_FALCON06 0x0518 +#define NVA1C0_SET_FALCON06_V 31:0 + +#define NVA1C0_SET_FALCON07 0x051c +#define NVA1C0_SET_FALCON07_V 31:0 + +#define NVA1C0_SET_FALCON08 0x0520 +#define NVA1C0_SET_FALCON08_V 31:0 + +#define NVA1C0_SET_FALCON09 0x0524 +#define NVA1C0_SET_FALCON09_V 31:0 + +#define NVA1C0_SET_FALCON10 0x0528 +#define NVA1C0_SET_FALCON10_V 31:0 + +#define NVA1C0_SET_FALCON11 0x052c +#define NVA1C0_SET_FALCON11_V 31:0 + +#define NVA1C0_SET_FALCON12 0x0530 +#define NVA1C0_SET_FALCON12_V 31:0 + +#define NVA1C0_SET_FALCON13 0x0534 +#define NVA1C0_SET_FALCON13_V 31:0 + +#define NVA1C0_SET_FALCON14 0x0538 +#define NVA1C0_SET_FALCON14_V 31:0 + +#define NVA1C0_SET_FALCON15 0x053c +#define NVA1C0_SET_FALCON15_V 31:0 + +#define NVA1C0_SET_FALCON16 0x0540 +#define NVA1C0_SET_FALCON16_V 31:0 + +#define NVA1C0_SET_FALCON17 0x0544 +#define NVA1C0_SET_FALCON17_V 31:0 + +#define NVA1C0_SET_FALCON18 0x0548 +#define NVA1C0_SET_FALCON18_V 31:0 + +#define NVA1C0_SET_FALCON19 0x054c +#define NVA1C0_SET_FALCON19_V 31:0 + +#define NVA1C0_SET_FALCON20 0x0550 +#define NVA1C0_SET_FALCON20_V 31:0 + +#define NVA1C0_SET_FALCON21 0x0554 +#define NVA1C0_SET_FALCON21_V 31:0 + +#define NVA1C0_SET_FALCON22 0x0558 +#define NVA1C0_SET_FALCON22_V 31:0 + +#define NVA1C0_SET_FALCON23 0x055c +#define NVA1C0_SET_FALCON23_V 31:0 + +#define NVA1C0_SET_FALCON24 0x0560 +#define NVA1C0_SET_FALCON24_V 31:0 + +#define NVA1C0_SET_FALCON25 0x0564 +#define NVA1C0_SET_FALCON25_V 31:0 + +#define NVA1C0_SET_FALCON26 0x0568 +#define NVA1C0_SET_FALCON26_V 31:0 + +#define NVA1C0_SET_FALCON27 0x056c +#define NVA1C0_SET_FALCON27_V 31:0 + +#define NVA1C0_SET_FALCON28 0x0570 +#define NVA1C0_SET_FALCON28_V 31:0 + +#define NVA1C0_SET_FALCON29 0x0574 +#define NVA1C0_SET_FALCON29_V 31:0 + +#define NVA1C0_SET_FALCON30 0x0578 +#define NVA1C0_SET_FALCON30_V 31:0 + +#define NVA1C0_SET_FALCON31 0x057c +#define NVA1C0_SET_FALCON31_V 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVA1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVA1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVA1C0_SET_SPARE_NOOP12 0x0f44 +#define NVA1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP13 0x0f48 +#define NVA1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP14 0x0f4c +#define NVA1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP15 0x0f50 +#define NVA1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP00 0x1040 +#define NVA1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP01 0x1044 +#define NVA1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP02 0x1048 +#define NVA1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP03 0x104c +#define NVA1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP04 0x1050 +#define NVA1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP05 0x1054 +#define NVA1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP06 0x1058 +#define NVA1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP07 0x105c +#define NVA1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP08 0x1060 +#define NVA1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP09 0x1064 +#define NVA1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP10 0x1068 +#define NVA1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVA1C0_SET_SPARE_NOOP11 0x106c +#define NVA1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVA1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVA1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVA1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVA1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVA1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVA1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVA1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVA1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVA1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVA1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVA1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVA1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVA1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVA1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVA1C0_SET_PROGRAM_REGION_B 0x160c +#define NVA1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVA1C0_SET_SHADER_CONTROL 0x1690 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL 0:0 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_ZERO 0x00000000 +#define NVA1C0_SET_SHADER_CONTROL_DEFAULT_PARTIAL_INFINITY 0x00000001 + +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVA1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVA1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVA1C0_PIPE_NOP 0x1a2c +#define NVA1C0_PIPE_NOP_V 31:0 + +#define NVA1C0_SET_SPARE00 0x1a30 +#define NVA1C0_SET_SPARE00_V 31:0 + +#define NVA1C0_SET_SPARE01 0x1a34 +#define NVA1C0_SET_SPARE01_V 31:0 + +#define NVA1C0_SET_SPARE02 0x1a38 +#define NVA1C0_SET_SPARE02_V 31:0 + +#define NVA1C0_SET_SPARE03 0x1a3c +#define NVA1C0_SET_SPARE03_V 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVA1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVA1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVA1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVA1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVA1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVA1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVA1C0_SET_TRAP_HANDLER 0x260c +#define NVA1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVA1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVA1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVA1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_kepler_compute_b_h_ */ diff --git a/Compute-Class-Methods/clb0c0.h b/Compute-Class-Methods/clb0c0.h new file mode 100644 index 0000000..7f63b4a --- /dev/null +++ b/Compute-Class-Methods/clb0c0.h @@ -0,0 +1,931 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_a_h_ +#define _cl_maxwell_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_a */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_A 0xB0C0 + +typedef volatile struct _clb0c0_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0x7]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 PmTriggerWfi; + NvU32 Reserved_0x148[0x2]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0xA]; + NvU32 LineLengthIn; + NvU32 LineCount; + NvU32 OffsetOutUpper; + NvU32 OffsetOut; + NvU32 PitchOut; + NvU32 SetDstBlockSize; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstOriginBytesX; + NvU32 SetDstOriginSamplesY; + NvU32 LaunchDma; + NvU32 LoadInlineData; + NvU32 Reserved_0x1B8[0x9]; + NvU32 SetI2mSemaphoreA; + NvU32 SetI2mSemaphoreB; + NvU32 SetI2mSemaphoreC; + NvU32 Reserved_0x1E8[0x2]; + NvU32 SetI2mSpareNoop00; + NvU32 SetI2mSpareNoop01; + NvU32 SetI2mSpareNoop02; + NvU32 SetI2mSpareNoop03; + NvU32 SetValidSpanOverflowAreaA; + NvU32 SetValidSpanOverflowAreaB; + NvU32 SetValidSpanOverflowAreaC; + NvU32 SetCoalesceWaitingPeriodUnit; + NvU32 PerfmonTransfer; + NvU32 SetShaderSharedMemoryWindow; + NvU32 SetSelectMaxwellTextureHeaders; + NvU32 InvalidateShaderCaches; + NvU32 SetReservedSwMethod00; + NvU32 SetReservedSwMethod01; + NvU32 SetReservedSwMethod02; + NvU32 SetReservedSwMethod03; + NvU32 SetReservedSwMethod04; + NvU32 SetReservedSwMethod05; + NvU32 SetReservedSwMethod06; + NvU32 SetReservedSwMethod07; + NvU32 SetCwdControl; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 SetCwdRefCounter; + NvU32 SetReservedSwMethod08; + NvU32 SetReservedSwMethod09; + NvU32 SetReservedSwMethod10; + NvU32 SetReservedSwMethod11; + NvU32 SetReservedSwMethod12; + NvU32 SetReservedSwMethod13; + NvU32 SetReservedSwMethod14; + NvU32 SetReservedSwMethod15; + NvU32 Reserved_0x26C[0x2]; + NvU32 InvalidateConstantBufferCacheA; + NvU32 InvalidateConstantBufferCacheB; + NvU32 InvalidateConstantBufferCacheC; + NvU32 SetComputeClassVersion; + NvU32 CheckComputeClassVersion; + NvU32 SetQmdVersion; + NvU32 Reserved_0x28C[0x1]; + NvU32 CheckQmdVersion; + NvU32 Reserved_0x294[0x7]; + NvU32 SetCwdSlotCount; + NvU32 SendPcasA; + NvU32 SendPcasB; + NvU32 SendSignalingPcasB; + NvU32 Reserved_0x2C0[0x9]; + NvU32 SetShaderLocalMemoryNonThrottledA; + NvU32 SetShaderLocalMemoryNonThrottledB; + NvU32 SetShaderLocalMemoryNonThrottledC; + NvU32 SetShaderLocalMemoryThrottledA; + NvU32 SetShaderLocalMemoryThrottledB; + NvU32 SetShaderLocalMemoryThrottledC; + NvU32 Reserved_0x2FC[0x5]; + NvU32 SetSpaVersion; + NvU32 Reserved_0x314[0x7B]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x7F]; + NvU32 SetShaderLocalMemoryWindow; + NvU32 Reserved_0x780[0x4]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 Reserved_0x798[0x17F]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x57]; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; + NvU32 Reserved_0xF54[0x3B]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 Reserved_0x1070[0x86]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x7]; + NvU32 ActivatePerfSettingsForComputeContext; + NvU32 Reserved_0x12AC[0x21]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x3A]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x40]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x22]; + NvU32 SetProgramRegionA; + NvU32 SetProgramRegionB; + NvU32 Reserved_0x1610[0x22]; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xAA]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A24[0x1]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x2BE]; + NvU32 SetBindlessTexture; + NvU32 SetTrapHandler; + NvU32 Reserved_0x2610[0x34B]; + NvU32 SetShaderPerformanceCounterValueUpper[0x8]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 StartShaderPerformanceCounter; + NvU32 StopShaderPerformanceCounter; + NvU32 Reserved_0x33E8[0x6]; + NvU32 SetMmeShadowScratch[0x8]; +} maxwell_compute_a_t; + + +#define NVB0C0_SET_OBJECT 0x0000 +#define NVB0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB0C0_NO_OPERATION 0x0100 +#define NVB0C0_NO_OPERATION_V 31:0 + +#define NVB0C0_SET_NOTIFY_A 0x0104 +#define NVB0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_NOTIFY_B 0x0108 +#define NVB0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_NOTIFY 0x010c +#define NVB0C0_NOTIFY_TYPE 31:0 +#define NVB0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB0C0_WAIT_FOR_IDLE 0x0110 +#define NVB0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SEND_GO_IDLE 0x013c +#define NVB0C0_SEND_GO_IDLE_V 31:0 + +#define NVB0C0_PM_TRIGGER 0x0140 +#define NVB0C0_PM_TRIGGER_V 31:0 + +#define NVB0C0_PM_TRIGGER_WFI 0x0144 +#define NVB0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB0C0_LINE_LENGTH_IN 0x0180 +#define NVB0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB0C0_LINE_COUNT 0x0184 +#define NVB0C0_LINE_COUNT_VALUE 31:0 + +#define NVB0C0_OFFSET_OUT_UPPER 0x0188 +#define NVB0C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB0C0_OFFSET_OUT 0x018c +#define NVB0C0_OFFSET_OUT_VALUE 31:0 + +#define NVB0C0_PITCH_OUT 0x0190 +#define NVB0C0_PITCH_OUT_VALUE 31:0 + +#define NVB0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB0C0_SET_DST_WIDTH 0x0198 +#define NVB0C0_SET_DST_WIDTH_V 31:0 + +#define NVB0C0_SET_DST_HEIGHT 0x019c +#define NVB0C0_SET_DST_HEIGHT_V 31:0 + +#define NVB0C0_SET_DST_DEPTH 0x01a0 +#define NVB0C0_SET_DST_DEPTH_V 31:0 + +#define NVB0C0_SET_DST_LAYER 0x01a4 +#define NVB0C0_SET_DST_LAYER_V 31:0 + +#define NVB0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB0C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB0C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB0C0_LAUNCH_DMA 0x01b0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB0C0_LOAD_INLINE_DATA 0x01b4 +#define NVB0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB0C0_PERFMON_TRANSFER 0x0210 +#define NVB0C0_PERFMON_TRANSFER_V 31:0 + +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB0C0_SET_CWD_CONTROL 0x0240 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_QMD_VERSION 0x0288 +#define NVB0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_CHECK_QMD_VERSION 0x0290 +#define NVB0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB0C0_SEND_PCAS_A 0x02b4 +#define NVB0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB0C0_SEND_PCAS_B 0x02b8 +#define NVB0C0_SEND_PCAS_B_FROM 23:0 +#define NVB0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB0C0_SET_SPA_VERSION 0x0310 +#define NVB0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB0C0_SET_FALCON00 0x0500 +#define NVB0C0_SET_FALCON00_V 31:0 + +#define NVB0C0_SET_FALCON01 0x0504 +#define NVB0C0_SET_FALCON01_V 31:0 + +#define NVB0C0_SET_FALCON02 0x0508 +#define NVB0C0_SET_FALCON02_V 31:0 + +#define NVB0C0_SET_FALCON03 0x050c +#define NVB0C0_SET_FALCON03_V 31:0 + +#define NVB0C0_SET_FALCON04 0x0510 +#define NVB0C0_SET_FALCON04_V 31:0 + +#define NVB0C0_SET_FALCON05 0x0514 +#define NVB0C0_SET_FALCON05_V 31:0 + +#define NVB0C0_SET_FALCON06 0x0518 +#define NVB0C0_SET_FALCON06_V 31:0 + +#define NVB0C0_SET_FALCON07 0x051c +#define NVB0C0_SET_FALCON07_V 31:0 + +#define NVB0C0_SET_FALCON08 0x0520 +#define NVB0C0_SET_FALCON08_V 31:0 + +#define NVB0C0_SET_FALCON09 0x0524 +#define NVB0C0_SET_FALCON09_V 31:0 + +#define NVB0C0_SET_FALCON10 0x0528 +#define NVB0C0_SET_FALCON10_V 31:0 + +#define NVB0C0_SET_FALCON11 0x052c +#define NVB0C0_SET_FALCON11_V 31:0 + +#define NVB0C0_SET_FALCON12 0x0530 +#define NVB0C0_SET_FALCON12_V 31:0 + +#define NVB0C0_SET_FALCON13 0x0534 +#define NVB0C0_SET_FALCON13_V 31:0 + +#define NVB0C0_SET_FALCON14 0x0538 +#define NVB0C0_SET_FALCON14_V 31:0 + +#define NVB0C0_SET_FALCON15 0x053c +#define NVB0C0_SET_FALCON15_V 31:0 + +#define NVB0C0_SET_FALCON16 0x0540 +#define NVB0C0_SET_FALCON16_V 31:0 + +#define NVB0C0_SET_FALCON17 0x0544 +#define NVB0C0_SET_FALCON17_V 31:0 + +#define NVB0C0_SET_FALCON18 0x0548 +#define NVB0C0_SET_FALCON18_V 31:0 + +#define NVB0C0_SET_FALCON19 0x054c +#define NVB0C0_SET_FALCON19_V 31:0 + +#define NVB0C0_SET_FALCON20 0x0550 +#define NVB0C0_SET_FALCON20_V 31:0 + +#define NVB0C0_SET_FALCON21 0x0554 +#define NVB0C0_SET_FALCON21_V 31:0 + +#define NVB0C0_SET_FALCON22 0x0558 +#define NVB0C0_SET_FALCON22_V 31:0 + +#define NVB0C0_SET_FALCON23 0x055c +#define NVB0C0_SET_FALCON23_V 31:0 + +#define NVB0C0_SET_FALCON24 0x0560 +#define NVB0C0_SET_FALCON24_V 31:0 + +#define NVB0C0_SET_FALCON25 0x0564 +#define NVB0C0_SET_FALCON25_V 31:0 + +#define NVB0C0_SET_FALCON26 0x0568 +#define NVB0C0_SET_FALCON26_V 31:0 + +#define NVB0C0_SET_FALCON27 0x056c +#define NVB0C0_SET_FALCON27_V 31:0 + +#define NVB0C0_SET_FALCON28 0x0570 +#define NVB0C0_SET_FALCON28_V 31:0 + +#define NVB0C0_SET_FALCON29 0x0574 +#define NVB0C0_SET_FALCON29_V 31:0 + +#define NVB0C0_SET_FALCON30 0x0578 +#define NVB0C0_SET_FALCON30_V 31:0 + +#define NVB0C0_SET_FALCON31 0x057c +#define NVB0C0_SET_FALCON31_V 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB0C0_SET_SPARE_NOOP12 0x0f44 +#define NVB0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP13 0x0f48 +#define NVB0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP14 0x0f4c +#define NVB0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP15 0x0f50 +#define NVB0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP00 0x1040 +#define NVB0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP01 0x1044 +#define NVB0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP02 0x1048 +#define NVB0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP03 0x104c +#define NVB0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP04 0x1050 +#define NVB0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP05 0x1054 +#define NVB0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP06 0x1058 +#define NVB0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP07 0x105c +#define NVB0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP08 0x1060 +#define NVB0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP09 0x1064 +#define NVB0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP10 0x1068 +#define NVB0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB0C0_SET_SPARE_NOOP11 0x106c +#define NVB0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB0C0_SET_PROGRAM_REGION_B 0x160c +#define NVB0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB0C0_PIPE_NOP 0x1a2c +#define NVB0C0_PIPE_NOP_V 31:0 + +#define NVB0C0_SET_SPARE00 0x1a30 +#define NVB0C0_SET_SPARE00_V 31:0 + +#define NVB0C0_SET_SPARE01 0x1a34 +#define NVB0C0_SET_SPARE01_V 31:0 + +#define NVB0C0_SET_SPARE02 0x1a38 +#define NVB0C0_SET_SPARE02_V 31:0 + +#define NVB0C0_SET_SPARE03 0x1a3c +#define NVB0C0_SET_SPARE03_V 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB0C0_SET_TRAP_HANDLER 0x260c +#define NVB0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_a_h_ */ diff --git a/Compute-Class-Methods/clb1c0.h b/Compute-Class-Methods/clb1c0.h new file mode 100644 index 0000000..ba5519d --- /dev/null +++ b/Compute-Class-Methods/clb1c0.h @@ -0,0 +1,968 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_maxwell_compute_b_h_ +#define _cl_maxwell_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl maxwell_compute_b */ + +#include "nvtypes.h" + +#define MAXWELL_COMPUTE_B 0xB1C0 + +typedef volatile struct _clb1c0_tag0 { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0x7]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 PmTriggerWfi; + NvU32 Reserved_0x148[0x2]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0xA]; + NvU32 LineLengthIn; + NvU32 LineCount; + NvU32 OffsetOutUpper; + NvU32 OffsetOut; + NvU32 PitchOut; + NvU32 SetDstBlockSize; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstOriginBytesX; + NvU32 SetDstOriginSamplesY; + NvU32 LaunchDma; + NvU32 LoadInlineData; + NvU32 Reserved_0x1B8[0x9]; + NvU32 SetI2mSemaphoreA; + NvU32 SetI2mSemaphoreB; + NvU32 SetI2mSemaphoreC; + NvU32 Reserved_0x1E8[0x2]; + NvU32 SetI2mSpareNoop00; + NvU32 SetI2mSpareNoop01; + NvU32 SetI2mSpareNoop02; + NvU32 SetI2mSpareNoop03; + NvU32 SetValidSpanOverflowAreaA; + NvU32 SetValidSpanOverflowAreaB; + NvU32 SetValidSpanOverflowAreaC; + NvU32 SetCoalesceWaitingPeriodUnit; + NvU32 PerfmonTransfer; + NvU32 SetShaderSharedMemoryWindow; + NvU32 SetSelectMaxwellTextureHeaders; + NvU32 InvalidateShaderCaches; + NvU32 SetReservedSwMethod00; + NvU32 SetReservedSwMethod01; + NvU32 SetReservedSwMethod02; + NvU32 SetReservedSwMethod03; + NvU32 SetReservedSwMethod04; + NvU32 SetReservedSwMethod05; + NvU32 SetReservedSwMethod06; + NvU32 SetReservedSwMethod07; + NvU32 SetCwdControl; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 SetCwdRefCounter; + NvU32 SetReservedSwMethod08; + NvU32 SetReservedSwMethod09; + NvU32 SetReservedSwMethod10; + NvU32 SetReservedSwMethod11; + NvU32 SetReservedSwMethod12; + NvU32 SetReservedSwMethod13; + NvU32 SetReservedSwMethod14; + NvU32 SetReservedSwMethod15; + NvU32 SetGwcScgType; + NvU32 SetScgControl; + NvU32 InvalidateConstantBufferCacheA; + NvU32 InvalidateConstantBufferCacheB; + NvU32 InvalidateConstantBufferCacheC; + NvU32 SetComputeClassVersion; + NvU32 CheckComputeClassVersion; + NvU32 SetQmdVersion; + NvU32 SetWfiConfig; + NvU32 CheckQmdVersion; + NvU32 WaitForIdleScgType; + NvU32 InvalidateSkedCaches; + NvU32 SetScgRenderEnableControl; + NvU32 Reserved_0x2A0[0x4]; + NvU32 SetCwdSlotCount; + NvU32 SendPcasA; + NvU32 SendPcasB; + NvU32 SendSignalingPcasB; + NvU32 Reserved_0x2C0[0x9]; + NvU32 SetShaderLocalMemoryNonThrottledA; + NvU32 SetShaderLocalMemoryNonThrottledB; + NvU32 SetShaderLocalMemoryNonThrottledC; + NvU32 SetShaderLocalMemoryThrottledA; + NvU32 SetShaderLocalMemoryThrottledB; + NvU32 SetShaderLocalMemoryThrottledC; + NvU32 Reserved_0x2FC[0x5]; + NvU32 SetSpaVersion; + NvU32 Reserved_0x314[0x7B]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x7F]; + NvU32 SetShaderLocalMemoryWindow; + NvU32 Reserved_0x780[0x4]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 Reserved_0x798[0x17F]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x57]; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; + NvU32 Reserved_0xF54[0x3B]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 Reserved_0x1070[0x67]; + NvU32 InvalidateSamplerCacheAll; + NvU32 InvalidateTextureHeaderCacheAll; + NvU32 Reserved_0x1214[0x1D]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x7]; + NvU32 ActivatePerfSettingsForComputeContext; + NvU32 Reserved_0x12AC[0x21]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x3A]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x40]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x22]; + NvU32 SetProgramRegionA; + NvU32 SetProgramRegionB; + NvU32 Reserved_0x1610[0x22]; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xAA]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A24[0x1]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x2BE]; + NvU32 SetBindlessTexture; + NvU32 SetTrapHandler; + NvU32 Reserved_0x2610[0x34B]; + NvU32 SetShaderPerformanceCounterValueUpper[0x8]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 StartShaderPerformanceCounter; + NvU32 StopShaderPerformanceCounter; + NvU32 Reserved_0x33E8[0x6]; + NvU32 SetMmeShadowScratch[0x8]; +} maxwell_compute_b_t; + + +#define NVB1C0_SET_OBJECT 0x0000 +#define NVB1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVB1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVB1C0_NO_OPERATION 0x0100 +#define NVB1C0_NO_OPERATION_V 31:0 + +#define NVB1C0_SET_NOTIFY_A 0x0104 +#define NVB1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_NOTIFY_B 0x0108 +#define NVB1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_NOTIFY 0x010c +#define NVB1C0_NOTIFY_TYPE 31:0 +#define NVB1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVB1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVB1C0_WAIT_FOR_IDLE 0x0110 +#define NVB1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SEND_GO_IDLE 0x013c +#define NVB1C0_SEND_GO_IDLE_V 31:0 + +#define NVB1C0_PM_TRIGGER 0x0140 +#define NVB1C0_PM_TRIGGER_V 31:0 + +#define NVB1C0_PM_TRIGGER_WFI 0x0144 +#define NVB1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVB1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVB1C0_LINE_LENGTH_IN 0x0180 +#define NVB1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVB1C0_LINE_COUNT 0x0184 +#define NVB1C0_LINE_COUNT_VALUE 31:0 + +#define NVB1C0_OFFSET_OUT_UPPER 0x0188 +#define NVB1C0_OFFSET_OUT_UPPER_VALUE 7:0 + +#define NVB1C0_OFFSET_OUT 0x018c +#define NVB1C0_OFFSET_OUT_VALUE 31:0 + +#define NVB1C0_PITCH_OUT 0x0190 +#define NVB1C0_PITCH_OUT_VALUE 31:0 + +#define NVB1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVB1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVB1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVB1C0_SET_DST_WIDTH 0x0198 +#define NVB1C0_SET_DST_WIDTH_V 31:0 + +#define NVB1C0_SET_DST_HEIGHT 0x019c +#define NVB1C0_SET_DST_HEIGHT_V 31:0 + +#define NVB1C0_SET_DST_DEPTH 0x01a0 +#define NVB1C0_SET_DST_DEPTH_V 31:0 + +#define NVB1C0_SET_DST_LAYER 0x01a4 +#define NVB1C0_SET_DST_LAYER_V 31:0 + +#define NVB1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVB1C0_SET_DST_ORIGIN_BYTES_X_V 19:0 + +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVB1C0_SET_DST_ORIGIN_SAMPLES_Y_V 15:0 + +#define NVB1C0_LAUNCH_DMA 0x01b0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVB1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVB1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVB1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVB1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVB1C0_LOAD_INLINE_DATA 0x01b4 +#define NVB1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVB1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVB1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVB1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVB1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVB1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVB1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVB1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVB1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVB1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVB1C0_PERFMON_TRANSFER 0x0210 +#define NVB1C0_PERFMON_TRANSFER_V 31:0 + +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVB1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVB1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVB1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVB1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVB1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVB1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVB1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVB1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVB1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVB1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVB1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVB1C0_SET_CWD_CONTROL 0x0240 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVB1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVB1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVB1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVB1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVB1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVB1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVB1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVB1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVB1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVB1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVB1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVB1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVB1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVB1C0_SET_GWC_SCG_TYPE 0x026c +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVB1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVB1C0_SET_SCG_CONTROL 0x0270 +#define NVB1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVB1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_QMD_VERSION 0x0288 +#define NVB1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_SET_WFI_CONFIG 0x028c +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVB1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVB1C0_CHECK_QMD_VERSION 0x0290 +#define NVB1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVB1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVB1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVB1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVB1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVB1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVB1C0_SEND_PCAS_A 0x02b4 +#define NVB1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVB1C0_SEND_PCAS_B 0x02b8 +#define NVB1C0_SEND_PCAS_B_FROM 23:0 +#define NVB1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVB1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVB1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVB1C0_SET_SPA_VERSION 0x0310 +#define NVB1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVB1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVB1C0_SET_FALCON00 0x0500 +#define NVB1C0_SET_FALCON00_V 31:0 + +#define NVB1C0_SET_FALCON01 0x0504 +#define NVB1C0_SET_FALCON01_V 31:0 + +#define NVB1C0_SET_FALCON02 0x0508 +#define NVB1C0_SET_FALCON02_V 31:0 + +#define NVB1C0_SET_FALCON03 0x050c +#define NVB1C0_SET_FALCON03_V 31:0 + +#define NVB1C0_SET_FALCON04 0x0510 +#define NVB1C0_SET_FALCON04_V 31:0 + +#define NVB1C0_SET_FALCON05 0x0514 +#define NVB1C0_SET_FALCON05_V 31:0 + +#define NVB1C0_SET_FALCON06 0x0518 +#define NVB1C0_SET_FALCON06_V 31:0 + +#define NVB1C0_SET_FALCON07 0x051c +#define NVB1C0_SET_FALCON07_V 31:0 + +#define NVB1C0_SET_FALCON08 0x0520 +#define NVB1C0_SET_FALCON08_V 31:0 + +#define NVB1C0_SET_FALCON09 0x0524 +#define NVB1C0_SET_FALCON09_V 31:0 + +#define NVB1C0_SET_FALCON10 0x0528 +#define NVB1C0_SET_FALCON10_V 31:0 + +#define NVB1C0_SET_FALCON11 0x052c +#define NVB1C0_SET_FALCON11_V 31:0 + +#define NVB1C0_SET_FALCON12 0x0530 +#define NVB1C0_SET_FALCON12_V 31:0 + +#define NVB1C0_SET_FALCON13 0x0534 +#define NVB1C0_SET_FALCON13_V 31:0 + +#define NVB1C0_SET_FALCON14 0x0538 +#define NVB1C0_SET_FALCON14_V 31:0 + +#define NVB1C0_SET_FALCON15 0x053c +#define NVB1C0_SET_FALCON15_V 31:0 + +#define NVB1C0_SET_FALCON16 0x0540 +#define NVB1C0_SET_FALCON16_V 31:0 + +#define NVB1C0_SET_FALCON17 0x0544 +#define NVB1C0_SET_FALCON17_V 31:0 + +#define NVB1C0_SET_FALCON18 0x0548 +#define NVB1C0_SET_FALCON18_V 31:0 + +#define NVB1C0_SET_FALCON19 0x054c +#define NVB1C0_SET_FALCON19_V 31:0 + +#define NVB1C0_SET_FALCON20 0x0550 +#define NVB1C0_SET_FALCON20_V 31:0 + +#define NVB1C0_SET_FALCON21 0x0554 +#define NVB1C0_SET_FALCON21_V 31:0 + +#define NVB1C0_SET_FALCON22 0x0558 +#define NVB1C0_SET_FALCON22_V 31:0 + +#define NVB1C0_SET_FALCON23 0x055c +#define NVB1C0_SET_FALCON23_V 31:0 + +#define NVB1C0_SET_FALCON24 0x0560 +#define NVB1C0_SET_FALCON24_V 31:0 + +#define NVB1C0_SET_FALCON25 0x0564 +#define NVB1C0_SET_FALCON25_V 31:0 + +#define NVB1C0_SET_FALCON26 0x0568 +#define NVB1C0_SET_FALCON26_V 31:0 + +#define NVB1C0_SET_FALCON27 0x056c +#define NVB1C0_SET_FALCON27_V 31:0 + +#define NVB1C0_SET_FALCON28 0x0570 +#define NVB1C0_SET_FALCON28_V 31:0 + +#define NVB1C0_SET_FALCON29 0x0574 +#define NVB1C0_SET_FALCON29_V 31:0 + +#define NVB1C0_SET_FALCON30 0x0578 +#define NVB1C0_SET_FALCON30_V 31:0 + +#define NVB1C0_SET_FALCON31 0x057c +#define NVB1C0_SET_FALCON31_V 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVB1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVB1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVB1C0_SET_SPARE_NOOP12 0x0f44 +#define NVB1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP13 0x0f48 +#define NVB1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP14 0x0f4c +#define NVB1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP15 0x0f50 +#define NVB1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP00 0x1040 +#define NVB1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP01 0x1044 +#define NVB1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP02 0x1048 +#define NVB1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP03 0x104c +#define NVB1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP04 0x1050 +#define NVB1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP05 0x1054 +#define NVB1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP06 0x1058 +#define NVB1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP07 0x105c +#define NVB1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP08 0x1060 +#define NVB1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP09 0x1064 +#define NVB1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP10 0x1068 +#define NVB1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVB1C0_SET_SPARE_NOOP11 0x106c +#define NVB1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVB1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVB1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVB1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVB1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVB1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVB1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVB1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVB1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVB1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVB1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVB1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVB1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVB1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVB1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 7:0 + +#define NVB1C0_SET_PROGRAM_REGION_B 0x160c +#define NVB1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVB1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVB1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVB1C0_PIPE_NOP 0x1a2c +#define NVB1C0_PIPE_NOP_V 31:0 + +#define NVB1C0_SET_SPARE00 0x1a30 +#define NVB1C0_SET_SPARE00_V 31:0 + +#define NVB1C0_SET_SPARE01 0x1a34 +#define NVB1C0_SET_SPARE01_V 31:0 + +#define NVB1C0_SET_SPARE02 0x1a38 +#define NVB1C0_SET_SPARE02_V 31:0 + +#define NVB1C0_SET_SPARE03 0x1a3c +#define NVB1C0_SET_SPARE03_V 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVB1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVB1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVB1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVB1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVB1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVB1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVB1C0_SET_TRAP_HANDLER 0x260c +#define NVB1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVB1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVB1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVB1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVB1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVB1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_maxwell_compute_b_h_ */ diff --git a/Compute-Class-Methods/clc0c0.h b/Compute-Class-Methods/clc0c0.h new file mode 100644 index 0000000..ee090ec --- /dev/null +++ b/Compute-Class-Methods/clc0c0.h @@ -0,0 +1,1006 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_a_h_ +#define _cl_pascal_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_a */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_A 0xC0C0 + +typedef volatile struct pascal_compute_a_struct { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0x7]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 PmTriggerWfi; + NvU32 Reserved_0x148[0x2]; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0xA]; + NvU32 LineLengthIn; + NvU32 LineCount; + NvU32 OffsetOutUpper; + NvU32 OffsetOut; + NvU32 PitchOut; + NvU32 SetDstBlockSize; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstOriginBytesX; + NvU32 SetDstOriginSamplesY; + NvU32 LaunchDma; + NvU32 LoadInlineData; + NvU32 Reserved_0x1B8[0x9]; + NvU32 SetI2mSemaphoreA; + NvU32 SetI2mSemaphoreB; + NvU32 SetI2mSemaphoreC; + NvU32 Reserved_0x1E8[0x2]; + NvU32 SetI2mSpareNoop00; + NvU32 SetI2mSpareNoop01; + NvU32 SetI2mSpareNoop02; + NvU32 SetI2mSpareNoop03; + NvU32 SetValidSpanOverflowAreaA; + NvU32 SetValidSpanOverflowAreaB; + NvU32 SetValidSpanOverflowAreaC; + NvU32 SetCoalesceWaitingPeriodUnit; + NvU32 PerfmonTransfer; + NvU32 SetShaderSharedMemoryWindow; + NvU32 SetSelectMaxwellTextureHeaders; + NvU32 InvalidateShaderCaches; + NvU32 SetReservedSwMethod00; + NvU32 SetReservedSwMethod01; + NvU32 SetReservedSwMethod02; + NvU32 SetReservedSwMethod03; + NvU32 SetReservedSwMethod04; + NvU32 SetReservedSwMethod05; + NvU32 SetReservedSwMethod06; + NvU32 SetReservedSwMethod07; + NvU32 SetCwdControl; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 SetCwdRefCounter; + NvU32 SetReservedSwMethod08; + NvU32 SetReservedSwMethod09; + NvU32 SetReservedSwMethod10; + NvU32 SetReservedSwMethod11; + NvU32 SetReservedSwMethod12; + NvU32 SetReservedSwMethod13; + NvU32 SetReservedSwMethod14; + NvU32 SetReservedSwMethod15; + NvU32 SetGwcScgType; + NvU32 SetScgControl; + NvU32 InvalidateConstantBufferCacheA; + NvU32 InvalidateConstantBufferCacheB; + NvU32 InvalidateConstantBufferCacheC; + NvU32 SetComputeClassVersion; + NvU32 CheckComputeClassVersion; + NvU32 SetQmdVersion; + NvU32 SetWfiConfig; + NvU32 CheckQmdVersion; + NvU32 WaitForIdleScgType; + NvU32 InvalidateSkedCaches; + NvU32 SetScgRenderEnableControl; + NvU32 SetShaderSharedMemoryWindowA; + NvU32 SetShaderSharedMemoryWindowB; + NvU32 Reserved_0x2A8[0x2]; + NvU32 SetCwdSlotCount; + NvU32 SendPcasA; + NvU32 SendPcasB; + NvU32 SendSignalingPcasB; + NvU32 Reserved_0x2C0[0x9]; + NvU32 SetShaderLocalMemoryNonThrottledA; + NvU32 SetShaderLocalMemoryNonThrottledB; + NvU32 SetShaderLocalMemoryNonThrottledC; + NvU32 SetShaderLocalMemoryThrottledA; + NvU32 SetShaderLocalMemoryThrottledB; + NvU32 SetShaderLocalMemoryThrottledC; + NvU32 Reserved_0x2FC[0x5]; + NvU32 SetSpaVersion; + NvU32 Reserved_0x314[0x1]; + NvU32 SetInlineQmdAddressA; + NvU32 SetInlineQmdAddressB; + NvU32 LoadInlineQmdData[0x40]; + NvU32 Reserved_0x420[0x38]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x7F]; + NvU32 SetShaderLocalMemoryWindow; + NvU32 Reserved_0x780[0x4]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 Reserved_0x798[0x6]; + NvU32 SetShaderLocalMemoryWindowA; + NvU32 SetShaderLocalMemoryWindowB; + NvU32 Reserved_0x7B8[0x177]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x57]; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; + NvU32 Reserved_0xF54[0x3B]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 Reserved_0x1070[0x67]; + NvU32 InvalidateSamplerCacheAll; + NvU32 InvalidateTextureHeaderCacheAll; + NvU32 Reserved_0x1214[0x1D]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x7]; + NvU32 ActivatePerfSettingsForComputeContext; + NvU32 Reserved_0x12AC[0x21]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x3A]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x40]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x22]; + NvU32 SetProgramRegionA; + NvU32 SetProgramRegionB; + NvU32 Reserved_0x1610[0x22]; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xAA]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A24[0x1]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x2BE]; + NvU32 SetBindlessTexture; + NvU32 SetTrapHandler; + NvU32 Reserved_0x2610[0x34B]; + NvU32 SetShaderPerformanceCounterValueUpper[0x8]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 StartShaderPerformanceCounter; + NvU32 StopShaderPerformanceCounter; + NvU32 SetShaderPerformanceCounterSctlFilter; + NvU32 SetShaderPerformanceCounterCoreMioFilter; + NvU32 Reserved_0x33F0[0x4]; + NvU32 SetMmeShadowScratch[0x8]; +} pascal_compute_a_t; + + +#define NVC0C0_SET_OBJECT 0x0000 +#define NVC0C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC0C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC0C0_NO_OPERATION 0x0100 +#define NVC0C0_NO_OPERATION_V 31:0 + +#define NVC0C0_SET_NOTIFY_A 0x0104 +#define NVC0C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_NOTIFY_B 0x0108 +#define NVC0C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_NOTIFY 0x010c +#define NVC0C0_NOTIFY_TYPE 31:0 +#define NVC0C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC0C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC0C0_WAIT_FOR_IDLE 0x0110 +#define NVC0C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SEND_GO_IDLE 0x013c +#define NVC0C0_SEND_GO_IDLE_V 31:0 + +#define NVC0C0_PM_TRIGGER 0x0140 +#define NVC0C0_PM_TRIGGER_V 31:0 + +#define NVC0C0_PM_TRIGGER_WFI 0x0144 +#define NVC0C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC0C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC0C0_LINE_LENGTH_IN 0x0180 +#define NVC0C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC0C0_LINE_COUNT 0x0184 +#define NVC0C0_LINE_COUNT_VALUE 31:0 + +#define NVC0C0_OFFSET_OUT_UPPER 0x0188 +#define NVC0C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC0C0_OFFSET_OUT 0x018c +#define NVC0C0_OFFSET_OUT_VALUE 31:0 + +#define NVC0C0_PITCH_OUT 0x0190 +#define NVC0C0_PITCH_OUT_VALUE 31:0 + +#define NVC0C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC0C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC0C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC0C0_SET_DST_WIDTH 0x0198 +#define NVC0C0_SET_DST_WIDTH_V 31:0 + +#define NVC0C0_SET_DST_HEIGHT 0x019c +#define NVC0C0_SET_DST_HEIGHT_V 31:0 + +#define NVC0C0_SET_DST_DEPTH 0x01a0 +#define NVC0C0_SET_DST_DEPTH_V 31:0 + +#define NVC0C0_SET_DST_LAYER 0x01a4 +#define NVC0C0_SET_DST_LAYER_V 31:0 + +#define NVC0C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC0C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC0C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC0C0_LAUNCH_DMA 0x01b0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC0C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC0C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC0C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC0C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC0C0_LOAD_INLINE_DATA 0x01b4 +#define NVC0C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC0C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC0C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC0C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC0C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC0C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC0C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC0C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC0C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC0C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC0C0_PERFMON_TRANSFER 0x0210 +#define NVC0C0_PERFMON_TRANSFER_V 31:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC0C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC0C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC0C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC0C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC0C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC0C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC0C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC0C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC0C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC0C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC0C0_SET_CWD_CONTROL 0x0240 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC0C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC0C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC0C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC0C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC0C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC0C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC0C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC0C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC0C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC0C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC0C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC0C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC0C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC0C0_SET_GWC_SCG_TYPE 0x026c +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC0C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC0C0_SET_SCG_CONTROL 0x0270 +#define NVC0C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC0C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_QMD_VERSION 0x0288 +#define NVC0C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_SET_WFI_CONFIG 0x028c +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC0C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC0C0_CHECK_QMD_VERSION 0x0290 +#define NVC0C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC0C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC0C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC0C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC0C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC0C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC0C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC0C0_SEND_PCAS_A 0x02b4 +#define NVC0C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC0C0_SEND_PCAS_B 0x02b8 +#define NVC0C0_SEND_PCAS_B_FROM 23:0 +#define NVC0C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC0C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC0C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC0C0_SET_SPA_VERSION 0x0310 +#define NVC0C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC0C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC0C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC0C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC0C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC0C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC0C0_SET_FALCON00 0x0500 +#define NVC0C0_SET_FALCON00_V 31:0 + +#define NVC0C0_SET_FALCON01 0x0504 +#define NVC0C0_SET_FALCON01_V 31:0 + +#define NVC0C0_SET_FALCON02 0x0508 +#define NVC0C0_SET_FALCON02_V 31:0 + +#define NVC0C0_SET_FALCON03 0x050c +#define NVC0C0_SET_FALCON03_V 31:0 + +#define NVC0C0_SET_FALCON04 0x0510 +#define NVC0C0_SET_FALCON04_V 31:0 + +#define NVC0C0_SET_FALCON05 0x0514 +#define NVC0C0_SET_FALCON05_V 31:0 + +#define NVC0C0_SET_FALCON06 0x0518 +#define NVC0C0_SET_FALCON06_V 31:0 + +#define NVC0C0_SET_FALCON07 0x051c +#define NVC0C0_SET_FALCON07_V 31:0 + +#define NVC0C0_SET_FALCON08 0x0520 +#define NVC0C0_SET_FALCON08_V 31:0 + +#define NVC0C0_SET_FALCON09 0x0524 +#define NVC0C0_SET_FALCON09_V 31:0 + +#define NVC0C0_SET_FALCON10 0x0528 +#define NVC0C0_SET_FALCON10_V 31:0 + +#define NVC0C0_SET_FALCON11 0x052c +#define NVC0C0_SET_FALCON11_V 31:0 + +#define NVC0C0_SET_FALCON12 0x0530 +#define NVC0C0_SET_FALCON12_V 31:0 + +#define NVC0C0_SET_FALCON13 0x0534 +#define NVC0C0_SET_FALCON13_V 31:0 + +#define NVC0C0_SET_FALCON14 0x0538 +#define NVC0C0_SET_FALCON14_V 31:0 + +#define NVC0C0_SET_FALCON15 0x053c +#define NVC0C0_SET_FALCON15_V 31:0 + +#define NVC0C0_SET_FALCON16 0x0540 +#define NVC0C0_SET_FALCON16_V 31:0 + +#define NVC0C0_SET_FALCON17 0x0544 +#define NVC0C0_SET_FALCON17_V 31:0 + +#define NVC0C0_SET_FALCON18 0x0548 +#define NVC0C0_SET_FALCON18_V 31:0 + +#define NVC0C0_SET_FALCON19 0x054c +#define NVC0C0_SET_FALCON19_V 31:0 + +#define NVC0C0_SET_FALCON20 0x0550 +#define NVC0C0_SET_FALCON20_V 31:0 + +#define NVC0C0_SET_FALCON21 0x0554 +#define NVC0C0_SET_FALCON21_V 31:0 + +#define NVC0C0_SET_FALCON22 0x0558 +#define NVC0C0_SET_FALCON22_V 31:0 + +#define NVC0C0_SET_FALCON23 0x055c +#define NVC0C0_SET_FALCON23_V 31:0 + +#define NVC0C0_SET_FALCON24 0x0560 +#define NVC0C0_SET_FALCON24_V 31:0 + +#define NVC0C0_SET_FALCON25 0x0564 +#define NVC0C0_SET_FALCON25_V 31:0 + +#define NVC0C0_SET_FALCON26 0x0568 +#define NVC0C0_SET_FALCON26_V 31:0 + +#define NVC0C0_SET_FALCON27 0x056c +#define NVC0C0_SET_FALCON27_V 31:0 + +#define NVC0C0_SET_FALCON28 0x0570 +#define NVC0C0_SET_FALCON28_V 31:0 + +#define NVC0C0_SET_FALCON29 0x0574 +#define NVC0C0_SET_FALCON29_V 31:0 + +#define NVC0C0_SET_FALCON30 0x0578 +#define NVC0C0_SET_FALCON30_V 31:0 + +#define NVC0C0_SET_FALCON31 0x057c +#define NVC0C0_SET_FALCON31_V 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC0C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC0C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC0C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC0C0_SET_SPARE_NOOP12 0x0f44 +#define NVC0C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP13 0x0f48 +#define NVC0C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP14 0x0f4c +#define NVC0C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP15 0x0f50 +#define NVC0C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP00 0x1040 +#define NVC0C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP01 0x1044 +#define NVC0C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP02 0x1048 +#define NVC0C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP03 0x104c +#define NVC0C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP04 0x1050 +#define NVC0C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP05 0x1054 +#define NVC0C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP06 0x1058 +#define NVC0C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP07 0x105c +#define NVC0C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP08 0x1060 +#define NVC0C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP09 0x1064 +#define NVC0C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP10 0x1068 +#define NVC0C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC0C0_SET_SPARE_NOOP11 0x106c +#define NVC0C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC0C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC0C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC0C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC0C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC0C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC0C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC0C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC0C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC0C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC0C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC0C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC0C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC0C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC0C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC0C0_SET_PROGRAM_REGION_B 0x160c +#define NVC0C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC0C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC0C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC0C0_PIPE_NOP 0x1a2c +#define NVC0C0_PIPE_NOP_V 31:0 + +#define NVC0C0_SET_SPARE00 0x1a30 +#define NVC0C0_SET_SPARE00_V 31:0 + +#define NVC0C0_SET_SPARE01 0x1a34 +#define NVC0C0_SET_SPARE01_V 31:0 + +#define NVC0C0_SET_SPARE02 0x1a38 +#define NVC0C0_SET_SPARE02_V 31:0 + +#define NVC0C0_SET_SPARE03 0x1a3c +#define NVC0C0_SET_SPARE03_V 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC0C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC0C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC0C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC0C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC0C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC0C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC0C0_SET_TRAP_HANDLER 0x260c +#define NVC0C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC0C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC0C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC0C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC0C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC0C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_a_h_ */ diff --git a/Compute-Class-Methods/clc1c0.h b/Compute-Class-Methods/clc1c0.h new file mode 100644 index 0000000..e5d824f --- /dev/null +++ b/Compute-Class-Methods/clc1c0.h @@ -0,0 +1,1026 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_pascal_compute_b_h_ +#define _cl_pascal_compute_b_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl pascal_compute_b */ + +#include "nvtypes.h" + +#define PASCAL_COMPUTE_B 0xC1C0 + +typedef volatile struct pascal_compute_b_struct { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0x7]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 PmTriggerWfi; + NvU32 FeAtomicSequenceBegin; + NvU32 FeAtomicSequenceEnd; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0xA]; + NvU32 LineLengthIn; + NvU32 LineCount; + NvU32 OffsetOutUpper; + NvU32 OffsetOut; + NvU32 PitchOut; + NvU32 SetDstBlockSize; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstOriginBytesX; + NvU32 SetDstOriginSamplesY; + NvU32 LaunchDma; + NvU32 LoadInlineData; + NvU32 Reserved_0x1B8[0x9]; + NvU32 SetI2mSemaphoreA; + NvU32 SetI2mSemaphoreB; + NvU32 SetI2mSemaphoreC; + NvU32 Reserved_0x1E8[0x2]; + NvU32 SetI2mSpareNoop00; + NvU32 SetI2mSpareNoop01; + NvU32 SetI2mSpareNoop02; + NvU32 SetI2mSpareNoop03; + NvU32 SetValidSpanOverflowAreaA; + NvU32 SetValidSpanOverflowAreaB; + NvU32 SetValidSpanOverflowAreaC; + NvU32 SetCoalesceWaitingPeriodUnit; + NvU32 PerfmonTransfer; + NvU32 SetShaderSharedMemoryWindow; + NvU32 SetSelectMaxwellTextureHeaders; + NvU32 InvalidateShaderCaches; + NvU32 SetReservedSwMethod00; + NvU32 SetReservedSwMethod01; + NvU32 SetReservedSwMethod02; + NvU32 SetReservedSwMethod03; + NvU32 SetReservedSwMethod04; + NvU32 SetReservedSwMethod05; + NvU32 SetReservedSwMethod06; + NvU32 SetReservedSwMethod07; + NvU32 SetCwdControl; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 SetCwdRefCounter; + NvU32 SetReservedSwMethod08; + NvU32 SetReservedSwMethod09; + NvU32 SetReservedSwMethod10; + NvU32 SetReservedSwMethod11; + NvU32 SetReservedSwMethod12; + NvU32 SetReservedSwMethod13; + NvU32 SetReservedSwMethod14; + NvU32 SetReservedSwMethod15; + NvU32 SetGwcScgType; + NvU32 SetScgControl; + NvU32 InvalidateConstantBufferCacheA; + NvU32 InvalidateConstantBufferCacheB; + NvU32 InvalidateConstantBufferCacheC; + NvU32 SetComputeClassVersion; + NvU32 CheckComputeClassVersion; + NvU32 SetQmdVersion; + NvU32 SetWfiConfig; + NvU32 CheckQmdVersion; + NvU32 WaitForIdleScgType; + NvU32 InvalidateSkedCaches; + NvU32 SetScgRenderEnableControl; + NvU32 SetShaderSharedMemoryWindowA; + NvU32 SetShaderSharedMemoryWindowB; + NvU32 ScgHysteresisControl; + NvU32 Reserved_0x2AC[0x1]; + NvU32 SetCwdSlotCount; + NvU32 SendPcasA; + NvU32 SendPcasB; + NvU32 SendSignalingPcasB; + NvU32 Reserved_0x2C0[0x9]; + NvU32 SetShaderLocalMemoryNonThrottledA; + NvU32 SetShaderLocalMemoryNonThrottledB; + NvU32 SetShaderLocalMemoryNonThrottledC; + NvU32 SetShaderLocalMemoryThrottledA; + NvU32 SetShaderLocalMemoryThrottledB; + NvU32 SetShaderLocalMemoryThrottledC; + NvU32 Reserved_0x2FC[0x5]; + NvU32 SetSpaVersion; + NvU32 Reserved_0x314[0x1]; + NvU32 SetInlineQmdAddressA; + NvU32 SetInlineQmdAddressB; + NvU32 LoadInlineQmdData[0x40]; + NvU32 Reserved_0x420[0x38]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x7F]; + NvU32 SetShaderLocalMemoryWindow; + NvU32 Reserved_0x780[0x4]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 Reserved_0x798[0x6]; + NvU32 SetShaderLocalMemoryWindowA; + NvU32 SetShaderLocalMemoryWindowB; + NvU32 Reserved_0x7B8[0x177]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x57]; + NvU32 SetSpareNoop12; + NvU32 SetSpareNoop13; + NvU32 SetSpareNoop14; + NvU32 SetSpareNoop15; + NvU32 Reserved_0xF54[0x3B]; + NvU32 SetSpareNoop00; + NvU32 SetSpareNoop01; + NvU32 SetSpareNoop02; + NvU32 SetSpareNoop03; + NvU32 SetSpareNoop04; + NvU32 SetSpareNoop05; + NvU32 SetSpareNoop06; + NvU32 SetSpareNoop07; + NvU32 SetSpareNoop08; + NvU32 SetSpareNoop09; + NvU32 SetSpareNoop10; + NvU32 SetSpareNoop11; + NvU32 Reserved_0x1070[0x67]; + NvU32 InvalidateSamplerCacheAll; + NvU32 InvalidateTextureHeaderCacheAll; + NvU32 Reserved_0x1214[0x1D]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x7]; + NvU32 ActivatePerfSettingsForComputeContext; + NvU32 Reserved_0x12AC[0x21]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x3A]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x40]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x22]; + NvU32 SetProgramRegionA; + NvU32 SetProgramRegionB; + NvU32 Reserved_0x1610[0x22]; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xAA]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A24[0x1]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x2BE]; + NvU32 SetBindlessTexture; + NvU32 SetTrapHandler; + NvU32 Reserved_0x2610[0x34B]; + NvU32 SetShaderPerformanceCounterValueUpper[0x8]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 StartShaderPerformanceCounter; + NvU32 StopShaderPerformanceCounter; + NvU32 SetShaderPerformanceCounterSctlFilter; + NvU32 SetShaderPerformanceCounterCoreMioFilter; + NvU32 Reserved_0x33F0[0x4]; + NvU32 SetMmeShadowScratch[0x8]; +} pascal_compute_b_t; + + +#define NVC1C0_SET_OBJECT 0x0000 +#define NVC1C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC1C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC1C0_NO_OPERATION 0x0100 +#define NVC1C0_NO_OPERATION_V 31:0 + +#define NVC1C0_SET_NOTIFY_A 0x0104 +#define NVC1C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_NOTIFY_B 0x0108 +#define NVC1C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_NOTIFY 0x010c +#define NVC1C0_NOTIFY_TYPE 31:0 +#define NVC1C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC1C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC1C0_WAIT_FOR_IDLE 0x0110 +#define NVC1C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SEND_GO_IDLE 0x013c +#define NVC1C0_SEND_GO_IDLE_V 31:0 + +#define NVC1C0_PM_TRIGGER 0x0140 +#define NVC1C0_PM_TRIGGER_V 31:0 + +#define NVC1C0_PM_TRIGGER_WFI 0x0144 +#define NVC1C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC1C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC1C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC1C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC1C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC1C0_LINE_LENGTH_IN 0x0180 +#define NVC1C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC1C0_LINE_COUNT 0x0184 +#define NVC1C0_LINE_COUNT_VALUE 31:0 + +#define NVC1C0_OFFSET_OUT_UPPER 0x0188 +#define NVC1C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC1C0_OFFSET_OUT 0x018c +#define NVC1C0_OFFSET_OUT_VALUE 31:0 + +#define NVC1C0_PITCH_OUT 0x0190 +#define NVC1C0_PITCH_OUT_VALUE 31:0 + +#define NVC1C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC1C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC1C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC1C0_SET_DST_WIDTH 0x0198 +#define NVC1C0_SET_DST_WIDTH_V 31:0 + +#define NVC1C0_SET_DST_HEIGHT 0x019c +#define NVC1C0_SET_DST_HEIGHT_V 31:0 + +#define NVC1C0_SET_DST_DEPTH 0x01a0 +#define NVC1C0_SET_DST_DEPTH_V 31:0 + +#define NVC1C0_SET_DST_LAYER 0x01a4 +#define NVC1C0_SET_DST_LAYER_V 31:0 + +#define NVC1C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC1C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC1C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC1C0_LAUNCH_DMA 0x01b0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC1C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC1C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC1C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC1C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC1C0_LOAD_INLINE_DATA 0x01b4 +#define NVC1C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC1C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC1C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC1C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC1C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC1C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC1C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC1C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC1C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT 0x020c +#define NVC1C0_SET_COALESCE_WAITING_PERIOD_UNIT_CLOCKS 31:0 + +#define NVC1C0_PERFMON_TRANSFER 0x0210 +#define NVC1C0_PERFMON_TRANSFER_V 31:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW 0x0214 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS 0x0218 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V 0:0 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_FALSE 0x00000000 +#define NVC1C0_SET_SELECT_MAXWELL_TEXTURE_HEADERS_V_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC1C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC1C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC1C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC1C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC1C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC1C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC1C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC1C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC1C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC1C0_SET_CWD_CONTROL 0x0240 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION 0:0 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_LOAD_BALANCED 0x00000000 +#define NVC1C0_SET_CWD_CONTROL_SM_SELECTION_ROUND_ROBIN 0x00000001 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC1C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC1C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC1C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC1C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC1C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC1C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC1C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC1C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC1C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC1C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC1C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC1C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC1C0_SET_GWC_SCG_TYPE 0x026c +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE 0:0 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_GRAPHICS_COMPUTE0 0x00000000 +#define NVC1C0_SET_GWC_SCG_TYPE_SCG_TYPE_COMPUTE1 0x00000001 + +#define NVC1C0_SET_SCG_CONTROL 0x0270 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC1C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A 0x0274 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B 0x0278 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C 0x027c +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_BYTE_COUNT 16:0 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2 31:31 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_CONSTANT_BUFFER_CACHE_C_THRU_L2_TRUE 0x00000001 + +#define NVC1C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_QMD_VERSION 0x0288 +#define NVC1C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_SET_WFI_CONFIG 0x028c +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI 0:0 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_FALSE 0x00000000 +#define NVC1C0_SET_WFI_CONFIG_ENABLE_SCG_TYPE_WFI_TRUE 0x00000001 + +#define NVC1C0_CHECK_QMD_VERSION 0x0290 +#define NVC1C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC1C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE 0x0294 +#define NVC1C0_WAIT_FOR_IDLE_SCG_TYPE_V 31:0 + +#define NVC1C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC1C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL 0x029c +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE 0:0 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SCG_RENDER_ENABLE_CONTROL_COMPUTE1_USES_RENDER_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC1C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC1C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC1C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC1C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC1C0_SEND_PCAS_A 0x02b4 +#define NVC1C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC1C0_SEND_PCAS_B 0x02b8 +#define NVC1C0_SEND_PCAS_B_FROM 23:0 +#define NVC1C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC1C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC1C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A 0x02f0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B 0x02f4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C 0x02f8 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC1C0_SET_SPA_VERSION 0x0310 +#define NVC1C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC1C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC1C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC1C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC1C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC1C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC1C0_SET_FALCON00 0x0500 +#define NVC1C0_SET_FALCON00_V 31:0 + +#define NVC1C0_SET_FALCON01 0x0504 +#define NVC1C0_SET_FALCON01_V 31:0 + +#define NVC1C0_SET_FALCON02 0x0508 +#define NVC1C0_SET_FALCON02_V 31:0 + +#define NVC1C0_SET_FALCON03 0x050c +#define NVC1C0_SET_FALCON03_V 31:0 + +#define NVC1C0_SET_FALCON04 0x0510 +#define NVC1C0_SET_FALCON04_V 31:0 + +#define NVC1C0_SET_FALCON05 0x0514 +#define NVC1C0_SET_FALCON05_V 31:0 + +#define NVC1C0_SET_FALCON06 0x0518 +#define NVC1C0_SET_FALCON06_V 31:0 + +#define NVC1C0_SET_FALCON07 0x051c +#define NVC1C0_SET_FALCON07_V 31:0 + +#define NVC1C0_SET_FALCON08 0x0520 +#define NVC1C0_SET_FALCON08_V 31:0 + +#define NVC1C0_SET_FALCON09 0x0524 +#define NVC1C0_SET_FALCON09_V 31:0 + +#define NVC1C0_SET_FALCON10 0x0528 +#define NVC1C0_SET_FALCON10_V 31:0 + +#define NVC1C0_SET_FALCON11 0x052c +#define NVC1C0_SET_FALCON11_V 31:0 + +#define NVC1C0_SET_FALCON12 0x0530 +#define NVC1C0_SET_FALCON12_V 31:0 + +#define NVC1C0_SET_FALCON13 0x0534 +#define NVC1C0_SET_FALCON13_V 31:0 + +#define NVC1C0_SET_FALCON14 0x0538 +#define NVC1C0_SET_FALCON14_V 31:0 + +#define NVC1C0_SET_FALCON15 0x053c +#define NVC1C0_SET_FALCON15_V 31:0 + +#define NVC1C0_SET_FALCON16 0x0540 +#define NVC1C0_SET_FALCON16_V 31:0 + +#define NVC1C0_SET_FALCON17 0x0544 +#define NVC1C0_SET_FALCON17_V 31:0 + +#define NVC1C0_SET_FALCON18 0x0548 +#define NVC1C0_SET_FALCON18_V 31:0 + +#define NVC1C0_SET_FALCON19 0x054c +#define NVC1C0_SET_FALCON19_V 31:0 + +#define NVC1C0_SET_FALCON20 0x0550 +#define NVC1C0_SET_FALCON20_V 31:0 + +#define NVC1C0_SET_FALCON21 0x0554 +#define NVC1C0_SET_FALCON21_V 31:0 + +#define NVC1C0_SET_FALCON22 0x0558 +#define NVC1C0_SET_FALCON22_V 31:0 + +#define NVC1C0_SET_FALCON23 0x055c +#define NVC1C0_SET_FALCON23_V 31:0 + +#define NVC1C0_SET_FALCON24 0x0560 +#define NVC1C0_SET_FALCON24_V 31:0 + +#define NVC1C0_SET_FALCON25 0x0564 +#define NVC1C0_SET_FALCON25_V 31:0 + +#define NVC1C0_SET_FALCON26 0x0568 +#define NVC1C0_SET_FALCON26_V 31:0 + +#define NVC1C0_SET_FALCON27 0x056c +#define NVC1C0_SET_FALCON27_V 31:0 + +#define NVC1C0_SET_FALCON28 0x0570 +#define NVC1C0_SET_FALCON28_V 31:0 + +#define NVC1C0_SET_FALCON29 0x0574 +#define NVC1C0_SET_FALCON29_V 31:0 + +#define NVC1C0_SET_FALCON30 0x0578 +#define NVC1C0_SET_FALCON30_V 31:0 + +#define NVC1C0_SET_FALCON31 0x057c +#define NVC1C0_SET_FALCON31_V 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW 0x077c +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC1C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC1C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC1C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC1C0_SET_SPARE_NOOP12 0x0f44 +#define NVC1C0_SET_SPARE_NOOP12_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP13 0x0f48 +#define NVC1C0_SET_SPARE_NOOP13_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP14 0x0f4c +#define NVC1C0_SET_SPARE_NOOP14_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP15 0x0f50 +#define NVC1C0_SET_SPARE_NOOP15_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP00 0x1040 +#define NVC1C0_SET_SPARE_NOOP00_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP01 0x1044 +#define NVC1C0_SET_SPARE_NOOP01_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP02 0x1048 +#define NVC1C0_SET_SPARE_NOOP02_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP03 0x104c +#define NVC1C0_SET_SPARE_NOOP03_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP04 0x1050 +#define NVC1C0_SET_SPARE_NOOP04_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP05 0x1054 +#define NVC1C0_SET_SPARE_NOOP05_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP06 0x1058 +#define NVC1C0_SET_SPARE_NOOP06_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP07 0x105c +#define NVC1C0_SET_SPARE_NOOP07_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP08 0x1060 +#define NVC1C0_SET_SPARE_NOOP08_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP09 0x1064 +#define NVC1C0_SET_SPARE_NOOP09_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP10 0x1068 +#define NVC1C0_SET_SPARE_NOOP10_V 31:0 + +#define NVC1C0_SET_SPARE_NOOP11 0x106c +#define NVC1C0_SET_SPARE_NOOP11_V 31:0 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC1C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC1C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC1C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC1C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC1C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC1C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC1C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC1C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC1C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC1C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC1C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC1C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC1C0_SET_PROGRAM_REGION_A 0x1608 +#define NVC1C0_SET_PROGRAM_REGION_A_ADDRESS_UPPER 16:0 + +#define NVC1C0_SET_PROGRAM_REGION_B 0x160c +#define NVC1C0_SET_PROGRAM_REGION_B_ADDRESS_LOWER 31:0 + +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC1C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC1C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC1C0_PIPE_NOP 0x1a2c +#define NVC1C0_PIPE_NOP_V 31:0 + +#define NVC1C0_SET_SPARE00 0x1a30 +#define NVC1C0_SET_SPARE00_V 31:0 + +#define NVC1C0_SET_SPARE01 0x1a34 +#define NVC1C0_SET_SPARE01_V 31:0 + +#define NVC1C0_SET_SPARE02 0x1a38 +#define NVC1C0_SET_SPARE02_V 31:0 + +#define NVC1C0_SET_SPARE03 0x1a3c +#define NVC1C0_SET_SPARE03_V 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC1C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC1C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC1C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC1C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC1C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC1C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC1C0_SET_TRAP_HANDLER 0x260c +#define NVC1C0_SET_TRAP_HANDLER_OFFSET 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC1C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC1C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC1C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC1C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC1C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_pascal_compute_b_h_ */ diff --git a/Compute-Class-Methods/clc3c0.h b/Compute-Class-Methods/clc3c0.h new file mode 100644 index 0000000..c70a44f --- /dev/null +++ b/Compute-Class-Methods/clc3c0.h @@ -0,0 +1,912 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_volta_compute_a_h_ +#define _cl_volta_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl volta_compute_a */ + +#include "nvtypes.h" + +#define VOLTA_COMPUTE_A 0xC3C0 + +typedef volatile struct volta_compute_a_struct { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0x7]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 PmTriggerWfi; + NvU32 FeAtomicSequenceBegin; + NvU32 FeAtomicSequenceEnd; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0xA]; + NvU32 LineLengthIn; + NvU32 LineCount; + NvU32 OffsetOutUpper; + NvU32 OffsetOut; + NvU32 PitchOut; + NvU32 SetDstBlockSize; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstOriginBytesX; + NvU32 SetDstOriginSamplesY; + NvU32 LaunchDma; + NvU32 LoadInlineData; + NvU32 Reserved_0x1B8[0x9]; + NvU32 SetI2mSemaphoreA; + NvU32 SetI2mSemaphoreB; + NvU32 SetI2mSemaphoreC; + NvU32 Reserved_0x1E8[0x2]; + NvU32 SetI2mSpareNoop00; + NvU32 SetI2mSpareNoop01; + NvU32 SetI2mSpareNoop02; + NvU32 SetI2mSpareNoop03; + NvU32 SetValidSpanOverflowAreaA; + NvU32 SetValidSpanOverflowAreaB; + NvU32 SetValidSpanOverflowAreaC; + NvU32 Reserved_0x20C[0x1]; + NvU32 PerfmonTransfer; + NvU32 Reserved_0x214[0x2]; + NvU32 InvalidateShaderCaches; + NvU32 SetReservedSwMethod00; + NvU32 SetReservedSwMethod01; + NvU32 SetReservedSwMethod02; + NvU32 SetReservedSwMethod03; + NvU32 SetReservedSwMethod04; + NvU32 SetReservedSwMethod05; + NvU32 SetReservedSwMethod06; + NvU32 SetReservedSwMethod07; + NvU32 Reserved_0x240[0x1]; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 SetCwdRefCounter; + NvU32 SetReservedSwMethod08; + NvU32 SetReservedSwMethod09; + NvU32 SetReservedSwMethod10; + NvU32 SetReservedSwMethod11; + NvU32 SetReservedSwMethod12; + NvU32 SetReservedSwMethod13; + NvU32 SetReservedSwMethod14; + NvU32 SetReservedSwMethod15; + NvU32 Reserved_0x26C[0x1]; + NvU32 SetScgControl; + NvU32 Reserved_0x274[0x3]; + NvU32 SetComputeClassVersion; + NvU32 CheckComputeClassVersion; + NvU32 SetQmdVersion; + NvU32 Reserved_0x28C[0x1]; + NvU32 CheckQmdVersion; + NvU32 Reserved_0x294[0x1]; + NvU32 InvalidateSkedCaches; + NvU32 Reserved_0x29C[0x1]; + NvU32 SetShaderSharedMemoryWindowA; + NvU32 SetShaderSharedMemoryWindowB; + NvU32 ScgHysteresisControl; + NvU32 Reserved_0x2AC[0x1]; + NvU32 SetCwdSlotCount; + NvU32 SendPcasA; + NvU32 SendPcasB; + NvU32 SendSignalingPcasB; + NvU32 Reserved_0x2C0[0x3]; + NvU32 SetSkedCacheControl; + NvU32 Reserved_0x2D0[0x5]; + NvU32 SetShaderLocalMemoryNonThrottledA; + NvU32 SetShaderLocalMemoryNonThrottledB; + NvU32 SetShaderLocalMemoryNonThrottledC; + NvU32 Reserved_0x2F0[0x8]; + NvU32 SetSpaVersion; + NvU32 Reserved_0x314[0x1]; + NvU32 SetInlineQmdAddressA; + NvU32 SetInlineQmdAddressB; + NvU32 LoadInlineQmdData[0x40]; + NvU32 Reserved_0x420[0x38]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x84]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 Reserved_0x798[0x6]; + NvU32 SetShaderLocalMemoryWindowA; + NvU32 SetShaderLocalMemoryWindowB; + NvU32 Reserved_0x7B8[0x177]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x13]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x109]; + NvU32 InvalidateSamplerCacheAll; + NvU32 InvalidateTextureHeaderCacheAll; + NvU32 Reserved_0x1214[0x1D]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x7]; + NvU32 ActivatePerfSettingsForComputeContext; + NvU32 Reserved_0x12AC[0x21]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x3A]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x40]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x46]; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xAA]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x2BA]; + NvU32 SetTrapHandlerA; + NvU32 SetTrapHandlerB; + NvU32 Reserved_0x2600[0x2]; + NvU32 SetBindlessTexture; + NvU32 Reserved_0x260C[0x33A]; + NvU32 SetShaderPerformanceSnapshotCounterValue[0x8]; + NvU32 SetShaderPerformanceSnapshotCounterValueUpper[0x8]; + NvU32 EnableShaderPerformanceSnapshotCounter; + NvU32 DisableShaderPerformanceSnapshotCounter; + NvU32 SetShaderPerformanceCounterValueUpper[0x8]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 StartShaderPerformanceCounter; + NvU32 StopShaderPerformanceCounter; + NvU32 SetShaderPerformanceCounterSctlFilter; + NvU32 SetShaderPerformanceCounterCoreMioFilter; + NvU32 Reserved_0x33F0[0x4]; + NvU32 SetMmeShadowScratch[0x8]; +} volta_compute_a_t; + + +#define NVC3C0_SET_OBJECT 0x0000 +#define NVC3C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC3C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC3C0_NO_OPERATION 0x0100 +#define NVC3C0_NO_OPERATION_V 31:0 + +#define NVC3C0_SET_NOTIFY_A 0x0104 +#define NVC3C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_NOTIFY_B 0x0108 +#define NVC3C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_NOTIFY 0x010c +#define NVC3C0_NOTIFY_TYPE 31:0 +#define NVC3C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC3C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC3C0_WAIT_FOR_IDLE 0x0110 +#define NVC3C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SEND_GO_IDLE 0x013c +#define NVC3C0_SEND_GO_IDLE_V 31:0 + +#define NVC3C0_PM_TRIGGER 0x0140 +#define NVC3C0_PM_TRIGGER_V 31:0 + +#define NVC3C0_PM_TRIGGER_WFI 0x0144 +#define NVC3C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC3C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC3C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC3C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC3C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC3C0_LINE_LENGTH_IN 0x0180 +#define NVC3C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC3C0_LINE_COUNT 0x0184 +#define NVC3C0_LINE_COUNT_VALUE 31:0 + +#define NVC3C0_OFFSET_OUT_UPPER 0x0188 +#define NVC3C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC3C0_OFFSET_OUT 0x018c +#define NVC3C0_OFFSET_OUT_VALUE 31:0 + +#define NVC3C0_PITCH_OUT 0x0190 +#define NVC3C0_PITCH_OUT_VALUE 31:0 + +#define NVC3C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC3C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC3C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC3C0_SET_DST_WIDTH 0x0198 +#define NVC3C0_SET_DST_WIDTH_V 31:0 + +#define NVC3C0_SET_DST_HEIGHT 0x019c +#define NVC3C0_SET_DST_HEIGHT_V 31:0 + +#define NVC3C0_SET_DST_DEPTH 0x01a0 +#define NVC3C0_SET_DST_DEPTH_V 31:0 + +#define NVC3C0_SET_DST_LAYER 0x01a4 +#define NVC3C0_SET_DST_LAYER_V 31:0 + +#define NVC3C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC3C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC3C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC3C0_LAUNCH_DMA 0x01b0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC3C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC3C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC3C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC3C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC3C0_LOAD_INLINE_DATA 0x01b4 +#define NVC3C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC3C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC3C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC3C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC3C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC3C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC3C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC3C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC3C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC3C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC3C0_PERFMON_TRANSFER 0x0210 +#define NVC3C0_PERFMON_TRANSFER_V 31:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC3C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC3C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC3C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC3C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC3C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC3C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC3C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC3C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC3C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC3C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC3C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC3C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC3C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC3C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC3C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC3C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC3C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC3C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC3C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC3C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC3C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC3C0_SET_SCG_CONTROL 0x0270 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC3C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC3C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC3C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_SET_QMD_VERSION 0x0288 +#define NVC3C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_CHECK_QMD_VERSION 0x0290 +#define NVC3C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC3C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC3C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC3C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC3C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC3C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC3C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC3C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC3C0_SEND_PCAS_A 0x02b4 +#define NVC3C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC3C0_SEND_PCAS_B 0x02b8 +#define NVC3C0_SEND_PCAS_B_FROM 23:0 +#define NVC3C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC3C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC3C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC3C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC3C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC3C0_SET_SPA_VERSION 0x0310 +#define NVC3C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC3C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC3C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC3C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC3C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC3C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC3C0_SET_FALCON00 0x0500 +#define NVC3C0_SET_FALCON00_V 31:0 + +#define NVC3C0_SET_FALCON01 0x0504 +#define NVC3C0_SET_FALCON01_V 31:0 + +#define NVC3C0_SET_FALCON02 0x0508 +#define NVC3C0_SET_FALCON02_V 31:0 + +#define NVC3C0_SET_FALCON03 0x050c +#define NVC3C0_SET_FALCON03_V 31:0 + +#define NVC3C0_SET_FALCON04 0x0510 +#define NVC3C0_SET_FALCON04_V 31:0 + +#define NVC3C0_SET_FALCON05 0x0514 +#define NVC3C0_SET_FALCON05_V 31:0 + +#define NVC3C0_SET_FALCON06 0x0518 +#define NVC3C0_SET_FALCON06_V 31:0 + +#define NVC3C0_SET_FALCON07 0x051c +#define NVC3C0_SET_FALCON07_V 31:0 + +#define NVC3C0_SET_FALCON08 0x0520 +#define NVC3C0_SET_FALCON08_V 31:0 + +#define NVC3C0_SET_FALCON09 0x0524 +#define NVC3C0_SET_FALCON09_V 31:0 + +#define NVC3C0_SET_FALCON10 0x0528 +#define NVC3C0_SET_FALCON10_V 31:0 + +#define NVC3C0_SET_FALCON11 0x052c +#define NVC3C0_SET_FALCON11_V 31:0 + +#define NVC3C0_SET_FALCON12 0x0530 +#define NVC3C0_SET_FALCON12_V 31:0 + +#define NVC3C0_SET_FALCON13 0x0534 +#define NVC3C0_SET_FALCON13_V 31:0 + +#define NVC3C0_SET_FALCON14 0x0538 +#define NVC3C0_SET_FALCON14_V 31:0 + +#define NVC3C0_SET_FALCON15 0x053c +#define NVC3C0_SET_FALCON15_V 31:0 + +#define NVC3C0_SET_FALCON16 0x0540 +#define NVC3C0_SET_FALCON16_V 31:0 + +#define NVC3C0_SET_FALCON17 0x0544 +#define NVC3C0_SET_FALCON17_V 31:0 + +#define NVC3C0_SET_FALCON18 0x0548 +#define NVC3C0_SET_FALCON18_V 31:0 + +#define NVC3C0_SET_FALCON19 0x054c +#define NVC3C0_SET_FALCON19_V 31:0 + +#define NVC3C0_SET_FALCON20 0x0550 +#define NVC3C0_SET_FALCON20_V 31:0 + +#define NVC3C0_SET_FALCON21 0x0554 +#define NVC3C0_SET_FALCON21_V 31:0 + +#define NVC3C0_SET_FALCON22 0x0558 +#define NVC3C0_SET_FALCON22_V 31:0 + +#define NVC3C0_SET_FALCON23 0x055c +#define NVC3C0_SET_FALCON23_V 31:0 + +#define NVC3C0_SET_FALCON24 0x0560 +#define NVC3C0_SET_FALCON24_V 31:0 + +#define NVC3C0_SET_FALCON25 0x0564 +#define NVC3C0_SET_FALCON25_V 31:0 + +#define NVC3C0_SET_FALCON26 0x0568 +#define NVC3C0_SET_FALCON26_V 31:0 + +#define NVC3C0_SET_FALCON27 0x056c +#define NVC3C0_SET_FALCON27_V 31:0 + +#define NVC3C0_SET_FALCON28 0x0570 +#define NVC3C0_SET_FALCON28_V 31:0 + +#define NVC3C0_SET_FALCON29 0x0574 +#define NVC3C0_SET_FALCON29_V 31:0 + +#define NVC3C0_SET_FALCON30 0x0578 +#define NVC3C0_SET_FALCON30_V 31:0 + +#define NVC3C0_SET_FALCON31 0x057c +#define NVC3C0_SET_FALCON31_V 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC3C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC3C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC3C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL 0x120c +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL 0x1210 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_ALL_V 0:0 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC3C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC3C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC3C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC3C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC3C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC3C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC3C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC3C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC3C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC3C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC3C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC3C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC3C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC3C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC3C0_PIPE_NOP 0x1a2c +#define NVC3C0_PIPE_NOP_V 31:0 + +#define NVC3C0_SET_SPARE00 0x1a30 +#define NVC3C0_SET_SPARE00_V 31:0 + +#define NVC3C0_SET_SPARE01 0x1a34 +#define NVC3C0_SET_SPARE01_V 31:0 + +#define NVC3C0_SET_SPARE02 0x1a38 +#define NVC3C0_SET_SPARE02_V 31:0 + +#define NVC3C0_SET_SPARE03 0x1a3c +#define NVC3C0_SET_SPARE03_V 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC3C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC3C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC3C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC3C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 + +#define NVC3C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC3C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC3C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC3C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC3C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC3C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC3C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC3C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC3C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC3C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC3C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC3C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC3C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_volta_compute_a_h_ */ diff --git a/Compute-Class-Methods/clc5c0.h b/Compute-Class-Methods/clc5c0.h new file mode 100644 index 0000000..3d0fd54 --- /dev/null +++ b/Compute-Class-Methods/clc5c0.h @@ -0,0 +1,942 @@ +/* + * Copyright (c) 2003-2004, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _cl_turing_compute_a_h_ +#define _cl_turing_compute_a_h_ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ +/* Command: ../../../../class/bin/sw_header.pl turing_compute_a */ + +#include "nvtypes.h" + +#define TURING_COMPUTE_A 0xC5C0 + +typedef volatile struct turing_compute_a_struct { + NvU32 SetObject; + NvU32 Reserved_0x04[0x3F]; + NvU32 NoOperation; + NvU32 SetNotifyA; + NvU32 SetNotifyB; + NvU32 Notify; + NvU32 WaitForIdle; + NvU32 Reserved_0x114[0x7]; + NvU32 SetGlobalRenderEnableA; + NvU32 SetGlobalRenderEnableB; + NvU32 SetGlobalRenderEnableC; + NvU32 SendGoIdle; + NvU32 PmTrigger; + NvU32 PmTriggerWfi; + NvU32 FeAtomicSequenceBegin; + NvU32 FeAtomicSequenceEnd; + NvU32 SetInstrumentationMethodHeader; + NvU32 SetInstrumentationMethodData; + NvU32 Reserved_0x158[0xA]; + NvU32 LineLengthIn; + NvU32 LineCount; + NvU32 OffsetOutUpper; + NvU32 OffsetOut; + NvU32 PitchOut; + NvU32 SetDstBlockSize; + NvU32 SetDstWidth; + NvU32 SetDstHeight; + NvU32 SetDstDepth; + NvU32 SetDstLayer; + NvU32 SetDstOriginBytesX; + NvU32 SetDstOriginSamplesY; + NvU32 LaunchDma; + NvU32 LoadInlineData; + NvU32 Reserved_0x1B8[0x9]; + NvU32 SetI2mSemaphoreA; + NvU32 SetI2mSemaphoreB; + NvU32 SetI2mSemaphoreC; + NvU32 SetSmScgControl; + NvU32 Reserved_0x1EC[0x1]; + NvU32 SetI2mSpareNoop00; + NvU32 SetI2mSpareNoop01; + NvU32 SetI2mSpareNoop02; + NvU32 SetI2mSpareNoop03; + NvU32 SetValidSpanOverflowAreaA; + NvU32 SetValidSpanOverflowAreaB; + NvU32 SetValidSpanOverflowAreaC; + NvU32 Reserved_0x20C[0x1]; + NvU32 PerfmonTransfer; + NvU32 SetQmdVirtualizationBaseA; + NvU32 SetQmdVirtualizationBaseB; + NvU32 InvalidateShaderCaches; + NvU32 SetReservedSwMethod00; + NvU32 SetReservedSwMethod01; + NvU32 SetReservedSwMethod02; + NvU32 SetReservedSwMethod03; + NvU32 SetReservedSwMethod04; + NvU32 SetReservedSwMethod05; + NvU32 SetReservedSwMethod06; + NvU32 SetReservedSwMethod07; + NvU32 Reserved_0x240[0x1]; + NvU32 InvalidateTextureHeaderCacheNoWfi; + NvU32 SetCwdRefCounter; + NvU32 SetReservedSwMethod08; + NvU32 SetReservedSwMethod09; + NvU32 SetReservedSwMethod10; + NvU32 SetReservedSwMethod11; + NvU32 SetReservedSwMethod12; + NvU32 SetReservedSwMethod13; + NvU32 SetReservedSwMethod14; + NvU32 SetReservedSwMethod15; + NvU32 Reserved_0x26C[0x1]; + NvU32 SetScgControl; + NvU32 Reserved_0x274[0x3]; + NvU32 SetComputeClassVersion; + NvU32 CheckComputeClassVersion; + NvU32 SetQmdVersion; + NvU32 Reserved_0x28C[0x1]; + NvU32 CheckQmdVersion; + NvU32 Reserved_0x294[0x1]; + NvU32 InvalidateSkedCaches; + NvU32 SetQmdVirtualizationControl; + NvU32 SetShaderSharedMemoryWindowA; + NvU32 SetShaderSharedMemoryWindowB; + NvU32 ScgHysteresisControl; + NvU32 Reserved_0x2AC[0x1]; + NvU32 SetCwdSlotCount; + NvU32 SendPcasA; + NvU32 SendPcasB; + NvU32 SendSignalingPcasB; + NvU32 Reserved_0x2C0[0x3]; + NvU32 SetSkedCacheControl; + NvU32 Reserved_0x2D0[0x5]; + NvU32 SetShaderLocalMemoryNonThrottledA; + NvU32 SetShaderLocalMemoryNonThrottledB; + NvU32 SetShaderLocalMemoryNonThrottledC; + NvU32 Reserved_0x2F0[0x8]; + NvU32 SetSpaVersion; + NvU32 Reserved_0x314[0x1]; + NvU32 SetInlineQmdAddressA; + NvU32 SetInlineQmdAddressB; + NvU32 LoadInlineQmdData[0x40]; + NvU32 Reserved_0x420[0x38]; + NvU32 SetFalcon00; + NvU32 SetFalcon01; + NvU32 SetFalcon02; + NvU32 SetFalcon03; + NvU32 SetFalcon04; + NvU32 SetFalcon05; + NvU32 SetFalcon06; + NvU32 SetFalcon07; + NvU32 SetFalcon08; + NvU32 SetFalcon09; + NvU32 SetFalcon10; + NvU32 SetFalcon11; + NvU32 SetFalcon12; + NvU32 SetFalcon13; + NvU32 SetFalcon14; + NvU32 SetFalcon15; + NvU32 SetFalcon16; + NvU32 SetFalcon17; + NvU32 SetFalcon18; + NvU32 SetFalcon19; + NvU32 SetFalcon20; + NvU32 SetFalcon21; + NvU32 SetFalcon22; + NvU32 SetFalcon23; + NvU32 SetFalcon24; + NvU32 SetFalcon25; + NvU32 SetFalcon26; + NvU32 SetFalcon27; + NvU32 SetFalcon28; + NvU32 SetFalcon29; + NvU32 SetFalcon30; + NvU32 SetFalcon31; + NvU32 Reserved_0x580[0x84]; + NvU32 SetShaderLocalMemoryA; + NvU32 SetShaderLocalMemoryB; + NvU32 Reserved_0x798[0x6]; + NvU32 SetShaderLocalMemoryWindowA; + NvU32 SetShaderLocalMemoryWindowB; + NvU32 Reserved_0x7B8[0x177]; + NvU32 SetShaderCacheControl; + NvU32 Reserved_0xD98[0x2]; + NvU32 SetScgComputeSchedulingParameters[0x10]; + NvU32 Reserved_0xDE0[0x1]; + NvU32 SetSmTimeoutInterval; + NvU32 Reserved_0xDE8[0x128]; + NvU32 InvalidateTextureDataCacheNoWfi; + NvU32 Reserved_0x128C[0x7]; + NvU32 ActivatePerfSettingsForComputeContext; + NvU32 Reserved_0x12AC[0x21]; + NvU32 InvalidateSamplerCache; + NvU32 InvalidateTextureHeaderCache; + NvU32 InvalidateTextureDataCache; + NvU32 Reserved_0x133C[0x3A]; + NvU32 InvalidateSamplerCacheNoWfi; + NvU32 Reserved_0x1428[0x40]; + NvU32 SetShaderExceptions; + NvU32 Reserved_0x152C[0x9]; + NvU32 SetRenderEnableA; + NvU32 SetRenderEnableB; + NvU32 SetRenderEnableC; + NvU32 SetTexSamplerPoolA; + NvU32 SetTexSamplerPoolB; + NvU32 SetTexSamplerPoolC; + NvU32 Reserved_0x1568[0x3]; + NvU32 SetTexHeaderPoolA; + NvU32 SetTexHeaderPoolB; + NvU32 SetTexHeaderPoolC; + NvU32 Reserved_0x1580[0x46]; + NvU32 InvalidateShaderCachesNoWfi; + NvU32 Reserved_0x169C[0xAA]; + NvU32 SetRenderEnableOverride; + NvU32 Reserved_0x1948[0x37]; + NvU32 Reserved_0x1A28[0x1]; + NvU32 PipeNop; + NvU32 SetSpare00; + NvU32 SetSpare01; + NvU32 SetSpare02; + NvU32 SetSpare03; + NvU32 Reserved_0x1A40[0x30]; + NvU32 SetReportSemaphoreA; + NvU32 SetReportSemaphoreB; + NvU32 SetReportSemaphoreC; + NvU32 SetReportSemaphoreD; + NvU32 Reserved_0x1B10[0x2BA]; + NvU32 SetTrapHandlerA; + NvU32 SetTrapHandlerB; + NvU32 Reserved_0x2600[0x2]; + NvU32 SetBindlessTexture; + NvU32 Reserved_0x260C[0x33A]; + NvU32 SetShaderPerformanceSnapshotCounterValue[0x8]; + NvU32 SetShaderPerformanceSnapshotCounterValueUpper[0x8]; + NvU32 EnableShaderPerformanceSnapshotCounter; + NvU32 DisableShaderPerformanceSnapshotCounter; + NvU32 SetShaderPerformanceCounterValueUpper[0x8]; + NvU32 SetShaderPerformanceCounterValue[0x8]; + NvU32 SetShaderPerformanceCounterEvent[0x8]; + NvU32 SetShaderPerformanceCounterControlA[0x8]; + NvU32 SetShaderPerformanceCounterControlB[0x8]; + NvU32 SetShaderPerformanceCounterTrapControl; + NvU32 StartShaderPerformanceCounter; + NvU32 StopShaderPerformanceCounter; + NvU32 SetShaderPerformanceCounterSctlFilter; + NvU32 SetShaderPerformanceCounterCoreMioFilter; + NvU32 Reserved_0x33F0[0x4]; + NvU32 SetMmeShadowScratch[0x8]; +} turing_compute_a_t; + + +#define NVC5C0_SET_OBJECT 0x0000 +#define NVC5C0_SET_OBJECT_CLASS_ID 15:0 +#define NVC5C0_SET_OBJECT_ENGINE_ID 20:16 + +#define NVC5C0_NO_OPERATION 0x0100 +#define NVC5C0_NO_OPERATION_V 31:0 + +#define NVC5C0_SET_NOTIFY_A 0x0104 +#define NVC5C0_SET_NOTIFY_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_NOTIFY_B 0x0108 +#define NVC5C0_SET_NOTIFY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_NOTIFY 0x010c +#define NVC5C0_NOTIFY_TYPE 31:0 +#define NVC5C0_NOTIFY_TYPE_WRITE_ONLY 0x00000000 +#define NVC5C0_NOTIFY_TYPE_WRITE_THEN_AWAKEN 0x00000001 + +#define NVC5C0_WAIT_FOR_IDLE 0x0110 +#define NVC5C0_WAIT_FOR_IDLE_V 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A 0x0130 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B 0x0134 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C 0x0138 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_GLOBAL_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SEND_GO_IDLE 0x013c +#define NVC5C0_SEND_GO_IDLE_V 31:0 + +#define NVC5C0_PM_TRIGGER 0x0140 +#define NVC5C0_PM_TRIGGER_V 31:0 + +#define NVC5C0_PM_TRIGGER_WFI 0x0144 +#define NVC5C0_PM_TRIGGER_WFI_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN 0x0148 +#define NVC5C0_FE_ATOMIC_SEQUENCE_BEGIN_V 31:0 + +#define NVC5C0_FE_ATOMIC_SEQUENCE_END 0x014c +#define NVC5C0_FE_ATOMIC_SEQUENCE_END_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER 0x0150 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_HEADER_V 31:0 + +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA 0x0154 +#define NVC5C0_SET_INSTRUMENTATION_METHOD_DATA_V 31:0 + +#define NVC5C0_LINE_LENGTH_IN 0x0180 +#define NVC5C0_LINE_LENGTH_IN_VALUE 31:0 + +#define NVC5C0_LINE_COUNT 0x0184 +#define NVC5C0_LINE_COUNT_VALUE 31:0 + +#define NVC5C0_OFFSET_OUT_UPPER 0x0188 +#define NVC5C0_OFFSET_OUT_UPPER_VALUE 16:0 + +#define NVC5C0_OFFSET_OUT 0x018c +#define NVC5C0_OFFSET_OUT_VALUE 31:0 + +#define NVC5C0_PITCH_OUT 0x0190 +#define NVC5C0_PITCH_OUT_VALUE 31:0 + +#define NVC5C0_SET_DST_BLOCK_SIZE 0x0194 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH 3:0 +#define NVC5C0_SET_DST_BLOCK_SIZE_WIDTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT 7:4 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_HEIGHT_THIRTYTWO_GOBS 0x00000005 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH 11:8 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_ONE_GOB 0x00000000 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_TWO_GOBS 0x00000001 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_FOUR_GOBS 0x00000002 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_EIGHT_GOBS 0x00000003 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_SIXTEEN_GOBS 0x00000004 +#define NVC5C0_SET_DST_BLOCK_SIZE_DEPTH_THIRTYTWO_GOBS 0x00000005 + +#define NVC5C0_SET_DST_WIDTH 0x0198 +#define NVC5C0_SET_DST_WIDTH_V 31:0 + +#define NVC5C0_SET_DST_HEIGHT 0x019c +#define NVC5C0_SET_DST_HEIGHT_V 31:0 + +#define NVC5C0_SET_DST_DEPTH 0x01a0 +#define NVC5C0_SET_DST_DEPTH_V 31:0 + +#define NVC5C0_SET_DST_LAYER 0x01a4 +#define NVC5C0_SET_DST_LAYER_V 31:0 + +#define NVC5C0_SET_DST_ORIGIN_BYTES_X 0x01a8 +#define NVC5C0_SET_DST_ORIGIN_BYTES_X_V 20:0 + +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y 0x01ac +#define NVC5C0_SET_DST_ORIGIN_SAMPLES_Y_V 16:0 + +#define NVC5C0_LAUNCH_DMA 0x01b0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT 0:0 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_BLOCKLINEAR 0x00000000 +#define NVC5C0_LAUNCH_DMA_DST_MEMORY_LAYOUT_PITCH 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE 5:4 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_DISABLE 0x00000000 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_FLUSH_ONLY 0x00000001 +#define NVC5C0_LAUNCH_DMA_COMPLETION_TYPE_RELEASE_SEMAPHORE 0x00000002 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE 9:8 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_NONE 0x00000000 +#define NVC5C0_LAUNCH_DMA_INTERRUPT_TYPE_INTERRUPT 0x00000001 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE 12:12 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_LAUNCH_DMA_SEMAPHORE_STRUCT_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE 1:1 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP 15:13 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_LAUNCH_DMA_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT 3:2 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_LAUNCH_DMA_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE 6:6 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_FALSE 0x00000000 +#define NVC5C0_LAUNCH_DMA_SYSMEMBAR_DISABLE_TRUE 0x00000001 + +#define NVC5C0_LOAD_INLINE_DATA 0x01b4 +#define NVC5C0_LOAD_INLINE_DATA_V 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_A 0x01dc +#define NVC5C0_SET_I2M_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_B 0x01e0 +#define NVC5C0_SET_I2M_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_I2M_SEMAPHORE_C 0x01e4 +#define NVC5C0_SET_I2M_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_SM_SCG_CONTROL 0x01e8 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS 0:0 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_FALSE 0x00000000 +#define NVC5C0_SET_SM_SCG_CONTROL_COMPUTE_IN_GRAPHICS_TRUE 0x00000001 + +#define NVC5C0_SET_I2M_SPARE_NOOP00 0x01f0 +#define NVC5C0_SET_I2M_SPARE_NOOP00_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP01 0x01f4 +#define NVC5C0_SET_I2M_SPARE_NOOP01_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP02 0x01f8 +#define NVC5C0_SET_I2M_SPARE_NOOP02_V 31:0 + +#define NVC5C0_SET_I2M_SPARE_NOOP03 0x01fc +#define NVC5C0_SET_I2M_SPARE_NOOP03_V 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A 0x0200 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B 0x0204 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C 0x0208 +#define NVC5C0_SET_VALID_SPAN_OVERFLOW_AREA_C_SIZE 31:0 + +#define NVC5C0_PERFMON_TRANSFER 0x0210 +#define NVC5C0_PERFMON_TRANSFER_V 31:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A 0x0214 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_A_ADDRESS_UPPER 7:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B 0x0218 +#define NVC5C0_SET_QMD_VIRTUALIZATION_BASE_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES 0x021c +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_CONSTANT_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS 1:1 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_LOCKS_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA 2:2 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_FLUSH_DATA_TRUE 0x00000001 + +#define NVC5C0_SET_RESERVED_SW_METHOD00 0x0220 +#define NVC5C0_SET_RESERVED_SW_METHOD00_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD01 0x0224 +#define NVC5C0_SET_RESERVED_SW_METHOD01_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD02 0x0228 +#define NVC5C0_SET_RESERVED_SW_METHOD02_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD03 0x022c +#define NVC5C0_SET_RESERVED_SW_METHOD03_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD04 0x0230 +#define NVC5C0_SET_RESERVED_SW_METHOD04_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD05 0x0234 +#define NVC5C0_SET_RESERVED_SW_METHOD05_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD06 0x0238 +#define NVC5C0_SET_RESERVED_SW_METHOD06_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD07 0x023c +#define NVC5C0_SET_RESERVED_SW_METHOD07_V 31:0 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI 0x0244 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_CWD_REF_COUNTER 0x0248 +#define NVC5C0_SET_CWD_REF_COUNTER_SELECT 5:0 +#define NVC5C0_SET_CWD_REF_COUNTER_VALUE 23:8 + +#define NVC5C0_SET_RESERVED_SW_METHOD08 0x024c +#define NVC5C0_SET_RESERVED_SW_METHOD08_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD09 0x0250 +#define NVC5C0_SET_RESERVED_SW_METHOD09_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD10 0x0254 +#define NVC5C0_SET_RESERVED_SW_METHOD10_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD11 0x0258 +#define NVC5C0_SET_RESERVED_SW_METHOD11_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD12 0x025c +#define NVC5C0_SET_RESERVED_SW_METHOD12_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD13 0x0260 +#define NVC5C0_SET_RESERVED_SW_METHOD13_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD14 0x0264 +#define NVC5C0_SET_RESERVED_SW_METHOD14_V 31:0 + +#define NVC5C0_SET_RESERVED_SW_METHOD15 0x0268 +#define NVC5C0_SET_RESERVED_SW_METHOD15_V 31:0 + +#define NVC5C0_SET_SCG_CONTROL 0x0270 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MAX_SM_COUNT 8:0 +#define NVC5C0_SET_SCG_CONTROL_COMPUTE1_MIN_SM_COUNT 20:12 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE 24:24 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_FALSE 0x00000000 +#define NVC5C0_SET_SCG_CONTROL_DISABLE_COMPUTE1_LIMIT_IN_ALL_COMPUTE_TRUE 0x00000001 + +#define NVC5C0_SET_COMPUTE_CLASS_VERSION 0x0280 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_SET_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION 0x0284 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_COMPUTE_CLASS_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_SET_QMD_VERSION 0x0288 +#define NVC5C0_SET_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_SET_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_CHECK_QMD_VERSION 0x0290 +#define NVC5C0_CHECK_QMD_VERSION_CURRENT 15:0 +#define NVC5C0_CHECK_QMD_VERSION_OLDEST_SUPPORTED 31:16 + +#define NVC5C0_INVALIDATE_SKED_CACHES 0x0298 +#define NVC5C0_INVALIDATE_SKED_CACHES_V 0:0 + +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL 0x029c +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_CONSTANT_BUFFER_MASK 7:0 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE 8:8 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE 12:12 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_I2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE 16:16 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_ADDR_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE 20:20 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_IQ2M_CONSTANT_BUFFER_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE 24:24 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_QMD_VIRTUALIZATION_CONTROL_SEND_PCAS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A 0x02a0 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B 0x02a4 +#define NVC5C0_SET_SHADER_SHARED_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SCG_HYSTERESIS_CONTROL 0x02a8 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE 0:0 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_TIMEOUT_ONCE_TRUE 0x00000001 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE 1:1 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_FALSE 0x00000000 +#define NVC5C0_SCG_HYSTERESIS_CONTROL_USE_NULL_TIMEOUT_ONCE_TRUE 0x00000001 + +#define NVC5C0_SET_CWD_SLOT_COUNT 0x02b0 +#define NVC5C0_SET_CWD_SLOT_COUNT_V 7:0 + +#define NVC5C0_SEND_PCAS_A 0x02b4 +#define NVC5C0_SEND_PCAS_A_QMD_ADDRESS_SHIFTED8 31:0 + +#define NVC5C0_SEND_PCAS_B 0x02b8 +#define NVC5C0_SEND_PCAS_B_FROM 23:0 +#define NVC5C0_SEND_PCAS_B_DELTA 31:24 + +#define NVC5C0_SEND_SIGNALING_PCAS_B 0x02bc +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE 0:0 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_INVALIDATE_TRUE 0x00000001 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE 1:1 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_FALSE 0x00000000 +#define NVC5C0_SEND_SIGNALING_PCAS_B_SCHEDULE_TRUE 0x00000001 + +#define NVC5C0_SET_SKED_CACHE_CONTROL 0x02cc +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID 0:0 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_FALSE 0x00000000 +#define NVC5C0_SET_SKED_CACHE_CONTROL_IGNORE_VEID_TRUE 0x00000001 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A 0x02e4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_A_SIZE_UPPER 7:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B 0x02e8 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_B_SIZE_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C 0x02ec +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_NON_THROTTLED_C_MAX_SM_COUNT 8:0 + +#define NVC5C0_SET_SPA_VERSION 0x0310 +#define NVC5C0_SET_SPA_VERSION_MINOR 7:0 +#define NVC5C0_SET_SPA_VERSION_MAJOR 15:8 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A 0x0318 +#define NVC5C0_SET_INLINE_QMD_ADDRESS_A_QMD_ADDRESS_SHIFTED8_UPPER 31:0 + +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B 0x031c +#define NVC5C0_SET_INLINE_QMD_ADDRESS_B_QMD_ADDRESS_SHIFTED8_LOWER 31:0 + +#define NVC5C0_LOAD_INLINE_QMD_DATA(i) (0x0320+(i)*4) +#define NVC5C0_LOAD_INLINE_QMD_DATA_V 31:0 + +#define NVC5C0_SET_FALCON00 0x0500 +#define NVC5C0_SET_FALCON00_V 31:0 + +#define NVC5C0_SET_FALCON01 0x0504 +#define NVC5C0_SET_FALCON01_V 31:0 + +#define NVC5C0_SET_FALCON02 0x0508 +#define NVC5C0_SET_FALCON02_V 31:0 + +#define NVC5C0_SET_FALCON03 0x050c +#define NVC5C0_SET_FALCON03_V 31:0 + +#define NVC5C0_SET_FALCON04 0x0510 +#define NVC5C0_SET_FALCON04_V 31:0 + +#define NVC5C0_SET_FALCON05 0x0514 +#define NVC5C0_SET_FALCON05_V 31:0 + +#define NVC5C0_SET_FALCON06 0x0518 +#define NVC5C0_SET_FALCON06_V 31:0 + +#define NVC5C0_SET_FALCON07 0x051c +#define NVC5C0_SET_FALCON07_V 31:0 + +#define NVC5C0_SET_FALCON08 0x0520 +#define NVC5C0_SET_FALCON08_V 31:0 + +#define NVC5C0_SET_FALCON09 0x0524 +#define NVC5C0_SET_FALCON09_V 31:0 + +#define NVC5C0_SET_FALCON10 0x0528 +#define NVC5C0_SET_FALCON10_V 31:0 + +#define NVC5C0_SET_FALCON11 0x052c +#define NVC5C0_SET_FALCON11_V 31:0 + +#define NVC5C0_SET_FALCON12 0x0530 +#define NVC5C0_SET_FALCON12_V 31:0 + +#define NVC5C0_SET_FALCON13 0x0534 +#define NVC5C0_SET_FALCON13_V 31:0 + +#define NVC5C0_SET_FALCON14 0x0538 +#define NVC5C0_SET_FALCON14_V 31:0 + +#define NVC5C0_SET_FALCON15 0x053c +#define NVC5C0_SET_FALCON15_V 31:0 + +#define NVC5C0_SET_FALCON16 0x0540 +#define NVC5C0_SET_FALCON16_V 31:0 + +#define NVC5C0_SET_FALCON17 0x0544 +#define NVC5C0_SET_FALCON17_V 31:0 + +#define NVC5C0_SET_FALCON18 0x0548 +#define NVC5C0_SET_FALCON18_V 31:0 + +#define NVC5C0_SET_FALCON19 0x054c +#define NVC5C0_SET_FALCON19_V 31:0 + +#define NVC5C0_SET_FALCON20 0x0550 +#define NVC5C0_SET_FALCON20_V 31:0 + +#define NVC5C0_SET_FALCON21 0x0554 +#define NVC5C0_SET_FALCON21_V 31:0 + +#define NVC5C0_SET_FALCON22 0x0558 +#define NVC5C0_SET_FALCON22_V 31:0 + +#define NVC5C0_SET_FALCON23 0x055c +#define NVC5C0_SET_FALCON23_V 31:0 + +#define NVC5C0_SET_FALCON24 0x0560 +#define NVC5C0_SET_FALCON24_V 31:0 + +#define NVC5C0_SET_FALCON25 0x0564 +#define NVC5C0_SET_FALCON25_V 31:0 + +#define NVC5C0_SET_FALCON26 0x0568 +#define NVC5C0_SET_FALCON26_V 31:0 + +#define NVC5C0_SET_FALCON27 0x056c +#define NVC5C0_SET_FALCON27_V 31:0 + +#define NVC5C0_SET_FALCON28 0x0570 +#define NVC5C0_SET_FALCON28_V 31:0 + +#define NVC5C0_SET_FALCON29 0x0574 +#define NVC5C0_SET_FALCON29_V 31:0 + +#define NVC5C0_SET_FALCON30 0x0578 +#define NVC5C0_SET_FALCON30_V 31:0 + +#define NVC5C0_SET_FALCON31 0x057c +#define NVC5C0_SET_FALCON31_V 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A 0x0790 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B 0x0794 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A 0x07b0 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_A_BASE_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B 0x07b4 +#define NVC5C0_SET_SHADER_LOCAL_MEMORY_WINDOW_B_BASE_ADDRESS 31:0 + +#define NVC5C0_SET_SHADER_CACHE_CONTROL 0x0d94 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE 0:0 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_CACHE_CONTROL_ICACHE_PREFETCH_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS(i) (0x0da0+(i)*4) +#define NVC5C0_SET_SCG_COMPUTE_SCHEDULING_PARAMETERS_V 31:0 + +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL 0x0de4 +#define NVC5C0_SET_SM_TIMEOUT_INTERVAL_COUNTER_BIT 5:0 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI 0x1288 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT 0x12a8 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL 0:0 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_FALSE 0x00000000 +#define NVC5C0_ACTIVATE_PERF_SETTINGS_FOR_COMPUTE_CONTEXT_ALL_TRUE 0x00000001 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE 0x1330 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE 0x1334 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_HEADER_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE 0x1338 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES 0:0 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_TEXTURE_DATA_CACHE_TAG 25:4 + +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI 0x1424 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES 0:0 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ALL 0x00000000 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_LINES_ONE 0x00000001 +#define NVC5C0_INVALIDATE_SAMPLER_CACHE_NO_WFI_TAG 25:4 + +#define NVC5C0_SET_SHADER_EXCEPTIONS 0x1528 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE 0:0 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_SHADER_EXCEPTIONS_ENABLE_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_A 0x1550 +#define NVC5C0_SET_RENDER_ENABLE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_RENDER_ENABLE_B 0x1554 +#define NVC5C0_SET_RENDER_ENABLE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_RENDER_ENABLE_C 0x1558 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE 2:0 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_FALSE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_TRUE 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_CONDITIONAL 0x00000002 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_EQUAL 0x00000003 +#define NVC5C0_SET_RENDER_ENABLE_C_MODE_RENDER_IF_NOT_EQUAL 0x00000004 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_A 0x155c +#define NVC5C0_SET_TEX_SAMPLER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_B 0x1560 +#define NVC5C0_SET_TEX_SAMPLER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_SAMPLER_POOL_C 0x1564 +#define NVC5C0_SET_TEX_SAMPLER_POOL_C_MAXIMUM_INDEX 19:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_A 0x1574 +#define NVC5C0_SET_TEX_HEADER_POOL_A_OFFSET_UPPER 16:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_B 0x1578 +#define NVC5C0_SET_TEX_HEADER_POOL_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_TEX_HEADER_POOL_C 0x157c +#define NVC5C0_SET_TEX_HEADER_POOL_C_MAXIMUM_INDEX 21:0 + +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI 0x1698 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION 0:0 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_INSTRUCTION_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA 4:4 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_GLOBAL_DATA_TRUE 0x00000001 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT 12:12 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_FALSE 0x00000000 +#define NVC5C0_INVALIDATE_SHADER_CACHES_NO_WFI_CONSTANT_TRUE 0x00000001 + +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE 0x1944 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE 1:0 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_USE_RENDER_ENABLE 0x00000000 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_ALWAYS_RENDER 0x00000001 +#define NVC5C0_SET_RENDER_ENABLE_OVERRIDE_MODE_NEVER_RENDER 0x00000002 + +#define NVC5C0_PIPE_NOP 0x1a2c +#define NVC5C0_PIPE_NOP_V 31:0 + +#define NVC5C0_SET_SPARE00 0x1a30 +#define NVC5C0_SET_SPARE00_V 31:0 + +#define NVC5C0_SET_SPARE01 0x1a34 +#define NVC5C0_SET_SPARE01_V 31:0 + +#define NVC5C0_SET_SPARE02 0x1a38 +#define NVC5C0_SET_SPARE02_V 31:0 + +#define NVC5C0_SET_SPARE03 0x1a3c +#define NVC5C0_SET_SPARE03_V 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_A 0x1b00 +#define NVC5C0_SET_REPORT_SEMAPHORE_A_OFFSET_UPPER 7:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_B 0x1b04 +#define NVC5C0_SET_REPORT_SEMAPHORE_B_OFFSET_LOWER 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_C 0x1b08 +#define NVC5C0_SET_REPORT_SEMAPHORE_C_PAYLOAD 31:0 + +#define NVC5C0_SET_REPORT_SEMAPHORE_D 0x1b0c +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION 1:0 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_RELEASE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_OPERATION_TRAP 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE 20:20 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_AWAKEN_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE 28:28 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE 2:2 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_FLUSH_DISABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE 3:3 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP 11:9 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT 18:17 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP 19:19 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_FALSE 0x00000000 +#define NVC5C0_SET_REPORT_SEMAPHORE_D_CONDITIONAL_TRAP_TRUE 0x00000001 + +#define NVC5C0_SET_TRAP_HANDLER_A 0x25f8 +#define NVC5C0_SET_TRAP_HANDLER_A_ADDRESS_UPPER 16:0 + +#define NVC5C0_SET_TRAP_HANDLER_B 0x25fc +#define NVC5C0_SET_TRAP_HANDLER_B_ADDRESS_LOWER 31:0 + +#define NVC5C0_SET_BINDLESS_TEXTURE 0x2608 +#define NVC5C0_SET_BINDLESS_TEXTURE_CONSTANT_BUFFER_SLOT_SELECT 2:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE(i) (0x32f4+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER(i) (0x3314+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3334 +#define NVC5C0_ENABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER 0x3338 +#define NVC5C0_DISABLE_SHADER_PERFORMANCE_SNAPSHOT_COUNTER_V 0:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER(i) (0x333c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_UPPER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE(i) (0x335c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_VALUE_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT(i) (0x337c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_EVENT_EVENT 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A(i) (0x339c+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT0 1:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT0 4:2 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT1 6:5 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT1 9:7 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT2 11:10 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT2 14:12 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT3 16:15 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT3 19:17 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT4 21:20 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT4 24:22 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_EVENT5 26:25 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_BIT_SELECT5 29:27 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_A_SPARE 31:30 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B(i) (0x33bc+(i)*4) +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_EDGE 0:0 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_MODE 2:1 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_WINDOWED 3:3 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CONTROL_B_FUNC 19:4 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL 0x33dc +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_TRAP_CONTROL_MASK 7:0 + +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER 0x33e0 +#define NVC5C0_START_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER 0x33e4 +#define NVC5C0_STOP_SHADER_PERFORMANCE_COUNTER_COUNTER_MASK 7:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER 0x33e8 +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_SCTL_FILTER_V 31:0 + +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER 0x33ec +#define NVC5C0_SET_SHADER_PERFORMANCE_COUNTER_CORE_MIO_FILTER_V 31:0 + +#define NVC5C0_SET_MME_SHADOW_SCRATCH(i) (0x3400+(i)*4) +#define NVC5C0_SET_MME_SHADOW_SCRATCH_V 31:0 + +#endif /* _cl_turing_compute_a_h_ */ diff --git a/Compute-QMD/clc3c0qmd.h b/Compute-QMD/clc3c0qmd.h new file mode 100644 index 0000000..588cc63 --- /dev/null +++ b/Compute-QMD/clc3c0qmd.h @@ -0,0 +1,245 @@ +/******************************************************************************* + Copyright (c) 2001-2010 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC3C0QMD_H__ +#define __CLC3C0QMD_H__ + +/* +** Queue Meta Data, Version 02_02 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC3C0_QMDV02_02_OUTER_PUT MW(30:0) +#define NVC3C0_QMDV02_02_OUTER_OVERFLOW MW(31:31) +#define NVC3C0_QMDV02_02_OUTER_GET MW(62:32) +#define NVC3C0_QMDV02_02_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC3C0_QMDV02_02_INNER_GET MW(94:64) +#define NVC3C0_QMDV02_02_INNER_OVERFLOW MW(95:95) +#define NVC3C0_QMDV02_02_INNER_PUT MW(126:96) +#define NVC3C0_QMDV02_02_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC3C0_QMDV02_02_QMD_GROUP_ID MW(133:128) +#define NVC3C0_QMDV02_02_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_IS_QUEUE MW(136:136) +#define NVC3C0_QMDV02_02_IS_QUEUE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_IS_QUEUE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_QMD_RESERVED_B MW(159:144) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC3C0_QMDV02_02_QMD_RESERVED_C MW(185:185) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC3C0_QMDV02_02_PROGRAM_OFFSET MW(287:256) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC3C0_QMDV02_02_QMD_RESERVED_D MW(335:328) +#define NVC3C0_QMDV02_02_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE MW(369:368) +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC3C0_QMDV02_02_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC3C0_QMDV02_02_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC3C0_QMDV02_02_SAMPLER_INDEX MW(382:382) +#define NVC3C0_QMDV02_02_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC3C0_QMDV02_02_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC3C0_QMDV02_02_CTA_RASTER_WIDTH MW(415:384) +#define NVC3C0_QMDV02_02_CTA_RASTER_HEIGHT MW(431:416) +#define NVC3C0_QMDV02_02_QMD_RESERVED13A MW(447:432) +#define NVC3C0_QMDV02_02_CTA_RASTER_DEPTH MW(463:448) +#define NVC3C0_QMDV02_02_QMD_RESERVED14A MW(479:464) +#define NVC3C0_QMDV02_02_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC3C0_QMDV02_02_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC3C0_QMDV02_02_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC3C0_QMDV02_02_SHARED_MEMORY_SIZE MW(561:544) +#define NVC3C0_QMDV02_02_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC3C0_QMDV02_02_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC3C0_QMDV02_02_QMD_VERSION MW(579:576) +#define NVC3C0_QMDV02_02_QMD_MAJOR_VERSION MW(583:580) +#define NVC3C0_QMDV02_02_QMD_RESERVED_H MW(591:584) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC3C0_QMDV02_02_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_REGISTER_COUNT_V MW(656:648) +#define NVC3C0_QMDV02_02_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC3C0_QMDV02_02_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC3C0_QMDV02_02_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC3C0_QMDV02_02_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC3C0_QMDV02_02_QMD_RESERVED_J MW(783:776) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_QMDV02_02_QMD_RESERVED_K MW(791:791) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE0_PAYLOAD MW(831:800) +#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC3C0_QMDV02_02_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC3C0_QMDV02_02_QMD_RESERVED_L MW(879:872) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC3C0_QMDV02_02_QMD_RESERVED_M MW(887:887) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC3C0_QMDV02_02_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC3C0_QMDV02_02_RELEASE1_PAYLOAD MW(927:896) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC3C0_QMDV02_02_QMD_RESERVED_N MW(954:952) +#define NVC3C0_QMDV02_02_BARRIER_COUNT MW(959:955) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC3C0_QMDV02_02_REGISTER_COUNT MW(991:984) +#define NVC3C0_QMDV02_02_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC3C0_QMDV02_02_SASS_VERSION MW(1023:1016) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC3C0_QMDV02_02_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC3C0_QMDV02_02_QMD_RESERVED_S MW(1599:1585) +#define NVC3C0_QMDV02_02_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC3C0_QMDV02_02_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC3C0_QMDV02_02_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC3C0_QMDV02_02_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC3C0_QMDV02_02_QMD_RESERVED_Q MW(1694:1694) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC3C0_QMDV02_02_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC3C0_QMDV02_02_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC3C0_QMDV02_02_QMD_SPARE_G MW(1759:1728) +#define NVC3C0_QMDV02_02_QMD_SPARE_H MW(1791:1760) +#define NVC3C0_QMDV02_02_QMD_SPARE_I MW(1823:1792) +#define NVC3C0_QMDV02_02_QMD_SPARE_J MW(1855:1824) +#define NVC3C0_QMDV02_02_QMD_SPARE_K MW(1887:1856) +#define NVC3C0_QMDV02_02_QMD_SPARE_L MW(1919:1888) +#define NVC3C0_QMDV02_02_QMD_SPARE_M MW(1951:1920) +#define NVC3C0_QMDV02_02_QMD_SPARE_N MW(1983:1952) +#define NVC3C0_QMDV02_02_DEBUG_ID_UPPER MW(2015:1984) +#define NVC3C0_QMDV02_02_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC3C0QMD_H__ diff --git a/Compute-QMD/clc5c0qmd.h b/Compute-QMD/clc5c0qmd.h new file mode 100644 index 0000000..180a491 --- /dev/null +++ b/Compute-QMD/clc5c0qmd.h @@ -0,0 +1,247 @@ +/******************************************************************************* + Copyright (c) 2001-2010 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC5C0QMD_H__ +#define __CLC5C0QMD_H__ + +/* +** Queue Meta Data, Version 02_03 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC5C0_QMDV02_03_OUTER_PUT MW(30:0) +#define NVC5C0_QMDV02_03_OUTER_OVERFLOW MW(31:31) +#define NVC5C0_QMDV02_03_OUTER_GET MW(62:32) +#define NVC5C0_QMDV02_03_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC5C0_QMDV02_03_INNER_GET MW(94:64) +#define NVC5C0_QMDV02_03_INNER_OVERFLOW MW(95:95) +#define NVC5C0_QMDV02_03_INNER_PUT MW(126:96) +#define NVC5C0_QMDV02_03_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC5C0_QMDV02_03_QMD_GROUP_ID MW(133:128) +#define NVC5C0_QMDV02_03_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_IS_QUEUE MW(136:136) +#define NVC5C0_QMDV02_03_IS_QUEUE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_IS_QUEUE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_QMD_RESERVED_B MW(159:144) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC5C0_QMDV02_03_QMD_RESERVED_C MW(185:185) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC5C0_QMDV02_03_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC5C0_QMDV02_03_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_LOWER_SHIFTED MW(287:256) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC5C0_QMDV02_03_QMD_RESERVED_D MW(335:328) +#define NVC5C0_QMDV02_03_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE MW(369:368) +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC5C0_QMDV02_03_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC5C0_QMDV02_03_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC5C0_QMDV02_03_SAMPLER_INDEX MW(382:382) +#define NVC5C0_QMDV02_03_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC5C0_QMDV02_03_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC5C0_QMDV02_03_CTA_RASTER_WIDTH MW(415:384) +#define NVC5C0_QMDV02_03_CTA_RASTER_HEIGHT MW(431:416) +#define NVC5C0_QMDV02_03_QMD_RESERVED13A MW(447:432) +#define NVC5C0_QMDV02_03_CTA_RASTER_DEPTH MW(463:448) +#define NVC5C0_QMDV02_03_QMD_RESERVED14A MW(479:464) +#define NVC5C0_QMDV02_03_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC5C0_QMDV02_03_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC5C0_QMDV02_03_QUEUE_ENTRIES_PER_CTA_LOG2 MW(534:530) +#define NVC5C0_QMDV02_03_SHARED_MEMORY_SIZE MW(561:544) +#define NVC5C0_QMDV02_03_MIN_SM_CONFIG_SHARED_MEM_SIZE MW(568:562) +#define NVC5C0_QMDV02_03_MAX_SM_CONFIG_SHARED_MEM_SIZE MW(575:569) +#define NVC5C0_QMDV02_03_QMD_VERSION MW(579:576) +#define NVC5C0_QMDV02_03_QMD_MAJOR_VERSION MW(583:580) +#define NVC5C0_QMDV02_03_QMD_RESERVED_H MW(591:584) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC5C0_QMDV02_03_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_REGISTER_COUNT_V MW(656:648) +#define NVC5C0_QMDV02_03_TARGET_SM_CONFIG_SHARED_MEM_SIZE MW(663:657) +#define NVC5C0_QMDV02_03_FREE_CTA_SLOTS_EMPTY_SM MW(671:664) +#define NVC5C0_QMDV02_03_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC5C0_QMDV02_03_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC5C0_QMDV02_03_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC5C0_QMDV02_03_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC5C0_QMDV02_03_QMD_RESERVED_J MW(783:776) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_QMDV02_03_QMD_RESERVED_K MW(791:791) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE0_PAYLOAD MW(831:800) +#define NVC5C0_QMDV02_03_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC5C0_QMDV02_03_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC5C0_QMDV02_03_QMD_RESERVED_L MW(879:872) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC5C0_QMDV02_03_QMD_RESERVED_M MW(887:887) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC5C0_QMDV02_03_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC5C0_QMDV02_03_RELEASE1_PAYLOAD MW(927:896) +#define NVC5C0_QMDV02_03_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC5C0_QMDV02_03_QMD_RESERVED_N MW(954:952) +#define NVC5C0_QMDV02_03_BARRIER_COUNT MW(959:955) +#define NVC5C0_QMDV02_03_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC5C0_QMDV02_03_REGISTER_COUNT MW(991:984) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_ADDR_UPPER_SHIFTED MW(1000:992) +#define NVC5C0_QMDV02_03_PROGRAM_PREFETCH_SIZE MW(1009:1001) +#define NVC5C0_QMDV02_03_QMD_RESERVED_A MW(1015:1010) +#define NVC5C0_QMDV02_03_SASS_VERSION MW(1023:1016) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC5C0_QMDV02_03_PROGRAM_ADDRESS_LOWER MW(1567:1536) +#define NVC5C0_QMDV02_03_PROGRAM_ADDRESS_UPPER MW(1584:1568) +#define NVC5C0_QMDV02_03_QMD_RESERVED_S MW(1599:1585) +#define NVC5C0_QMDV02_03_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC5C0_QMDV02_03_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC5C0_QMDV02_03_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC5C0_QMDV02_03_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC5C0_QMDV02_03_QMD_RESERVED_Q MW(1694:1694) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC5C0_QMDV02_03_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC5C0_QMDV02_03_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC5C0_QMDV02_03_QMD_SPARE_G MW(1759:1728) +#define NVC5C0_QMDV02_03_QMD_SPARE_H MW(1791:1760) +#define NVC5C0_QMDV02_03_QMD_SPARE_I MW(1823:1792) +#define NVC5C0_QMDV02_03_QMD_SPARE_J MW(1855:1824) +#define NVC5C0_QMDV02_03_QMD_SPARE_K MW(1887:1856) +#define NVC5C0_QMDV02_03_QMD_SPARE_L MW(1919:1888) +#define NVC5C0_QMDV02_03_QMD_SPARE_M MW(1951:1920) +#define NVC5C0_QMDV02_03_QMD_SPARE_N MW(1983:1952) +#define NVC5C0_QMDV02_03_DEBUG_ID_UPPER MW(2015:1984) +#define NVC5C0_QMDV02_03_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC5C0QMD_H__ diff --git a/DCB/DCB-4.x-Specification.html b/DCB/DCB-4.x-Specification.html new file mode 100644 index 0000000..354f218 --- /dev/null +++ b/DCB/DCB-4.x-Specification.html @@ -0,0 +1,9712 @@ + + + + + +Device Control Block 4.0 Specification + + + + + +
+
+

Purpose

+
+

Device Control Blocks (DCBs) are static tables used to describe the +board topology and connections external to the GPU chip.

+

Each board built has specific additions to the capabilities through +external devices, as well as limitations where output lines are not +linked to device connectors. DCBs define the devices connected, +specific information needed to configure those devices, and the external +electrical connections such as HDMI and Display Port.

+

DCBs do not try to explain the capabilities of the chip itself. That +information is implicit in the VBIOS, firmware and drivers, which are +built differently for each chip. Both the firmware and the drivers +know the inherent capability of each chip, and use runtime choices to +determine chip dependent code paths.

+
DCB version and use
    +
  • +

    +DCB 1.x is used with Core3 VBIOS (NV5, NV10, NV11, NV15, NV20). +

    +
    • +
  • +

    +DCB 2.x (2.0-2.4) is used with Core4 and Core4r2 VBIOS (NV17, NV25, NV28, NV3x). +

    +
    • +
  • +

    +DCB 3.0 is used with Core5 VBIOS (NV4x, G7x). +

    +
    • +
  • +

    +DCB 4.0 is used with Core6, Core7, and Core8 VBIOS (G80+). +

    +
    • +
+
+
+
+

Device Control Block Structure

+
+

The 4.0 DCB Data Structure consists of the following parts:

+
    +
  • +

    +Header - The version number (0x40 for Version 4.0), the header size, the size of each DCB Entry (currently 8 bytes), the number of valid DCB Entries, pointers to different tables, and the DCB signature. If any of the pointers here are NULL, then those tables are considered to be absent or invalid. +

    +
    • +
  • +

    +Device entries list - One for each display connector (two for DVI-I +connectors). Each device entry is subdivided into two main parts: +Display Path Information and +Device Specific Information. +

    +
    • +
+
+
+
+

Device Control Block Header

+
+
+ + +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. Device Control Block Header
Name Bit width Optional/Mandatory Values and Meaning

Version

8

O

Version # of the DCB Header and Entries. DCB 4.0 will start with a +value of 0x40 here. A version number of zero directs the driver to use +an internal DCB table.

Header Size

8

M

Size of the DCB Header in Bytes. For v4.0 this will be 27 bytes.

Entry Count

8

M

Number of DCB Device Entries immediately +following this table.

Entry Size

8

M

Size of Each Entry in bytes. With the start of DCB 4.0, this field should be 8.

Communications Control Block Pointer

16

M

Pointer to the Communications Control Block. In v3.0 this was the I2C Control Block Pointer.

DCB Signature

32

M

DCB signature = 0x4EDCBDCB. +This is used to tell a valid DCB from an invalid one.

GPIO Assignment Table Pointer

16

M

Pointer to the GPIO Assignment Table.

Input Devices Table Pointer

16

O

Pointer to the Input Devices Table.

Personal Cinema Table Pointer

16

O

Pointer to the Personal Cinema Table.

Spread Spectrum Table Pointer

16

O

Pointer to the Spread Spectrum Table.

I2C Devices Table Pointer

16

O

Pointer to the I2C Devices Table.

Connector Table Pointer

16

M

Pointer to the Connector Table.

Flags

8

M

See DCB Flags below

HDTV Translation Table Pointer

16

O

Pointer to the HDTV Translation Table. +This structure is optional. If the structure is not needed, then this pointer can be set to 0.

Switched Outputs Table Pointer

16

O

Pointer to the Switched Outputs Table. This structure is optional.

+
+

An "optional" table pointer or field may be set to zero to indicate that +no table is present. If the structure is not needed, then this pointer +can be set to 0.

+
+ + + +
+
Note
+		Throughout this document, a "pointer" means a byte offset relative +to the start of the VBIOS image.
+
+
+

DCB Flags

+

Each bit flag has a different meaning. +All undefined bits are reserved and must be set to 0.

+
DCB Flag Bits
    +
  • +

    +Bit 0 - Boot Display Count: +

    +
      +
    • +

      +0 - Only 1 boot display is allowed. +

      +
      • +
    • +

      +1 - 2 boot displays are allowed. +

      +
      • +
    +
    • +
+

These next 2 bits are all used for VIP connections.

+
    +
  • +

    +Bits 5:4 - VIP location. Possible values are: +

    +
      +
    • +

      +00b - No VIP. +

      +
      • +
    • +

      +01b - VIP is on Pin Set A. +

      +
      • +
    • +

      +10b - VIP is on Pin Set B. +

      +
      • +
    • +

      +11b - Reserved +

      +
      • +
    +
    • +
+

These next 2 bits are used for Distributed Rendering (DR) configuration.

+
    +
  • +

    +Bit 6 - All capable DR ports: Pin Set A: +

    +
      +
    • +

      +1 - Pin Set A is routed to a SLI Finger. +

      +
      • +
    • +

      +0 - Pin Set A is not attached. +

      +
      • +
    +
    • +
  • +

    +Bit 7 - All capable DR Ports: Pin Set B: +

    +
      +
    • +

      +1 - Pin Set B is routed to a SLI Finger. +

      +
      • +
    • +

      +0 - Pin Set B is not attached. +

      +
      • +
    +
    • +
+
+ + + +
+
Note
+		A PIOR port cannot be used both as a Distributed Rendering +connection and as an Output Display at the same time.
+
+
+
+

DCB Header Version 4.0 Sizes

+

The v4.0 DCB header has added fields over time.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + +
DATE New Size Last Inclusive Field

Start

23 Bytes

Flags

08-02-06

25 Bytes

DCB 3.0, HDTV Translation Table Pointer

11-07-06

27 Bytes

Switched Outputs Table Pointer

+
+
+
+
+
+

DCB Device Entries

+
+

A DCB device entry is 64 bits wide, two double words. The first 32 bits, +Display Path Information, contain the +main routing information. Their format is common to all devices. The second +32 bits, Device Specific Information, +are interpreted based on the Type field from the Display Path Information.

+

There is one device entry for each output display path. The number of +DCB entries is listed in the DCB Header.

+
+ + + +
+
Note
+		For DVI-I connectors there are two entries: one for the CRT and one for +the LCD. The two device entries share the same I2C port.
+
+

Device Entries are listed in order of boot priority. The VBIOS code +will iterate through the DCB entries and if a device is found, then that +device will be configured. If not, the VBIOS moves to the next index in the +DCB. If no device is found, the first CRT on the list should be chosen.

+

GPUs earlier than G80 have a "mirror mode" feature that enables up to two +display devices to be enabled by the VBIOS, and controlled through the same VGA +registers. G80 and later display hardware only supports one display in VGA +mode, and the VBIOS will only enable one display device.

+

When Device Entries are listed, it is not allowed to have two entries +for the same output device.

+
+

Display Path Information

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Rsvd

VD

Output Devices

BBDR

BDR

Loc

Bus

Connector

Head

EDID Port

Type

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Type

4

Display type.

EDID

4

EDID Port.

Head

4

Head bitmask.

Con

4

Connector table entry index.

Bus

4

Logical bus, used for mutual exclusion.

Loc

2

Location of the final stage devices, on-chip or off-chip.

BDR

1

Disables this as a boot display if set.

BBDR

1

If set, disables the ability to boot if not display is detected.

VD

1

Indicates this is a virtual device.

Rsvd

3

Reserved, set to 0.

+
+
Type

This field defines the Type of the display used on this display path. +Currently defined values are:

+
    +
  • +

    +0 = CRT +

    +
    • +
  • +

    +1 = TV +

    +
    • +
  • +

    +2 = TMDS +

    +
    • +
  • +

    +3 = LVDS +

    +
    • +
  • +

    +4 = Reserved +

    +
    • +
  • +

    +5 = SDI +

    +
    • +
  • +

    +6 = DisplayPort +

    +
    • +
  • +

    +E = EOL (End of Line) - This signals the SW to stop parsing any more entries. +

    +
    • +
  • +

    +F = Skip Entry - This allows quick removal of entries from DCB. +

    +
    • +
+
EDID Port

Each number refers to an entry in the +Communications Control Block Structure +that represents the port to use in order to query the EDID. This number +cannot be equal to or greater than the Communication Control Block Header’s +Entry Count value, except if the EDID is not retrieved via DDC (over I2C +or DPAux).

+

For DFPs, if the EDID source is set to straps or SBIOS, then this field +must be set to 0xF to indicate that we are not using a Communications Control +Block port for this device to get the EDID.

+
Head Bitmask

Each bit defines the ability of that head with this device.

+
    +
  • +

    +Bit 0 = Head 0 +

    +
    • +
  • +

    +Bit 1 = Head 1 +

    +
    • +
  • +

    +Bit 2 = Head 2 +

    +
    • +
  • +

    +Bit 3 = Head 3 +

    +
    • +
+

GPUs before GK107 only support two heads. For those devices, bits 2 and +3 should always be zero.

+
Connector Index

This field signifies a specific entry in the Connector Table. More than +one DCB device can have the same Connector Index. This number cannot +be equal to or greater than the Connector Table Header’s Entry Count value.

+
+ + + +
+
Note
+		If two DCB entries have the same Connector Index, that still allows them +to be displayed at the same time. To prevent combinations based on the +connector, use the Bus field.
+
+
Bus

This field only allows for logical mutual exclusion of devices so that +they cannot display simultaneously. The driver uses this field to disallow the +use of a combination of two devices if they share the same bus number.

+
Location

This field shows the location of the last output device before the data +is sent off from our board to the display.

+

Currently defined values are:

+
    +
  • +

    +0 = On Chip (internal) TV encoder, internal TMDS encoder +

    +
    • +
  • +

    +1 = On Board (external) DAC, external TMDS encoder +

    +
    • +
  • +

    +2 = Reserved. +

    +
    • +
+
Boot Device Removed
    +
  • +

    +0 = This device is allowed to boot if detected. +

    +
    • +
  • +

    +1 = This device is not allowed to boot, even if detected. +

    +
    • +
+
Blind Boot Device Removed
    +
  • +

    +0 = This device is allowed to boot if no devices are detected. +

    +
    • +
  • +

    +1 = This device is not allowed to boot if no devices are detected. +

    +
    • +
+
DAC/SOR/PIOR Assignment (Output Resource)

Each bit defines the use of this connector with a DAC for internal CRTs +and TVs, an SOR for internal DFPs, and a PIOR for external devices like +TMDS, SDI or TV Encoders.

+

Currently defined values are:

+
    +
  • +

    +Bit 0 = DAC 0, SOR 0, or PIOR 0 +

    +
    • +
  • +

    +Bit 1 = DAC 1, SOR 1, or PIOR 1 +

    +
    • +
  • +

    +Bit 2 = DAC 2, SOR 2, or PIOR 2 +

    +
    • +
  • +

    +Bit 3 = DAC 3, SOR 3, or PIOR 3 +

    +
    • +
+
Virtual Device
    +
  • +

    +0 = This is a physical device. +

    +
    • +
  • +

    +1 = This is a virtual device. +

    +
    • +
+

Virtual devices are used only for remote desktop rendering. When set to +1, EDID Port should be set to 0xF (unused) and the Connector Index +should reference an entry with Type="Skip Entry".

+
Extra Information

The BUS field may reflect only a logical limitation of the buses. It can +describe an actual physical limitation, or it may be solely a way to +remove the combination between two DCB entries.

+
+
+

Device Specific Information

+

Each device type has a different specific information associated with it. +However, TMDS, LVDS, SDI, and DisplayPort share the same DFP Specific +Information.

+
+

CRT Specific Information

+
+ ++ + + + + + + + + + +
31..0

Reserved (Set to 0)

+
+
+
+

DFP Specific Information

+

DFP Specific Information is used to decribe TMDS, LVDS, SDI and +DisplayPort Types of devices.

+
+ +++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
31..28 27..2423..212019..18 17 16 15..8 7..6 5..4 3..21..0

Rsvd

MxLM

MLR

E

Rsvd

HDMI

Rsvd

Ext Enc

Rsvd

SL/DPL

Ctrl

EDID

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

EDID

2

EDID source.

Ctrl

2

Power and Backlight Control.

SL/DPL

2

Sub-link/DisplayPort Link.

Rsvd

2

Reserved, set to 0.

Ext Enc

8

External Link Type.

Rsvd

1

Reserved.

HDMI

1

HDMI Enable.

Rsvd

2

Reserved, set to 0.

E

1

External Communications Port.

MxLR

3

Maximum Link Rate.

MxLM

4

Maximum Lane Mask.

Rsvd

4

Reserved, set to 0.

+
+
EDID source

This field states where to get the EDIDs for the panels. Current values are:

+
    +
  • +

    +0 = EDID is read via DDC. +

    +
    • +
  • +

    +1 = EDID is determined via Panel Straps and VBIOS tables. +

    +
    • +
  • +

    +2 = EDID is obtained using the _DDC ACPI interface or VBIOS 5F80/02 SBIOS INT15 calls. +

    +
    • +
  • +

    +3 = Reserved. +

    +
    • +
+
Mobile LVDS Detection Policy

There is a secondary fallback policy that is used for all mobile LVDS panels. +It follows this convention:

+
+ +++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DCB EDID Source Panel Strap Panel Index EDID Retrieval

DDC

== 0xF

Don’t Care.

Use DDC.

!= 0xF

Don’t Care.

Use Straps and VBIOS Tables.

Straps and VBIOS Tables

!= 0xF

Don’t Care.

Use Straps and VBIOS Tables.

== 0xF

!= 0xF

Use Straps and VBIOS Tables.

== 0xF

No Panel.

SBIOS

Don’t Care.

Don’t Care.

Use SBIOS _DDC ACPI method or SBIOS/VBIOS Call.

+
+

If the board designer chooses to use DDC based EDIDs always, the VBIOS can +override the Panel Strap to always indicate 0xF via SW Strap Overrides or through +the DevInit scripts.

+
Power and Backlight Control

This field describes the control method for the power and backlight of the +panel. Currently defined values are:

+
    +
  • +

    +0 = External. This is used to define panels where we don’t have direct control over the power or backlight. For example, this value is used for most TMDS panels. +

    +
    • +
  • +

    +1 = Scripts. Used for most LVDS panels. +

    +
    • +
  • +

    +2 = VBIOS callbacks to the SBIOS. +

    +
    • +
+
Sub-link/DisplayPort Link

This field specifies a board-supported sub-link mask for TMDS, LVDS, and +SDI. For Display Port, this field specifies the link mask supported +on the board.

+

For TMDS, LVDS, and SDI, this field lists which sub-links in each SOR are +routed to the connector on the board.

+

Possible sub-link values are:

+
    +
  • +

    +Bit 0: Sub-link A +

    +
    • +
  • +

    +Bit 1: Sub-link B +

    +
    • +
+

If both sub-links are routed to the connector, specifying a dual-link +connector, then bits 0 and 1 will both be set.

+
+ + + +
+
Note
+		Dual-link hook-up does not necessarily mean that both links should +be used during programming. According to the DVI 1.0 specification, +the crossover frequency of 165 MHZ should be the deciding factor for when +dual-link vs. single-link connections should be used for TMDS use. This field +merely indicates whether the connector has two links connected to it. It +does not specify the actual use of either single-link or dual-link connections.
+
+

LVDS uses single-link or dual-link connections based on the individual panel +model’s requirements. For example, SXGA panels may be run with single-link or +dual-link LVDS connections.

+

For DisplayPort, this field describes which links in each SOR are routed to the +connector on the board. Possible link values are:

+
    +
  • +

    +Bit 0: DP-A (Display Port Resource A) +

    +
    • +
  • +

    +Bit 1: DP-B (Display Port Resource B) +

    +
    • +
+
+ + + +
+
Note
+		Unlike TMDS, LVDS, and SDI, if both links are routed to the +connector, this does not indicate the presence of a dual-link connector. It +simply means that both Display Port (DP) resources A and B may be used +with this SOR. That is: DP-A or DP-B may be associated with an output device +(OD) to output via DisplayPort, but not both simultaneously.
+
+
Reserved

Set to 0.

+
External Link Type

This field describes the exact external link used on the board. If this +Location field in the Display Path of this DCB entry is set to ON CHIP, +then these bits should be set to 0.

+

Currently defined values:

+
HDMI Enable

This bit is placed here to allow the use of HDMI on this particular DFP +output display.

+

Currently defined values are:

+
    +
  • +

    +0 = Disable HDMI on this DFP +

    +
    • +
  • +

    +1 = Enable HDMI on this DFP +

    +
    • +
+
External Communications Port

If this device uses external I2C or DPAux communication, then this field +allows us to know which port is to be used. If the device is internal +to the chip, set this bit to 0 by default.

+

Currently defined values are:

+
    +
  • +

    +0 = Primary Communications Port +

    +
    • +
  • +

    +1 = Secondary Communications Port +

    +
    • +
+

The +Communications Control Block Header +holds the primary and secondary port indices. Each index maps to an entry in +the Communications control Block table, +which specifies the physical port and type to use to communicate with this +device.

+
Maximum Link Rate

This field describes the maximum link rate allowed for the links within +the Display Port connection. This field is only applicable to DisplayPort +device types.

+

Possible values are:

+
+ +++ + + + + + + + + + + + + + +

0

1.62 Gbps

1

2.7 Gbps

2

5.4 Gbps

+
+
Maximum Lane Mask

This field describes the maximum lanes that are populated on the board. This +field is only applicable to DisplayPort device types.

+

Possible values are:

+
+ +++ + + + + + + + + + + + + + +

0x1

1 Lane

0x3

2 Lanes

0xF

4 Lanes

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. External Link Type
Value Name I2C Addr

0

Undefined (allows backward compatibility) - Assumes Single-Link.

1

Silicon Image 164 - Single-Link TMDS.

0x70

2

Silicon Image 178 - Single-Link TMDS.

0x70

3

Dual Silicon Image 178 - Dual-Link TMDS.

0x70 (primary), 0x72 (secondary)

4

Chrontel 7009 - Single-Link TMDS.

0xEA

5

Chrontel 7019 - Dual-Link LVDS.

0xEA

6

National Semiconductor DS90C387 - Dual Link LVDS.

7

Silicon Image 164 - Single-Link TMDS (Alternate Address).

0x74

8

Chrontel 7301 - Single-Link TMDS.

9

Silicon Image 1162 - Single Link TMDS (Alternate Address).

0x72

A

Reserved

Reserved

B

Analogix ANX9801 - 4-Lane DisplayPort.

0x70 (transmitter), 0x72 (receiver)

C

Parade Tech DP501 - 4-Lane DisplayPort.

D

Analogix ANX9805 - HDMI and DisplayPort.

0x70, 0x72, 0x7A, 0x74

E

Analogix ANX9805 - HDMI and DisplayPort (Alternate Address).

0x78, 0x76, 0x7E, 0x7C

+
+
+
+

TV Specific Information

+
+ +++++++ + + + + + + + + + + + + + + + + + + + +
31..24 23..20 19..16 15..8 7..4 3..0

Rsvd

HDTV

CC

E

DACS+

Encoder

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

SDTV

3

SDTV Format.

Rsvd

1

Reserved, set to 0.

DACs

4

DAC description, lower four bits.

Encoder

8

Encoder identifier.

TVDACs+

4

DAC description, upper four bits.

E

1

External Communication Port.

CC

2

Connector Count.

HDTV

4

HDTV Format.

Rsvd

5

Reserved, set to 0.

+
+
SDTV Format

This field determines the default SDTV Format.

+

Currently defined values are:

+
    +
  • +

    +0x0 = NTSC_M (US) +

    +
    • +
  • +

    +0x1 = NTSC_J (Japan) +

    +
    • +
  • +

    +0x2 = PAL_M (NTSC Timing w/PAL Encoding - Brazilian Format) +

    +
    • +
  • +

    +0x3 = PAL_BDGHI (US) +

    +
    • +
  • +

    +0x4 = PAL_N (Paraguay and Uruguay Format) +

    +
    • +
  • +

    +0x5 = PAL_NC (Argentina Format) +

    +
    • +
  • +

    +0x6 = Reserved +

    +
    • +
  • +

    +0x7 = Reserved +

    +
    • +
+
DACs

These bits define the availability of encoder outputs that the board +supports to the TV connectors.

+
+ +++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Meaning

0x00

Reserved.

0x01

Invalid.

0x02

CVBS on Green.

0x03

CVBS on Green and S-Video on Red (chroma) and Green (luma).

0x04

CVBS on Blue.

0x05

Invalid.

0x06

Invalid.

0x07

CVBS on Blue, S-Video on Red (chroma) and Green (luma).

0x08

Standard HDTV.

0x09

HDTV Twist 1.

0x0A

SCART.

0x0B

Twist 2.

0x0C

SCART + HDTV.

0x0D

Standard HDTV without SDTV.

0x0E

SCART Twist 1.

0x0F

SCART + HDTV.

0x11

Composite + HDTV outputs.

0x12

HDTV + Scart Twist 1.

0x13

S-Video on Red (chroma) and Green (luma).

+
+
Encoder

This field describes the exact encoder used on the board.

+
    +
  • +

    +Brooktree/Conexant +

    +
      +
    • +

      +0x00 = Brooktree 868 +

      +
      • +
    • +

      +0x01 = Brooktree 869 +

      +
      • +
    • +

      +0x02 = Conexant 870 +

      +
      • +
    • +

      +0x03 = Conexant 871 +

      +
      • +
    • +

      +0x04 = Conexant 872 +

      +
      • +
    • +

      +0x05 = Conexant 873 +

      +
      • +
    • +

      +0x06 = Conexant 874 +

      +
      • +
    • +

      +0x07 = Conexant 875 +

      +
      • +
    +
    • +
  • +

    +Chrontel +

    +
      +
    • +

      +0x40 = Chrontel 7003 +

      +
      • +
    • +

      +0x41 = Chrontel 7004 +

      +
      • +
    • +

      +0x42 = Chrontel 7005 +

      +
      • +
    • +

      +0x43 = Chrontel 7006 +

      +
      • +
    • +

      +0x44 = Chrontel 7007 +

      +
      • +
    • +

      +0x45 = Chrontel 7008 +

      +
      • +
    • +

      +0x46 = Chrontel 7009 +

      +
      • +
    • +

      +0x47 = Chrontel 7010 +

      +
      • +
    • +

      +0x48 = Chrontel 7011 +

      +
      • +
    • +

      +0x49 = Chrontel 7012 +

      +
      • +
    • +

      +0x4A = Chrontel 7019 +

      +
      • +
    • +

      +0x4B = Chrontel 7021 +

      +
      • +
    +
    • +
  • +

    +Philips +

    +
      +
    • +

      +0x80 = Philips 7102 +

      +
      • +
    • +

      +0x81 = Philips 7103 +

      +
      • +
    • +

      +0x82 = Philips 7104 +

      +
      • +
    • +

      +0x83 = Philips 7105 +

      +
      • +
    • +

      +0x84 = Philips 7108 +

      +
      • +
    • +

      +0x85 = Philips 7108A +

      +
      • +
    • +

      +0x86 = Philips 7108B +

      +
      • +
    • +

      +0x87 = Philips 7109 +

      +
      • +
    • +

      +0x88 = Philips 7109A +

      +
      • +
    +
    • +
  • +

    +NVIDIA +

    +
      +
    • +

      +0xC0 = NVIDIA internal encoder +

      +
      • +
    +
    • +
+
TVDACs+

This field shows bits 4-7 of the TVDACs value.

+
External Communication Port

If this device uses external I2C communication, then this field allows +us to know which device will be used. If the device is internal to the +chip, set this bit to 0 as default.

+

Currently defined values are:

+
    +
  • +

    +0 = Primary Communications Port +

    +
    • +
  • +

    +1 = Secondary Communications Port +

    +
    • +
+

The I2C Control Block Header holds the primary and secondary port indices.

+
Connector Count

Generally, there is only 1 connector per DCB display path. TVs are +special since one output device could have multiple connectors.

+

Currently defined values are:

+
    +
  • +

    +0 = 1 Connector +

    +
    • +
  • +

    +1 = 2 Connectors +

    +
    • +
  • +

    +2 = 3 Connectors +

    +
    • +
  • +

    +3 = 4 Connectors +

    +
    • +
+

If only one bit of either of the Red, Green or Blue defines in the above +DACs field is set, then this field must be set to 1 connector.

+

If two bits of either of the Red, Green or Blue defines in the above +DACs field is set, then this field must be set to 1 or 2 connectors for +a S-Video and/or Composite connector. But those connectors cannot be +displayed simultaneously.

+

If three bits of either of the Red, Green or Blue defines in the above +DACs field is set, then this field must be set to 2 connectors for both +a S-Video and Composite connector.

+

If the HDTV Bit is set, then we can assume that there will be connectors +for YPrPb, S-Video, and Composite off of the Personal Cinema pod. So, this field should be set to 3 connectors.

+
HDTV Format

This field determines the default HDTV Format.

+

Currently defined values are:

+
    +
  • +

    +0x0 = HDTV 576i +

    +
    • +
  • +

    +0x1 = HDTV 480i +

    +
    • +
  • +

    +0x2 = HDTV 480p @60Hz +

    +
    • +
  • +

    +0x3 = HDTV 576p @50Hz +

    +
    • +
  • +

    +0x4 = HDTV 720p @50Hz +

    +
    • +
  • +

    +0x5 = HDTV 720p @60Hz +

    +
    • +
  • +

    +0x6 = HDTV 1080i @50Hz +

    +
    • +
  • +

    +0x7 = HDTV 1080i @60Hz +

    +
    • +
  • +

    +0x8 = HDTV 1080p @24Hz +

    +
    • +
  • +

    +0x9-0xE = Reserved +

    +
    • +
  • +

    +0xF = Reserved +

    +
    • +
+
SDTV Format

This field determines the default SDTV Format.

+

Currently defined values are:

+
    +
  • +

    +0x0 = NTSC_M (US) +

    +
    • +
  • +

    +0x1 = NTSC_J (Japan) +

    +
    • +
  • +

    +0x2 = PAL_M (NTSC Timing w/PAL Encoding - Brazilian Format) +

    +
    • +
  • +

    +0x3 = PAL_BDGHI (US) +

    +
    • +
  • +

    +0x4 = PAL_N (Paraguay and Uruguay Format) +

    +
    • +
  • +

    +0x5 = PAL_NC (Argentina Format) +

    +
    • +
  • +

    +0x6 = Reserved +

    +
    • +
  • +

    +0x7 = Reserved +

    +
    • +
+
Extra Information

The TV sub-DACs are labeled 0, 1, 2, and 3 for G80 and later GPUs. There is +no plan currently to support external TV encoders. When the CRT is used, +sub-DAC 0 is used for Red, sub-DAC 1 is used for Green and sub-DAC 2 is used +for Blue, always.

+

This table should explain how each TVDACs value corresponds to each sub-DAC +TV Protocol:

+
+ ++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TVDACs Composite S-Video HDTV SCART

0

1

2

3

0

1

2

3

0

1

2

3

0

1

2

3

0

Invalid

1

Invalid

2

CVBS

3

CVBS

C

Y

4

CVBS

5

Invalid

6

Invalid

7

CVBS

C

Y

8

CVBS

C

Y

R/Pr

G/Y

B/Pb

9

CVBS

Y

C

R/Pr

G/Y

B/Pb

A

CVBS

Y

C

G

B

R

CVBS

B

CVBS

C

Y

R/Pr

G/Y

B/Pb

C

CVBS

Y

C

G/Y

B/Pb

R/Pr

G

B

R

CVBS

D

R/Pr

G/Y

B/Pb

E

CVBS

Y

C

R

G

B

CVBS

F

CVBS

Y

C

G/Y

R/Pr

B/Pb

R

G

B

CVBS

0x10

Reserved

0x11

CVBS

R/Pr

G/Y

B/Pb

0x12

CVBS1

CVBS2

Y

C

G/Y

B/Pb

R/Pr

CVBS

G

R

B

0x13

Y

C

+
+

Only the entries above in red are currently supported in Core6+.

+

Here’s how we choose the connector types based on the load:

+
    +
  • +

    +The SCART configuration is chosen if SCART is valid for the board’s TVDACs +setting, and loads are detected on all four sub-DACS. +

    +
    • +
  • +

    +The HDTV configuration is chosen if HDTV is valid for the board’s TVDACs +setting, SCART was not chosen, and loads are detected on the three +sub-DACS that are specified to carry signals for the HDTV configuration. +

    +
    • +
  • +

    +The S-Video configuration is chosen if S-Video is valid for the board’s TVDACs +setting, SCART or HTDV were not chosen, and loads are detected on the two +sub-DACS that are specified to carry signals for the S-Video configuration. +

    +
    • +
  • +

    +The Composite configuration is chosen if Composite is valid for the board’s +TVDACs setting while SCART, HTDV, or S-Video were not chosen. +

    +
    • +
  • +

    +Some configurations allow for two different Composite/CVBS signals. +CVBS1 is used if that DAC has a load. Otherwise, we use CVBS2. CVBS1 is the +CVBS signal when the 4-pin S-Video to CVBS dongle is used. CVBS2 is the +CVBS signal when the 7-pin HDTV component dongle is used (the B/Pb connector on +the HDTV component RCA connectors on the 7-pin dongle is labeled as "Comp" for +use with CVBS). +

    +
    • +
+
Additional Notes
    +
  • +

    +The S-Video Y signal will always follow the G/Y signal on the 7-pin HDTV component dongle (because the pins match up on the connectors). +

    +
    • +
  • +

    +The S-Video C signal will always follow the R/Pr signal on the 7-pin HDTV component dongle (because the pins match up on the connectors). +

    +
    • +
  • +

    +The CVBS (Composite) signal will always follow the B/Pb signal on the 7-pin HDTV component dongle (because the B/Pb connector is labeled for use as Composite (CVBS)). +

    +
    • +
  • +

    +The CVBS (Composite) signal will always follow the Y signal on the 4-pin S-Video to CVBS dongle (because the dongle has the RCA CVBS signal wired that way). +

    +
    • +
+
+
+
+
+
+

Communications Control Block

+
+

This structure is REQUIRED in the DCB 4.0 spec. It must be listed inside +every DCB. The VBIOS and the FCODE will use the data from this +structure.

+

The Communications Control Block provides logical to physical +translation of all the different ways that the GPU can use to +communicate with other devices on the board or to displays. Prior to +DCB 4.0 there were 3 different I2C Ports for GPUs and an +extra 2 for Crush (nForce chipset) 11/17. The Northbridge, which holds the integrated +GPU, only has 1.5 V signaling, but the DDC/EDID spec requires 3.3 V +signaling. So, for Crush, we use two ports on the south bridge to handle +the DDC voltage requirements.

+
+ + + +
+
Note
+		Crush, also known as nForce or nForce2, is a motherboard chipset created by NVIDIA. +Crush was released in mid-2001.
+
+

For DCB 4.0, the norm will be 4 I2C ports as exposed on G80. With +Display Port added in G98, we’ll expose DPAUX ports as well.

+
+

Communications Control Block Header

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Version

8

Version # of the CCB Header and Entries. CCB 4.0 will start with a value of 0x40 here. A version of 0 here is invalid.

Header Size

8

Size of the CCB Header in bytes. This is typically 5 bytes.

Entry Count

8

Number of CCB Entries starting directly after the end of this table.

Entry Size

8

Size of each entry in bytes. This field should be 4.

Primary Communication Port

4

Index for the primary communications port. Specifically, if we need to talk with an external device, the port referenced by this index will be the primary port to talk with that device.

Secondary Communication Port

4

Index for the secondary communications port. Specifically, if we need to talk with an external device, this port referenced by this index will be the secondary port to talk with that device.

+
+

There is one port entry for each port used. A DVI-I connector’s two device entries share the same I2C port.

+
+
+

Communications Control Block Entry

+
Access Method

The first upper 8 bits of each entry is called the Access Method. This +field indicates how the software should control each port. From NV50 onward +a new port mapping was implemented. Older I2C Access methods - CRTC +indexed mapping and PCI IO Mapping - have been removed, but their values +reserved to allow SW compatibility. Here’s the NV50 and later Defined Access +Methods:

+
+ +++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Value Method

0

Reserved (Prior DCB Usage)

1

Reserved (Prior DCB Usage)

2

Reserved (Prior DCB Usage)

3

Reserved (Prior DCB Usage)

4

Reserved (Prior DCB Usage)

5

I2C Access Method

6

Display Port AUX Channel Access Method

+
+
+

I2C Access Method

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

I2CAccess = 5

Reserved

Rsv

DP

H

Speed

Phys Port

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Physical Port

4

Physical Nv5x Port

+

* 0 = DDC0 +* 1 = DDC1 +* 2 = DDC2 +* 3 = I2C

Port Speed

4

The I2C spec defines 3 different communication speeds: +* Standard - 100 kHz +* Fast - 400 kHz +* High Speed - 3.4 MHz

+

Each device on an I2C bus must comply with that speed otherwise, the +lowest device on that bus will clock stall the speed to what it can +handle. High Speed requires extra programming to allow a specific +master to send the high speed data. There are programming requirements +to also allow for the fallback between higher level speeds and lower +levels speeds.

+

No traffic on the I2C port may exceed the speed specified here.

+

Most (perhaps all) DCBs set this field to 0. The currently defined levels are:

+

* 0x0 = Use Defaults (Probably the only one we’ll ever use.) +* 0x1 = 100 kHz as per Standard specification +* 0x2 = 200 kHz +* 0x3 = 400 kHz as per Fast specification +* 0x4 = 800 kHz +* 0x5 = 1.6 MHz +* 0x6 = 3.4 MHz as per High Speed specification +* 0x7 = 60 KHz

Hybrid Pad

1

This bit is used to tell us if we’re enabling Hybrid Pad control for this entry. Hybrid pad control requires that we switch bits in the NV_PMGR_HYBRID_PADCTL area when switching between I2C output and DPAux output. The values here are:

+

* 0 = Normal Mode - Generic I2C Port +* 1 = Hybrid Mode - Pad allows for switching between DPAux and I2C

Physical DP Aux Port

4

This is the physical DP Aux port used only when Hybrid Pad field is in Hybrid Mode. We need this value since NV_PMGR_HYBRID_PADCTL is indexed based on the DP Port value.

Reserved

11

Set as 0.

I2C Access Method

8

Must be set to 5 for this Access Method

+
+
+
+

Display Port AUX Channel Access Method

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

DP Aux Access = 6

Reserved

Rsvd

I2C

H

Rsvd

Phys Port

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Port

4

Physical Display Ports

H

1

Hybrid Pad

I2C

4

Physical I2C Port

Rsvd

11

Reserved. Set as 0.

Type

8

Display Port AUX Channel Access Method = 6

+
+
Physical Display Port mappings:
    +
  • +

    +0 = AUXCH 0 +

    +
    • +
  • +

    +1 = AUXCH 1 +

    +
    • +
  • +

    +2 = AUXCH 2 +

    +
    • +
  • +

    +3 = AUXCH 3 +

    +
    • +
+
Hybrid Pad

This bit is used to tell us if we’re enabling Hybrid Pad control for +this entry. Hybrid pad control requires that we switch bits in the +NV_PMGR_HYBRID_PADCTL area when switching between I2C output and DPAux +output. The values here are:

+
    +
  • +

    +0 = Normal Mode - Generic I2C Port +

    +
    • +
  • +

    +1 = Hybrid Mode - Pad allows for switching between DPAux and I2C +

    +
    • +
+
Physical I2C Port

This is the physical I2C port used only when Hybrid Pad field is in Hybrid Mode.

+
Type

Must be set to 6 to indicate Display Port AUX Channel Access Method

+
+
+
+
+
+

Input Devices Table

+
+

This structure is optional. It only needs to be defined if the board +provides input devices. Also, the VBIOS or FCODE does not need to use +this structure. Only the drivers will use it.

+

The Input Devices are listed at a location in the ROM dictated by the +16-bit Input Devices Pointer listed in the DCB Header. Currently, +the maximum number of devices is 8. Each device is listed in one 8-bit +entry.

+

If a device has an Input Device Structure, but not a +Personal Cinema Structure defined, we treat +that board as a generic VIVO (Video-In, Video-Out) board.

+

It is assumed that each of these Input Devices is controlled via I2C +through the Primary Communications Port.

+
+

Input Devices Header

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Version

8

Version # of the Input Devices Header and Entries. +Input Devices 4.0 start with a version of 0x40.

Header Size

8

Size of the Input Devices Header in Bytes. Initially, this is 4 bytes.

Entry Count

8

Number of Input Devices Entries starting directly after the end of this table.

Entry Size

8

Size of Each Entry in bytes. This field should be 1.

+
+
+
+

Input Device Entry

+
+ +++++++++ + + + + + + + + + + + + + + + + + + +
76543210

VT

T

Mode

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Mode

4

This field lists the Mode number that this device supports. If we +encounter a Mode of 0xF, that signifies a Skip Entry. This allows for +quick removal of a specific entry from the Input Devices.

Type

2

This field describes the type of input device that is connected. Current +defined possible values are:

+

* 0 = VCR, +* 1 = TV

Video Type

2

This field describes the video type of input device that is connected.

+

Currently defined values are:

+

* 0 = CVBS, +* 1 = Tuner, +* 2 = S-Video

+
+
+
+
+
+

Personal Cinema Table

+
+
+ + + +
+
Note
+		"Personal Cinema" refers to a line of graphics boards with pre-G80 +NVIDIA GPUs and on-board television tuners.
+
+

This structure is optional. It only needs to be defined if the board is +intending to provide Personal Cinema support. The VBIOS or FCODE +does not need to use this structure. Only the drivers will use it.

+

There are many specific defines needed for the personal cinema in order +to know which devices are available. Because there are no entries +needed for this table, the normal Entry Count and Entry Size will not be +a part of this table for now.

+

If both the Board ID and the Vendor ID are 0, then the Personal Cinema +Table data should be considered invalid. This is akin to other table’s +SKIP ENTRY, meaning that we should just skip this table if these IDs are +both 0.

+

If a device has an Input Devices Table, but not +a Personal Cinema Structure defined, we treat that board as a generic +VIVO (Video-In, Video-Out) board.

+

It is assumed that each of these Personal Cinema Devices is controlled +via I2C through the Primary Communications Port.

+
+

Personal Cinema Table Structure

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0

Vendor ID

Board ID

Header Size

Version

+
+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
6362616059585756555453525150494847464544434241403938373635343332

IRCtrl

PwrCtrlIC

Demod1

ATuner 1

SndDcd1

Std

Eio

+
+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
9594939291908988878685848382818079787776757473727170696867666564

Demod2

R

T2F

R

T1F

ATuner2

Rsvd

SndDcd2

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Version

8

Version = 0x40

Header Size

8

Size in bytes, 12 for v4.0

Board ID

8

Personal Cinema Board ID for this board

Vendor ID

8

Vendor ID for this board

Eio

2

Expander IO bus width

TVStd

2

TV Standard used e.g. NTSC or PAL

SndDec1

4

Sound Decoder #1 ID

ATuner1

8

Analog Tuner #1 type, the first analog tuner

Demod1

8

Demodulator #1, the first digital-signal tuner

PwrCtrlIC

4

Satellite Dish power controller IC type

IRCtrl

4

The InfraRed transmitter microcontroller type

SndDec2

4

Sound Decoder #2 ID

Rsvd

4

Reserved, set to 0

ATuner2

8

Analog Tuner #2 type.

T1F

3

Tuner #1 Functionality, digitial TV, analog TV and FM.

Reserved

1

Reserved, set to 0

T2F

3

Tuner #2 Functionality

Reserved

1

Reserved, set to 0

Demod2

8

Demodulator #2, the second digital-signal tuner

+
+
Version

Version # of the Personal Cinema Header. The original Personal Cinema +table version will start with a value of 0x40 here. If the version is 0 +here, then the driver will assume that this table is invalid.

+
Header Size

Size of the Personal Cinema Header in bytes. This is 12 bytes for v4.0.

+
Board ID

This field lists the Personal Cinema Board ID for this board. This provides +a mechanism for SW to differentiate between individual Personal Cinema boards +and generic Video-In-Video-Out (VIVO) boards.

+

Currently defined values are:

+
    +
  • +

    +0x00 = Generic VIVO board or No Personal Cinema Support +

    +
    • +
  • +

    +0x01 = P79 +

    +
    • +
  • +

    +0x02 = P104 +

    +
    • +
  • +

    +0x03 = P164-NV31 +

    +
    • +
  • +

    +0x04 = P164-NV34 +

    +
    • +
  • +

    +0x05 = P186-NV35 +

    +
    • +
  • +

    +0x06 = P187-NV35 +

    +
    • +
  • +

    +0x07 = P178-NV36 +

    +
    • +
  • +

    +0x08 = P253-NV43 +

    +
    • +
  • +

    +0x09 = P254-NV44 +

    +
    • +
  • +

    +0x0A = P178-NV36-A2M +

    +
    • +
  • +

    +0x0B = P293 +

    +
    • +
  • +

    +0x0C = P178-NV36-FPGA +

    +
    • +
  • +

    +0x0D = P143-NV34-FPGA +

    +
    • +
  • +

    +0x0E = P143-NV34-Non-FPGA +

    +
    • +
  • +

    +0x10 = P256-NV43 +

    +
    • +
  • +

    +0x11 = Compro +

    +
    • +
  • +

    +0x13 = P274-NV41 +

    +
    • +
  • +

    +0x21 = Asus AIO +

    +
    • +
  • +

    +0x22 = Asus external tuner +

    +
    • +
  • +

    +0x30 = Customer Reserved 0 +

    +
    • +
  • +

    +0x31 = Customer Reserved 1 +

    +
    • +
  • +

    +0x32 = Customer Reserved 2 +

    +
    • +
+
Vendor ID

This field lists the Personal Cinema Vendor ID for this board. Current +defined possible values are:

+
    +
  • +

    +0x00 = Generic VIVO board or No Personal Cinema Support +

    +
    • +
  • +

    +0xde = NVIDIA +

    +
    • +
  • +

    +0xcb = Compro +

    +
    • +
  • +

    +0x81 = Asus +

    +
    • +
+
Expander IO

This field describes the exact number of bits used for the expander IO +bus.

+

Currently defined values are:

+
    +
  • +

    +0 = None or Not Applicable +

    +
    • +
  • +

    +1 = 8 bits +

    +
    • +
  • +

    +2 = 16 bits +

    +
    • +
  • +

    +3 = RF remote +

    +
    • +
+
TV Standard

This field describes the TV standard used for the input devices.

+

Currently defined values are:

+
    +
  • +

    +0 = NTSC +

    +
    • +
  • +

    +1 = PAL/SECAM +

    +
    • +
  • +

    +2 = Worldwide +

    +
    • +
  • +

    +3 = Reserved +

    +
    • +
+
Sound Decoder #1

This field describes the first Sound Decoder used on the board. Current +defined possible values are:

+
    +
  • +

    +0 = Mono +

    +
    • +
  • +

    +2 = A2 (TDA9873) +

    +
    • +
  • +

    +3 = NICAM (TDA9874) +

    +
    • +
  • +

    +4 = BTSC (TDA9850) +

    +
    • +
  • +

    +5 = FM-FM Japan (TA8874z) +

    +
    • +
  • +

    +6 = BTSC/EIAJ (SAA7133/SAA7173) +

    +
    • +
  • +

    +7 = A2,NICAM (SAA7134/SAA7174) +

    +
    • +
  • +

    +8 = Worldwide (SAA7135/SAA7175) +

    +
    • +
  • +

    +9 = Micronas MSP 3425G (NTSC) +

    +
    • +
  • +

    +10 = Micronas MSP 3415G (PAL) +

    +
    • +
  • +

    +11 = SAA7174A +

    +
    • +
  • +

    +12 = SAA7171 +

    +
    • +
  • +

    +15 = Not Present +

    +
    • +
+
Tuner Type #1

This field describes the first analog-signal tuner used on the +board.

+

Currently defined values are:

+
    +
  • +

    +0x00 = Not Present +

    +
    • +
  • +

    +0x01 = Philips FI1216 MK2 +

    +
    • +
  • +

    +0x02 = Philips FI1216 MF +

    +
    • +
  • +

    +0x03 = Philips FI1236 MK2 +

    +
    • +
  • +

    +0x04 = Philips FI1246 MK2 +

    +
    • +
  • +

    +0x05 = Philips FI1256 MK2 +

    +
    • +
  • +

    +0x06 = Philips FQ1216 ME +

    +
    • +
  • +

    +0x07 = Philips FQ1216 ME MK3 +

    +
    • +
  • +

    +0x08 = Philips FQ1236 ME MK3 +

    +
    • +
  • +

    +0x09 = Philips TDA 8275 +

    +
    • +
  • +

    +0x11 = Temic 4036FY5,4032FY5 +

    +
    • +
  • +

    +0x12 = Temic 4006FH5,4002FH5 +

    +
    • +
  • +

    +0x13 = Temic 4066FY5,4036FY5 +

    +
    • +
  • +

    +0x14 = Temic 4016FY5,4012FY5 +

    +
    • +
  • +

    +0x15 = Temic 4136 +

    +
    • +
  • +

    +0x16 = Temic 4146 +

    +
    • +
  • +

    +0x17 = Microtune MT2040 +

    +
    • +
  • +

    +0x18 = Microtune MT2050 +

    +
    • +
  • +

    +0x19 = Microtune 7102DT5 +

    +
    • +
  • +

    +0x20 = Microtune 7132DT5 +

    +
    • +
  • +

    +0x21 = Microtune MT2060 +

    +
    • +
  • +

    +0x22 = Microtune 4039FR5 +

    +
    • +
  • +

    +0x23 = Microtune 4049FM5 +

    +
    • +
  • +

    +0x30 = LG TALN-M200T (PAL) +

    +
    • +
  • +

    +0x31 = LG TALN-H200T (NTSC) +

    +
    • +
  • +

    +0x32 = TALN-S200T (SECAM L/L' & PAL B/G, I/I, D/K) +

    +
    • +
  • +

    +0x60 = Samsung TEBN9282PK01A +

    +
    • +
  • +

    +0x81 = Philips FM1216 +

    +
    • +
  • +

    +0x82 = Philips FM1216MF +

    +
    • +
  • +

    +0x83 = Philips FM1236 +

    +
    • +
  • +

    +0x84 = Philips FM1246 +

    +
    • +
  • +

    +0x85 = Philips FM1256 +

    +
    • +
  • +

    +0x86 = Philips FM1216 ME +

    +
    • +
  • +

    +0x87 = Philips FM1216 ME MK3 +

    +
    • +
  • +

    +0x88 = Philips FM1236 ME MK3 +

    +
    • +
+
Demodulator #1

The first digital-signal tuner used this board. This field has these hex +defines:

+
    +
  • +

    +0x00 = Not present +

    +
    • +
  • +

    +0x01 = TDA9885 (PAL/NTSC Analog) +

    +
    • +
  • +

    +0x02 = TDA9886 (PAL/NTSC/SECAM Analog) +

    +
    • +
  • +

    +0x03 = TDA9887 (PAL/NTSC/SECAM QSS Analog) +

    +
    • +
  • +

    +0x04 = Philips SAA7171 +

    +
    • +
  • +

    +0x10 = Conexant CX24121 +

    +
    • +
  • +

    +0x15 = Phillips TDA8260TW +

    +
    • +
  • +

    +0x16 = Zarlink MT352 +

    +
    • +
  • +

    +0x17 = LGDT3302 +

    +
    • +
  • +

    +0x18 = Micronas DRX3960A +

    +
    • +
+
Power Control IC

Satellite Dish power controller. This field has these hex defines:

+
    +
  • +

    +0 = Not present +

    +
    • +
  • +

    +1 = LNBP21 - I2C Address 0x10 +

    +
    • +
+
Microcontroller

The microcontroller chip used for infrared (IR) transmitting to control +other IR devices. This field has these values

+
    +
  • +

    +0 = Not present +

    +
    • +
  • +

    +6 = PIC12F629 +

    +
    • +
  • +

    +7 = PIC12CE673 +

    +
    • +
+
Sound Decoder #2

This field describes a possible second Sound Decoder used on the +board. The values are the same as with Sound Decoder #1.

+
Tuner Type #2

This field describes a possible second analog-signal tuner used on the +board. The values are the same as with Tuner Type #1.

+
Tuner #1 Functionality

This field describes the functionality supported by Tuner #1.

+

Currently defined values are:

+
    +
  • +

    +0 = None +

    +
    • +
  • +

    +1 = Digital TV +

    +
    • +
  • +

    +2 = Analog TV +

    +
    • +
  • +

    +3 = Analog + Digital TV +

    +
    • +
  • +

    +4 = FM +

    +
    • +
  • +

    +5 = Digital + FM +

    +
    • +
  • +

    +6 = Analog + FM +

    +
    • +
  • +

    +7 = Analog + Digital + FM +

    +
    • +
+
Tuner #2 Functionality

This field describes the functionality allowed by Tuner Type #2 field. +The currently defined values are the same as those for Tuner #1 Functionality.

+
Demodulator #2

The possible second digital-signal tuner used this board. This field has +the same defines as Demodulator #1.

+
+
+
+
+

GPIO Assignment Table

+
+

The GPIO Assignment table creates a logical mapping of function-based +usage names to physical GPIOs within the GPU. Each pin has

+
    +
  • +

    +a logical ON State and +

    +
    • +
  • +

    +a logical OFF State. +

    +
    • +
+

Each state can be distinctly defined physically via:

+
    +
  • +

    +Sending output high to the GPIO, +

    +
    • +
  • +

    +Sending output low to the GPIO, or +

    +
    • +
  • +

    +Tristating the GPIO (Setting it to Input Mode). +

    +
    • +
+

Alternately, specific GPIOs can also be assigned to carry Pulse Width +Modulated (PWM) signals. This can be used for fan speed control or +backlight power control.

+

This table is required in all ROMs. It must be listed inside every DCB. +The VBIOS and the FCODE will use the data from this structure.

+
+

GPIO Assignment Table Header

+

When moving to GF110, the HW team merged the Normal/Alternate/Sequencer +modes of the GPIO into one 8 bit field in a GPIO register. In order to +better manage that change, we decided to increase the revision from the +initial 0x40 version to 0x41 and re-organize the bit fields in each GPIO +table entry to accommodate a new field that matches the field in the HW +register directly.

+

Version 0x41, as used for GF11x+ / Core75 and future cores, is +listed below.

+
+ + +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 3. GPIO Assignment Table Header Version 4.1
31302928272625242322212019181716151413121110 9 8 7 6 5 4 3 2 1 0

Entry Size = 5

Entry Count

Header Size = 6

Version = 0x41

+
+
+ +++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + +
47464544434241403938373635343332

GPIOAssTabPtr

+
+
Version

Version # of the GPIO Assignment Table Header and Entries. The current +GPIO Assignment Table version is 4.1 or a value of 0x41 in this field. +If this version is 0, then the driver will assume that this table +is invalid.

+
Header Size

Size of the GPIO Assignment Table in bytes. For version 4.1 this is 6 bytes.

+
Entry Count

Number of GPIO Assignment Table Entries starting directly after the end +of this header.

+
Entry Size

Size of Each Entry in bytes. For version 4.0, this was 4 bytes. For +version 4.1, this is now 5 bytes.

+
External GPIO Assignment Table Master Header Pointer

Pointer to the External GPIO Assignment Master Table. This field can be set to 0 to indicate no +support for this table.

+
+
+

GPIO Assignment Table Entry

+

Please note that this structure below is for version 4.1.

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

PM

R

GS

Input HW Select

Output HW Select

Function

I

IO

PinNum

+
+
+ +++++++++ + + + + + + + + + + + + + + + + + + + + +
3938373635343332

OE

OT

FE

FT

LockPin

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

PinNum

6 (5:0)

GPIO Pin Number

IO

1 (6:6)

I/O Type

I

1 (7:7)

Initialize pin state

Function

8 (15:8)

Output HW select

8 (23:16)

Output hardware function setting

Input HW select

5 (28:24)

Input hardware function setting

GS

1 (29:29)

GSYNC Header

R

1 (30:30)

Reserved

PM

1 (31:31)

Pulse Width Modulate

LockPin

4 (35:32)

Lock Pin Number

FT

1 (36:36)

Off Data

FE

1 (37:37)

Off Enable

OT

1 (38:38)

On Data

OE

1 (39:39)

On Enable

+
+
GPIO Number (5:0)

The GPIO number associated with this entry. Older chips have a maximum of 9 +GPIO pins. G80+ have 15 GPIOs in register space. This field must be 0 +if the I/O Type field is set to NV_GPIO_IO_TYPE_DEDICATED_LOCK_PIN.

+
I/O Type

The I/O Type field is used to specify if this entry represents an actual +GPIO or instead represents a similar type of entity. This field is an +enumeration that currently has the following values:

+
    +
  • +

    +0 = NV_GPIO_IO_TYPE_GPIO - This entry represents a normal internal GPIO. +

    +
    • +
  • +

    +1 = NV_GPIO_IO_TYPE_DEDICATED_LOCK_PIN - This entry represents an internal + dedicated lock pin. No actual GPIO is associated with the lock pin. The + GPIO Number field must be set to zero. +

    +
    • +
+
Initialize State (Init) (7:7)

This field specifies the initial state to set the GPIO to during boot. +If this bit is 0, then the software will initialize the GPIO at boot to +the settings specified by "Off Data" and "Off Enable". If this bit is +1, then the software will initialize the GPIO at boot to the settings +specified by "On Data" and "On Enable".

+
Function (15:8)

This lists the function of each GPIO pin. Here’s a list of the function +numbers and a short description of each:

+
    +
  • +

    +0 = LCD0 backlight: Backlight control. LCD0 corresponds to the LCD0 defined + in the LCD ID field in the Connector Table. +

    +
    • +
  • +

    +1 = LCD0 power: Panel Power control. LCD0 corresponds to the LCD0 defined in + the LCD ID field in the Connector Table. +

    +
    • +
  • +

    +2 = LCD0 Power Status: Panel Power status. LCD0 corresponds to the LCD0 + defined in the LCD ID field in the Connector Table. +

    +
    • +
  • +

    +3 = VSYNC: Alternate VSync signal using GPIO pin. +

    +
    • +
  • +

    +4 = VSEL0: Voltage Select Bit 0 +

    +
    • +
  • +

    +5 = VSEL1: Voltage Select Bit 1 +

    +
    • +
  • +

    +6 = VSEL2: Voltage Select Bit 2 +

    +
    • +
  • +

    +7 = Hotplug A: 1st Hotplug signal +

    +
    • +
  • +

    +8 = Hotplug B: 2nd Hotplug signal +

    +
    • +
  • +

    +9 = Fan: Fan control. Can be on or off, or pulse width modulation to control speed. +

    +
    • +
  • +

    +10 = Reserved +

    +
    • +
  • +

    +11 = Reserved +

    +
    • +
  • +

    +12 = DAC 1 Select: DAC 1 mux select that allows us to switch between using + the CRT (Off state) or TV (On State) filters on the board. +

    +
    • +
  • +

    +13 = DAC 1 Alternate Load Detect: When the DAC 1 is not currently switched to + a device that needs detection, this GPIO pin can be used to detect the + alternate load on the green channel. +

    +
    • +
  • +

    +14 = Stereo DAC Select: Chooses which DAC to use for the stereo goggles. +

    +
    • +
  • +

    +15 = Stereo toggle: Switch between Left and Right eyes for the stereo goggles. +

    +
    • +
  • +

    +16 = Thermal and External Power Detect: Sense bit when there’s a thermal + event or the external power connector is connected or removed from the board. +

    +
    • +
  • +

    +17 = Thermal Event Detect: Sense bit when there’s a thermal event sent from + the thermal device. +

    +
    • +
  • +

    +18 = Vtg rst: Input Signal from daughter card for Frame Lock interface headers. +

    +
    • +
  • +

    +19 = Sus stat: Input requesting the suspend state be entered +

    +
    • +
  • +

    +20 = Spread0: Bit 0 of output to control Spread Spectrum if the chip isn’t I2C controlled. +

    +
    • +
  • +

    +21 = Spread1: Bit 1 of output to control Spread Spectrum if the chip isn’t I2C controlled. +

    +
    • +
  • +

    +22 = VDS FrameID0 - Bit 0 of the frame ID when using Virtual Display Switching. +

    +
    • +
  • +

    +23 = VDS FrameID1: Bit 1 of the frame ID when using Virtual Display Switching. +

    +
    • +
  • +

    +24 = FBVDDQ Select: Selects between: +

    +
    • +
  • +

    +: ON state: High FBVDD/Q voltage (i.e. 1.8V) +

    +
    • +
  • +

    +: OFF State: Low FBVDD/Q voltage (i.e. 1.5V) +

    +
    • +
  • +

    +25 = Customer: This function is here to be used by the OEM. It just reserves + the GPIO so our software will know not to use it. +

    +
    • +
  • +

    +26 = VSEL 3: Voltage Select Bit 3 +

    +
    • +
  • +

    +27 = VSEL Default - Allow switching from default voltage (1) to selected voltage (0). +

    +
    • +
  • +

    +28 = Tuner +

    +
    • +
  • +

    +29 = Current Share +

    +
    • +
  • +

    +30 = Current Share Enable +

    +
    • +
  • +

    +31 = LCD0 Self Test. LCD0 corresponds to the LCD0 defined in LCD ID field in + Connector Table. +

    +
    • +
  • +

    +32 = LCD0 Lamp Status. LCD0 corresponds to the LCD0 defined in LCD ID field + in Connector Table. +

    +
    • +
  • +

    +33 = LCD0 Brightness - Allow brightness adjustment via PWM. (Must have PWM + set when this is selected.). LCD0 corresponds to the LCD0 defined in LCD ID + field in Connector Table. +

    +
    • +
  • +

    +34 = Required Power Sense. Similar to 16, but without the thermal half. +

    +
    • +
  • +

    +35 = OverTemp - This GPIO will assert when the GPU has reached some + adjustable temperature threshold +

    +
    • +
  • +

    +36 = HDTV Select: Allows selection of lines driven between SDTV - Off state, + and HDTV - On State. +

    +
    • +
  • +

    +37 = HDTV Alt-Detect: Allows detection of the connectors that are not + selected by HDTV Select. That is, if HDTV Select is currently selecting SDTV, + then this GPIO would allow us to detect the presence of the HDTV connection. +

    +
    • +
  • +

    +38 = Reserved +

    +
    • +
  • +

    +39 = Optional Power Sense. Similar to 16 and 34, but without the thermal half + and not necessary for normal non-overclocked operation.1 +

    +
    • +
  • +

    +40 = DAC 0 Select: DAC 0 mux that allows us to switch between using the CRT + (Off state) or TV (On State) filters on the board. +

    +
    • +
  • +

    +41 = Framelock daughter-card interrupt +

    +
    • +
  • +

    +42 = SW Performance Level Slowdown. When asserted, the SW will lower it’s + performance level to the lowest state. +

    +
    • +
  • +

    +43 = HW Slowdown Enable. On assertion HW will slowdown clocks (NVCLK, HOTCLK) + using either _EXT_POWER, _EXT_ALERT or _EXT_OVERT settings (depends on GPIO + configured: 12, 9 & 8 respectively). Than SW will take over, limit GPU + p-state to battery level and disable slowdown. On deassertion SW will + reenable slowdown and remove p-state limit. System will continue running full + clocks. +

    +
    • +
  • +

    +44 = Disable Power Sense. If asserted, this GPIO will remove the power sense + circuit from affecting HW Slowdown. +

    +
    • +
  • +

    +45 = RSET HDTV Select. Allows selecting between SDTV, On State, and HDTV, Off + State, RSET values during TV detection. +

    +
    • +
  • +

    +46 = FBVREF Select: Selects between: +

    +
      +
    • +

      +ON state: High FBVREF voltage (i.e. 70% FBVDDQ) +

      +
      • +
    • +

      +OFF state: Low FBVREF voltage (i.e. 50% FBVDDQ) +

      +
      • +
    +
    • +
  • +

    +47 = Reserved +

    +
    • +
  • +

    +48 = Generic Initialized: This GPIO is used, but does not have a specific + function assigned to it or has a function defined elsewhere. System software + should initialize this GPIO using the _INIT values for the chip. This function + should be specified when a GPIO needs to be set statically during + initialization. This is different than function 25, which implies that the + GPIO is not used by NVIDIA software. +

    +
    • +
  • +

    +49 = Inquiry for HD over SD TV boot preference. Allows user to select whether + to boot to SDTV or component output by default. +

    +
    • +
  • +

    +50 = Digital Encoder Interrupt Enable: For Si1930uC, a GPIO will be set ON to + trigger interrupt to Si1930uC to enable I2C communication. When I2C + transactions to the Si1930uC are complete, the drivers will set this GPIO to + OFF. +

    +
    • +
  • +

    +51 = Selects I2C communications between either DDC or I2C +

    +
    • +
  • +

    +52 = Thermal Alert: Interrupt input from external thermal device. Indicates + that the device needs to be serviced. +

    +
    • +
  • +

    +53 = Thermal Critical: Comparator-driven input from external thermal device. + Indicates that a temperature is above a critical limit. +

    +
    • +
  • +

    +54 = Reserved +

    +
    • +
  • +

    +55 = Reserved +

    +
    • +
  • +

    +56 = Reserved +

    +
    • +
  • +

    +57 = Reserved +

    +
    • +
  • +

    +58 = Reserved +

    +
    • +
  • +

    +59 = Reserved +

    +
    • +
  • +

    +60 = SCART Select: Allows selection of lines driven between SDTV (S-Video, + Composite) and SDTV (SCART). +

    +
    • +
  • +

    +61 = Fan Speed Sense. This GPIO will sense a fan’s tachometer output (on + 4-wire fans). In the beginning, it will be more for sensing a stuck fan than + determining speed. Later GPUs will be able to measure the fan’s speed + internally from the GPIO. +

    +
    • +
  • +

    +62 = Reserved +

    +
    • +
  • +

    +63 = ExtSync0 - Used with external framelock with GSYNC products. It also + could be used for raster lock. +

    +
    • +
  • +

    +64 = SLI Raster Sync A: This signal is carried across the SLI bus to + synchronize the RG between GPUs. This signal will always be set as + Alternate. +

    +
    • +
  • +

    +65 = SLI Raster Sync B: This signal is carried across the SLI bus to + synchronize the RG between GPUs. This signal will always be set as + Alternate. This signal is just the second GPIO that can be used for Raster + sync from each GPU. It should only be defined when we have 2 pin sets being + used on one board to allow more than two GPUs to run in SLI mode. One will + be used with one pin set for input and the other will be used with the other + pin set for output. +

    +
    • +
  • +

    +66 = Swap Ready In A: This signal, which is related to Fliplocking, is used + to sense the state of the FET drain, which is pulled high and is connected to + the Swap Ready pin on the Distributed Rendering connector. +

    +
    • +
  • +

    +67 = Swap Ready Out: This signal, which is related to Fliplocking, is used to + drive the gate of an external FET. +

    +
    • +
  • +

    +68 = Available +

    +
    • +
  • +

    +69 = SCART 0: Bit 0 of the SCART Aspect Ratio Field +

    +
    • +
  • +

    +70 = SCART 1: Bit 1 of the SCART Aspect Ratio Field +

    +
    • +
  • +

    +GPIOs 69 and 70 define a 2 bit SCART Aspect Ratio Field. Here’s the possible + values for the SCART Aspect Ratio Field: +

    +
      +
    • +

      +0 = 4:3(12V) +

      +
      • +
    • +

      +1 = 16:9(6V) +

      +
      • +
    • +

      +2 = Undefined +

      +
      • +
    • +

      +3 = SCART inactive (0 V) +

      +
      • +
    +
    • +
  • +

    +71 HD Dongle Strap 0: Bit 0 of the HD Dongle Strap Field +

    +
    • +
  • +

    +72 HD Dongle Strap 1: Bit 1 of the HD Dongle Strap Field +

    +
    • +
+
+ + + +
+
Note
+		GPIOs 71 and 72 define a 2 bit HD Dongle Strap Field. These two bits index +into an array found at the +HDTV Translation Table that will determine the +default HD standard.
+
+
    +
  • +

    +73 = Thermal Alert Output: Output signal that indicates to other board + component(s) that the gpu’s internal temp has exceeded a certain threshold + for a duration longer than a programmed interval. +

    +
    • +
  • +

    +74 = DisplayPort to DVI dongle present A, when this GPIO asserts, we need to + configure DisplayPort encoder to output TMDS signal. +

    +
    • +
  • +

    +75 = DisplayPort to DVI dongle present B, when this GPIO asserts, we need to + configure DisplayPort encoder to output TMDS signal. +

    +
    • +
  • +

    +76 = Power Alert, when this GPIO asserts, the on-board power supply + controller needs attention. +

    +
    • +
  • +

    +77 = DAC 0 Load Detect: When the DAC 0 is not currently switched to a device + that needs detection, this GPIO pin can be used to detect the alternate + display’s load on the green channel. +

    +
    • +
  • +

    +78 = Analogix Encoder External Reset: For Analogix encoder, a GPIO is used to + control the RESET# line. +

    +
    • +
  • +

    +79 = I2C SCL Keeper Circuit Enable. See {{Bug|273429}}. Possible logical values are: +

    +
      +
    • +

      +OFF state: Normal operation (do nothing) +

      +
      • +
    • +

      +ON state: Enable the hardware to detect slave-issued stretches on the SCL + line and hold SCL low. +

      +
      • +
    +
    • +
  • +

    +80 = DVI to DAC connector switch. This GPIO allows for DAC 0 (TV) to be + selected to route to the DVI Connector when the GPIO is set to the logical + OFF state. When the GPIO is set to logical ON state, DAC 1 (CRT) will be + routed to the DVI connector. +

    +
    • +
  • +

    +81 = Hotplug C: 3rd Hotplug signal +

    +
    • +
  • +

    +82 = Hotplug D: 4th Hotplug signal +

    +
    • +
  • +

    +83 = DisplayPort to DVI dongle present C, when this GPIO asserts, we need to + configure DisplayPort encoder to output TMDS signal. +

    +
    • +
  • +

    +84 = DisplayPort to DVI dongle present D, when this GPIO asserts, we need to + configure DisplayPort encoder to output TMDS signal. +

    +
    • +
  • +

    +85 = Maxim Max6305 or compatible external reset controller. Enabled is Active + Low so init value should be Active High [No inversions] +

    +
    • +
  • +

    +86 = Active display LED to indicate the GPU with active display in SLI mode. +

    +
    • +
  • +

    +87 = SPDIF input. +

    +
    • +
  • +

    +88 = TOSLINK input. +

    +
    • +
  • +

    +89 = SPDIF/TOSLINK Select. When GPIO is set LOW, SPDIF is selected. When + GPIO is set HI, TOSLINK is selected. +

    +
    • +
  • +

    +90 = DPAUX/I2C select A. When this GPIO is set to Logical ON state, DPAUX + will be selected. Logical OFF state selects I2C. +

    +
    • +
  • +

    +91 = DPAUX/I2C select B. When this GPIO is set to Logical ON state, DPAUX + will be selected. Logical OFF state selects I2C. +

    +
    • +
  • +

    +92 = DPAUX/I2C select C. When this GPIO is set to Logical ON state, DPAUX + will be selected. Logical OFF state selects I2C. +

    +
    • +
  • +

    +93 = DPAUX/I2C select D. When this GPIO is set to Logical ON state, DPAUX + will be selected. Logical OFF state selects I2C. +

    +
    • +
  • +

    +94 = Hotplug E: 5th Hotplug signal +

    +
    • +
  • +

    +95 = Hotplug F: 6th Hotplug signal +

    +
    • +
  • +

    +96 = Hotplug G: 7th Hotplug signal +

    +
    • +
  • +

    +99 = GPIO External Device 1 Interrupt - Used to surface an interrupt from a + GPIO external device +

    +
    • +
  • +

    +106 = Switched Outputs: This GPIO is used by the + switched outputs table. A switched outputs GPIO + must be processed by the INIT_GPIO_ALL devinit opcode and set to its init + state. +

    +
    • +
  • +

    +107 = Customer Asyncronous Read/Write - Allows a customer to use the GPIO for + whatever purpose they want. +

    +
    • +
  • +

    +108 = Access to MXM 3.0 bus’s Direct GPIO0 (Pin 26). Once the system has the + MXM structure/GPIO Device structure which defines usage of Direct GPIO0, this + GPU’s GPIO is the physical pin to take on any enabling/detection/disabling + function defined in the MXM Output Device data structure with MXM Direct + GPIO0. +

    +
    • +
  • +

    +109 = Access to MXM 3.0 bus’s Direct GPIO1 (Pin 28). Once the system has the + MXM structure/GPIO Device structure which defines usage of Direct GPIO1, this + GPU’s GPIO is the physical pin to take on any enabling/detection/disabling + function defined in the MXM Output Device data structure with MXM Direct + GPIO1. +

    +
    • +
  • +

    +110 = Access to MXM 3.0 bus’s Direct GPIO2 (Pin 30). Once the system has the + MXM structure/GPIO Device structure which defines usage of Direct GPIO2, this + GPU’s GPIO is the physical pin to take on any enabling/detection/disabling + function defined in the MXM Output Device data structure with MXM Direct + GPIO2. +

    +
    • +
  • +

    +111 = HW Only Slowdown Enable. On assertion HW will slowdown clocks (NVCLK, + HOTCLK) using _EXT_POWER settings (use only with GPIO12). No software action + will be taken. On deassertion HW will release clock slowdown. +

    +
    • +
  • +

    +112 = Swap Ready In B: This signal, which is related to Fliplocking, is used + to sense the state of the FET drain, which is pulled high and is connected to + the Swap Ready pin on the Distributed Rendering connector. +

    +
    • +
  • +

    +113 = Trigger condition for PMU: Can either be triggered by system notify + bit set in SBIOS postbox command register or an error entering into + deep-idle. +

    +
    • +
  • +

    +114 = Reserved for Swap Ready Out B +

    +
    • +
  • +

    +115 = VSEL4: Voltage Select Bit 4 +

    +
    • +
  • +

    +116 = VSEL5: Voltage Select Bit 5 +

    +
    • +
  • +

    +117 = VSEL6: Voltage Select Bit 6 +

    +
    • +
  • +

    +118 = VSEL7: Voltage Select Bit 7 +

    +
    • +
  • +

    +119 = LVDS Fast switch mux +

    +
    • +
  • +

    +120 = Fan Failsafe PWM: The functionality controls FAN fail safe PWM + generator. If function is present in VBIOS, GPIO should be configured as + normal output and initially asserted. Once RM is loaded and FAN control is + successfully initialized RM will dessert this pin to allow FAN_PWM control. +

    +
    • +
  • +

    +121 = External Power Emergency: This GPIO provides an input to let SW know + when the GPU does not have enough power to initialize. +

    +
    • +
  • +

    +122 = NVVDD PSI: The NVVDD Power State Indicator (PSI) signals the NVVDD + power supply controller to switch to reduced phase operation (typically 1 or + 2 phases) for efficiency in low power states. + Here are the logical states: +

    +
      +
    • +

      +ON state: Enable low power state (reduced phase operation) +

      +
      • +
    • +

      +OFF state: Disable low power state (all phase operation) +

      +
      • +
    +
    • +
  • +

    +123 = Fan with Overtemp: denotes that the pin will be driven from PWM source that has capability to MAX duty cycle based on the thermal ALERT signal, as opposed to the already present "Fan" function which only outputs PWM. This PWM source is independent from the pwm source for "Fan" function. +

    +
    • +
  • +

    +124 = POSTed GPU LED to indicate the GPU that was POSTed by the SBIOS. +

    +
    • +
  • +

    +125 = Reserved +

    +
    • +
  • +

    +126 = Reserved +

    +
    • +
  • +

    +127 = Reserved +

    +
    • +
  • +

    +128 = SMPBI Event Notification: Notifies the EC (or client of the SMBus Post + Box Interface) of a pending GPU event requiring its attention. +

    +
    • +
  • +

    +129 = PWM based serial VID voltage control. +

    +
    • +
  • +

    +130 = Reserved +

    +
    • +
  • +

    +131 = SLI Bridge LED Brightness - Allow SLI Bridge brightness adjustment via + PWM. (Must have PWM set when this is selected.) +

    +
    • +
  • +

    +132 = Cover LOGO LED Brightness - Allow Cover LOGO brightness adjustment via + PWM. (Must have PWM set when this is selected.) +

    +
    • +
  • +

    +133 = Panel Self Refresh Frame Lock A : This function is defined for + Self-Refresh Panel. The SR panel will send the frame-lock interrupt to GPU to + sync the raster frame signal. +

    +
    • +
  • +

    +134 = FB Clamp: This function is used to monitor the FB clamp signal driven + by the Embedded Controller (EC) for JT memory self-refresh entry and exit. +

    +
    • +
  • +

    +135 = FB Clamp Toggle Request: This function is used to request the Embedded + Controller (EC) to toggle the FB clamp signal. +

    +
    • +
  • +

    +136 = Reserved +

    +
    • +
  • +

    +137 = Reserved +

    +
    • +
  • +

    +138 = LCD1 backlight: Backlight control. LCD1 corresponds to the LCD1 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +139 = LCD1 power: Panel Power control. LCD1 corresponds to the LCD1 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +140 = LCD1 Power Status: Panel Power status. LCD1 corresponds to the LCD1 + defined in LCD ID field in Connector Table. +

    +
    • +
  • +

    +141 = LCD1 Self Test. LCD1 corresponds to the LCD1 defined in LCD ID field in + Connector Table. +

    +
    • +
  • +

    +142 = LCD1 Lamp Status. LCD1 corresponds to the LCD1 defined in LCD ID field + in Connector Table. +

    +
    • +
  • +

    +143 = LCD1 Brightness - Allow brightness adjustment via PWM. (Must have PWM + set when this is selected.). LCD1 corresponds to the LCD1 defined in LCD ID + field in Connector Table. +

    +
    • +
  • +

    +144 = LCD2 backlight: Backlight control. LCD2 corresponds to the LCD2 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +145 = LCD2 power: Panel Power control. LCD2 corresponds to the LCD2 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +146 = LCD2 Power Status: Panel Power status. LCD2 corresponds to the LCD2 + defined in LCD ID field in Connector Table. +

    +
    • +
  • +

    +147 = LCD2 Self Test. LCD2 corresponds to the LCD2 defined in LCD ID field in +

    +
    • +
  • +

    +Connector Table. +

    +
    • +
  • +

    +148 = LCD2 Lamp Status. LCD2 corresponds to the LCD2 defined in LCD ID field + in Connector Table. +

    +
    • +
  • +

    +149 = LCD2 Brightness - Allow brightness adjustment via PWM. (Must have PWM + set when this is selected.). LCD2 corresponds to the LCD2 defined in LCD ID + field in Connector Table. +

    +
    • +
  • +

    +150 = LCD3 backlight: Backlight control. LCD3 corresponds to the LCD3 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +151 = LCD3 power: Panel Power control. LCD3 corresponds to the LCD3 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +152 = LCD3 Power Status: Panel Power status. LCD3 corresponds to the LCD3 + defined in LCD ID field in Connector Table. +

    +
    • +
  • +

    +153 = LCD3 Self Test. LCD3 corresponds to the LCD3 defined in LCD ID field in + Connector Table. +

    +
    • +
  • +

    +154 = LCD3 Lamp Status. LCD3 corresponds to the LCD3 defined in LCD ID field + in Connector Table. +

    +
    • +
  • +

    +155 = LCD3 Brightness - Allow brightness adjustment via PWM. (Must have PWM + set when this is selected.). LCD3 corresponds to the LCD3 defined in LCD ID + field in Connector Table. +

    +
    • +
  • +

    +156 = LCD4 backlight: Backlight control. LCD4 corresponds to the LCD4 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +157 = LCD4 power: Panel Power control. LCD4 corresponds to the LCD4 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +158 = LCD4 Power Status: Panel Power status. LCD4 corresponds to the LCD4 + defined in LCD ID field in Connector Table. +

    +
    • +
  • +

    +159 = LCD4 Self Test. LCD4 corresponds to the LCD4 defined in LCD ID field in + Connector Table. +

    +
    • +
  • +

    +160 = LCD4 Lamp Status. LCD4 corresponds to the LCD4 defined in LCD ID field + in Connector Table. +

    +
    • +
  • +

    +161 = LCD4 Brightness - Allow brightness adjustment via PWM. (Must have PWM + set when this is selected.). LCD4 corresponds to the LCD4 defined in LCD ID + field in Connector Table. +

    +
    • +
  • +

    +162 = LCD5 backlight: Backlight control. LCD5 corresponds to the LCD5 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +163 = LCD5 power: Panel Power control. LCD5 corresponds to the LCD5 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +164 = LCD5 Power Status: Panel Power status. LCD5 corresponds to the LCD5 + defined in LCD ID field in Connector Table. +

    +
    • +
  • +

    +165 = LCD5 Self Test. LCD5 corresponds to the LCD5 defined in LCD ID field in + Connector Table. +

    +
    • +
  • +

    +166 = LCD5 Lamp Status. LCD5 corresponds to the LCD5 defined in LCD ID field + in Connector Table. +

    +
    • +
  • +

    +167 = LCD5 Brightness - Allow brightness adjustment via PWM. (Must have PWM + set when this is selected.). LCD5 corresponds to the LCD5 defined in LCD ID + field in Connector Table. +

    +
    • +
  • +

    +168 = LCD6 backlight: Backlight control. LCD6 corresponds to the LCD6 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +169 = LCD6 power: Panel Power control. LCD6 corresponds to the LCD6 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +170 = LCD6 Power Status: Panel Power status. LCD6 corresponds to the LCD6 + defined in LCD ID field in Connector Table. +

    +
    • +
  • +

    +171 = LCD6 Self Test. LCD6 corresponds to the LCD6 defined in LCD ID field in + Connector Table. +

    +
    • +
  • +

    +172 = LCD6 Lamp Status. LCD6 corresponds to the LCD6 defined in LCD ID field + in Connector Table. +

    +
    • +
  • +

    +173 = LCD6 Brightness - Allow brightness adjustment via PWM. (Must have PWM + set when this is selected.). LCD6 corresponds to the LCD6 defined in LCD ID + field in Connector Table. +

    +
    • +
  • +

    +174 = LCD7 backlight: Backlight control. LCD7 corresponds to the LCD7 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +175 = LCD7 power: Panel Power control. LCD7 corresponds to the LCD7 defined + in LCD ID field in Connector Table. +

    +
    • +
  • +

    +176 = LCD7 Power Status: Panel Power status. LCD7 corresponds to the LCD7 + defined in LCD ID field in Connector Table. +

    +
    • +
  • +

    +177 = LCD7 Self Test. LCD7 corresponds to the LCD7 defined in LCD ID field in + Connector Table. +

    +
    • +
  • +

    +178 = LCD7 Lamp Status. LCD7 corresponds to the LCD7 defined in LCD ID field + in Connector Table. +

    +
    • +
  • +

    +179 = LCD7 Brightness - Allow brightness adjustment via PWM. (Must have PWM + set when this is selected.). LCD7 corresponds to the LCD7 defined in LCD ID + field in Connector Table. +

    +
    • +
  • +

    +180 = Reserved +

    +
    • +
  • +

    +255 = 0xFF = Skip Entry. This allows for quick removal of an entry from the + GPIO Assignment table. +

    +
    • +
+
Output HW select (23:16)

This field specifies HW Select value which has to be directly written +by software into the OUTPUT register field for deciding which output HW +function/enumerant will drive the PIN.

+

Values as specified in class20x HW manual

+
    +
  • +

    +0x00 = SEL_NORMAL +

    +
    • +
  • +

    +0x40 = SEL_RASTER_SYNC_0 +

    +
    • +
  • +

    +0x41 = SEL_RASTER_SYNC_1 +

    +
    • +
  • +

    +0x42 = SEL_RASTER_SYNC_2 +

    +
    • +
  • +

    +0x43 = SEL_RASTER_SYNC_3 +

    +
    • +
  • +

    +0x48 = SEL_STEREO_0 +

    +
    • +
  • +

    +0x49 = SEL_STEREO_1 +

    +
    • +
  • +

    +0x4A = SEL_STEREO_2 +

    +
    • +
  • +

    +0x4B = SEL_STEREO_3 +

    +
    • +
  • +

    +0x50 = SEL_SWAP_READY_OUT_0 +

    +
    • +
  • +

    +0x51 = SEL_SWAP_READY_OUT_1 +

    +
    • +
  • +

    +0x52 = SEL_SWAP_READY_OUT_2 +

    +
    • +
  • +

    +0x53 = SEL_SWAP_READY_OUT_3 +

    +
    • +
  • +

    +0x58 = SEL_THERMAL_OVERT +

    +
    • +
  • +

    +0x59 = SEL_FAN_ALERT +

    +
    • +
  • +

    +0x5A = SEL_THERMAL_LOAD_STEP_0 +

    +
    • +
  • +

    +0x5B = SEL_THERMAL_LOAD_STEP_1 +

    +
    • +
  • +

    +0x5C = SEL_PWM_OUTPUT +

    +
    • +
  • +

    +0x80 = SEL_SOR0_TMDS_OUT_PWM +

    +
    • +
  • +

    +0x81 = SEL_SOR0_TMDS_OUT_PINA +

    +
    • +
  • +

    +0x82 = SEL_SOR0_TMDS_OUT_PINB +

    +
    • +
  • +

    +0x84 = SEL_SOR1_TMDS_OUT_PWM +

    +
    • +
  • +

    +0x85 = SEL_SOR1_TMDS_OUT_PINA +

    +
    • +
  • +

    +0x86 = SEL_SOR1_TMDS_OUT_PINB +

    +
    • +
  • +

    +0x88 = SEL_SOR2_TMDS_OUT_PWM +

    +
    • +
  • +

    +0x89 = SEL_SOR2_TMDS_OUT_PINA +

    +
    • +
  • +

    +0x8A = SEL_SOR2_TMDS_OUT_PINB +

    +
    • +
  • +

    +0x8C = SEL_SOR3_TMDS_OUT_PWM +

    +
    • +
  • +

    +0x8D = SEL_SOR3_TMDS_OUT_PINA +

    +
    • +
  • +

    +0x8E = SEL_SOR3_TMDS_OUT_PINB +

    +
    • +
+
Input HW select (28:24)

This field specifies the input HW function number which needs to be +routed to the given pin (given by GPIO Number) which is also equivalent +to the index of the INPUT_CNTL register that needs to be programmed.

+

Right now the manual specifies space for 24 functions(1-24) which are +given below. Note that 0 is not a valid input function in HW and is used +only to specify that no input function needs to be programmed on the +given pin.

+
    +
  • +

    +00 / 0x00 = No Input function needs to be programmed on the given pin. Note that 0 is not a valid input value in HW. +

    +
    • +
  • +

    +01 / 0x01 = NV_PMGR_GPIO_INPUT_FUNC_AUX_HPD(0) +

    +
    • +
  • +

    +02 / 0x02 = NV_PMGR_GPIO_INPUT_FUNC_AUX_HPD(1) +

    +
    • +
  • +

    +03 / 0x03 = NV_PMGR_GPIO_INPUT_FUNC_AUX_HPD(2) +

    +
    • +
  • +

    +04 / 0x04 = NV_PMGR_GPIO_INPUT_FUNC_AUX_HPD(3) +

    +
    • +
  • +

    +09 / 0x09 = NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC(0) +

    +
    • +
  • +

    +10 / 0x0A = NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC(1) +

    +
    • +
  • +

    +11 / 0x0B = NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC(2) +

    +
    • +
  • +

    +12 / 0x0C = NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC(3) +

    +
    • +
  • +

    +17 / 0x11 = NV_PMGR_GPIO_INPUT_FUNC_SWAP_READY(0) +

    +
    • +
  • +

    +18 / 0x12 = NV_PMGR_GPIO_INPUT_FUNC_SWAP_READY(1) +

    +
    • +
  • +

    +21 / 0x15 = NV_PMGR_GPIO_INPUT_FUNC_THERMAL_OVERTEMP +

    +
    • +
  • +

    +22 / 0x16 = NV_PMGR_GPIO_INPUT_FUNC_THERMAL_ALERT +

    +
    • +
  • +

    +23 / 0x17 = NV_PMGR_GPIO_INPUT_FUNC_POWER_ALERT +

    +
    • +
  • +

    +24 / 0x18 = NV_PMGR_GPIO_INPUT_FUNC_TACH +

    +
    • +
+
GSYNC Header (29:29)

GSYNC Header Connection. Possible values are:

+
    +
  • +

    +0 - Not Connected +

    +
    • +
  • +

    +1 - Connected +

    +
    • +
+

RM is responsible for discerning Raster Sync or Flip Lock from the GPIO +Function.

+
Pulse Width Modulate (PWM)

If this bit is 1, then this GPIO is used with PWM.

+
Lock Pin Number (35:32)

The lock pin number associated with this entry. In ISO designs there are +currently four lock pins that are either assigned to GPIO pins or +internal dedicated pins. This only applies to a subset of GPIO +functions. Depending on the chip, some lock pins are done with real +GPIO’s so they have a real GPIO number and the I/O Type Field is set to +NV_GPIO_IO_TYPE_GPIO, while other lock pins do not have a real GPIO so +they are set to NV_GPIO_IO_TYPE_DEDICATED_LOCK_PIN and the GPIO number +is meaningless (but is always set to zero). This field must be 0xF for +GPIO functions that do not involve a lock pin.

+
Off Data (FT) (36:36)

This field determines in what physcial data output must be present on the +GPIO pin to indicate the logical OFF signal. If this bit is 0, then the +software will set the GPIO pin to 0 when it wants to turn the function +off.

+
Off Enable (FE) (37:37)

This field determines in which physical direction the GPIO should be placed +when requesting the logical function to be OFF. If this bit is 0, then +the GPIO will be set as an Output when OFF is requested. If this bit is +a 1, then the GPIO will be set as an Input when OFF is requested.

+
On Data (OT) (38:38)

This field determines what physical data output must be present on the +GPIO pin to indicate the logical ON signal. If this bit is 0, then the +software will set the GPIO pin to 0 when it wants to turn the function +on.

+
On Enable (OE) (39:39)

This field determines in which physical direction the GPIO should be placed +when requesting the logical function to be ON. If this bit is 0, then +the GPIO will be set as an Output when ON is requested. If this bit is +a 1, then the GPIO will be set as an Input when ON is requested.

+
+
+

Note:

+

Some GPIOs have some overloading with HW Slowdown features and the +detected presence of a thermal chip. +HW Slowdown consists of two parts:

+
    +
  1. +

    +Enabling/Disabling the functionality through GPIO 8. (Note, this + functionality is only available on NV18 and NV30+ chips.) +

    +
    2. +
  2. +

    +Triggering GPIO 8 when the functionality is enabled. The trigger can + come from a thermal device, external power connector, some logic on the + board, a combination of the above, etc. The trigger method is what the GPIO + function should define, but by defining it, we understand that we must + enable HW slowdown (A) as well. +

    +
    3. +
+

Trigger or Assert implies that the GPIO 8 is brought LOW and since the +functionality is enabled (A), the HW Clocks are reduced by 2x, 4x or +8x. The opposite of trigger/assert is deassert.

+

In most cases today, HW Slowdown is set to ACTIVE LOW due to the ACTIVE +LOW signal from the thermal chips. We can program GPIO 8 based HW +Slowdown to be ACTIVE HIGH, but then the trigger level for the line +routed to GPIO 8 must follow the ACTIVE HIGH signaling.

+

Here is a list of all the different GPIO functions and their meaning in +relationship to the above:

+
    +
  • +

    +16 = Thermal and External Power Detect: If attached to GPIO 8, assumes + HW Slowdown enabled (A). If thermal device is not found, HW Slowdown is + disabled (A). Here’s a logical diagram of this connection: + +Thermal GPIO and Power routing + +

    +
    • +
  • +

    +17 = Thermal Event Detect: Same as above, but without the Power + Connected signal. Specifically, the Thermal ASSERT is routed directly to + GPIO 8. +

    +
    • +
  • +

    +34 = Required Power Sense: This version is similar to Thermal and + External Power Detect, but without the Thermal ASSERT signal. Specifically, + the Power Connected signal is routed directly to GPIO 8. The intention of + the SW is to disable HW Slowdown (A) with this function. +

    +
    • +
  • +

    +39 = Optional Power Sense: Same as Required Power Sense with regards to + HW Slowdown. +

    +
    • +
  • +

    +42 = SW Performance Level Slowdown: This GPIO function will act as a trigger + point for the SW to lower the clocks. HW Slowdown (A) is not enabled. +

    +
    • +
  • +

    +43 = HW Slowdown Enable: This function strictly allows for an undefined + trigger point to cause HW Slowdown. There is no requirement to have a + thermal device present in order to use HW Slowdown as in the functions + Thermal and External Power Detect (16) and Thermal Event Detect (17). +

    +
    • +
  • +

    +44 = Disable Power Sense. If asserted, this GPIO will remove the + power sense circuit from affecting HW Slowdown. Note that HW Slowdown + enable/disable (A) is not affected by the usage of this functionality. This + function exists only to change the trigger method (B) for HW Slowdown. Here’s + a logical diagram of this connection: + +Thermal GPIO and Power with Disable routing + +

    +
    • +
  • +

    +52 = Thermal Alert and 53 = Thermal Critical. Although we have other thermal + inputs that are tied to GPIO8, these can be assigned to any GPIO, and can + cover many different situations. +

    +
    • +
  • +

    +79 = The Analogix Encoder implements clock stretching in a manner that our SW + emulated I2C cannot properly handle. To workaround this issue, a keeper + circuit is added to detect slave issued stretches on the SCL and hold the SCL + line. This allows our GPU to properly communicate with the Analogix chip. + The keeper circuit is turned on and off at specific points during the I2C + transaction. +

    +
    • +
+
+
+ + + +
+
Note
+		The presence of the GSYNC header can be positively determined by (1 == +GSYNCRasterSync) for any non-skip entry or (1 == GSYNCFlipLock) for any +non-skip entry.
+
+
+

Lock Pins

+

There is a subset of GPIO functions that are "lock pins". +In the case of an entry that has one of these lock pin GPIO functions, +the Lock Pin Number Field tells which lock pin the functionality is +mapped to.

+

Depending on the chip, some lock pins are done with real GPIOs so they +have a real GPIO number and the I/O Type Field is set to +NV_GPIO_IO_TYPE_GPIO, while other lock pins do not have a real GPIO so +they are set to NV_GPIO_IO_TYPE_DEDICATED_LOCK_PIN and the GPIO number +is meaningless (but is always set to zero).

+

Lockpins can be thought of as IO interface to the display HW. +For example; a head/rg can be programmed to be connected to a +lockpin. The lockpin can interface with GPIOs on the other side.

+

+Stall lock pin configuration +

+
+
+
+

External GPIO Assignment Master Table

+

Some boards require extra control, since we don’t have enough internal +GPIO pins to manage them. The board designers add an external chip +that is used to control more GPIO pins on the board. Because we expect +that there could be more than just one external GPIO controller on the +board, we have separated the tables into Master and Specific. The Master +table lists pointers to all the different external GPIO controllers on +the board. The Specific Table lists the data associated with one +controller on the board. A pointer to the External GPIO Assignment +Master Table is found in the GPIO Assignment Table Header.

+

The Master Table is made up of two parts: the Header and the Entries. The +Entries follow immediately after the Header.

+
+

External GPIO Assignment Master Table Header

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Entry Size = 2

Entry Count

Header Size = 4

Version = 0x40

+
+
Version

Version number of the GPIO Assignment Master Table Header and Entries. The +GPIO Assignment Master Table version will start with 4.0, or a value +of 0x40, in this field. If this version is 0, then the driver will +assume that this table is invalid.

+
Header Size

Size of the GPIO Assignment Master Table Header in bytes. Initially, +this is 4 bytes.

+
Entry Count

Number of GPIO Assignment Table Entries starting directly after the end +of this header.

+
Entry Size

Size of each Master Table Entry in bytes. Initially, this is 2 bytes.

+
+
+

External GPIO Assignment Master Table Entry

+
+ ++++ + + + + + + + + + + + + + +
Name Bit width Values and Meaning

External GPIO Assignment Specific Table Pointer

16

Pointer to an External GPIO Assignment Specific Table. A value of 0 +here means skip entry.

+
+
+
+
+

External GPIO Assignment Specific Table

+

The Specific Table is made up of two parts, the Header and the Entries. +The Entries follow immediately after the Header.

+
+

External GPIO Assignment Specific Table Header

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Entry Size = 4

Entry Count

Header Size = 7

Version = 0x40

+
+
+ +++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
555453525150494847464544434241403938373635343332

Rsvd

P

Rsvd

xInt

I2C Address

External Type

+
+
Version

Version number of the GPIO Assignment Specific Table Header and Entries. The +GPIO Assignment Master Table will version will start with 4.0, or a value +of 0x40, in this field. If this version is 0, then the driver will +assume that this table is invalid.

+
Header Size

Size of the GPIO Assignment Specific Table Header in bytes. Initially, +this is 7 bytes.

+
Entry Count

Number of GPIO Assignment Specific Table Entries starting directly after the +end of this table.

+
Entry Size

Size of each Specific Table Entry in bytes. Initially, this is 4 bytes.

+
External Type

The actual chip used to control the GPIO pins. Possible values are:

+
    +
  • +

    +0: Unknown - Used to signify to skip an entire Specific Table. +

    +
    • +
  • +

    +1: PCA9555 for 10-pin Personal Cinema VIVO pods +

    +
    • +
  • +

    +2: ADT7473 Automatic Fan Controller Chip +

    +
    • +
  • +

    +3: CX25875 General Purpose Output pins +

    +
    • +
  • +

    +4: PCA9555 for GPIO pins on MXM external HDMI control +

    +
    • +
  • +

    +5: PCA9536 for GPIO pins for HDMI/DVI Multiplexing +

    +
    • +
  • +

    +6: PCA9555 for GPIOs +

    +
    • +
  • +

    +7: PCA9536 for GPIOs +

    +
    • +
  • +

    +8: PCA9555 for Napoleon +

    +
    • +
  • +

    +9: ANX9805 for GPIOs +

    +
    • +
  • +

    +A: Pic18f24k20 GPIO expander +

    +
    • +
+
I2C Address

7-bit I2C communication Address left shifted to bits 7:1, with a 0 in +bit 0. This is the standard I2C address specification for SW.

+
External Device Interrupt Number (xInt)

This field gives the number of the external interrupt pin that is used +to signal interrupt requests by this device. Possible values are:

+
    +
  • +

    +0: No interrupts will be generated by this device +

    +
    • +
  • +

    +1: The function "GPIO Expansion 1 Interrupt" from the GPIO Assignment table + will signal interrupts for this device +

    +
    • +
  • +

    +2: reserved for future use +

    +
    • +
  • +

    +3: reserved for future use +

    +
    • +
+
External Communications Port (P)

This field defines which communications port is used for this device. +See the I2C Control Block Header for the listing of the Primary and +Secondary Communication ports.

+
+
+

External GPIO Assignment Specific Table Entry

+

Each entry here is defined exactly like the internal GPIO Entries. The +only differences are:

+
    +
  • +

    +The GPIO number associated here. If the External GPIO labels its +GPIOs with numbers, we will use their number labels for the GPIO +number here. If the external chip does not label with numbers, but +labels them like "GPIO ABC", then we’ll use the GPIO pin that is +closest to pin 0 of the part as GPIO 0. +

    +
    • +
  • +

    +The GPIO functions associated here. All functions must be explicitly +defined for any given External Type. They can be defined exactly like +the internal internal GPIO Entries, but it must be explicitly defined +that way. A complete list of function code definitions for each +defined External Type will be added to this document, as they are +defined. +

    +
    • +
  • +

    +The SKIP ENTRY is defined by the value 0 for all External GPIO +Types instead of 63. +

    +
    • +
+
+
+

GPIO Entries for External Type 1 - PCA9555 for 10-pin Personal Cinema VIVO pods

+

For this particular External Type ("1: PCA9555 for 10-pin Personal +Cinema VIVO pods") there is a physical limit of 16 GPIO pins.

+

Here are the functions as listed for External Type 1

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = DTERM_LINE1A: used to control Japanese HDTV sets. +

    +
    • +
  • +

    +2 = CONFIG_480p576p: indicates whether the user desires 480p/576p support +

    +
    • +
  • +

    +3 = DTERM_LINE1B: used to control Japanese HDTV sets. +

    +
    • +
  • +

    +4 = CONFIG_720p: indicates whether the user desires 720p support +

    +
    • +
  • +

    +5 = DTERM_LINE2A: used to control Japanese HDTV sets. +

    +
    • +
  • +

    +6 = CONFIG_1080i: indicates whether the user desires 1080i support +

    +
    • +
  • +

    +7 = DTERM_LINE2B: used to control Japanese HDTV sets. +

    +
    • +
  • +

    +8 = DTERM_LINE3A: used to control Japanese HDTV sets. +

    +
    • +
  • +

    +9 = POD_LOAD_DET: used to detect connections to SDTV connectors +

    +
    • +
  • +

    +10 = DTERM_LINE3B: used to control Japanese HDTV sets. +

    +
    • +
  • +

    +11 = POD_SEL_2ND_DEV: used to activate SDTV connectors +

    +
    • +
  • +

    +12 = DTERM_SENSE: used to detect connections to Japanese HDTV connectors +

    +
    • +
  • +

    +13 = CONFIG_SDTV_NOT_COMPONENT:: indicates whether the user prefers SDTV or component output as the boot default. +

    +
    • +
  • +

    +14 = POD_LOCALE_BIT0: used to indicate the geopolitical locale of the POD design. See interpretation below. +

    +
    • +
  • +

    +15 = POD_LOCALE_BIT1: used to indicate the geopolitical locale of the POD design. See interpretation below. +

    +
    • +
+

The locale bits are interpreted with this table

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + +

0

0

North America YPrPb POD

1

0

Japanese D-Connector POD

0

1

European SCART with RGB POD

1

1

Reserved

+
+
+
+

GPIO Entries for External Type 2 - ADT7473 Automatic Fan Controller Chip

+

Currently, there will be only one GPIO defined for this chip.

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = FANCONTROL: This GPIO will provide on, off, or on with PWM control. In + addition, when set as an input, the fan controller will switch to automatic + temperature-based fan control. +

    +
    • +
+

There are 3 physical fan controllers on this chip. To reference any of these, +use the GPIO Number to differentiate each controller.

+
+
+

GPIO Entries for External Type 3 - CX25875 General Purpose Output pins

+

There are 3 physical GPIO pins on this chip. Additional GPIO +functionality may be added in a future revision.

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = SCART_RGB: Used to control the TV output as Composite (low) or RGB format (high). +

    +
    • +
  • +

    +2 = SCART_VIDEO_ASPECT: used to control ouput picture as 16x9 (low) or 4x3 (high). +

    +
    • +
+
+
+

GPIO Entries for External Type 4 - PCA9555 for GPIO pins on MXM external HDMI

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = Digital Encoder Interrupt Enable: used to control I2C CLK line for SI1930 firmware update. +

    +
    • +
  • +

    +2 = si1930uC Programming: used to control SI1930 firmware update. +

    +
    • +
  • +

    +3 = si1930uC Reset: used to control reset signal of SI1930 uC. +

    +
    • +
+
+
+

GPIO Entries for External Type 5 - PCA9536 for GPIO pins for HDMI/DVI Multiplexing

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = DVI/HDMI Select: controls whether the display data is routed to the DVI + device or to the HDMI device. +

    +
    • +
  • +

    +2 = I2C HDMI Enable: enables or disables the I2C bus for the HDMI device. +

    +
    • +
  • +

    +3 = I2C DVI Enable: enables or disables the I2C bus for the DVI device. +

    +
    • +
+

Note that HDMI and DVI enable are mutually exclusive and may never be +asserted at the same time. See table below for additional information.

+
+ +++++ + + + + + + + + + + + + + + + + + + + +

DVI/HDMI Select

I2C HDMI Enable

I2C DVI Enable

DVI-Mode

1

0

1

HDMI-Mode

0

1

0

+
+
+
+

GPIO Entries for External Type 6 and 7 - PCA9555 and PCA9536 for GPIOs

+

This define was originally defined to support MXM, but has more general +applicability.

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = Output Device Control: Used for DDC Bus Expander or Mux control (Switched Outputs) +

    +
    • +
  • +

    +5 = Japanese D connector line 1 +

    +
    • +
  • +

    +6 = Japanese D connector line 2 +

    +
    • +
  • +

    +7 = Japanese D connector line 3 +

    +
    • +
  • +

    +8 = Japanese D connector plug insertion detect +

    +
    • +
  • +

    +9 = Japanese D connector spare line 1 +

    +
    • +
  • +

    +10 = Japanese D connector spare line 2 +

    +
    • +
  • +

    +11 = Japanese D connector spare line 3 +

    +
    • +
  • +

    +12 = VSEL0: Voltage Select Bit 0 +

    +
    • +
  • +

    +13 = VSEL1: Voltage Select Bit 1 +

    +
    • +
  • +

    +14 = VSEL2: Voltage Select Bit 2 +

    +
    • +
  • +

    +15 = VSEL3: Voltage Select Bit 3 +

    +
    • +
  • +

    +16 = VSEL4: Voltage Select Bit 4 +

    +
    • +
  • +

    +17 = VSEL5: Voltage Select Bit 5 +

    +
    • +
  • +

    +18 = VSEL6: Voltage Select Bit 6 +

    +
    • +
  • +

    +19 = VSEL7: Voltage Select Bit 7 +

    +
    • +
  • +

    +31 = LCD Self Test +

    +
    • +
  • +

    +32 = LCD Lamp Status +

    +
    • +
  • +

    +36 = HDTV Select: Allows selection of lines driven between SDTV (OFF state) and HDTV (ON state) +

    +
    • +
  • +

    +37 = HDTV Alt-Detect: Allows detection of the connectors that are not + selected by HDTV Select. That is, if HDTV Select is currently selecting SDTV, + then this GPIO would allow us detect the presence of the HDTV connection. +

    +
    • +
+
+
+

GPIO Entries for External Type 8 - PCA9555 for S/PDif Detect and TV resolution LEDs

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = LED for 480/576i (Output) +

    +
    • +
  • +

    +2 = LED for 480/576p (Output) +

    +
    • +
  • +

    +3 = LED for 720p (Output) +

    +
    • +
  • +

    +4 = LED for 1080i (Output) +

    +
    • +
  • +

    +5 = LED for 1080p (Output) +

    +
    • +
  • +

    +6 = HDAudio Signal Detect (Input) +

    +
    • +
  • +

    +7 = S/PDif 0 (Coax) Signal Detect (Input) +

    +
    • +
  • +

    +8 = S/PDif 1 (Header) Signal Detect (Input) +

    +
    • +
  • +

    +9 = S/PDif Input Select - 0. Coax, 1. Header (Output) +

    +
    • +
  • +

    +10 = Panic Button - Resets screen resolution to the lowest possible setting (Input) +

    +
    • +
  • +

    +11 = Resolution Change Button - Changes the screen resolution to its next highest setting (Input) +

    +
    • +
+
+
+

GPIO Entries for External Type 9 - ANX9805 External DP Encoder GPIO

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = DP2DVI Dongle A: This GPIO is used to detect DP2DVI dongle’s presence + (input) and is associated with the Connector Table’s DP2DVI A bit. +

    +
    • +
  • +

    +2 = DP2DVI Dongle B: This GPIO is used to detect DP2DVI dongle’s presence + (input) and is associated with the Connector Table’s DP2DVI B bit. +

    +
    • +
  • +

    +3 = DP2DVI Dongle C: This GPIO is used to detect DP2DVI dongle’s presence + (input) and is associated with the Connector Table’s DP2DVI C bit. +

    +
    • +
  • +

    +4 = DP2DVI Dongle D: This GPIO is used to detect DP2DVI dongle’s presence + (input) and is associated with the Connector Table’s DP2DVI D bit. +

    +
    • +
+
+
+

GPIO Entries for External Type A Pic18f24k20 GPIO expander for P678/668

+
    +
  • +

    +0 = SKIP ENTRY: This allows for quick removal of an entry from the GPIO Assignment table. +

    +
    • +
  • +

    +1 = Output Device Control: Used for DDC Bus Expander or Mux control (Switched Outputs). +

    +
    • +
+
+
+
+
+
+

Spread Spectrum Table

+
+

This table is not required in the ROM. This table only needs to be +defined if the specific board requires spread spectrum. This table will +be used by both the VBIOS and the driver.

+
+

Spread Spectrum Table Header

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Version

8

Version # of the Spread Spectrum Table Header and Entries. The current +Spread Spectrum Table is version with 4.1, a value of 0x41 for this +field. If the version is 0, then this table will be considered invalid +and the driver will not use spread spectrum.

Header Size

8

Size of the Spread Spectrum Table Header in Bytes. Version 4.1 starts +with 5 bytes.

Entry Count

8

Number of Spread Spectrum Table Entries starting directly after the end +of this table.

Entry Size

8

Size of Each Entry in bytes. Version 4.1 are currently 2 bytes each.

Flags

8

Flags for Spread Spectrum, currently unused. All bits are reserved and +set to 0.

+
+
+
+

Spread Spectrum Table Entry

+
+ +++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
1514131211109876543210

R

T

FreqDt

Indx

R

VS

V

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

V

1

Set if this is a valid entry

VS

2

VPLL spread Source

R

1

Reserved, set as 0

Indx

4

DCB Index

FreqDt

6

Frequency Delta in 0.05% units

T

1

Spread profile type, 0 = center, 1 = down

R

1

Reserved, set as 0

+
+
Valid

This field defines whether this entry is valid or not. Defined values are:

+
    +
  • +

    +0 = Entry is invalid and should be skipped. +

    +
    • +
  • +

    +1 = Entry is valid. +

    +
    • +
+
VPLL Source

This field lists the source of the VPLL spread. Defined values are:

+
    +
  • +

    +0 = Reference, GPU Internal Source 0 (INTERNAL_SPREAD_0) +

    +
    • +
  • +

    +1 = Reference, GPU Internal Source 1 (INTERNAL_SPREAD_1) +

    +
    • +
  • +

    +2 = Reference, GPU External Source (EXTERNAL_SPREAD) +

    +
    • +
  • +

    +3 = Self, PLL Internal Mechanism +

    +
    • +
+
DCB Index

This field lists the associated DCB Index device that should enable +spread on VPLL while in use.

+
Frequency Delta

Delta from target frequency (0.05%).

+
Spread Type

Spread profile type. Defined values are:

+
    +
  • +

    +0 = Center Spread +

    +
    • +
  • +

    +1 = Down Spread +

    +
    • +
+
Notes

The Frequency Delta and Type fields inside the Entry above are only used +when VPLL Source is set to 3 (i.e., Self, PLL Internal Mechanism). When +calculating the configuration for the VPLL’s own spread, Frequency Delta +should be interpreted as delta from target frequency such that center +spread has a bandwidth of

+
+
+
  (2 x SpreadSpectrumTableEntry.FrequencyDelta)
+
+

and down spread has a bandwidth of

+
+
+
  (1 x SpreadSpectrumTableEntry.FrequencyDelta)
+
+

The target modulation frequency is assumed to be 33 kHz.

+
+
+
+
+

I2C Device Table

+
+

This table is not required in the ROM. This table only needs to be +defined if the board requires some specific driver handling of an I2C +device. This table will be used only by the the driver.

+

Specifically, this table grew from the need to define various new I2C HW +monitoring devices as well as HDTV chips.

+
+

I2C Device Table Header

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Entry Size = 4

Entry Count

Header Size = 5

Version = 0x40

+
+
+ +++++++++ + + + + + + + + + + + + + + + + +
3938373635343332

Flags

+
+
Version

Version # of the I2C Device Table Header and Entries. The version will +start with 4.0, a value of 0x40 here. If this version is 0, then the +driver will consider this table as invalid and will not use any of the +data present here.

+
Header Size

Size of the I2C Device Table Header in Bytes. Initially, this is 5 +bytes.

+
Entry Count

Number of I2C Device Table Entries starting directly after the end of +this table.

+
Entry Size

Size of Each Entry in bytes. Version 4.0 starts with 4 bytes.

+
Flags

Flags for I2C Devices.

+

Currently defined fields are:

+
    +
  • +

    +Bit 0 : Disable External Device Probing: The driver spends some time +probing for external devices like the framelock, SDI boards, or Thermal +devices not found in the thermal tables. This bit is added to notify +the driver that probing isn’t required because the board doesn’t support +it. If set to 0, probing will still occur as normal. If set to 1, it +will disable the probing on the board. +

    +
    • +
  • +

    +Bits 1-7 : Reserved. Set as 0. +

    +
    • +
+
+
+

I2C Device Table Header Version 4.0 Prior Sizes

+
+ ++++ + + + + + + + + + + + + + + + + + + +
DATE New Size Last Inclusive Field

Start

4 Bytes

Entry Size

09-14-06

5 Bytes

Flags

+
+
+
+

I2C Device Table Entry

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Rsvd

RA

WA

P

Rsvd

I2C Address

Type

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Type

8

Device (chip) type

I2C Address

8

8 bit adjusted I2C address (LSB 0)

Rsvd

4

Reserved, set to 0

P

1

External Communications Port

WA

3

Write Access privilege level

RA

3

Read Access privilege level

Rsvd

5

Reserved, set to 0

+
+
Type

Currently defined values are:

+
    +
  • +

    +THERMAL CHIPS +

    +
      +
    • +

      +0x01 = ADM 1032 +

      +
      • +
    • +

      +0x02 = MAX 6649 +

      +
      • +
    • +

      +0x03 = LM99 +

      +
      • +
    • +

      +0x06 = MAX 1617 +

      +
      • +
    • +

      +0x07 = LM64 +

      +
      • +
    • +

      +0x0A = ADT7473 +

      +
      • +
    • +

      +0x0B = LM89 +

      +
      • +
    • +

      +0x0C = TMP411 +

      +
      • +
    • +

      +0x04, 0x05, 0x08, and 0x09 = deprecated. +

      +
      • +
    +
    • +
  • +

    +I2C ANALOG TO DIGITAL CONVERTERS +

    +
      +
    • +

      +0x30 = ADS1112 +

      +
      • +
    +
    • +
  • +

    +I2C POWER CONTROLLERS +

    +
      +
    • +

      +0xC0 = PIC16F690 micro controller +

      +
      • +
    • +

      +0x40 = VT1103 +

      +
      • +
    • +

      +0x41 = PX3540 Primarion PX3540 Digital Multiphase PWM Voltage Controller +

      +
      • +
    • +

      +0x42 = Volterra VT1165 +

      +
      • +
    • +

      +0x43 = CHiL CHL8203/8212/8213/8214 +

      +
      • +
    +
    • +
  • +

    +SMBUS POWER CONTROLLERS +

    +
      +
    • +

      +0x48 = CHiL CHL8112A/B, CHL8225/8228 +

      +
      • +
    • +

      +0x49 = CHiL CHL8266, CHL8316 +

      +
      • +
    +
    • +
  • +

    +POWER SENSORS +

    +
      +
    • +

      +0x4C = INA219 +

      +
      • +
    • +

      +0x4D = INA209 +

      +
      • +
    • +

      +0x4E = INA3221 +

      +
      • +
    +
    • +
  • +

    +1 CLOCK GENERATORS +

    +
      +
    • +

      +0x50 = Cypress CY2XP304 +

      +
      • +
    +
    • +
  • +

    +GENERAL PURPOSE GPIO CONTROLLERS +

    +
      +
    • +

      +0x60 = Philips PCA9555 device for EIAJ-4120 - Japanese HDTV support +

      +
      • +
    +
    • +
  • +

    +FAN CONTROLS +

    +
      +
    • +

      +0x70 = ADT7473, dBCool Fan Controller +

      +
      • +
    +
    • +
  • +

    +HDMI COMPOSITOR/CONVERTER DEVICES +

    +
      +
    • +

      +0x80 = Silicon Image Microcontroller SI1930uC device for HDMI Compositor/Converter +

      +
      • +
    +
    • +
  • +

    +GPU I2CS CONTROLLERS +

    +
      +
    • +

      +0xB0 = GT21X - GF10X I2CS interface +

      +
      • +
    • +

      +0xB1 = GF11X and beyond I2CS interface +

      +
      • +
    +
    • +
  • +

    +DISPLAY ENCODER TYPES +

    +
      +
    • +

      +0xD0 = Anx9805 +

      +
      • +
    +
    • +
  • +

    +0xFF = Skip Entry. This allows for quick removal of an entry from the I2C Devices Table. +

    +
    • +
+
I2C Address

8-bit aligned, right shifted 7-bit address of the I2C device. The I2C +spec defines 7 bits for the address [7:1] of the device with 1 bit for +R/W [0:0]. So, generally, most addresses are listed in their 8 bit +adjusted form with 0 for the R/W bit. This field must list that 8-bit +adjusted address.

+
External Communications Port

This field defines which communications port is used for this +device. See the I2C Control Block Header for the listing of the Primary +and Secondary Communication ports.

+
Write Access

This field defines the write access privileges to specific +levels.

+

Currently defined values are: +* 0x0-0x7 = Reserved

+
Read Access

This field defines the read access privileges to specific +levels.

+

Currently defined values are:

+
    +
  • +

    +0x0-0x7 = Reserved +

    +
    • +
+
+
+
+
+

Connector Table

+
+

This table is required in the ROM. This table should always be defined +to allow graphical representations of the board to be created. This +table will be used only by the the driver.

+

For purposes of this table a connector is defined as the end point on +the display path where one display can be attached. This may be the +card edge or attachment points on a breakout cable.

+

A connector can only output one stream at a time. So, if you have a +Low-Force Helix (LFH) port on the back of the card, the connector is defined as a DVI-I +adapter of that breakout cable. That is, there are 2 connectors for +every 1 LFH port on the back of a card.

+
+

Connector Table Header

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Entry Size = 4

Entry Count

Header Size = 5

Version = 0x40

+
+
+ +++++++++ + + + + + + + + + + + + + + + + +
3938373635343332

Platform

+
+
Version

Version # of the Connector Table Header and Entries. The Version will +start with 4.0, a value of 0x40 here. If this version is 0, then the +driver will consider this table as invalid and will not use any of the +data present here.

+
Header Size

Size of the Connector Table Header in bytes. Initially, this is 5 bytes.

+
Entry Count

Number of Connector Table Entries starting directly after the end of +this table header.

+
Entry Size

Size of Each Entry in bytes. Currently 4 bytes.

+
+ +++ + + + + + + + + + + + + + + + +
DATE New Size

Start

2 Bytes

2007-06-19

4 Bytes

+
+
Platform

This field specifies the layout of the connectors.

+

Currently defined values are:

+
    +
  • +

    +0x00 = Normal Add-in Card +

    +
    • +
  • +

    +0x01 = Two back plate Add-in Cards (Used for tall fan sinks that cause adjacent PCI connection to be unusable) +

    +
    • +
  • +

    +0x02 = Add-in card (Configurable) - All I2C ports need to be rescanned at boot for possible external device changes. +

    +
    • +
  • +

    +0x07 = Desktop with Integrated full DP +

    +
    • +
  • +

    +0x08 = Mobile Add-in Card. Generally have LVDS-SPWG connector on the north edge of the card away from the AGP/PCI bus. +

    +
    • +
  • +

    +0x09 = MXM module +

    +
    • +
  • +

    +0x10 = Mobile system with all displays on the back of the system. +

    +
    • +
  • +

    +0x11 = Mobile system with display connectors on the back and left of the system. +

    +
    • +
  • +

    +0x18 = Mobile system with extra connectors on the dock +

    +
    • +
  • +

    +0x20 = Crush (nForce chipset) normal back plate design +

    +
    • +
+
+
+

Connector Table Entry

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Rsvd

LCD ID

SRA

G

F

E

DID

DIC

DIB

DIA

DPD

DPC

D

C

DPB

DPA

B

A

Location

Type

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Type

8

Connector Type

Location

4

Physical location description

A

1

Hotplug A interrupt generation

B

1

Hotplug B interrupt

DPA

1

DP2DVI A

DPB

1

DP2DVI B

C

1

Hotplug C interrupt

D

1

Hotplug D interrupt

DPC

1

DP2DVI C

DPD

1

DP2DVI D

DIA

1

DPAux/I2C-A

DIB

1

DPAux/I2C-B

DIC

1

DPAux/I2C-C

DID

1

DPAux/I2C-D

E

1

Hotplug E interrupt

F

1

Hotplug F interrupt

G

1

Hotplug G interrupt

SRA

1

Panel Self Refresh frame lock A interrupt

LCDID

3

LCD interrupt GPIO pin

R

1

Reserved, set to 0

+
+
Type

Descriptive name of each connector where only one signal may be +displayed through that connector at any given time.

+

If there is a breakout cable where multiple displays can be displayed +through that breakout cable at the same time, generally the type should +be listed as Breakout Cable Name - End connector, or Initial Connector - +Final Connector. Example: LFH - DVI-I - 1.

+

Because TV’s can allow more than one connector per TV encoder, all +connectors associated with the TV device must be grouped together. The +DCB Display Path will point to the first TV connector on the list. The +DCB TV DSI Connector Count field will list how many connectors are +available for the TV.

+

All devices are considered detachable (or removable) unless otherwise noted.

+

Currently defined values are:

+
    +
  • +

    +0x00 = VGA 15-pin connector +

    +
    • +
  • +

    +0x01 = DVI-A +

    +
    • +
  • +

    +0x02 = Pod - VGA 15-pin connector +

    +
    • +
  • +

    +0x10 = TV - Composite Out +

    +
    • +
  • +

    +0x11 = TV - S-Video Out +

    +
    • +
  • +

    +0x12 = TV - S-Video Breakout - Composite (Used for board that list 2 of the RGB bits in the TVDACs field) +

    +
    • +
  • +

    +0x13 = TV - HDTV Component - YPrPb +

    +
    • +
  • +

    +0x14 = TV - SCART Connector +

    +
    • +
  • +

    +0x16 = TV - Composite SCART over the BLUE channel of EIAJ4120 (D-connector) +

    +
    • +
  • +

    +0x17 = TV - HDTV - EIAJ4120 Connector (aka D-connector) +

    +
    • +
  • +

    +0x18 = Pod - HDTV - YPrPb +

    +
    • +
  • +

    +0x19 = Pod - S-Video +

    +
    • +
  • +

    +0x1A = Pod - Composite +

    +
    • +
  • +

    +0x20 = DVI-I-TV-S-Video +

    +
    • +
  • +

    +0x21 = DVI-I-TV-Composite +

    +
    • +
  • +

    +0x22 = DVI-I-TV-S-Video Breakout-Composite (Used for board that list 2 of the RGB bits in the TVDACs field) +

    +
    • +
  • +

    +0x30 = DVI-I +

    +
    • +
  • +

    +0x31 = DVI-D +

    +
    • +
  • +

    +0x32 = Apple Display Connector (ADC) +

    +
    • +
  • +

    +0x38 = LFH-DVI-I-1 +

    +
    • +
  • +

    +0x39 = LFH-DVI-I-2 +

    +
    • +
  • +

    +0x3C = BNC Connector +

    +
    • +
  • +

    +0x40 = LVDS-SPWG-Attached (non-removeable) +

    +
    • +
  • +

    +0x41 = LVDS-OEM-Attached (non-removeable) +

    +
    • +
  • +

    +0x42 = LVDS-SPWG-Detached (removeable) +

    +
    • +
  • +

    +0x43 = LVDS-OEM-Detached (removeable) +

    +
    • +
  • +

    +0x45 = TMDS-OEM-Attached (non-removeable) +

    +
    • +
  • +

    +0x46 = DisplayPort External Connector (as a special case, if the "Location" + field is 0 and the "Platform" type in the Connector Table Header is 7 + (Desktop with Integrated full DP), this indicates a non-eDP DisplayPort + Internal Connector, which is non-removeable) +

    +
    • +
  • +

    +0x47 = DisplayPort Internal Connector(non-removeable) +

    +
    • +
  • +

    +0x48 = DisplayPort (Mini) External Connector +

    +
    • +
  • +

    +0x50 = VGA 15-pin connector if not docked '(See Notes below)' +

    +
    • +
  • +

    +0x51 = VGA 15-pin connector if docked '(See Notes below)' +

    +
    • +
  • +

    +0x52 = DVI-I connector if not docked '(See Notes below)' +

    +
    • +
  • +

    +0x53 = DVI-I connector if docked '(See Notes below)' +

    +
    • +
  • +

    +0x54 = DVI-D connector if not docked '(See Notes below)' +

    +
    • +
  • +

    +0x55 = DVI-D connector if docked '(See Notes below)' +

    +
    • +
  • +

    +0x56 = DisplayPort External Connector if not docked '(See Notes below)' +

    +
    • +
  • +

    +0x57 = DisplayPort External Connector if docked '(See Notes below)' +

    +
    • +
  • +

    +0x58 = DisplayPort (Mini) External Connector if not docked '(See Notes below)' +

    +
    • +
  • +

    +0x59 = DisplayPort (Mini) External Connector if docked '(See Notes below)' +

    +
    • +
  • +

    +0x60 = 3-Pin DIN Stereo Connector +

    +
    • +
  • +

    +0x61 = HDMI-A connector +

    +
    • +
  • +

    +0x62 = Audio S/PDIF connector +

    +
    • +
  • +

    +0x63 = HDMI-C (Mini) connector +

    +
    • +
  • +

    +0x64 = LFH-DP-1 +

    +
    • +
  • +

    +0x65 = LFH-DP-2 +

    +
    • +
  • +

    +0x70 = Virtual connector for Wifi Display (WFD) +

    +
    • +
  • +

    +0xFF = Skip Entry. This allows for quick removal of an entry from the +Connector Table. +

    +
    • +
+
Location

Specific locations depend on the platform type. The SW could define +Real location as ((Platform Type << 4) | This Location Field) if +it’s easier to deal with a single number rather than two separate lists. +Generally, a value of 0 defines the South most connector, which is the +connector on the bracket closest to the AGP/PCI connector. The specific +values here are to be determined.

+
Hotplug A

This field dictates if this connector triggers the Hotplug A interrupt. +If defined, then the Hotplug A interrupt must be defined inside the GPIO +Assignment table.

+
Hotplug B

This field dictates if this connector triggers the Hotplug B interrupt. +If defined, then the Hotplug B interrupt must be defined inside the GPIO +Assignment table.

+
DP2DVI A

This field indictates if this connector is connected to DP to DVI +present A. If defined, then the DisplayPort to DVI dongle A present must +be defined inside the GPIO Assignment table.

+
DP2DVI B

This field indictates if this connector is connected to DP to DVI +present B. If defined, then the DisplayPort to DVI dongle B present must +be defined inside the GPIO Assignment table.

+
Hotplug C

This field dictates if this connector triggers the Hotplug C interrupt. +If defined, then the Hotplug C interrupt must be defined inside the GPIO +Assignment table.

+
Hotplug D

This field dictates if this connector triggers the Hotplug D interrupt. +If defined, then the Hotplug D interrupt must be defined inside the GPIO +Assignment table.

+
DP2DVI C

This field indictates if this connector is connected to DP to DVI +present C. If defined, then the DisplayPort to DVI dongle C present must +be defined inside the GPIO Assignment table.

+
DP2DVI D

This field indictates if this connector is connected to DP to DVI +present D. If defined, then the DisplayPort to DVI dongle D present must +be defined inside the GPIO Assignment table.

+
DPAux/I2C Select A

This field indictates if this connector is connected to DPAUX/I2C select +A. If defined, then the DPAUX/I2C select A must be defined inside the +GPIO Assignment table.

+
DPAux/I2C Select B

This field indictates if this connector is connected to DPAUX/I2C select +B. If defined, then the DPAUX/I2C select B must be defined inside the +GPIO Assignment table.

+
DPAux/I2C Select C

This field indictates if this connector is connected to DPAUX/I2C select +C. If defined, then the DPAUX/I2C select C must be defined inside the +GPIO Assignment table.

+
DPAux/I2C Select D

This field indictates if this connector is connected to DPAUX/I2C select +D. If defined, then the DPAUX/I2C select D must be defined inside the +GPIO Assignment table.

+
Hotplug E

This field dictates if this connector triggers the Hotplug E interrupt. +If defined, then the Hotplug E interrupt must be defined inside the GPIO +Assignment table.

+
Hotplug F

This field dictates if this connector triggers the Hotplug F interrupt. +If defined, then the Hotplug F interrupt must be defined inside the GPIO +Assignment table.

+

Hotplug G. +This field dictates if this connector triggers the Hotplug G interrupt. +If defined, then the Hotplug G interrupt must be defined inside the GPIO +Assignment table.

+
Panel Self Refresh Frame Lock A

This field dictates if this connector triggers the FrameLock A +interrupt. If defined, then the FrameLock A interrupt must be defined +inside the GPIO Assignment table.

+
LCD ID

This field dictates if this connector is connected to LCD# GPIO(s). If +defined, then the LCD# GPIO(s) must be defined inside the GPIO +Assignment table. LCD ID field only applies to the connector types +listed below. All other types must set this field to 0. If +defined, then the FrameLock A interrupt must be defined inside the GPIO +Assignment table.

+

LCD ID only applies for these connector types:

+
    +
  • +

    +0x40 = LVDS-SPWG-Attached (non-removeable) +

    +
    • +
  • +

    +0x41 = LVDS-OEM-Attached (non-removeable) +

    +
    • +
  • +

    +0x42 = LVDS-SPWG-Detached (removeable) +

    +
    • +
  • +

    +0x43 = LVDS-OEM-Detached (removeable) +

    +
    • +
  • +

    +0x45 = TMDS-OEM-Attached (non-removeable) +

    +
    • +
  • +

    +0x46 = DisplayPort with Integrated Full DP (only if the special case described + above in the type field’s entry 0x46 applies) +

    +
    • +
  • +

    +0x47 = DisplayPort Internal Connector(non-removeable) +

    +
    • +
+

Values are:

+
    +
  • +

    +0 = Connected to LCD0 GPIO(s) +

    +
    • +
  • +

    +1 = Connected to LCD1 GPIO(s) +

    +
    • +
  • +

    +2 = Connected to LCD2 GPIO(s) +

    +
    • +
  • +

    +3 = Connected to LCD3 GPIO(s) +

    +
    • +
  • +

    +4 = Connected to LCD4 GPIO(s) +

    +
    • +
  • +

    +5 = Connected to LCD5 GPIO(s) +

    +
    • +
  • +

    +6 = Connected to LCD6 GPIO(s) +

    +
    • +
  • +

    +7 = Connected to LCD7 GPIO(s) +

    +
    • +
+
+

Connector Table Entry Notes

+

There are some connector types, 0x50 through 0x57, that require extra +code in the detection routines inside any code that uses the DCB. +For Mobile systems, some connectors might only be on the actual body of +the notebook. Also, some connectors might only show up on the docking +station. Therefore we need to make sure that we don’t allow anyone +to select a device that is not actually present. So, when we see +connectors with the "if not docked" and "if docked" text in the +description, we must make sure that our detection code checks the docked +condition first and possibly culls any further detection attempts if the +docked condition is not met.

+
+
+
+
+
+

HDTV Translation Table

+
+

Two GPIO functions (HD Dongle Strap 0/1) are defined to allows users to +specify the format of an HDTV connected to the system via an external +switch inside a dongle. Only two pins have been assigned for more than 4 +possible formats (9 as it now) because it is +unlikely that a given GPU board needs to support all formats. This +array is indexed from those two GPIOs which would define the HDTV +format.

+
+

HDTV Translation Table Header

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Entry Size = 1

Entry Count

Header Size = 4

Version = 0

+
+
Version

Version # of the HDTV Translation Table Header and Entries. The HDTV +Translation Table version will start with 0 in this field.

+
Header Size

Size of the HDTV Translation Table in bytes. Initially, this is 4 bytes.

+
Entry Count

Number of HDTV Translation Table Entries starting directly after the end +of this header.

+
Entry Size

Size of each entry in bytes. Initially, this is 1 byte.

+
+
+

HDTV Translation Table Entry

+
+ +++++++++ + + + + + + + + + + + + + + + + + +
76543210

Rsvd

HDStand

+
+
HD Standard

This field lists the specific standard to use for this entry. Defined +values are:

+
    +
  • +

    +0 = HD576i +

    +
    • +
  • +

    +1 = HD480i +

    +
    • +
  • +

    +2 = HD480p_60 +

    +
    • +
  • +

    +3 = HD576p_50 +

    +
    • +
  • +

    +4 = HD720p_50 +

    +
    • +
  • +

    +5 = HD720p_60 +

    +
    • +
  • +

    +6 = HD1080i_50 +

    +
    • +
  • +

    +7 = HD1080i_60 +

    +
    • +
  • +

    +8 = HD1080p_24 +

    +
    • +
+
+
+
+
+

Switched Outputs Table

+
+

There are new designs that allow to change the routing of device +detection, selection, switching and I2C switching by way of a GPIO. +This table assigns the relationship of the routing to specific DCB +indices.

+
+

Switched Outputs Table Header

+
+ +++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
313029282726252423222120191817161514131211109876543210

Entry Size = 5

Entry Count

Header Size = 4

Version = 0x10

+
+
Version

Version # of the Switched Outputs Table Header and Entries. The Switched +Outputs Table will version will start with 0x10 in this field.

+
Header Size

Size of the Switched Outputs Table in bytes.

+
Entry Count

Number of Switched Outputs Table Entries starting directly after the end +of this header.

+
Entry Size

Size of each entry in bytes. Initially, this is 5 bytes.

+
+
+

Switched Outputs Table Entry

+
+ +++++++++++++++++++++++++++++++++++++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
3938373635343332313029282726252423222120191817161514131211109876543210

R

S

GPIO#

T

R

S

GPIO#

T

R

S

GPIO#

T

R

S

GPIO#

T

Rsvd

DCBx

+
+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

DCBx

5

DCB table index for this entry

Rsvd

3

Reserved, set to 0

T

1

Device Selection GPIO Type, 1 = external

GPIO#

5

Device Selection GPIO Number

S

1

Device Selection GPIO State

R

1

Reserved, set to 0

+
+
DCB Index

This index is used to determine which entry in the DCB table this +Switched Output Table entry goes with.

+
Device Selection GPIO Type

This flag determines the location of the control for the GPIO that +controls Device Selection. Defined values are:

+
    +
  • +

    +0 = Internal GPIO or GPU controlled GPIO +

    +
    • +
  • +

    +1 = External GPIO +

    +
    • +
+
Device Selection GPIO Number

This field describes the GPIO number that controls device selection. If +the value is set to 0x1F, then this functionality is not used. The

+
Device Selection GPIO State

This flag tells the logical GPIO state in order to select or enable the +associated DCB index for this entry. The physical logic here is found +in the GPIO Assignment Table. Defined values +are:

+
    +
  • +

    +0 = Logical OFF state. +

    +
    • +
  • +

    +1 = Logical ON state. +

    +
    • +
+
Device Detection Switching GPIO Type

This flag determines the location of the control for the GPIO that +controls Device Detection. Defined values are:

+
    +
  • +

    +0 = Internal GPIO or GPU controlled GPIO +

    +
    • +
  • +

    +1 = External GPIO +

    +
    • +
+
Device Detection Switching GPIO Number

This field describes the GPIO number that controls Device Detection. If +the value is set to 0x1F, then this functionality is not used. In order +to run detection, this GPIO must be set to the Device Detection +Switching GPIO State before reading the state.

+
Device Detection Switching GPIO State

This flag tells the logical GPIO state in order to detect the associated +DCB index for this entry. The physical logic here is found in the +GPIO Assignment Table. Defined values are:

+
    +
  • +

    +0 = Logical OFF state. +

    +
    • +
  • +

    +1 = Logical ON state. +

    +
    • +
+
Device Detection Load GPIO Type

This flag determines the location of the input for the GPIO that returns +the Device Detection Load. Defined Values are:

+
    +
  • +

    +0 = Internal GPIO or GPU controlled GPIO +

    +
    • +
  • +

    +1 = External GPIO +

    +
    • +
+
Device Detection Load GPIO Number

This field describes the GPIO number that returns Device Detection Load. +If the value is set to 0x1F, then this functionality is not used. When +running detection, the Devices Detecion Switching GPIO must be set to +the Device Detection Switching GPIO State. Then read this GPIO to get +the Load State.

+
Device Detection Load GPIO State

This flag tells the physical GPIO state that indicates a connected +state. Defined values are:

+
    +
  • +

    +0 = If the GPIO reads back physically as 0, then the device is connected. +

    +
    • +
  • +

    +1 = If the GPIO reads back physically as 1, then the device is connected. +

    +
    • +
+
DDC Port Switching GPIO Type

This flag determines the location of the control for the GPIO that +controls the DDC port. Defined Values are:

+
    +
  • +

    +0 = Internal GPIO or GPU controlled GPIO +

    +
    • +
  • +

    +1 = External GPIO +

    +
    • +
+
DDC Port Switching GPIO Number

This field describes the GPIO number that controls the routing of the +DDC Port. If the value is set to 0x1F, then this functionality is not +used. In order to use the DDC Port, this GPIO must be set to the DDC +Port Switching GPIO State.

+
DDC Port Switching GPIO State

This flag tells the logical GPIO state in order to use the DDC Port for +this DCB index entry. The physical logic here is found in the +GPIO Assignment Table. Defined values are:

+
    +
  • +

    +0 = Logical OFF state. +

    +
    • +
  • +

    +1 = Logical ON state. +

    +
    • +
+
+
+
+
+
+ + + diff --git a/DCB/Stall_lock_dcb.jpg b/DCB/Stall_lock_dcb.jpg new file mode 100644 index 0000000..185fc9b Binary files /dev/null and b/DCB/Stall_lock_dcb.jpg differ diff --git a/DCB/ThermalPower.gif b/DCB/ThermalPower.gif new file mode 100644 index 0000000..510beb7 Binary files /dev/null and b/DCB/ThermalPower.gif differ diff --git a/DCB/ThermalPowerDisable.gif b/DCB/ThermalPowerDisable.gif new file mode 100644 index 0000000..ae658d2 Binary files /dev/null and b/DCB/ThermalPowerDisable.gif differ diff --git a/Devinit/devinit.css b/Devinit/devinit.css new file mode 100644 index 0000000..297b803 --- /dev/null +++ b/Devinit/devinit.css @@ -0,0 +1,222 @@ +/* Cascading Style Sheet for devinit.xml/devinit.xsl */ + +.title {font-family:Ariel;font-size:16pt;font-weight:bold;margin-bottom:24pt;} + +.topic-header {font-size:12pt;font-weight:bold;} +.topic-body {margin-left:5%;} +.topic-paragraph + { + margin-bottom:12pt; + } +.topic-code {font-family:Courier;} + + +.index-header {font-size:12pt;font-weight:bold;} +.index-body {margin-left:5%;} +.index { + width:50em; + margin-bottom:36pt; + background-color:#FFFFCC; + font-family:Verdana; + font-size:10pt; + } +.numeric-index { + width:30em; + margin-bottom:36pt; + background-color:#FFFFCC; + font-family:Verdana; + font-size:10pt; + } +.index-table-header + { + font-weight:bold; + color:#FFFFFF; + background-color:#800000; + border-color:#000000; + border-width:1pt; + border-style:solid; + border-top-style:none; + } +.index-row {border-color:#000000;border-width:1pt;border-style:solid;border-top-style:none;} +.link {width:40%;vertical-align:top} +.numeric {width:10%;vertical-align:top} +.element {width:60%;vertical-align:top} + +.opcode-page { + page-break-before: always + } + +.opcode { + margin-top:36pt; + padding-top:12pt; + border-top-color:#000000; + border-top-width:4pt; + border-top-style:solid; + font-family:Verdana; + font-size:10pt; + page-break-before: always + } + +.opcode-deprecated + { + position:relative; + margin-top:36pt; + padding-top:12pt; + border-top-color:#000000; + border-top-width:4pt; + border-top-style:solid; + font-family:Verdana; + font-size:10pt; + background-color:#E8E8E8; + } + +.opcode-new + { + position:relative; + margin-top:36pt; + padding-top:12pt; + border-top-color:#000000; + border-top-width:4pt; + border-top-style:solid; + font-family:Verdana; + font-size:10pt; + background-color:#FFDDDD; + } + +.opcode-header { + border-bottom-color:#808080; + border-bottom-width:1pt; + border-bottom-style:solid; + font-size:14pt; + font-weight:bold; + } + +.summary {margin-bottom:12pt;} + +.layout-header {font-size:12pt;font-weight:bold;} +.layout-body {margin-left:5%;} +.layout-table {width:50em;margin-bottom:12pt;background-color:#FFFFE0;position:relative;} +.parameter {} +.parameter-size {width:12%;overflow:hidden;vertical-align:top;} +.parameter-name {width:35%;overflow:hidden;vertical-align:top;} +.parameter-desc {width:53%;overflow:hidden;vertical-align:top;} + + +.details-header {font-size:12pt;font-weight:bold;} +.details-body {margin-left:5%;} + +.attrib-table { + border-top-color:#FFFFFF; + border-top-width:1pt; + border-top-style:solid; + font-size:8pt; + width:50em; + margin-bottom:12pt; + } +.attrib-row + { + border-left-color:#FFFFFF; + border-left-width:1pt; + border-left-style:solid; + border-bottom-color:#FFFFFF; + border-bottom-width:1pt; + border-bottom-style:solid; + background-color:#E8E8E8; + } +.attrib-name { + width:30%; + overflow:hidden; + padding:2pt; + font-weight:bold; + border-right-color:#FFFFFF; + border-right-width:1pt; + border-right-style:solid; + background-color:#DDDDDD; + vertical-align:top; + } +.attrib-value { + width:70%; + overflow:hidden; + padding:2pt; + border-right-color:#FFFFFF; + border-right-width:1pt; + border-right-style:solid; + vertical-align:top; + } + +.paragraph {margin-bottom:12pt;} +.list {margin-left:5%;margin-bottom:12pt;} +.item {} +.note {margin-bottom:12pt;font-style:italic;color:#FF0000;} +.restriction {margin-bottom:12pt;font-style:italic;color:#FF0000;} +.todo {margin-bottom:12pt;font-style:italic;color:#FF0000;text-decoration:blink;} + + +.example-header {font-size:12pt;font-weight:bold;} +.example-body {margin-left:5%;} +.example {margin-bottom:12pt;} +.example-description + { + } +.example-line {font-family:Courier;} + + +.history-header {font-size:12pt;font-weight:bold;} +.history-body {margin-left:5%;} +.history-table { + border-top-color:#FFFFFF; + border-top-width:1pt; + border-top-style:solid; + font-size:8pt; + width:15em; + margin-bottom:12pt; + } +.history-row + { + border-left-color:#FFFFFF; + border-left-width:1pt; + border-left-style:solid; + border-bottom-color:#FFFFFF; + border-bottom-width:1pt; + border-bottom-style:solid; + background-color:#E8FFE8; + } +.history-core { + width:40%; + overflow:hidden; + padding:2pt; + font-weight:bold; + border-right-color:#FFFFFF; + border-right-width:1pt; + border-right-style:solid; + background-color:#DDFFDD; + vertical-align:top; + } +.history-value { + width:60%; + overflow:hidden; + padding:2pt; + border-right-color:#FFFFFF; + border-right-width:1pt; + border-right-style:solid; + vertical-align:top; + } + + +.audits-header {font-size:12pt;font-weight:bold;} +.audits-body {margin-left:5%;} +.audit {margin-bottom:12pt;font-style:italic;} + +.watermark { + position:absolute; + text-align:center; + width:100%; + height:100%; + font-size:24pt; + color:#CCCCCC; + font-style:italic; + z-index:-1; + } + + +.error {text-decoration:overline;color:#FF0000;} diff --git a/Devinit/devinit.xml b/Devinit/devinit.xml new file mode 100644 index 0000000..b3aa517 --- /dev/null +++ b/Devinit/devinit.xml @@ -0,0 +1,6876 @@ + + + + + + + + + + + + + The devinit system allows a GPU programming sequence to be shared by multiple entities that would otherwise not be able to execute common code. + One of the primary uses is to initialize the GPU at boot time. + The same sequence can be used by the VGA BIOS, the Resource Manager for secondary adapter cases, and the FCode firmware for the Apple Mac platforms. + The devinit system also saves space because it can express many types of sequences in less space than normal x86 assembler code. + Also, the format of the opcodes used by the devinit system are easy to parse which facilitates being able to customize sequences in an already compiled BIOS image using the BIOSMOD tool. + + + The devinit system consists of scripts that contain opcodes that specify what operations a devinit engine need to perform. + Many opcodes have parameters that specify things such as register addresses to use and data values to write to registers. + A devinit engine parses these opcodes and performs the indicated operations. + Each platform that uses devinit scripts needs to have its own engine (VBIOS, Resource Manager, FCODE). + + + + + + Starting with core6 the devinit engine has variations of a limited subset of opcodes that get their data values from a passed in data buffer. + In the VBIOS implementation this buffer is passed in ES:DI. + Because ES is used, the data buffer can be located in either the code segment (CS) for fixed data or the stack segment (SS) for dynamic data. + There will be two types of variations: one that just grabs the data in sequence and one that has offsets from the beginning of the buffer specified. + For example there is now: + + + INIT_NV_REG (the original "inline data" version) + dd <address> + dd <mask> + dd <data> + + INIT_NV_REG_UNCOUPLED (data is taken from ES:[DI + <data offset>], DI is not changed) + dd <address> + dd <mask> + db <data offset> (notice "db", not "dd") + + INIT_NV_REG_STREAM (data is taken from next bits at ES:DI, current bit position advanced) + dd <address> + dd <mask> + (notice no data value or offset at all) + + + + So for example scaler data could be in a buffer of dwords, and a sequence of INIT_ZM_REG_STREAM opcodes in a script could control where the values are written. + + + + With the *_UNCOUPLED opcodes the offset into the passed in data buffer is specified as a byte, which represents the byte offset into the data buffer. + This results in a maximum offset of 255 bytes for a maximum buffer size of 256 bytes. + The current position is not adjusted, all offsets are relative to the initial data buffer starting location (unless _STREAM opcodes have also been used). + + + + With the *_STREAM opcodes the devinit engine keeps track of the current bit position within the current byte. + For opcodes with a mask each position of the mask that is a zero will result in a bit being extracted from the stream to fill that position in the data value. + When all the bits of the current byte are used up, the devinit engine will advance to the next byte (ES:DI is incremented in the VBIOS implementation). + All bits in the data value that correspond to bit positions in the mask that are one will be set to zero. + This means that the bit stream is a "packed" bit stream. + Bits are taken starting from the least significant bit of the stream byte, and shifted into the most significant bit of the constructed value and shifted to the right. + So a mask of 0x00 (inverse is 0xFF) and a stream byte of 0x12 (assuming your starting at bit 0) would result in a data value of 0x12. + A mask of 0x0F (inverse is 0xF0) and a stream byte of 0x12 (assuming your starting at bit 0) would result in a data value of 0x20. + + + + Below is an example of use of an *_STREAM opcode: + + + + Data Buffer Contents: + + + 0x12 0xF4 + + + + Devinit Script: + + + ; This will write a 0x12 into CRTC[A0] and advance the stream 8 bits + db INIT_ZM_CRTC_STREAM + db 0xA0 + + ; This opcode usage will result in an OR mask of 0x40 + ; (the devinit engine extracts stream from the least significant bit), + ; and will advance the stream by 4 bits + ; (the inverse of the mask ^0x0F = 0xF0 which tells where the bits + ; will be and how many there are) + db INIT_CRTC_STREAM + db 0xA1 + db 0x0F + + ; For this operation the OR mask will be 0xC3 + ; (comes from the "F" in 0xF4), + ; the stream is advanced by 4 bits + db INIT_CRTC_STREAM + db 0xA2 + db 0x3C + + + + It is possible to mix *_STREAM and *_UNCOUPLED opcodes. + The *_UNCOUPLED opcodes will simply offset for the adjusted data buffer position without making any further adjustments. + Note that the current bit position within the current byte is ignored and not changed by the *_UNCOUPLED opcodes. + While mixing the opcodes can be useful in certain situations, great care must be taken to do it properly. + + + + + + The data buffer to use when running scripts for use with *_UNCOUPLED, *_STREAM, and *_READ type opcodes (only applicable for core6 and beyond) depends on the context. + In other words, what buffer the devinit engine needs to use depends on what type of script is being run. + + + When no specific data buffer is specified for a type of script, the Resource Manager script engine shall always be called with a default read/write buffer + that is 256 bytes in length and initialized to be filled with zeros. + This allows scripts to read registers, perform logic operations on the value read, and then write the value back to the same or other registers. + + + Currently, the only script specific data buffer defined is the data buffer for the boot devinit scripts. + Like the default data buffer, it shall be a 256 byte read/write buffer. + Before passing the buffer to the engine the buffer shall first be cleared to all zeros and then the first portion shall be filled with data copied from the <TBD> table which is pointed to by the BIT in the bios image. + This block of fixed values will usually be pointed to by the BIOS Preservation Table so that they remain fixed between firmware upgrades (and thus simulate fuses). + + + + + + Starting with core6 the devinit engine now has the ability to have a common script run for different display pipes (heads), different + devices (Output Resources) or/and different sublinks. + When the devinit engine is invoked, the device and/or display pipe to use is passed as a parameter to the engine. + The device is often taken from the DCB entry of the device that needs to be accessed. + + + + To specify that a privileged register address needs to be adjusted depending on the passed in display pipe, the address to access is combined with DEVINIT_USE_DPIPE(0x80000000) using a logic OR. + When the devinit engine sees an address with this bit set it masks out the bit and adjusts the base address to be correct for the display pipe that was specified when the engine was invoked. + Under EVO designs, this means the passed in display pipe is multiplied by 0x800 and added to the base address. + + + + This example illustrates writing the pixel clock on the display pipe that was passed to the devinit engine. + + + ; Write clock + db INIT_NV_REG + dd NV_PDISP_DSI_FLIPLOCK(0) OR DEVINIT_USE_DPIPE + db DEVINIT_OFFSET_ECX + + + + Note that in some scripts the concept of specifying a display pipe has no meaning. + Such scripts shall not have any addresses that use DEVINIT_USE_DPIPE. + The INITCHK utility will flag scripts that use DEVINIT_USE_DEVICE but have no display pipe context with an error (not yet implemented). + + + + To specify that a opcode needs to be adjusted depending on the passed in device, the privileged register address to access is combined with the DEVINIT_USE_DEVICE(0x40000000) using a logic OR. + When the devinit engine sees an address with this bit set it masks out the bit and adjusts the base address to be correct for the device that was specified when the engine was invoked. + Under EVO designs, this means the passed in device is multiplied by 0x800 and added to the base address. + + + + This example illustrates disconnecting the source from a DAC output resource. + The DAC index to use is passed to the devinit engine. + + + ; Set up the source + db  INIT_ZM_REG + dd  NV_PDISP_VGA_DAC_CONTROL OR DEVINIT_USE_DEVICE + dd  NV_PDISP_VGA_DAC_CONTROL_OWNER_NONE OR \\ +     NV_PDISP_VGA_DAC_CONTROL_CRCMODE_INIT OR \\ +     NV_PDISP_VGA_DAC_CONTROL_PROTOCOL_RGB_CRT + + + + Note that in some scripts the concept of specifying a device has no meaning. + Such scripts shall not have any addresses that use DEVINIT_USE_DEVICE. + The INITCHK utility will flag scripts that use DEVINIT_USE_DEVICE but have no device context with an error (not yet implemented). + + + + To specify that a opcode needs to be adjusted depending on the passed in sublink, the privileged register address to access is combined with the DEVINIT_USE_SUBLINK(0x20000000) using a logic OR, + as it is now, when DEVINIT_USE_SUBLINK is set, we would also need DEVINIT_USE_DEVICE to be set. + When the devinit engine sees an address with this bit set it masks out the bit and adjusts the base address to be correct for the sublink that was specified when the engine was invoked. + Under EVO designs, this means the passed in device is multiplied by 0x80 and added to the base address. + + + + This example illustrates enabling power to a particular SOR and Sublink. + + + ; Enable link power + db  INIT_NV_REG + dd  NV_PDISP_SOR_DP_LINKCTL0(0) OR DEVINIT_USE_DEVICE OR DEVINIT_USE_SUBLINK + dd  NOT NV_PDISP_SOR_DP_LINKCTL0_ENABLE_FIELD_MASK + dd  NOT NV_PDISP_SOR_DP_LINKCTL0_ENABLE_YES + + + + Note that in some scripts the concept of specifying a sublink has no meaning. + Such scripts shall not have any addresses that use DEVINIT_USE_SUBLINK. + The INITCHK utility will flag scripts that use DEVINIT_USE_SUBLINK but have no device context with an error (not yet implemented). + + + + The DEVINIT_USE_DPIPE, DEVINIT_USE_DEVICE and DEVINIT_USE_SUBLINK bits are in the upper nibble of the 32-bit address, so they do not conflict with the address space of privileged registers (which are constrained to 24 bits). + + + + + + + Similar to handling Device Indexes and Display Pipe Indexes for normal opcodes, the method opcodes (INIT_DISPLAY_METHOD*) have flags that are bitwise OR'ed with the method offset. + + + + To specify that a method offset needs to be adjusted depending on the passed in display pipe, the method offset is combined with DEVINIT_METHOD_USE_DPIPE using a logic OR. + When the devinit engine sees a method offset with this bit set it masks out the bit and adjusts the base method offset to be correct for the display pipe that was specified when the engine was invoked. + Under EVO designs, this means the passed in display pipe is multiplied by the proper amount and added to the base method offset. + + + + To specify that a opcode needs to be adjusted depending on the passed in DAC, SOR, or PIOR, the method offset is combined with DEVINIT_METHOD_USE_DAC, DEVINIT_METHOD_USE_SOR, or DEVINIT_METHOD_USE_PIOR using a logic OR. + When the devinit engine sees a method offset with one of these bits it masks out the bit and adjusts the base method offset to be correct for the device that was specified when the engine was invoked. + Under EVO designs, this means the passed in device is multiplied by the proper amount and added to the base method offset. + + + + The DEVINIT_METHOD_USE_DPIPE, DEVINIT_METHOD_USE_DAC, DEVINIT_METHOD_USE_SOR, and DEVINIT_METHOD_USE_PIOR bits are in the upper nibble of the 32-bit method offset, so they do not conflict with the address space of the method offsets themselves. + + + + + + + There are a variety of opcodes that are no longer in use that are marked as deprecated. + Deprecated opcodes are subject to be removed or redefined without further notice. + + + + + + + All opcodes that deal with an I/O port may need to be adjusted according to the operating environment at the time of execution unless otherwise specified. + For example, if the I/O port is specified as 0x3D4 and the controller is configured for monochrome operation, the port will be automatically adjusted to 0x3B4. + This is also true of any of the CRTC opcodes, where the current I/O port address of the CRTC at the time the opcode is process is used. + Implementations may need or wish to cache writes to the Miscellaneous Output Register (which controls the CRTC I/O port location) and simulate this operation. + + + Unless otherwise noted, scripts and implementations of devinit engines shall not rely on scripts to preserve I/O register indexes. + However, it is valid for implementations to preserve the indexes if it simplifies handling of the opcodes. + Thus scripts can not rely on I/O indexes either being preserved or not preserved. + Implementations are allowed to save and restore I/O register indexes even when no other operations are performed due to the condition flag state being set to skip operations. + + + Devinit engines in platforms other than the VGA BIOS, such as the Resource Manager, + usually need to convert I/O port operations into their equivalent privileged register operation. + Please see "NVXX Display Class Priv Register Manual" (dev_disp.ref) for the proper mappings to use. + + + + + + Any devinit engines that use I/O ports directly must take into account the Attribute Controller flip-flop + when Attribute Controller registers are specified by an instruction. + This is required so that the index and data registers are accessed correctly. + Devinit engines that convert I/O port accesses to privileged registers may need to simulate the Attribute Controller + flip-flop depending on how the Attribute Controller registers are mapped to privileged registers on a given chip. + While not required, it is acceptable to reset the Attribute Controller flip-flop even when other accesses are being skipped due to the state of the condition flag. + It is also acceptable to reset the Attribute Controller flip-flop for all registers, not just Attribute Controller registers. + + + + + + For the I2C opcodes devinit engines may acquire the I2C port and prepare it for usage and shut it down and release it when it has finished processing the opcode, + even when no I2C transactions are performed such as when the state of the condition flag is set to skip operations. + + + + + + + The PLL ID's are used to identify a PLL with a single byte instead of having to use the full 32-bit privileged registers address. + These are standardized and used by the Resource Manager, they can not change (other than adding new ones, old ones are not reused). + + + PLL ID's above 080h are assume to be in groups of 16. + The lower nibble is stripped when the VGA BIOS searches the PLL lookup table for previous calculated coefficients, + so all PLL's in a group need to have the same limit parameters for their PLL coefficient calculation. + + + The PLL ID's defines are listed with the PLL Info Table specification in the "Core 6 Design Specification". + + + + + + + For chips with two VGA heads (NV11-NV49), unless otherwise specified the opcodes all use the current CR44 head setting for reads and writes. + If the CR44 head is not set earlier in the current script, the setting at the time the script is run is used. + Note that chips G80 and beyond only have one VGA head (but have more than one display pipe). + + + + + + With very few exceptions, Devinit engines on different platforms must not attempt to "interpret" what a devinit script is doing in order to slightly modify the operations performed, unless absolutely necessary (starting with Core 6 VGA BIOS and FCODE images). + Devinit engines must generally execute the operations specified by the devinit script verbatim. + Doing this is very important in order to allow maintaining compatibility with future chips using existing drivers. + + + Exceptions to this rule include conversion of I/O port opcodes to privileged registers in engines that cannot use I/O ports directly, + tracking the location of the CRTC registers (0x3B4/0x3D4), + and properly dealing with or simulating the attribute controller index/data flip-flop. + Any other exceptions to this rule must be listed in this specification. + + + + + + Sub scripts, which are invoked with INIT_SUB/INIT_SUB_DIRECT, are typically implemented by starting a new Devinit Engine context. This new context would reset the Condition Flag. However, this is not the case in all engines: + + + VBIOS CPU engine: INIT_SUB/INIT_SUB_DIRECT implicitly saves and restores the condition flag. + + + + VBIOS PMU engine: INIT_SUB/INIT_SUB_DIRECT implicitly saves and restores the condition flag. + + + + UEFI CPU engine: INIT_SUB/INIT_SUB_DIRECT implicitly saves and restores the condition flag. + + + + RM CPU engine: INIT_SUB/INIT_SUB_DIRECT re-uses the same context, so the condition flag is not saved/restored. + + + + + + + + Delay a period of time in microsecond units. + +
+ + This opcode causes the BIOS to delay processing for the number of microseconds specified in the delay value field. + + + If the condition flag is set to the skip execution state, the time delay shall not occur. + + + Prior to core6, a delay of 0 invokes debugger (int1). + This can be used as a devinit script "breakpoint". + For core6 and beyond, use INIT_BREAK. + +
+ + + + + + + + + + + + + All implementations prior to core6 ignore the condition flag. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + Delay a period of time in milliseconds. + +
+ + This opcode causes the BIOS to delay processing for the number of milliseconds specified in the delay value field. + + + If the condition flag is set to the skip execution state, the time delay shall not occur. + +
+ + + + + + + + + + + + + All implementations prior to core6 ignore the condition flag. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + Modify a privileged register. + +
+ + This opcode first reads the specified privileged register. + It then performs a logical AND on the read value using the AND mask, then a logical OR on the value using the OR mask. + The resulting value is then written to the privileged register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final write. + + + Engine is skipping all register accesses, not just the final write. + + + + + + + + + + + Modify a privileged register using a value from a passed in data buffer. + +
+ + This opcode first reads the specified privileged register. + It then performs a logical AND on the read value using the AND mask, then a logical OR on the value using the 32-bit OR mask retrieved from the passed in data buffer. + The resulting value is then written to the privileged register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + + Modify a privileged register using a value from a passed in data stream. + +
+ + This opcode first reads the specified privileged register. + It then performs a logical AND on the read value using the AND mask, then a logical OR on the value using the 32-bit OR mask retrieved from the passed in data stream. + The resulting value is then written to the privileged register. + + + The number of bits the devinit engine will extract from the stream will be equal to the number of bits that are clear in the mask. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Read a privileged register. + +
+ + This opcode reads the specified privileged register and stores the value read at an offset in the passed in data buffer. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Write a new value to a privileged register (zero mask). + +
+ + This opcode writes the data value to the specified privileged register without prior consideration to the previous value of the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Performs special handling for certain GPIO, PLL, power, and clock registers (needs to be removed for core6). + + + Code in compliance. + + + + + + + + + + Write a new value to a privileged register (zero mask) using a value from a passed in data buffer. + +
+ + This opcode writes the data value to the specified privileged register without prior consideration to the previous value of the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Write a new value to a privileged register (zero mask) using a value from a passed in data stream. + +
+ + This opcode writes the data value to the specified privileged register without prior consideration to the previous value of the register. + + + The devinit engine will always extract 32 bits from the stream for this opcode. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + Sets specified bits in a privileged register leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified register, performs an "OR" operation with the specified data value, and writes the result back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Sets bits specified by a value from a passed in data buffer in a privileged register leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified register, performs an "OR" operation with a value from the passed in data buffer, and writes the result back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Sets bits specified by a value from a passed in data stream in a privileged register leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified register, performs an "OR" operation with a value from the passed in data stream, and writes the result back to the register. + + + The devinit engine will always extract 32 bits from the stream for this opcode. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + Resets specified bits in a privileged register leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified register, performs an "AND" operation with the complement of the specified data value, and writes the result back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Resets bits specified by a value from a passed in data buffer in a privileged register leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified register, performs an "AND" operation with the complement of a value from the passed in data buffer, and writes the result back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Resets bits specified by a value from a passed in data stream in a privileged register leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified register, performs an "AND" operation with the complement of a value from the passed in data stream, and writes the result back to the register. + + + The devinit engine will always extract 32 bits from the stream for this opcode. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + Write a new 16-bit value to a privileged register (zero mask). + +
+ + This opcode writes the 16-bit data value to the specified privileged register without prior consideration to the previous value of the register. + +
+ + + + + + + + + + + + + Not implemented (deprecated). + + + Performs special handling for certain GPIO, PLL, power, and clock registers (needs to be removed for core6). + + + + + + + + + + + Write a sequential block of privileged register with set of values. + +
+ + This opcode writes a sequential set of data values to a sequential set of privileged registers. + The privileged registers are assumed to be offset 4 bytes from each other. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + + + + Write the same privileged register repeatedly with a sequence of data values. + +
+ + This opcode writes a sequential set of data values to a single privileged register. + This is usually used for programming blocks of indexed data registers where auto-incrementing of the index occurs. + The initial index is usually written with a previous instruction such as INIT_ZM_REG. + +
+ + + + + + + + + + + + + + + + Not implemented. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + Program the specified PLL with a 16-bit frequency value. + +
+ + This opcode will cause the indicated PLL to be programmed with a value that generates the specified clock frequency. + The coefficients programmed into the PLL are calculated by the BIOS from the frequency, based on the chipset's PLL programming algorithm. + + + The 16-bit frequency value is stored in kilohertz units (i.e.: 125Mhz = 12500). + +
+ + + + + + + + + + + + + Not implemented. + + + Code in compliance. + + + Ignores condition code. + + + + + + + + + + + Program the specified PLL with a 32-bit frequency value. + +
+ + This opcode will cause the indicated PLL to be programmed with a value that generates the specified clock frequency. + The coefficients programmed into the PLL are calculated by the BIOS from the frequency, based on the chipset's PLL programming algorithm. + + + The 32-bit frequency value is stored in kilohertz (i.e.: 125Mhz = 125000). + + + This opcode was actually added in core4r2, but first released in core5. + + + Starting with core6 the opcode only updates the coefficients and does not configure or enable the PLL. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Ignores condition code. + + + + + + + + + + + Program the PLL specified by a PLL ID with a 32-bit frequency value. + +
+ + This opcode will cause the indicated PLL to be programmed with a value that generates the specified clock frequency. + The coefficients programmed into the PLL are calculated by the BIOS from the frequency, based on the chipset's PLL programming algorithm. + + + The PLL is specified by a PLLID. The ID's are fixed defined values. + + + The 32-bit frequency value is stored in kilohertz (i.e.: 125Mhz = 125000). + + + This opcode only updates the coefficients and does not configure or enable the PLL. + +
+ + + + + + + + + + + + + Not implemented. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + Modify an I/O port. + +
+ + This opcode first reads a data value from the I/O port. + It then performs a logical AND on the read value using the AND mask, then a logical OR on the value using the OR mask. + The resulting value is then written back to the I/O port. + +
+ + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final write. + + + Engine is skipping all register accesses, not just the final write. + + + + + + + + + + + Modify an I/O port using a value from a data stream. + +
+ + This opcode first reads a data value from the I/O port. + It then performs a logical AND on the read value using the AND mask, then a logical OR on the value using a value from a passed in data stream. + The resulting value is then written back to the I/O port. + + + The number of bits the devinit engine will extract from the stream will be equal to the number of bits that are clear in the mask. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Write a new value to an I/O port (zero mask). + +
+ + This opcode writes the specified value to the specified I/O port. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + Modify an indexed I/O port. + +
+ + This opcode first writes the register index to the index register of the indexed I/O port (i.e.: 0x3D4) to select the indexed register to be written. + It then reads a value from the data register of the indexed I/O port (i.e.: 0x3D5), performs a logical AND on the read value using the AND mask, then a logical OR on the value using the OR mask. + The resulting value is then written back to the data register of the indexed I/O port. + +
+ + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final write. No special handling is being performed for Attribute Controller registers. + + + Engine is skipping all register accesses, not just the final write. No special handling is being performed for Attribute Controller registers. + + + + + + + + + + + + Modify an indexed I/O port using a value from a passed in data buffer. + +
+ + This opcode first writes the register index to the index register of the indexed I/O port (i.e.: 0x3D4) to select the indexed register to be written. + It then reads a value from the data register of the indexed I/O port (i.e.: 0x3D5), performs a logical AND on the read value using the AND mask, then a logical OR on the value using a value from a passed in data buffer. + The resulting value is then written back to the data register of the indexed I/O port. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + + + Modify an indexed I/O port using a value from a passed in data stream. + +
+ + This opcode first writes the register index to the index register of the indexed I/O port (i.e.: 0x3D4) to select the indexed register to be written. + It then reads a value from the data register of the indexed I/O port (i.e.: 0x3D5), performs a logical AND on the read value using the AND mask, then a logical OR on the value using a value from a passed in data stream. + The resulting value is then written back to the data register of the indexed I/O port. + + + The number of bits the devinit engine will extract from the stream will be equal to the number of bits that are clear in the mask. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + + Modify a CRTC register. + +
+ + This opcode first writes the register index to the CRTC index register to select the indexed register to be written. + It then reads a value from the CRTC data register, performs a logical AND on the read value using the AND mask, then a logical OR on the value using the OR mask. + The resulting value is then written back to the CRTC data register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final write. + + + Code in compliance. + + + + + + + + + + + Modify a CRTC register using a value from a passed in data buffer. + +
+ + This opcode first writes the register index to the CRTC index register to select the indexed register to be written. + It then reads a value from the CRTC data register, performs a logical AND on the read value using the AND mask, then a logical OR on the value using a value from a passed in data buffer. + The resulting value is then written back to the CRTC data register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + + Modify a CRTC register using a value from a passed in data stream. + +
+ + This opcode first writes the register index to the CRTC index register to select the indexed register to be written. + It then reads a value from the CRTC data register, performs a logical AND on the read value using the AND mask, then a logical OR on the value using a value from a passed in data stream. + The resulting value is then written back to the CRTC data register. + + + The number of bits the devinit engine will extract from the stream will be equal to the number of bits that are clear in the mask. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Set bits in a CRTC register leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified CRTC register, performs an "OR" operation with the specified data value, and writes the result back to the CRTC register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Set bits in a CRTC register using a value from a passed in data buffer leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified CRTC register, performs an "OR" operation using a value from a passed in data buffer, and writes the result back to the CRTC register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Set bits in a CRTC register using a value from a passed in data stream leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified CRTC register, performs an "OR" operation using a value from a passed in data stream, and writes the result back to the CRTC register. + + + The devinit engine will always extract 8 bits from the stream for this opcode. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + Reset bits in a CRTC register leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified CRTC register, performs an "AND" operation with the complement of the specified data value, and writes the result back to the CRTC register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Reset bits in a CRTC register using a value from a passed in data buffer leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified CRTC register, performs an "AND" operation with the complement of a value from a passed in data buffer, and writes the result back to the CRTC register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Reset bits in a CRTC register using a value from a passed in data stream leaving other bits unchanged. + +
+ + This opcode reads the current value of the specified CRTC register, performs an "AND" operation with the complement of a value from a passed in data stream, and writes the result back to the CRTC register. + + + The devinit engine will always extract 8 bits from the stream for this opcode. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + Read a CRTC register. + +
+ + This opcode reads the specified CRTC register and stores the value read at an offset in the passed in data buffer. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Read a span of CRTC registers and store the values in a byte stream. + +
+ + This opcode reads sequential span of CRTC registers and stores the values read into the passed in data stream. + + + The devinit engine will always insert 8 bits for each read CRTC register into the stream when processing this opcode. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Write a span of CRTC registers with data from a byte stream. + +
+ + This opcode writes a sequential span of CRTC registers using values from a passed in data stream. + + + The devinit engine will always extract 8 bits for each CRTC register from the stream for this opcode. + The bits must be extracted even when the condition code state prevents the final values from being written back to the registers. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Poll an I/O port until a masked value compares correctly. + +
+ + This opcode will poll an I/O port continually until a masked value results in a positive compare. + This opcode uses the same table of conditions as the INIT_IO_CONDITION opcode. + + + The timeout value sets the maximum amount of time this opcode will consume, and is not meant to control the sample rate for the terminating condition. + This means that the mask/compare operation will usually occur at a higher rate than the delay value. + + + If the poll is not satisfied and a timeout condition occurs the condition flag will be set to the skip execution state. + Otherwise the condition flag is left in its current state from before the execution of the opcode. + For this reason, it will often be necessary to follow this opcode with an INIT_RESUME if there is no need to know if the timeout occurred. + + + An index of 0xFF in the I/O condition table signals that a direct I/O port shall be used instead of an indexed I/O port. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + BYTE INIT_POLL + BYTE 1 ; I/O Condition code + BYTE 02h ; 200 milliseconds max before continuing + + + + + + + + + + Poll a privileged register until a masked value compares correctly. + +
+ + This opcode will poll a privileged register continually until a masked value results in a positive compare. + This opcode uses the same table of conditions as the INIT_CONDITION opcode. + + + The timeout value sets the maximum amount of time this opcode will consume, and is not meant to control the sample rate for the terminating condition. + This means that the mask/compare operation will usually occur at a higher rate than the delay value. + + + If the poll is not satisfied and a timeout condition occurs the condition flag will be set to the skip execution state. + Otherwise the condition flag is left in its current state from before the execution of the opcode. + For this reason, it will often be necessary to follow this opcode with an INIT_RESUME if there is no need to know if the timeout occurred. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + This example will poll using condition code 1, and will not take more than 200 milliseconds before terminating. + + BYTE INIT_POLL_NV + BYTE 03h ;Condition code to poll for + BYTE 02h ;200 milliseconds max before continuing + + + + + + + + + + + Write a new value to an indexed I/O port (zero mask). + +
+ + This opcode first writes the register index to the index register of the indexed I/O port (i.e.: 0x3D4) to select the indexed register to be written. + It then writes the data value to the data register of the indexed I/O port. + +
+ + + + + + + + + + + + + Code in compliance. + + + No special handling is being performed for Attribute Controller registers. + + + No special handling is being performed for Attribute Controller registers. + + + + + + + + + + + + Write a new value to a CRTC register (zero mask). + +
+ + This opcode first writes the register index to the CRTC index register to select the indexed register to be written. + It then writes the data value to the CRTC data register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + Write a new value to a CRTC register from a passed in data buffer (zero mask). + +
+ + This opcode first writes the register index to the CRTC index register to select the indexed register to be written. + It then writes the data value from a passed in data buffer to the CRTC data register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + + Write a new value to a CRTC register from a passed in data stream (zero mask). + +
+ + This opcode first writes the register index to the CRTC index register to select the indexed register to be written. + It then writes the data value from a passed in data stream to the CRTC data register. + + + The devinit engine will always extract 8 bits from the stream for this opcode. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Write a set values to a set of CRTC registers with no mask (zero mask). + +
+ + This opcode writes a specified number of CRTC registers, with the index for each data value being specified. + The register indexes can be specified randomly, they do not have to follow any particular sequence or order. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + + + + Perform a copy from a privileged register to an indexed I/O port. + +
+ + This opcode is used to copy data from a portion of a privileged register and copy it to an indexed I/O port. + First a 32-bit value is read from the register at the specified privileged register. + This value is then shifted using the 8-bit shift count. + A positive shift count indicates a right shift, and a negative shift count (two's complement) indicates a left shift. + An AND operation is then performed on this shifted value using the 8-bit source AND mask. + Next, an 8-bit value is read from the specified indexed I/O port at the specified index. + An AND operation is performed on this value with the 8-bit AND mask. + Finally, an OR operation is performed using the this value and the value resulting from the AND with the 8-bit source AND mask. + The result is then written back to the indexed I/O port. + + + S008shift can be negative (two's complement) for a left shift + + + This opcode may eventually be deprecated, but currently full support exists in core6+ as of 2008-01-17. + +
+ + Once a data buffer is available for boot devinit scripts, this opcode will be replaced with the use of the read and logic opcodes. + + + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final write. + + + Engine is skipping all register accesses, not just the final write. + + + + + + + + + + + + + + + + Perform a copy from a privileged register to another privileged register. + +
+ + This opcode is used to copy data from a portion of a privileged register to a different privileged register. + First a value is read from the specified privileged register. + This value is then shifted using the shift count. + A positive shift count indicates a right shift, and a negative shift count (two's complement) indicates a left shift. + An AND operation is then performed on this shifted value using the source AND mask. + An XOR operation is then performed on the result of the AND operation and the XOR mask. + Next, a value is read from the destination register address. + An AND operation is performed on this value and the destination AND mask, with that result then used in an OR operation with the previous result of the XOR operation. + The result is then written back to the destination register. + + + Note that any of the following changes can be done to the individual bits of the destination register by using the specified values for the source AND mask and source XOR mask (for all four cases, the corresponding bit in the destination AND mask needs to be 0): + + + + Direct copy from source register (AND mask bit = 1, XOR mask bit = 0) + + + Inverted copy from source register (AND mask bit = 1, XOR mask bit = 1) + + + Force bit to 0 (AND mask bit = 0, XOR mask bit = 0) + + + Force bit to 1 (AND mask bit = 0, XOR mask bit = 1) + + + + To preserve a bit in the destination register, the corresponding bit in the destination AND mask needs to be 1, and both the source AND mask and source XOR mask need to be zero. + + + S008shift can be negative (two's complement) for a left shift. + + + This opcode may eventually be deprecated, but currently full support exists in core6+ as of 2008-01-17. + +
+ + Once a data buffer is available for boot devinit scripts, this opcode will be replaced with the use of the read and logic opcodes. + + + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final write. + + + Engine is skipping all register accesses, not just the final write. + + + + + + + + + + + + + + + Perform a direct copy from a privileged register to another privileged register with no manipulation of the data value. + +
+ + This opcode is used to copy data from a privileged register to a different privileged register. + A value is read from the privileged register specified by the u032addr field. + The value read is then written back to the destination register specified by u032destaddr. + +
+ + + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Not implemented. + + + + + + + + + + + Restrict processing according to memory configuration register + +
+ + This opcode first reads a 32-bit value from the NV_PFB_BOOT_0 register and applies the logical AND mask to the lower 8 bits. + The resulting value is compared to the comparison value. + If the values do not match the condition flag is set to the skip operations state. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Not implemented (deprecated). + + + + + + + + + + + + Restrict processing according to strap register contents. + +
+ + This opcode first reads a value from the NV_PEXTDEV_BOOT_0 register and applies the logical AND mask to the value read. + The resulting value is compared to the comparison value. + If the values do not match the condition flag is set to the skip operations state. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Not implemented (deprecated). + + + + + + + + + + Used to end a block of script that was restricted due to a condition. + +
+ + This opcode unconditionally sets the condition flag to the allow operations state so that following opcodes will be processed. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + Perform NOT on the condition flag. + +
+ + This opcode causes the current state of the condition flag to be inverted. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + Toggle bits to perform a reset operation. + +
+ + This opcode is used to toggle bits in a register to a disabled state, delay, and then back to an enabled state in order to perform a reset operation. + + + As of core5, the VGA BIOS implementation of handler for this opcode saves the value of NV_PBUS_PCI_NV_19 and clears it to 0. + It then sets the specified off state in NV_PMC_ENABLE, delays for 5 microseconds, and sets the on state in NV_PMC_ENABLE. + Next it restores NV_PBUS_PCI_NV_19 and turns off NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED in NV_PBUS_PCI_NV_20. + + + The Resource Manager implementation disables SBA and AGP. + For non-mobile NV17 boards it reads the value of NV_PMC_ENABLE, writes the off state to NV_PMC_ENABLE, delays for 1 millisecond, + writes the on state to NV_PMC_ENABLE and reads NV_PMC_ENABLE two more times. + For all other boards it writes the off state to NV_PMC_ENABLE and then writes the on state NV_PMC_ENABLE. + Finally, for all boards the Resource Manager restores the AGP command register, disables ROM shadow, and reinitializes the timer. + + + The FCode implementation differs in that it respects the condition flag. + It disables AGP, SBA, and FW, writes the off state to NV_PMC_ENABLE, delays 5 microseconds, writes the on state to NV_PMC_ENABLE, restores the AGP Command register, and disables ROM shadow. + + + For core6 and beyond, the use of this opcode has been replaced with the use of other opcodes to perform the same operation. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Engine is honoring the condition flag. + + + + + + + + + + + + Execute another script and then return to process the current script. + +
+ + The Script Table entry to be executed can be found by taking the script table index, multiplying by 2, and adding the result to the Script Table pointer. + + + Control returns to the opcode immediately following the INIT_SUB after the sub script has been executed. + + + In the VBIOS implementation of the devinit engine, the new script is executed by calling the devinit engine recursively. + + + If the condition flag is set to the skip operations state the subscript will not be executed. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + Terminate execution of the current script and run a new one. + +
+ + The Script Table entry to be executed can be found by taking the script table index, multiplying by 2, and adding the result to the Script Table pointer. + + + This opcode ends processing of the current script, and begins execution of the new script. + Control is not returned to the script containing the INIT_JUMP opcode. + + + If the condition flag is set to the skip operations state the jump will not be executed. + In that case, there need to be valid opcodes following the INIT_JUMP opcode. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + Execute a generic function in the function table. + +
+ + This opcode causes the code function specified by the index number to be executed. + Following the return of the function, execution continues at the next opcode. + + + Taking the function number, multiplying by 2, and adding the result to the Function Table Pointer base offset will find the location of the offset of the desired function. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Not implemented. + + + + + + + + + + Execute register macro array. + +
+ + This opcode causes the specified macro sequence to be executed from the Macro Table. + After completing the macro, execution will continue with the next opcode in the current script. + + + Taking the macro index from the Macro Index Table, multiplying by 8, and adding the result to the Macro Table Pointer base offset will provide the start of the macro in the Macro Table. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + Restrict further processing based on a register condition. + +
+ + This opcode causes the indicated condition to be tested. + If the condition is met the condition flag is unmodified. + If the condition is not met the condition flag is set to the skip operations state. + + + Taking the condition number, multiplying by 12, and adding the result to the Condition Table Pointer base offset will find the start of the given condition. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Engine is checking condition code on entry. + + + + + + + + + + Restrict further processing based on an I/O condition. + +
+ + This opcode causes the indicated I/O condition to be tested. + If the condition is met the condition flag is unmodified. + If the condition is not met the condition flag is set to the skip operations state. + + + Taking the condition number, multiplying by 5, and adding the result to the I/O Condition Table Pointer base offset will find the start of the given condition. + + + Starting with core5, an index of 0xFF in the I/O condition table signals that a direct I/O port shall be used instead of an indexed I/O port. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Engine is checking condition code on entry. + + + + + + + + + + Restrict further processing based on a flag in a flag array indexed by an I/O port value. + +
+ + This opcode causes the indicated I/O flag condition to be tested. + If the condition is met the condition flag is unmodified. + If the condition is not met the condition flag is set to the skip operations state. + + + Taking the condition number, multiplying by 9, and adding the result to the I/O Flag Condition Table Pointer base offset will find the start of the given condition. + +
+ + + + + + + + + + + + + Code in compliance. + + + Engine is forcing the condition code to allow operations on entry when it should be unmodified if condition succeeds. + + + Engine is checking condition code on entry. + + + + + + + + + Write a privileged register with a value from an array chosen based on the value of another privileged register. + +
+ + The first privileged register is read and the value read is masked with the specified AND mask and shifted by the specified shift count. + The resulting value is used as an index into the array of data values to determine the value to write to the destination privileged register. + + + If the address of the privileged register to write is specified as 0, then no writes will occur. + This can be used as a placeholder for a future register address. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + And example of writing a panel register, based on a strap field, would be: + + BYTE  INIT_RESTRICT_PROG + DWORD NV_PEXTDEV_BOOT_0 ; Base on strap register + DWORD 0x03000000 ; AND mask for desired straps + BYTE  24 ; Shift count to make 0 based index + BYTE  4  ; Maximum values to select from + DWORD NV_PRAMDAC_FP_DEBUG_0 ; Register to write with data + DWORD 0x00000384 ; Data for strap index 0 + DWORD 0x0000037F ; Data for strap index 1 + DWORD 0x00000383 ; Data for strap index 2 + DWORD 0x00000384 ; Data for strap index 3 + + + + + + + + + + + + + + + + + Write a privileged register with a value from an array chosen based on the value of an indexed I/O port. + +
+ + The indexed I/O register specified by the I/O port and index is read and the value read is masked with the specified AND mask and shifted by the specified shift count. + The resulting value is used as an index into the array of data values to determine the value to write to the destination privileged register. + + + If the address of the privileged register to write is specified as 0, then no writes will occur. + This can be used as a placeholder for a future register address. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + + + + + + + Modify a privileged register with a value from an array chosen based on the value of an indexed I/O port. + +
+ + The indexed I/O register specified by the I/O port and index is read and the value read is masked with the specified source AND mask and shifted by the specified shift count. + The resulting value is used as an index into the array of data values to determine the value to use to modify the destination privileged register. + + + The destination privileged register is read and the resulting value is masked with the specified AND mask. + An OR operation is performed between masked value and the value selected from the data array. + The result is written back into the destination privileged register. + + + If the address of the privileged register to write is specified as 0, then no writes will occur. + This can be used as a placeholder for a future register address. + +
+ + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final write. + + + Code in compliance. + + + + + + + + + + + + + + + + + + + Program a PLL with a frequency in a table indexed by the value in I/O port. + +
+ + The indexed I/O register specified by the I/O port and index is read and the value read is masked with the specified AND mask and shifted by the specified shift count. + The resulting value is used as an index into the array of data values to fetch the frequency value to program the PLL to. + + + The frequency array is in 10 kHz units. + If the specified doubling I/O flag condition is true, then the frequency will be doubled before being programmed. + This is typically used for DDR memory. + + + If the address of the PLL register to program is specified as 0, then no PLL programming will occur. + This can be used as a placeholder for a future PLL register address. + +
+ + + + + + + + + + + + + Not implemented. + + + Engine is skipping all register accesses, not just the final setting of the PLL. + + + Engine is skipping all register accesses, not just the final setting of the PLL. + + + + + + + + + + + + + + + + + + Program a PLL from a dword frequency array indexed by the value in I/O port. + +
+ + The indexed I/O register specified by the I/O port and index is read and the value read is masked with the specified AND mask and shifted by the specified shift count. + The resulting value is used as an index into the array of data values to fetch the frequency value to program the PLL to. + + + The frequency array is in 1 kHz units. + + + If the address of the PLL register to program is specified as 0, then no PLL programming will occur. + This can be used as a placeholder for a future PLL register address. + + + This opcode was added in core4r2, but first released in core5. + + + Starting with core6 the opcode only updates the coefficients and does not configure or enable the PLL. + +
+ + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final setting of the PLL. + + + Engine is skipping all register accesses, not just the final setting of the PLL. + + + + + + + + + + + + + + + + + + Program a PLL specified by a PLLID from a dword frequency array indexed by the value in I/O port. + +
+ + The indexed I/O register specified by the I/O port and index is read and the value read is masked with the specified AND mask and shifted by the specified shift count. + The resulting value is used as an index into the array of data values to fetch the frequency value to program the PLL to. + + + The frequency array is in 1 kHz units. + + + The PLL is specified by a PLLID. The ID's are fixed defined values. + + + If the ID of the PLL register to program is specified as 0, then no PLL programming will occur. + This can be used as a placeholder for a future PLL register address. + + + This opcode only updates the coefficients and does not configure or enable the PLL. + +
+ + + + + + + + + + + + + Not implemented. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + + + + + Write a privileged register with a value from an array chosen based on the boards memory strap, with a bit screen to specify if the write should be allowed. + +
+ + The VFIELDID_STRAP_MEMSEL virtual register field is used to obtain a memory strap value. + The memory strap value is used as an index into the MemoryStrapTranslation array (pointed to by the BIT). + The byte retrieved from the MemoryStrapTranslation is used as an index into the array of data values to retrieve the value to write to the destination privileged register. + + + The translated value is also used to index into a bit screen (mask). + If the selected bit is zero, the final write to the destination register shall be skipped. + If the selected bit is one, the state of the condition flag determines if the final write to the destination register shall be skipped. + + + The number of data values is specified by the MemoryStrapDataCount (located in the BIT). + The number of bits used for the bit screen is determined by rounding MemoryStrapDataCount up to the next whole byte (8 screen bits per byte). + + + If the address of the privileged register to write is specified as 0, then no writes shall occur. + This can be used as a placeholder for a future register address. + + + While the Resource Manager must use the VFIELDID_STRAP_MEMSEL virtual register field to obtain the memory strap, + the VGA BIOS and Fcode implementations can optionally hard code the logic for obtaining the memory strap or use a different table to obtain it. + This can be used to avoid requiring the VGA BIOS or Fcode implementations do processing of virtual fields. + +
+ + + + + + + + + + + + + Not implemented. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + + + Modify a privileged register using an AND mask and a value from an array chosen based on the boards memory strap, with a bit screen to specify if the write should be allowed. + +
+ + The VFIELDID_STRAP_MEMSEL virtual register field is used to obtain a memory strap value. + The memory strap value is used as an index into the MemoryStrapTranslation array (pointed to by the BIT). + The byte retrieved from the MemoryStrapTranslation is used as an index into the array of data values to retrieve the value used to modify the destination privileged register. + The engine reads the privileged register, and then performs a logical AND on the read value using the AND mask. + It then does a logical OR on the value using the chosen value from the array of data values. + The resulting value is then written back to the privileged register. + + + The translated value is also used to index into a bit screen (mask). + If the selected bit is zero, the final write to the destination register shall be skipped. + If the selected bit is one, the state of the condition flag determines if the final write to the destination register shall be skipped. + + + The number of data values is specified by the MemoryStrapDataCount (located in the BIT). + The number of bits used for the bit screen is determined by rounding MemoryStrapDataCount up to the next whole byte (8 screen bits per byte). + + + If the address of the privileged register to write is specified as 0, then no writes shall occur. + This can be used as a placeholder for a future register address. + + + While the Resource Manager must use the VFIELDID_STRAP_MEMSEL virtual register field to obtain the memory strap, + the VGA BIOS and Fcode implementations can optionally hard code the logic for obtaining the memory strap or use a different table to obtain it. + This can be used to avoid requiring the VGA BIOS or Fcode implementations do processing of virtual fields. + +
+ + + + + + + + + + + + + Not implemented. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + + + + Write a consecutive sequence of privileged registers with a block of values from a two dimensional array chosen based on the boards memory strap. + +
+ + The VFIELDID_STRAP_MEMSEL virtual register field is used to obtain a memory strap value. + The memory strap value is used as an index into the MemoryStrapTranslation array (pointed to by the BIT). + + The byte retrieved from the MemoryStrapTranslation is used as a starting index into the array of data values. + The address specified in the instruction is used as the starting privileged register address. + A 32-bit value retrieved from the array using the starting index is written to the privileged register. + The privileged register address is advanced by the number of bytes specified by the stride and the index into the data values + is advanced by adding the value of MemoryStrapDataCount (located in the BIT). + This is repeated so that the total number of registers written is equal to the value of the count field in the instruction. + + + The total number of data values in the array is computed by multiplying the count specified in the instruction by the value of MemoryStrapDataCount. + + + If the address of the privileged register to write is specified as 0, then no writes shall occur. + This can be used as a placeholder for a future register address. + + + While the Resource Manager must use the VFIELDID_STRAP_MEMSEL virtual register field to obtain the memory strap, + the VGA BIOS and Fcode implementations can optionally hard code the logic for obtaining the memory strap or use a different table to obtain it. + This can be used to avoid requiring the VGA BIOS or Fcode implementations do processing of virtual fields. + +
+ + + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + + Set a PLL with a frequency from an array chosen based on the boards memory strap. + +
+ + The VFIELDID_STRAP_MEMSEL virtual register field is used to obtain a memory strap value. + The memory strap value is used as an index into the MemoryStrapTranslation array (pointed to by the BIT). + The byte retrieved from the MemoryStrapTranslation is used as an index into the array of frequencies to determine the frequency to program the specified PLL to. + The coefficients programmed into the PLL are calculated by the BIOS from the frequency, based on the chipset's PLL programming algorithm. + + + The 32-bit frequency value is stored in kilohertz (i.e.: 125Mhz = 125000). + + + The PLL is specified by a PLLID. The ID's are fixed defined values. + + + The number of frequency values is specified by the MemoryStrapDataCount (located in the BIT). + + + While the Resource Manager must use the VFIELDID_STRAP_MEMSEL virtual register field to obtain the memory strap, + the VGA BIOS and Fcode implementations can optionally hard code the logic for obtaining the memory strap or use a different table to obtain it. + This can be used to avoid having the VGA BIOS or Fcode implementations have to do virtual field processing. + + + This opcode only updates the coefficients and does not configure or enable the PLL. + +
+ + + + + + + + + + + + + Not implemented. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + Repeat a block of script a specified number of times. + +
+ + This opcode causes the following code, up to an INIT_END_REPEAT, to be executed a specified number of times. + + + Note that there must not be an INIT_DONE (or synonym) before the INIT_END_REPEAT code. + + + The INIT_REPEAT opcode ignores the condition flag, but the codes being repeated will refer to or change the condition flag as they normally would. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + End of current script. + +
+ + This opcode terminates the processing of the current script. + For the boot scripts the devinit engine will continue processing with the next script in the Script Table. + + + If the condition flag is not reset via INIT_RESUME prior to INIT_DONE, correct operation is not guaranteed. See section on "Sub scripts and the Condition Flag." + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + NV1 opcode for the end of current script. + +
+ + This opcode signifies the end of the current script. + It was replaced by INIT_DONE. + +
+ + + + + + + + + + + + + + + + + + + Signal the end of a repeat block. + +
+ + This opcode delimitates the end of a INIT_REPEAT block. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + Execute another script (specified with a direct offset) and then return to process the current script. + +
+ + Unlike INIT_SUB which uses a script index, this opcode has a direct offset to the sub script. + + + Control returns to the opcode immediately following the INIT_SUB after the sub script has been executed. + + + In the VBIOS implementation of the devinit engine, the new script is executed by calling the devinit engine recursively. + + + If the condition flag is set to the skip operations state the subscript will not be executed. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + Terminate execution of the current script and run a new one (specified with a direct offset). + +
+ + This opcode ends processing of the current script, and begins execution of the new script. + Control is not returned to the script containing the INIT_JUMP opcode. + Unlike INIT_JUMP which uses a script index, this opcode has a direct offset to the new script. + + + If the condition flag is set to the skip operations state the jump will not be executed. + In that case, there need to be valid opcodes following the INIT_JUMP opcode. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + Terminate execution of the current script and run a new one (specified relative to the current offset). + +
+ + This opcode ends processing of the current script, and begins execution of the new script. + Control is not returned to the script containing the INIT_JUMP opcode. + This opcode uses a relative displacement from the current location to specify where to continue execution. + The displacement is relative to the offset immediately after the displacement byte. + The displacement is a signed two's complement value. + + + If the condition flag is set to the skip operations state the jump will not be executed. + In that case, there need to be valid opcodes following the INIT_JUMP opcode. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + Exit current script if conditions have been met. + +
+ + This opcode terminates processing of the current script if the condition flag is set to the perform operations state. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + Write a sequence of new values to a sequence of I2C registers (zero mask). When count = 1, Sends I2C register byte address, without adding any effective write + +
+ + The I2C Port Index uses the same equates normally used in the VBIOS, i.e. I2C_A, I2C_B, to indicate the first and second logical I2C ports, respectively. + Alternatively, USE_DCB_I2C (0xFF) will force the usage of the logical I2C port index associated with the currently active display for programming external devices, a per-head value. + Internally, the VBIOS uses the DCB index scratch register field for the current head to find the I2C port specified by the DCB entry. + This assumes: + + + + 1. When this opcode is called, the VBIOS is NOT in broadcast mode + + + 2. The DCB index for the head the VBIOS is on is either a valid DCB index or EMPTY_HEAD + + + 3. If the DCB index is EMPTY_HEAD the opcode processing will be skipped (essentially, making this opcode a no-op) + + + + For core4r2 the I2C port for external devices is always assumed to be I2C_C except on crush where it is I2C_D. + So for core4r2 the current head does not need to be known. + For core5 the DCB entry for the currently active device on the CR44 head is checked to see if the primary or secondary I2C port for external devices shall be used. + The primary and secondary ports are specified in the DCB I2C Control Block. + + + For core5 two other special values can also be used for the I2C Port Index. + USE_PRIMARY_I2C uses the primary port and USE_SECONDARY_I2C uses the secondary port as specified in the DCB I2C Control Block. + + + For core6 another special value USE_DCB_DDC (0xFE) can also be used for the I2C Port Index, it uses the associated DCB entry's DDC port. + + + The device address specifies the I2C address of the device to initialize via the selected I2C port (e.g. SI178 uses 0x70, CX871 uses 0x88). + + + Note that the count shall include the register address byte (RAB) and thus has to be one more than the number of data values following the RAB. + + + The devinit engine must not generate any I2C traffic when the condition code specifies that operations should be skipped. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + Write a set of new values to a set of I2C registers (zero mask). + +
+ + This opcode causes a given number of registers in a device to be written with specified values through a given I2C port. + + + The designation 'alternating' refers to this opcode's ability to simulate the mode of some I2C devices which allows them to write several non-adjacent I2C registers in a single I2C message by concatenating {address, data} pairs (normally described as 'alternating write mode'). + This opcode simulates that ability by breaking the {address, data} pairs into separate I2C messages, with a full stop/start inserted between each pair. + + + The I2C Port Index uses the same equates normally used in the VBIOS, i.e. I2C_A, I2C_B, to indicate the first and second logical I2C ports, respectively. + Alternatively, USE_DCB_I2C (0xFF) will force the usage of the logical I2C port index associated with the currently active display for programming external devices, a per-head value. + Internally, the VBIOS uses the DCB index scratch register field for the current head to find the I2C port specified by the DCB entry. + This assumes: + + + + 1. When this opcode is called, the VBIOS is NOT in broadcast mode + + + 2. The DCB index for the head the VBIOS is on is either a valid DCB index or EMPTY_HEAD + + + 3. If the DCB index is EMPTY_HEAD the opcode processing will be skipped (essentially, making this opcode a no-op) + + + + For core4r2 the I2C port for external devices is always assumed to be I2C_C except on crush where it is I2C_D. + So for core4r2 the current head does not need to be known. + For core5 the DCB entry for the currently active device on the CR44 head is checked to see if the primary or secondary I2C port for external devices shall be used. + The primary and secondary ports are specified in the DCB I2C Control Block. + + + For core5 two other special values can also be used for the I2C Port Index. + USE_PRIMARY_I2C uses the primary port and USE_SECONDARY_I2C uses the secondary port as specified in the DCB I2C Control Block. + + + For core6 another special value USE_DCB_DDC (0xFE) can also be used for the I2C Port Index, it uses the associated DCB entry's DDC port. + + + The device address specifies the I2C address of the device to initialize via the selected I2C port (e.g. SI178 uses 0x70, CX871 uses 0x88). + + + The devinit engine must not generate any I2C traffic when the condition code specifies that operations should be skipped. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + + Read/modify/write an list of I2C register(s) + +
+ + This opcode causes a specified set of registers in a device to be read, modified, and rewritten through a given I2C port. + + + The designation 'alternating' refers to this opcode's ability to simulate the mode of some I2C devices which allows them to write several non-adjacent I2C registers in a single I2C message by concatenating {address, data} pairs (normally described as 'alternating write mode'). + This opcode simulates that ability by breaking the {address, data} pairs into separate I2C messages, with a full Stop/Start inserted between each pair. + + + The I2C Port Index uses the same equates normally used in the VBIOS, i.e. I2C_A, I2C_B, to indicate the first and second logical I2C ports, respectively. + Alternatively, USE_DCB_I2C (0xFF) will force the usage of the logical I2C port index associated with the currently active display for programming external devices, a per-head value. + Internally, the VBIOS uses the DCB index scratch register field for the current head to find the I2C port specified by the DCB entry. + This assumes: + + + + 1. When this opcode is called, the VBIOS is NOT in broadcast mode + + + 2. The DCB index for the head the VBIOS is on is either a valid DCB index or EMPTY_HEAD + + + 3. If the DCB index is EMPTY_HEAD the opcode processing will be skipped (essentially, making this opcode a no-op) + + + + For core4r2 the I2C port for external devices is always assumed to be I2C_C except on crush where it is I2C_D. + So for core4r2 the current head does not need to be known. + For core5 the DCB entry for the currently active device on the CR44 head is checked to see if the primary or secondary I2C port for external devices shall be used. + The primary and secondary ports are specified in the DCB I2C Control Block. + + + For core6 another special value USE_DCB_DDC (0xFE) can also be used for the I2C Port Index, it uses the associated DCB entry's DDC port. + + + For core5 two other special values can also be used for the I2C Port Index. + USE_PRIMARY_I2C uses the primary port and USE_SECONDARY_I2C uses the secondary port as specified in the DCB I2C Control Block. + + + The device address specifies the I2C address of the device to initialize via the selected I2C port (e.g. SI178 uses 0x70, CX871 uses 0x88). + + + The devinit engine must not generate any I2C traffic when the condition code specifies that operations should be skipped. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + + + Poll an I2C register until a masked value compares correctly + +
+ + This opcode will poll an I2C register continually until a masked value results in a positive compare. + + + The timeout value sets the maximum amount of time this opcode will consume, and is not meant to control the sample rate for the terminating condition. + This means that the mask/compare operation will usually occur at a higher rate than the delay value. + Note that the units for this opcode are different than the other polling opcodes. + + + If the poll is not satisfied and a timeout condition or an I2C read failure occurs the condition flag will be set to the skip operations state. + Otherwise the condition flag is left in its current state from before the execution of the opcode. + For this reason, it will often be desirable to follow this opcode with an INIT_RESUME if there is no need to know if the timeout occurred. + + + The I2C Port Index uses the same equates normally used in the VBIOS, i.e. I2C_A, I2C_B, to indicate the first and second logical I2C ports, respectively. + Alternatively, USE_DCB_I2C (0xFF) will force the usage of the logical I2C port index associated with the currently active display for programming external devices, a per-head value. + Internally, the VBIOS uses the DCB index scratch register field for the current head to find the I2C port specified by the DCB entry. + This assumes: + + + + 1. When this opcode is called, the VBIOS is NOT in broadcast mode + + + 2. The DCB index for the head the VBIOS is on is either a valid DCB index or EMPTY_HEAD + + + 3. If the DCB index is EMPTY_HEAD the opcode processing will be skipped (essentially, making this opcode a no-op) + + + + For core4r2 the I2C port for external devices is always assumed to be I2C_C except on crush where it is I2C_D. + So for core4r2 the current head does not need to be known. + For core5 the DCB entry for the currently active device on the CR44 head is checked to see if the primary or secondary I2C port for external devices shall be used. + The primary and secondary ports are specified in the DCB I2C Control Block. + + + For core5 two other special values can also be used for the I2C Port Index. + USE_PRIMARY_I2C uses the primary port and USE_SECONDARY_I2C uses the secondary port as specified in the DCB I2C Control Block. + + + For core6 another special value USE_DCB_DDC (0xFE) can also be used for the I2C Port Index, it uses the associated DCB entry's DDC port. + + + The device address specifies the I2C address of the device to initialize via the selected I2C port (e.g. SI178 uses 0x70, CX871 uses 0x88). + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + This example will poll register 0x04 from the device at address 0x70 on I2C port B. + Bit 3 of the read value needs to be 0 and bit 2 needs to be a 1. + The polling will not take more than 20 milliseconds before terminating. + + BYTE INIT_POLL_I2C + BYTE 02h ; Use I2C port B as specified in the DCB + BYTE 70h ; Device address 0x70 + BYTE 04h ; Register address 0x04 + BYTE 0Ch ; AND mask + BYTE 04h ; Compare value + BYTE 02h ; 20 milliseconds max before continuing + + + + + + + + + + + + + + + Check the condition of a register over I2C port + +
+ + This opcode causes the indicated I2C condition to be tested. + If the condition is met the condition flag is unmodified. + If the condition is not met or an I2C read failure occurs the condition flag is set to the skip operations state. + + + The I2C Port Index uses the same equates normally used in the VBIOS, i.e. I2C_A, I2C_B, to indicate the first and second logical I2C ports, respectively. + Alternatively, USE_DCB_I2C (0xFF) will force the usage of the logical I2C port index associated with the currently active display for programming external devices, a per-head value. + Internally, the VBIOS uses the DCB index scratch register field for the current head to find the I2C port specified by the DCB entry. + This assumes: + + + + 1. When this opcode is called, the VBIOS is NOT in broadcast mode + + + 2. The DCB index for the head the VBIOS is on is either a valid DCB index or EMPTY_HEAD + + + 3. If the DCB index is EMPTY_HEAD the opcode processing will be skipped (essentially, making this opcode a no-op) + + + + For core4r2 the I2C port for external devices is always assumed to be I2C_C except on crush where it is I2C_D. + So for core4r2 the current head does not need to be known. + For core5 the DCB entry for the currently active device on the CR44 head is checked to see if the primary or secondary I2C port for external devices shall be used. + The primary and secondary ports are specified in the DCB I2C Control Block. + + + For core5 two other special values can also be used for the I2C Port Index. + USE_PRIMARY_I2C uses the primary port and USE_SECONDARY_I2C uses the secondary port as specified in the DCB I2C Control Block. + + + For core6 another special value USE_DCB_DDC (0xFE) can also be used for the I2C Port Index, it uses the associated DCB entry's DDC port. + + + The device address specifies the I2C address of the device to initialize via the selected I2C port (e.g. SI178 uses 0x70, CX871 uses 0x88). + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + This example will test register 0x04 from the device at address 0x70 on I2C port B. + Bit 3 of the read value needs to be 0 and bit 2 needs to be a 1 for the condition to be considered met. + + BYTE INIT_I2C_CONDITION + BYTE 02h ; Use I2C port B as specified in the DCB + BYTE 70h ; Device address 0x70 + BYTE 04h ; Register address 0x04 + BYTE 0Ch ; AND mask + BYTE 04h ; Compare value + + + + + + + + + + + + + Performs read/modify/write on an internal TMDS/LVDS encoder link register. + +
+ + This opcode reads a TMDS/LVDS encoder link register at the specified index on the specified link, masks the value with the specified AND mask, performs an OR operation with the specified OR mask, and write the result back to the register. + + + The definition of the "link" field is as follows: + + + + 0 - link A + + + 1 - link B + + + 2 - link C + + + 3 - link D + + + 0x80 - "context" link + + + 0x81 - "context" link's mate (link B if link A is the "context" link) + + + + Where "context" link is defined as the link that needs to be operated on. + For the Resource Manager, the code will have complete knowledge of which this is. + + + For the VBIOS the definition of the "context" link as follows: + + + + 1. Take the current value for CR44 to determine the "current" head. + (Note: While the VBIOS always leaves CR44 in broadcast mode for apps, internally it sets it to only the head its currently dealing with (enabling, disabling, changing DPMS level, etc.) + + + 2. Use the scratch register to find what the current DCB index is for the current head (Note: Step 1 above is just conceptual, by just reading the scratch register, CR44 automatically directs us to the current head). + + + 3. Use the link specified in the retrieved DCB entry + + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + + Write a sequence of data values to an internal TMDS/LVDS encoder link. + +
+ + This opcode writes the specified index/data pairs to the specified internal TMDS/LVDS encoder link. + + + The definition of the "link" field is as follows: + + + + 0 - link A + + + 1 - link B + + + 2 - link C + + + 3 - link D + + + 0x80 - "context" link + + + 0x81 - "context" link's mate (link B if link A is the "context" link) + + + + Where "context" link is defined as the link that needs to be operated on. + For the Resource Manager, the code will have complete knowledge of which this is. + + + For the VBIOS the definition of the "context" link as follows: + + + + 1. Take the current value for CR44 to determine the "current" head. (Note: While the VBIOS always leaves CR44 in broadcast mode for apps, internally it sets it to only the head its currently dealing with (enabling, disabling, changing DPMS level, etc.) + + + 2. Use the scratch register to find what the current DCB index is for the current head (Note: Step 1 above is just conceptual, by just reading the scratch register, CR44 automatically directs us to the current head). + + + 3. Use the link specified in the retrieved DCB entry + + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + + + + Write a set of indirectly indexed CRTC registers with constants. + +
+ + This opcode will write a series of indirectly indexed CRTC registers. + + + This opcode first writes the index register index to the CRTC base address (0x3D4 or 0x3B4) to select the 'CR space' of the bank of indirect CRTC registers (referred to as INDxx here) to access. + It then writes the starting indirect index to the CRTC data register (0x3D5 or 0x3B5). + + + The next step is to write the data register index to the CRTC base address (0x3D4 or 0x3B4) to allow access to the INDxx register of interest. + It then writes the data1 value to the CRTC data register (0x3D5 or 0x3B5), effectively updating that INDxx register. + + + This repeats for the number of INDxx registers specified by the count N. + + + A two INDxx register example is given here. + The example sets IND00 and IND01 to FFh. + + + For clarity, the example is translated here as a series of DEBUG commands. + + + + o 3d4 57 ;use color CRTC base address to select INDxx index + + + o 3d5 0 ;point at IND00 + + + o 3d4 58 ;use color CRTC base address to select INDxx data + + + o 3d5 FF ;update IND00 to FFh + + + o 3d4 57 ;use color CRTC base address to select INDxx index + + + o 3d5 1 ;point at IND01 + + + o 3d4 58 ;use color CRTC base address to select INDxx data + + + o 3d5 FF ;update IND01 to FFh + + +
+ + + + + + + + + + + + + Code in compliance. + + + Engine is skipping all register accesses, not just the final write. + + + Engine is skipping all register accesses, not just the final write. + + + BYTE INIT_INDEXED_CRTC + BYTE 57h ;CRTC INDxx index register + BYTE 58h ;CRTC INDxx data register + BYTE 00h ;starting INDxx index + BYTE 02h ;count + BYTE FFh ;first data byte + BYTE FFh ;second data byte + + + + + + + + + + + + + + + Perform a logic AND operation on a dword in the data buffer and a specified value. + +
+ + The 32-bit value at the specified byte offset into the data buffer is retrieved. + An AND operation is performed between the retrieved value and the data value specified in the opcode. + The result is stored back at the specified byte offset into the data buffer. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Perform a logic OR operation on a dword in the data buffer and a specified value. + +
+ + The 32-bit value at the specified byte offset into the data buffer is retrieved. + An OR operation is performed between the retrieved value and the data value specified in the opcode. + The result is stored back at the specified byte offset into the data buffer. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Perform a logic XOR operation on a dword in the data buffer and a specified value. + +
+ + The 32-bit value at the specified byte offset into the data buffer is retrieved. + An XOR operation is performed between the retrieved value and the data value specified in the opcode. + The result is stored back at the specified byte offset into the data buffer. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Perform a shift operation on a dword in the data buffer by a specified amount. + +
+ + The 32-bit value at the specified byte offset into the data buffer is retrieved. + The value is right shifted by the specified number of bits. + The result is stored back at the specified byte offset into the data buffer. + + + S008shift can be negative (two's complement) for a left shift + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Perform a logic AND operation on a byte in the data buffer and a specified value. + +
+ + The 8-bit value at the specified byte offset into the data buffer is retrieved. + An AND operation is performed between the retrieved value and the data value specified in the opcode. + The result is stored back at the specified byte offset into the data buffer. + +
+
+ + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Perform a logic OR operation on a byte in the data buffer and a specified value. + +
+ + The 8-bit value at the specified byte offset into the data buffer is retrieved. + An OR operation is performed between the retrieved value and the data value specified in the opcode. + The result is stored back at the specified byte offset into the data buffer. + +
+
+ + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Perform a logic XOR operation on a byte in the data buffer and a specified value. + +
+ + The 8-bit value at the specified byte offset into the data buffer is retrieved. + An XOR operation is performed between the retrieved value and the data value specified in the opcode. + The result is stored back at the specified byte offset into the data buffer. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Perform a shift operation on a byte in the data buffer by a specified amount. + +
+ + The 8-bit value at the specified byte offset into the data buffer is retrieved. + The value is right shifted by the specified number of bits. + The result is stored back at the specified byte offset into the data buffer. + + + S008shift can be negative (two's complement) for a left shift + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + + Skip past the specified number of bits in the data stream. + +
+ + The current position of the data stream is advanced by the specified number of bits. + The stream can be advanced into the next byte or any following bytes. + + + S008data can be negative (two's complement) to go backward in the stream. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not implemented yet. + + + Not implemented yet. + + + + + + + + + Forces a computation of the memory size. + +
+ + This function forces the init processor to execute the chipset specific algorithm to compute the total frame buffer memory size installed. + + + This opcode causes the BIOS function NVResizeMemory to be called. + Upon return from the memory sizing routine, the devinit engine continues processing. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Engine is honoring the condition flag. + + + + + + + + Forces the Memory Information Table entry look-up. + +
+ + This function forces the init processor to execute entry look-up in the Memory Information Table, which includes reading Memory Strap and/or Memory ID from hardware registers and searching for the matching entry. The memory information is then cached for fast retrieval in subsequent operations. Upon return from the Memory Information Table entry look-up, the devinit engine continues processing. + + + This opcode allows for clear indication of when to read the Memory Strap and Memory ID registers, which may be manipulated by other devinit opcodes, so that all engines can be instructed to process the Memory Information Table in an identical sequence. + +
+ + + + + + + + + + + + + + + Not Implemented. + + + Not Implemented. + + + Not Implemented. + + + + + + + + Write an NV1 DAC register after applying a mask. + +
+ + This opcode first reads the DAC register. + It then performs a logical AND on the read value using the AND mask, then a logical OR on the value using the OR mask. + The resulting value is then written to the specified register. + +
+ + + + + + + + + + + + + Not implemented (deprecated). + + + + + + + + + + + Configure Memory Registers (Skip to Next Table). + +
+ + This function forces the initialization processor to execute the chipset specific algorithm to initialize the memory configuration registers using the memory configuration tables. + This operation is performed before the memory sizing is performed. + + + Prior to core3, the opcode would cause the devinit engine to call the hard coded memory initialization routine (NVConfigureMemory). + + + This opcode was modified starting in core3 to instead terminate the current script, which would cause the execution of the following script in the POST Script Table to be executed. + + + Note: Compatibility with older drivers written for BIOS images before core3 is maintained by pointing the next sequential Script Table entry at the memory initialization script. + The Script Table entry following the memory initialization script entry points back to the next opcode in the pre-core3 compatible devinit script. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + +
+ + This function forces the initialization processor to execute the chipset specific algorithm to initialize the memory PLL and NV PLL using the memory configuration tables. + + + Prior to core3, the opcode would cause the devinit engine to call the hard coded memory initialization routine (NVConfigureClocks). + + + This opcode was modified starting in core3 to instead terminate the current script, which would cause the execution of the following script in the POST Script Table to be executed. + + + Note: Compatibility with older drivers written for BIOS images before core3 is maintained by pointing the next sequential Script Table entry at the clock initialization script. + The Script Table entry following the clock initialization script entry points back to the next opcode in the pre-core3 compatible devinit script. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + Configure initialization variables from HW strapping. + +
+ + This function forces the initialization processor to execute the chipset specific algorithm to initialize certain scratch bits that indicate the strapped hardware configuration by way of reading the Strapping Register (NV_PEXTDEV_BOOT_0). + + + The opcode initializes variables for the reference frequency (13Mhz vs. 14.318Mhz), and the RAM configuration straps. + + + Prior to core3, the opcode would cause the devinit engine to call the hard coded initialization routine (ChipPreInit). + + + This opcode was modified starting in core3 to instead terminate the current script, which would cause the execution of the following script in the POST Script Table to be executed. + + + Note: Compatibility with older drivers written for BIOS images before core3 is maintained by pointing the next sequential Script Table entry at the pre-initialization script. + The Script Table entry following the pre-initialization script entry points back to the next opcode in the pre-core3 compatible devinit script. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + Set the NV1 DAC PLL synthesizer clock. + +
+ + Programs the specified NV1 PLL with the specified coefficients. + +
+ + + + + + + + + + + + + Not implemented (deprecated). + + + + + + + + + + + + + + Signal end of the initialization script. + +
+ + This opcode terminates the processing of the current script. + For the boot scripts the devinit engine will continue processing with the next script in the Script Table. + +
+ + + + + + + + + + + + + + + + + + Write a sequence of data values to an address latched index register set. + +
+ + This opcode retrieves the first data value and writes it to the data register. + It then reads the control register and performs an AND operation on the value read and the control AND mask. + An OR operation is done between the resulting value, the control OR mask, and the first index value. + This value is then written back to the control register. + + + This process is repeated for all the index/data pairs. + The number of pairs is specified by the count value. + + + If the data register is specified as zero, the devinit engine must skip processing of this opcode. + +
+ + + + + + + + + + + + + The Core5 implementation is not checking for a data register address of zero. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + + + + + + + Test frequency condition. + +
+ + This opcode causes the indicated frequency condition to be tested. + If the condition is met the condition flag is unmodified. + If the condition is not met the condition flag is set to the skip operations state. + + + Taking the PLL code, multiplying by 4, and adding the result to the PLL Register Table Pointer base offset will find the register address of the PLL coefficients to use for the test. + The clock frequency is computed from these coefficients and then compared to the range. + The range is specified in 10 kHz units. + The range to use is first determined by using the virtual field code to access the virtual field table. + The value from this register field is fetched. + The value is then used as a byte index into the translation table referenced by the translation code. + The value at that byte is then used as the index in the frequency array to determine which range to use. + +
+ + This opcode is only used in the full memory initialization sequence for the Resource Manager. + + + + + + + + + + + + + + Not implemented (not needed at this time). + + + Code in compliance. + + + Not implemented (not needed at this time). + + + + + + + + + + + + + + + + Write a privileged register with a value from a table indexed by the translated value of field in another privileged register. + +
+ + This opcode writes different values to a register based on a translated value. + The virtual field code is used to access the virtual field table. + The value from this register field is fetched. + The value is then used as a byte index into the translation table referenced by the translation code. + The value at that byte is then used as the index in the data array to determine which dword to use. + The indicated register is read and an AND operation is performed using the AND mask. + Finally, an OR operation is performed using the dword from the data array and the result is written back into the register. + + + If the address of the privileged register to write is specified as 0, then no writes will occur. + This can be used as a placeholder for a future register address. + +
+ + This opcode is only used in the full memory initialization sequence for the Resource Manager. + + + + + + + + + + + + + + Not implemented (not needed at this time). + + + Code in compliance. + + + Not implemented (not needed at this time). + + + + + + + + + + + + + + + + Write a part of a privileged register with a value from a table indexed by the translated value of field in another register. + +
+ + This opcode writes different values to a register based on a translated value. + The virtual field code is used to access the virtual field table. + The value from this register field is fetched. + The value is then used as a byte index into the translation table referenced by the translation code. + The value at that byte is then used as the index in the data array to determine which byte to use. + The indicated register is read and an AND operation is performed using the AND mask. + Finally, an OR operation is performed using the byte from the data array after it has been shifted by the indicated shift amount and the result is written back into the register. + + + If the address of the privileged register to write is specified as 0, then no writes will occur. + This can be used as a placeholder for a future register address. + +
+ + This opcode is only used in the full memory initialization sequence for the Resource Manager. + + + + + + + + + + + + + + Not implemented (not needed at this time). + + + Code in compliance. + + + Not implemented (not needed at this time). + + + + + + + + + + + + + + + + + Programs a PLL with a value from a table indexed by the translated value of field in another register. + +
+ + This opcode programs different values to a PLL based on a translated value. + The virtual field code is used to access the virtual field table. + The value from this register field is fetched. + The value is then used as a byte index into the translation table referenced by the translation code. + The value at that byte is then used as the index in the data array to determine which frequency to use. + + + If the address of the PLL register to program is specified as 0, then no PLL programming will occur. + This can be used as a placeholder for a future PLL register address. + +
+ + This opcode is only used in the full memory initialization sequence for the Resource Manager. + + + + + + + + + + + + + + Not implemented (not needed at this time). + + + Not checking to see if the PLL register to program is zero. + + + Not implemented (not needed at this time). + + + + + + + + + + + + + + + Programs spread spectrum for all PLL's/clocks that have spread spectrum enabled, other than the pixel clocks. + +
+ + This function causes all spread spectrum programming to occur for the system, other than pixel clocks. + Processing of the opcode depends on the core and chip family, but for the most part involves checking the DCB to see if spread is enabled and what the settings are and programming those settings. + + + Spread programming should be performed for both internal and external spread (which ever one is specified in the DCB). + +
+ + + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Not implemented. + + + + + + + + + Add a delta to current value of a privileged register with mask. + +
+ + This opcode first reads the specified privileged register. + It then adds the add value to the value read. + Next it performs a logical AND on the resulting sum using the bitwise inverse of the AND mask to mask out any overflow. + A logical AND on the original value read using the AND mask (not inverted) is then performed. + The results of the two AND operations are then combined with a logical OR operation. + The result from the final OR operation is then written to the privileged register. + +
+ + + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + Write DPCD registers with mask. + +
+ + This opcode first reads the specified DPCD registers, and with AND mask, then or with the data. + The result is then written to the DPCD registers. + +
+ + + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + + + + Write DPCD registers. + +
+ + This opcode writes the specified DPCD registers. + +
+ + + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Code in compliance. + + + + + + + + + + + + + Poll DPCD register until a masked value compares correctly + +
+ + This opcode will poll a DPCD register continually until a masked value results in a positive compare. + + + The timeout value sets the maximum amount of time this opcode will consume, and is not meant to control the sample rate for the terminating condition. + This means that the mask/compare operation will usually occur at a higher rate than the delay value. + + + If the poll is not satisfied and a timeout condition or a DPCD read failure occurs the condition flag will be set to the skip operations state. + Otherwise the condition flag is left in its current state from before the execution of the opcode. + For this reason, it will often be desirable to follow this opcode with an INIT_RESUME if there is no need to know if the timeout occurred. + +
+ + + + + + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + Check the condition of a DPCD register + +
+ + This opcode causes the indicated DPCD condition to be tested. + If the condition is met the condition flag is unmodified. + If the condition is not met or a DPCD read failure occurs the condition flag is set to the skip operations state. + +
+ + + + + + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + Programs a PLL with a frequency from a table indexed by the translated value of field in another register. + +
+ + This opcode programs different values to a PLL based on a translated value. + The virtual field code is used to access the virtual field table. + The value from this register field is fetched. + The value is then used as a byte index into the translation table referenced by the translation code. + The value at that byte is then used as the index in the data array to determine which frequency to use. + + + If the address of the PLL register to program is specified as 0, then no PLL programming will occur. + This can be used as a placeholder for a future PLL register address. + + + Starting with core6 the opcode only updates the coefficients and does not configure or enable the PLL. + +
+ + This opcode is only used in the full memory initialization sequence for the Resource Manager. + + + + + + + + + + + + + + Not implemented (not needed at this time). + + + Not implemented. + + + Not implemented (not needed at this time). + + + + + + + + + + + + + + + Write a part of a privileged register with a value from a table indexed by the value of field in another privileged register. + +
+ + First a 32-bit value is read from the register at the specified privileged register (source register). + This value is then right shifted using the 8-bit shift count. + An AND operation is then performed on this shifted value using the 8-bit source AND mask. + The resulting value, the data array offset, is then used as an index into a data array of bytes to get the value to write into the destination privileged register. + The data array to use is indicated by the data array table index. + The data array table index is an index into a table of word pointers to data arrays. + The base address of the data array pointer table (referred to as the table of word pointers above) is in the VBIOS BIT (DataArraysTablePtr in the BIT_NVINIT_PTRS structure). + The destination register is read and an AND operation is performed using the AND mask. + The value retrieved from the data array is shifted left by the indicated shift amount and then ORed with the the result of the AND operation in the previous step. + The resulting value is written back into the destination register. + +
+ + + + + + + + + + + + + + Code in compliance. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + + Cause a breakpoint to be triggered while processing the devinit script. + +
+ + This opcode causes the BIOS to assert an INT1 to invoke the debugger. This can be used as a devinit script "breakpoint". + + + This opcode must never appear in production code. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not currently supported. + + + Not currently supported. + + + + + + + + Signal that the reset sequence has begun. + +
+ + This opcode signals that the software reset sequence has begun. + Ordinarily, no actual operations are performed by the opcode. + However it allows for possible software work arounds by devinit engines in software agents other than the VBIOS, such as the resman, FCODE, and EFI driver. + This opcode is designed to be included in the devinit script immediately after the NV_PMC_ENABLE register has be written to put most engines into a reset state. + + + In general, performing operations when encountering this opcode should be avoided. + Ideally any new operations needed should be communicated back to the VGA BIOS team so that they can be listed explicitly in the devinit sequence. + The reason for this is that these work arounds can interfere with forward compatibility. + However, this opcode exists for those cases where embedding the operations in the devinit sequence is not possible or practical + (such as work arounds for VGA BIOS images that have already shipped). + + + Any operations performed when this opcode is processed must be documented here in this specification to make + sure these operations are taken into account for future devinit scripts. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not currently supported. + + + Not currently supported. + + + + + + + + Signal that the reset sequence has completed. + +
+ + This opcode signals that the software reset sequence has completed. + Ordinarily, no actual operations are performed by the opcode. + However it allows for possible software work arounds by devinit engines in software agents other than the VBIOS, such as the resman, FCODE, and EFI driver. + This opcode is designed to be included in the devinit script immediately after the NV_PMC_ENABLE register has be written to take most of the engines out of the reset state. + + + In general, performing operations when encountering this opcode should be avoided. + Ideally any new operations needed should be communicated back to the VGA BIOS team so that they can be listed explicitly in the devinit sequence. + The reason for this is that these work arounds can interfere with forward compatibility. + However, this opcode exists for those cases where embedding the operations in the devinit sequence is not possible or practical + (such as work arounds for VGA BIOS images that have already shipped). + + + Any operations performed when this opcode is processed must be documented here in this specification to make + sure these operations are taken into account for future devinit scripts. + +
+ + + + + + + + + + + + + Code in compliance. + + + Not currently supported. + + + Not currently supported. + + + + + + + + Configure all GPIO's based on the DCB GPIO Assignment Table. + +
+ + This opcode causes the devinit engine to process the DCB GPIO Assignment Table and initialize + the output enable and output level for each listed GPIO to the state specified by the "init" bit in each entry. + The normal, sequencer, alternate setting for each GPIO listed is also configured. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Not currently supported. + + + + + + + + Initialize all GPIOs less a specified set of GPIOs by function, based on the DCB GPIO Assignment Table. + +
+ + This opcode is similar to INIT_GPIO_ALL, except that it lists an array of GPIO functions to be excluded from initialization. + It can only be called once in devinit. + +
+ + + + + + + + + + + + + + + + + Code in compliance. + + + Code in compliance. + + + Not currently supported. + + + + + + + + + + + + Initialize a specified set of GPIOs by function, based on the DCB GPIO Assignment Table. + +
+ + This opcode is similar to INIT_GPIO_ALL, except that it lists an array of GPIO functions to be initialized. + It can be called multiple times in devinit. + +
+ + + + + + + + + + + + + + + + + Code in compliance. + + + Not currently supported. + + + Not currently supported. + + + + + + + + + + + + Invoke a dipslay class method. + +
+ + This opcode executes a display class method. + See the following documents for information about display methods: + + + + \\hw\nv5x\class\mfs\class\disp\dispClass_01.mfs, + + + \\hw\nv5x\doc\nv50\iso\specifications\display\display_software_interface.doc, + + + \\hw\nv5x\doc\nv50\iso\specifications\display\display_driver_vbios_switching.doc + + + + This opcode is usually not used and is never included in scripts visible to the resman. + + + This opcode is called INIT_METHOD_507D in the EFI source code, but plans are to update that. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code not present. Should remain that way for now. + + + Code in compliance, but name of opcode incorrect. + + + + + + + + + + Invoke a dipslay class method using a data value from a passed in data buffer. + +
+ + This opcode executes a display class method. + See the following documents for information about display methods: + + + + \\hw\nv5x\class\mfs\class\disp\dispClass_01.mfs, + + + \\hw\nv5x\doc\nv50\iso\specifications\display\display_software_interface.doc, + + + \\hw\nv5x\doc\nv50\iso\specifications\display\display_driver_vbios_switching.doc + + + + This opcode is usually not used and is never included in scripts visible to the resman. + + + This opcode is called INIT_METHOD_507D_UNCOUPLED in the EFI source code, but plans are to update that. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code not present. Should remain that way for now. + + + Code in compliance, but name of opcode incorrect. + + + + + + + + + + Invoke a dipslay class method using a data value a passed in data stream. + +
+ + This opcode executes a display class method. + See the following documents for information about display methods: + + + + \\hw\nv5x\class\mfs\class\disp\dispClass_01.mfs, + + + \\hw\nv5x\doc\nv50\iso\specifications\display\display_software_interface.doc, + + + \\hw\nv5x\doc\nv50\iso\specifications\display\display_driver_vbios_switching.doc + + + + This opcode is usually not used and is never included in scripts visible to the resman. + + + The devinit engine will extract 32-bits from the stream. + The bits must be extracted even when the condition code state prevents the final value from being written back to the register. + + + This opcode is called INIT_METHOD_507D_STREAM in the EFI source code, but plans are to update that. + +
+ + + + + + + + + + + + + Code in compliance. + + + Code not present. Should remain that way for now. + + + Code in compliance, but name of opcode incorrect. + + + + + + + + + Restrict further processing based on a generic condition with a condition ID. + +
+ + This opcode causes the indicated condition to be tested. + If the condition is met the condition flag is unmodified. + If the condition is not met the condition flag is set to the skip operations state. + + + Condition ID: + CONDITION_ID_INT_DP = 0x00: condition is met if it is internal DP(i.e. requires sequencer control). + CONDITION_ID_USE_SPPLL0 = 0x01: condition is met if DP uses SPPLL0. + CONDITION_ID_USE_SPPLL1 = 0x02: condition is met if DP uses SPPLL1. + (0x3 and 0x4 are reserved for future expansion if we are going to have more SPPLLs.) + CONDITION_ID_ASSR_SUPPORT = 0x05: condition is met if DP panel supports ASSR(eDP). + CONDITION_ID_FINISH_VCO_CAL_IN_DEVINIT = 0x06: condition is met if the final steps of TMDS VCO calibration should be handled in the devinit script. + CONDITION_ID_NO_PANEL_SEQ_DELAYS = 0x07: This condition is true when the panel is in self refresh or if RM has setup a flag to capture supervisor script + or for other modes for which we are sure that the panel will not be powered down and doesnt need sequencing. When this condition is true, we run + the IED Script with no delays (sor_lvds_Init_Sequencer_nd) and if this condition is false, we run the normal script which has delays (sor_lvds_Init_Sequencer). + CONDITION_INVALID = 0xFF: we could override condition ID to _INVALID, in effect to skip this condition. + + + Condition length field is added in an effort to make smooth synchronization between vbios and driver changes. + When new condition ID is added, if code(vbios/driver/efi) doesn't support it yet, it should skip + condition_length bytes, and continue to process the next devinit token. + + +
+ + + + + + + + + + + + + + + Code in compliance. + + + Code not present. + + + Code not present. + + + + + + + + + + Resets CR register bit based on OUTDEV, e.g. resets bit0 if it is SOR0. + +
+ + This opcode resets bitx if it is OUTDEVx. + +
+ + + + + + + + + + + + + + + Code in compliance. + + + Code not present. + + + Code not present. + + + + + + + + + Sets CR register bit based on OUTDEV, e.g. sets bit0 if it is SOR0. + +
+ + This opcode sets bitx if it is OUTDEVx. + +
+ + + + + + + + + + + + + + + Code in compliance. + + + Code not present. + + + Code not present. + + + + + + + + + Attempts to obtain a PMU hardware mutex + +
+ + This opcode attempts to obtain a hardware mutex specified by the PMU architecture. The code will make + multiple attempts over several milliseconds. Number and time to be determined through testing. + + + Mutex values 1-3 are reserved for vbios. When run by vbios, this opcode will use a value of 2. + Operations will be skipped if the mutex is currently held by vbios. + + + When run by RM, the normal process of obtaining a mutex value through the NEXT_AVAIL_MUTEX_ID register + should be followed. + + + Be careful when using this opcode within a condition block. Operations will be skipped if the condition + flag is set, but this opcode can also set the condition flag if the mutex is not obtained. + +
+ + + + + + + + + + + + + + + Code not present. + + + Code not present. + + + Code not present. + + + + + + + + + Releases a PMU hardware mutex + +
+ + This opcode releases a hardware mutex obtained with INIT_OBTAIN_HW_MUTEX. The write will only be + performed if the mutex is held by the party executing the command (VBIOS or RM). + + + As this opcode honors the condition flag which is set by INIT_OBTAIN_HW_MUTEX, it should be followed by + INIT_RESUME in most cases. + +
+ + + + + + + + + + + + + + + Code not present. + + + Code not present. + + + Code not present. + + + + + + + + + Executes a specified PMU routine + +
+ + This opcode executes a PMU routine through the PBI (post-box interface). It can be modeled by this + sequence: + + + INIT_HW_OBTAIN_MUTEX pbi + INIT_ZM_REG pbi_data_in, param + INIT_ZM_REG pbi_ctrl, exec_routine + INIT_HW_RELEASE_MUTEX pbi + INIT_RESUME + + + The exception to this sequence is that this opcode honors the condition flag and does not affect it. + +
+ + + + + + + + + + + + + + + Code not present. + + + Code not present. + + + Code not present. + + + + + + + + + + Check the condition of a register over 16-bit I2C port + +
+ + This opcode performs the same functions as INIT_I2C_CONDITION, but for I2C devices that use 16-bit register addressing. + +
+ + + + + + + + + + + + + + + Not audited. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + Set NVVDD depending on the VDT entry + +
+ + This opcode invokes the PMU to set the NVVDD depending on the VDT table entry that is passed. + +
+ + + + + + + + + + + + + + + + Audited. + + + Not implemented. + + + Not implemented. + + + + + + + + + + No operation + +
+ + This opcode does nothing and used to increment the current script offset. + This opcode is primarily used to replace existing opcodes in devinit WAR infrastructure. + +
+ + + + + + + + + + + + + + + + + + Code in compliance + + + Not implemented + + + Not implemented. + + + Not implemented. + + + + + + + + Restrict further processing based on a register condition. + +
+ + This opcode reads the specified priveleged register. It then performs a logical AND operation on the read value using the AND MASK provided. It then compares this result to the value field. + If the value field matches the result, condition flag is unmodified. + If the value field doesn't match the result, condition flag is set to skip operations state. + +
+ + + + + + + + + + + + + + + + + + Code in compliance + + + Not implemented + + + Not implemented. + + + Not implemented. + + + + + + + + + + + Reduce the privilege level of the EXT transaction. + +
+ + This opcode is used to reduce the privilege level to 0. Please note that we only lower the PRIV level only for the transaction and not the actual priv level. + This opcode is primarily used in the devinit WAR binary before OVERWRITE and INSERT operations. + +
+ + + + + + + + + + + + + + + + + + Code in compliance + + + Not implemented + + + Not implemented. + + + Not implemented. + + + + + + + + Restore the privilege level of the EXT transaction + +
+ + This opcode is used to restore the privilege level to 3. Please note that we only restore the PRIV level only for the transaction and not the actual priv level. + This opcode is primarily used in the devinit WAR binary after OVERWRITE and INSERT operations. + +
+ + + + + + + + + + + + + + + + + + Code in compliance + + + Not implemented + + + Not implemented. + + + Not implemented. + + + + + + + Write a set of privileged registers repeatedly with different sequences of data values. + +
+ + This opcode writes different blocks of values into a set of privileged registers. This opcode provides scope of space optimizations + where a particular set of registers needs to be written with different set of values multiple times. + +
+ + + + + + + + + + + + + + + + + + + Code in compliance + + + Not implemented + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + Calculates and sets up TSOSC temperature coefficients. + +
+ + Temperature Sensing OSCillators (TSOSCs) require various coefficients for calibration. + This opcode reads calibration values from fuses as parameters, calculates the needed coefficients, and programs them. + +
+ + + + + + + + + + + + + + + + + + + + Code in compliance + + + Not implemented + + + Not implemented. + + + Not implemented. + + + + + + + Poll a privileged register until a masked value compares correctly, only if surrounding INIT_CONDITION is true. + +
+ + This opcode does the same routine as INIT_POLL_NV after checking for prior register condition in INIT_CONDITION, skips the polling process if the prior condition is not met. + +
+ + + + + + + + + + + + + + + + + + + + Code in compliance + + + Code in compliance + + + Not implemented. + + + Not implemented. + + + + If INIT_CONDITION just before INIT_POLL_NV_COND is met, this example will poll using condition code 1, and will not take more than 200 milliseconds before terminating, else will skip the polling process. + + BYTE INIT_POLL_NV_COND + BYTE 03h ;Condition code to poll for + BYTE 02h ;200 milliseconds max before continuing + + + + + + + + + Write a set of new word values to a set of I2C registers (zero mask). + +
+ + This opcode causes a given number of registers in a device to be written with specified values through a given I2C port. + + + The designation 'alternating' refers to this opcode's ability to simulate the mode of some I2C devices which allows them to write several non-adjacent I2C registers in a single I2C message by concatenating {address, data} pairs (normally described as 'alternating write mode'). + This opcode simulates that ability by breaking the {address, data} pairs into separate I2C messages, with a full stop/start inserted between each pair. + + + The I2C Port Index uses the same equates normally used in the VBIOS, i.e. I2C_A, I2C_B, to indicate the first and second logical I2C ports, respectively. + Alternatively, USE_DCB_I2C (0xFF) will force the usage of the logical I2C port index associated with the currently active display for programming external devices, a per-head value. + Internally, the VBIOS uses the DCB index scratch register field for the current head to find the I2C port specified by the DCB entry. + This assumes: + + + + 1. When this opcode is called, the VBIOS is NOT in broadcast mode + + + 2. The DCB index for the head the VBIOS is on is either a valid DCB index or EMPTY_HEAD + + + 3. If the DCB index is EMPTY_HEAD the opcode processing will be skipped (essentially, making this opcode a no-op) + + + + The primary and secondary ports are specified in the DCB I2C Control Block. + + + USE_PRIMARY_I2C uses the primary port and USE_SECONDARY_I2C uses the secondary port as specified in the DCB I2C Control Block. + + + The device address specifies the I2C address of the device to initialize via the selected I2C port (e.g. SI178 uses 0x70, CX871 uses 0x88). + + + The devinit engine must not generate any I2C traffic when the condition code specifies that operations should be skipped. + +
+ + + + + + + + + + + + + + + + + + + Code in compliance + + + Not implemented. + + + Not implemented. + + + Not implemented. + + + + + + + + + + + + + + + Check the condition of a register with 16bit data over I2C port + +
+ + This opcode causes the indicated I2C condition to be tested. + If the condition is met the condition flag is unmodified. + If the condition is not met or an I2C read failure occurs the condition flag is set to the skip operations state. + + + The I2C Port Index uses the same equates normally used in the VBIOS, i.e. I2C_A, I2C_B, to indicate the first and second logical I2C ports, respectively. + Alternatively, USE_DCB_I2C (0xFF) will force the usage of the logical I2C port index associated with the currently active display for programming external devices, a per-head value. + Internally, the VBIOS uses the DCB index scratch register field for the current head to find the I2C port specified by the DCB entry. + This assumes: + + + + 1. When this opcode is called, the VBIOS is NOT in broadcast mode + + + 2. The DCB index for the head the VBIOS is on is either a valid DCB index or EMPTY_HEAD + + + 3. If the DCB index is EMPTY_HEAD the opcode processing will be skipped (essentially, making this opcode a no-op) + + + + The device address specifies the I2C address of the device to initialize via the selected I2C port (e.g. SI178 uses 0x70, CX871 uses 0x88). + +
+ + + + + + + + + + + + + + + + + + + + Code in compliance + + + Not implemented. + + + Not implemented. + + + Not implemented. + + + + + + + + + + diff --git a/Devinit/devinit.xsl b/Devinit/devinit.xsl new file mode 100644 index 0000000..d1f4777 --- /dev/null +++ b/Devinit/devinit.xsl @@ -0,0 +1,384 @@ + + + + + + + NVIDIA VGA BIOS Device Initialization (devinit) Script Opcode Specification + + + +
NVIDIA VGA BIOS Device Initialization (devinit) Script Opcode Specification
+ + + +
Opcode Index
+ +
+
+
+ + Opcode + + + Description + +
+ + + + + +
+
+ +
Numeric Opcode Index
+ +
+
+
+ + Numeric + + + Opcode + +
+ + + + + +
+
+ + + + + + + + + + +
+
+ +
+ + + + +
+ +
+ + + + +
+ +
+ + + + + + +
+ + + # + + + + + + +
+ + + + + + + +
+ + + + + + # + + + +
+ + + + + + +
+
+ + + + opcode-deprecated + + + opcode-new + + + opcode + + + +
+ + () +
+ + + + + + + + + + + + +
Audits
+
+ +
+ + +
+
+ + + + + +
+ +
+ + + + +
Format
+
+
+ + +
+ Deprecated +
+ + +
+ New +
+ + +
+ BYTE + + ; Opcode +
+ +
+
+ + + + + + 0 + + + 1 + + + <N-1> + + + + + + +
+ + + BYTE + BYTE + WORD + WORD + DWORD + <Unknown size> + + + + + u008 + s008 + u016 + s016 + u032 + unknown + + + + + + ; + +
+ + + + +
Details
+ +
+ +
+
+ Deprecated + + + Yes + No + + +
+
+ Condition Flag + + + Set to SKIP operations on failure + Reset to allow operations to be performed + Operations shall not performed when set to SKIP + Only final register write not performed when set to SKIP + Only final writes to each register are not performed when set to SKIP + Only final read/modify/write not performed when set to SKIP + Inverted + Ignored + <UNKNOWN> + + +
+
+ + + + + + + +
+ + + + + +
+ +
+ + + + +
+ +
+ + + +
+ +
+ + + + +
+ +
+ + + + +
+ TODO: +
+ + + +
+ +
+ + + +
Example
+
+ +
+ +
+
+ + + +
+ +
+ + + +
+ +
+ + + + +
History
+
+
+ +
+
+ + + +
+ + + + Yes + No + Modified + Resman only + VBIOS only + <UNKNOWN> + + +
+ + + +
+ - + : + +
+ + + diff --git a/Display-Class-Methods/README.txt b/Display-Class-Methods/README.txt new file mode 100644 index 0000000..5400006 --- /dev/null +++ b/Display-Class-Methods/README.txt @@ -0,0 +1,142 @@ +EVO CLASSES + +The NVIDIA "EVO" Display Engine was introduced in NV50, and has been +incrementally updated in GPUs since then. + +EVO consists of several channels: + + "core": This channel is used to perform modesets, as well as things + such as manage the LUT, and cursor properties (other than + position). It has GPU scope. + "base": This channel is intended to be used for OpenGL SwapBuffers + flipping. There is one base channel per head. + "overlay": This channel is intended to be used for flipping the + overlay. There is one overlay channel per head. + "overlay immediate": This channel is intended to be used to position + the overlay within the raster of the head. There is one + overlay immediate channel per head. Originally, it was + conceived that a display driver would position the overlay + in response to a window move, using the "overlay immediate" + channel, and a video driver would flip buffers using the + overlay channel. + "cursor": This channel is used to position the cursor. There is + one cursor channel per head. The cursor format and buffer + is specified through the core channel. It was originally + conceived that the management of cursor would be distributed + between the core and cursor channels in the same way that + overlay management is distributed between overlay and overlay + immediate channels. The cursor channel allows low-latency + cursor position updates, asynchronously to the core channel. + +There is a per-channel header file that defines the method interface to +each channel. + +There are both an EVO "class name" and a software class number that are +used to describe the combination of channel versions used together. + +The table below describes which EVO class name is used with which GPU, +and which channel header files are used with that EVO class. + +__________________________________________________________________________ + +Class Name: DISP010X +Software Class Number: 5070 +Cursor Channel: cl507a.h +Overlay Immediate Channel: cl507b.h +Base Channel: cl507c.h +Core Channel: cl507d.h +Overlay Channel: cl507e.h +GPUs: nv50 +__________________________________________________________________________ + +Class Name: DISP011X +Software Class Number: 8270 +Cursor Channel: cl827a.h +Overlay Immediate Channel: cl827b.h +Base Channel: cl827c.h +Core Channel: cl827d.h +Overlay Channel: cl827e.h +GPUs: g84, g86, g92 +__________________________________________________________________________ + +Class Name: DISP012X +Software Class Number: 8370 +Cursor Channel: cl827a.h +Overlay Immediate Channel: cl827b.h +Base Channel: cl837c.h +Core Channel: cl837d.h +Overlay Channel: cl837e.h +GPUs: gt200 +__________________________________________________________________________ + +Class Name: DISP014X +Software Class Number: 8870 +Cursor Channel: cl827a.h +Overlay Immediate Channel: cl827b.h +Base Channel: cl837c.h +Core Channel: cl887d.h +Overlay Channel: cl837e.h +GPUs: g94, g96, g98, mcp7x +__________________________________________________________________________ + +Class Name: DISP015X +Software Class Number: 8570 +Cursor Channel: cl857a.h +Overlay Immediate Channel: cl857b.h +Base Channel: cl857c.h +Core Channel: cl857d.h +Overlay Channel: cl857e.h +GPUs: gt215, gt216, gt218, mcp89 + gf100, gf104, gf106, gf114, gf116, gf108 +__________________________________________________________________________ + +Class Name: DISP020X +Software Class Number: 9070 +Cursor Channel: cl907a.h +Overlay Immediate Channel: cl907b.h +Base Channel: cl907c.h +Core Channel: cl907d.h +Overlay Channel: cl907e.h +GPUs: gf119 +__________________________________________________________________________ + +Class Name: DISP021X +Software Class Number: 9170 +Cursor Channel: cl917a.h +Overlay Immediate Channel: cl917b.h +Base Channel: cl917c.h +Core Channel: cl917d.h +Overlay Channel: cl917e.h +GPUs: gk104, gk106, gk107 +__________________________________________________________________________ + +Class Name: DISP022X +Software Class Number: 9270 +Cursor Channel: cl917a.h +Overlay Immediate Channel: cl917b.h +Base Channel: cl927c.h +Core Channel: cl927d.h +Overlay Channel: cl917e.h +GPUs: gk110, gk208 +__________________________________________________________________________ + +Class Name: DISP024X +Software Class Number: 9470 +Cursor Channel: cl917a.h +Overlay Immediate Channel: cl917b.h +Base Channel: cl927c.h +Core Channel: cl947d.h +Overlay Channel: cl917e.h +GPUs: gm107 +__________________________________________________________________________ + +Class Name: DISP025X +Software Class Number: 9570 +Cursor Channel: cl917a.h +Overlay Immediate Channel: cl917b.h +Base Channel: cl927c.h +Core Channel: cl957d.h +Overlay Channel: cl917e.h +GPUs: gm204 +__________________________________________________________________________ + diff --git a/Display-Class-Methods/cl507a.h b/Display-Class-Methods/cl507a.h new file mode 100644 index 0000000..d2c38f4 --- /dev/null +++ b/Display-Class-Methods/cl507a.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507a_h_ +#define _cl507a_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV507A_CURSOR_CHANNEL_PIO (0x0000507A) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetCursorHotSpotPointOut; // 0x00000084 - 0x00000087 + NvV32 Reserved02[0x3DE]; +} Nv50DispCursorControlPio; + +#define NV507A_FREE (0x00000008) +#define NV507A_FREE_COUNT 5:0 +#define NV507A_UPDATE (0x00000080) +#define NV507A_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV507A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV507A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT (0x00000084) +#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NV507A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl507a_h + diff --git a/Display-Class-Methods/cl507b.h b/Display-Class-Methods/cl507b.h new file mode 100644 index 0000000..460bc27 --- /dev/null +++ b/Display-Class-Methods/cl507b.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507b_h_ +#define _cl507b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV507B_OVERLAY_IMM_CHANNEL_PIO (0x0000507B) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetPointOut; // 0x00000084 - 0x00000087 + NvV32 AwakenOnceFlippedTo; // 0x00000088 - 0x0000008B + NvV32 Reserved02[0x3DD]; +} Nv50DispOverlayImmControlPio; + +#define NV507B_FREE (0x00000008) +#define NV507B_FREE_COUNT 5:0 +#define NV507B_UPDATE (0x00000080) +#define NV507B_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV507B_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV507B_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV507B_SET_POINT_OUT (0x00000084) +#define NV507B_SET_POINT_OUT_X 15:0 +#define NV507B_SET_POINT_OUT_Y 31:16 +#define NV507B_AWAKEN_ONCE_FLIPPED_TO (0x00000088) +#define NV507B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT 11:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl507b_h + diff --git a/Display-Class-Methods/cl507c.h b/Display-Class-Methods/cl507c.h new file mode 100644 index 0000000..db9aba5 --- /dev/null +++ b/Display-Class-Methods/cl507c.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507c_h_ +#define _cl507c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV507C_BASE_CHANNEL_DMA (0x0000507C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +// dma opcode instructions +#define NV507C_DMA 0x00000000 +#define NV507C_DMA_OPCODE 31:29 +#define NV507C_DMA_OPCODE_METHOD 0x00000000 +#define NV507C_DMA_OPCODE_JUMP 0x00000001 +#define NV507C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV507C_DMA_OPCODE 31:29 +#define NV507C_DMA_OPCODE_METHOD 0x00000000 +#define NV507C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV507C_DMA_METHOD_COUNT 27:18 +#define NV507C_DMA_METHOD_OFFSET 11:2 +#define NV507C_DMA_DATA 31:0 +#define NV507C_DMA_NOP 0x00000000 +#define NV507C_DMA_OPCODE 31:29 +#define NV507C_DMA_OPCODE_JUMP 0x00000001 +#define NV507C_DMA_JUMP_OFFSET 11:2 +#define NV507C_DMA_OPCODE 31:29 +#define NV507C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV507C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV507C_PUT (0x00000000) +#define NV507C_PUT_PTR 11:2 +#define NV507C_GET (0x00000004) +#define NV507C_GET_PTR 11:2 +#define NV507C_GET_SCANLINE (0x00000010) +#define NV507C_GET_SCANLINE_LINE 15:0 +#define NV507C_UPDATE (0x00000080) +#define NV507C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV507C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV507C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV507C_SET_PRESENT_CONTROL (0x00000084) +#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV507C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV507C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV507C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV507C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV507C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV507C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV507C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV507C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV507C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV507C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV507C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV507C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV507C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV507C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV507C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV507C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV507C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV507C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV507C_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV507C_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV507C_SET_BASE_LUT_LO (0x000000E0) +#define NV507C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV507C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV507C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV507C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000003) +#define NV507C_SET_BASE_LUT_LO_MODE 29:29 +#define NV507C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV507C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV507C_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV507C_SET_BASE_LUT_HI (0x000000E4) +#define NV507C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV507C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV507C_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV507C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV507C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV507C_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV507C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV507C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV507C_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV507C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV507C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV507C_SET_PROCESSING (0x00000110) +#define NV507C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV507C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV507C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV507C_SET_CONVERSION (0x00000114) +#define NV507C_SET_CONVERSION_GAIN 15:0 +#define NV507C_SET_CONVERSION_OFS 31:16 +#define NV507C_SET_SPARE (0x000007BC) +#define NV507C_SET_SPARE_UNUSED 31:0 +#define NV507C_SET_SPARE_NOOP(b) (0x000007C0 + (b)*0x00000004) +#define NV507C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV507C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004) +#define NV507C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV507C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020) +#define NV507C_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV507C_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV507C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV507C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV507C_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV507C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV507C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020) +#define NV507C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV507C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV507C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV507C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV507C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV507C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV507C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) +#define NV507C_SURFACE_SET_PARAMS_KIND 22:16 +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_PITCH (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D) +#define NV507C_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E) +#define NV507C_SURFACE_SET_PARAMS_KIND_FROM_PTE (0x0000007F) +#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE 24:24 +#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000) +#define NV507C_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl507c_h + diff --git a/Display-Class-Methods/cl507d.h b/Display-Class-Methods/cl507d.h new file mode 100644 index 0000000..675b9e4 --- /dev/null +++ b/Display-Class-Methods/cl507d.h @@ -0,0 +1,676 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507d_h_ +#define _cl507d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV507D_CORE_CHANNEL_DMA (0x0000507D) + +#define NV_DISP_CORE_NOTIFIER_1 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_SIZEOF 0x00000054 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_R0 15:1 +#define NV_DISP_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP 29:16 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO 2:2 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_R0 3:3 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA 20:20 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS 21:21 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_1_R1 31:22 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_2 0x00000002 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_2_R2 31:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_3 0x00000003 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_3_R3 31:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_4 0x00000004 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_4_R4 31:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5 0x00000005 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE 3:3 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6 0x00000006 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE 3:3 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7 0x00000007 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE 3:3 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8 0x00000008 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18 2:2 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24 3:3 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A 4:4 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B 5:5 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS 6:6 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS 7:7 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI 9:9 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9 0x00000009 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18 2:2 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24 3:3 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A 4:4 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B 5:5 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS 6:6 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS 7:7 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI 9:9 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10 0x0000000A +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11 0x0000000B +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12 0x0000000C +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC 1:1 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13 0x0000000D +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0 31:2 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14 0x0000000E +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444 14:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1 15:15 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422 30:16 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2 31:31 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15 0x0000000F +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444 14:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3 15:15 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422 30:16 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4 31:31 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16 0x00000010 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444 14:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5 15:15 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422 30:16 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6 31:31 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17 0x00000011 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE 0:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE 0x00000000 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE 0x00000001 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0 31:2 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18 0x00000012 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444 14:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1 15:15 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422 30:16 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2 31:31 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19 0x00000013 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444 14:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3 15:15 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422 30:16 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4 31:31 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20 0x00000014 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444 14:0 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5 15:15 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422 30:16 +#define NV_DISP_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6 31:31 + + +// dma opcode instructions +#define NV507D_DMA 0x00000000 +#define NV507D_DMA_OPCODE 31:29 +#define NV507D_DMA_OPCODE_METHOD 0x00000000 +#define NV507D_DMA_OPCODE_JUMP 0x00000001 +#define NV507D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV507D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV507D_DMA_OPCODE 31:29 +#define NV507D_DMA_OPCODE_METHOD 0x00000000 +#define NV507D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV507D_DMA_METHOD_COUNT 27:18 +#define NV507D_DMA_METHOD_OFFSET 11:2 +#define NV507D_DMA_DATA 31:0 +#define NV507D_DMA_NOP 0x00000000 +#define NV507D_DMA_OPCODE 31:29 +#define NV507D_DMA_OPCODE_JUMP 0x00000001 +#define NV507D_DMA_JUMP_OFFSET 11:2 +#define NV507D_DMA_OPCODE 31:29 +#define NV507D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV507D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV507D_PUT (0x00000000) +#define NV507D_PUT_PTR 11:2 +#define NV507D_GET (0x00000004) +#define NV507D_GET_PTR 11:2 +#define NV507D_UPDATE (0x00000080) +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1 8:8 +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_BASE1 9:9 +#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1 10:10 +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 11:11 +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV507D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV507D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV507D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV507D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV507D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV507D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV507D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV507D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV507D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV507D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV507D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV507D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV507D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV507D_GET_CAPABILITIES (0x0000008C) +#define NV507D_GET_CAPABILITIES_DUMMY 31:0 +#define NV507D_SET_SPARE (0x000003BC) +#define NV507D_SET_SPARE_UNUSED 31:0 +#define NV507D_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV507D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV507D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0x00000080) +#define NV507D_DAC_SET_CONTROL_OWNER 3:0 +#define NV507D_DAC_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV507D_DAC_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV507D_DAC_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV507D_DAC_SET_CONTROL_SUB_OWNER 5:4 +#define NV507D_DAC_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV507D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV507D_DAC_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV507D_DAC_SET_CONTROL_PROTOCOL 13:8 +#define NV507D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV507D_DAC_SET_CONTROL_PROTOCOL_CUSTOM (0x0000003F) +#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD 14:14 +#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE (0x00000000) +#define NV507D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE (0x00000001) +#define NV507D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0x00000080) +#define NV507D_DAC_SET_POLARITY_HSYNC 0:0 +#define NV507D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE (0x00000000) +#define NV507D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE (0x00000001) +#define NV507D_DAC_SET_POLARITY_VSYNC 1:1 +#define NV507D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE (0x00000000) +#define NV507D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE (0x00000001) +#define NV507D_DAC_SET_POLARITY_RESERVED 31:2 +#define NV507D_DAC_SET_ENCODE_QUALITY(a) (0x00000420 + (a)*0x00000080) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS 7:7 +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375 (0x00000000) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75 (0x00000001) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN 2:0 +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0 (0x00000000) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625 (0x00000001) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125 (0x00000002) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25 (0x00000003) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5 (0x00000004) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0 (0x00000005) +#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN 6:4 +#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0 (0x00000000) +#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625 (0x00000001) +#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125 (0x00000002) +#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25 (0x00000003) +#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5 (0x00000004) +#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0 (0x00000005) +#define NV507D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH 15:8 +#define NV507D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH 23:16 +#define NV507D_DAC_SET_ENCODE_QUALITY_TINT 31:24 +#define NV507D_DAC_UPDATE_ENCODER_PRESET(a) (0x0000047C + (a)*0x00000080) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL 5:0 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM (0x0000003F) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT 6:6 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV (0x00000001) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R 7:7 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE (0x00000001) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G 8:8 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE (0x00000001) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B 9:9 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE (0x00000001) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH 12:10 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358 (0x00000001) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358 (0x00000002) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443 (0x00000003) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443 (0x00000004) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW 13:13 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6 (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4 (0x00000001) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER 15:15 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE (0x00000001) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER 16:16 +#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW (0x00000000) +#define NV507D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE (0x00000001) + +#define NV507D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040) +#define NV507D_SOR_SET_CONTROL_OWNER 3:0 +#define NV507D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV507D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV507D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV507D_SOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV507D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV507D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV507D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV507D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV507D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007) +#define NV507D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) + +#define NV507D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040) +#define NV507D_PIOR_SET_CONTROL_OWNER 3:0 +#define NV507D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV507D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV507D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV507D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV507D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV507D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) + +#define NV507D_HEAD_SET_PRESENT_CONTROL(a) (0x00000800 + (a)*0x00000400) +#define NV507D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV507D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV507D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV507D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0x00000400) +#define NV507D_HEAD_SET_PIXEL_CLOCK_FREQUENCY 21:0 +#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE 23:22 +#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25 (0x00000000) +#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28 (0x00000001) +#define NV507D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM (0x00000002) +#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001 24:24 +#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE (0x00000000) +#define NV507D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE (0x00000001) +#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER 25:25 +#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE (0x00000000) +#define NV507D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE (0x00000001) +#define NV507D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0x00000400) +#define NV507D_HEAD_SET_CONTROL_STRUCTURE 2:1 +#define NV507D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV507D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV507D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0x00000400) +#define NV507D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV507D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV507D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV507D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV507D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV507D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV507D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV507D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV507D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV507D_HEAD_SET_RASTER_BLANK_START(a) (0x00000820 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV507D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV507D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000824 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV507D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI(a) (0x00000828 + (a)*0x00000400) +#define NV507D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION 11:0 +#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000082C + (a)*0x00000400) +#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV507D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV507D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400) +#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV507D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV507D_HEAD_SET_BASE_LUT_LO_MODE 30:30 +#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV507D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV507D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV507D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400) +#define NV507D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV507D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000848 + (a)*0x00000400) +#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV507D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV507D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV507D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000084C + (a)*0x00000400) +#define NV507D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV507D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004) +#define NV507D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV507D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400) +#define NV507D_HEAD_SET_SIZE_WIDTH 14:0 +#define NV507D_HEAD_SET_SIZE_HEIGHT 30:16 +#define NV507D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV507D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV507D_HEAD_SET_STORAGE_PITCH 17:8 +#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV507D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV507D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400) +#define NV507D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV507D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV507D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV507D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV507D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV507D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV507D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV507D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV507D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV507D_HEAD_SET_PARAMS_KIND 22:16 +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_PITCH (0x00000000) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D) +#define NV507D_HEAD_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E) +#define NV507D_HEAD_SET_PARAMS_KIND_FROM_PTE (0x0000007F) +#define NV507D_HEAD_SET_PARAMS_PART_STRIDE 24:24 +#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000) +#define NV507D_HEAD_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001) +#define NV507D_HEAD_SET_CONTEXT_DMA_ISO(a) (0x00000874 + (a)*0x00000400) +#define NV507D_HEAD_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV507D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400) +#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV507D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4 +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV507D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003) +#define NV507D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400) +#define NV507D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV507D_HEAD_SET_DITHER_CONTROL(a) (0x000008A0 + (a)*0x00000400) +#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV507D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV507D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV507D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV507D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV507D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x000008A4 + (a)*0x00000400) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV507D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV507D_HEAD_SET_PROCAMP(a) (0x000008A8 + (a)*0x00000400) +#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV507D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV507D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV507D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV507D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV507D_HEAD_SET_PROCAMP_TRANSITION 4:3 +#define NV507D_HEAD_SET_PROCAMP_TRANSITION_HARD (0x00000000) +#define NV507D_HEAD_SET_PROCAMP_TRANSITION_NTSC (0x00000001) +#define NV507D_HEAD_SET_PROCAMP_TRANSITION_PAL (0x00000002) +#define NV507D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004) +#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV507D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000008C8 + (a)*0x00000400) +#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000008D4 + (a)*0x00000400) +#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV507D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000008D8 + (a)*0x00000400) +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000008DC + (a)*0x00000400) +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV507D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x00000900 + (a)*0x00000400) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV507D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x00000904 + (a)*0x00000400) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV507D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV507D_HEAD_SET_SPARE(a) (0x00000BBC + (a)*0x00000400) +#define NV507D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV507D_HEAD_SET_SPARE_NOOP(a,b) (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004) +#define NV507D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl507d_h + diff --git a/Display-Class-Methods/cl507e.h b/Display-Class-Methods/cl507e.h new file mode 100644 index 0000000..1827276 --- /dev/null +++ b/Display-Class-Methods/cl507e.h @@ -0,0 +1,173 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl507e_h_ +#define _cl507e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV507E_OVERLAY_CHANNEL_DMA (0x0000507E) + +#define NV_DISP_OVERLAY_NOTIFIER_1 0x00000000 +#define NV_DISP_OVERLAY_NOTIFIER_1_SIZEOF 0x00000008 +#define NV_DISP_OVERLAY_NOTIFIER_1__0 0x00000000 +#define NV_DISP_OVERLAY_NOTIFIER_1__0_PRESENT_COUNT 15:0 +#define NV_DISP_OVERLAY_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_OVERLAY_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 +#define NV_DISP_OVERLAY_NOTIFIER_1__1 0x00000001 +#define NV_DISP_OVERLAY_NOTIFIER_1__1_PRESENT_START_TIME 31:0 + + +// dma opcode instructions +#define NV507E_DMA 0x00000000 +#define NV507E_DMA_OPCODE 31:29 +#define NV507E_DMA_OPCODE_METHOD 0x00000000 +#define NV507E_DMA_OPCODE_JUMP 0x00000001 +#define NV507E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV507E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV507E_DMA_OPCODE 31:29 +#define NV507E_DMA_OPCODE_METHOD 0x00000000 +#define NV507E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV507E_DMA_METHOD_COUNT 27:18 +#define NV507E_DMA_METHOD_OFFSET 11:2 +#define NV507E_DMA_DATA 31:0 +#define NV507E_DMA_NOP 0x00000000 +#define NV507E_DMA_OPCODE 31:29 +#define NV507E_DMA_OPCODE_JUMP 0x00000001 +#define NV507E_DMA_JUMP_OFFSET 11:2 +#define NV507E_DMA_OPCODE 31:29 +#define NV507E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV507E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV507E_PUT (0x00000000) +#define NV507E_PUT_PTR 11:2 +#define NV507E_GET (0x00000004) +#define NV507E_GET_PTR 11:2 +#define NV507E_UPDATE (0x00000080) +#define NV507E_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV507E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV507E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV507E_SET_PRESENT_CONTROL (0x00000084) +#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV507E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV507E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV507E_SET_SEMAPHORE_ACQUIRE (0x00000088) +#define NV507E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV507E_SET_SEMAPHORE_RELEASE (0x0000008C) +#define NV507E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV507E_SET_SEMAPHORE_CONTROL (0x00000090) +#define NV507E_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV507E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV507E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV507E_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV507E_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV507E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV507E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV507E_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV507E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV507E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV507E_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV507E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV507E_SET_POINT_IN (0x000000E0) +#define NV507E_SET_POINT_IN_X 14:0 +#define NV507E_SET_POINT_IN_Y 30:16 +#define NV507E_SET_SIZE_IN (0x000000E4) +#define NV507E_SET_SIZE_IN_WIDTH 14:0 +#define NV507E_SET_SIZE_IN_HEIGHT 30:16 +#define NV507E_SET_SIZE_OUT (0x000000E8) +#define NV507E_SET_SIZE_OUT_WIDTH 14:0 +#define NV507E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV507E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV507E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV507E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV507E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002) +#define NV507E_SET_KEY_COLOR (0x00000104) +#define NV507E_SET_KEY_COLOR_COLOR 31:0 +#define NV507E_SET_KEY_MASK (0x00000108) +#define NV507E_SET_KEY_MASK_MASK 31:0 +#define NV507E_SET_TIMESTAMP_VALUE (0x00000120) +#define NV507E_SET_TIMESTAMP_VALUE_TIMESTAMP 31:0 +#define NV507E_SET_UPDATE_TIMESTAMP (0x00000124) +#define NV507E_SET_UPDATE_TIMESTAMP_TIMESTAMP 31:0 +#define NV507E_SET_SPARE (0x000007BC) +#define NV507E_SET_SPARE_UNUSED 31:0 +#define NV507E_SET_SPARE_NOOP(b) (0x000007C0 + (b)*0x00000004) +#define NV507E_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV507E_SURFACE_SET_OFFSET (0x00000800) +#define NV507E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV507E_SURFACE_SET_SIZE (0x00000808) +#define NV507E_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV507E_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV507E_SURFACE_SET_STORAGE (0x0000080C) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV507E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV507E_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV507E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV507E_SURFACE_SET_PARAMS (0x00000810) +#define NV507E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV507E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV507E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV507E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV507E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV507E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NV507E_SURFACE_SET_PARAMS_KIND 22:16 +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_PITCH (0x00000000) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2 (0x00000070) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_8BX2_BANKSWIZ (0x00000072) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1 (0x00000074) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_GENERIC_16BX1_BANKSWIZ (0x00000076) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4 (0x00000078) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8 (0x00000079) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS4_BANKSWIZ (0x0000007A) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C32_MS8_BANKSWIZ (0x0000007B) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS4 (0x0000007C) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C64_MS8 (0x0000007D) +#define NV507E_SURFACE_SET_PARAMS_KIND_KIND_C128_MS4 (0x0000007E) +#define NV507E_SURFACE_SET_PARAMS_KIND_FROM_PTE (0x0000007F) +#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE 24:24 +#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_256 (0x00000000) +#define NV507E_SURFACE_SET_PARAMS_PART_STRIDE_PARTSTRIDE_1024 (0x00000001) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl507e_h + diff --git a/Display-Class-Methods/cl827a.h b/Display-Class-Methods/cl827a.h new file mode 100644 index 0000000..bd10ceb --- /dev/null +++ b/Display-Class-Methods/cl827a.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl827a_h_ +#define _cl827a_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV827A_CURSOR_CHANNEL_PIO (0x0000827A) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetCursorHotSpotPointOut; // 0x00000084 - 0x00000087 + NvV32 Reserved02[0x3DE]; +} G82DispCursorControlPio; + +#define NV827A_FREE (0x00000008) +#define NV827A_FREE_COUNT 5:0 +#define NV827A_UPDATE (0x00000080) +#define NV827A_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV827A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV827A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT (0x00000084) +#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NV827A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl827a_h + diff --git a/Display-Class-Methods/cl827b.h b/Display-Class-Methods/cl827b.h new file mode 100644 index 0000000..f85bfc2 --- /dev/null +++ b/Display-Class-Methods/cl827b.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl827b_h_ +#define _cl827b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV827B_OVERLAY_IMM_CHANNEL_PIO (0x0000827B) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetPointOut; // 0x00000084 - 0x00000087 + NvV32 AwakenOnceFlippedTo; // 0x00000088 - 0x0000008B + NvV32 Reserved02[0x3DD]; +} G82DispOverlayImmControlPio; + +#define NV827B_FREE (0x00000008) +#define NV827B_FREE_COUNT 5:0 +#define NV827B_UPDATE (0x00000080) +#define NV827B_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV827B_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV827B_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV827B_SET_POINT_OUT (0x00000084) +#define NV827B_SET_POINT_OUT_X 15:0 +#define NV827B_SET_POINT_OUT_Y 31:16 +#define NV827B_AWAKEN_ONCE_FLIPPED_TO (0x00000088) +#define NV827B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT 11:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl827b_h + diff --git a/Display-Class-Methods/cl827c.h b/Display-Class-Methods/cl827c.h new file mode 100644 index 0000000..a92df84 --- /dev/null +++ b/Display-Class-Methods/cl827c.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl827c_h_ +#define _cl827c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV827C_BASE_CHANNEL_DMA (0x0000827C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +// dma opcode instructions +#define NV827C_DMA 0x00000000 +#define NV827C_DMA_OPCODE 31:29 +#define NV827C_DMA_OPCODE_METHOD 0x00000000 +#define NV827C_DMA_OPCODE_JUMP 0x00000001 +#define NV827C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV827C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV827C_DMA_OPCODE 31:29 +#define NV827C_DMA_OPCODE_METHOD 0x00000000 +#define NV827C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV827C_DMA_METHOD_COUNT 27:18 +#define NV827C_DMA_METHOD_OFFSET 11:2 +#define NV827C_DMA_DATA 31:0 +#define NV827C_DMA_NOP 0x00000000 +#define NV827C_DMA_OPCODE 31:29 +#define NV827C_DMA_OPCODE_JUMP 0x00000001 +#define NV827C_DMA_JUMP_OFFSET 11:2 +#define NV827C_DMA_OPCODE 31:29 +#define NV827C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV827C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV827C_PUT (0x00000000) +#define NV827C_PUT_PTR 11:2 +#define NV827C_GET (0x00000004) +#define NV827C_GET_PTR 11:2 +#define NV827C_GET_SCANLINE (0x00000010) +#define NV827C_GET_SCANLINE_LINE 15:0 +#define NV827C_UPDATE (0x00000080) +#define NV827C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV827C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV827C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV827C_SET_PRESENT_CONTROL (0x00000084) +#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV827C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV827C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV827C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV827C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV827C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV827C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV827C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV827C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV827C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV827C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV827C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV827C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV827C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV827C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV827C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV827C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV827C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV827C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV827C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV827C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV827C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV827C_SET_BASE_LUT_LO (0x000000E0) +#define NV827C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV827C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV827C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV827C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000003) +#define NV827C_SET_BASE_LUT_LO_MODE 29:29 +#define NV827C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV827C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV827C_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV827C_SET_BASE_LUT_HI (0x000000E4) +#define NV827C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV827C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV827C_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV827C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV827C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV827C_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV827C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV827C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV827C_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV827C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV827C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV827C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV827C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV827C_SET_PROCESSING (0x00000110) +#define NV827C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV827C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV827C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV827C_SET_CONVERSION (0x00000114) +#define NV827C_SET_CONVERSION_GAIN 15:0 +#define NV827C_SET_CONVERSION_OFS 31:16 +#define NV827C_SET_SPARE (0x000007BC) +#define NV827C_SET_SPARE_UNUSED 31:0 +#define NV827C_SET_SPARE_NOOP(b) (0x000007C0 + (b)*0x00000004) +#define NV827C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV827C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004) +#define NV827C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV827C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020) +#define NV827C_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV827C_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV827C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV827C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV827C_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV827C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV827C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020) +#define NV827C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV827C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV827C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV827C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV827C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV827C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV827C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV827C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV827C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) +#define NV827C_SURFACE_SET_PARAMS_RESERVED0 22:16 +#define NV827C_SURFACE_SET_PARAMS_RESERVED1 24:24 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl827c_h + diff --git a/Display-Class-Methods/cl827d.h b/Display-Class-Methods/cl827d.h new file mode 100644 index 0000000..7294769 --- /dev/null +++ b/Display-Class-Methods/cl827d.h @@ -0,0 +1,678 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl827d_h_ +#define _cl827d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV827D_CORE_CHANNEL_DMA (0x0000827D) + +#define NV827D_CORE_NOTIFIER_1 0x00000000 +#define NV827D_CORE_NOTIFIER_1_SIZEOF 0x00000054 +#define NV827D_CORE_NOTIFIER_1_COMPLETION_0 0x00000000 +#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0 +#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_R0 15:1 +#define NV827D_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP 29:16 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO 2:2 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_R0 3:3 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA 20:20 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS 21:21 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_1_R1 31:22 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_2 0x00000002 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_2_R2 31:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_3 0x00000003 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_3_R3 31:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_4 0x00000004 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_4_R4 31:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5 0x00000005 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE 3:3 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6 0x00000006 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE 3:3 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7 0x00000007 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE 3:3 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8 0x00000008 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18 2:2 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24 3:3 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A 4:4 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B 5:5 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS 6:6 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS 7:7 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI 9:9 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9 0x00000009 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18 2:2 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24 3:3 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A 4:4 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B 5:5 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS 6:6 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS 7:7 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI 9:9 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10 0x0000000A +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11 0x0000000B +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12 0x0000000C +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC 1:1 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13 0x0000000D +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0 31:2 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14 0x0000000E +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444 14:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1 15:15 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422 30:16 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2 31:31 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15 0x0000000F +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444 14:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3 15:15 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422 30:16 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4 31:31 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16 0x00000010 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444 14:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5 15:15 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422 30:16 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6 31:31 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17 0x00000011 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE 0:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE 0x00000000 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE 0x00000001 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0 31:2 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18 0x00000012 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444 14:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1 15:15 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422 30:16 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2 31:31 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19 0x00000013 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444 14:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3 15:15 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422 30:16 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4 31:31 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20 0x00000014 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444 14:0 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5 15:15 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422 30:16 +#define NV827D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6 31:31 + + +// dma opcode instructions +#define NV827D_DMA 0x00000000 +#define NV827D_DMA_OPCODE 31:29 +#define NV827D_DMA_OPCODE_METHOD 0x00000000 +#define NV827D_DMA_OPCODE_JUMP 0x00000001 +#define NV827D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV827D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV827D_DMA_OPCODE 31:29 +#define NV827D_DMA_OPCODE_METHOD 0x00000000 +#define NV827D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV827D_DMA_METHOD_COUNT 27:18 +#define NV827D_DMA_METHOD_OFFSET 11:2 +#define NV827D_DMA_DATA 31:0 +#define NV827D_DMA_NOP 0x00000000 +#define NV827D_DMA_OPCODE 31:29 +#define NV827D_DMA_OPCODE_JUMP 0x00000001 +#define NV827D_DMA_JUMP_OFFSET 11:2 +#define NV827D_DMA_OPCODE 31:29 +#define NV827D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV827D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV827D_PUT (0x00000000) +#define NV827D_PUT_PTR 11:2 +#define NV827D_GET (0x00000004) +#define NV827D_GET_PTR 11:2 +#define NV827D_UPDATE (0x00000080) +#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1 8:8 +#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV827D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV827D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV827D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV827D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV827D_UPDATE_INTERLOCK_WITH_BASE1 9:9 +#define NV827D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV827D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1 10:10 +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 11:11 +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV827D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV827D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV827D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV827D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV827D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV827D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV827D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV827D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV827D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV827D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV827D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV827D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV827D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV827D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV827D_GET_CAPABILITIES (0x0000008C) +#define NV827D_GET_CAPABILITIES_DUMMY 31:0 +#define NV827D_SET_SPARE (0x000003BC) +#define NV827D_SET_SPARE_UNUSED 31:0 +#define NV827D_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV827D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV827D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0x00000080) +#define NV827D_DAC_SET_CONTROL_OWNER 3:0 +#define NV827D_DAC_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV827D_DAC_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV827D_DAC_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV827D_DAC_SET_CONTROL_SUB_OWNER 5:4 +#define NV827D_DAC_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV827D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV827D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV827D_DAC_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV827D_DAC_SET_CONTROL_PROTOCOL 13:8 +#define NV827D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV827D_DAC_SET_CONTROL_PROTOCOL_CUSTOM (0x0000003F) +#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD 14:14 +#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE (0x00000000) +#define NV827D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE (0x00000001) +#define NV827D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0x00000080) +#define NV827D_DAC_SET_POLARITY_HSYNC 0:0 +#define NV827D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE (0x00000000) +#define NV827D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE (0x00000001) +#define NV827D_DAC_SET_POLARITY_VSYNC 1:1 +#define NV827D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE (0x00000000) +#define NV827D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE (0x00000001) +#define NV827D_DAC_SET_POLARITY_RESERVED 31:2 +#define NV827D_DAC_SET_ENCODE_QUALITY(a) (0x00000420 + (a)*0x00000080) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS 7:7 +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375 (0x00000000) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75 (0x00000001) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN 2:0 +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0 (0x00000000) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625 (0x00000001) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125 (0x00000002) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25 (0x00000003) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5 (0x00000004) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0 (0x00000005) +#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN 6:4 +#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0 (0x00000000) +#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625 (0x00000001) +#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125 (0x00000002) +#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25 (0x00000003) +#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5 (0x00000004) +#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0 (0x00000005) +#define NV827D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH 15:8 +#define NV827D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH 23:16 +#define NV827D_DAC_SET_ENCODE_QUALITY_TINT 31:24 +#define NV827D_DAC_UPDATE_ENCODER_PRESET(a) (0x0000047C + (a)*0x00000080) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL 5:0 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM (0x0000003F) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT 6:6 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV (0x00000001) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R 7:7 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE (0x00000001) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G 8:8 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE (0x00000001) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B 9:9 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE (0x00000001) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH 12:10 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358 (0x00000001) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358 (0x00000002) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443 (0x00000003) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443 (0x00000004) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW 13:13 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6 (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4 (0x00000001) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER 15:15 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE (0x00000001) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER 16:16 +#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW (0x00000000) +#define NV827D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE (0x00000001) + +#define NV827D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040) +#define NV827D_SOR_SET_CONTROL_OWNER 3:0 +#define NV827D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV827D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV827D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV827D_SOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV827D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV827D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV827D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV827D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV827D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV827D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV827D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003) +#define NV827D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004) +#define NV827D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV827D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007) +#define NV827D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV827D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV827D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV827D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) + +#define NV827D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040) +#define NV827D_PIOR_SET_CONTROL_OWNER 3:0 +#define NV827D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV827D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV827D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV827D_PIOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV827D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV827D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV827D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV827D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV827D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV827D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV827D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) + +#define NV827D_HEAD_SET_PRESENT_CONTROL(a) (0x00000800 + (a)*0x00000400) +#define NV827D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV827D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV827D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV827D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0x00000400) +#define NV827D_HEAD_SET_PIXEL_CLOCK_FREQUENCY 21:0 +#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE 23:22 +#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25 (0x00000000) +#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28 (0x00000001) +#define NV827D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM (0x00000002) +#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001 24:24 +#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE (0x00000000) +#define NV827D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE (0x00000001) +#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER 25:25 +#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE (0x00000000) +#define NV827D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE (0x00000001) +#define NV827D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0x00000400) +#define NV827D_HEAD_SET_CONTROL_STRUCTURE 2:1 +#define NV827D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV827D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV827D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0x00000400) +#define NV827D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV827D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV827D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV827D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0x00000400) +#define NV827D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV827D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV827D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0x00000400) +#define NV827D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV827D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV827D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0x00000400) +#define NV827D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV827D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV827D_HEAD_SET_RASTER_BLANK_START(a) (0x00000820 + (a)*0x00000400) +#define NV827D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV827D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV827D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000824 + (a)*0x00000400) +#define NV827D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV827D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV827D_HEAD_SET_RASTER_VERT_BLANK_DMI(a) (0x00000828 + (a)*0x00000400) +#define NV827D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION 11:0 +#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000082C + (a)*0x00000400) +#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV827D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV827D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400) +#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV827D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV827D_HEAD_SET_BASE_LUT_LO_MODE 30:30 +#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV827D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV827D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV827D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400) +#define NV827D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV827D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000848 + (a)*0x00000400) +#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV827D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV827D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV827D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000084C + (a)*0x00000400) +#define NV827D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV827D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400) +#define NV827D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV827D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004) +#define NV827D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV827D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400) +#define NV827D_HEAD_SET_SIZE_WIDTH 14:0 +#define NV827D_HEAD_SET_SIZE_HEIGHT 30:16 +#define NV827D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV827D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV827D_HEAD_SET_STORAGE_PITCH 17:8 +#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV827D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV827D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400) +#define NV827D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV827D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV827D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV827D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV827D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV827D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV827D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV827D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV827D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV827D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV827D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV827D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV827D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV827D_HEAD_SET_PARAMS_RESERVED0 22:16 +#define NV827D_HEAD_SET_PARAMS_RESERVED1 24:24 +#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0x00000400 + (b)*0x00000004) +#define NV827D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV827D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400) +#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV827D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4 +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV827D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003) +#define NV827D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400) +#define NV827D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000089C + (a)*0x00000400) +#define NV827D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NV827D_HEAD_SET_DITHER_CONTROL(a) (0x000008A0 + (a)*0x00000400) +#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV827D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV827D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV827D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV827D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV827D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV827D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV827D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x000008A4 + (a)*0x00000400) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV827D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV827D_HEAD_SET_PROCAMP(a) (0x000008A8 + (a)*0x00000400) +#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV827D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV827D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV827D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV827D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV827D_HEAD_SET_PROCAMP_TRANSITION 4:3 +#define NV827D_HEAD_SET_PROCAMP_TRANSITION_HARD (0x00000000) +#define NV827D_HEAD_SET_PROCAMP_TRANSITION_NTSC (0x00000001) +#define NV827D_HEAD_SET_PROCAMP_TRANSITION_PAL (0x00000002) +#define NV827D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004) +#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV827D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000008C8 + (a)*0x00000400) +#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV827D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000008D4 + (a)*0x00000400) +#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV827D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000008D8 + (a)*0x00000400) +#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000008DC + (a)*0x00000400) +#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV827D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x00000900 + (a)*0x00000400) +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV827D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x00000904 + (a)*0x00000400) +#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV827D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV827D_HEAD_SET_PROCESSING(a) (0x00000910 + (a)*0x00000400) +#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV827D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV827D_HEAD_SET_CONVERSION(a) (0x00000914 + (a)*0x00000400) +#define NV827D_HEAD_SET_CONVERSION_GAIN 15:0 +#define NV827D_HEAD_SET_CONVERSION_OFS 31:16 +#define NV827D_HEAD_SET_SPARE(a) (0x00000BBC + (a)*0x00000400) +#define NV827D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV827D_HEAD_SET_SPARE_NOOP(a,b) (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004) +#define NV827D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl827d_h + diff --git a/Display-Class-Methods/cl827e.h b/Display-Class-Methods/cl827e.h new file mode 100644 index 0000000..b142fd1 --- /dev/null +++ b/Display-Class-Methods/cl827e.h @@ -0,0 +1,183 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl827e_h_ +#define _cl827e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV827E_OVERLAY_CHANNEL_DMA (0x0000827E) + +#define NV_DISP_NOTIFICATION_1 0x00000000 +#define NV_DISP_NOTIFICATION_1_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_1__2 0x00000002 +#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP 31:0 +#define NV_DISP_NOTIFICATION_1__3 0x00000003 +#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_1__3_R0 15:8 +#define NV_DISP_NOTIFICATION_1__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_R0 15:8 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV827E_DMA 0x00000000 +#define NV827E_DMA_OPCODE 31:29 +#define NV827E_DMA_OPCODE_METHOD 0x00000000 +#define NV827E_DMA_OPCODE_JUMP 0x00000001 +#define NV827E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV827E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV827E_DMA_OPCODE 31:29 +#define NV827E_DMA_OPCODE_METHOD 0x00000000 +#define NV827E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV827E_DMA_METHOD_COUNT 27:18 +#define NV827E_DMA_METHOD_OFFSET 11:2 +#define NV827E_DMA_DATA 31:0 +#define NV827E_DMA_NOP 0x00000000 +#define NV827E_DMA_OPCODE 31:29 +#define NV827E_DMA_OPCODE_JUMP 0x00000001 +#define NV827E_DMA_JUMP_OFFSET 11:2 +#define NV827E_DMA_OPCODE 31:29 +#define NV827E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV827E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV827E_PUT (0x00000000) +#define NV827E_PUT_PTR 11:2 +#define NV827E_GET (0x00000004) +#define NV827E_GET_PTR 11:2 +#define NV827E_UPDATE (0x00000080) +#define NV827E_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV827E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV827E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV827E_SET_PRESENT_CONTROL (0x00000084) +#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV827E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV827E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV827E_SET_SEMAPHORE_ACQUIRE (0x00000088) +#define NV827E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV827E_SET_SEMAPHORE_RELEASE (0x0000008C) +#define NV827E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV827E_SET_SEMAPHORE_CONTROL (0x00000090) +#define NV827E_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV827E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV827E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV827E_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV827E_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV827E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV827E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV827E_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV827E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV827E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV827E_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV827E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV827E_SET_POINT_IN (0x000000E0) +#define NV827E_SET_POINT_IN_X 14:0 +#define NV827E_SET_POINT_IN_Y 30:16 +#define NV827E_SET_SIZE_IN (0x000000E4) +#define NV827E_SET_SIZE_IN_WIDTH 14:0 +#define NV827E_SET_SIZE_IN_HEIGHT 30:16 +#define NV827E_SET_SIZE_OUT (0x000000E8) +#define NV827E_SET_SIZE_OUT_WIDTH 14:0 +#define NV827E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV827E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV827E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV827E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV827E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002) +#define NV827E_SET_KEY_COLOR (0x00000104) +#define NV827E_SET_KEY_COLOR_COLOR 31:0 +#define NV827E_SET_KEY_MASK (0x00000108) +#define NV827E_SET_KEY_MASK_MASK 31:0 +#define NV827E_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV827E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV827E_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV827E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV827E_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV827E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV827E_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV827E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV827E_SET_SPARE (0x000007BC) +#define NV827E_SET_SPARE_UNUSED 31:0 +#define NV827E_SET_SPARE_NOOP(b) (0x000007C0 + (b)*0x00000004) +#define NV827E_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV827E_SURFACE_SET_OFFSET (0x00000800) +#define NV827E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV827E_SURFACE_SET_SIZE (0x00000808) +#define NV827E_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV827E_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV827E_SURFACE_SET_STORAGE (0x0000080C) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV827E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV827E_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV827E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV827E_SURFACE_SET_PARAMS (0x00000810) +#define NV827E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV827E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV827E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV827E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV827E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV827E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV827E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NV827E_SURFACE_SET_PARAMS_RESERVED0 22:16 +#define NV827E_SURFACE_SET_PARAMS_RESERVED1 24:24 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl827e_h + diff --git a/Display-Class-Methods/cl837c.h b/Display-Class-Methods/cl837c.h new file mode 100644 index 0000000..a05d3f2 --- /dev/null +++ b/Display-Class-Methods/cl837c.h @@ -0,0 +1,181 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl837c_h_ +#define _cl837c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV837C_BASE_CHANNEL_DMA (0x0000837C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +// dma opcode instructions +#define NV837C_DMA 0x00000000 +#define NV837C_DMA_OPCODE 31:29 +#define NV837C_DMA_OPCODE_METHOD 0x00000000 +#define NV837C_DMA_OPCODE_JUMP 0x00000001 +#define NV837C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV837C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV837C_DMA_OPCODE 31:29 +#define NV837C_DMA_OPCODE_METHOD 0x00000000 +#define NV837C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV837C_DMA_METHOD_COUNT 27:18 +#define NV837C_DMA_METHOD_OFFSET 11:2 +#define NV837C_DMA_DATA 31:0 +#define NV837C_DMA_NOP 0x00000000 +#define NV837C_DMA_OPCODE 31:29 +#define NV837C_DMA_OPCODE_JUMP 0x00000001 +#define NV837C_DMA_JUMP_OFFSET 11:2 +#define NV837C_DMA_OPCODE 31:29 +#define NV837C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV837C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV837C_PUT (0x00000000) +#define NV837C_PUT_PTR 11:2 +#define NV837C_GET (0x00000004) +#define NV837C_GET_PTR 11:2 +#define NV837C_GET_SCANLINE (0x00000010) +#define NV837C_GET_SCANLINE_LINE 15:0 +#define NV837C_UPDATE (0x00000080) +#define NV837C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV837C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV837C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV837C_SET_PRESENT_CONTROL (0x00000084) +#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV837C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV837C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV837C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV837C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV837C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV837C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV837C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV837C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV837C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV837C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV837C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV837C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV837C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV837C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV837C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV837C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV837C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV837C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV837C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV837C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV837C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV837C_SET_BASE_LUT_LO (0x000000E0) +#define NV837C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV837C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV837C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV837C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000003) +#define NV837C_SET_BASE_LUT_LO_MODE 29:29 +#define NV837C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV837C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV837C_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV837C_SET_BASE_LUT_HI (0x000000E4) +#define NV837C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV837C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV837C_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV837C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV837C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV837C_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV837C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV837C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV837C_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV837C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV837C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV837C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV837C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV837C_SET_PROCESSING (0x00000110) +#define NV837C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV837C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV837C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV837C_SET_CONVERSION (0x00000114) +#define NV837C_SET_CONVERSION_GAIN 15:0 +#define NV837C_SET_CONVERSION_OFS 31:16 +#define NV837C_SET_SPARE (0x000007BC) +#define NV837C_SET_SPARE_UNUSED 31:0 +#define NV837C_SET_SPARE_NOOP(b) (0x000007C0 + (b)*0x00000004) +#define NV837C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV837C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004) +#define NV837C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV837C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020) +#define NV837C_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV837C_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV837C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020) +#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV837C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV837C_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV837C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV837C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020) +#define NV837C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV837C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV837C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV837C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV837C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV837C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV837C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV837C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV837C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV837C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV837C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV837C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV837C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV837C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV837C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV837C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) +#define NV837C_SURFACE_SET_PARAMS_RESERVED0 22:16 +#define NV837C_SURFACE_SET_PARAMS_RESERVED1 24:24 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl837c_h + diff --git a/Display-Class-Methods/cl837d.h b/Display-Class-Methods/cl837d.h new file mode 100644 index 0000000..57c04f2 --- /dev/null +++ b/Display-Class-Methods/cl837d.h @@ -0,0 +1,709 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl837d_h_ +#define _cl837d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV837D_CORE_CHANNEL_DMA (0x0000837D) + +#define NV837D_CORE_NOTIFIER_1 0x00000000 +#define NV837D_CORE_NOTIFIER_1_SIZEOF 0x00000054 +#define NV837D_CORE_NOTIFIER_1_COMPLETION_0 0x00000000 +#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE 0:0 +#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_R0 15:1 +#define NV837D_CORE_NOTIFIER_1_COMPLETION_0_TIMESTAMP 29:16 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_DONE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_VM_USABLE4ISO_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO 2:2 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_R0 3:3 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA 20:20 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS 21:21 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_1_R1 31:22 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_2 0x00000002 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_2_R2 31:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_3 0x00000003 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_3_R3 31:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_4 0x00000004 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_4_R4 31:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5 0x00000005 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_RGB_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_TV_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE 3:3 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC0_5_SCART_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6 0x00000006 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_RGB_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_TV_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE 3:3 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC1_6_SCART_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7 0x00000007 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_RGB_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_TV_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE 3:3 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_DAC2_7_SCART_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8 0x00000008 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS18_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_LVDS24_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18 2:2 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS18_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24 3:3 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_LVDS24_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A 4:4 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B 5:5 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS 6:6 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS 7:7 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DUAL_TMDS_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI 9:9 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR0_8_DDI_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9 0x00000009 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS18_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_LVDS24_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18 2:2 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS18_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24 3:3 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_LVDS24_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A 4:4 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B 5:5 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS 6:6 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS 7:7 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DUAL_TMDS_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI 9:9 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_SOR1_9_DDI_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10 0x0000000A +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TV_ENC_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR0_10_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11 0x0000000B +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TV_ENC_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR1_11_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12 0x0000000C +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC 1:1 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TV_ENC_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_PIOR2_12_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13 0x0000000D +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_13_R0 31:2 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14 0x0000000E +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP444 14:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R1 15:15 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_MAX_PIXELS5TAP422 30:16 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_14_R2 31:31 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15 0x0000000F +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP444 14:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R3 15:15 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_MAX_PIXELS3TAP422 30:16 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_15_R4 31:31 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16 0x00000010 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP444 14:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R5 15:15 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_MAX_PIXELS2TAP422 30:16 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD0_16_R6 31:31 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17 0x00000011 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE 0:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_FALSE 0x00000000 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_USABLE_TRUE 0x00000001 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_17_R0 31:2 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18 0x00000012 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP444 14:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R1 15:15 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_MAX_PIXELS5TAP422 30:16 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_18_R2 31:31 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19 0x00000013 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP444 14:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R3 15:15 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_MAX_PIXELS3TAP422 30:16 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_19_R4 31:31 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20 0x00000014 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP444 14:0 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R5 15:15 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_MAX_PIXELS2TAP422 30:16 +#define NV837D_CORE_NOTIFIER_1_CAPABILITIES_CAP_HEAD1_20_R6 31:31 + + +// dma opcode instructions +#define NV837D_DMA 0x00000000 +#define NV837D_DMA_OPCODE 31:29 +#define NV837D_DMA_OPCODE_METHOD 0x00000000 +#define NV837D_DMA_OPCODE_JUMP 0x00000001 +#define NV837D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV837D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV837D_DMA_OPCODE 31:29 +#define NV837D_DMA_OPCODE_METHOD 0x00000000 +#define NV837D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV837D_DMA_METHOD_COUNT 27:18 +#define NV837D_DMA_METHOD_OFFSET 11:2 +#define NV837D_DMA_DATA 31:0 +#define NV837D_DMA_NOP 0x00000000 +#define NV837D_DMA_OPCODE 31:29 +#define NV837D_DMA_OPCODE_JUMP 0x00000001 +#define NV837D_DMA_JUMP_OFFSET 11:2 +#define NV837D_DMA_OPCODE 31:29 +#define NV837D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV837D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV837D_PUT (0x00000000) +#define NV837D_PUT_PTR 11:2 +#define NV837D_GET (0x00000004) +#define NV837D_GET_PTR 11:2 +#define NV837D_UPDATE (0x00000080) +#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1 8:8 +#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV837D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV837D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV837D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV837D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV837D_UPDATE_INTERLOCK_WITH_BASE1 9:9 +#define NV837D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV837D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1 10:10 +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 11:11 +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV837D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV837D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV837D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV837D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV837D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV837D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV837D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV837D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV837D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV837D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV837D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV837D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV837D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV837D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV837D_GET_CAPABILITIES (0x0000008C) +#define NV837D_GET_CAPABILITIES_DUMMY 31:0 +#define NV837D_SET_SPARE (0x000003BC) +#define NV837D_SET_SPARE_UNUSED 31:0 +#define NV837D_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV837D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV837D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0x00000080) +#define NV837D_DAC_SET_CONTROL_OWNER 3:0 +#define NV837D_DAC_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV837D_DAC_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV837D_DAC_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV837D_DAC_SET_CONTROL_SUB_OWNER 5:4 +#define NV837D_DAC_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV837D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV837D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV837D_DAC_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV837D_DAC_SET_CONTROL_PROTOCOL 13:8 +#define NV837D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV837D_DAC_SET_CONTROL_PROTOCOL_CUSTOM (0x0000003F) +#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD 14:14 +#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE (0x00000000) +#define NV837D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE (0x00000001) +#define NV837D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0x00000080) +#define NV837D_DAC_SET_POLARITY_HSYNC 0:0 +#define NV837D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE (0x00000000) +#define NV837D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE (0x00000001) +#define NV837D_DAC_SET_POLARITY_VSYNC 1:1 +#define NV837D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE (0x00000000) +#define NV837D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE (0x00000001) +#define NV837D_DAC_SET_POLARITY_RESERVED 31:2 +#define NV837D_DAC_SET_ENCODE_QUALITY(a) (0x00000420 + (a)*0x00000080) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS 7:7 +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375 (0x00000000) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75 (0x00000001) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN 2:0 +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0 (0x00000000) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625 (0x00000001) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125 (0x00000002) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25 (0x00000003) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5 (0x00000004) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0 (0x00000005) +#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN 6:4 +#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0 (0x00000000) +#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625 (0x00000001) +#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125 (0x00000002) +#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25 (0x00000003) +#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5 (0x00000004) +#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0 (0x00000005) +#define NV837D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH 15:8 +#define NV837D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH 23:16 +#define NV837D_DAC_SET_ENCODE_QUALITY_TINT 31:24 +#define NV837D_DAC_UPDATE_ENCODER_PRESET(a) (0x0000047C + (a)*0x00000080) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL 5:0 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM (0x0000003F) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT 6:6 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV (0x00000001) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R 7:7 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE (0x00000001) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G 8:8 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE (0x00000001) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B 9:9 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE (0x00000001) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH 12:10 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358 (0x00000001) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358 (0x00000002) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443 (0x00000003) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443 (0x00000004) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW 13:13 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6 (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4 (0x00000001) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER 15:15 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE (0x00000001) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER 16:16 +#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW (0x00000000) +#define NV837D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE (0x00000001) + +#define NV837D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040) +#define NV837D_SOR_SET_CONTROL_OWNER 3:0 +#define NV837D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV837D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV837D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV837D_SOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV837D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007) +#define NV837D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV837D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040) +#define NV837D_PIOR_SET_CONTROL_OWNER 3:0 +#define NV837D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV837D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV837D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV837D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV837D_HEAD_SET_PRESENT_CONTROL(a) (0x00000800 + (a)*0x00000400) +#define NV837D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV837D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV837D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV837D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0x00000400) +#define NV837D_HEAD_SET_PIXEL_CLOCK_FREQUENCY 21:0 +#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE 23:22 +#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25 (0x00000000) +#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28 (0x00000001) +#define NV837D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM (0x00000002) +#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001 24:24 +#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE (0x00000000) +#define NV837D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE (0x00000001) +#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER 25:25 +#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE (0x00000000) +#define NV837D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE (0x00000001) +#define NV837D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0x00000400) +#define NV837D_HEAD_SET_CONTROL_STRUCTURE 2:1 +#define NV837D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV837D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV837D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0x00000400) +#define NV837D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV837D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV837D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV837D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0x00000400) +#define NV837D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV837D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV837D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0x00000400) +#define NV837D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV837D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV837D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0x00000400) +#define NV837D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV837D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV837D_HEAD_SET_RASTER_BLANK_START(a) (0x00000820 + (a)*0x00000400) +#define NV837D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV837D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV837D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000824 + (a)*0x00000400) +#define NV837D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV837D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV837D_HEAD_SET_RASTER_VERT_BLANK_DMI(a) (0x00000828 + (a)*0x00000400) +#define NV837D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION 11:0 +#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000082C + (a)*0x00000400) +#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV837D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV837D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400) +#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV837D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV837D_HEAD_SET_BASE_LUT_LO_MODE 30:30 +#define NV837D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV837D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV837D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV837D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400) +#define NV837D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV837D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000848 + (a)*0x00000400) +#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV837D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV837D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV837D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000084C + (a)*0x00000400) +#define NV837D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV837D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400) +#define NV837D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV837D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004) +#define NV837D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV837D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400) +#define NV837D_HEAD_SET_SIZE_WIDTH 14:0 +#define NV837D_HEAD_SET_SIZE_HEIGHT 30:16 +#define NV837D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400) +#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV837D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV837D_HEAD_SET_STORAGE_PITCH 17:8 +#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV837D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV837D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400) +#define NV837D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV837D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV837D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV837D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV837D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV837D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV837D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV837D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV837D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV837D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV837D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV837D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV837D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV837D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV837D_HEAD_SET_PARAMS_RESERVED0 22:16 +#define NV837D_HEAD_SET_PARAMS_RESERVED1 24:24 +#define NV837D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0x00000400 + (b)*0x00000004) +#define NV837D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV837D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400) +#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV837D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV837D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV837D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV837D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV837D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV837D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4 +#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000) +#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV837D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003) +#define NV837D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400) +#define NV837D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV837D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000089C + (a)*0x00000400) +#define NV837D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NV837D_HEAD_SET_DITHER_CONTROL(a) (0x000008A0 + (a)*0x00000400) +#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV837D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV837D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV837D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV837D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV837D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV837D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV837D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x000008A4 + (a)*0x00000400) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV837D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV837D_HEAD_SET_PROCAMP(a) (0x000008A8 + (a)*0x00000400) +#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV837D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV837D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV837D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV837D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV837D_HEAD_SET_PROCAMP_TRANSITION 4:3 +#define NV837D_HEAD_SET_PROCAMP_TRANSITION_HARD (0x00000000) +#define NV837D_HEAD_SET_PROCAMP_TRANSITION_NTSC (0x00000001) +#define NV837D_HEAD_SET_PROCAMP_TRANSITION_PAL (0x00000002) +#define NV837D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004) +#define NV837D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV837D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000008C8 + (a)*0x00000400) +#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV837D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000008D4 + (a)*0x00000400) +#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV837D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000008D8 + (a)*0x00000400) +#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000008DC + (a)*0x00000400) +#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV837D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x00000900 + (a)*0x00000400) +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV837D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x00000904 + (a)*0x00000400) +#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV837D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV837D_HEAD_SET_PROCESSING(a) (0x00000910 + (a)*0x00000400) +#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV837D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV837D_HEAD_SET_CONVERSION(a) (0x00000914 + (a)*0x00000400) +#define NV837D_HEAD_SET_CONVERSION_GAIN 15:0 +#define NV837D_HEAD_SET_CONVERSION_OFS 31:16 +#define NV837D_HEAD_SET_SPARE(a) (0x00000BBC + (a)*0x00000400) +#define NV837D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV837D_HEAD_SET_SPARE_NOOP(a,b) (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004) +#define NV837D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl837d_h + diff --git a/Display-Class-Methods/cl837e.h b/Display-Class-Methods/cl837e.h new file mode 100644 index 0000000..62cc069 --- /dev/null +++ b/Display-Class-Methods/cl837e.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl837e_h_ +#define _cl837e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV837E_OVERLAY_CHANNEL_DMA (0x0000837E) + +#define NV_DISP_NOTIFICATION_1 0x00000000 +#define NV_DISP_NOTIFICATION_1_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_1__2 0x00000002 +#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP 31:0 +#define NV_DISP_NOTIFICATION_1__3 0x00000003 +#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_1__3_R0 15:8 +#define NV_DISP_NOTIFICATION_1__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_R0 15:8 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV837E_DMA 0x00000000 +#define NV837E_DMA_OPCODE 31:29 +#define NV837E_DMA_OPCODE_METHOD 0x00000000 +#define NV837E_DMA_OPCODE_JUMP 0x00000001 +#define NV837E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV837E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV837E_DMA_OPCODE 31:29 +#define NV837E_DMA_OPCODE_METHOD 0x00000000 +#define NV837E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV837E_DMA_METHOD_COUNT 27:18 +#define NV837E_DMA_METHOD_OFFSET 11:2 +#define NV837E_DMA_DATA 31:0 +#define NV837E_DMA_NOP 0x00000000 +#define NV837E_DMA_OPCODE 31:29 +#define NV837E_DMA_OPCODE_JUMP 0x00000001 +#define NV837E_DMA_JUMP_OFFSET 11:2 +#define NV837E_DMA_OPCODE 31:29 +#define NV837E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV837E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV837E_PUT (0x00000000) +#define NV837E_PUT_PTR 11:2 +#define NV837E_GET (0x00000004) +#define NV837E_GET_PTR 11:2 +#define NV837E_UPDATE (0x00000080) +#define NV837E_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV837E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV837E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV837E_SET_PRESENT_CONTROL (0x00000084) +#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV837E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV837E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV837E_SET_SEMAPHORE_ACQUIRE (0x00000088) +#define NV837E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV837E_SET_SEMAPHORE_RELEASE (0x0000008C) +#define NV837E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV837E_SET_SEMAPHORE_CONTROL (0x00000090) +#define NV837E_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV837E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV837E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV837E_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV837E_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV837E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV837E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV837E_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV837E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV837E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV837E_SET_CONTEXT_DMA_LUT (0x000000B0) +#define NV837E_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV837E_SET_OVERLAY_LUT_LO (0x000000B4) +#define NV837E_SET_OVERLAY_LUT_LO_ENABLE 30:30 +#define NV837E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV837E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV837E_SET_OVERLAY_LUT_LO_MODE 29:29 +#define NV837E_SET_OVERLAY_LUT_LO_MODE_LORES (0x00000000) +#define NV837E_SET_OVERLAY_LUT_LO_MODE_HIRES (0x00000001) +#define NV837E_SET_OVERLAY_LUT_LO_ORIGIN 7:2 +#define NV837E_SET_OVERLAY_LUT_HI (0x000000B8) +#define NV837E_SET_OVERLAY_LUT_HI_ORIGIN 31:0 +#define NV837E_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV837E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV837E_SET_POINT_IN (0x000000E0) +#define NV837E_SET_POINT_IN_X 14:0 +#define NV837E_SET_POINT_IN_Y 30:16 +#define NV837E_SET_SIZE_IN (0x000000E4) +#define NV837E_SET_SIZE_IN_WIDTH 14:0 +#define NV837E_SET_SIZE_IN_HEIGHT 30:16 +#define NV837E_SET_SIZE_OUT (0x000000E8) +#define NV837E_SET_SIZE_OUT_WIDTH 14:0 +#define NV837E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV837E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV837E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV837E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV837E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002) +#define NV837E_SET_KEY_COLOR (0x00000104) +#define NV837E_SET_KEY_COLOR_COLOR 31:0 +#define NV837E_SET_KEY_MASK (0x00000108) +#define NV837E_SET_KEY_MASK_MASK 31:0 +#define NV837E_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV837E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV837E_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV837E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV837E_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV837E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV837E_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV837E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV837E_SET_SPARE (0x000007BC) +#define NV837E_SET_SPARE_UNUSED 31:0 +#define NV837E_SET_SPARE_NOOP(b) (0x000007C0 + (b)*0x00000004) +#define NV837E_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV837E_SURFACE_SET_OFFSET (0x00000800) +#define NV837E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV837E_SURFACE_SET_SIZE (0x00000808) +#define NV837E_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV837E_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV837E_SURFACE_SET_STORAGE (0x0000080C) +#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV837E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV837E_SURFACE_SET_STORAGE_PITCH 17:8 +#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV837E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV837E_SURFACE_SET_PARAMS (0x00000810) +#define NV837E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV837E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV837E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV837E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV837E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV837E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV837E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NV837E_SURFACE_SET_PARAMS_RESERVED0 22:16 +#define NV837E_SURFACE_SET_PARAMS_RESERVED1 24:24 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl837e_h + diff --git a/Display-Class-Methods/cl857a.h b/Display-Class-Methods/cl857a.h new file mode 100644 index 0000000..cc5fbca --- /dev/null +++ b/Display-Class-Methods/cl857a.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl857a_h_ +#define _cl857a_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV857A_CURSOR_CHANNEL_PIO (0x0000857A) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetCursorHotSpotPointOut; // 0x00000084 - 0x00000087 + NvV32 Reserved02[0x3DE]; +} GT214DispCursorControlPio; + +#define NV857A_FREE (0x00000008) +#define NV857A_FREE_COUNT 5:0 +#define NV857A_UPDATE (0x00000080) +#define NV857A_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV857A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV857A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT (0x00000084) +#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NV857A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl857a_h + diff --git a/Display-Class-Methods/cl857b.h b/Display-Class-Methods/cl857b.h new file mode 100644 index 0000000..a6c8c49 --- /dev/null +++ b/Display-Class-Methods/cl857b.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl857b_h_ +#define _cl857b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV857B_OVERLAY_IMM_CHANNEL_PIO (0x0000857B) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetPointOut; // 0x00000084 - 0x00000087 + NvV32 AwakenOnceFlippedTo; // 0x00000088 - 0x0000008B + NvV32 Reserved02[0x3DD]; +} GT214DispOverlayImmControlPio; + +#define NV857B_FREE (0x00000008) +#define NV857B_FREE_COUNT 5:0 +#define NV857B_UPDATE (0x00000080) +#define NV857B_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV857B_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV857B_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV857B_SET_POINT_OUT (0x00000084) +#define NV857B_SET_POINT_OUT_X 15:0 +#define NV857B_SET_POINT_OUT_Y 31:16 +#define NV857B_AWAKEN_ONCE_FLIPPED_TO (0x00000088) +#define NV857B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT 11:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl857b_h + diff --git a/Display-Class-Methods/cl857c.h b/Display-Class-Methods/cl857c.h new file mode 100644 index 0000000..bfb610c --- /dev/null +++ b/Display-Class-Methods/cl857c.h @@ -0,0 +1,188 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl857c_h_ +#define _cl857c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV857C_BASE_CHANNEL_DMA (0x0000857C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +// dma opcode instructions +#define NV857C_DMA 0x00000000 +#define NV857C_DMA_OPCODE 31:29 +#define NV857C_DMA_OPCODE_METHOD 0x00000000 +#define NV857C_DMA_OPCODE_JUMP 0x00000001 +#define NV857C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV857C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV857C_DMA_OPCODE 31:29 +#define NV857C_DMA_OPCODE_METHOD 0x00000000 +#define NV857C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV857C_DMA_METHOD_COUNT 27:18 +#define NV857C_DMA_METHOD_OFFSET 11:2 +#define NV857C_DMA_DATA 31:0 +#define NV857C_DMA_DATA_NOP 0x00000000 +#define NV857C_DMA_OPCODE 31:29 +#define NV857C_DMA_OPCODE_JUMP 0x00000001 +#define NV857C_DMA_JUMP_OFFSET 11:2 +#define NV857C_DMA_OPCODE 31:29 +#define NV857C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV857C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV857C_PUT (0x00000000) +#define NV857C_PUT_PTR 11:2 +#define NV857C_GET (0x00000004) +#define NV857C_GET_PTR 11:2 +#define NV857C_GET_SCANLINE (0x00000010) +#define NV857C_GET_SCANLINE_LINE 15:0 +#define NV857C_UPDATE (0x00000080) +#define NV857C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV857C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV857C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV857C_SET_PRESENT_CONTROL (0x00000084) +#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV857C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV857C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV857C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV857C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV857C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV857C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV857C_SET_SEMAPHORE_CONTROL_DELAY 26:26 +#define NV857C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000) +#define NV857C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001) +#define NV857C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV857C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV857C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV857C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV857C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV857C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV857C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV857C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV857C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV857C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV857C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV857C_SET_NOTIFIER_CONTROL_DELAY 26:26 +#define NV857C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000) +#define NV857C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001) +#define NV857C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV857C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV857C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV857C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV857C_SET_BASE_LUT_LO (0x000000E0) +#define NV857C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV857C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV857C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV857C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000003) +#define NV857C_SET_BASE_LUT_LO_MODE 29:29 +#define NV857C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV857C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV857C_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV857C_SET_BASE_LUT_HI (0x000000E4) +#define NV857C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV857C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV857C_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV857C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV857C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV857C_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV857C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV857C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV857C_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV857C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV857C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV857C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV857C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV857C_SET_PROCESSING (0x00000110) +#define NV857C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV857C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV857C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV857C_SET_CONVERSION (0x00000114) +#define NV857C_SET_CONVERSION_GAIN 15:0 +#define NV857C_SET_CONVERSION_OFS 31:16 +#define NV857C_SET_SPARE (0x000007BC) +#define NV857C_SET_SPARE_UNUSED 31:0 +#define NV857C_SET_SPARE_NOOP(b) (0x000007C0 + (b)*0x00000004) +#define NV857C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV857C_SURFACE_SET_OFFSET(a,b) (0x00000800 + (a)*0x00000020 + (b)*0x00000004) +#define NV857C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV857C_SURFACE_SET_SIZE(a) (0x00000808 + (a)*0x00000020) +#define NV857C_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV857C_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV857C_SURFACE_SET_STORAGE(a) (0x0000080C + (a)*0x00000020) +#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV857C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV857C_SURFACE_SET_STORAGE_PITCH 19:8 +#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV857C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV857C_SURFACE_SET_PARAMS(a) (0x00000810 + (a)*0x00000020) +#define NV857C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV857C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV857C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV857C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV857C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV857C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV857C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV857C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV857C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV857C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV857C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X8_AA (0x00000003) +#define NV857C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV857C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV857C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV857C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV857C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) +#define NV857C_SURFACE_SET_PARAMS_RESERVED0 22:16 +#define NV857C_SURFACE_SET_PARAMS_RESERVED1 24:24 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl857c_h + diff --git a/Display-Class-Methods/cl857d.h b/Display-Class-Methods/cl857d.h new file mode 100644 index 0000000..13ef79f --- /dev/null +++ b/Display-Class-Methods/cl857d.h @@ -0,0 +1,1121 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl857d_h_ +#define _cl857d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV857D_CORE_CHANNEL_DMA (0x0000857D) + +#define NV857D_CORE_NOTIFIER_2 0x00000000 +#define NV857D_CORE_NOTIFIER_2_SIZEOF 0x00000124 +#define NV857D_CORE_NOTIFIER_2_COMPLETION_0 0x00000000 +#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE 0:0 +#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_R0 15:1 +#define NV857D_CORE_NOTIFIER_2_COMPLETION_0_TIMESTAMP 29:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_GAMMA_FOS10BPC_SUPPORTED_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA 20:20 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS 21:21 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA 22:22 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X8AA_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2 0x00000002 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_FP16CDOS_SUPPORTED_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_SEMA_NOTIF_DELAY_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_2_R2 31:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_3 0x00000003 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_3_R3 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_4 0x00000004 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_4_R4 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_5 0x00000005 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_5_R5 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_6 0x00000006 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_6_R6 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_7 0x00000007 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_7_R7 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_8 0x00000008 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_8_R8 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9 0x00000009 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_R0 31:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10 0x0000000A +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11 0x0000000B +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_R0 31:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12 0x0000000C +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13 0x0000000D +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_R0 31:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14 0x0000000E +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15 0x0000000F +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_R0 31:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16 0x00000010 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17 0x00000011 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A 4:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B 5:5 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS 7:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI 9:9 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A 10:10 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B 11:11 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ 12:12 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS225MHZ_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_R0 31:14 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18 0x00000012 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19 0x00000013 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A 4:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B 5:5 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS 7:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI 9:9 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A 10:10 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B 11:11 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ 12:12 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS225MHZ_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_R0 31:14 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20 0x00000014 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21 0x00000015 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A 4:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B 5:5 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS 7:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI 9:9 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A 10:10 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B 11:11 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ 12:12 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS225MHZ_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_R0 31:14 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22 0x00000016 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23 0x00000017 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A 4:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B 5:5 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS 7:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI 9:9 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A 10:10 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B 11:11 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ 12:12 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS225MHZ_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_R0 31:14 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24 0x00000018 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25 0x00000019 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A 4:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B 5:5 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS 7:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI 9:9 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A 10:10 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B 11:11 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ 12:12 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS225MHZ_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_R0 31:14 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26 0x0000001A +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27 0x0000001B +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A 4:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B 5:5 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS 7:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI 9:9 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A 10:10 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B 11:11 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ 12:12 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS225MHZ_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_R0 31:14 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28 0x0000001C +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29 0x0000001D +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A 4:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B 5:5 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS 7:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI 9:9 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A 10:10 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B 11:11 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ 12:12 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS225MHZ_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_R0 31:14 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30 0x0000001E +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31 0x0000001F +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18 2:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24 3:3 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A 4:4 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B 5:5 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS 7:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI 9:9 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A 10:10 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B 11:11 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ 12:12 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS225MHZ_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_R0 31:14 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32 0x00000020 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33 0x00000021 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_R0 31:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34 0x00000022 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35 0x00000023 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_R0 31:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36 0x00000024 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37 0x00000025 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_R0 31:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38 0x00000026 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39 0x00000027 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC 1:1 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_R0 31:7 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40 0x00000028 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40_R1 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41 0x00000029 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_R0 31:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42 0x0000002A +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R1 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R2 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43 0x0000002B +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R3 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R4 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44 0x0000002C +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R5 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R6 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45 0x0000002D +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45_R7 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46 0x0000002E +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46_R8 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47 0x0000002F +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47_R9 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48 0x00000030 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48_R10 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49 0x00000031 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_R0 31:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50 0x00000032 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R1 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R2 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51 0x00000033 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R3 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R4 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52 0x00000034 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R5 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R6 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53 0x00000035 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53_R7 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54 0x00000036 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54_R8 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55 0x00000037 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55_R9 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56 0x00000038 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56_R10 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57 0x00000039 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_R0 31:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58 0x0000003A +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R1 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R2 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59 0x0000003B +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R3 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R4 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60 0x0000003C +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R5 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R6 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61 0x0000003D +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61_R7 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62 0x0000003E +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62_R8 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63 0x0000003F +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63_R9 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64 0x00000040 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64_R10 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65 0x00000041 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE 0:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_FALSE 0x00000000 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_TRUE 0x00000001 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_R0 31:2 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66 0x00000042 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R1 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R2 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67 0x00000043 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R3 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R4 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68 0x00000044 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP444 14:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R5 15:15 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP422 30:16 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R6 31:31 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69 0x00000045 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69_R7 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70 0x00000046 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70_R8 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71 0x00000047 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71_R9 31:0 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72 0x00000048 +#define NV857D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72_R10 31:0 + + +// dma opcode instructions +#define NV857D_DMA 0x00000000 +#define NV857D_DMA_OPCODE 31:29 +#define NV857D_DMA_OPCODE_METHOD 0x00000000 +#define NV857D_DMA_OPCODE_JUMP 0x00000001 +#define NV857D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV857D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV857D_DMA_OPCODE 31:29 +#define NV857D_DMA_OPCODE_METHOD 0x00000000 +#define NV857D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV857D_DMA_METHOD_COUNT 27:18 +#define NV857D_DMA_METHOD_OFFSET 11:2 +#define NV857D_DMA_DATA 31:0 +#define NV857D_DMA_DATA_NOP 0x00000000 +#define NV857D_DMA_OPCODE 31:29 +#define NV857D_DMA_OPCODE_JUMP 0x00000001 +#define NV857D_DMA_JUMP_OFFSET 11:2 +#define NV857D_DMA_OPCODE 31:29 +#define NV857D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV857D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV857D_PUT (0x00000000) +#define NV857D_PUT_PTR 11:2 +#define NV857D_GET (0x00000004) +#define NV857D_GET_PTR 11:2 +#define NV857D_UPDATE (0x00000080) +#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1 8:8 +#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV857D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV857D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV857D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV857D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV857D_UPDATE_INTERLOCK_WITH_BASE1 9:9 +#define NV857D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV857D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1 10:10 +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 11:11 +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV857D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV857D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV857D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV857D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV857D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV857D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV857D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV857D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV857D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV857D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV857D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV857D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV857D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV857D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV857D_GET_CAPABILITIES (0x0000008C) +#define NV857D_GET_CAPABILITIES_DUMMY 31:0 +#define NV857D_SET_SPARE (0x000003BC) +#define NV857D_SET_SPARE_UNUSED 31:0 +#define NV857D_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV857D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV857D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0x00000080) +#define NV857D_DAC_SET_CONTROL_OWNER 3:0 +#define NV857D_DAC_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV857D_DAC_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV857D_DAC_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV857D_DAC_SET_CONTROL_SUB_OWNER 5:4 +#define NV857D_DAC_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV857D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV857D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV857D_DAC_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV857D_DAC_SET_CONTROL_PROTOCOL 13:8 +#define NV857D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV857D_DAC_SET_CONTROL_PROTOCOL_CUSTOM (0x0000003F) +#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD 14:14 +#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE (0x00000000) +#define NV857D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE (0x00000001) +#define NV857D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0x00000080) +#define NV857D_DAC_SET_POLARITY_HSYNC 0:0 +#define NV857D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE (0x00000000) +#define NV857D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE (0x00000001) +#define NV857D_DAC_SET_POLARITY_VSYNC 1:1 +#define NV857D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE (0x00000000) +#define NV857D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE (0x00000001) +#define NV857D_DAC_SET_POLARITY_RESERVED 31:2 +#define NV857D_DAC_SET_ENCODE_QUALITY(a) (0x00000420 + (a)*0x00000080) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS 7:7 +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375 (0x00000000) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75 (0x00000001) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN 2:0 +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0 (0x00000000) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625 (0x00000001) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125 (0x00000002) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25 (0x00000003) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5 (0x00000004) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0 (0x00000005) +#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN 6:4 +#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0 (0x00000000) +#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625 (0x00000001) +#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125 (0x00000002) +#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25 (0x00000003) +#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5 (0x00000004) +#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0 (0x00000005) +#define NV857D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH 15:8 +#define NV857D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH 23:16 +#define NV857D_DAC_SET_ENCODE_QUALITY_TINT 31:24 +#define NV857D_DAC_UPDATE_ENCODER_PRESET(a) (0x0000047C + (a)*0x00000080) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL 5:0 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM (0x0000003F) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT 6:6 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV (0x00000001) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R 7:7 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE (0x00000001) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G 8:8 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE (0x00000001) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B 9:9 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE (0x00000001) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH 12:10 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358 (0x00000001) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358 (0x00000002) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443 (0x00000003) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443 (0x00000004) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW 13:13 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6 (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4 (0x00000001) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER 15:15 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE (0x00000001) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER 16:16 +#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW (0x00000000) +#define NV857D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE (0x00000001) + +#define NV857D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040) +#define NV857D_SOR_SET_CONTROL_OWNER 3:0 +#define NV857D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV857D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV857D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV857D_SOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV857D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV857D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV857D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV857D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV857D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV857D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV857D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV857D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV857D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV857D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV857D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV857D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV857D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040) +#define NV857D_PIOR_SET_CONTROL_OWNER 3:0 +#define NV857D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV857D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV857D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV857D_PIOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV857D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV857D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV857D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV857D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV857D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV857D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV857D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV857D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV857D_HEAD_SET_PRESENT_CONTROL(a) (0x00000800 + (a)*0x00000400) +#define NV857D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV857D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV857D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV857D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0x00000400) +#define NV857D_HEAD_SET_PIXEL_CLOCK_FREQUENCY 21:0 +#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE 23:22 +#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25 (0x00000000) +#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28 (0x00000001) +#define NV857D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM (0x00000002) +#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001 24:24 +#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE (0x00000000) +#define NV857D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE (0x00000001) +#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER 25:25 +#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE (0x00000000) +#define NV857D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE (0x00000001) +#define NV857D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0x00000400) +#define NV857D_HEAD_SET_CONTROL_STRUCTURE 2:1 +#define NV857D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV857D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV857D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0x00000400) +#define NV857D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV857D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV857D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV857D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0x00000400) +#define NV857D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV857D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV857D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0x00000400) +#define NV857D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV857D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV857D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0x00000400) +#define NV857D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV857D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV857D_HEAD_SET_RASTER_BLANK_START(a) (0x00000820 + (a)*0x00000400) +#define NV857D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV857D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV857D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000824 + (a)*0x00000400) +#define NV857D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV857D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV857D_HEAD_SET_RASTER_VERT_BLANK_DMI(a) (0x00000828 + (a)*0x00000400) +#define NV857D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION 11:0 +#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000082C + (a)*0x00000400) +#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV857D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV857D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400) +#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV857D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV857D_HEAD_SET_BASE_LUT_LO_MODE 30:30 +#define NV857D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV857D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV857D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV857D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400) +#define NV857D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV857D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000848 + (a)*0x00000400) +#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV857D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV857D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV857D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000084C + (a)*0x00000400) +#define NV857D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV857D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400) +#define NV857D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV857D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004) +#define NV857D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV857D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400) +#define NV857D_HEAD_SET_SIZE_WIDTH 14:0 +#define NV857D_HEAD_SET_SIZE_HEIGHT 30:16 +#define NV857D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400) +#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV857D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV857D_HEAD_SET_STORAGE_PITCH 19:8 +#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV857D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV857D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400) +#define NV857D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV857D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV857D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV857D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV857D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV857D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV857D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV857D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV857D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV857D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV857D_HEAD_SET_PARAMS_SUPER_SAMPLE_X8_AA (0x00000003) +#define NV857D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV857D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV857D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV857D_HEAD_SET_PARAMS_RESERVED0 22:16 +#define NV857D_HEAD_SET_PARAMS_RESERVED1 24:24 +#define NV857D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0x00000400 + (b)*0x00000004) +#define NV857D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV857D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400) +#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV857D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV857D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV857D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV857D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV857D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV857D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4 +#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000) +#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV857D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003) +#define NV857D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400) +#define NV857D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV857D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000089C + (a)*0x00000400) +#define NV857D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NV857D_HEAD_SET_DITHER_CONTROL(a) (0x000008A0 + (a)*0x00000400) +#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV857D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV857D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV857D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV857D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV857D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV857D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV857D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x000008A4 + (a)*0x00000400) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV857D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV857D_HEAD_SET_PROCAMP(a) (0x000008A8 + (a)*0x00000400) +#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV857D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV857D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV857D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV857D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV857D_HEAD_SET_PROCAMP_TRANSITION 4:3 +#define NV857D_HEAD_SET_PROCAMP_TRANSITION_HARD (0x00000000) +#define NV857D_HEAD_SET_PROCAMP_TRANSITION_NTSC (0x00000001) +#define NV857D_HEAD_SET_PROCAMP_TRANSITION_PAL (0x00000002) +#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV857D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV857D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV857D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004) +#define NV857D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV857D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000008C8 + (a)*0x00000400) +#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV857D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000008D4 + (a)*0x00000400) +#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV857D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000008D8 + (a)*0x00000400) +#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000008DC + (a)*0x00000400) +#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV857D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x00000900 + (a)*0x00000400) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV857D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X8_AA (0x00000003) +#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x00000904 + (a)*0x00000400) +#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV857D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV857D_HEAD_SET_PROCESSING(a) (0x00000910 + (a)*0x00000400) +#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV857D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV857D_HEAD_SET_CONVERSION(a) (0x00000914 + (a)*0x00000400) +#define NV857D_HEAD_SET_CONVERSION_GAIN 15:0 +#define NV857D_HEAD_SET_CONVERSION_OFS 31:16 +#define NV857D_HEAD_SET_SPARE(a) (0x00000BBC + (a)*0x00000400) +#define NV857D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV857D_HEAD_SET_SPARE_NOOP(a,b) (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004) +#define NV857D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl857d_h + diff --git a/Display-Class-Methods/cl857e.h b/Display-Class-Methods/cl857e.h new file mode 100644 index 0000000..045a134 --- /dev/null +++ b/Display-Class-Methods/cl857e.h @@ -0,0 +1,195 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl857e_h_ +#define _cl857e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV857E_OVERLAY_CHANNEL_DMA (0x0000857E) + +#define NV_DISP_NOTIFICATION_1 0x00000000 +#define NV_DISP_NOTIFICATION_1_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_1_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_1__2 0x00000002 +#define NV_DISP_NOTIFICATION_1__2_AUDIT_TIMESTAMP 31:0 +#define NV_DISP_NOTIFICATION_1__3 0x00000003 +#define NV_DISP_NOTIFICATION_1__3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_1__3_R0 15:8 +#define NV_DISP_NOTIFICATION_1__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_1__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_1__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_1__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_R0 15:8 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV857E_DMA 0x00000000 +#define NV857E_DMA_OPCODE 31:29 +#define NV857E_DMA_OPCODE_METHOD 0x00000000 +#define NV857E_DMA_OPCODE_JUMP 0x00000001 +#define NV857E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV857E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV857E_DMA_OPCODE 31:29 +#define NV857E_DMA_OPCODE_METHOD 0x00000000 +#define NV857E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV857E_DMA_METHOD_COUNT 27:18 +#define NV857E_DMA_METHOD_OFFSET 11:2 +#define NV857E_DMA_DATA 31:0 +#define NV857E_DMA_DATA_NOP 0x00000000 +#define NV857E_DMA_OPCODE 31:29 +#define NV857E_DMA_OPCODE_JUMP 0x00000001 +#define NV857E_DMA_JUMP_OFFSET 11:2 +#define NV857E_DMA_OPCODE 31:29 +#define NV857E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV857E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV857E_PUT (0x00000000) +#define NV857E_PUT_PTR 11:2 +#define NV857E_GET (0x00000004) +#define NV857E_GET_PTR 11:2 +#define NV857E_UPDATE (0x00000080) +#define NV857E_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV857E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV857E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV857E_SET_PRESENT_CONTROL (0x00000084) +#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV857E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV857E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV857E_SET_SEMAPHORE_ACQUIRE (0x00000088) +#define NV857E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV857E_SET_SEMAPHORE_RELEASE (0x0000008C) +#define NV857E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV857E_SET_SEMAPHORE_CONTROL (0x00000090) +#define NV857E_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV857E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV857E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV857E_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV857E_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV857E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV857E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV857E_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV857E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV857E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV857E_SET_CONTEXT_DMA_LUT (0x000000B0) +#define NV857E_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV857E_SET_OVERLAY_LUT_LO (0x000000B4) +#define NV857E_SET_OVERLAY_LUT_LO_ENABLE 30:30 +#define NV857E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV857E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV857E_SET_OVERLAY_LUT_LO_MODE 29:29 +#define NV857E_SET_OVERLAY_LUT_LO_MODE_LORES (0x00000000) +#define NV857E_SET_OVERLAY_LUT_LO_MODE_HIRES (0x00000001) +#define NV857E_SET_OVERLAY_LUT_LO_ORIGIN 7:2 +#define NV857E_SET_OVERLAY_LUT_HI (0x000000B8) +#define NV857E_SET_OVERLAY_LUT_HI_ORIGIN 31:0 +#define NV857E_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV857E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV857E_SET_POINT_IN (0x000000E0) +#define NV857E_SET_POINT_IN_X 14:0 +#define NV857E_SET_POINT_IN_Y 30:16 +#define NV857E_SET_SIZE_IN (0x000000E4) +#define NV857E_SET_SIZE_IN_WIDTH 14:0 +#define NV857E_SET_SIZE_IN_HEIGHT 30:16 +#define NV857E_SET_SIZE_OUT (0x000000E8) +#define NV857E_SET_SIZE_OUT_WIDTH 14:0 +#define NV857E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV857E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV857E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV857E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV857E_SET_COMPOSITION_CONTROL_MODE_OPAQUE_SUSPEND_BASE (0x00000002) +#define NV857E_SET_KEY_COLOR (0x00000104) +#define NV857E_SET_KEY_COLOR_COLOR 31:0 +#define NV857E_SET_KEY_MASK (0x00000108) +#define NV857E_SET_KEY_MASK_MASK 31:0 +#define NV857E_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV857E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV857E_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV857E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV857E_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV857E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV857E_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV857E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV857E_SET_SPARE (0x000007BC) +#define NV857E_SET_SPARE_UNUSED 31:0 +#define NV857E_SET_SPARE_NOOP(b) (0x000007C0 + (b)*0x00000004) +#define NV857E_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV857E_SURFACE_SET_OFFSET (0x00000800) +#define NV857E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV857E_SURFACE_SET_SIZE (0x00000808) +#define NV857E_SURFACE_SET_SIZE_WIDTH 14:0 +#define NV857E_SURFACE_SET_SIZE_HEIGHT 30:16 +#define NV857E_SURFACE_SET_STORAGE (0x0000080C) +#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV857E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV857E_SURFACE_SET_STORAGE_PITCH 19:8 +#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV857E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV857E_SURFACE_SET_PARAMS (0x00000810) +#define NV857E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV857E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV857E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV857E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV857E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV857E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV857E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) +#define NV857E_SURFACE_SET_PARAMS_RESERVED0 22:16 +#define NV857E_SURFACE_SET_PARAMS_RESERVED1 24:24 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl857e_h + diff --git a/Display-Class-Methods/cl887d.h b/Display-Class-Methods/cl887d.h new file mode 100644 index 0000000..fde2a4a --- /dev/null +++ b/Display-Class-Methods/cl887d.h @@ -0,0 +1,1078 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl887d_h_ +#define _cl887d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV887D_CORE_CHANNEL_DMA (0x0000887D) + +#define NV887D_CORE_NOTIFIER_2 0x00000000 +#define NV887D_CORE_NOTIFIER_2_SIZEOF 0x00000124 +#define NV887D_CORE_NOTIFIER_2_COMPLETION_0 0x00000000 +#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE 0:0 +#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_R0 15:1 +#define NV887D_CORE_NOTIFIER_2_COMPLETION_0_TIMESTAMP 29:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_DONE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_VM_USABLE4ISO_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_R0 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA 20:20 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS 21:21 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_FP16CONVERSION_GAIN_OFS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_1_R1 31:22 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_2 0x00000002 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_2_R2 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_3 0x00000003 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_3_R3 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_4 0x00000004 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_4_R4 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_5 0x00000005 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_5_R5 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_6 0x00000006 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_6_R6 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_7 0x00000007 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_7_R7 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_8 0x00000008 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_8_R8 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9 0x00000009 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_RGB_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_TV_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_SCART_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_9_R0 31:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10 0x0000000A +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC0_10_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11 0x0000000B +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_RGB_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_TV_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_SCART_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_11_R0 31:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12 0x0000000C +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC1_12_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13 0x0000000D +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_RGB_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_TV_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_SCART_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_13_R0 31:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14 0x0000000E +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC2_14_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15 0x0000000F +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_RGB_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_TV_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_SCART_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_15_R0 31:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16 0x00000010 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_DAC3_16_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17 0x00000011 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A 4:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B 5:5 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS 7:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DUAL_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI 9:9 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DDI_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A 10:10 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B 11:11 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_DP_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_17_R0 31:12 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18 0x00000012 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR0_18_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19 0x00000013 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A 4:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B 5:5 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS 7:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DUAL_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI 9:9 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DDI_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A 10:10 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B 11:11 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_DP_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_19_R0 31:12 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20 0x00000014 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR1_20_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21 0x00000015 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A 4:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B 5:5 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS 7:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DUAL_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI 9:9 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DDI_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A 10:10 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B 11:11 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_DP_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_21_R0 31:12 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22 0x00000016 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR2_22_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23 0x00000017 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A 4:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B 5:5 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS 7:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DUAL_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI 9:9 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DDI_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A 10:10 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B 11:11 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_DP_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_23_R0 31:12 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24 0x00000018 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR3_24_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25 0x00000019 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A 4:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B 5:5 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS 7:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DUAL_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI 9:9 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DDI_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A 10:10 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B 11:11 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_DP_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_25_R0 31:12 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26 0x0000001A +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR4_26_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27 0x0000001B +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A 4:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B 5:5 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS 7:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DUAL_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI 9:9 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DDI_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A 10:10 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B 11:11 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_DP_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_27_R0 31:12 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28 0x0000001C +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR5_28_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29 0x0000001D +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A 4:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B 5:5 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS 7:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DUAL_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI 9:9 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DDI_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A 10:10 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B 11:11 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_DP_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_29_R0 31:12 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30 0x0000001E +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR6_30_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31 0x0000001F +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18 2:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS18_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24 3:3 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_LVDS24_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A 4:4 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B 5:5 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_SINGLE_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS 7:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DUAL_TMDS_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI 9:9 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DDI_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A 10:10 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_A_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B 11:11 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_DP_B_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_31_R0 31:12 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32 0x00000020 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_SOR7_32_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33 0x00000021 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TV_ENC_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_33_R0 31:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34 0x00000022 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR0_34_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35 0x00000023 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TV_ENC_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_35_R0 31:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36 0x00000024 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR1_36_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37 0x00000025 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TV_ENC_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_37_R0 31:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38 0x00000026 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR2_38_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39 0x00000027 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC 1:1 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TV_ENC_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_39_R0 31:7 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40 0x00000028 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_PIOR3_40_R1 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41 0x00000029 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_41_R0 31:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42 0x0000002A +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R1 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_MAX_PIXELS5TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_42_R2 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43 0x0000002B +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R3 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_MAX_PIXELS3TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_43_R4 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44 0x0000002C +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R5 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_MAX_PIXELS2TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_44_R6 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45 0x0000002D +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_45_R7 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46 0x0000002E +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_46_R8 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47 0x0000002F +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_47_R9 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48 0x00000030 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD0_48_R10 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49 0x00000031 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_49_R0 31:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50 0x00000032 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R1 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_MAX_PIXELS5TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_50_R2 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51 0x00000033 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R3 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_MAX_PIXELS3TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_51_R4 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52 0x00000034 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R5 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_MAX_PIXELS2TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_52_R6 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53 0x00000035 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_53_R7 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54 0x00000036 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_54_R8 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55 0x00000037 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_55_R9 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56 0x00000038 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD1_56_R10 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57 0x00000039 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_57_R0 31:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58 0x0000003A +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R1 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_MAX_PIXELS5TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_58_R2 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59 0x0000003B +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R3 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_MAX_PIXELS3TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_59_R4 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60 0x0000003C +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R5 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_MAX_PIXELS2TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_60_R6 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61 0x0000003D +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_61_R7 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62 0x0000003E +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_62_R8 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63 0x0000003F +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_63_R9 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64 0x00000040 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD2_64_R10 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65 0x00000041 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE 0:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_FALSE 0x00000000 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_USABLE_TRUE 0x00000001 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_65_R0 31:2 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66 0x00000042 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R1 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_MAX_PIXELS5TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_66_R2 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67 0x00000043 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R3 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_MAX_PIXELS3TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_67_R4 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68 0x00000044 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP444 14:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R5 15:15 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_MAX_PIXELS2TAP422 30:16 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_68_R6 31:31 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69 0x00000045 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_69_R7 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70 0x00000046 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_70_R8 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71 0x00000047 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_71_R9 31:0 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72 0x00000048 +#define NV887D_CORE_NOTIFIER_2_CAPABILITIES_CAP_HEAD3_72_R10 31:0 + + +// dma opcode instructions +#define NV887D_DMA 0x00000000 +#define NV887D_DMA_OPCODE 31:29 +#define NV887D_DMA_OPCODE_METHOD 0x00000000 +#define NV887D_DMA_OPCODE_JUMP 0x00000001 +#define NV887D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV887D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV887D_DMA_OPCODE 31:29 +#define NV887D_DMA_OPCODE_METHOD 0x00000000 +#define NV887D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV887D_DMA_METHOD_COUNT 27:18 +#define NV887D_DMA_METHOD_OFFSET 11:2 +#define NV887D_DMA_DATA 31:0 +#define NV887D_DMA_NOP 0x00000000 +#define NV887D_DMA_OPCODE 31:29 +#define NV887D_DMA_OPCODE_JUMP 0x00000001 +#define NV887D_DMA_JUMP_OFFSET 11:2 +#define NV887D_DMA_OPCODE 31:29 +#define NV887D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV887D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV887D_PUT (0x00000000) +#define NV887D_PUT_PTR 11:2 +#define NV887D_GET (0x00000004) +#define NV887D_GET_PTR 11:2 +#define NV887D_UPDATE (0x00000080) +#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1 8:8 +#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV887D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV887D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV887D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV887D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV887D_UPDATE_INTERLOCK_WITH_BASE1 9:9 +#define NV887D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV887D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1 10:10 +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 11:11 +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV887D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV887D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV887D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV887D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV887D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV887D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV887D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV887D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV887D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV887D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV887D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV887D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV887D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV887D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV887D_GET_CAPABILITIES (0x0000008C) +#define NV887D_GET_CAPABILITIES_DUMMY 31:0 +#define NV887D_SET_SPARE (0x000003BC) +#define NV887D_SET_SPARE_UNUSED 31:0 +#define NV887D_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV887D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV887D_DAC_SET_CONTROL(a) (0x00000400 + (a)*0x00000080) +#define NV887D_DAC_SET_CONTROL_OWNER 3:0 +#define NV887D_DAC_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV887D_DAC_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV887D_DAC_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV887D_DAC_SET_CONTROL_SUB_OWNER 5:4 +#define NV887D_DAC_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV887D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV887D_DAC_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV887D_DAC_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV887D_DAC_SET_CONTROL_PROTOCOL 13:8 +#define NV887D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV887D_DAC_SET_CONTROL_PROTOCOL_CUSTOM (0x0000003F) +#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD 14:14 +#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_FALSE (0x00000000) +#define NV887D_DAC_SET_CONTROL_INVALIDATE_FIRST_FIELD_TRUE (0x00000001) +#define NV887D_DAC_SET_POLARITY(a) (0x00000404 + (a)*0x00000080) +#define NV887D_DAC_SET_POLARITY_HSYNC 0:0 +#define NV887D_DAC_SET_POLARITY_HSYNC_POSITIVE_TRUE (0x00000000) +#define NV887D_DAC_SET_POLARITY_HSYNC_NEGATIVE_TRUE (0x00000001) +#define NV887D_DAC_SET_POLARITY_VSYNC 1:1 +#define NV887D_DAC_SET_POLARITY_VSYNC_POSITIVE_TRUE (0x00000000) +#define NV887D_DAC_SET_POLARITY_VSYNC_NEGATIVE_TRUE (0x00000001) +#define NV887D_DAC_SET_POLARITY_RESERVED 31:2 +#define NV887D_DAC_SET_ENCODE_QUALITY(a) (0x00000420 + (a)*0x00000080) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS 7:7 +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_3_375 (0x00000000) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_FILTER_BANDPASS_BW_6_75 (0x00000001) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN 2:0 +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0 (0x00000000) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_0625 (0x00000001) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_125 (0x00000002) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_25 (0x00000003) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_0_5 (0x00000004) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_GAIN_GN_1_0 (0x00000005) +#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN 6:4 +#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0 (0x00000000) +#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_0625 (0x00000001) +#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_125 (0x00000002) +#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_25 (0x00000003) +#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_0_5 (0x00000004) +#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_GAIN_GN_1_0 (0x00000005) +#define NV887D_DAC_SET_ENCODE_QUALITY_NOISE_THRSH 15:8 +#define NV887D_DAC_SET_ENCODE_QUALITY_SHARPEN_THRSH 23:16 +#define NV887D_DAC_SET_ENCODE_QUALITY_TINT 31:24 +#define NV887D_DAC_UPDATE_ENCODER_PRESET(a) (0x0000047C + (a)*0x00000080) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL 5:0 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_RGB_CRT (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_M (0x00000001) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_NTSC_J (0x00000002) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_BDGHI (0x00000003) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_M (0x00000004) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_N (0x00000005) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CPST_PAL_CN (0x00000006) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_M (0x00000007) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_NTSC_J (0x00000008) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_BDGHI (0x00000009) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_M (0x0000000A) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_N (0x0000000B) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_PAL_CN (0x0000000C) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_480P_60 (0x0000000D) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_576P_50 (0x0000000E) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_50 (0x0000000F) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_720P_60 (0x00000010) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_50 (0x00000011) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_COMP_1080I_60 (0x00000012) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_PROTOCOL_CUSTOM (0x0000003F) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT 6:6 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_RGB (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FORMAT_YUV (0x00000001) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R 7:7 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_DISABLE (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_R_ENABLE (0x00000001) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G 8:8 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_DISABLE (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_G_ENABLE (0x00000001) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B 9:9 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_DISABLE (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_ENABLE_SYNC_ON_B_ENABLE (0x00000001) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH 12:10 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NONE (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_358 (0x00000001) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_358 (0x00000002) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_NARROW_443 (0x00000003) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_LUMA_NOTCH_WIDE_443 (0x00000004) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW 13:13 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_0_6 (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_CHROMA_BW_NARROW_BW_1_4 (0x00000001) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER 15:15 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_NARROW (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_CPST_FILTER_WIDE (0x00000001) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER 16:16 +#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_NARROW (0x00000000) +#define NV887D_DAC_UPDATE_ENCODER_PRESET_COMP_FILTER_WIDE (0x00000001) + +#define NV887D_SOR_SET_CONTROL(a) (0x00000600 + (a)*0x00000040) +#define NV887D_SOR_SET_CONTROL_OWNER 3:0 +#define NV887D_SOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV887D_SOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV887D_SOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV887D_SOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV887D_SOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV887D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV887D_SOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV887D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV887D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB (0x00000003) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS (0x00000004) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT (0x00000007) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV887D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV887D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV887D_PIOR_SET_CONTROL(a) (0x00000700 + (a)*0x00000040) +#define NV887D_PIOR_SET_CONTROL_OWNER 3:0 +#define NV887D_PIOR_SET_CONTROL_OWNER_NONE (0x00000000) +#define NV887D_PIOR_SET_CONTROL_OWNER_HEAD0 (0x00000001) +#define NV887D_PIOR_SET_CONTROL_OWNER_HEAD1 (0x00000002) +#define NV887D_PIOR_SET_CONTROL_SUB_OWNER 5:4 +#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_NONE (0x00000000) +#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV887D_PIOR_SET_CONTROL_SUB_OWNER_BOTH (0x00000003) +#define NV887D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV887D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV887D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY 12:12 +#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY 13:13 +#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV887D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH 19:16 +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV887D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444 (0x00000009) + +#define NV887D_HEAD_SET_PRESENT_CONTROL(a) (0x00000800 + (a)*0x00000400) +#define NV887D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV887D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV887D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV887D_HEAD_SET_PIXEL_CLOCK(a) (0x00000804 + (a)*0x00000400) +#define NV887D_HEAD_SET_PIXEL_CLOCK_FREQUENCY 21:0 +#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE 23:22 +#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_25 (0x00000000) +#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_28 (0x00000001) +#define NV887D_HEAD_SET_PIXEL_CLOCK_MODE_CLK_CUSTOM (0x00000002) +#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001 24:24 +#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_FALSE (0x00000000) +#define NV887D_HEAD_SET_PIXEL_CLOCK_ADJ1000DIV1001_TRUE (0x00000001) +#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER 25:25 +#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_FALSE (0x00000000) +#define NV887D_HEAD_SET_PIXEL_CLOCK_NOT_DRIVER_TRUE (0x00000001) +#define NV887D_HEAD_SET_CONTROL(a) (0x00000808 + (a)*0x00000400) +#define NV887D_HEAD_SET_CONTROL_STRUCTURE 2:1 +#define NV887D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV887D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV887D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000810 + (a)*0x00000400) +#define NV887D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV887D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV887D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV887D_HEAD_SET_RASTER_SIZE(a) (0x00000814 + (a)*0x00000400) +#define NV887D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV887D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV887D_HEAD_SET_RASTER_SYNC_END(a) (0x00000818 + (a)*0x00000400) +#define NV887D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV887D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV887D_HEAD_SET_RASTER_BLANK_END(a) (0x0000081C + (a)*0x00000400) +#define NV887D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV887D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV887D_HEAD_SET_RASTER_BLANK_START(a) (0x00000820 + (a)*0x00000400) +#define NV887D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV887D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV887D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000824 + (a)*0x00000400) +#define NV887D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV887D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV887D_HEAD_SET_RASTER_VERT_BLANK_DMI(a) (0x00000828 + (a)*0x00000400) +#define NV887D_HEAD_SET_RASTER_VERT_BLANK_DMI_DURATION 11:0 +#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000082C + (a)*0x00000400) +#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV887D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV887D_HEAD_SET_BASE_LUT_LO(a) (0x00000840 + (a)*0x00000400) +#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV887D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV887D_HEAD_SET_BASE_LUT_LO_MODE 30:30 +#define NV887D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV887D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV887D_HEAD_SET_BASE_LUT_LO_ORIGIN 7:2 +#define NV887D_HEAD_SET_BASE_LUT_HI(a) (0x00000844 + (a)*0x00000400) +#define NV887D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV887D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000848 + (a)*0x00000400) +#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE 30:30 +#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV887D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV887D_HEAD_SET_OUTPUT_LUT_LO_ORIGIN 7:2 +#define NV887D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000084C + (a)*0x00000400) +#define NV887D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV887D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000085C + (a)*0x00000400) +#define NV887D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV887D_HEAD_SET_OFFSET(a,b) (0x00000860 + (a)*0x00000400 + (b)*0x00000004) +#define NV887D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV887D_HEAD_SET_SIZE(a) (0x00000868 + (a)*0x00000400) +#define NV887D_HEAD_SET_SIZE_WIDTH 14:0 +#define NV887D_HEAD_SET_SIZE_HEIGHT 30:16 +#define NV887D_HEAD_SET_STORAGE(a) (0x0000086C + (a)*0x00000400) +#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV887D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV887D_HEAD_SET_STORAGE_PITCH 17:8 +#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT 20:20 +#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV887D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV887D_HEAD_SET_PARAMS(a) (0x00000870 + (a)*0x00000400) +#define NV887D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV887D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV887D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV887D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV887D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV887D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV887D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV887D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV887D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV887D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV887D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV887D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV887D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV887D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV887D_HEAD_SET_PARAMS_RESERVED0 22:16 +#define NV887D_HEAD_SET_PARAMS_RESERVED1 24:24 +#define NV887D_HEAD_SET_CONTEXT_DMAS_ISO(a,b) (0x00000874 + (a)*0x00000400 + (b)*0x00000004) +#define NV887D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV887D_HEAD_SET_CONTROL_CURSOR(a) (0x00000880 + (a)*0x00000400) +#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV887D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV887D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV887D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV887D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV887D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV887D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER 5:4 +#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_NONE (0x00000000) +#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD0 (0x00000001) +#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_SUBHEAD1 (0x00000002) +#define NV887D_HEAD_SET_CONTROL_CURSOR_SUB_OWNER_BOTH (0x00000003) +#define NV887D_HEAD_SET_OFFSET_CURSOR(a) (0x00000884 + (a)*0x00000400) +#define NV887D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV887D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000089C + (a)*0x00000400) +#define NV887D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NV887D_HEAD_SET_DITHER_CONTROL(a) (0x000008A0 + (a)*0x00000400) +#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV887D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV887D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV887D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV887D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV887D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV887D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV887D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x000008A4 + (a)*0x00000400) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV887D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV887D_HEAD_SET_PROCAMP(a) (0x000008A8 + (a)*0x00000400) +#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV887D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV887D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV887D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV887D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV887D_HEAD_SET_PROCAMP_TRANSITION 4:3 +#define NV887D_HEAD_SET_PROCAMP_TRANSITION_HARD (0x00000000) +#define NV887D_HEAD_SET_PROCAMP_TRANSITION_NTSC (0x00000001) +#define NV887D_HEAD_SET_PROCAMP_TRANSITION_PAL (0x00000002) +#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV887D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV887D_HEAD_SET_VIEWPORT_POINT_IN(a,b) (0x000008C0 + (a)*0x00000400 + (b)*0x00000004) +#define NV887D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV887D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000008C8 + (a)*0x00000400) +#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV887D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000008D4 + (a)*0x00000400) +#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV887D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000008D8 + (a)*0x00000400) +#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000008DC + (a)*0x00000400) +#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV887D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x00000900 + (a)*0x00000400) +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV887D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x00000904 + (a)*0x00000400) +#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV887D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV887D_HEAD_SET_PROCESSING(a) (0x00000910 + (a)*0x00000400) +#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV887D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV887D_HEAD_SET_CONVERSION(a) (0x00000914 + (a)*0x00000400) +#define NV887D_HEAD_SET_CONVERSION_GAIN 15:0 +#define NV887D_HEAD_SET_CONVERSION_OFS 31:16 +#define NV887D_HEAD_SET_SPARE(a) (0x00000BBC + (a)*0x00000400) +#define NV887D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV887D_HEAD_SET_SPARE_NOOP(a,b) (0x00000BC0 + (a)*0x00000400 + (b)*0x00000004) +#define NV887D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl887d_h + diff --git a/Display-Class-Methods/cl907a.h b/Display-Class-Methods/cl907a.h new file mode 100644 index 0000000..c1a23c0 --- /dev/null +++ b/Display-Class-Methods/cl907a.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl907a_h_ +#define _cl907a_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV907A_CURSOR_CHANNEL_PIO (0x0000907A) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetCursorHotSpotPointOut; // 0x00000084 - 0x00000087 + NvV32 Reserved02[0x3DE]; +} GF110DispCursorControlPio; + +#define NV907A_FREE (0x00000008) +#define NV907A_FREE_COUNT 5:0 +#define NV907A_UPDATE (0x00000080) +#define NV907A_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV907A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV907A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT (0x00000084) +#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT_X 15:0 +#define NV907A_SET_CURSOR_HOT_SPOT_POINT_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl907a_h + diff --git a/Display-Class-Methods/cl907b.h b/Display-Class-Methods/cl907b.h new file mode 100644 index 0000000..7450c59 --- /dev/null +++ b/Display-Class-Methods/cl907b.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl907b_h_ +#define _cl907b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV907B_OVERLAY_IMM_CHANNEL_PIO (0x0000907B) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetPointOut; // 0x00000084 - 0x00000087 + NvV32 AwakenOnceFlippedTo; // 0x00000088 - 0x0000008B + NvV32 Reserved02[0x3DD]; +} GF110DispOverlayImmControlPio; + +#define NV907B_FREE (0x00000008) +#define NV907B_FREE_COUNT 5:0 +#define NV907B_UPDATE (0x00000080) +#define NV907B_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV907B_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV907B_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV907B_SET_POINT_OUT (0x00000084) +#define NV907B_SET_POINT_OUT_X 15:0 +#define NV907B_SET_POINT_OUT_Y 31:16 +#define NV907B_AWAKEN_ONCE_FLIPPED_TO (0x00000088) +#define NV907B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT 11:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl907b_h + diff --git a/Display-Class-Methods/cl907c.h b/Display-Class-Methods/cl907c.h new file mode 100644 index 0000000..9f280db --- /dev/null +++ b/Display-Class-Methods/cl907c.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl907c_h_ +#define _cl907c_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV907C_BASE_CHANNEL_DMA (0x0000907C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +// dma opcode instructions +#define NV907C_DMA 0x00000000 +#define NV907C_DMA_OPCODE 31:29 +#define NV907C_DMA_OPCODE_METHOD 0x00000000 +#define NV907C_DMA_OPCODE_JUMP 0x00000001 +#define NV907C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV907C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV907C_DMA_OPCODE 31:29 +#define NV907C_DMA_OPCODE_METHOD 0x00000000 +#define NV907C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV907C_DMA_METHOD_COUNT 27:18 +#define NV907C_DMA_METHOD_OFFSET 11:2 +#define NV907C_DMA_DATA 31:0 +#define NV907C_DMA_DATA_NOP 0x00000000 +#define NV907C_DMA_OPCODE 31:29 +#define NV907C_DMA_OPCODE_JUMP 0x00000001 +#define NV907C_DMA_JUMP_OFFSET 11:2 +#define NV907C_DMA_OPCODE 31:29 +#define NV907C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV907C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV907C_PUT (0x00000000) +#define NV907C_PUT_PTR 11:2 +#define NV907C_GET (0x00000004) +#define NV907C_GET_PTR 11:2 +#define NV907C_GET_SCANLINE (0x00000010) +#define NV907C_GET_SCANLINE_LINE 15:0 +#define NV907C_UPDATE (0x00000080) +#define NV907C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV907C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV907C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV907C_UPDATE_SPECIAL_HANDLING 25:24 +#define NV907C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV907C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV907C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV907C_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV907C_SET_PRESENT_CONTROL (0x00000084) +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV907C_SET_PRESENT_CONTROL_BEGIN_MODE_AT_FRAME (0x00000003) +#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2 +#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NV907C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NV907C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV907C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV907C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV907C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV907C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV907C_SET_SEMAPHORE_CONTROL_DELAY 26:26 +#define NV907C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000) +#define NV907C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001) +#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV907C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV907C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV907C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV907C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV907C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV907C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV907C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV907C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV907C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV907C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV907C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV907C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV907C_SET_NOTIFIER_CONTROL_DELAY 26:26 +#define NV907C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000) +#define NV907C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001) +#define NV907C_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV907C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV907C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV907C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV907C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV907C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV907C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV907C_SET_BASE_LUT_LO (0x000000E0) +#define NV907C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV907C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV907C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV907C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV907C_SET_BASE_LUT_LO_MODE 27:24 +#define NV907C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV907C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV907C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV907C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV907C_SET_BASE_LUT_HI (0x000000E4) +#define NV907C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV907C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV907C_SET_OUTPUT_LUT_LO_ENABLE 31:30 +#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV907C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV907C_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV907C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV907C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV907C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV907C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV907C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV907C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV907C_SET_PROCESSING (0x00000110) +#define NV907C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV907C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV907C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV907C_SET_CONVERSION_RED (0x00000114) +#define NV907C_SET_CONVERSION_RED_GAIN 15:0 +#define NV907C_SET_CONVERSION_RED_OFS 31:16 +#define NV907C_SET_CONVERSION_GRN (0x00000118) +#define NV907C_SET_CONVERSION_GRN_GAIN 15:0 +#define NV907C_SET_CONVERSION_GRN_OFS 31:16 +#define NV907C_SET_CONVERSION_BLU (0x0000011C) +#define NV907C_SET_CONVERSION_BLU_GAIN 15:0 +#define NV907C_SET_CONVERSION_BLU_OFS 31:16 +#define NV907C_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV907C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV907C_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV907C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV907C_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV907C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV907C_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV907C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV907C_SET_CSC_RED2RED (0x00000140) +#define NV907C_SET_CSC_RED2RED_OWNER 31:31 +#define NV907C_SET_CSC_RED2RED_OWNER_CORE (0x00000000) +#define NV907C_SET_CSC_RED2RED_OWNER_BASE (0x00000001) +#define NV907C_SET_CSC_RED2RED_COEFF 18:0 +#define NV907C_SET_CSC_GRN2RED (0x00000144) +#define NV907C_SET_CSC_GRN2RED_COEFF 18:0 +#define NV907C_SET_CSC_BLU2RED (0x00000148) +#define NV907C_SET_CSC_BLU2RED_COEFF 18:0 +#define NV907C_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV907C_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV907C_SET_CSC_RED2GRN (0x00000150) +#define NV907C_SET_CSC_RED2GRN_COEFF 18:0 +#define NV907C_SET_CSC_GRN2GRN (0x00000154) +#define NV907C_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV907C_SET_CSC_BLU2GRN (0x00000158) +#define NV907C_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV907C_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV907C_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV907C_SET_CSC_RED2BLU (0x00000160) +#define NV907C_SET_CSC_RED2BLU_COEFF 18:0 +#define NV907C_SET_CSC_GRN2BLU (0x00000164) +#define NV907C_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV907C_SET_CSC_BLU2BLU (0x00000168) +#define NV907C_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV907C_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV907C_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV907C_SET_SPARE (0x000003BC) +#define NV907C_SET_SPARE_UNUSED 31:0 +#define NV907C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV907C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV907C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004) +#define NV907C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV907C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020) +#define NV907C_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV907C_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV907C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV907C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV907C_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV907C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV907C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020) +#define NV907C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV907C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV907C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV907C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV907C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV907C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV907C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV907C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV907C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl907c_h diff --git a/Display-Class-Methods/cl907d.h b/Display-Class-Methods/cl907d.h new file mode 100644 index 0000000..d2bf4ab --- /dev/null +++ b/Display-Class-Methods/cl907d.h @@ -0,0 +1,1140 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl907d_h_ +#define _cl907d_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV907D_CORE_CHANNEL_DMA (0x0000907D) + +#define NV907D_CORE_NOTIFIER_3 0x00000000 +#define NV907D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV907D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV907D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV907D_CORE_NOTIFIER_3__1 0x00000001 +#define NV907D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV907D_CORE_NOTIFIER_3__2 0x00000002 +#define NV907D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV907D_CORE_NOTIFIER_3__3 0x00000003 +#define NV907D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:27 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:27 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:27 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:27 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:27 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:27 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:27 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV907D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV907D_DMA 0x00000000 +#define NV907D_DMA_OPCODE 31:29 +#define NV907D_DMA_OPCODE_METHOD 0x00000000 +#define NV907D_DMA_OPCODE_JUMP 0x00000001 +#define NV907D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV907D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV907D_DMA_OPCODE 31:29 +#define NV907D_DMA_OPCODE_METHOD 0x00000000 +#define NV907D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV907D_DMA_METHOD_COUNT 27:18 +#define NV907D_DMA_METHOD_OFFSET 11:2 +#define NV907D_DMA_DATA 31:0 +#define NV907D_DMA_DATA_NOP 0x00000000 +#define NV907D_DMA_OPCODE 31:29 +#define NV907D_DMA_OPCODE_JUMP 0x00000001 +#define NV907D_DMA_JUMP_OFFSET 11:2 +#define NV907D_DMA_OPCODE 31:29 +#define NV907D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV907D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV907D_PUT (0x00000000) +#define NV907D_PUT_PTR 11:2 +#define NV907D_GET (0x00000004) +#define NV907D_GET_PTR 11:2 +#define NV907D_UPDATE (0x00000080) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV907D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV907D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV907D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV907D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV907D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV907D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV907D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV907D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV907D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV907D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV907D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV907D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV907D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV907D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV907D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV907D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV907D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV907D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV907D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV907D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV907D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV907D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV907D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV907D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV907D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV907D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV907D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV907D_GET_CAPABILITIES (0x0000008C) +#define NV907D_GET_CAPABILITIES_DUMMY 31:0 +#define NV907D_SET_SPARE (0x0000016C) +#define NV907D_SET_SPARE_UNUSED 31:0 +#define NV907D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV907D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV907D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV907D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV907D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV907D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV907D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV907D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV907D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV907D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV907D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV907D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV907D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV907D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV907D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV907D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV907D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV907D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV907D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV907D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV907D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV907D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV907D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV907D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV907D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV907D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV907D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV907D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV907D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV907D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV907D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV907D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV907D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV907D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV907D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV907D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV907D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV907D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV907D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV907D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV907D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV907D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV907D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV907D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV907D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV907D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV907D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV907D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV907D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV907D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV907D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV907D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV907D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV907D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV907D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV907D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV907D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV907D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV907D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV907D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV907D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV907D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV907D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV907D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV907D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV907D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV907D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV907D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV907D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV907D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV907D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV907D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV907D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV907D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV907D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV907D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV907D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV907D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV907D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV907D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV907D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV907D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV907D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV907D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV907D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV907D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV907D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV907D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV907D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV907D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV907D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV907D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV907D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV907D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV907D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE 26:26 +#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV907D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 13:8 +#define NV907D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 21:16 +#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV907D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV907D_HEAD_SET_OFFSET_CURSOR(a) (0x00000484 + (a)*0x00000300) +#define NV907D_HEAD_SET_OFFSET_CURSOR_ORIGIN 31:0 +#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR(a) (0x0000048C + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTEXT_DMA_CURSOR_HANDLE 31:0 +#define NV907D_HEAD_SET_DITHER_CONTROL(a) (0x00000490 + (a)*0x00000300) +#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV907D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV907D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV907D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV907D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV907D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV907D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV907D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV907D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV907D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV907D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV907D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV907D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV907D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV907D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV907D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV907D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV907D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV907D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV907D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV907D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV907D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV907D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV907D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV907D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV907D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV907D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV907D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV907D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV907D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV907D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV907D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV907D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV907D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV907D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV907D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV907D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV907D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV907D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV907D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV907D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV907D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV907D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV907D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV907D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV907D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV907D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl907d_h diff --git a/Display-Class-Methods/cl907e.h b/Display-Class-Methods/cl907e.h new file mode 100644 index 0000000..631fe6d --- /dev/null +++ b/Display-Class-Methods/cl907e.h @@ -0,0 +1,255 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl907e_h_ +#define _cl907e_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV907E_OVERLAY_CHANNEL_DMA (0x0000907E) + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV907E_DMA 0x00000000 +#define NV907E_DMA_OPCODE 31:29 +#define NV907E_DMA_OPCODE_METHOD 0x00000000 +#define NV907E_DMA_OPCODE_JUMP 0x00000001 +#define NV907E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV907E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV907E_DMA_OPCODE 31:29 +#define NV907E_DMA_OPCODE_METHOD 0x00000000 +#define NV907E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV907E_DMA_METHOD_COUNT 27:18 +#define NV907E_DMA_METHOD_OFFSET 11:2 +#define NV907E_DMA_DATA 31:0 +#define NV907E_DMA_DATA_NOP 0x00000000 +#define NV907E_DMA_OPCODE 31:29 +#define NV907E_DMA_OPCODE_JUMP 0x00000001 +#define NV907E_DMA_JUMP_OFFSET 11:2 +#define NV907E_DMA_OPCODE 31:29 +#define NV907E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV907E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV907E_PUT (0x00000000) +#define NV907E_PUT_PTR 11:2 +#define NV907E_GET (0x00000004) +#define NV907E_GET_PTR 11:2 +#define NV907E_UPDATE (0x00000080) +#define NV907E_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV907E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV907E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV907E_UPDATE_SPECIAL_HANDLING 25:24 +#define NV907E_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV907E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV907E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV907E_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV907E_SET_PRESENT_CONTROL (0x00000084) +#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV907E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV907E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV907E_SET_SEMAPHORE_ACQUIRE (0x00000088) +#define NV907E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV907E_SET_SEMAPHORE_RELEASE (0x0000008C) +#define NV907E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV907E_SET_SEMAPHORE_CONTROL (0x00000090) +#define NV907E_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV907E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV907E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV907E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV907E_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV907E_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV907E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV907E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV907E_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV907E_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV907E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV907E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV907E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV907E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV907E_SET_CONTEXT_DMA_LUT (0x000000B0) +#define NV907E_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV907E_SET_OVERLAY_LUT_LO (0x000000B4) +#define NV907E_SET_OVERLAY_LUT_LO_ENABLE 31:31 +#define NV907E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV907E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV907E_SET_OVERLAY_LUT_LO_MODE 27:24 +#define NV907E_SET_OVERLAY_LUT_LO_MODE_LORES (0x00000000) +#define NV907E_SET_OVERLAY_LUT_LO_MODE_HIRES (0x00000001) +#define NV907E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV907E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV907E_SET_OVERLAY_LUT_HI (0x000000B8) +#define NV907E_SET_OVERLAY_LUT_HI_ORIGIN 31:0 +#define NV907E_SET_CONTEXT_DMA_ISO (0x000000C0) +#define NV907E_SET_CONTEXT_DMA_ISO_HANDLE 31:0 +#define NV907E_SET_POINT_IN (0x000000E0) +#define NV907E_SET_POINT_IN_X 14:0 +#define NV907E_SET_POINT_IN_Y 30:16 +#define NV907E_SET_SIZE_IN (0x000000E4) +#define NV907E_SET_SIZE_IN_WIDTH 14:0 +#define NV907E_SET_SIZE_IN_HEIGHT 30:16 +#define NV907E_SET_SIZE_OUT (0x000000E8) +#define NV907E_SET_SIZE_OUT_WIDTH 14:0 +#define NV907E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV907E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV907E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV907E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV907E_SET_COMPOSITION_CONTROL_MODE_OPAQUE (0x00000002) +#define NV907E_SET_KEY_COLOR_LO (0x00000104) +#define NV907E_SET_KEY_COLOR_LO_COLOR 31:0 +#define NV907E_SET_KEY_COLOR_HI (0x00000108) +#define NV907E_SET_KEY_COLOR_HI_COLOR 31:0 +#define NV907E_SET_KEY_MASK_LO (0x0000010C) +#define NV907E_SET_KEY_MASK_LO_MASK 31:0 +#define NV907E_SET_KEY_MASK_HI (0x00000110) +#define NV907E_SET_KEY_MASK_HI_MASK 31:0 +#define NV907E_SET_PROCESSING (0x00000118) +#define NV907E_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV907E_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV907E_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV907E_SET_CONVERSION_RED (0x0000011C) +#define NV907E_SET_CONVERSION_RED_GAIN 15:0 +#define NV907E_SET_CONVERSION_RED_OFS 31:16 +#define NV907E_SET_CONVERSION_GRN (0x00000120) +#define NV907E_SET_CONVERSION_GRN_GAIN 15:0 +#define NV907E_SET_CONVERSION_GRN_OFS 31:16 +#define NV907E_SET_CONVERSION_BLU (0x00000124) +#define NV907E_SET_CONVERSION_BLU_GAIN 15:0 +#define NV907E_SET_CONVERSION_BLU_OFS 31:16 +#define NV907E_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV907E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV907E_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV907E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV907E_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV907E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV907E_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV907E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV907E_SET_CSC_RED2RED (0x00000140) +#define NV907E_SET_CSC_RED2RED_COEFF 18:0 +#define NV907E_SET_CSC_GRN2RED (0x00000144) +#define NV907E_SET_CSC_GRN2RED_COEFF 18:0 +#define NV907E_SET_CSC_BLU2RED (0x00000148) +#define NV907E_SET_CSC_BLU2RED_COEFF 18:0 +#define NV907E_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV907E_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV907E_SET_CSC_RED2GRN (0x00000150) +#define NV907E_SET_CSC_RED2GRN_COEFF 18:0 +#define NV907E_SET_CSC_GRN2GRN (0x00000154) +#define NV907E_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV907E_SET_CSC_BLU2GRN (0x00000158) +#define NV907E_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV907E_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV907E_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV907E_SET_CSC_RED2BLU (0x00000160) +#define NV907E_SET_CSC_RED2BLU_COEFF 18:0 +#define NV907E_SET_CSC_GRN2BLU (0x00000164) +#define NV907E_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV907E_SET_CSC_BLU2BLU (0x00000168) +#define NV907E_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV907E_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV907E_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV907E_SET_SPARE (0x000003BC) +#define NV907E_SET_SPARE_UNUSED 31:0 +#define NV907E_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV907E_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV907E_SURFACE_SET_OFFSET (0x00000400) +#define NV907E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV907E_SURFACE_SET_SIZE (0x00000408) +#define NV907E_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV907E_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV907E_SURFACE_SET_STORAGE (0x0000040C) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV907E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV907E_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV907E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV907E_SURFACE_SET_PARAMS (0x00000410) +#define NV907E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV907E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV907E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV907E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl907e_h diff --git a/Display-Class-Methods/cl917a.h b/Display-Class-Methods/cl917a.h new file mode 100644 index 0000000..b6d6239 --- /dev/null +++ b/Display-Class-Methods/cl917a.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917a_h_ +#define _cl917a_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917A_CURSOR_CHANNEL_PIO (0x0000917A) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetCursorHotSpotPointsOut[2]; // 0x00000084 - 0x0000008B + NvV32 Reserved02[0x3DD]; +} GK104DispCursorControlPio; + +#define NV917A_FREE (0x00000008) +#define NV917A_FREE_COUNT 5:0 +#define NV917A_UPDATE (0x00000080) +#define NV917A_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917A_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917A_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT(b) (0x00000084 + (b)*0x00000004) +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_X 15:0 +#define NV917A_SET_CURSOR_HOT_SPOT_POINTS_OUT_Y 31:16 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917a_h + diff --git a/Display-Class-Methods/cl917b.h b/Display-Class-Methods/cl917b.h new file mode 100644 index 0000000..05270e2 --- /dev/null +++ b/Display-Class-Methods/cl917b.h @@ -0,0 +1,60 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917b_h_ +#define _cl917b_h_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917B_OVERLAY_IMM_CHANNEL_PIO (0x0000917B) + +typedef volatile struct { + NvV32 Reserved00[0x2]; + NvV32 Free; // 0x00000008 - 0x0000000B + NvV32 Reserved01[0x1D]; + NvV32 Update; // 0x00000080 - 0x00000083 + NvV32 SetPointsOut[2]; // 0x00000084 - 0x0000008B + NvV32 Reserved02[0x1]; + NvV32 AwakenOnceFlippedTo; // 0x00000090 - 0x00000093 + NvV32 Reserved03[0x3DB]; +} GK104DispOverlayImmControlPio; + +#define NV917B_FREE (0x00000008) +#define NV917B_FREE_COUNT 5:0 +#define NV917B_UPDATE (0x00000080) +#define NV917B_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917B_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917B_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917B_SET_POINTS_OUT(b) (0x00000084 + (b)*0x00000004) +#define NV917B_SET_POINTS_OUT_X 15:0 +#define NV917B_SET_POINTS_OUT_Y 31:16 +#define NV917B_AWAKEN_ONCE_FLIPPED_TO (0x00000090) +#define NV917B_AWAKEN_ONCE_FLIPPED_TO_AWAKEN_COUNT 11:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917b_h + diff --git a/Display-Class-Methods/cl917c.h b/Display-Class-Methods/cl917c.h new file mode 100644 index 0000000..9870f36 --- /dev/null +++ b/Display-Class-Methods/cl917c.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917c_h_ +#define _cl917c_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917C_BASE_CHANNEL_DMA (0x0000917C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV917C_DMA 0x00000000 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_METHOD 0x00000000 +#define NV917C_DMA_OPCODE_JUMP 0x00000001 +#define NV917C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_METHOD 0x00000000 +#define NV917C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917C_DMA_METHOD_COUNT 27:18 +#define NV917C_DMA_METHOD_OFFSET 11:2 +#define NV917C_DMA_DATA 31:0 +#define NV917C_DMA_DATA_NOP 0x00000000 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_JUMP 0x00000001 +#define NV917C_DMA_JUMP_OFFSET 11:2 +#define NV917C_DMA_OPCODE 31:29 +#define NV917C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917C_PUT (0x00000000) +#define NV917C_PUT_PTR 11:2 +#define NV917C_GET (0x00000004) +#define NV917C_GET_PTR 11:2 +#define NV917C_GET_SCANLINE (0x00000010) +#define NV917C_GET_SCANLINE_LINE 15:0 +#define NV917C_UPDATE (0x00000080) +#define NV917C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917C_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917C_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917C_SET_PRESENT_CONTROL (0x00000084) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2 +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NV917C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NV917C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV917C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV917C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV917C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV917C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY 26:26 +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000) +#define NV917C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001) +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV917C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV917C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV917C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV917C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV917C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV917C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV917C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917C_SET_NOTIFIER_CONTROL_DELAY 26:26 +#define NV917C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001) +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV917C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV917C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917C_SET_BASE_LUT_LO (0x000000E0) +#define NV917C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV917C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV917C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV917C_SET_BASE_LUT_LO_MODE 27:24 +#define NV917C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV917C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV917C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917C_SET_BASE_LUT_HI (0x000000E4) +#define NV917C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV917C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE 31:30 +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV917C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV917C_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV917C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV917C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV917C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV917C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917C_SET_PROCESSING (0x00000110) +#define NV917C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917C_SET_CONVERSION_RED (0x00000114) +#define NV917C_SET_CONVERSION_RED_GAIN 15:0 +#define NV917C_SET_CONVERSION_RED_OFS 31:16 +#define NV917C_SET_CONVERSION_GRN (0x00000118) +#define NV917C_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917C_SET_CONVERSION_GRN_OFS 31:16 +#define NV917C_SET_CONVERSION_BLU (0x0000011C) +#define NV917C_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917C_SET_CONVERSION_BLU_OFS 31:16 +#define NV917C_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV917C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV917C_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV917C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV917C_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV917C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV917C_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV917C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV917C_SET_CSC_RED2RED (0x00000140) +#define NV917C_SET_CSC_RED2RED_OWNER 31:31 +#define NV917C_SET_CSC_RED2RED_OWNER_CORE (0x00000000) +#define NV917C_SET_CSC_RED2RED_OWNER_BASE (0x00000001) +#define NV917C_SET_CSC_RED2RED_COEFF 18:0 +#define NV917C_SET_CSC_GRN2RED (0x00000144) +#define NV917C_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917C_SET_CSC_BLU2RED (0x00000148) +#define NV917C_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV917C_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917C_SET_CSC_RED2GRN (0x00000150) +#define NV917C_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917C_SET_CSC_GRN2GRN (0x00000154) +#define NV917C_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917C_SET_CSC_BLU2GRN (0x00000158) +#define NV917C_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV917C_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917C_SET_CSC_RED2BLU (0x00000160) +#define NV917C_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917C_SET_CSC_GRN2BLU (0x00000164) +#define NV917C_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917C_SET_CSC_BLU2BLU (0x00000168) +#define NV917C_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917C_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV917C_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917C_SET_SPARE (0x000003BC) +#define NV917C_SET_SPARE_UNUSED 31:0 +#define NV917C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV917C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004) +#define NV917C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV917C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020) +#define NV917C_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV917C_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV917C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917C_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020) +#define NV917C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV917C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV917C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV917C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917c_h diff --git a/Display-Class-Methods/cl917d.h b/Display-Class-Methods/cl917d.h new file mode 100644 index 0000000..cf08d92 --- /dev/null +++ b/Display-Class-Methods/cl917d.h @@ -0,0 +1,1176 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917d_h_ +#define _cl917d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917D_CORE_CHANNEL_DMA (0x0000917D) + +#define NV917D_CORE_NOTIFIER_3 0x00000000 +#define NV917D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV917D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV917D_CORE_NOTIFIER_3__1 0x00000001 +#define NV917D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV917D_CORE_NOTIFIER_3__2 0x00000002 +#define NV917D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV917D_CORE_NOTIFIER_3__3 0x00000003 +#define NV917D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:27 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV917D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV917D_DMA 0x00000000 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_METHOD 0x00000000 +#define NV917D_DMA_OPCODE_JUMP 0x00000001 +#define NV917D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_METHOD 0x00000000 +#define NV917D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917D_DMA_METHOD_COUNT 27:18 +#define NV917D_DMA_METHOD_OFFSET 11:2 +#define NV917D_DMA_DATA 31:0 +#define NV917D_DMA_DATA_NOP 0x00000000 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_JUMP 0x00000001 +#define NV917D_DMA_JUMP_OFFSET 11:2 +#define NV917D_DMA_OPCODE 31:29 +#define NV917D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917D_PUT (0x00000000) +#define NV917D_PUT_PTR 11:2 +#define NV917D_GET (0x00000004) +#define NV917D_GET_PTR 11:2 +#define NV917D_UPDATE (0x00000080) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV917D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV917D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV917D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV917D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV917D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV917D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV917D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV917D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV917D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917D_GET_CAPABILITIES (0x0000008C) +#define NV917D_GET_CAPABILITIES_DUMMY 31:0 +#define NV917D_SET_SPARE (0x0000016C) +#define NV917D_SET_SPARE_UNUSED 31:0 +#define NV917D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV917D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV917D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV917D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV917D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV917D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV917D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV917D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV917D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV917D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV917D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV917D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV917D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV917D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV917D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV917D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV917D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV917D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV917D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV917D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV917D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV917D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV917D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV917D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV917D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV917D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV917D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV917D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV917D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV917D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV917D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV917D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV917D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV917D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV917D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV917D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV917D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV917D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV917D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV917D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV917D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV917D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV917D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV917D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV917D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV917D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV917D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV917D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV917D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV917D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV917D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV917D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV917D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV917D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV917D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV917D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV917D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV917D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV917D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV917D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV917D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV917D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV917D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV917D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV917D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV917D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV917D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV917D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV917D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV917D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV917D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV917D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV917D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV917D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV917D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV917D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV917D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV917D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV917D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV917D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV917D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917d_h diff --git a/Display-Class-Methods/cl917e.h b/Display-Class-Methods/cl917e.h new file mode 100644 index 0000000..ad6423c --- /dev/null +++ b/Display-Class-Methods/cl917e.h @@ -0,0 +1,257 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl917e_h_ +#define _cl917e_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV917E_OVERLAY_CHANNEL_DMA (0x0000917E) + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV917E_DMA 0x00000000 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_METHOD 0x00000000 +#define NV917E_DMA_OPCODE_JUMP 0x00000001 +#define NV917E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_METHOD 0x00000000 +#define NV917E_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV917E_DMA_METHOD_COUNT 27:18 +#define NV917E_DMA_METHOD_OFFSET 11:2 +#define NV917E_DMA_DATA 31:0 +#define NV917E_DMA_DATA_NOP 0x00000000 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_JUMP 0x00000001 +#define NV917E_DMA_JUMP_OFFSET 11:2 +#define NV917E_DMA_OPCODE 31:29 +#define NV917E_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV917E_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV917E_PUT (0x00000000) +#define NV917E_PUT_PTR 11:2 +#define NV917E_GET (0x00000004) +#define NV917E_GET_PTR 11:2 +#define NV917E_UPDATE (0x00000080) +#define NV917E_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV917E_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV917E_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV917E_UPDATE_SPECIAL_HANDLING 25:24 +#define NV917E_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV917E_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV917E_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV917E_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV917E_SET_PRESENT_CONTROL (0x00000084) +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE 1:0 +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_ASAP (0x00000000) +#define NV917E_SET_PRESENT_CONTROL_BEGIN_MODE_TIMESTAMP (0x00000003) +#define NV917E_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV917E_SET_SEMAPHORE_ACQUIRE (0x00000088) +#define NV917E_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV917E_SET_SEMAPHORE_RELEASE (0x0000008C) +#define NV917E_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV917E_SET_SEMAPHORE_CONTROL (0x00000090) +#define NV917E_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917E_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917E_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV917E_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV917E_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV917E_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV917E_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV917E_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV917E_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV917E_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV917E_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV917E_SET_CONTEXT_DMA_LUT (0x000000B0) +#define NV917E_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV917E_SET_OVERLAY_LUT_LO (0x000000B4) +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE 31:31 +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV917E_SET_OVERLAY_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV917E_SET_OVERLAY_LUT_LO_MODE 27:24 +#define NV917E_SET_OVERLAY_LUT_LO_MODE_LORES (0x00000000) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_HIRES (0x00000001) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV917E_SET_OVERLAY_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV917E_SET_OVERLAY_LUT_HI (0x000000B8) +#define NV917E_SET_OVERLAY_LUT_HI_ORIGIN 31:0 +#define NV917E_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV917E_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV917E_SET_POINT_IN (0x000000E0) +#define NV917E_SET_POINT_IN_X 14:0 +#define NV917E_SET_POINT_IN_Y 30:16 +#define NV917E_SET_SIZE_IN (0x000000E4) +#define NV917E_SET_SIZE_IN_WIDTH 14:0 +#define NV917E_SET_SIZE_IN_HEIGHT 30:16 +#define NV917E_SET_SIZE_OUT (0x000000E8) +#define NV917E_SET_SIZE_OUT_WIDTH 14:0 +#define NV917E_SET_COMPOSITION_CONTROL (0x00000100) +#define NV917E_SET_COMPOSITION_CONTROL_MODE 3:0 +#define NV917E_SET_COMPOSITION_CONTROL_MODE_SOURCE_COLOR_VALUE_KEYING (0x00000000) +#define NV917E_SET_COMPOSITION_CONTROL_MODE_DESTINATION_COLOR_VALUE_KEYING (0x00000001) +#define NV917E_SET_COMPOSITION_CONTROL_MODE_OPAQUE (0x00000002) +#define NV917E_SET_KEY_COLOR_LO (0x00000104) +#define NV917E_SET_KEY_COLOR_LO_COLOR 31:0 +#define NV917E_SET_KEY_COLOR_HI (0x00000108) +#define NV917E_SET_KEY_COLOR_HI_COLOR 31:0 +#define NV917E_SET_KEY_MASK_LO (0x0000010C) +#define NV917E_SET_KEY_MASK_LO_MASK 31:0 +#define NV917E_SET_KEY_MASK_HI (0x00000110) +#define NV917E_SET_KEY_MASK_HI_MASK 31:0 +#define NV917E_SET_PROCESSING (0x00000118) +#define NV917E_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV917E_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV917E_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV917E_SET_CONVERSION_RED (0x0000011C) +#define NV917E_SET_CONVERSION_RED_GAIN 15:0 +#define NV917E_SET_CONVERSION_RED_OFS 31:16 +#define NV917E_SET_CONVERSION_GRN (0x00000120) +#define NV917E_SET_CONVERSION_GRN_GAIN 15:0 +#define NV917E_SET_CONVERSION_GRN_OFS 31:16 +#define NV917E_SET_CONVERSION_BLU (0x00000124) +#define NV917E_SET_CONVERSION_BLU_GAIN 15:0 +#define NV917E_SET_CONVERSION_BLU_OFS 31:16 +#define NV917E_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV917E_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV917E_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV917E_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV917E_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV917E_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV917E_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV917E_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV917E_SET_CSC_RED2RED (0x00000140) +#define NV917E_SET_CSC_RED2RED_COEFF 18:0 +#define NV917E_SET_CSC_GRN2RED (0x00000144) +#define NV917E_SET_CSC_GRN2RED_COEFF 18:0 +#define NV917E_SET_CSC_BLU2RED (0x00000148) +#define NV917E_SET_CSC_BLU2RED_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV917E_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV917E_SET_CSC_RED2GRN (0x00000150) +#define NV917E_SET_CSC_RED2GRN_COEFF 18:0 +#define NV917E_SET_CSC_GRN2GRN (0x00000154) +#define NV917E_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV917E_SET_CSC_BLU2GRN (0x00000158) +#define NV917E_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV917E_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV917E_SET_CSC_RED2BLU (0x00000160) +#define NV917E_SET_CSC_RED2BLU_COEFF 18:0 +#define NV917E_SET_CSC_GRN2BLU (0x00000164) +#define NV917E_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV917E_SET_CSC_BLU2BLU (0x00000168) +#define NV917E_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV917E_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV917E_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV917E_SET_SPARE (0x000003BC) +#define NV917E_SET_SPARE_UNUSED 31:0 +#define NV917E_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV917E_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV917E_SURFACE_SET_OFFSET(b) (0x00000400 + (b)*0x00000004) +#define NV917E_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV917E_SURFACE_SET_SIZE (0x00000408) +#define NV917E_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV917E_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV917E_SURFACE_SET_STORAGE (0x0000040C) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV917E_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV917E_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV917E_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV917E_SURFACE_SET_PARAMS (0x00000410) +#define NV917E_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV917E_SURFACE_SET_PARAMS_FORMAT_VE8YO8UE8YE8 (0x00000028) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_YO8VE8YE8UE8 (0x00000029) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV917E_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE 1:0 +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_RGB (0x00000000) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_601 (0x00000001) +#define NV917E_SURFACE_SET_PARAMS_COLOR_SPACE_YUV_709 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl917e_h diff --git a/Display-Class-Methods/cl927c.h b/Display-Class-Methods/cl927c.h new file mode 100644 index 0000000..2cd1e47 --- /dev/null +++ b/Display-Class-Methods/cl927c.h @@ -0,0 +1,291 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl927c_h_ +#define _cl927c_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV927C_BASE_CHANNEL_DMA (0x0000927C) + +#define NV_DISP_BASE_NOTIFIER_1 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1_SIZEOF 0x00000004 +#define NV_DISP_BASE_NOTIFIER_1__0 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_PRESENTATION_COUNT 15:0 +#define NV_DISP_BASE_NOTIFIER_1__0_TIMESTAMP 29:16 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS 31:30 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_NOT_BEGUN 0x00000000 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_BEGUN 0x00000001 +#define NV_DISP_BASE_NOTIFIER_1__0_STATUS_FINISHED 0x00000002 + + +#define NV_DISP_NOTIFICATION_2 0x00000000 +#define NV_DISP_NOTIFICATION_2_SIZEOF 0x00000010 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0 0x00000000 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_0_NANOSECONDS0 31:0 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1 0x00000001 +#define NV_DISP_NOTIFICATION_2_TIME_STAMP_1_NANOSECONDS1 31:0 +#define NV_DISP_NOTIFICATION_2_INFO32_2 0x00000002 +#define NV_DISP_NOTIFICATION_2_INFO32_2_R0 31:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3 0x00000003 +#define NV_DISP_NOTIFICATION_2_INFO16_3_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_2_INFO16_3_FIELD 8:8 +#define NV_DISP_NOTIFICATION_2_INFO16_3_R1 15:9 +#define NV_DISP_NOTIFICATION_2__3_STATUS 31:16 +#define NV_DISP_NOTIFICATION_2__3_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_2__3_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_2__3_STATUS_FINISHED 0x00000000 + + +#define NV_DISP_NOTIFICATION_INFO16 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_INFO16__0 0x00000000 +#define NV_DISP_NOTIFICATION_INFO16__0_PRESENT_COUNT 7:0 +#define NV_DISP_NOTIFICATION_INFO16__0_FIELD 8:8 +#define NV_DISP_NOTIFICATION_INFO16__0_R1 15:9 + + +#define NV_DISP_NOTIFICATION_STATUS 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS_SIZEOF 0x00000002 +#define NV_DISP_NOTIFICATION_STATUS__0 0x00000000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS 15:0 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_NOT_BEGUN 0x00008000 +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_BEGUN 0x0000FFFF +#define NV_DISP_NOTIFICATION_STATUS__0_STATUS_FINISHED 0x00000000 + + +// dma opcode instructions +#define NV927C_DMA 0x00000000 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_METHOD 0x00000000 +#define NV927C_DMA_OPCODE_JUMP 0x00000001 +#define NV927C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_METHOD 0x00000000 +#define NV927C_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927C_DMA_METHOD_COUNT 27:18 +#define NV927C_DMA_METHOD_OFFSET 11:2 +#define NV927C_DMA_DATA 31:0 +#define NV927C_DMA_DATA_NOP 0x00000000 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_JUMP 0x00000001 +#define NV927C_DMA_JUMP_OFFSET 11:2 +#define NV927C_DMA_OPCODE 31:29 +#define NV927C_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927C_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV927C_PUT (0x00000000) +#define NV927C_PUT_PTR 11:2 +#define NV927C_GET (0x00000004) +#define NV927C_GET_PTR 11:2 +#define NV927C_GET_SCANLINE (0x00000010) +#define NV927C_GET_SCANLINE_LINE 15:0 +#define NV927C_UPDATE (0x00000080) +#define NV927C_UPDATE_INTERLOCK_WITH_CORE 0:0 +#define NV927C_UPDATE_INTERLOCK_WITH_CORE_DISABLE (0x00000000) +#define NV927C_UPDATE_INTERLOCK_WITH_CORE_ENABLE (0x00000001) +#define NV927C_UPDATE_SPECIAL_HANDLING 25:24 +#define NV927C_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV927C_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV927C_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV927C_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV927C_SET_PRESENT_CONTROL (0x00000084) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE 9:8 +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_NON_TEARING (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_IMMEDIATE (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_BEGIN_MODE_ON_LINE (0x00000002) +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE 2:2 +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_DISABLE (0x00000000) +#define NV927C_SET_PRESENT_CONTROL_TIMESTAMP_MODE_ENABLE (0x00000001) +#define NV927C_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 7:4 +#define NV927C_SET_PRESENT_CONTROL_BEGIN_LINE 30:16 +#define NV927C_SET_PRESENT_CONTROL_ON_LINE_MARGIN 15:10 +#define NV927C_SET_SEMAPHORE_CONTROL (0x00000088) +#define NV927C_SET_SEMAPHORE_CONTROL_OFFSET 11:2 +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY 26:26 +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_DISABLE (0x00000000) +#define NV927C_SET_SEMAPHORE_CONTROL_DELAY_ENABLE (0x00000001) +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT 28:28 +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927C_SET_SEMAPHORE_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927C_SET_SEMAPHORE_ACQUIRE (0x0000008C) +#define NV927C_SET_SEMAPHORE_ACQUIRE_VALUE 31:0 +#define NV927C_SET_SEMAPHORE_RELEASE (0x00000090) +#define NV927C_SET_SEMAPHORE_RELEASE_VALUE 31:0 +#define NV927C_SET_CONTEXT_DMA_SEMAPHORE (0x00000094) +#define NV927C_SET_CONTEXT_DMA_SEMAPHORE_HANDLE 31:0 +#define NV927C_SET_NOTIFIER_CONTROL (0x000000A0) +#define NV927C_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV927C_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV927C_SET_NOTIFIER_CONTROL_DELAY 26:26 +#define NV927C_SET_NOTIFIER_CONTROL_DELAY_DISABLE (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_DELAY_ENABLE (0x00000001) +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927C_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927C_SET_CONTEXT_DMA_NOTIFIER (0x000000A4) +#define NV927C_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV927C_SET_CONTEXT_DMAS_ISO(b) (0x000000C0 + (b)*0x00000004) +#define NV927C_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV927C_SET_BASE_LUT_LO (0x000000E0) +#define NV927C_SET_BASE_LUT_LO_ENABLE 31:30 +#define NV927C_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927C_SET_BASE_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV927C_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV927C_SET_BASE_LUT_LO_MODE 27:24 +#define NV927C_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV927C_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV927C_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927C_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927C_SET_BASE_LUT_HI (0x000000E4) +#define NV927C_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV927C_SET_OUTPUT_LUT_LO (0x000000E8) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE 31:30 +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT (0x00000001) +#define NV927C_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000002) +#define NV927C_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV927C_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927C_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927C_SET_OUTPUT_LUT_HI (0x000000EC) +#define NV927C_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV927C_SET_CONTEXT_DMA_LUT (0x000000FC) +#define NV927C_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV927C_SET_PROCESSING (0x00000110) +#define NV927C_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV927C_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV927C_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV927C_SET_CONVERSION_RED (0x00000114) +#define NV927C_SET_CONVERSION_RED_GAIN 15:0 +#define NV927C_SET_CONVERSION_RED_OFS 31:16 +#define NV927C_SET_CONVERSION_GRN (0x00000118) +#define NV927C_SET_CONVERSION_GRN_GAIN 15:0 +#define NV927C_SET_CONVERSION_GRN_OFS 31:16 +#define NV927C_SET_CONVERSION_BLU (0x0000011C) +#define NV927C_SET_CONVERSION_BLU_GAIN 15:0 +#define NV927C_SET_CONVERSION_BLU_OFS 31:16 +#define NV927C_SET_TIMESTAMP_ORIGIN_LO (0x00000130) +#define NV927C_SET_TIMESTAMP_ORIGIN_LO_TIMESTAMP_LO 31:0 +#define NV927C_SET_TIMESTAMP_ORIGIN_HI (0x00000134) +#define NV927C_SET_TIMESTAMP_ORIGIN_HI_TIMESTAMP_HI 31:0 +#define NV927C_SET_UPDATE_TIMESTAMP_LO (0x00000138) +#define NV927C_SET_UPDATE_TIMESTAMP_LO_TIMESTAMP_LO 31:0 +#define NV927C_SET_UPDATE_TIMESTAMP_HI (0x0000013C) +#define NV927C_SET_UPDATE_TIMESTAMP_HI_TIMESTAMP_HI 31:0 +#define NV927C_SET_CSC_RED2RED (0x00000140) +#define NV927C_SET_CSC_RED2RED_OWNER 31:31 +#define NV927C_SET_CSC_RED2RED_OWNER_CORE (0x00000000) +#define NV927C_SET_CSC_RED2RED_OWNER_BASE (0x00000001) +#define NV927C_SET_CSC_RED2RED_COEFF 18:0 +#define NV927C_SET_CSC_GRN2RED (0x00000144) +#define NV927C_SET_CSC_GRN2RED_COEFF 18:0 +#define NV927C_SET_CSC_BLU2RED (0x00000148) +#define NV927C_SET_CSC_BLU2RED_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2RED (0x0000014C) +#define NV927C_SET_CSC_CONSTANT2RED_COEFF 18:0 +#define NV927C_SET_CSC_RED2GRN (0x00000150) +#define NV927C_SET_CSC_RED2GRN_COEFF 18:0 +#define NV927C_SET_CSC_GRN2GRN (0x00000154) +#define NV927C_SET_CSC_GRN2GRN_COEFF 18:0 +#define NV927C_SET_CSC_BLU2GRN (0x00000158) +#define NV927C_SET_CSC_BLU2GRN_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2GRN (0x0000015C) +#define NV927C_SET_CSC_CONSTANT2GRN_COEFF 18:0 +#define NV927C_SET_CSC_RED2BLU (0x00000160) +#define NV927C_SET_CSC_RED2BLU_COEFF 18:0 +#define NV927C_SET_CSC_GRN2BLU (0x00000164) +#define NV927C_SET_CSC_GRN2BLU_COEFF 18:0 +#define NV927C_SET_CSC_BLU2BLU (0x00000168) +#define NV927C_SET_CSC_BLU2BLU_COEFF 18:0 +#define NV927C_SET_CSC_CONSTANT2BLU (0x0000016C) +#define NV927C_SET_CSC_CONSTANT2BLU_COEFF 18:0 +#define NV927C_SET_SPARE (0x000003BC) +#define NV927C_SET_SPARE_UNUSED 31:0 +#define NV927C_SET_SPARE_NOOP(b) (0x000003C0 + (b)*0x00000004) +#define NV927C_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV927C_SURFACE_SET_OFFSET(a,b) (0x00000400 + (a)*0x00000020 + (b)*0x00000004) +#define NV927C_SURFACE_SET_OFFSET_ORIGIN 31:0 +#define NV927C_SURFACE_SET_SIZE(a) (0x00000408 + (a)*0x00000020) +#define NV927C_SURFACE_SET_SIZE_WIDTH 15:0 +#define NV927C_SURFACE_SET_SIZE_HEIGHT 31:16 +#define NV927C_SURFACE_SET_STORAGE(a) (0x0000040C + (a)*0x00000020) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV927C_SURFACE_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV927C_SURFACE_SET_STORAGE_PITCH 20:8 +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV927C_SURFACE_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV927C_SURFACE_SET_PARAMS(a) (0x00000410 + (a)*0x00000020) +#define NV927C_SURFACE_SET_PARAMS_FORMAT 15:8 +#define NV927C_SURFACE_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV927C_SURFACE_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927C_SURFACE_SET_PARAMS_GAMMA 2:2 +#define NV927C_SURFACE_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT 5:4 +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FRM (0x00000000) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD1 (0x00000001) +#define NV927C_SURFACE_SET_PARAMS_LAYOUT_FLD2 (0x00000002) + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl927c_h diff --git a/Display-Class-Methods/cl927d.h b/Display-Class-Methods/cl927d.h new file mode 100644 index 0000000..4363a79 --- /dev/null +++ b/Display-Class-Methods/cl927d.h @@ -0,0 +1,1181 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl927d_h_ +#define _cl927d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV927D_CORE_CHANNEL_DMA (0x0000927D) + +#define NV927D_CORE_NOTIFIER_3 0x00000000 +#define NV927D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV927D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV927D_CORE_NOTIFIER_3__1 0x00000001 +#define NV927D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV927D_CORE_NOTIFIER_3__2 0x00000002 +#define NV927D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV927D_CORE_NOTIFIER_3__3 0x00000003 +#define NV927D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:27 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV927D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV927D_DMA 0x00000000 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_METHOD 0x00000000 +#define NV927D_DMA_OPCODE_JUMP 0x00000001 +#define NV927D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_METHOD 0x00000000 +#define NV927D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV927D_DMA_METHOD_COUNT 27:18 +#define NV927D_DMA_METHOD_OFFSET 11:2 +#define NV927D_DMA_DATA 31:0 +#define NV927D_DMA_DATA_NOP 0x00000000 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_JUMP 0x00000001 +#define NV927D_DMA_JUMP_OFFSET 11:2 +#define NV927D_DMA_OPCODE 31:29 +#define NV927D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV927D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV927D_PUT (0x00000000) +#define NV927D_PUT_PTR 11:2 +#define NV927D_GET (0x00000004) +#define NV927D_GET_PTR 11:2 +#define NV927D_UPDATE (0x00000080) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV927D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV927D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV927D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV927D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV927D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV927D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV927D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV927D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV927D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV927D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV927D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV927D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV927D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV927D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV927D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV927D_GET_CAPABILITIES (0x0000008C) +#define NV927D_GET_CAPABILITIES_DUMMY 31:0 +#define NV927D_SET_SPARE (0x0000016C) +#define NV927D_SET_SPARE_UNUSED 31:0 +#define NV927D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV927D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV927D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV927D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV927D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV927D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV927D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV927D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV927D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV927D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV927D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV927D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV927D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV927D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV927D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV927D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV927D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV927D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV927D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV927D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV927D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV927D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV927D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV927D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV927D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV927D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV927D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV927D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV927D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV927D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV927D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV927D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV927D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV927D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV927D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV927D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV927D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV927D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV927D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV927D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV927D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV927D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV927D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV927D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV927D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV927D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV927D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV927D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV927D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV927D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV927D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV927D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV927D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV927D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV927D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV927D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV927D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV927D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV927D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV927D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV927D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV927D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV927D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV927D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV927D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV927D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV927D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV927D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV927D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV927D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV927D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV927D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV927D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV927D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV927D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV927D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV927D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV927D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV927D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV927D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV927D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV927D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV927D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV927D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV927D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV927D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV927D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV927D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV927D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV927D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV927D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV927D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV927D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV927D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV927D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV927D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl927d_h diff --git a/Display-Class-Methods/cl947d.h b/Display-Class-Methods/cl947d.h new file mode 100644 index 0000000..66ae39b --- /dev/null +++ b/Display-Class-Methods/cl947d.h @@ -0,0 +1,1189 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl947d_h_ +#define _cl947d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV947D_CORE_CHANNEL_DMA (0x0000947D) + +#define NV947D_CORE_NOTIFIER_3 0x00000000 +#define NV947D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV947D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV947D_CORE_NOTIFIER_3__1 0x00000001 +#define NV947D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV947D_CORE_NOTIFIER_3__2 0x00000002 +#define NV947D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV947D_CORE_NOTIFIER_3__3 0x00000003 +#define NV947D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 12:12 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 15:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_LVDS_CLK_MAX 23:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R8 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_REORDER_BANK_WIDTH_SIZE_MAX 13:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV947D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV947D_DMA 0x00000000 +#define NV947D_DMA_OPCODE 31:29 +#define NV947D_DMA_OPCODE_METHOD 0x00000000 +#define NV947D_DMA_OPCODE_JUMP 0x00000001 +#define NV947D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV947D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV947D_DMA_METHOD_COUNT 27:18 +#define NV947D_DMA_METHOD_OFFSET 11:2 +#define NV947D_DMA_DATA 31:0 +#define NV947D_DMA_DATA_NOP 0x00000000 +#define NV947D_DMA_JUMP_OFFSET 11:2 +#define NV947D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV947D_PUT (0x00000000) +#define NV947D_PUT_PTR 11:2 +#define NV947D_GET (0x00000004) +#define NV947D_GET_PTR 11:2 +#define NV947D_UPDATE (0x00000080) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV947D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV947D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV947D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV947D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV947D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV947D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV947D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV947D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV947D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV947D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV947D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV947D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV947D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV947D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV947D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV947D_GET_CAPABILITIES (0x0000008C) +#define NV947D_GET_CAPABILITIES_DUMMY 31:0 +#define NV947D_SET_SPARE (0x0000016C) +#define NV947D_SET_SPARE_UNUSED 31:0 +#define NV947D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV947D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV947D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV947D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV947D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV947D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV947D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV947D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV947D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV947D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV947D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV947D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV947D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV947D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV947D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV947D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV947D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV947D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV947D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV947D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV947D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV947D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV947D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV947D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV947D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV947D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV947D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV947D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV947D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV947D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV947D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV947D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV947D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV947D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV947D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV947D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV947D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV947D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV947D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV947D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV947D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV947D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV947D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV947D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV947D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV947D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV947D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV947D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV947D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV947D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV947D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV947D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV947D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV947D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV947D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV947D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV947D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV947D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV947D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV947D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV947D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV947D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV947D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV947D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV947D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV947D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV947D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV947D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV947D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV947D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV947D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV947D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV947D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV947D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV947D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV947D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV947D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV947D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV947D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV947D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV947D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV947D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV947D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV947D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV947D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV947D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV947D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV947D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV947D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV947D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV947D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV947D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV947D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV947D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV947D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV947D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV947D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV947D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl947d_h diff --git a/Display-Class-Methods/cl957d.h b/Display-Class-Methods/cl957d.h new file mode 100644 index 0000000..cc6452f --- /dev/null +++ b/Display-Class-Methods/cl957d.h @@ -0,0 +1,1185 @@ +/* + * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + + +#ifndef _cl957d_h_ +#define _cl957d_h_ + + +#ifdef __cplusplus +extern "C" { +#endif + +#define NV957D_CORE_CHANNEL_DMA (0x0000957D) + +#define NV957D_CORE_NOTIFIER_3 0x00000000 +#define NV957D_CORE_NOTIFIER_3_SIZEOF 0x00000150 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0 0x00000000 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE 0:0 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_DONE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_R0 15:1 +#define NV957D_CORE_NOTIFIER_3_COMPLETION_0_TIMESTAMP 29:16 +#define NV957D_CORE_NOTIFIER_3__1 0x00000001 +#define NV957D_CORE_NOTIFIER_3__1_R1 31:0 +#define NV957D_CORE_NOTIFIER_3__2 0x00000002 +#define NV957D_CORE_NOTIFIER_3__2_R2 31:0 +#define NV957D_CORE_NOTIFIER_3__3 0x00000003 +#define NV957D_CORE_NOTIFIER_3__3_R3 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4 0x00000004 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_DONE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_VM_USABLE4ISO_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_NVM_USABLE4ISO_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R0 19:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA 20:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_FOS_FETCH_X4AA_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_4_R1 29:21 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_5 0x00000005 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_6 0x00000006 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7 0x00000007 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_DISPCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_7_R4 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8 0x00000008 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_8_R5 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9 0x00000009 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_9_R6 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10 0x0000000A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_10_R7 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11 0x0000000B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_11_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12 0x0000000C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_12_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13 0x0000000D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC0_13_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14 0x0000000E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_14_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15 0x0000000F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC1_15_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16 0x00000010 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_16_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17 0x00000011 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC2_17_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18 0x00000012 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_RGB_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_TV_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_SCART_USABLE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_18_R0 31:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19 0x00000013 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_CRT_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_DAC3_19_R1 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20 0x00000014 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_20_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21 0x00000015 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR0_21_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22 0x00000016 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_22_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23 0x00000017 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR1_23_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24 0x00000018 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_24_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25 0x00000019 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR2_25_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26 0x0000001A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_26_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27 0x0000001B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR3_27_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28 0x0000001C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_28_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29 0x0000001D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR4_29_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30 0x0000001E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_30_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31 0x0000001F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR5_31_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32 0x00000020 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_32_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33 0x00000021 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR6_33_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34 0x00000022 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18 2:2 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS18_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24 3:3 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_LVDS24_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R0 7:4 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A 8:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B 9:9 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_SINGLE_TMDS_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R1 10:10 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS 11:11 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DUAL_TMDS_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R2 13:12 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R3 16:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R4 19:17 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R5 23:20 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A 24:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_A_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B 25:25 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_B_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE 26:26 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_DP_INTERLACE_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_34_R6 31:28 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35 0x00000023 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_DP_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_R7 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_TMDS_CLK_MAX 23:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SOR7_35_LVDS_CLK_MAX 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36 0x00000024 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_36_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37 0x00000025 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR0_37_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38 0x00000026 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_38_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39 0x00000027 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR1_39_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40 0x00000028 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_40_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41 0x00000029 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR2_41_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42 0x0000002A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC 0:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC 1:1 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TV_ENC_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED 6:6 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_FALSE 0x00000000 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_EXT_TMDS10BPC_ALLOWED_TRUE 0x00000001 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_42_R0 31:7 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43 0x0000002B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_EXT_ENC_CLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R1 15:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_PIOR3_43_R2 31:24 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44 0x0000002C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_44_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45 0x0000002D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR0_45_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46 0x0000002E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_46_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47 0x0000002F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR1_47_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48 0x00000030 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_48_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49 0x00000031 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR2_49_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50 0x00000032 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_50_R0 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51 0x00000033 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_SIR3_51_R1 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52 0x00000034 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_52_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53 0x00000035 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_53_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54 0x00000036 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_54_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55 0x00000037 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_55_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56 0x00000038 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_56_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57 0x00000039 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_57_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58 0x0000003A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_58_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59 0x0000003B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD0_59_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60 0x0000003C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_60_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61 0x0000003D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_61_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62 0x0000003E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_62_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63 0x0000003F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_63_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64 0x00000040 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_64_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65 0x00000041 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_65_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66 0x00000042 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_66_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67 0x00000043 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD1_67_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68 0x00000044 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_68_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69 0x00000045 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_69_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70 0x00000046 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_70_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71 0x00000047 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_71_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72 0x00000048 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_72_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73 0x00000049 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_73_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74 0x0000004A +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_74_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75 0x0000004B +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD2_75_R10 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76 0x0000004C +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_76_R0 31:14 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77 0x0000004D +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R1 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_MAX_PIXELS5TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_77_R2 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78 0x0000004E +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R3 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_MAX_PIXELS3TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_78_R4 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79 0x0000004F +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP444 14:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R5 15:15 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_MAX_PIXELS2TAP422 30:16 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_79_R6 31:31 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80 0x00000050 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_PCLK_MAX 7:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_80_R7 31:8 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81 0x00000051 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_81_R8 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82 0x00000052 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_82_R9 31:0 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83 0x00000053 +#define NV957D_CORE_NOTIFIER_3_CAPABILITIES_CAP_HEAD3_83_R10 31:0 + + +// dma opcode instructions +#define NV957D_DMA 0x00000000 +#define NV957D_DMA_OPCODE 31:29 +#define NV957D_DMA_OPCODE_METHOD 0x00000000 +#define NV957D_DMA_OPCODE_JUMP 0x00000001 +#define NV957D_DMA_OPCODE_NONINC_METHOD 0x00000002 +#define NV957D_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 +#define NV957D_DMA_METHOD_COUNT 27:18 +#define NV957D_DMA_METHOD_OFFSET 11:2 +#define NV957D_DMA_DATA 31:0 +#define NV957D_DMA_DATA_NOP 0x00000000 +#define NV957D_DMA_JUMP_OFFSET 11:2 +#define NV957D_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 + +// class methods +#define NV957D_PUT (0x00000000) +#define NV957D_PUT_PTR 11:2 +#define NV957D_GET (0x00000004) +#define NV957D_GET_PTR 11:2 +#define NV957D_UPDATE (0x00000080) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR(i) (0 +(i)*4):(0 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0 0:0 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1 4:4 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2 8:8 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3 12:12 +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_CURSOR3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE(i) (1 +(i)*4):(1 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0 1:1 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1 5:5 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2 9:9 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3 13:13 +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_BASE3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY(i) (2 +(i)*4):(2 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0 2:2 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1 6:6 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2 10:10 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3 14:14 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY3_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM(i) (3 +(i)*4):(3 +(i)*4) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM__SIZE_1 4 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0 3:3 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM0_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1 7:7 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM1_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2 11:11 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM2_ENABLE (0x00000001) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3 15:15 +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_DISABLE (0x00000000) +#define NV957D_UPDATE_INTERLOCK_WITH_OVERLAY_IMM3_ENABLE (0x00000001) +#define NV957D_UPDATE_SPECIAL_HANDLING 25:24 +#define NV957D_UPDATE_SPECIAL_HANDLING_NONE (0x00000000) +#define NV957D_UPDATE_SPECIAL_HANDLING_INTERRUPT_RM (0x00000001) +#define NV957D_UPDATE_SPECIAL_HANDLING_MODE_SWITCH (0x00000002) +#define NV957D_UPDATE_SPECIAL_HANDLING_REASON 23:16 +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY 31:31 +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_FALSE (0x00000000) +#define NV957D_UPDATE_NOT_DRIVER_FRIENDLY_TRUE (0x00000001) +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY 30:30 +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_FALSE (0x00000000) +#define NV957D_UPDATE_NOT_DRIVER_UNFRIENDLY_TRUE (0x00000001) +#define NV957D_UPDATE_INHIBIT_INTERRUPTS 29:29 +#define NV957D_UPDATE_INHIBIT_INTERRUPTS_FALSE (0x00000000) +#define NV957D_UPDATE_INHIBIT_INTERRUPTS_TRUE (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL (0x00000084) +#define NV957D_SET_NOTIFIER_CONTROL_MODE 30:30 +#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_MODE_WRITE_AWAKEN (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL_OFFSET 11:2 +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY 31:31 +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_DISABLE (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_NOTIFY_ENABLE (0x00000001) +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT 28:28 +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_LEGACY (0x00000000) +#define NV957D_SET_NOTIFIER_CONTROL_FORMAT_FOUR_WORD (0x00000001) +#define NV957D_SET_CONTEXT_DMA_NOTIFIER (0x00000088) +#define NV957D_SET_CONTEXT_DMA_NOTIFIER_HANDLE 31:0 +#define NV957D_GET_CAPABILITIES (0x0000008C) +#define NV957D_GET_CAPABILITIES_DUMMY 31:0 +#define NV957D_SET_SPARE (0x0000016C) +#define NV957D_SET_SPARE_UNUSED 31:0 +#define NV957D_SET_SPARE_NOOP(b) (0x00000170 + (b)*0x00000004) +#define NV957D_SET_SPARE_NOOP_UNUSED 31:0 + +#define NV957D_DAC_SET_CONTROL(a) (0x00000180 + (a)*0x00000020) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_DAC_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_DAC_SET_CONTROL_PROTOCOL 12:8 +#define NV957D_DAC_SET_CONTROL_PROTOCOL_RGB_CRT (0x00000000) +#define NV957D_DAC_SET_CONTROL_PROTOCOL_YUV_CRT (0x00000013) +#define NV957D_DAC_SET_SW_SPARE_A(a) (0x00000184 + (a)*0x00000020) +#define NV957D_DAC_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_DAC_SET_SW_SPARE_B(a) (0x00000188 + (a)*0x00000020) +#define NV957D_DAC_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_DAC_SET_CUSTOM_REASON(a) (0x00000190 + (a)*0x00000020) +#define NV957D_DAC_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_SOR_SET_CONTROL(a) (0x00000200 + (a)*0x00000020) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_SOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_SOR_SET_CONTROL_PROTOCOL 11:8 +#define NV957D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM (0x00000000) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A (0x00000001) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B (0x00000002) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS (0x00000005) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_A (0x00000008) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_DP_B (0x00000009) +#define NV957D_SOR_SET_CONTROL_PROTOCOL_CUSTOM (0x0000000F) +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE 21:20 +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_OFF (0x00000000) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X2 (0x00000001) +#define NV957D_SOR_SET_CONTROL_PIXEL_REPLICATE_MODE_X4 (0x00000002) +#define NV957D_SOR_SET_SW_SPARE_A(a) (0x00000204 + (a)*0x00000020) +#define NV957D_SOR_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_SOR_SET_SW_SPARE_B(a) (0x00000208 + (a)*0x00000020) +#define NV957D_SOR_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_SOR_SET_CUSTOM_REASON(a) (0x00000210 + (a)*0x00000020) +#define NV957D_SOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_PIOR_SET_CONTROL(a) (0x00000300 + (a)*0x00000020) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK 3:0 +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_NONE (0x00000000) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD0 (0x00000001) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD1 (0x00000002) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD2 (0x00000004) +#define NV957D_PIOR_SET_CONTROL_OWNER_MASK_HEAD3 (0x00000008) +#define NV957D_PIOR_SET_CONTROL_PROTOCOL 11:8 +#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC (0x00000000) +#define NV957D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC (0x00000001) +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY 14:14 +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_PIOR_SET_SW_SPARE_A(a) (0x00000304 + (a)*0x00000020) +#define NV957D_PIOR_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_PIOR_SET_SW_SPARE_B(a) (0x00000308 + (a)*0x00000020) +#define NV957D_PIOR_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_PIOR_SET_CUSTOM_REASON(a) (0x00000310 + (a)*0x00000020) +#define NV957D_PIOR_SET_CUSTOM_REASON_CODE 31:0 + +#define NV957D_HEAD_SET_PRESENT_CONTROL(a) (0x00000400 + (a)*0x00000300) +#define NV957D_HEAD_SET_PRESENT_CONTROL_MIN_PRESENT_INTERVAL 3:0 +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD 8:8 +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PRESENT_CONTROL_USE_BEGIN_FIELD_ENABLE (0x00000001) +#define NV957D_HEAD_SET_PRESENT_CONTROL_BEGIN_FIELD 6:4 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE(a) (0x00000404 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY 3:3 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_HSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY 4:4 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_POSITIVE_TRUE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_VSYNC_POLARITY_NEGATIVE_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH 9:6 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_DEFAULT (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_16_422 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_18_444 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_20_422 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_422 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_24_444 (0x00000005) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_30_444 (0x00000006) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_32_422 (0x00000007) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_36_444 (0x00000008) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_PIXEL_DEPTH_BPP_48_444 (0x00000009) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE 12:12 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_OVERRIDE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_RESOURCE_COLOR_SPACE_FLAG 20:13 +#define NV957D_HEAD_SET_CONTROL(a) (0x00000408 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_STRUCTURE 0:0 +#define NV957D_HEAD_SET_CONTROL_STRUCTURE_PROGRESSIVE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_STRUCTURE_INTERLACED (0x00000001) +#define NV957D_HEAD_SET_OVERSCAN_COLOR(a) (0x00000410 + (a)*0x00000300) +#define NV957D_HEAD_SET_OVERSCAN_COLOR_RED 9:0 +#define NV957D_HEAD_SET_OVERSCAN_COLOR_GRN 19:10 +#define NV957D_HEAD_SET_OVERSCAN_COLOR_BLU 29:20 +#define NV957D_HEAD_SET_RASTER_SIZE(a) (0x00000414 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_SIZE_WIDTH 14:0 +#define NV957D_HEAD_SET_RASTER_SIZE_HEIGHT 30:16 +#define NV957D_HEAD_SET_RASTER_SYNC_END(a) (0x00000418 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_SYNC_END_X 14:0 +#define NV957D_HEAD_SET_RASTER_SYNC_END_Y 30:16 +#define NV957D_HEAD_SET_RASTER_BLANK_END(a) (0x0000041C + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_BLANK_END_X 14:0 +#define NV957D_HEAD_SET_RASTER_BLANK_END_Y 30:16 +#define NV957D_HEAD_SET_RASTER_BLANK_START(a) (0x00000420 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_BLANK_START_X 14:0 +#define NV957D_HEAD_SET_RASTER_BLANK_START_Y 30:16 +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2(a) (0x00000424 + (a)*0x00000300) +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YSTART 14:0 +#define NV957D_HEAD_SET_RASTER_VERT_BLANK2_YEND 30:16 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR(a) (0x0000042C + (a)*0x00000300) +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_RED 9:0 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_GREEN 19:10 +#define NV957D_HEAD_SET_DEFAULT_BASE_COLOR_BLUE 29:20 +#define NV957D_HEAD_SET_BASE_LUT_LO(a) (0x00000440 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE 31:31 +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE 27:24 +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_LORES (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_HIRES (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV957D_HEAD_SET_BASE_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_BASE_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_BASE_LUT_HI(a) (0x00000444 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_LUT_HI_ORIGIN 31:0 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO(a) (0x00000448 + (a)*0x00000300) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE 31:31 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE 27:24 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_LORES (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_HIRES (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INDEX_1025_UNITY_RANGE (0x00000003) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_UNITY_RANGE (0x00000004) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XRBIAS_RANGE (0x00000005) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_1025_XVYCC_RANGE (0x00000006) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_UNITY_RANGE (0x00000007) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_MODE_INTERPOLATE_257_LEGACY_RANGE (0x00000008) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE 20:20 +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_OUTPUT_LUT_LO_NEVER_YIELD_TO_BASE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_OUTPUT_LUT_HI(a) (0x0000044C + (a)*0x00000300) +#define NV957D_HEAD_SET_OUTPUT_LUT_HI_ORIGIN 31:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY(a) (0x00000450 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_HERTZ 30:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001 31:31 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_ADJ1000DIV1001_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION(a) (0x00000454 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE 21:20 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_25 (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_28 (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_MODE_CLK_CUSTOM (0x00000002) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER 24:24 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_NOT_DRIVER_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING 25:25 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_ENABLE_HOPPING_TRUE (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE 26:26 +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_VBLANK (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_CONFIGURATION_HOPPING_MODE_HBLANK (0x00000001) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX(a) (0x00000458 + (a)*0x00000300) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_HERTZ 30:0 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001 31:31 +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_FALSE (0x00000000) +#define NV957D_HEAD_SET_PIXEL_CLOCK_FREQUENCY_MAX_ADJ1000DIV1001_TRUE (0x00000001) +#define NV957D_HEAD_SET_CONTEXT_DMA_LUT(a) (0x0000045C + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTEXT_DMA_LUT_HANDLE 31:0 +#define NV957D_HEAD_SET_OFFSET(a) (0x00000460 + (a)*0x00000300) +#define NV957D_HEAD_SET_OFFSET_ORIGIN 31:0 +#define NV957D_HEAD_SET_SIZE(a) (0x00000468 + (a)*0x00000300) +#define NV957D_HEAD_SET_SIZE_WIDTH 15:0 +#define NV957D_HEAD_SET_SIZE_HEIGHT 31:16 +#define NV957D_HEAD_SET_STORAGE(a) (0x0000046C + (a)*0x00000300) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT 3:0 +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_ONE_GOB (0x00000000) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_TWO_GOBS (0x00000001) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_FOUR_GOBS (0x00000002) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_EIGHT_GOBS (0x00000003) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_SIXTEEN_GOBS (0x00000004) +#define NV957D_HEAD_SET_STORAGE_BLOCK_HEIGHT_THIRTYTWO_GOBS (0x00000005) +#define NV957D_HEAD_SET_STORAGE_PITCH 20:8 +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT 24:24 +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_BLOCKLINEAR (0x00000000) +#define NV957D_HEAD_SET_STORAGE_MEMORY_LAYOUT_PITCH (0x00000001) +#define NV957D_HEAD_SET_PARAMS(a) (0x00000470 + (a)*0x00000300) +#define NV957D_HEAD_SET_PARAMS_FORMAT 15:8 +#define NV957D_HEAD_SET_PARAMS_FORMAT_I8 (0x0000001E) +#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID16 (0x0000001F) +#define NV957D_HEAD_SET_PARAMS_FORMAT_VOID32 (0x0000002E) +#define NV957D_HEAD_SET_PARAMS_FORMAT_RF16_GF16_BF16_AF16 (0x000000CA) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A8R8G8B8 (0x000000CF) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A2B10G10R10 (0x000000D1) +#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XRBIAS (0x00000022) +#define NV957D_HEAD_SET_PARAMS_FORMAT_X2BL10GL10RL10_XVYCC (0x00000024) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A8B8G8R8 (0x000000D5) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R5G6B5 (0x000000E8) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A1R5G5B5 (0x000000E9) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16 (0x000000C6) +#define NV957D_HEAD_SET_PARAMS_FORMAT_R16_G16_B16_A16_NVBIAS (0x00000023) +#define NV957D_HEAD_SET_PARAMS_FORMAT_A2R10G10B10 (0x000000DF) +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE 1:0 +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV957D_HEAD_SET_PARAMS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV957D_HEAD_SET_PARAMS_GAMMA 2:2 +#define NV957D_HEAD_SET_PARAMS_GAMMA_LINEAR (0x00000000) +#define NV957D_HEAD_SET_PARAMS_GAMMA_SRGB (0x00000001) +#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO(a) (0x00000474 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTEXT_DMAS_ISO_HANDLE 31:0 +#define NV957D_HEAD_SET_CONTROL_CURSOR(a) (0x00000480 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE 31:31 +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT 25:24 +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A1R5G5B5 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_FORMAT_A8R8G8B8 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE 27:26 +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W32_H32 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W64_H64 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W128_H128 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_CURSOR_SIZE_W256_H256 (0x00000003) +#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_X 15:8 +#define NV957D_HEAD_SET_CONTROL_CURSOR_HOT_SPOT_Y 23:16 +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION 29:28 +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_ALPHA_BLEND (0x00000000) +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_PREMULT_ALPHA_BLEND (0x00000001) +#define NV957D_HEAD_SET_CONTROL_CURSOR_COMPOSITION_XOR (0x00000002) +#define NV957D_HEAD_SET_OFFSETS_CURSOR(a,b) (0x00000484 + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_OFFSETS_CURSOR_ORIGIN 31:0 +#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR(a,b) (0x0000048C + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_CONTEXT_DMAS_CURSOR_HANDLE 31:0 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER(a) (0x00000494 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS 2:0 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_1 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_2 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_3_ADAPTIVE (0x00000003) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VERTICAL_TAPS_TAPS_5 (0x00000004) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS 4:3 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_1 (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_2 (0x00000001) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HORIZONTAL_TAPS_TAPS_8 (0x00000002) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_HRESPONSE_BIAS 23:16 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_VRESPONSE_BIAS 31:24 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422 8:8 +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_OUTPUT_SCALER_FORCE422_ENABLE (0x00000001) +#define NV957D_HEAD_SET_PROCAMP(a) (0x00000498 + (a)*0x00000300) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE 1:0 +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_RGB (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_601 (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_COLOR_SPACE_YUV_709 (0x00000002) +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF 2:2 +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_AUTO (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_CHROMA_LPF_ON (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_SAT_COS 19:8 +#define NV957D_HEAD_SET_PROCAMP_SAT_SINE 31:20 +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE 5:5 +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_VESA (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_DYNAMIC_RANGE_CEA (0x00000001) +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION 6:6 +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PROCAMP_RANGE_COMPRESSION_ENABLE (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL(a) (0x000004A0 + (a)*0x00000300) +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE 0:0 +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS 2:1 +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_6_BITS (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_8_BITS (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_BITS_DITHER_TO_10_BITS (0x00000002) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE 6:3 +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_ERR_ACC (0x00000000) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_ERR_ACC (0x00000001) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_DYNAMIC_2X2 (0x00000002) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_STATIC_2X2 (0x00000003) +#define NV957D_HEAD_SET_DITHER_CONTROL_MODE_TEMPORAL (0x00000004) +#define NV957D_HEAD_SET_DITHER_CONTROL_PHASE 8:7 +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN(a) (0x000004B0 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_X 14:0 +#define NV957D_HEAD_SET_VIEWPORT_POINT_IN_Y 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN(a) (0x000004B8 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_IN_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST(a) (0x000004BC + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_X 15:0 +#define NV957D_HEAD_SET_VIEWPORT_POINT_OUT_ADJUST_Y 31:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT(a) (0x000004C0 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN(a) (0x000004C4 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MIN_HEIGHT 30:16 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX(a) (0x000004C8 + (a)*0x00000300) +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_WIDTH 14:0 +#define NV957D_HEAD_SET_VIEWPORT_SIZE_OUT_MAX_HEIGHT 30:16 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS(a) (0x000004D0 + (a)*0x00000300) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE 0:0 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_8 (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE 13:12 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X1_AA (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_SUPER_SAMPLE_X4_AA (0x00000002) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT 17:16 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_BASE_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT 21:20 +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_BASE_CHANNEL_USAGE_BOUNDS_OUTPUT_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS(a) (0x000004D4 + (a)*0x00000300) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE 0:0 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_FALSE (0x00000000) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_USABLE_TRUE (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH 11:8 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_16 (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_32 (0x00000003) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_PIXEL_DEPTH_BPP_64 (0x00000005) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT 13:12 +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_NONE (0x00000000) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_257 (0x00000001) +#define NV957D_HEAD_SET_OVERLAY_USAGE_BOUNDS_OVERLAY_LUT_USAGE_1025 (0x00000002) +#define NV957D_HEAD_SET_PROCESSING(a) (0x000004E0 + (a)*0x00000300) +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS 0:0 +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_DISABLE (0x00000000) +#define NV957D_HEAD_SET_PROCESSING_USE_GAIN_OFS_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONVERSION_RED(a) (0x000004E4 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_RED_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_RED_OFS 31:16 +#define NV957D_HEAD_SET_CONVERSION_GRN(a) (0x000004E8 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_GRN_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_GRN_OFS 31:16 +#define NV957D_HEAD_SET_CONVERSION_BLU(a) (0x000004EC + (a)*0x00000300) +#define NV957D_HEAD_SET_CONVERSION_BLU_GAIN 15:0 +#define NV957D_HEAD_SET_CONVERSION_BLU_OFS 31:16 +#define NV957D_HEAD_SET_HDMI_CTRL(a) (0x00000520 + (a)*0x00000300) +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT 2:0 +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_NORMAL (0x00000000) +#define NV957D_HEAD_SET_HDMI_CTRL_VIDEO_FORMAT_EXTENDED (0x00000001) +#define NV957D_HEAD_SET_HDMI_CTRL_HDMI_VIC 11:4 +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR(a) (0x00000524 + (a)*0x00000300) +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_RED_CR 9:0 +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_GRN_Y 19:10 +#define NV957D_HEAD_SET_VACTIVE_SPACE_COLOR_BLU_CB 29:20 +#define NV957D_HEAD_SET_DISPLAY_ID(a,b) (0x0000052C + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_DISPLAY_ID_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_A(a) (0x0000054C + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_A_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_B(a) (0x00000550 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_B_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_C(a) (0x00000554 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_C_CODE 31:0 +#define NV957D_HEAD_SET_SW_SPARE_D(a) (0x00000558 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_SPARE_D_CODE 31:0 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL(a) (0x0000055C + (a)*0x00000300) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK 0:0 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_NO_CHANGE (0x00000000) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_BLANK_ENABLE (0x00000001) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK 1:1 +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_NO_CHANGE (0x00000000) +#define NV957D_HEAD_SET_GET_BLANKING_CTRL_UNBLANK_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION(a) (0x00000560 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE 0:0 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_DISABLE (0x00000000) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_ENABLE_ENABLE (0x00000001) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_CHUNK_BANDWIDTH 12:1 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LAST_BANDWIDTH 24:13 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA(a) (0x00000564 + (a)*0x00000300) +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY1 7:4 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY2 11:8 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_LOSSY3 15:12 +#define NV957D_HEAD_SET_CONTROL_COMPRESSION_LA_CHUNK_SIZE 23:16 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A(a) (0x000006D0 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_A_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B(a) (0x000006D4 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_B_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C(a) (0x000006D8 + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_C_UNUSED 31:0 +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D(a) (0x000006DC + (a)*0x00000300) +#define NV957D_HEAD_SET_SW_METHOD_PLACEHOLDER_D_UNUSED 31:0 +#define NV957D_HEAD_SET_SPARE(a) (0x000006EC + (a)*0x00000300) +#define NV957D_HEAD_SET_SPARE_UNUSED 31:0 +#define NV957D_HEAD_SET_SPARE_NOOP(a,b) (0x000006F0 + (a)*0x00000300 + (b)*0x00000004) +#define NV957D_HEAD_SET_SPARE_NOOP_UNUSED 31:0 + +#ifdef __cplusplus +}; /* extern "C" */ +#endif +#endif // _cl957d_h diff --git a/Display-Ref-Manuals/gv100/dev_display.ref.txt b/Display-Ref-Manuals/gv100/dev_display.ref.txt new file mode 100644 index 0000000..e287338 --- /dev/null +++ b/Display-Ref-Manuals/gv100/dev_display.ref.txt @@ -0,0 +1,6028 @@ +Copyright (c) 2018 NVIDIA Corporation + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to +deal in the Software without restriction, including without limitation the +rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +sell copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be +included in all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +#define NV_PDISP_FE 0x00615FFF:0x00610000 /* RW--D */ +#define NV_PDISP_HEADS 8 /* */ +#define NV_PDISP_SORS 8 /* */ +#define NV_PDISP_PIORS 4 /* */ +#define NV_PDISP_MAX_HEAD 4 /* */ +#define NV_PDISP_MAX_DAC 0 /* */ +#define NV_PDISP_MAX_SOR 4 /* */ +#define NV_PDISP_MAX_PIOR 3 /* */ +#define NV_PDISP_CHANNELS 84 /* */ +#define NV_PDISP_CHN_NUM_CORE 0 /* */ +#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */ +#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */ +#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */ +#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */ +#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */ +#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */ +#define NV_PDISP_CHN_NUM_PCALC 82 /* */ +#define NV_PDISP_CHN_NUM_SUPERVISOR 83 /* */ +#define NV_PDISP_EXCEPT_CHN_NUM_CORE 0 /* */ +#define NV_PDISP_EXCEPT_CHN_NUM_WIN(i) (1+(i)) /* */ +#define NV_PDISP_EXCEPT_CHN_NUM_WIN__SIZE_1 32 /* */ +#define NV_PDISP_FE_CLASSES 0x00610000 /* R--4R */ +#define NV_PDISP_FE_CLASSES_HW_REV 3:0 /* R--UF */ +#define NV_PDISP_FE_CLASSES_API_REV 7:4 /* R--UF */ +#define NV_PDISP_FE_CLASSES_CLASS_REV 15:8 /* R--UF */ +#define NV_PDISP_FE_CLASSES_CLASS_ID 31:16 /* R--UF */ +#define NV_PDISP_FE_CLASSES_0 3278897936 /* */ +#define NV_PDISP_FE_INST_MEM0 0x00610010 /* RW-4R */ +#define NV_PDISP_FE_INST_MEM0_TARGET 1:0 /* RWIVF */ +#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_NVM 0x00000001 /* RW--V */ +#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_PCI 0x00000002 /* RW--V */ +#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */ +#define NV_PDISP_FE_INST_MEM0_STATUS 3:3 /* RWIVF */ +#define NV_PDISP_FE_INST_MEM0_STATUS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_INST_MEM0_STATUS_INVALID 0x00000000 /* RW--V */ +#define NV_PDISP_FE_INST_MEM0_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_PDISP_FE_INST_MEM1 0x00610014 /* RW-4R */ +#define NV_PDISP_FE_INST_MEM1_ADDR 30:0 /* RWIUF */ +#define NV_PDISP_FE_INST_MEM1_ADDR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_IP_VER 0x00610018 /* R--4R */ +#define NV_PDISP_FE_IP_VER_DEV 7:0 /* R-IVF */ +#define NV_PDISP_FE_IP_VER_DEV_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_IP_VER_ECO 15:8 /* R-IVF */ +#define NV_PDISP_FE_IP_VER_ECO_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_IP_VER_MINOR 23:16 /* R-IVF */ +#define NV_PDISP_FE_IP_VER_MINOR_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_IP_VER_MAJOR 31:24 /* R-IVF */ +#define NV_PDISP_FE_IP_VER_MAJOR_INIT 0x00000003 /* R-I-V */ +#define NV_PDISP_FE_ACQ_DELAY 0x00610040 /* RW-4R */ +#define NV_PDISP_FE_ACQ_DELAY_SEMA 7:0 /* RWIUF */ +#define NV_PDISP_FE_ACQ_DELAY_SEMA_INIT 0x0000000a /* RWI-V */ +#define NV_PDISP_FE_ACQ_DELAY_SEMA_10US 0x0000000a /* RW--V */ +#define NV_PDISP_FE_ACQ_DELAY_SYNCPT 15:8 /* RWIUF */ +#define NV_PDISP_FE_ACQ_DELAY_SYNCPT_INIT 0x0000000a /* RWI-V */ +#define NV_PDISP_FE_ACQ_DELAY_SYNCPT_10US 0x0000000a /* RW--V */ +#define NV_PDISP_FE_HW_SYS_CAP 0x00610060 /* R--4R */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS 0:0 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS 1:1 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS 2:2 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS 3:3 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS 4:4 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS 5:5 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS 6:6 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS 7:7 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS 8:8 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS 9:9 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS 10:10 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS 11:11 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS 12:12 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS 13:13 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS 14:14 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS 15:15 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB 0x00610064 /* R--4R */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS 0:0 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS 1:1 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS 2:2 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS 3:3 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS 4:4 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS 5:5 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS 6:6 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS 7:7 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS 8:8 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS 9:9 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS 10:10 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS 11:11 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS 12:12 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS 13:13 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS 14:14 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS 15:15 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS 16:16 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS 17:17 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS 18:18 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS 19:19 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS 20:20 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS 21:21 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS 22:22 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS 23:23 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS 24:24 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS 25:25 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS 26:26 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS 27:27 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS 28:28 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS 29:29 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS 30:30 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS 31:31 /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_HW_LOCK_PIN_CAP 0x00610068 /* R--4R */ +#define NV_PDISP_FE_HW_LOCK_PIN_CAP_FLIP_LOCK_PINS 3:0 /* R--UF */ +#define NV_PDISP_FE_HW_LOCK_PIN_CAP_SCAN_LOCK_PINS 7:4 /* R--UF */ +#define NV_PDISP_FE_HW_LOCK_PIN_CAP_STEREO_PINS 11:8 /* R--UF */ +#define NV_PDISP_FE_MISC_CONFIGA 0x00610074 /* R--4R */ +#define NV_PDISP_FE_MISC_CONFIGA_NUM_HEADS 3:0 /* R--UF */ +#define NV_PDISP_FE_MISC_CONFIGA_NUM_SORS 11:8 /* R--UF */ +#define NV_PDISP_FE_MISC_CONFIGA_NUM_WINDOWS 25:20 /* R--UF */ +#define NV_PDISP_FE_LOCK_CAPS 0x00610078 /* RWI4R */ +#define NV_PDISP_FE_LOCK_CAPS_LOCK 0:0 /* RWIVF */ +#define NV_PDISP_FE_LOCK_CAPS_LOCK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_LOCK_CAPS_LOCK_UNLOCKED 0x00000000 /* RW--V */ +#define NV_PDISP_FE_LOCK_CAPS_LOCK_LOCKED 0x00000001 /* RW--V */ +#define NV_PDISP_FE_TRAP(i) (0x00610360+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_TRAP__SIZE_1 32 /* */ +#define NV_PDISP_FE_TRAP_METHOD 13:2 /* RWIUF */ +#define NV_PDISP_FE_TRAP_METHOD_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_TRAP_CHN_NUM 22:16 /* RWIUF */ +#define NV_PDISP_FE_TRAP_CHN_NUM_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_TRAP_CHN_TYPE 22:16 /* RWIUF */ +#define NV_PDISP_FE_TRAP_CHN_TYPE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_TRAP_CHN_TYPE_CORE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_TRAP_CHN_TYPE_WIN 0x00000001 /* RW--V */ +#define NV_PDISP_FE_TRAP_CHN_TYPE_WRBK 0x00000002 /* RW--V */ +#define NV_PDISP_FE_TRAP_MODE 30:28 /* RWIVF */ +#define NV_PDISP_FE_TRAP_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_TRAP_MODE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_TRAP_MODE_METHOD_CHANNEL 0x00000001 /* RW--V */ +#define NV_PDISP_FE_TRAP_MODE_METHOD_CHANNEL_TYPE 0x00000002 /* RW--V */ +#define NV_PDISP_FE_TRAP_MODE_ALL_CHANNEL 0x00000003 /* RW--V */ +#define NV_PDISP_FE_TRAP_MODE_ALL_CHANNEL_TYPE 0x00000004 /* RW--V */ +#define NV_PDISP_FE_ERRMASK(i) (0x006103E0+(i)*8) /* RW-4A */ +#define NV_PDISP_FE_ERRMASK__SIZE_1 32 /* */ +#define NV_PDISP_FE_ERRMASK_METHOD 13:2 /* RWIUF */ +#define NV_PDISP_FE_ERRMASK_METHOD_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ERRMASK_CHN_MODE 16:16 /* RWIUF */ +#define NV_PDISP_FE_ERRMASK_CHN_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ERRMASK_CHN_MODE_INSTANCE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_CHN_MODE_TYPE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_CHN_NUM 26:20 /* RWIUF */ +#define NV_PDISP_FE_ERRMASK_CHN_NUM_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ERRMASK_CHN_TYPE 26:20 /* RWIUF */ +#define NV_PDISP_FE_ERRMASK_CHN_TYPE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ERRMASK_CHN_TYPE_CORE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_CHN_TYPE_WIN 0x00000001 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_CHN_TYPE_WRBK 0x00000002 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_MODE 31:29 /* RWIVF */ +#define NV_PDISP_FE_ERRMASK_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ERRMASK_MODE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_MODE_ALL 0x00000001 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_MODE_ALL_ARG 0x00000002 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_MODE_ALL_STATE 0x00000003 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_MODE_METHOD_ARG 0x00000004 /* RW--V */ +#define NV_PDISP_FE_ERRMASK_MODE_STATE_CODE 0x00000005 /* RW--V */ +#define NV_PDISP_FE_ERRMASKCODE(i) (0x006103E4+(i)*8) /* RW-4A */ +#define NV_PDISP_FE_ERRMASKCODE__SIZE_1 32 /* */ +#define NV_PDISP_FE_ERRMASKCODE_CODE 23:0 /* RWIUF */ +#define NV_PDISP_FE_ERRMASKCODE_CODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ERRMASKCODE_CODE_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_ERRMASKCODE_MASK_SIZE 28:24 /* RWIUF */ +#define NV_PDISP_FE_ERRMASKCODE_MASK_SIZE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE 0x006104E0 /* RW-4R */ +#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION 0:0 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_DEALLOCATE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION 1:1 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_DISCONNECT 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_CONNECT 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE 4:4 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_EFI 5:5 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_EFI_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_EFI_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_EFI_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF 9:9 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK 11:11 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED 12:12 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE 14:13 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN 15:15 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN(i) (0x006104E4+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_CHNCTL_WIN__SIZE_1 32 /* */ +#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION 0:0 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_DEALLOCATE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION 1:1 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_DISCONNECT 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_CONNECT 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE 4:4 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT 6:6 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP 7:7 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI 8:8 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF 9:9 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA 10:10 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK 11:11 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE 14:13 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM(i) (0x00610564+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_CHNCTL_WINIM__SIZE_1 32 /* */ +#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION 0:0 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_DEALLOCATE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION 1:1 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_DISCONNECT 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_CONNECT 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE 4:4 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK 11:11 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE 14:13 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS(i) (0x00610604+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_CHNCTL_CURS__SIZE_1 8 /* */ +#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION 0:0 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_DEALLOCATE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO 4:4 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK 11:11 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE 14:13 /* RWIVF */ +#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CHNSTATUS_CORE 0x00610630 /* R--4R */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE 3:0 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_READ_METHOD 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_REQ_METHOD_INFO 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CHK_METHOD_INFO 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CHK_CTXDMA 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CTX_DMA_LOOKUP 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_WAIT_FOR_STG2 0x00000006 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_WAIT_FOR_UPD 0x00000007 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_EXCEPTION 0x00000008 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE 7:4 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_PUBLIC 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_MISC 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_LIMIT 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_BASE 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_SETPARAMSCRSR 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE 20:16 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC_LIMBO 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT1 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT2 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_OPERATION 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT1 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT2 0x00000006 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_OPERATION 0x00000007 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_UNCONNECTED 0x00000008 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT1 0x00000009 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT2 0x0000000A /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_IDLE 0x0000000B /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_BUSY 0x0000000C /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN1 0x0000000D /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN2 0x0000000E /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME 24:24 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO 25:25 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_EMPTY 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_NOTEMPTY 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING 26:26 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING 27:27 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS 29:29 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT 30:30 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC 31:31 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_RUNNING 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN(i) (0x00610664+(i)*4) /* R--4A */ +#define NV_PDISP_FE_CHNSTATUS_WIN__SIZE_1 32 /* */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE 3:0 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_READ_METHOD 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_REQ_METHOD_INFO 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CHK_METHOD_INFO 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CHK_CTXDMA 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CTX_DMA_LOOKUP 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_WAIT_FOR_STG2 0x00000006 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_WAIT_FOR_UPD 0x00000007 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_EXCEPTION 0x00000008 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE 7:4 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_PUBLIC 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_MISC 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_LIMIT 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_BASE 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_WIN_SETCONFIG 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE 11:8 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_IDLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_BLOCK 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_MPI 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_PH_1 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_STATE_ERRCHK 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_RDY_TO_FLIP 0x00000006 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_PH_2 0x00000007 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_CHECK_PEND_LOADV 0x00000008 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_SEND_UPD 0x00000009 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_PRM 0x0000000a /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_EXCEPTION 0x0000000b /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_ABORT 0x0000000c /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE 19:16 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_DEALLOC 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_UNCONNECTED 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT1 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT2 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_IDLE 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_BUSY 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN1 0x00000006 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN2 0x00000007 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME 24:24 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO 25:25 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_EMPTY 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_NOTEMPTY 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING 26:26 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING 27:27 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS 29:29 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT 30:30 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC 31:31 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_RUNNING 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM(i) (0x006106E4+(i)*4) /* R--4A */ +#define NV_PDISP_FE_CHNSTATUS_WINIM__SIZE_1 32 /* */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE 3:0 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_EXCEPT 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_SEND_PUBLIC 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_ILK1 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_FLIP 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_ILK2 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_LOADV 0x00000006 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_SEND_UPDATE 0x00000007 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_PRM 0x00000008 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE 19:16 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_DEALLOC 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_UNCONNECTED 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT1 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT2 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_IDLE 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_BUSY 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN1 0x00000006 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN2 0x00000007 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME 24:24 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO 25:25 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_EMPTY 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_NOTEMPTY 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING 26:26 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING 27:27 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS 29:29 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT 30:30 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC 31:31 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_RUNNING 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS(i) (0x00610784+(i)*4) /* R--4A */ +#define NV_PDISP_FE_CHNSTATUS_CURS__SIZE_1 8 /* */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE 3:0 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_PBERR 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_RSVD 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_SND_PUBLIC 0x00000003 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_WAIT_PUBLIC 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK1_START 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK1_WAIT 0x00000006 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK2_START 0x00000007 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK2_WAIT 0x00000008 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_CHECK_PEND_LOADV 0x00000009 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_SEND_UPD 0x0000000a /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_WAIT_PRM 0x0000000b /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME 24:24 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATE 18:16 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_DEALLOC 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_INIT1 0x00000002 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_IDLE 0x00000004 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_BUSY 0x00000005 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC 31:31 /* R-IVF */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_RUNNING 0x00000001 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN 0x006107A8 /* RW-4R */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH 4:4 /* R--VF */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH_NOT_IN_PROGRESS 0x00000000 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH_IN_PROGRESS 0x00000001 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT 24:24 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT 25:25 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART 31:31 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_DONE 0x00000000 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD(i) (0x006107AC+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_SUPERVISOR_HEAD__SIZE_1 8 /* */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK 8:8 /* R-IVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK 9:9 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK 10:10 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN 12:12 /* R-IVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN 13:13 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN 14:14 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL 16:16 /* R-IVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_NO 0x00000000 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_YES 0x00000001 /* R---V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL 17:17 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL 18:18 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP 20:20 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN 21:21 /* RWIVF */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_PBBASEHI_REGBASE 0x00000b20 /* */ +#define NV_PDISP_FE_PBBASE_REGBASE 0x00000b24 /* */ +#define NV_PDISP_FE_PBSUBDEV_REGBASE 0x00000b28 /* */ +#define NV_PDISP_FE_PBCLIENT_REGBASE 0x00000b2c /* */ +#define NV_PDISP_FE_PBBASEHI(i) (0x00610B20+(i)*16) /* RW-4A */ +#define NV_PDISP_FE_PBBASEHI__SIZE_1 73 /* */ +#define NV_PDISP_FE_PBBASEHI_PUSHBUFFER_ADDR 6:0 /* RWIUF */ +#define NV_PDISP_FE_PBBASEHI_PUSHBUFFER_ADDR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_PBBASE(i) (0x00610B24+(i)*16) /* RW-4A */ +#define NV_PDISP_FE_PBBASE__SIZE_1 73 /* */ +#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET 1:0 /* RWIVF */ +#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_NVM 0x00000001 /* RW--V */ +#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_PCI 0x00000002 /* RW--V */ +#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */ +#define NV_PDISP_FE_PBBASE_PUSHBUFFER_ADDR 31:4 /* RWIUF */ +#define NV_PDISP_FE_PBBASE_PUSHBUFFER_ADDR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_PBSUBDEV(i) (0x00610B28+(i)*16) /* RW-4A */ +#define NV_PDISP_FE_PBSUBDEV__SIZE_1 73 /* */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID 11:0 /* RWIVF */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_0 0x00000001 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_1 0x00000002 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_2 0x00000004 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_3 0x00000008 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_4 0x00000010 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_5 0x00000020 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_6 0x00000040 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_7 0x00000080 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_8 0x00000100 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_9 0x00000200 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_10 0x00000400 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_11 0x00000800 /* RW--V */ +#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_ALL 0x00000FFF /* RW--V */ +#define NV_PDISP_FE_PBCLIENT(i) (0x00610B2C+(i)*16) /* RW-4A */ +#define NV_PDISP_FE_PBCLIENT__SIZE_1 73 /* */ +#define NV_PDISP_FE_PBCLIENT_CLIENT_ID 13:0 /* RWIUF */ +#define NV_PDISP_FE_PBCLIENT_CLIENT_ID_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_PBBASEHI_CORE (0x00610B20+0*16) /* */ +#define NV_PDISP_FE_PBBASE_CORE (0x00610B24+0*16) /* */ +#define NV_PDISP_FE_PBSUBDEV_CORE (0x00610B28+0*16) /* */ +#define NV_PDISP_FE_PBCLIENT_CORE (0x00610B2C+0*16) /* */ +#define NV_PDISP_FE_PBBASEHI_WIN(i) (0x00610B20+(1+(i))*16) /* */ +#define NV_PDISP_FE_PBBASEHI_WIN__SIZE_1 32 /* */ +#define NV_PDISP_FE_PBBASE_WIN(i) (0x00610B24+(1+(i))*16) /* */ +#define NV_PDISP_FE_PBBASE_WIN__SIZE_1 32 /* */ +#define NV_PDISP_FE_PBSUBDEV_WIN(i) (0x00610B28+(1+(i))*16) /* */ +#define NV_PDISP_FE_PBSUBDEV_WIN__SIZE_1 32 /* */ +#define NV_PDISP_FE_PBCLIENT_WIN(i) (0x00610B2C+(1+(i))*16) /* */ +#define NV_PDISP_FE_PBCLIENT_WIN__SIZE_1 32 /* */ +#define NV_PDISP_FE_PBBASEHI_WINIM(i) (0x00610B20+(33+(i))*16) /* */ +#define NV_PDISP_FE_PBBASEHI_WINIM__SIZE_1 32 /* */ +#define NV_PDISP_FE_PBBASE_WINIM(i) (0x00610B24+(33+(i))*16) /* */ +#define NV_PDISP_FE_PBBASE_WINIM__SIZE_1 32 /* */ +#define NV_PDISP_FE_PBSUBDEV_WINIM(i) (0x00610B28+(33+(i))*16) /* */ +#define NV_PDISP_FE_PBSUBDEV_WINIM__SIZE_1 32 /* */ +#define NV_PDISP_FE_PBCLIENT_WINIM(i) (0x00610B2C+(33+(i))*16) /* */ +#define NV_PDISP_FE_PBCLIENT_WINIM__SIZE_1 32 /* */ +#define NV_PDISP_FE_PBBASEHI_WRBK(i) (0x00610B20+(65+(i))*16) /* */ +#define NV_PDISP_FE_PBBASEHI_WRBK__SIZE_1 8 /* */ +#define NV_PDISP_FE_PBBASE_WRBK(i) (0x00610B24+(65+(i))*16) /* */ +#define NV_PDISP_FE_PBBASE_WRBK__SIZE_1 8 /* */ +#define NV_PDISP_FE_PBSUBDEV_WRBK(i) (0x00610B28+(65+(i))*16) /* */ +#define NV_PDISP_FE_PBSUBDEV_WRBK__SIZE_1 8 /* */ +#define NV_PDISP_FE_PBCLIENT_WRBK(i) (0x00610B2C+(65+(i))*16) /* */ +#define NV_PDISP_FE_PBCLIENT_WRBK__SIZE_1 8 /* */ +#define NV_PDISP_FE_EXCEPT(i) (0x00611020+(i)*12) /* RW-4A */ +#define NV_PDISP_FE_EXCEPT__SIZE_1 81 /* */ +#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET 11:0 /* R--VF */ +#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET_PBERR_INVALOP 0x00000000 /* R---V */ +#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET_PBERR_PROTFAULT 0x00000000 /* R---V */ +#define NV_PDISP_FE_EXCEPT_REASON 14:12 /* R--VF */ +#define NV_PDISP_FE_EXCEPT_REASON_NONE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EXCEPT_REASON_PUSHBUFFER_ERR 0x00000001 /* R---V */ +#define NV_PDISP_FE_EXCEPT_REASON_TRAP 0x00000002 /* R---V */ +#define NV_PDISP_FE_EXCEPT_REASON_RESERVED_METHOD 0x00000003 /* R---V */ +#define NV_PDISP_FE_EXCEPT_REASON_INVALID_ARG 0x00000004 /* R---V */ +#define NV_PDISP_FE_EXCEPT_REASON_INVALID_STATE 0x00000005 /* R---V */ +#define NV_PDISP_FE_EXCEPT_REASON_UNRESOLVABLE_HANDLE 0x00000007 /* R---V */ +#define NV_PDISP_FE_EXCEPT_RESTART_MODE 29:28 /* RWIVF */ +#define NV_PDISP_FE_EXCEPT_RESTART_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_EXCEPT_RESTART_MODE_RESUME 0x00000000 /* RW--V */ +#define NV_PDISP_FE_EXCEPT_RESTART_MODE_SKIP 0x00000001 /* RW--V */ +#define NV_PDISP_FE_EXCEPT_RESTART_MODE_REPLAY 0x00000002 /* RW--V */ +#define NV_PDISP_FE_EXCEPT_RESTART 31:31 /* RWIVF */ +#define NV_PDISP_FE_EXCEPT_RESTART_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_EXCEPT_RESTART_DONE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EXCEPT_RESTART_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EXCEPT_RESTART_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EXCEPTARG(i) (0x00611024+(i)*12) /* RW-4A */ +#define NV_PDISP_FE_EXCEPTARG__SIZE_1 41 /* */ +#define NV_PDISP_FE_EXCEPTARG_RDARG 31:0 /* RWIVF */ +#define NV_PDISP_FE_EXCEPTARG_RDARG_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EXCEPTARG_RDARG_PBERR_INVALOP 0x00000000 /* R---V */ +#define NV_PDISP_FE_EXCEPTARG_RDARG_PBERR_PROTFAULT 0x00000400 /* R---V */ +#define NV_PDISP_FE_EXCEPTARG_WRARG 31:0 /* -W-VF */ +#define NV_PDISP_FE_EXCEPTERR(i) (0x00611028+(i)*12) /* R--4A */ +#define NV_PDISP_FE_EXCEPTERR__SIZE_1 41 /* */ +#define NV_PDISP_FE_EXCEPTERR_CODE 23:0 /* R-IVF */ +#define NV_PDISP_FE_EXCEPTERR_CODE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EXCEPTERR_CODE_NONE 0x00000000 /* R---V */ +#define NV_PDISP_FE_TIMEOUT 0x00611400 /* RW-4R */ +#define NV_PDISP_FE_TIMEOUT_PRI_VALUE 7:0 /* RWIVF */ +#define NV_PDISP_FE_TIMEOUT_PRI_VALUE_INIT 0x00000064 /* RWI-V */ +#define NV_PDISP_FE_TIMEOUT_BB_VALUE 15:8 /* RWIVF */ +#define NV_PDISP_FE_TIMEOUT_BB_VALUE_INIT 0x00000064 /* RWI-V */ +#define NV_PDISP_FE_TIMEOUT_STATUS_SRC 0:0 /* R--VF */ +#define NV_PDISP_FE_TIMEOUT_STATUS_SRC_EXTERNAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_TIMEOUT_STATUS_SRC_INTERNAL 0x00000001 /* R---V */ +#define NV_PDISP_FE_TIMEOUT_STATUS_REQTYPE 1:1 /* R--VF */ +#define NV_PDISP_FE_TIMEOUT_STATUS_REQTYPE_READ 0x00000000 /* R---V */ +#define NV_PDISP_FE_TIMEOUT_STATUS_REQTYPE_WRITE 0x00000001 /* R---V */ +#define NV_PDISP_FE_TIMEOUT_STATUS_ADDR 21:2 /* R--VF */ +#define NV_PDISP_FE_TIMEOUT_STATUS_ERR 31:31 /* R-IVF */ +#define NV_PDISP_FE_TIMEOUT_STATUS_ERR_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_TIMEOUT_STATUS_ERR_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0 0x00611408 /* RW-4R */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_FE 0:0 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB 1:1 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA 2:2 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC 3:3 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0 8:8 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1 9:9 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2 10:10 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3 11:11 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4 12:12 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5 13:13 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6 14:14 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7 15:15 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD__SIZE_1 8 /* */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0 16:16 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1 17:17 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2 18:18 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3 19:19 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4 20:20 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5 21:21 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6 22:22 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7 23:23 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR(i) (16+(i)):(16+(i)) /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR__SIZE_1 8 /* */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1 0x0061140C /* RW-4R */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0 0:0 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1 1:1 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2 2:2 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3 3:3 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4 4:4 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5 5:5 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6 6:6 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7 7:7 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8 8:8 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9 9:9 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10 10:10 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11 11:11 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12 12:12 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13 13:13 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14 14:14 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15 15:15 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16 16:16 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17 17:17 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18 18:18 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19 19:19 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20 20:20 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21 21:21 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22 22:22 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23 23:23 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24 24:24 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25 25:25 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26 26:26 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27 27:27 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28 28:28 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29 29:29 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30 30:30 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31 31:31 /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN__SIZE_1 32 /* */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_LOCKED 0x00000001 /* R---V */ +#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_UNLOCK 0x00000001 /* -W--V */ +#define NV_PDISP_FE_CMGR_LOCK_DELAY 0x00611704 /* RW-4R */ +#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL 15:0 /* RWIUF */ +#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL_INIT 0x00000064 /* RWI-V */ +#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL_100US 0x00000064 /* RW--V */ +#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL 31:16 /* RWIUF */ +#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL_INIT 0x000000C8 /* RWI-V */ +#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL_200US 0x000000C8 /* RW--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING(i) (0x00611800+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC 0x00611840 /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0 8:8 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1 9:9 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2 10:10 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3 11:11 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4 12:12 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5 13:13 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6 14:14 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7 15:15 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0 16:16 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1 17:17 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2 18:18 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3 19:19 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4 20:20 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5 21:21 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6 22:22 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7 23:23 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW(i) (16+(i)):(16+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0 24:24 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1 25:25 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2 26:26 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3 27:27 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4 28:28 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5 29:29 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6 30:30 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7 31:31 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT(i) (24+(i)):(24+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP 0x00611848 /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT 16:16 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT 17:17 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN 0x0061184C /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8 8:8 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9 9:9 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10 10:10 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11 11:11 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12 12:12 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13 13:13 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14 14:14 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15 15:15 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16 16:16 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17 17:17 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18 18:18 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19 19:19 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20 20:20 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21 21:21 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22 22:22 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23 23:23 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24 24:24 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25 25:25 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26 26:26 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27 27:27 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28 28:28 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29 29:29 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30 30:30 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31 31:31 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH__SIZE_1 32 /* */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM 0x00611850 /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8 8:8 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9 9:9 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10 10:10 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11 11:11 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12 12:12 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13 13:13 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14 14:14 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15 15:15 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16 16:16 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17 17:17 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18 18:18 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19 19:19 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20 20:20 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21 21:21 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22 22:22 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23 23:23 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24 24:24 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25 25:25 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26 26:26 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27 27:27 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28 28:28 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29 29:29 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30 30:30 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31 31:31 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH__SIZE_1 32 /* */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER 0x00611854 /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0 16:16 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1 17:17 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2 18:18 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3 19:19 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4 20:20 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5 21:21 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6 22:22 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7 23:23 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN 0x00611858 /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8 8:8 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9 9:9 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10 10:10 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11 11:11 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12 12:12 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13 13:13 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14 14:14 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15 15:15 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16 16:16 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17 17:17 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18 18:18 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19 19:19 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20 20:20 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21 21:21 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22 22:22 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23 23:23 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24 24:24 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25 25:25 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26 26:26 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27 27:27 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28 28:28 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29 29:29 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30 30:30 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31 31:31 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH__SIZE_1 32 /* */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER 0x0061185C /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP 0x00611860 /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR 0x00611864 /* RW-4R */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_STAT_OR_SOR_RESET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP 0x00611948 /* RW-4R */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT 16:16 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT 17:17 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_CLEAR 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP 0x006119C8 /* RW-4R */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT 16:16 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT 17:17 /* RWIVF */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_SET 0x00000001 /* -W--V */ +#define NV_PDISP_FE_EVT_DISPATCH 0x00611A00 /* R--4R */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0 0:0 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1 1:1 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2 2:2 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3 3:3 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4 4:4 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5 5:5 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6 6:6 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7 7:7 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_0 8:8 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_1 9:9 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_2 10:10 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_3 11:11 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_4 12:12 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_5 13:13 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_6 14:14 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_7 15:15 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS(i) (8+(i)):(8+(i)) /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS__SIZE_1 8 /* */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DSC 16:16 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DSC_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DSC_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_FP16 17:17 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_FP16_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_FP16_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP 18:18 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN 19:19 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM 20:20 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER 21:21 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN 22:22 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER 23:23 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP 24:24 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_OR 25:25 /* R--VF */ +#define NV_PDISP_FE_EVT_DISPATCH_OR_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_EVT_DISPATCH_OR_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1 0:0 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2 1:1 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3 2:2 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE 3:3 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A 4:4 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B 5:5 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN 6:6 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR 7:7 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR 0x00611C34 /* R--4R */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0 0:0 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1 1:1 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2 2:2 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3 3:3 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4 4:4 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5 5:5 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6 6:6 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7 7:7 /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR(i) (0+(i)):(0+(i)) /* R-IVF */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR__SIZE_1 8 /* */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING(i) (0x00611CC0+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING__SIZE_1 8 /* */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SD3_BUCKET_WALK_DONE 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SD3_BUCKET_WALK_DONE_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SD3_BUCKET_WALK_DONE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SD3_BUCKET_WALK_DONE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN 0x00611CE4 /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8 8:8 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9 9:9 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10 10:10 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11 11:11 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12 12:12 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13 13:13 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14 14:14 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15 15:15 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16 16:16 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17 17:17 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18 18:18 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19 19:19 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20 20:20 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21 21:21 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22 22:22 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23 23:23 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24 24:24 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25 25:25 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26 26:26 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27 27:27 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28 28:28 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29 29:29 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30 30:30 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31 31:31 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH__SIZE_1 32 /* */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM 0x00611CE8 /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8 8:8 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9 9:9 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10 10:10 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11 11:11 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12 12:12 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13 13:13 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14 14:14 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15 15:15 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16 16:16 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17 17:17 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18 18:18 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19 19:19 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20 20:20 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21 21:21 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22 22:22 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23 23:23 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24 24:24 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25 25:25 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26 26:26 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27 27:27 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28 28:28 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29 29:29 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30 30:30 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31 31:31 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH__SIZE_1 32 /* */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER 0x00611CEC /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0 16:16 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1 17:17 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2 18:18 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3 19:19 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4 20:20 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5 21:21 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6 22:22 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7 23:23 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS__SIZE_1 8 /* */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP 0x00611CF0 /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN 8:8 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR 0x00611CF4 /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR__SIZE_1 8 /* */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(i) (0x00611D80+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING__SIZE_1 8 /* */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SD3_BUCKET_WALK_DONE 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SD3_BUCKET_WALK_DONE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SD3_BUCKET_WALK_DONE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SD3_BUCKET_WALK_DONE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN 0x00611DA4 /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8 8:8 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9 9:9 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10 10:10 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11 11:11 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12 12:12 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13 13:13 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14 14:14 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15 15:15 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16 16:16 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17 17:17 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18 18:18 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19 19:19 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20 20:20 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21 21:21 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22 22:22 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23 23:23 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24 24:24 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25 25:25 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26 26:26 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27 27:27 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28 28:28 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29 29:29 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30 30:30 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31 31:31 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH__SIZE_1 32 /* */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM 0x00611DA8 /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8 8:8 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9 9:9 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10 10:10 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11 11:11 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12 12:12 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13 13:13 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14 14:14 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15 15:15 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16 16:16 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17 17:17 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18 18:18 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19 19:19 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20 20:20 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21 21:21 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22 22:22 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23 23:23 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24 24:24 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25 25:25 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26 26:26 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27 27:27 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28 28:28 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29 29:29 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30 30:30 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31 31:31 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH__SIZE_1 32 /* */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER 0x00611DAC /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0 16:16 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1 17:17 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2 18:18 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3 19:19 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4 20:20 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5 21:21 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6 22:22 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7 23:23 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS__SIZE_1 8 /* */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP 0x00611DB0 /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN 8:8 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR 0x00611DB4 /* RW-4R */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0 0:0 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1 1:1 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2 2:2 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3 3:3 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4 4:4 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5 5:5 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6 6:6 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7 7:7 /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR__SIZE_1 8 /* */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH 0x00611EC0 /* R--4R */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0 0:0 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1 1:1 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2 2:2 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3 3:3 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4 4:4 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5 5:5 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6 6:6 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7 7:7 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING__SIZE_1 8 /* */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_NVDPS 8:8 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_NVDPS_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_NVDPS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN 9:9 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM 10:10 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER 11:11 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP 12:12 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_OR 13:13 /* R--VF */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_OR_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PDISP_FE_RM_INTR_DISPATCH_OR_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_RG(i) (0x00612200+(i)*2048) /* RW-4A */ +#define NV_PDISP_FE_CMGR_CLK_RG__SIZE_1 8 /* */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV 3:0 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_1 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_2 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_3 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_4 0x00000003 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_5 0x00000004 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_6 0x00000005 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_7 0x00000006 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_8 0x00000007 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_9 0x00000008 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_10 0x00000009 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_11 0x0000000a /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_12 0x0000000b /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_13 0x0000000c /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_14 0x0000000d /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_15 0x0000000e /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_16 0x0000000f /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_MODE 7:6 /* R--VF */ +#define NV_PDISP_FE_CMGR_CLK_RG_MODE_NORMAL 0x00000001 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_RG_MODE_SAFE 0x00000002 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE 11:11 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_RG_STATE 23:23 /* R--VF */ +#define NV_PDISP_FE_CMGR_CLK_RG_STATE_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_RG_STATE_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR(i) (0x00612300+(i)*2048) /* RW-4A */ +#define NV_PDISP_FE_CMGR_CLK_SOR__SIZE_1 8 /* */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV 3:0 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_1 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_2 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_3 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_4 0x00000003 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_5 0x00000004 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_6 0x00000005 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_7 0x00000006 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_8 0x00000007 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_9 0x00000008 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_10 0x00000009 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_11 0x0000000a /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_12 0x0000000b /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_13 0x0000000c /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_14 0x0000000d /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_15 0x0000000e /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_16 0x0000000f /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE 7:6 /* R--VF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_NORMAL 0x00000001 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_SAFE 0x00000002 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV 11:8 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_1 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_2 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_3 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_4 0x00000003 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_5 0x00000004 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_6 0x00000005 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_7 0x00000006 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_8 0x00000007 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_9 0x00000008 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_10 0x00000009 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_11 0x0000000a /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_12 0x0000000b /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_13 0x0000000c /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_14 0x0000000d /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_15 0x0000000e /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_16 0x0000000f /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD 15:12 /* R--VF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_NONE 0x0000000F /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_0 0x00000000 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_1 0x00000001 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_2 0x00000002 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_3 0x00000003 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_4 0x00000004 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_5 0x00000005 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_6 0x00000006 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_7 0x00000007 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS 17:16 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_DP_NORMAL 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_DP_SAFE 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_FEEDBACK 0x00000003 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED 22:18 /* RWIUF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_INIT 0x00000006 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_1_62GHZ 0x00000006 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_2_70GHZ 0x0000000A /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_5_40GHZ 0x00000014 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_8_10GHZ 0x0000001E /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_2_16GHZ 0x00000008 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_2_43GHZ 0x00000009 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_3_24GHZ 0x0000000C /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_4_32GHZ 0x00000010 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_TMDS 0x0000000A /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_TMDS_HIGH_SPEED 0x00000014 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_LVDS 0x00000007 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_STATE 23:23 /* R--VF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_STATE_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_STATE_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE 25:24 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_SINGLE_PCLK 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_DIFF_PCLK 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_SINGLE_DPCLK 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_DIFF_DPCLK 0x00000003 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR 2:2 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE 5:3 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPA 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPB 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPC 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPD 0x00000003 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPE 0x00000004 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPF 0x00000005 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPG 0x00000006 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL(i) (0x00612308+(i)*128) /* RW-4A */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL__SIZE_1 6 /* */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND 3:0 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR0 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR1 0x00000002 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR2 0x00000003 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR3 0x00000004 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR4 0x00000005 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR5 0x00000006 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR6 0x00000007 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR7 0x00000008 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR 4:4 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_PRIMARY 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_SECONDARY 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL 5:5 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_PRIMARY 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_SECONDARY 0x00000001 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT 7:7 /* R--VF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT_LOW 0x00000000 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT_HIGH 0x00000001 /* R---V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ 11:8 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ_INIT 0x00000008 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ_500OHM 0x00000000 /* RW--V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_MODE 16:16 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_DIV 17:17 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_DIV_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_SEL 20:18 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_SEL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_PRBS_SEL 22:21 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_PRBS_SEL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CLK_EN_DIFF_DET 23:23 /* RWIVF */ +#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CLK_EN_DIFF_DET_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION(i) (0x00612050+(i)*2048) /* RW-4A */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION__SIZE_1 8 /* */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_VALUE 15:0 /* RWIVF */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_WRITE_MODE 28:28 /* RWIVF */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_WRITE_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_UPDATE 29:29 /* RWIVF */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_UPDATE_IMMEDIATE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_UPDATE_CORE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_STATUS 31:30 /* R-IVF */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_STATUS_ACTIVE 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_STATUS_ARMED 0x00000001 /* R---V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_STATUS_ASSEMBLY 0x00000002 /* R---V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY(i) (0x00612054+(i)*2048) /* RW-4A */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY__SIZE_1 8 /* */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_VALUE 15:0 /* RWIVF */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE 28:28 /* RWIVF */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE 29:29 /* RWIVF */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_IMMEDIATE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_CORE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS 31:30 /* R--VF */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ARMED 0x00000001 /* R---V */ +#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ASSEMBLY 0x00000002 /* R---V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK(i) (0x00612058+(i)*2048) /* RW-4A */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK__SIZE_1 8 /* */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_VALUE 15:0 /* RWIVF */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_MASK 30:30 /* RWIVF */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_MASK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_MASK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_MASK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_ELV_BLOCK(i) (0x00612068+(i)*2048) /* RW-4A */ +#define NV_PDISP_FE_ELV_BLOCK__SIZE_1 8 /* */ +#define NV_PDISP_FE_ELV_BLOCK_CTRL 0:0 /* RWIVF */ +#define NV_PDISP_FE_ELV_BLOCK_CTRL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_ELV_BLOCK_CTRL_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_ELV_BLOCK_CTRL_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV 1:1 /* RWIVF */ +#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_DONE 0x00000000 /* R---V */ +#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV 2:2 /* RWIVF */ +#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_DONE 0x00000000 /* R---V */ +#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_FE_FLIPLOCK 0x0061206C /* RW-4R */ +#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME 23:0 /* RWIVF */ +#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME_INIT 0x00000080 /* RWI-V */ +#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME_32NS 0x00000020 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP 0x00640000 /* RW-4R */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB 0x00640004 /* RW-4R */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_LOCK_PIN_CAP 0x00640008 /* RW-4R */ +#define NV_PDISP_FE_SW_LOCK_PIN_CAP_FLIP_LOCK_PINS 3:0 /* RWIVF */ +#define NV_PDISP_FE_SW_LOCK_PIN_CAP_FLIP_LOCK_PINS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_LOCK_PIN_CAP_SCAN_LOCK_PINS 7:4 /* RWIVF */ +#define NV_PDISP_FE_SW_LOCK_PIN_CAP_SCAN_LOCK_PINS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_LOCK_PIN_CAP_STEREO_PINS 11:8 /* RWIVF */ +#define NV_PDISP_FE_SW_LOCK_PIN_CAP_STEREO_PINS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA 0x00640010 /* RW-4R */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR 24:24 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE 25:25 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPB 0x00640014 /* RW-4R */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC 0x00640018 /* RW-4R */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE 10:8 /* RWIVF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_ONE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_TWO 0x00000002 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_THREE 0x00000003 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_FOUR 0x00000004 /* RW--V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD 0x0064001C /* RW-4R */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD_REORDER_BUFFER_DEPTH 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD_REORDER_BUFFER_DEPTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD_RDOUT_BUFFER_SIZE 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD_RDOUT_BUFFER_SIZE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPA(i) (0x00640030+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_HEAD_CAPA__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER 0:0 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_HAS_YUV422 1:1 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_HAS_YUV422_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_HAS_YUV422_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_HAS_YUV422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_HSAT 2:2 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPA_HSAT_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_HSAT_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_HSAT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_OCSC 3:3 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPA_OCSC_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_OCSC_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_OCSC_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_YUV422 4:4 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPA_YUV422_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_YUV422_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_YUV422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE 6:5 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE_257 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE_1025 0x00000002 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_LOCATION 7:7 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_LOCATION_EARLY 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_LOCATION_LATE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_LOCATION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPB(i) (0x00640034+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_HEAD_CAPB__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_HEAD_CAPB_MAX_PIXELS_5TAP422 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_CAPB_MAX_PIXELS_5TAP422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPB_MAX_PIXELS_5TAP444 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_CAPB_MAX_PIXELS_5TAP444_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPC(i) (0x00640038+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_HEAD_CAPC__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_HEAD_CAPC_MAX_PIXELS_3TAP422 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_CAPC_MAX_PIXELS_3TAP422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPC_MAX_PIXELS_3TAP444 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_CAPC_MAX_PIXELS_3TAP444_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPD(i) (0x0064003C+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_HEAD_CAPD__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_HEAD_CAPD_MAX_PIXELS_2TAP422 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_CAPD_MAX_PIXELS_2TAP422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPD_MAX_PIXELS_2TAP444 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_CAPD_MAX_PIXELS_2TAP444_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPE(i) (0x00640040+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_HEAD_CAPE__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_HEAD_CAPE_MAX_PIXELS_1TAP422 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_CAPE_MAX_PIXELS_1TAP422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPE_MAX_PIXELS_1TAP444 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_CAPE_MAX_PIXELS_1TAP444_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPF(i) (0x00640044+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_HEAD_CAPF__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_HEAD_CAPF_FULL_WIDTH 3:0 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPF_FULL_WIDTH_INIT 0x000000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPF_UNIT_WIDTH 7:4 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPF_UNIT_WIDTH_INIT 0x000000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPF_SCLR_WIDTH 11:8 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPF_SCLR_WIDTH_INIT 0x000000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPF_HSAT_WIDTH 15:12 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPF_HSAT_WIDTH_INIT 0x000000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPF_LUT_WIDTH 19:16 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPF_LUT_WIDTH_INIT 0x000000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPF_OCSC_WIDTH 23:20 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPF_OCSC_WIDTH_INIT 0x000000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPF_OLPF_WIDTH 27:24 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPF_OLPF_WIDTH_INIT 0x000000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_CAPF_TZ_WIDTH 31:28 /* RWIVF */ +#define NV_PDISP_FE_SW_HEAD_CAPF_TZ_WIDTH_INIT 0x000000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_RG_CAPA(i) (0x00640048+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_HEAD_RG_CAPA__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_HEAD_RG_CAPA_SUPPORT_DSC 16:16 /* RWIUF */ +#define NV_PDISP_FE_SW_HEAD_RG_CAPA_SUPPORT_DSC_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_HEAD_RG_CAPA_SUPPORT_DSC_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_HEAD_RG_CAPA_SUPPORT_DSC_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP(i) (0x00640144+(i)*8) /* RW-4A */ +#define NV_PDISP_FE_SW_SOR_CAP__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SDI 16:16 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_A 24:24 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_B 25:25 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA(i) (0x006401E4+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA__SIZE_1 32 /* */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_FULL_WIDTH 3:0 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_UNIT_WIDTH 7:4 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_SCLR_WIDTH 11:8 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_SCLR_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_YUV_WIDTH 15:12 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_YUV_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_LUT_WIDTH 19:16 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_LUT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_CGMT_WIDTH 23:20 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_CGMT_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB(i) (0x006401E8+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB__SIZE_1 32 /* */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE 9:8 /* RWIVF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_NORMAL 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_WIDE 0x00000002 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE 13:12 /* RWIVF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_257 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_1025 0x00000002 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT 14:14 /* RWIVF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT 15:15 /* RWIVF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_DEGAMMA_SUPPORT 16:16 /* RWIVF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_DEGAMMA_SUPPORT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_DEGAMMA_SUPPORT_NO 0x00000000 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_DEGAMMA_SUPPORT_YES 0x00000001 /* RW--V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC(i) (0x006401EC+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC__SIZE_1 32 /* */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP422 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP444 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP444_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD(i) (0x006401F0+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD__SIZE_1 32 /* */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP422 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP444 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP444_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE(i) (0x006401F4+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE__SIZE_1 32 /* */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP422 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP444 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP444_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF(i) (0x006401F8+(i)*32) /* RW-4A */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF__SIZE_1 32 /* */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP422 15:0 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP422_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP444 31:16 /* RWIUF */ +#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP444_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CLK_CAP(i) (0x00640608+(i)*4) /* RW-4A */ +#define NV_PDISP_FE_SW_SOR_CLK_CAP__SIZE_1 8 /* */ +#define NV_PDISP_FE_SW_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */ +#define NV_PDISP_FE_SW_SOR_CLK_CAP_DP_MAX_INIT 0x00000036 /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */ +#define NV_PDISP_FE_SW_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */ +#define NV_PDISP_FE_SW_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */ +#define NV_PDISP_FE_SW_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */ +#define NV_UDISP_HASH 0x00001FFF:0x00000000 /* RW--M */ +#define NV_UDISP_HASH_BASE 0x00000000 /* */ +#define NV_UDISP_HASH_LIMIT 0x00001FFF /* */ +#define NV_UDISP_OBJ_MEM 0x0000FFFF:0x00002000 /* RW--M */ +#define NV_UDISP_OBJ_MEM_BASE 0x00002000 /* */ +#define NV_UDISP_OBJ_MEM_LIMIT 0x0000FFFF /* */ +#define NV_UDISP_HASH_TBL /* ----G */ +#define NV_UDISP_HASH_TBL_HANDLE (0*32+31):(0*32+0) /* RWXVF */ +#define NV_UDISP_HASH_TBL_CLIENT_ID (1*32+13):(1*32+0) /* RWXVF */ +#define NV_UDISP_HASH_TBL_INSTANCE (1*32+24):(1*32+14) /* RWXUF */ +#define NV_UDISP_HASH_TBL_INSTANCE_INVALID 0x00000000 /* RW--V */ +#define NV_UDISP_HASH_TBL_CHN (1*32+31):(1*32+25) /* RWXUF */ +#define NV_DMA /* ----G */ +#define NV_DMA_TARGET_NODE (0*32+1):(0*32+0) /* RWXVF */ +#define NV_DMA_TARGET_NODE_PHYSICAL_NVM 0x00000001 /* RW--V */ +#define NV_DMA_TARGET_NODE_PHYSICAL_PCI 0x00000002 /* RW--V */ +#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT 0x00000003 /* RW--V */ +#define NV_DMA_ACCESS (0*32+2):(0*32+2) /* RWXVF */ +#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */ +#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */ +#define NV_DMA_PAGE_SIZE (0*32+6):(0*32+6) /* RWXUF */ +#define NV_DMA_PAGE_SIZE_BIG 0x00000000 /* RW--V */ +#define NV_DMA_PAGE_SIZE_SMALL 0x00000001 /* RW--V */ +#define NV_DMA_KIND (0*32+20):(0*32+20) /* RWXVF */ +#define NV_DMA_KIND_PITCH 0x00000000 /* RW--V */ +#define NV_DMA_KIND_BLOCKLINEAR 0x00000001 /* RW--V */ +#define NV_DMA_ADDRESS_BASE_LO (1*32+31):(1*32+0) /* RWXUF */ +#define NV_DMA_ADDRESS_BASE_HI (2*32+6):(2*32+0) /* RWXUF */ +#define NV_DMA_ADDRESS_LIMIT_LO (3*32+31):(3*32+0) /* RWXUF */ +#define NV_DMA_ADDRESS_LIMIT_HI (4*32+6):(4*32+0) /* RWXUF */ +#define NV_DMA__SIZE 20 /* */ +#define NV_DMA__ALIGN 32 /* */ +#define NV_DMA__ADDRESS_BASE_SHIFT 8 /* */ +#define NV_PDISP_IHUB_COMMON_CAPA 0x0062E000 /* R--4R */ +#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* R--UF */ +#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* R--VF */ +#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* R--VF */ +#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* R--VF */ +#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPB 0x0062E004 /* R--4R */ +#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS 17:12 /* R--UF */ +#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS 23:18 /* R--UF */ +#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_422_ROTATION_THREAD_GROUPS 29:24 /* R--UF */ +#define NV_PDISP_IHUB_COMMON_CAPC 0x0062E008 /* R--4R */ +#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* R--VF */ +#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* R--VF */ +#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CAPD 0x0062E00C /* R--4R */ +#define NV_PDISP_IHUB_COMMON_CAPD_REORDER_BUFFER_DEPTH 15:0 /* R--UF */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL 0x0062E018 /* RW-4R */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_WINDOW_INSTANCE 4:0 /* RWIUF */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_WINDOW_INSTANCE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_HEAD_INSTANCE 7:5 /* RWIUF */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_HEAD_INSTANCE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_SELECT 8:8 /* RWIVF */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_SELECT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_SELECT_WINDOW 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_SELECT_HEAD 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE 10:9 /* RWIVF */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_IMMEDIATE 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_STRICT 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_SEMI_STRICT 0x00000002 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_NO_UPDATE_WAIT 11:11 /* RWIVF */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_NO_UPDATE_WAIT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_NO_UPDATE_WAIT_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_NO_UPDATE_WAIT_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE 31:31 /* RWIVF */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_DONE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_TRIGGER 0x00000001 /* -W--T */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL 0x0062E024 /* RW-4R */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH 1:1 /* RWIVF */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT 30:30 /* RWIVF */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER 31:31 /* RWIVF */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG 0x0062E02C /* RW-4R */ +#define NV_PDISP_IHUB_COMMON_CONFIG_REQUEST_BATCH_SIZE 2:0 /* RWIVF */ +#define NV_PDISP_IHUB_COMMON_CONFIG_REQUEST_BATCH_SIZE_1 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_COMMON_CONFIG_REQUEST_BATCH_SIZE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG(i) (0x00628000+(i)*512) /* RW-4A */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG__SIZE_1 32 /* */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_ENTRIES 15:0 /* RWIUF */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_ENTRIES_INIT 0x00000278 /* RWI-V */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE 16:16 /* RWIVF */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_GLOBAL 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_IDLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS 31:31 /* R--VF */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS_DONE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER(i) (0x00628004+(i)*512) /* RW-4A */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER__SIZE_1 32 /* */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS 7:0 /* RWIUF */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_ONE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_MAX 0x0000000F /* RW--V */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE 16:16 /* RWIVF */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_GLOBAL 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_IDLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS 31:31 /* R--VF */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS_DONE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT(i) (0x0062800C+(i)*512) /* RW-4A */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT__SIZE_1 32 /* */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT 11:0 /* RWIUF */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT_INIT 0x00000FFF /* RWI-V */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT_MAX 0x00000FFF /* */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE 16:16 /* RWIVF */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_GLOBAL 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_IDLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS 31:31 /* R--VF */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS_DONE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_WINDOW_OCC(i) (0x00628028+(i)*512) /* R--4A */ +#define NV_PDISP_IHUB_WINDOW_OCC__SIZE_1 32 /* */ +#define NV_PDISP_IHUB_WINDOW_OCC_BYTES 28:0 /* R--UF */ +#define NV_PDISP_IHUB_WINDOW_OCC_PIXELS 28:0 /* ----- */ +#define NV_PDISP_IHUB_WINDOW_REQ(i) (0x00628078+(i)*512) /* R--4A */ +#define NV_PDISP_IHUB_WINDOW_REQ__SIZE_1 32 /* */ +#define NV_PDISP_IHUB_WINDOW_REQ_LINE 15:0 /* R--UF */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG(i) (0x0062C000+(i)*512) /* RW-4A */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG__SIZE_1 8 /* */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_ENTRIES 15:0 /* RWIUF */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_ENTRIES_INIT 0x00000010 /* RWI-V */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE 16:16 /* RWIVF */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_GLOBAL 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_IDLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS 31:31 /* R--VF */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS_DONE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_CURS_FETCH_METER(i) (0x0062C004+(i)*512) /* RW-4A */ +#define NV_PDISP_IHUB_CURS_FETCH_METER__SIZE_1 8 /* */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS 7:0 /* RWIUF */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_ONE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_MAX 0x0000000F /* RW--V */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE 16:16 /* RWIVF */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_GLOBAL 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_IDLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS 31:31 /* R--VF */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS_DONE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT(i) (0x0062C008+(i)*512) /* RW-4A */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT__SIZE_1 8 /* */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT 11:0 /* RWIUF */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT_INIT 0x00000FFF /* RWI-V */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT_MAX 0x00000FFF /* */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE 16:16 /* RWIVF */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_GLOBAL 0x00000000 /* RW--V */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_IDLE 0x00000001 /* RW--V */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS 31:31 /* R--VF */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS_DONE 0x00000000 /* R---V */ +#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_IHUB_CURS_OCC(i) (0x0062C028+(i)*512) /* R--4A */ +#define NV_PDISP_IHUB_CURS_OCC__SIZE_1 8 /* */ +#define NV_PDISP_IHUB_CURS_OCC_BYTES 28:0 /* R--UF */ +#define NV_PDISP_IHUB_CURS_OCC_PIXELS 28:0 /* ----- */ +#define NV_PDISP_IHUB_CURS_REQ(i) (0x0062C078+(i)*512) /* R--4A */ +#define NV_PDISP_IHUB_CURS_REQ__SIZE_1 8 /* */ +#define NV_PDISP_IHUB_CURS_REQ_LINE 15:0 /* R--UF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER(i) (0x00630020+(i)*2048) /* RW-4A */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER__SIZE_1 32 /* */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_VAL 15:0 /* RWIUF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO 15:14 /* RWIUF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_1 0x00000000 /* RW--V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_2 0x00000001 /* RW--V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_4 0x00000002 /* RW--V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_8 0x00000003 /* RW--V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_PXVAL 13:0 /* RWIUF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_PXVAL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE 28:28 /* RWIVF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE 29:29 /* RWIVF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_IMMEDIATE 0x00000000 /* RW--V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_CORE 0x00000001 /* RW--V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS 31:30 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ARMED 0x00000001 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ASSEMBLY 0x00000002 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA(i) (0x00630050+(i)*2048) /* R--4A */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA__SIZE_1 32 /* */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_FULL_WIDTH 3:0 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_UNIT_WIDTH 7:4 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_SCLR_WIDTH 11:8 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_YUV_WIDTH 15:12 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_LUT_WIDTH 19:16 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_CGMT_WIDTH 23:20 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB(i) (0x00630054+(i)*2048) /* R--4A */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB__SIZE_1 32 /* */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE 9:8 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_NONE 0x00000000 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_NORMAL 0x00000001 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE 13:12 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_NONE 0x00000000 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_1025 0x00000002 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT 14:14 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_NO 0x00000000 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_YES 0x00000001 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT 15:15 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_NO 0x00000000 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_YES 0x00000001 /* R---V */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPC(i) (0x00630058+(i)*2048) /* R--4A */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPC__SIZE_1 32 /* */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP422 15:0 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP444 31:16 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPD(i) (0x0063005C+(i)*2048) /* R--4A */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPD__SIZE_1 32 /* */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP422 15:0 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP444 31:16 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPE(i) (0x00630060+(i)*2048) /* R--4A */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPE__SIZE_1 32 /* */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP422 15:0 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP444 31:16 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPF(i) (0x00630064+(i)*2048) /* R--4A */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPF__SIZE_1 32 /* */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP422 15:0 /* R--VF */ +#define NV_PDISP_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP444 31:16 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA(i) (0x00616100+(i)*2048) /* R--4A */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER 0:0 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_HAS_YUV422 1:1 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_HAS_YUV422_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_HAS_YUV422_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_HSAT 2:2 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_HSAT_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_HSAT_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_OCSC 3:3 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_OCSC_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_OCSC_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_YUV422 4:4 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_YUV422_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_YUV422_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_TYPE 6:5 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_TYPE_NONE 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_TYPE_257 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_TYPE_1025 0x00000002 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_LOCATION 7:7 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_LOCATION_EARLY 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_LOCATION_LATE 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_TZ 8:8 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_TZ_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPA_TZ_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_CAPB(i) (0x00616104+(i)*2048) /* R--4A */ +#define NV_PDISP_POSTCOMP_HEAD_CAPB__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_HEAD_CAPB_MAX_PIXELS_5TAP422 15:0 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPB_MAX_PIXELS_5TAP444 31:16 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPC(i) (0x00616108+(i)*2048) /* R--4A */ +#define NV_PDISP_POSTCOMP_HEAD_CAPC__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_HEAD_CAPC_MAX_PIXELS_3TAP422 15:0 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPC_MAX_PIXELS_3TAP444 31:16 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPD(i) (0x0061610C+(i)*2048) /* R--4A */ +#define NV_PDISP_POSTCOMP_HEAD_CAPD__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_HEAD_CAPD_MAX_PIXELS_2TAP422 15:0 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPD_MAX_PIXELS_2TAP444 31:16 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPE(i) (0x00616110+(i)*2048) /* R--4A */ +#define NV_PDISP_POSTCOMP_HEAD_CAPE__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_HEAD_CAPE_MAX_PIXELS_1TAP422 15:0 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPE_MAX_PIXELS_1TAP444 31:16 /* R--UF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF(i) (0x00616114+(i)*2048) /* R--4A */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF_FULL_WIDTH 3:0 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF_UNIT_WIDTH 7:4 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF_SCLR_WIDTH 11:8 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF_HSAT_WIDTH 15:12 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF_LUT_WIDTH 19:16 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF_OCSC_WIDTH 23:20 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF_OLPF_WIDTH 27:24 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_CAPF_TZ_WIDTH 31:28 /* R--VF */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER(i) (0x0061611C+(i)*2048) /* RW-4A */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER__SIZE_1 8 /* */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE 31:0 /* RWIUF */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_HW 0x00000000 /* R---V */ +#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_SW 0x00000000 /* -W--V */ +#define NV_PDISP_RG_HEAD_CAPA(i) (0x00616300+(i)*2048) /* R--4A */ +#define NV_PDISP_RG_HEAD_CAPA__SIZE_1 8 /* */ +#define NV_PDISP_RG_HEAD_CAPA_REORDER_BANK_WIDTH_SIZE_MAX 13:0 /* R-IUF */ +#define NV_PDISP_RG_HEAD_CAPA_REORDER_BANK_WIDTH_SIZE_MAX_INIT 0x00000A00 /* R-I-V */ +#define NV_PDISP_RG_HEAD_CAPA_SUPPORT_DSC 16:16 /* R-IUF */ +#define NV_PDISP_RG_HEAD_CAPA_SUPPORT_DSC_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_HEAD_CAPA_SUPPORT_DSC_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_RG_HEAD_CAPA_SUPPORT_DSC_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_RG_SWAP_LOCKOUT(i) (0x00616304+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_SWAP_LOCKOUT__SIZE_1 8 /* */ +#define NV_PDISP_RG_SWAP_LOCKOUT_START 15:0 /* RWIUF */ +#define NV_PDISP_RG_SWAP_LOCKOUT_START_INIT 0x00000004 /* RWI-V */ +#define NV_PDISP_RG_ELV(i) (0x00616308+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_ELV__SIZE_1 8 /* */ +#define NV_PDISP_RG_ELV_START 14:0 /* RWIUF */ +#define NV_PDISP_RG_ELV_START_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_RG_UNDERFLOW(i) (0x0061630C+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_UNDERFLOW__SIZE_1 8 /* */ +#define NV_PDISP_RG_UNDERFLOW_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_RG_UNDERFLOW_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNDERFLOW_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_RG_UNDERFLOW_ENABLE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED 4:4 /* RWIVF */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_CLR 0x00000001 /* -W--V */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_YES 0x00000001 /* R---V */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_NO 0x00000000 /* R---V */ +#define NV_PDISP_RG_UNDERFLOW_MODE 8:8 /* RWIVF */ +#define NV_PDISP_RG_UNDERFLOW_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNDERFLOW_MODE_REPEAT 0x00000000 /* RW--V */ +#define NV_PDISP_RG_UNDERFLOW_MODE_RED 0x00000001 /* RW--V */ +#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED 23:16 /* R-IVF */ +#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST 24:24 /* RWIVF */ +#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_DONE 0x00000000 /* R---V */ +#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_RG_UNDERFLOW_PIXEL__SIZE_1 8 /* */ +#define NV_PDISP_RG_UNDERFLOW_PIXEL_CNT 31:0 /* RWIVF */ +#define NV_PDISP_RG_UNDERFLOW_PIXEL_CNT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_UNDERFLOW_PIXEL_CNT_CLR 0x00000000 /* -W--V */ +#define NV_PDISP_RG_STATUS(i) (0x00616314+(i)*2048) /* R--4A */ +#define NV_PDISP_RG_STATUS__SIZE_1 8 /* */ +#define NV_PDISP_RG_STATUS_STALLED 3:3 /* R--VF */ +#define NV_PDISP_RG_STATUS_STALLED_NO 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_STALLED_YES 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_EXTERNAL_UNSTALL_EVENT_CNT 8:5 /* R-IVF */ +#define NV_PDISP_RG_STATUS_EXTERNAL_UNSTALL_EVENT_CNT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_STATUS_RG_UNSTALL_CNT 12:9 /* R-IVF */ +#define NV_PDISP_RG_STATUS_RG_UNSTALL_CNT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE 15:14 /* R--VF */ +#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_SLEEP 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_SNOOZE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_AWAKE 0x00000002 /* R---V */ +#define NV_PDISP_RG_STATUS_HSYNC 16:16 /* R--VF */ +#define NV_PDISP_RG_STATUS_HSYNC_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_HSYNC_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_HBLNK 17:17 /* R--VF */ +#define NV_PDISP_RG_STATUS_HBLNK_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_HBLNK_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_VSYNC 20:20 /* R--VF */ +#define NV_PDISP_RG_STATUS_VSYNC_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_VSYNC_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_VBLNK 21:21 /* R--VF */ +#define NV_PDISP_RG_STATUS_VBLNK_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_VBLNK_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_FID 22:22 /* R--UF */ +#define NV_PDISP_RG_STATUS_FID_FLD0 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_FID_FLD1 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_BLNK 24:24 /* R--VF */ +#define NV_PDISP_RG_STATUS_BLNK_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_BLNK_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_VACT_SPACE 25:25 /* R--VF */ +#define NV_PDISP_RG_STATUS_VACT_SPACE_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_VACT_SPACE_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_STEREO 27:27 /* R--VF */ +#define NV_PDISP_RG_STATUS_STEREO_RIGHT 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_STEREO_LEFT 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_VIEWPORT 28:28 /* R--VF */ +#define NV_PDISP_RG_STATUS_VIEWPORT_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_VIEWPORT_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_BORDER 29:29 /* R--VF */ +#define NV_PDISP_RG_STATUS_BORDER_INACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_BORDER_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_LOCKED 30:30 /* R--VF */ +#define NV_PDISP_RG_STATUS_LOCKED_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_LOCKED_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_RG_STATUS_FLIPLOCKED 31:31 /* R--VF */ +#define NV_PDISP_RG_STATUS_FLIPLOCKED_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_RG_STATUS_FLIPLOCKED_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP(i) (0x00616318+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP__SIZE_1 8 /* */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_VALUE 19:0 /* RWIUF */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE 28:28 /* RWIUF */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE 29:29 /* RWIUF */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_IMMEDIATE 0x00000000 /* RW--V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_CORE 0x00000001 /* RW--V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS 31:30 /* R--UF */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ARMED 0x00000001 /* R---V */ +#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ASSEMBLY 0x00000002 /* R---V */ +#define NV_PDISP_RG_IN_LOADV_COUNTER(i) (0x00616320+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_IN_LOADV_COUNTER__SIZE_1 8 /* */ +#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE 31:0 /* RWIUF */ +#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_RG_DPCA(i) (0x00616330+(i)*2048) /* R--4A */ +#define NV_PDISP_RG_DPCA__SIZE_1 8 /* */ +#define NV_PDISP_RG_DPCA_LINE_CNT 15:0 /* R--UF */ +#define NV_PDISP_RG_DPCA_FRM_CNT 31:16 /* R--UF */ +#define NV_PDISP_RG_DPCB(i) (0x00616334+(i)*2048) /* R--4A */ +#define NV_PDISP_RG_DPCB__SIZE_1 8 /* */ +#define NV_PDISP_RG_DPCB_PIXEL_CNT 15:0 /* R--UF */ +#define NV_PDISP_RG_LINE_A_INTR(i) (0x00616348+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_LINE_A_INTR__SIZE_1 8 /* */ +#define NV_PDISP_RG_LINE_A_INTR_LINE_CNT 15:0 /* RWIUF */ +#define NV_PDISP_RG_LINE_A_INTR_LINE_CNT_INIT 0x0000FFFF /* RWI-V */ +#define NV_PDISP_RG_LINE_A_INTR_ENABLE 31:31 /* RWIUF */ +#define NV_PDISP_RG_LINE_A_INTR_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_LINE_A_INTR_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_RG_LINE_A_INTR_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_RG_LINE_B_INTR(i) (0x0061634C+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_LINE_B_INTR__SIZE_1 8 /* */ +#define NV_PDISP_RG_LINE_B_INTR_LINE_CNT 15:0 /* RWIUF */ +#define NV_PDISP_RG_LINE_B_INTR_LINE_CNT_INIT 0x0000FFFF /* RWI-V */ +#define NV_PDISP_RG_LINE_B_INTR_ENABLE 31:31 /* RWIUF */ +#define NV_PDISP_RG_LINE_B_INTR_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_LINE_B_INTR_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_RG_LINE_B_INTR_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH(i) (0x00616360+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH__SIZE_1 8 /* */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_HEIGHT 13:0 /* R-IUF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_HEIGHT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE 14:14 /* R-IVF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_NO 0x00000000 /* R---V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_YES 0x00000001 /* R---V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_DBG 15:15 /* RWIUF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_DBG_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_HEIGHT 29:16 /* RWIUF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_HEIGHT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE 30:30 /* RWIVF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE 31:31 /* RW-VF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_DONE 0x00000000 /* R---V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH(i) (0x00616364+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH__SIZE_1 8 /* */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_HEIGHT 13:0 /* R-IUF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_HEIGHT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE 14:14 /* R-IVF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_NO 0x00000000 /* R---V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_YES 0x00000001 /* R---V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_DBG 15:15 /* RWIUF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_DBG_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_HEIGHT 29:16 /* RWIUF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_HEIGHT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE 30:30 /* RWIVF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE 31:31 /* RW-VF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_DONE 0x00000000 /* R---V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_RG_RASTER_EXTEND(i) (0x00616368+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_RASTER_EXTEND__SIZE_1 8 /* */ +#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_WIDTH 13:0 /* R-IUF */ +#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_WIDTH_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE 14:14 /* R-IVF */ +#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_NO 0x00000000 /* R---V */ +#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_YES 0x00000001 /* R---V */ +#define NV_PDISP_RG_RASTER_EXTEND_DBG 15:15 /* RWIUF */ +#define NV_PDISP_RG_RASTER_EXTEND_DBG_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_EXTEND_SET_WIDTH 29:16 /* RWIUF */ +#define NV_PDISP_RG_RASTER_EXTEND_SET_WIDTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE 30:30 /* RWIVF */ +#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_RG_RASTER_EXTEND_UPDATE 31:31 /* RW-VF */ +#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_DONE 0x00000000 /* R---V */ +#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_RG_HEAD_CLK_CAP(i) (0x006163C0+(i)*2048) /* R--4A */ +#define NV_PDISP_RG_HEAD_CLK_CAP__SIZE_1 8 /* */ +#define NV_PDISP_RG_HEAD_CLK_CAP_PCLK_MAX 7:0 /* R-IUF */ +#define NV_PDISP_RG_HEAD_CLK_CAP_PCLK_MAX_INIT 0x00000085 /* R-I-V */ +#define NV_PDISP_RG_MISC_CTL(i) (0x006163C4+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_MISC_CTL__SIZE_1 8 /* */ +#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL 4:4 /* RWIVF */ +#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_DONE 0x00000000 /* R---V */ +#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST 13:13 /* RWIVF */ +#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_DONE 0x00000000 /* R---V */ +#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY(i) (0x006163C8+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY__SIZE_1 8 /* */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH 3:0 /* RWIUF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_TWO 0x00000001/* RW--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH 7:4 /* RWIUF */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_TWO 0x00000001 /* RW--V */ +#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER(i) (0x00616208+(i)*2048) /* RW-4A */ +#define NV_PDISP_CURSOR_PIPE_METER__SIZE_1 8 /* */ +#define NV_PDISP_CURSOR_PIPE_METER_VAL 15:0 /* RWIUF */ +#define NV_PDISP_CURSOR_PIPE_METER_VAL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_CURSOR_PIPE_METER_RATIO 15:14 /* RWIUF */ +#define NV_PDISP_CURSOR_PIPE_METER_RATIO_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_1 0x00000000 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_2 0x00000001 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_4 0x00000002 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_8 0x00000003 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER_PXVAL 13:0 /* RWIUF */ +#define NV_PDISP_CURSOR_PIPE_METER_PXVAL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE 28:28 /* RWIVF */ +#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER_UPDATE 29:29 /* RWIVF */ +#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_IMMEDIATE 0x00000000 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_CORE 0x00000001 /* RW--V */ +#define NV_PDISP_CURSOR_PIPE_METER_STATUS 31:30 /* R--VF */ +#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ACTIVE 0x00000000 /* R---V */ +#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ARMED 0x00000001 /* R---V */ +#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ASSEMBLY 0x00000002 /* R---V */ +#define NV_PDISP_SF_TEST(i) (0x0061650C+(i)*2048) /* R--4A */ +#define NV_PDISP_SF_TEST__SIZE_1 8 /* */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE 9:8 /* R--UF */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_SLEEP 0x00000000 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_SNOOZE 0x00000001 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_AWAKE 0x00000002 /* R---V */ +#define NV_PDISP_SF_TEST_OWNER_MASK 13:10 /* R--UF */ +#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD0 0x00000001 /* R---V */ +#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD1 0x00000002 /* R---V */ +#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD2 0x00000004 /* R---V */ +#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD3 0x00000008 /* R---V */ +#define NV_PDISP_SF_TEST_OWNER_MASK_NONE 0x00000000 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG(i) (2*(i)+15):(2*(i)+14) /* R--UF */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG__SIZE_1 2 /* */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG_SLEEP 0x00000000 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG_SNOOZE 0x00000001 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG_AWAKE 0x00000002 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG0 15:14 /* R--UF */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG0_SLEEP 0x00000000 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG0_SNOOZE 0x00000001 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG0_AWAKE 0x00000002 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG1 17:16 /* R--UF */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG1_SLEEP 0x00000000 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG1_SNOOZE 0x00000001 /* R---V */ +#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG1_AWAKE 0x00000002 /* R---V */ +#define NV_PDISP_SF_AUDIO_CNTRL0(i) (0x00616528+(i)*2048) /* RW-4A */ +#define NV_PDISP_SF_AUDIO_CNTRL0__SIZE_1 8 /* */ +#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY 6:4 /* RWIVF */ +#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_INIT 0x00000007 /* RWI-V */ +#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_NONE 0x00000007 /* RW--V */ +#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_ONE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_TWO 0x00000002 /* RW--V */ +#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_THREE 0x00000003 /* RW--V */ +#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH 12:12 /* RWIVF */ +#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_ENABLED 0x00000001 /* RW--V */ +#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_DISABLED 0x00000000 /* RW--V */ +#define NV_PDISP_SF_SPARE0(i) (0x00616530+(i)*2048) /* RWI4A */ +#define NV_PDISP_SF_SPARE0__SIZE_1 8 /* */ +#define NV_PDISP_SF_SPARE0_DP_VERSION 0:0 /* RWIVF */ +#define NV_PDISP_SF_SPARE0_DP_VERSION_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_SPARE0_DP_VERSION_11 0x00000000 /* RW--V */ +#define NV_PDISP_SF_SPARE0_DP_VERSION_12 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL(i) (0x00616540+(i)*2048) /* RW-4A */ +#define NV_PDISP_SF_DP_LINKCTL__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_LINKCTL_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_TUSIZE 8:2 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_TUSIZE_INIT 0x00000040 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE 10:10 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT 11:11 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_PRIMARY 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_SECONDARY 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_RESERVED 13:12 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_RESERVED_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME 14:14 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL 15:15 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_ONE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_TWO 0x00000003 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_FOUR 0x0000000F /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_EIGHT 0x000000FF /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE 24:24 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE 25:25 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_LOADV 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_IMMEDIATE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN 26:26 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_DONE 0x00000000 /* R---V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_TRIGGER 0x00000001 /* -W--T */ +#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST 27:27 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE 30:30 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_SINGLE_STREAM 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_MULTI_STREAM 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE 31:31 /* RWIVF */ +#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_MN(i) (0x0061654C+(i)*2048) /* RW-4A */ +#define NV_PDISP_SF_DP_MN__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_MN_N_VAL 23:0 /* RWIVF */ +#define NV_PDISP_SF_DP_MN_N_VAL_INIT 0x00008000 /* RWI-V */ +#define NV_PDISP_SF_DP_MN_M_DELTA 27:24 /* RWIVF */ +#define NV_PDISP_SF_DP_MN_M_DELTA_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE 28:28 /* RWIVF */ +#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_MN_M_MOD 31:30 /* RWIVF */ +#define NV_PDISP_SF_DP_MN_M_MOD_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_MN_M_MOD_NONE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_MN_M_MOD_INC 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_MN_M_MOD_DEC 0x00000002 /* RW--V */ +#define NV_PDISP_SF_DP_CONFIG(i) (0x00616550+(i)*2048) /* RW-4A */ +#define NV_PDISP_SF_DP_CONFIG__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_CONFIG_WATERMARK 5:0 /* RWIVF */ +#define NV_PDISP_SF_DP_CONFIG_WATERMARK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_COUNT 14:8 /* RWIVF */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_COUNT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_FRAC 19:16 /* RWIVF */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_FRAC_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY 24:24 /* RWIVF */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE 27:26 /* RWIVF */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_INIT 0x00000002 /* RWI-V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_LEGACY 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_AUTO 0x00000002 /* RW--V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL(i) (0x00616560+(i)*2048) /* RWI4A */ +#define NV_PDISP_SF_DP_AUDIO_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE 3:2 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_AUTO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_DISABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_ENABLE 0x00000002 /* RW--V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_PACKETID 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_PACKETID_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS 21:21 /* R--VF */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS_ENABLE 0x00000001 /* R---V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS_DISABLE 0x00000000 /* R---V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS 31:31 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_DONE 0x00000000 /* R---V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_TRIGGER 0x00000001 /* -W--T */ +#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS(i) (0x00616568+(i)*2048) /* RWI4A */ +#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_VALUE 16:0 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS(i) (0x0061656C+(i)*2048) /* RWI4A */ +#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_VALUE 20:0 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_STREAM_CTL(i) (0x00616578+(i)*2048) /* RW-4A */ +#define NV_PDISP_SF_DP_STREAM_CTL__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_STREAM_CTL_START 5:0 /* RWIVF */ +#define NV_PDISP_SF_DP_STREAM_CTL_START_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH 13:8 /* RWIVF */ +#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_STREAM_CTL_START_ACTIVE 21:16 /* R-IVF */ +#define NV_PDISP_SF_DP_STREAM_CTL_START_ACTIVE_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_ACTIVE 29:24 /* R-IVF */ +#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_ACTIVE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SF_DP_STREAM_BW(i) (0x0061657C+(i)*2048) /* RW-4A */ +#define NV_PDISP_SF_DP_STREAM_BW__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_STREAM_BW_ALLOCATED 15:0 /* RWIVF */ +#define NV_PDISP_SF_DP_STREAM_BW_ALLOCATED_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_STREAM_BW_TIMESLICE 31:16 /* RWIVF */ +#define NV_PDISP_SF_DP_STREAM_BW_TIMESLICE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED__SIZE_2 6 /* */ +#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED_VALUE 31:0 /* RWIVF */ +#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_STREAM_BW_RESERVED__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_STREAM_BW_RESERVED__SIZE_2 6 /* */ +#define NV_PDISP_SF_DP_STREAM_BW_RESERVED_VALUE 31:0 /* RWIVF */ +#define NV_PDISP_SF_DP_STREAM_BW_RESERVED_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY(i,j) (((j)==0)?(0x00616578+(i)*2048):(0x00616584+(i)*2048)+((j)-1)*8) /* */ +#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY__SIZE_2 2 /* */ +#define NV_PDISP_SF_DP_STREAM_BW_ARRAY(i,j) (((j)==0)?(0x0061657C+(i)*2048):(0x00616588+(i)*2048)+((j)-1)*8) /* */ +#define NV_PDISP_SF_DP_STREAM_BW_ARRAY__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_STREAM_BW_ARRAY__SIZE_2 2 /* */ +#define NV_PDISP_SF_HDMI_CTRL(i) (0x006165C0+(i)*2048) /* RWX4A */ +#define NV_PDISP_SF_HDMI_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_CTRL_REKEY 6:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_CTRL_REKEY_INIT 0x00000038 /* RWI-V */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT 8:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_2CH 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_8CH 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT 10:10 /* RWIVF */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT_HW_BASED 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT_SW_BASED 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT 12:12 /* RWIVF */ +#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT_CLR 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT_SET 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_CTRL_MAX_AC_PACKET 20:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_CTRL_MAX_AC_PACKET_INIT 0x00000002 /* RWI-V */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO 24:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_CTRL_AUDIO_EN 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_HDMI_CTRL_ENABLE 30:30 /* RWIVF */ +#define NV_PDISP_SF_HDMI_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW(i) (0x006165C8+(i)*2048) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_END 9:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_END_INIT 0x00000210 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_START 25:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_START_INIT 0x00000200 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE 31:31 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_YES 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x006F0000+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x006F0004+(i)*1024) /* R--4A */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x006F0008+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x006F000C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x006F0010+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x006F0014+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x006F0018+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL(i) (0x006F0040+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER 4:4 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK 12:12 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GENERIC_STATUS(i) (0x006F0044+(i)*1024) /* R--4A */ +#define NV_PDISP_SF_HDMI_GENERIC_STATUS__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT 0:0 /* R-IVF */ +#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SF_HDMI_GENERIC_HEADER(i) (0x006F0048+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_HEADER__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x006F004C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x006F0050+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x006F0054+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x006F0058+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x006F005C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x006F0060+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x006F0064+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x006F0068+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL(i) (0x006F0080+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_ACR_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE 16:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_YES 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY 20:20 /* RWIVF */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_HIGH 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_LOW 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS 27:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_INIT 0x00000002 /* RWI-V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_32KHZ 0x00000003 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_44_1KHZ 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_48KHZ 0x00000002 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_88_2KHZ 0x00000008 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_96KHZ 0x0000000A /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_176_4KHZ 0x0000000C /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_192KHZ 0x0000000E /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE 31:31 /* RWIVF */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_HW 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_SW 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_GCP_CTRL(i) (0x006F00C0+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GCP_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER 4:4 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS(i) (0x006F00C4+(i)*1024) /* R--4A */ +#define NV_PDISP_SF_HDMI_GCP_STATUS__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT 0:0 /* R-IVF */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP 6:4 /* R--VF */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_0 0x00000004 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_1 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_2 0x00000002 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_3 0x00000003 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP 10:8 /* R--VF */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_0 0x00000004 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_1 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_2 0x00000002 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_3 0x00000003 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP 14:12 /* R--VF */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_0 0x00000004 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_1 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_2 0x00000002 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_3 0x00000003 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP 18:16 /* R--VF */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_0 0x00000004 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_1 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_2 0x00000002 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_3 0x00000003 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP 22:20 /* R--VF */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_0 0x00000004 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_1 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_2 0x00000002 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_3 0x00000003 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP 26:24 /* R--VF */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_0 0x00000004 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_1 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_2 0x00000002 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_3 0x00000003 /* R---V */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK(i) (0x006F00CC+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL(i) (0x006F0100+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_NO 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER 4:4 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE 8:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW 9:9 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT 16:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */ +#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_STATUS(i) (0x006F0104+(i)*1024) /* R--4A */ +#define NV_PDISP_SF_HDMI_VSI_STATUS__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT 0:0 /* R-IVF */ +#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_DONE 0x00000001 /* R---V */ +#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_WAITING 0x00000000 /* R---V */ +#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SF_HDMI_VSI_HEADER(i) (0x006F0108+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_HEADER__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x006F010C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x006F0110+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x006F0114+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x006F0118+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x006F011C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x006F0120+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x006F0124+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x006F0128+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 8 /* */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */ +#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL(i) (0x006F0300+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE 1:1 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_DONE 0x00000000 /* R---V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_TRIGGER 0x00000001 /* -W--T */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE 2:2 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER(i) (0x006F0304+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0(i) (0x006F0308+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB3 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1(i) (0x006F030C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB4 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB5 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB6 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB7 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2(i) (0x006F0310+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB8 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB9 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB10 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB11 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3(i) (0x006F0314+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB12 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB13 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB14 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB15 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4(i) (0x006F0318+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB16 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB17 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB18 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB19 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5(i) (0x006F031C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB20 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB21 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB22 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB23 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6(i) (0x006F0320+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB24 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB25 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB26 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB27 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7(i) (0x006F0324+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB28 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB29 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB30 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB31 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL(i) (0x006F0330+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE 4:4 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER(i) (0x006F0334+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER(i) (0x006F0344+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB3 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0(i) (0x006F0348+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB0 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB1 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB2 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB3 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1(i) (0x006F034C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB4 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB5 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB6 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB7 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2(i) (0x006F0350+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB8 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB9 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB10 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB11 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3(i) (0x006F0354+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB12 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB13 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB14 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB15 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4(i) (0x006F0358+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB16 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB17 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB18 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB19 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5(i) (0x006F035C+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB20 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB21 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB22 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB23 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6(i) (0x006F0360+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB24 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB25 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB26 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB27 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7(i) (0x006F0364+(i)*1024) /* RWX4A */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7__SIZE_1 8 /* */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB28 7:0 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB29 15:8 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB30 23:16 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB31 31:24 /* RWIVF */ +#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_CAP(i) (0x0061C000+(i)*2048) /* R--4A */ +#define NV_PDISP_SOR_CAP__SIZE_1 8 /* */ +#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18 0:0 /* R--VF */ +#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24 1:1 /* R--VF */ +#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_DUAL_LVDS_18 2:2 /* R--VF */ +#define NV_PDISP_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_DUAL_LVDS_24 3:3 /* R--VF */ +#define NV_PDISP_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A 8:8 /* R--VF */ +#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B 9:9 /* R--VF */ +#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_DUAL_TMDS 11:11 /* R--VF */ +#define NV_PDISP_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* R--VF */ +#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_SDI 16:16 /* R--VF */ +#define NV_PDISP_SOR_CAP_SDI_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_SDI_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_DP_A 24:24 /* R--VF */ +#define NV_PDISP_SOR_CAP_DP_A_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_DP_A_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_DP_B 25:25 /* R--VF */ +#define NV_PDISP_SOR_CAP_DP_B_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_DP_B_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_DP_INTERLACE 26:26 /* R--VF */ +#define NV_PDISP_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_DP_8_LANES 27:27 /* R--VF */ +#define NV_PDISP_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_CAP_LVDS_ONLY 31:31 /* R--VF */ +#define NV_PDISP_SOR_CAP_LVDS_ONLY_FALSE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_CAP_LVDS_ONLY_TRUE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_PWR(i) (0x0061C004+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_PWR__SIZE_1 8 /* */ +#define NV_PDISP_SOR_PWR_NORMAL_STATE 0:0 /* RWIVF */ +#define NV_PDISP_SOR_PWR_NORMAL_STATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_PWR_NORMAL_STATE_PD 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_PWR_NORMAL_STATE_PU 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_PWR_NORMAL_START 1:1 /* RWIVF */ +#define NV_PDISP_SOR_PWR_NORMAL_START_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_PWR_NORMAL_START_NORMAL 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_PWR_NORMAL_START_ALT 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_PWR_SAFE_STATE 16:16 /* RWIVF */ +#define NV_PDISP_SOR_PWR_SAFE_STATE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_PWR_SAFE_STATE_PD 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_PWR_SAFE_STATE_PU 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_PWR_SAFE_START 17:17 /* RWIVF */ +#define NV_PDISP_SOR_PWR_SAFE_START_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_PWR_SAFE_START_NORMAL 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_PWR_SAFE_START_ALT 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_PWR_HALT_DELAY 24:24 /* R--VF */ +#define NV_PDISP_SOR_PWR_HALT_DELAY_DONE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_PWR_HALT_DELAY_ACTIVE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_PWR_MODE 28:28 /* R-IVF */ +#define NV_PDISP_SOR_PWR_MODE_INIT 0x00000001 /* R-I-V */ +#define NV_PDISP_SOR_PWR_MODE_NORMAL 0x00000000 /* R---V */ +#define NV_PDISP_SOR_PWR_MODE_SAFE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_PWR_SETTING_NEW 31:31 /* RWIVF */ +#define NV_PDISP_SOR_PWR_SETTING_NEW_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SOR_PWR_SETTING_NEW_DONE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_PWR_SETTING_NEW_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_SOR_PWR_SETTING_NEW_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_SOR_TEST(i) (0x0061C008+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_TEST__SIZE_1 8 /* */ +#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE 9:8 /* R--UF */ +#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_SLEEP 0x00000000 /* R---V */ +#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE 0x00000001 /* R---V */ +#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_AWAKE 0x00000002 /* R---V */ +#define NV_PDISP_SOR_TEST_OWNER_MASK 13:10 /* R--UF */ +#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD0 0x00000001 /* R---V */ +#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD1 0x00000002 /* R---V */ +#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD2 0x00000004 /* R---V */ +#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD3 0x00000008 /* R---V */ +#define NV_PDISP_SOR_TEST_OWNER_MASK_NONE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_PWM_DIV(i) (0x0061C080+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_PWM_DIV__SIZE_1 8 /* */ +#define NV_PDISP_SOR_PWM_DIV_DIVIDE 23:0 /* RWIUF */ +#define NV_PDISP_SOR_PWM_DIV_DIVIDE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_PWM_CTL(i) (0x0061C084+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_PWM_CTL__SIZE_1 8 /* */ +#define NV_PDISP_SOR_PWM_CTL_DUTY_CYCLE 23:0 /* RWIUF */ +#define NV_PDISP_SOR_PWM_CTL_DUTY_CYCLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_PWM_CTL_CLKSEL 30:30 /* RWIUF */ +#define NV_PDISP_SOR_PWM_CTL_CLKSEL_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_PWM_CTL_CLKSEL_PCLK 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_PWM_CTL_CLKSEL_XTAL 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW 31:31 /* RWIVF */ +#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_DONE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_SOR_DP_LINKCTL(i,j) (0x0061C10C+(i)*2048+(j)*128) /* RW-4A */ +#define NV_PDISP_SOR_DP_LINKCTL__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_LINKCTL__SIZE_2 2 /* */ +#define NV_PDISP_SOR_DP_LINKCTL_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK 1:1 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME 14:14 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT 23:16 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_ONE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_TWO 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_FOUR 0x0000000F /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_EIGHT 0x000000FF /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN 27:26 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_D102 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_SBLERRRATE 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_PRBS7 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE 30:30 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_SINGLE_STREAM 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_MULTI_STREAM 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN 31:31 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK 1:1 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME 14:14 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT 23:16 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_ONE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_TWO 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_FOUR 0x0000000F /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_EIGHT 0x000000FF /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN 27:26 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_D102 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_SBLERRRATE 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_PRBS7 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE 30:30 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_SINGLE_STREAM 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_MULTI_STREAM 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN 31:31 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK 1:1 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME 14:14 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT 23:16 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_ONE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_TWO 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_FOUR 0x0000000F /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_EIGHT 0x000000FF /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN 27:26 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_D102 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_SBLERRRATE 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_PRBS7 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE 30:30 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_SINGLE_STREAM 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_MULTI_STREAM 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN 31:31 /* RWIVF */ +#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_NO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_YES 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG(i,j) (0x0061C110+(i)*2048+(j)*28) /* RW-4A */ +#define NV_PDISP_SOR_DP_TPG__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_TPG__SIZE_2 2 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN 3:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN 4:4 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING 6:6 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN 11:8 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN 12:12 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING 14:14 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN 19:16 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN 20:20 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING 22:22 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN 27:24 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN 28:28 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING 30:30 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN(i) (3+(i)*8):((i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_NOPATTERN 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING1 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING2 0x00000002 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING3 0x00000003 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_D102 0x00000004 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_SBLERRRATE 0x00000005 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_PRBS7 0x00000006 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CSTM 0x00000007 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_HBR2_COMPLIANCE 0x00000008 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CP2520_PAT1 0x00000009 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CP2520_PAT3 0x0000000A /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING4 0x0000000B /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN(i) (4+(i)*8):(4+(i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_INIT 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_ENABLE 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_DISABLE 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING(i) (6+(i)*8):(6+(i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_INIT 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_ENABLE 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_DISABLE 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG0__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN 3:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN 4:4 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING 6:6 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN 11:8 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN 12:12 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING 14:14 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN 19:16 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN 20:20 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING 22:22 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN 27:24 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN 28:28 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING 30:30 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN(i) (3+(i)*8):((i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_NOPATTERN 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING1 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING2 0x00000002 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING3 0x00000003 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_D102 0x00000004 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_SBLERRRATE 0x00000005 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_PRBS7 0x00000006 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CSTM 0x00000007 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_HBR2_COMPLIANCE 0x00000008 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CP2520_PAT1 0x00000009 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CP2520_PAT3 0x0000000A /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING4 0x0000000B /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN(i) (4+(i)*8):(4+(i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_INIT 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_ENABLE 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_DISABLE 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING(i) (6+(i)*8):(6+(i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_INIT 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_ENABLE 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_DISABLE 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG1__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN 3:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN 4:4 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING 6:6 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN 11:8 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN 12:12 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING 14:14 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN 19:16 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN 20:20 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING 22:22 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN 27:24 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_NOPATTERN 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING1 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING2 0x00000002 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING3 0x00000003 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_D102 0x00000004 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_SBLERRRATE 0x00000005 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_PRBS7 0x00000006 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CSTM 0x00000007 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING4 0x0000000B /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN 28:28 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING 30:30 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN(i) (3+(i)*8):((i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_NOPATTERN 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING1 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING2 0x00000002 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING3 0x00000003 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_D102 0x00000004 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_SBLERRRATE 0x00000005 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_PRBS7 0x00000006 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CSTM 0x00000007 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_HBR2_COMPLIANCE 0x00000008 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CP2520_PAT1 0x00000009 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CP2520_PAT3 0x0000000A /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING4 0x0000000B /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN(i) (4+(i)*8):(4+(i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_INIT 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_ENABLE 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_DISABLE 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING(i) (6+(i)*8):(6+(i)*8) /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING__SIZE_1 4 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_INIT 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_ENABLE 0x00000001 /* */ +#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_DISABLE 0x00000000 /* */ +#define NV_PDISP_SOR_DP_TPG_CONFIG(i) (0x0061C114+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_DP_TPG_CONFIG__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_TPG_CONFIG_HBR2_COMPLIANCE_PERIOD 16:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_TPG_CONFIG_HBR2_COMPLIANCE_PERIOD_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_MS_CTL(i) (0x0061C150+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_DP_MS_CTL__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT 0:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_MS_CTL_SF_MASK 11:8 /* RWIVF */ +#define NV_PDISP_SOR_DP_MS_CTL_SF_MASK_INIT 0x0000000F /* RWI-V */ +#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE 29:29 /* RWIVF */ +#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_YES 0x00000001 /* R---V */ +#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_NO 0x00000000 /* R---V */ +#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_RESET 0x00000000 /* -W--V */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH 30:30 /* RWIVF */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE 31:31 /* RWIVF */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_DONE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_SOR_DP_LQ_CSTM(i,j) (0x0061C154+(i)*2048+(j)*4) /* RW-4A */ +#define NV_PDISP_SOR_DP_LQ_CSTM__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_LQ_CSTM__SIZE_2 3 /* */ +#define NV_PDISP_SOR_DP_LQ_CSTM_SYM 31:0 /* RWIUF */ +#define NV_PDISP_SOR_DP_LQ_CSTM_SYM_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LQ_CSTM0(i) (0x0061C154+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_DP_LQ_CSTM0__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_LQ_CSTM0_SYM 31:0 /* RWIUF */ +#define NV_PDISP_SOR_DP_LQ_CSTM0_SYM_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LQ_CSTM1(i) (0x0061C158+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_DP_LQ_CSTM1__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_LQ_CSTM1_SYM 31:0 /* RWIUF */ +#define NV_PDISP_SOR_DP_LQ_CSTM1_SYM_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_LQ_CSTM2(i) (0x0061C15C+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_DP_LQ_CSTM2__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_LQ_CSTM2_SYM 31:0 /* RWIUF */ +#define NV_PDISP_SOR_DP_LQ_CSTM2_SYM_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_ECF0(i) (0x0061C160+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_DP_ECF0__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_ECF0_VALUE 31:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_ECF0_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_ECF0_VALUE_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_ECF1(i) (0x0061C164+(i)*2048) /* RW-4A */ +#define NV_PDISP_SOR_DP_ECF1__SIZE_1 8 /* */ +#define NV_PDISP_SOR_DP_ECF1_VALUE 30:0 /* RWIVF */ +#define NV_PDISP_SOR_DP_ECF1_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_DP_ECF1_VALUE_ZERO 0x00000000 /* RW--V */ +#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS 31:31 /* RWIVF */ +#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_INIT 0x00000000 /* R-I-V */ +#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_DONE 0x00000000 /* R---V */ +#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_PENDING 0x00000001 /* R---V */ +#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_TRIGGER 0x00000001 /* -W--V */ +#define NV_PDISP_SOR_HDMI2_CTRL(i) (0x0061C5BC+(i)*2048) /* RWX4A */ +#define NV_PDISP_SOR_HDMI2_CTRL__SIZE_1 8 /* */ +#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE 0:0 /* RWIVF */ +#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_DISABLE 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE 1:1 /* RWIVF */ +#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE_NORMAL 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV 2:2 /* RWIVF */ +#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV_DISABLE 0x00000000 /* RWI-V */ +#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_LENGTH 7:4 /* RWIVF */ +#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_LENGTH_INIT 0x00000008 /* RWI-V */ +#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_START 31:16 /* RWIVF */ +#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_START_INIT 0x00000214 /* RWI-V */ +#define NV_PDISP_VGA_INDIRECT_SCRATCH(i) (0x00625E00+(i)*4) /* RW-4A */ +#define NV_PDISP_VGA_INDIRECT_SCRATCH__SIZE_1 16 /* */ +#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE3 31:24 /* RWX-F */ +#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE2 23:16 /* RWX-F */ +#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE1 15:8 /* RWX-F */ +#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE0 7:0 /* RWX-F */ +#define NV_PDISP_VGA_BASE 0x00625F00 /* RW-4R */ +#define NV_PDISP_VGA_BASE_TARGET 1:0 /* RWIVF */ +#define NV_PDISP_VGA_BASE_TARGET_PHYS_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_VGA_BASE_TARGET_PHYS_NVM 0x00000001 /* RW--V */ +#define NV_PDISP_VGA_BASE_TARGET_PHYS_PCI 0x00000002 /* RW--V */ +#define NV_PDISP_VGA_BASE_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */ +#define NV_PDISP_VGA_BASE_STATUS 3:3 /* RWIVF */ +#define NV_PDISP_VGA_BASE_STATUS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_VGA_BASE_STATUS_INVALID 0x00000000 /* RW--V */ +#define NV_PDISP_VGA_BASE_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_PDISP_VGA_BASE_ADDR 31:10 /* RWIVF */ +#define NV_PDISP_VGA_BASE_ADDR_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */ +#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET 1:0 /* RWIVF */ +#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_INIT 0x00000001 /* RWI-V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_NVM 0x00000001 /* RW--V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_PCI 0x00000002 /* RW--V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */ +#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_INVALID 0x00000000 /* RW--V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */ +#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */ +#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR_INIT 0x00000000 /* RWI-V */ +#define NV_UDISP 0x006FFFFF:0x00670000 /* RW--D */ +#define NV_UDISP_PVT 0x0067FFFF:0x00670000 /* RW--D */ +#define NV_UDISP_CORE 0x0068FFFF:0x00680000 /* RW--D */ +#define NV_UDISP_REMAP 0x006FFFFF:0x00690000 /* RW--D */ +#define NV_UDISP_REMAP_PAGE0 0x0069FFFF:0x00690000 /* RW--D */ +#define NV_UDISP_REMAP_PAGE1 0x006AFFFF:0x006A0000 /* RW--D */ +#define NV_UDISP_REMAP_PAGE2 0x006BFFFF:0x006B0000 /* RW--D */ +#define NV_UDISP_REMAP_PAGE3 0x006CFFFF:0x006C0000 /* RW--D */ +#define NV_UDISP_REMAP_PAGE4 0x006DFFFF:0x006D0000 /* RW--D */ +#define NV_UDISP_REMAP_PAGE5 0x006EFFFF:0x006E0000 /* RW--D */ +#define NV_UDISP_REMAP_PAGE6 0x006FFFFF:0x006F0000 /* RW--D */ +#define NV_UDISP_FE_CORE_PUT 0x00680000 /* RW-4R */ +#define NV_UDISP_FE_CORE_PUT_POINTER 11:2 /* RWIUF */ +#define NV_UDISP_FE_CORE_PUT_POINTER_INIT 0x00000000 /* RWI-V */ +#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS 31:31 /* R-IVF */ +#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_INIT 0x00000001 /* R-I-V */ +#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_WRITABLE 0x00000000 /* R---V */ +#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_LOCKED 0x00000001 /* R---V */ +#define NV_UDISP_FE_CORE_GET 0x00680004 /* R--4R */ +#define NV_UDISP_FE_CORE_GET_POINTER 11:2 /* R--UF */ +#define NV_UDISP_FE_SAT_PUT(i) (0x00690000+(i)*4096) /* RW-4A */ +#define NV_UDISP_FE_SAT_PUT__SIZE_1 72 /* */ +#define NV_UDISP_FE_SAT_PUT_POINTER 11:2 /* RWIUF */ +#define NV_UDISP_FE_SAT_PUT_POINTER_INIT 0x00000000 /* RWI-V */ +#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS 31:31 /* R-IVF */ +#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_INIT 0x00000001 /* R-I-V */ +#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_WRITABLE 0x00000000 /* R---V */ +#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_LOCKED 0x00000001 /* R---V */ +#define NV_UDISP_FE_SAT_GET(i) (0x00690004+(i)*4096) /* R--4A */ +#define NV_UDISP_FE_SAT_GET__SIZE_1 72 /* */ +#define NV_UDISP_FE_SAT_GET_POINTER 11:2 /* R--UF */ +#define NV_UDISP_FE_PUT(i) ((i)>0?((0x00690000+((i-1)*4096))):0x00680000) /* */ +#define NV_UDISP_FE_PUT__SIZE_1 73 /* */ +#define NV_UDISP_FE_PUT_POINTER 11:2 /* */ +#define NV_UDISP_FE_PUT_POINTER_INIT 0x00000000 /* */ +#define NV_UDISP_FE_PUT_POINTER_STATUS 31:31 /* */ +#define NV_UDISP_FE_PUT_POINTER_STATUS_INIT 0x00000001 /* */ +#define NV_UDISP_FE_PUT_POINTER_STATUS_WRITABLE 0x00000000 /* */ +#define NV_UDISP_FE_PUT_POINTER_STATUS_LOCKED 0x00000001 /* */ +#define NV_UDISP_FE_GET(i) ((i)>0?((0x00690004+((i-1)*4096))):0x00680004) /* */ +#define NV_UDISP_FE_GET__SIZE_1 73 /* */ +#define NV_UDISP_FE_GET_POINTER 11:2 /* */ +#define NV_UDISP_FE_CHN_ARMED_PCALC 0x00670000 /* R--4R */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN_PVT(i) (0x00674000+(i)*1024) /* R--4A */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN_PVT__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN_PVT(i) (0x00674200+(i)*1024) /* R--4A */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN_PVT__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_ASSY_CORE_PVT 0x0067E000 /* R--4R */ +#define NV_UDISP_FE_CHN_ARMED_CORE_PVT 0x0067E800 /* R--4R */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE 0x00680000 /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE (0x00680000+32768) /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i) ((0x00690000+(i)*4096)) /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN(i) ((0x00690000+(i)*4096)+2048) /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i) ((0x00690000+((i+32)*4096))) /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_WINIM(i) ((0x00690000+((i+32)*4096))+2048) /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_WINIM__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i) (0x006D8000+(i)*4096) /* RW-4A */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS__SIZE_1 8 /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_CURS(i) (0x006D8800+(i)*4096) /* R--4A */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR_CURS__SIZE_1 8 /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR(i) ((i)>0?(((0x00690000+(i-1)*4096))):0x00680000) /* */ +#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1 81 /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR(i) ((i)>0?(((0x00690000+(i-1)*4096)+2048)):(0x00680000+32768)) /* */ +#define NV_UDISP_FE_CHN_ARMED_BASEADR__SIZE_1 81 /* */ +#define NV_UDISP_FE_CHN_PCALC 0x00670000 /* R--4R */ +#define NV_UDISP_FE_CHN_CORE_PVT 0x0067E000 /* R--4R */ +#define NV_UDISP_FE_CHN_WIN_PVT(i) (0x00674000+(i)*1024) /* R--4A */ +#define NV_UDISP_FE_CHN_WIN_PVT__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_CORE_VARIABLES 0x0067E400 /* R--4R */ +#define NV_UDISP_FE_CHN_LOCAL 0x0067E800 /* R--4R */ +#define NV_UDISP_FE_CHN_CORE 0x00680000 /* */ +#define NV_UDISP_FE_CHN_WIN(i) (((0x00690000+(i)*4096))) /* */ +#define NV_UDISP_FE_CHN_WIN__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_WINIM(i) (((0x00690000+((i+32)*4096)))) /* */ +#define NV_UDISP_FE_CHN_WINIM__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_CURS(i) ((0x006D8000+(i)*4096)) /* */ +#define NV_UDISP_FE_CHN_CURS__SIZE_1 8 /* */ +#define NV_UDISP_FE_CHN_CORE_BASEADR 0x00680000 /* */ +#define NV_UDISP_FE_CHN_WIN_BASEADR(i) (((0x00690000+(i)*4096))) /* */ +#define NV_UDISP_FE_CHN_WIN_BASEADR__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_WINIM_BASEADR(i) (((0x00690000+((i+32)*4096)))) /* */ +#define NV_UDISP_FE_CHN_WINIM_BASEADR__SIZE_1 32 /* */ +#define NV_UDISP_FE_CHN_CURS_BASEADR(i) ((0x006D8000+(i)*4096)) /* */ +#define NV_UDISP_FE_CHN_CURS_BASEADR__SIZE_1 8 /* */ +#define NV_UDISP_DMA /* ----G */ +#define NV_UDISP_DMA_OPCODE 31:29 /* RWXVF */ +#define NV_UDISP_DMA_OPCODE_METHOD 0x00000000 /* RW--V */ +#define NV_UDISP_DMA_OPCODE_JUMP 0x00000001 /* RW--V */ +#define NV_UDISP_DMA_OPCODE_NONINC_METHOD 0x00000002 /* RW--V */ +#define NV_UDISP_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 /* RW--V */ +#define NV_UDISP_DMA_METHOD_COUNT 27:18 /* RWXUF */ +#define NV_UDISP_DMA_METHOD_OFFSET 13:2 /* RWXUF */ +#define NV_UDISP_DMA_DATA 31:0 /* RWXUF */ +#define NV_UDISP_DMA_DATA_NOP 0x00000000 /* RW--V */ +#define NV_UDISP_DMA_JUMP_OFFSET 11:2 /* RWXUF */ +#define NV_UDISP_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 /* RWXUF */ diff --git a/Falcon-Security/Falcon-Security.html b/Falcon-Security/Falcon-Security.html new file mode 100644 index 0000000..4b64d0d --- /dev/null +++ b/Falcon-Security/Falcon-Security.html @@ -0,0 +1,840 @@ + + + + + +NVIDIA Falcon Security + + + + + +
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NVIDIA GPUs embed several microprocessors based on a custom architecture called +"Falcon". Starting with the Maxwell family of GPUs, these microprocessors are +changing to be able to better protect the hardware from being misprogrammed.

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Falcon security modes

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A Falcon microprocessor supporting advanced security modes can run in one of +three modes. Not all Falcon microprocessors on a GPU support all modes.

+
    +
  • +

    +Non-secure (NS). In this mode, functionality is similar to Falcon + architectures before security modes were introduced (pre-Maxwell), but + capability is restricted. In particular, certain registers may be + inaccessible for reads and/or writes, and physical memory access may be + disabled (on certain Falcon instances). + This is the only possible mode that can be used if you don’t have + microcode cryptographically signed by NVIDIA. +

    +
    • +
  • +

    +Heavy Secure (HS). In this mode, the microprocessor is a black box — it’s + not possible to read or write any Falcon internal state or Falcon registers + from outside the Falcon (for example, from the host system). The only way to + enable this mode is by loading microcode that has been signed by NVIDIA. + (The loading process involves tagging the IMEM block as secure, writing the + signature into a Falcon register, and starting execution. The hardware will + validate the signature, and if valid, grant HS privileges.) +

    +
    • +
  • +

    +Light Secure (LS). In this mode, the microprocessor has more privileges than + NS but fewer than HS. Some of the microprocessor state is visible to host + software to ease debugging. The only way to enable this mode is by HS + microcode enabling LS mode. Some privileges available to HS mode are not + available here. LS mode is introduced in GM20x. +

    +
    • +
+
+
+
+

GM10x

+
+

The intent for GM10x is to protect fuses and ROM from being written by +incorrect or malicious software.

+

This is implemented by preventing access to select GPU registers from anything +other than a Falcon running in a secure mode.

+
+
+
+

GM20x

+
+

The intent for GM20x is to improve upon the GM10x implementation and add some +protection to the configuration of the hardware thermal shutdown mechanism.

+

In addition to the registers protected by GM10x:

+
    +
  • +

    +Thermal shutdown registers are protected and can only be written from a + secure microprocessor context. These registers can be broken down into two + categories: +

    +
      +
    • +

      +Thermal sensor setup +

      +
      • +
    • +

      +The temperature beyond which hardware triggers a forced shutdown to + prevent damage. +

      +
      • +
    +
    • +
  • +

    +I2C bus C writes are restricted to a secure context, to prevent + misprogramming thermal sensors. +

    +
    • +
  • +

    +A new mechanism is introduced to prevent microcode tampering after load. This + is achieved by placing microcode in a write-protected region of memory. +

    +
    • +
  • +

    +Physical memory access restrictions are introduced. On all Falcons other + than PMU (the "kitchen sink" Falcon) and DPU (the Falcon that services + display), microprocessors running in NS mode will be unable to access + physical memory (they may use virtual memory exclusively). In particular, + this includes all microprocessors which perform work directly in response to + userspace requests. +

    +
    • +
  • +

    +Devinit scripts are signed and executed on the PMU so that these scripts can + configure protected registers like thermal shutdown parameters. +

    +
    • +
+
+
+
+
+ + + diff --git a/Host-Fifo/volta/gv100/dev_bus.ref.txt b/Host-Fifo/volta/gv100/dev_bus.ref.txt new file mode 100644 index 0000000..488e265 --- /dev/null +++ b/Host-Fifo/volta/gv100/dev_bus.ref.txt @@ -0,0 +1,316 @@ +Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +#define NV_PBUS_SW_SCRATCH(i) (0x00001580+(i)*4) /* RW-4A */ +#define NV_PBUS_SW_SCRATCH__SIZE_1 32 /* */ +#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */ +#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_0 0x00001100 /* RW-4R */ +#define NV_PBUS_INTR_0_PRI_SQUASH 1:1 /* RWIVF */ +#define NV_PBUS_INTR_0_PRI_SQUASH_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_PRI_SQUASH_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_PRI_SQUASH_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 /* RWIVF */ +#define NV_PBUS_INTR_0_PRI_FECSERR_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_PRI_FECSERR_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_PRI_FECSERR_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 /* RWIVF */ +#define NV_PBUS_INTR_0_PRI_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_PRI_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_PRI_TIMEOUT_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_FB_REQ_TIMEOUT 4:4 /* RWIVF */ +#define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */ +#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_FB_ACK_EXTRA 6:6 /* RWIVF */ +#define NV_PBUS_INTR_0_FB_ACK_EXTRA_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_FB_ACK_EXTRA_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_FB_ACK_EXTRA_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT 7:7 /* RWIVF */ +#define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_FB_RDATA_EXTRA 8:8 /* RWIVF */ +#define NV_PBUS_INTR_0_FB_RDATA_EXTRA_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_FB_RDATA_EXTRA_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_FB_RDATA_EXTRA_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_SW 26:26 /* RWIVF */ +#define NV_PBUS_INTR_0_SW_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_SW_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_SW_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */ +#define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_0_ACCESS_TIMEOUT 31:31 /* RWIVF */ +#define NV_PBUS_INTR_0_ACCESS_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PBUS_INTR_0_ACCESS_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PBUS_INTR_0_ACCESS_TIMEOUT_RESET 0x00000001 /* -W--C */ +#define NV_PBUS_INTR_EN_0 0x00001140 /* RW-4R */ +#define NV_PBUS_INTR_EN_0_PRI_SQUASH 1:1 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_PRI_SQUASH_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_PRI_SQUASH_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_PRI_FECSERR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_PRI_FECSERR_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT 4:4 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA 6:6 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT 7:7 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA 8:8 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_SW 26:26 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_SW_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_SW_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT 31:31 /* RWIVF */ +#define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1 0x00001144 /* RW-4R */ +#define NV_PBUS_INTR_EN_1_PRI_SQUASH 1:1 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_PRI_SQUASH_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_PRI_SQUASH_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_PRI_FECSERR 2:2 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_PRI_FECSERR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_PRI_FECSERR_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_PRI_TIMEOUT 3:3 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_PRI_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_PRI_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT 4:4 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT 5:5 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA 6:6 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT 7:7 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA 8:8 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_SW 26:26 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_SW_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_SW_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT 31:31 /* RWIVF */ +#define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_SW_INTR_0 0x00001150 /* -W-4R */ +#define NV_PBUS_SW_INTR_0_SET 0:0 /* -W-VF */ +#define NV_PBUS_SW_INTR_0_SET_PENDING 0x00000001 /* -W--V */ +#define NV_PBUS_SW_INTR_1 0x00001154 /* RW-4R */ +#define NV_PBUS_SW_INTR_1_SCRATCH 31:0 /* RWIVF */ +#define NV_PBUS_SW_INTR_1_SCRATCH_DATA 0x00000000 /* RWI-V */ +#define NV_PBUS_SW_INTR_2 0x00001158 /* RW-4R */ +#define NV_PBUS_SW_INTR_2_SCRATCH 31:0 /* RWIVF */ +#define NV_PBUS_SW_INTR_2_SCRATCH_DATA 0x00000000 /* RWI-V */ +#define NV_PBUS_SW_INTR_3 0x0000115C /* RW-4R */ +#define NV_PBUS_SW_INTR_3_SCRATCH 31:0 /* RWIVF */ +#define NV_PBUS_SW_INTR_3_SCRATCH_FLAG 0x00000000 /* RWI-V */ +#define NV_PBUS_SW_INTR_4 0x00001160 /* RW-4R */ +#define NV_PBUS_SW_INTR_4_SCRATCH 31:0 /* RWIVF */ +#define NV_PBUS_SW_INTR_4_SCRATCH_FLAG 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR0_WINDOW 0x00001700 /* RW-4R */ +#define NV_PBUS_BAR0_WINDOW_BASE 23:0 /* RWIUF */ +#define NV_PBUS_BAR0_WINDOW_BASE_0 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR0_WINDOW_TARGET 25:24 /* RWIUF */ +#define NV_PBUS_BAR0_WINDOW_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PBUS_BAR0_WINDOW_BASE_SHIFT 16 /* */ +#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */ +#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */ +#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */ +#define NV_PBUS_BIND_STATUS 0x00001710 /* R--4R */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */ +#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* */ +#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */ +#define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */ +#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */ +#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */ +#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */ +#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */ +#define NV_PBUS_EXT_CG 0x00001C00 /* RW-4R */ +#define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ +#define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ +#define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ +#define NV_PBUS_EXT_CG_IDLE_CG_EN 6:6 /* RWIVF */ +#define NV_PBUS_EXT_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_EXT_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_EXT_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ +#define NV_PBUS_EXT_CG_STALL_CG_EN 14:14 /* RWIVF */ +#define NV_PBUS_EXT_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_EXT_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_EXT_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */ +#define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */ +#define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1 0x00001C04 /* RW-4R */ +#define NV_PBUS_EXT_CG1_MONITOR_CG_EN 0:0 /* RWIVF */ +#define NV_PBUS_EXT_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PBUS_EXT_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PBUS_EXT_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG 9:1 /* */ +#define NV_PBUS_EXT_CG1_SLCG_ENABLED 0x00000000 /* */ +#define NV_PBUS_EXT_CG1_SLCG_DISABLED 0x000001ff /* */ +#define NV_PBUS_EXT_CG1_SLCG__PROD 0x00000000 /* */ +#define NV_PBUS_EXT_CG1_SLCG_BL 1:1 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_BL_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_BL_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_BL__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_C11 2:2 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_C11_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_C11_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_C11__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_MAP 3:3 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_MAP_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_MAP_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_MAP__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_PRI 4:4 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_PRI_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_PRI_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_PRI__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_UNROLL 5:5 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_UNROLL_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_UNROLL_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_UNROLL__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_ASMBL 6:6 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_ASMBL_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_ASMBL_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_ASMBL__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_ROLL 7:7 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_ROLL_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_ROLL_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_ROLL__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_IFR 8:8 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_IFR_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_IFR_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_IFR__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_PM 9:9 /* RWIVF */ +#define NV_PBUS_EXT_CG1_SLCG_PM_ENABLED 0x00000000 /* RW--V */ +#define NV_PBUS_EXT_CG1_SLCG_PM_DISABLED 0x00000001 /* RWI-V */ +#define NV_PBUS_EXT_CG1_SLCG_PM__PROD 0x00000000 /* RW--V */ +#define NV_PBUS_IFR_STATUS1 0x00001724 /* R--4R */ +#define NV_PBUS_IFR_STATUS1_BAR0ADDR 23:0 /* R-IVF */ +#define NV_PBUS_IFR_STATUS1_BAR0ADDR_INIT 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_STATUS1_IFF_DONE 27:27 /* R-IVF */ +#define NV_PBUS_IFR_STATUS1_IFF_DONE_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_STATUS1_IFF_DONE_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_STATUS1_IDLE 29:29 /* R-IVF */ +#define NV_PBUS_IFR_STATUS1_IDLE_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_STATUS1_IDLE_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_STATUS1_LASTEXEC 30:30 /* R-IVF */ +#define NV_PBUS_IFR_STATUS1_LASTEXEC_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_STATUS1_LASTEXEC_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_STATUS1_READINRMW 31:31 /* R-IVF */ +#define NV_PBUS_IFR_STATUS1_READINRMW_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_STATUS1_READINRMW_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR 0x00001728 /* R--4R */ +#define NV_PBUS_IFR_ERROR_BADSIG 0:0 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_BADSIG_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_BADSIG_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT 1:1 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_BADPARITY 8:8 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_BADPARITY_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_BADPARITY_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_BADROMLEN 12:12 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_BADROMLEN_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_BADROMLEN_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_BADCHECKSUM 16:16 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_BADCHECKSUM_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_BADCHECKSUM_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_BADFORMAT 20:20 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_BADFORMAT_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_BADFORMAT_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_PRI_ERROR 21:21 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_PRI_ERROR_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_PRI_ERROR_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT 23:23 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC 24:24 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_IFF_BADSPACEID 25:25 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_IFF_BADSPACEID_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_IFF_BADSPACEID_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN 26:26 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_IFF_BADCMDOP 27:27 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_IFF_BADCMDOP_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_IFF_BADCMDOP_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR 29:29 /* R-IVF */ +#define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR_TRUE 0x00000001 /* R---V */ +#define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR_FALSE 0x00000000 /* R-I-V */ +#define NV_PBUS_LVDS_USER 0x00001800 /* RW-4R */ +#define NV_PBUS_LVDS_USER_VALUE 3:0 /* RWIVF */ +#define NV_PBUS_LVDS_USER_VALUE_INIT 0x0000000F /* RWI-V */ diff --git a/Host-Fifo/volta/gv100/dev_fifo.ref.txt b/Host-Fifo/volta/gv100/dev_fifo.ref.txt new file mode 100644 index 0000000..dcb055e --- /dev/null +++ b/Host-Fifo/volta/gv100/dev_fifo.ref.txt @@ -0,0 +1,639 @@ +Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +#define NV_PFIFO_CFG0 0x00002004 /* R--4R */ +#define NV_PFIFO_CFG0_NUM_PBDMA 7:0 /* R-IUF */ +#define NV_PFIFO_CFG0_NUM_PBDMA_INIT 14 /* R-I-V */ +#define NV_PFIFO_CFG0_PBDMA_FAULT_ID 23:16 /* R-IUF */ +#define NV_PFIFO_CFG0_PBDMA_FAULT_ID_INIT 32 /* R-I-V */ +#define NV_PFIFO_CFG1 0x00002008 /* R--4R */ +#define NV_PFIFO_CFG1_NUM_CHANNELS 31:0 /* R-IUF */ +#define NV_PFIFO_CFG1_NUM_CHANNELS_INIT 4096 /* R-I-V */ +#define NV_PFIFO_CFG2 0x0000200c /* R--4R */ +#define NV_PFIFO_CFG2_HOST_CLASS_ID 15:0 /* R-IUF */ +#define NV_PFIFO_CFG2_HOST_CLASS_ID_VALUE 50031 /* R-I-V */ +#define NV_PFIFO_CONFIG 0x00002200 /* RW-4R */ +#define NV_PFIFO_CONFIG_L2_EVICT 9:8 /* RWIVF */ +#define NV_PFIFO_CONFIG_L2_EVICT_FIRST 0x00000000 /* RWI-V */ +#define NV_PFIFO_CONFIG_L2_EVICT_NORMAL 0x00000001 /* RW--V */ +#define NV_PFIFO_ACQ_PRETEST 0x00002250 /* RW-4R */ +#define NV_PFIFO_ACQ_PRETEST_TIMEOUT 7:0 /* RWIUF */ +#define NV_PFIFO_ACQ_PRETEST_TIMEOUT_8 0x00000008 /* RWI-V */ +#define NV_PFIFO_ACQ_PRETEST_TIMESCALE 15:12 /* RWIUF */ +#define NV_PFIFO_ACQ_PRETEST_TIMESCALE_0 0x00000000 /* RWI-V */ +#define NV_PFIFO_ACQ_PRETEST_TIMESCALE_10 0x0000000a /* RW--V */ +#define NV_PFIFO_USERD_WRITEBACK 0x0000225C /* RW-4R */ +#define NV_PFIFO_USERD_WRITEBACK_TIMER 7:0 /* RWIUF */ +#define NV_PFIFO_USERD_WRITEBACK_TIMER_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_USERD_WRITEBACK_TIMER_SHORT 0x00000003 /* RW--V */ +#define NV_PFIFO_USERD_WRITEBACK_TIMER_100US 0x00000064 /* RWI-V */ +#define NV_PFIFO_USERD_WRITEBACK_TIMESCALE 15:12 /* RWIUF */ +#define NV_PFIFO_USERD_WRITEBACK_TIMESCALE_0 0x00000000 /* RWI-V */ +#define NV_PFIFO_USERD_WRITEBACK_TIMESCALE_SHORT 0x00000000 /* */ +#define NV_PFIFO_USERD_WRITEBACK_TIMESCALE_100US 0x00000000 /* */ +#define NV_PCCSR_CHANNEL_INST(i) (0x00800000+(i)*8) /* RW-4A */ +#define NV_PCCSR_CHANNEL_INST__SIZE_1 4096 /* */ +#define NV_PCCSR_CHANNEL_INST_PTR 27:0 /* RWXUF */ +#define NV_PCCSR_CHANNEL_INST_TARGET 29:28 /* RWXVF */ +#define NV_PCCSR_CHANNEL_INST_TARGET_VID_MEM 0x00000000 /* RW--V */ +#define NV_PCCSR_CHANNEL_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PCCSR_CHANNEL_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PCCSR_CHANNEL_INST_BIND 31:31 /* RWIVF */ +#define NV_PCCSR_CHANNEL_INST_BIND_FALSE 0x00000000 /* RWI-V */ +#define NV_PCCSR_CHANNEL_INST_BIND_TRUE 0x00000001 /* RW--V */ +#define NV_PCCSR_CHANNEL_INST_PTR_ALIGN_SHIFT 12 /* */ +#define NV_PCCSR_CHANNEL(i) (0x00800004+(i)*8) /* RW-4A */ +#define NV_PCCSR_CHANNEL__SIZE_1 4096 /* */ +#define NV_PCCSR_CHANNEL_ENABLE 0:0 /* R-IVF */ +#define NV_PCCSR_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* R-I-V */ +#define NV_PCCSR_CHANNEL_ENABLE_IN_USE 0x00000001 /* R---V */ +#define NV_PCCSR_CHANNEL_NEXT 1:1 /* RWIVF */ +#define NV_PCCSR_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */ +#define NV_PCCSR_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */ +#define NV_PCCSR_CHANNEL_FORCE_CTX_RELOAD 8:8 /* -W-VF */ +#define NV_PCCSR_CHANNEL_FORCE_CTX_RELOAD_FALSE 0x00000000 /* -W--T */ +#define NV_PCCSR_CHANNEL_FORCE_CTX_RELOAD_TRUE 0x00000001 /* -W--T */ +#define NV_PCCSR_CHANNEL_ENABLE_SET 10:10 /* -W-VF */ +#define NV_PCCSR_CHANNEL_ENABLE_SET_TRUE 0x00000001 /* -W--T */ +#define NV_PCCSR_CHANNEL_ENABLE_SET_FALSE 0x00000000 /* -W--T */ +#define NV_PCCSR_CHANNEL_ENABLE_CLR 11:11 /* -W-VF */ +#define NV_PCCSR_CHANNEL_ENABLE_CLR_TRUE 0x00000001 /* -W--T */ +#define NV_PCCSR_CHANNEL_ENABLE_CLR_FALSE 0x00000000 /* -W--T */ +#define NV_PCCSR_CHANNEL_PBDMA_FAULTED 22:22 /* RWIVF */ +#define NV_PCCSR_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* R-I-V */ +#define NV_PCCSR_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* R---V */ +#define NV_PCCSR_CHANNEL_PBDMA_FAULTED_RESET 0x00000001 /* -W--T */ +#define NV_PCCSR_CHANNEL_ENG_FAULTED 23:23 /* RWIVF */ +#define NV_PCCSR_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* R-I-V */ +#define NV_PCCSR_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* R---V */ +#define NV_PCCSR_CHANNEL_ENG_FAULTED_RESET 0x00000001 /* -W--T */ +#define NV_PCCSR_CHANNEL_STATUS 27:24 /* R-IVF */ +#define NV_PCCSR_CHANNEL_STATUS_IDLE 0x00000000 /* R-I-V */ +#define NV_PCCSR_CHANNEL_STATUS_PENDING 0x00000001 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_PENDING_CTX_RELOAD 0x00000002 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_PENDING_ACQUIRE 0x00000003 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_PENDING_ACQ_CTX_RELOAD 0x00000004 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_PBDMA 0x00000005 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_PBDMA_AND_ENG 0x00000006 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_ENG 0x00000007 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_ENG_PENDING_ACQUIRE 0x00000008 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_ENG_PENDING 0x00000009 /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_PBDMA_CTX_RELOAD 0x0000000A /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_PBDMA_AND_ENG_CTX_RELOAD 0x0000000B /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_ENG_CTX_RELOAD 0x0000000C /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_ENG_PENDING_CTX_RELOAD 0x0000000D /* R---V */ +#define NV_PCCSR_CHANNEL_STATUS_ON_ENG_PENDING_ACQ_CTX_RELOAD 0x0000000E /* R---V */ +#define NV_PCCSR_CHANNEL_BUSY 28:28 /* R-IVF */ +#define NV_PCCSR_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */ +#define NV_PCCSR_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_RUNLIST_BASE 0x00002270 /* RW-4R */ +#define NV_PFIFO_RUNLIST_BASE_PTR 27:0 /* RWEUF */ +#define NV_PFIFO_RUNLIST_BASE_PTR_NULL 0x00000000 /* RWE-V */ +#define NV_PFIFO_RUNLIST_BASE_TARGET 29:28 /* RWEVF */ +#define NV_PFIFO_RUNLIST_BASE_TARGET_VID_MEM 0x00000000 /* RWE-V */ +#define NV_PFIFO_RUNLIST_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_PFIFO_RUNLIST_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ +#define NV_PFIFO_RUNLIST_BASE_PTR_ALIGN_SHIFT 12 /* */ +#define NV_PFIFO_RUNLIST 0x00002274 /* RW-4R */ +#define NV_PFIFO_RUNLIST_LENGTH 15:0 /* RWEUF */ +#define NV_PFIFO_RUNLIST_LENGTH_ZERO 0x00000000 /* RWE-V */ +#define NV_PFIFO_RUNLIST_LENGTH_MAX 0x0000ffff /* RW--V */ +#define NV_PFIFO_RUNLIST_ID 23:20 /* RWXUF */ +#define NV_PFIFO_ENG_RUNLIST_BASE(i) (0x00002280+(i)*8) /* R--4A */ +#define NV_PFIFO_ENG_RUNLIST_BASE__SIZE_1 13 /* */ +#define NV_PFIFO_ENG_RUNLIST_BASE_PTR 27:0 /* R-EUF */ +#define NV_PFIFO_ENG_RUNLIST_BASE_PTR_NULL 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENG_RUNLIST_BASE_TARGET 29:28 /* R-EVF */ +#define NV_PFIFO_ENG_RUNLIST_BASE_TARGET_VID_MEM 0x0 /* R-E-V */ +#define NV_PFIFO_ENG_RUNLIST_BASE_TARGET_SYS_MEM_COHERENT 0x2 /* R---V */ +#define NV_PFIFO_ENG_RUNLIST_BASE_TARGET_SYS_MEM_NONCOHERENT 0x3 /* R---V */ +#define NV_PFIFO_ENG_RUNLIST(i) (0x00002284+(i)*8) /* R--4A */ +#define NV_PFIFO_ENG_RUNLIST__SIZE_1 13 /* */ +#define NV_PFIFO_ENG_RUNLIST_LENGTH 15:0 /* R-EUF */ +#define NV_PFIFO_ENG_RUNLIST_LENGTH_ZERO 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENG_RUNLIST_LENGTH_MAX 0x0000ffff /* R---V */ +#define NV_PFIFO_ENG_RUNLIST_PENDING 20:20 /* R-EVF */ +#define NV_PFIFO_ENG_RUNLIST_PENDING_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENG_RUNLIST_PENDING_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_PBDMA_MAP(i) (0x00002390+(i)*4) /* R--4A */ +#define NV_PFIFO_PBDMA_MAP__SIZE_1 14 /* */ +#define NV_PFIFO_PBDMA_MAP_RUNLISTS 15:0 /* R-XVF */ +#define NV_PFIFO_LB_ENTRY_SIZE 128 /* */ +#define NV_PFIFO_LB_GPBUF_CONTROL(i) (0x000023E0+(i)*8) /* R--4A */ +#define NV_PFIFO_LB_GPBUF_CONTROL__SIZE_1 14 /* */ +#define NV_PFIFO_LB_GPBUF_CONTROL_SIZE 30:24 /* R-XUF */ +#define NV_PFIFO_LB_GPBUF_CONTROL_SIZE_128B 0x00000001 /* R-X-V */ +#define NV_PFIFO_LB_PBBUF_CONTROL(i) (0x000023E4+(i)*8) /* R--4A */ +#define NV_PFIFO_LB_PBBUF_CONTROL__SIZE_1 14 /* */ +#define NV_PFIFO_LB_PBBUF_CONTROL_SIZE 31:24 /* R-XUF */ +#define NV_PFIFO_LB_PBBUF_CONTROL_SIZE_128B 0x00000001 /* R-X-V */ +#define NV_PFIFO_INTR_0 0x00002100 /* RW-4R */ +#define NV_PFIFO_INTR_0_BIND_ERROR 0:0 /* RWEVF */ +#define NV_PFIFO_INTR_0_BIND_ERROR_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_0_BIND_ERROR_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_BIND_ERROR_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_0_SCHED_ERROR 8:8 /* RWEVF */ +#define NV_PFIFO_INTR_0_SCHED_ERROR_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_0_SCHED_ERROR_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_SCHED_ERROR_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_0_CHSW_ERROR 16:16 /* RWEVF */ +#define NV_PFIFO_INTR_0_CHSW_ERROR_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_0_CHSW_ERROR_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_CHSW_ERROR_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_0_MEMOP_TIMEOUT 23:23 /* RWIVF */ +#define NV_PFIFO_INTR_0_MEMOP_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */ +#define NV_PFIFO_INTR_0_MEMOP_TIMEOUT_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_MEMOP_TIMEOUT_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_0_LB_ERROR 24:24 /* RWEVF */ +#define NV_PFIFO_INTR_0_LB_ERROR_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_0_LB_ERROR_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_LB_ERROR_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_0_PBDMA_INTR 29:29 /* R-XVF */ +#define NV_PFIFO_INTR_0_PBDMA_INTR_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PFIFO_INTR_0_PBDMA_INTR_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_RUNLIST_EVENT 30:30 /* R-EVF */ +#define NV_PFIFO_INTR_0_RUNLIST_EVENT_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_0_RUNLIST_EVENT_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_CHANNEL_INTR 31:31 /* RWEVF */ +#define NV_PFIFO_INTR_0_CHANNEL_INTR_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_0_CHANNEL_INTR_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_0_CHANNEL_INTR_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_EN_0 0x00002140 /* RW-4R */ +#define NV_PFIFO_INTR_EN_0_BIND_ERROR 0:0 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_BIND_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_BIND_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR 8:8 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_SCHED_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_CHSW_ERROR 16:16 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_CHSW_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_CHSW_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_MEMOP_TIMEOUT 23:23 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_MEMOP_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_MEMOP_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_LB_ERROR 24:24 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_LB_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_LB_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_PBDMA_INTR 29:29 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_PBDMA_INTR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_PBDMA_INTR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_RUNLIST_EVENT 30:30 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_RUNLIST_EVENT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_RUNLIST_EVENT_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_0_CHANNEL_INTR 31:31 /* RWIVF */ +#define NV_PFIFO_INTR_EN_0_CHANNEL_INTR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_0_CHANNEL_INTR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_1 0x00002528 /* RW-4R */ +#define NV_PFIFO_INTR_EN_1_BIND_ERROR 0:0 /* RWIVF */ +#define NV_PFIFO_INTR_EN_1_BIND_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_1_BIND_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_1_SCHED_ERROR 8:8 /* RWIVF */ +#define NV_PFIFO_INTR_EN_1_SCHED_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_1_SCHED_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_1_CHSW_ERROR 16:16 /* RWIVF */ +#define NV_PFIFO_INTR_EN_1_CHSW_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_1_CHSW_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_1_MEMOP_TIMEOUT 23:23 /* RWIVF */ +#define NV_PFIFO_INTR_EN_1_MEMOP_TIMEOUT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_1_MEMOP_TIMEOUT_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_1_LB_ERROR 24:24 /* RWIVF */ +#define NV_PFIFO_INTR_EN_1_LB_ERROR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_1_LB_ERROR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_1_PBDMA_INTR 29:29 /* RWIVF */ +#define NV_PFIFO_INTR_EN_1_PBDMA_INTR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_1_PBDMA_INTR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_1_RUNLIST_EVENT 30:30 /* RWIVF */ +#define NV_PFIFO_INTR_EN_1_RUNLIST_EVENT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_1_RUNLIST_EVENT_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_EN_1_CHANNEL_INTR 31:31 /* RWIVF */ +#define NV_PFIFO_INTR_EN_1_CHANNEL_INTR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_EN_1_CHANNEL_INTR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_STALL 0x00002530 /* RW-4R */ +#define NV_PFIFO_INTR_STALL_BIND_ERROR 0:0 /* RWIVF */ +#define NV_PFIFO_INTR_STALL_BIND_ERROR_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_INTR_STALL_BIND_ERROR_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_INTR_STALL_SCHED_ERROR 8:8 /* RWIVF */ +#define NV_PFIFO_INTR_STALL_SCHED_ERROR_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_INTR_STALL_SCHED_ERROR_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_INTR_STALL_CHSW_ERROR 16:16 /* RWIVF */ +#define NV_PFIFO_INTR_STALL_CHSW_ERROR_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_INTR_STALL_CHSW_ERROR_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_INTR_STALL_MEMOP_TIMEOUT 23:23 /* RWIVF */ +#define NV_PFIFO_INTR_STALL_MEMOP_TIMEOUT_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_INTR_STALL_MEMOP_TIMEOUT_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_INTR_STALL_LB_ERROR 24:24 /* RWIVF */ +#define NV_PFIFO_INTR_STALL_LB_ERROR_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_INTR_STALL_LB_ERROR_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_INTR_STALL_PBDMA_INTR 29:29 /* RWIVF */ +#define NV_PFIFO_INTR_STALL_PBDMA_INTR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_STALL_PBDMA_INTR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_STALL_RUNLIST_EVENT 30:30 /* RWIVF */ +#define NV_PFIFO_INTR_STALL_RUNLIST_EVENT_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_STALL_RUNLIST_EVENT_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_STALL_CHANNEL_INTR 31:31 /* RWIVF */ +#define NV_PFIFO_INTR_STALL_CHANNEL_INTR_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_INTR_STALL_CHANNEL_INTR_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_INTR_BIND_ERROR 0x0000252C /* R--4R */ +#define NV_PFIFO_INTR_BIND_ERROR_CODE 7:0 /* R-EVF */ +#define NV_PFIFO_INTR_BIND_ERROR_CODE_NO_ERROR 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_BIND_ERROR_CODE_BIND_NOT_UNBOUND 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_BIND_ERROR_CODE_UNBIND_WHILE_RUNNING 0x00000003 /* R---V */ +#define NV_PFIFO_INTR_BIND_ERROR_CODE_INVALID_CTX_TGT 0x00000006 /* R---V */ +#define NV_PFIFO_INTR_BIND_ERROR_CODE_UNBIND_WHILE_PARKED 0x0000000B /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR 0x0000254C /* R--4R */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE 7:0 /* R-EVF */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_NO_ERROR 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_ENGINE_RESET 0x00000005 /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_RL_REQ_TIMEOUT 0x0000000c /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_RL_ACK_TIMEOUT 0x00000006 /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_RL_ACK_EXTRA 0x00000007 /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_RL_RDAT_TIMEOUT 0x00000008 /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_RL_RDAT_EXTRA 0x00000009 /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CTXSW_TIMEOUT 0x0000000a /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_NEW_RUNLIST 0x0000000d /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_CONFIG_WHILE_BUSY 0x0000000e /* R---V */ +#define NV_PFIFO_INTR_SCHED_ERROR_CODE_BAD_TSG 0x00000020 /* R---V */ +#define NV_PFIFO_INTR_CHSW_ERROR 0x0000256C /* R--4R */ +#define NV_PFIFO_INTR_CHSW_ERROR_CODE 7:0 /* R-EVF */ +#define NV_PFIFO_INTR_CHSW_ERROR_CODE_NO_ERROR 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_CHSW_ERROR_CODE_REQ_TIMEOUT 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_CHSW_ERROR_CODE_ACK_TIMEOUT 0x00000002 /* R---V */ +#define NV_PFIFO_INTR_CHSW_ERROR_CODE_ACK_EXTRA 0x00000003 /* R---V */ +#define NV_PFIFO_INTR_CHSW_ERROR_CODE_RDAT_TIMEOUT 0x00000004 /* R---V */ +#define NV_PFIFO_INTR_CHSW_ERROR_CODE_RDAT_EXTRA 0x00000005 /* R---V */ +#define NV_PFIFO_INTR_LB_ERROR 0x0000258C /* R--4R */ +#define NV_PFIFO_INTR_LB_ERROR_CODE 7:0 /* R-EVF */ +#define NV_PFIFO_INTR_LB_ERROR_CODE_NO_ERROR 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_LB_ERROR_CODE_REQ_TIMEOUT 0x00000002 /* R---V */ +#define NV_PFIFO_INTR_LB_ERROR_CODE_ACK_TIMEOUT 0x00000003 /* R---V */ +#define NV_PFIFO_INTR_LB_ERROR_CODE_ACK_EXTRA 0x00000004 /* R---V */ +#define NV_PFIFO_INTR_LB_ERROR_CODE_RDAT_TIMEOUT 0x00000005 /* R---V */ +#define NV_PFIFO_INTR_LB_ERROR_CODE_RDAT_EXTRA 0x00000006 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID 0x000025A0 /* R--4R */ +#define NV_PFIFO_INTR_PBDMA_ID_0 0:0 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_0_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_0_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_1 1:1 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_1_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_1_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_2 2:2 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_2_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_2_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_3 3:3 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_3_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_3_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_4 4:4 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_4_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_4_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_5 5:5 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_5_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_5_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_6 6:6 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_6_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_6_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_7 7:7 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_7_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_7_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_8 8:8 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_8_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_8_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_9 9:9 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_9_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_9_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_10 10:10 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_10_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_10_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_11 11:11 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_11_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_11_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_12 12:12 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_12_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_12_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_13 13:13 /* R-EVF */ +#define NV_PFIFO_INTR_PBDMA_ID_13_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_PBDMA_ID_13_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_PBDMA_ID_STATUS(i) (i):(i) /* */ +#define NV_PFIFO_INTR_PBDMA_ID_STATUS__SIZE_1 14 /* */ +#define NV_PFIFO_INTR_PBDMA_ID_STATUS_NOT_PENDING 0x00000000 /* */ +#define NV_PFIFO_INTR_PBDMA_ID_STATUS_PENDING 0x00000001 /* */ +#define NV_PFIFO_INTR_RUNLIST 0x00002A00 /* RW-4R */ +#define NV_PFIFO_INTR_RUNLIST_EVENT(i) (i):(i) /* */ +#define NV_PFIFO_INTR_RUNLIST_EVENT__SIZE_1 32 /* */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_NOT_PENDING 0x00000000 /* */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_PENDING 0x00000001 /* */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_RESET 0x00000001 /* */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_0 0:0 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_0_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_0_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_0_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_1 1:1 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_1_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_1_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_1_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_2 2:2 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_2_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_2_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_2_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_3 3:3 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_3_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_3_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_3_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_4 4:4 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_4_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_4_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_4_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_5 5:5 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_5_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_5_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_5_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_6 6:6 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_6_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_6_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_6_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_7 7:7 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_7_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_7_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_7_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_8 8:8 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_8_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_8_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_8_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_9 9:9 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_9_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_9_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_9_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_10 10:10 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_10_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_10_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_10_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_11 11:11 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_11_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_11_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_11_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_12 12:12 /* RWEVF */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_12_NOT_PENDING 0x00000000 /* R-E-V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_12_PENDING 0x00000001 /* R---V */ +#define NV_PFIFO_INTR_RUNLIST_EVENT_12_RESET 0x00000001 /* -W--T */ +#define NV_PFIFO_ENG_TIMEOUT 0x00002A0C /* RW-4R */ +#define NV_PFIFO_ENG_TIMEOUT_PERIOD 30:0 /* RWIVF */ +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_INIT 0x003fffff /* RWI-V */ +#define NV_PFIFO_ENG_TIMEOUT_PERIOD_MAX 0x7fffffff /* RW--V */ +#define NV_PFIFO_ENG_TIMEOUT_DETECTION 31:31 /* RWIVF */ +#define NV_PFIFO_ENG_TIMEOUT_DETECTION_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_ENG_TIMEOUT_DETECTION_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_CLEAR_FAULTED_TIMEOUT 0x00002A14 /* RW-4R */ +#define NV_PFIFO_CLEAR_FAULTED_TIMEOUT_PERIOD 29:0 /* RWIVF */ +#define NV_PFIFO_CLEAR_FAULTED_TIMEOUT_PERIOD_INIT 0x000003ff /* RWI-V */ +#define NV_PFIFO_CLEAR_FAULTED_TIMEOUT_PERIOD_MAX 0x3fffffff /* RW--V */ +#define NV_PFIFO_CLEAR_FAULTED_TIMEOUT_DETECTION 31:31 /* RWIVF */ +#define NV_PFIFO_CLEAR_FAULTED_TIMEOUT_DETECTION_DISABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_CLEAR_FAULTED_TIMEOUT_DETECTION_ENABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG 0x000026E0 /* RW-4R */ +#define NV_PFIFO_BLKCG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */ +#define NV_PFIFO_BLKCG_IDLE_CG_DLY_CNT_INIT 0x00000000 /* RWI-V */ +#define NV_PFIFO_BLKCG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ +#define NV_PFIFO_BLKCG_IDLE_CG_EN 6:6 /* RWIVF */ +#define NV_PFIFO_BLKCG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_BLKCG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_BLKCG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ +#define NV_PFIFO_BLKCG_STALL_CG_EN 14:14 /* RWIVF */ +#define NV_PFIFO_BLKCG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_BLKCG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_BLKCG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ +#define NV_PFIFO_BLKCG_WAKEUP_DLY_CNT 19:16 /* RWIVF */ +#define NV_PFIFO_BLKCG_WAKEUP_DLY_CNT_INIT 0x00000000 /* RWI-V */ +#define NV_PFIFO_BLKCG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1 0x000026EC /* RW-4R */ +#define NV_PFIFO_BLKCG1_MONITOR_CG_EN 0:0 /* RWIVF */ +#define NV_PFIFO_BLKCG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_BLKCG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG 16:1 /* */ +#define NV_PFIFO_BLKCG1_SLCG_ENABLED 0x00000000 /* */ +#define NV_PFIFO_BLKCG1_SLCG_DISABLED 0x0000FFFF /* */ +#define NV_PFIFO_BLKCG1_SLCG__PROD 0x00000000 /* */ +#define NV_PFIFO_BLKCG1_SLCG_RLP 1:1 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_RLP_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_RLP_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_RLP__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_CPUQ_RSP 2:2 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_CPUQ_RSP_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_CPUQ_RSP_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_CPUQ_RSP__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_EVH 3:3 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_EVH_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_EVH_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_EVH__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PMC 4:4 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_PMC_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PMC_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_PMC__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_FECS_PRIV 5:5 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_FECS_PRIV_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_FECS_PRIV_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_FECS_PRIV__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PRIV_RING 6:6 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_PRIV_RING_ENABLED 0x00000000 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_PRIV_RING_DISABLED 0x00000001 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PRIV_RING__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_EISM 7:7 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_EISM_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_EISM_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_EISM__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_LB 8:8 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_LB_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_LB_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_LB__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_CTL 9:9 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_CTL_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_CTL_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_CTL__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_GP 10:10 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_GP_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_GP_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_GP__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_PB 11:11 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_PB_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_PB_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_PBDMA_PB__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_TMR 12:12 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_TMR_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_TMR_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_TMR__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PRI 13:13 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_PRI_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_PRI_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_PRI__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_CHSW 14:14 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_CHSW_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_CHSW_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_CHSW__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_XBAR 15:15 /* RWIVF */ +#define NV_PFIFO_BLKCG1_SLCG_XBAR_ENABLED 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_XBAR_DISABLED 0x00000001 /* RWI-V */ +#define NV_PFIFO_BLKCG1_SLCG_XBAR__PROD 0x00000000 /* RW--V */ +#define NV_PFIFO_BLKCG1_SLCG_UNUSED 16:16 /* */ +#define NV_PFIFO_BLKCG1_SLCG_UNUSED_ENABLED 0x00000000 /* */ +#define NV_PFIFO_BLKCG1_SLCG_UNUSED_DISABLED 0x00000001 /* */ +#define NV_PFIFO_BLKCG1_SLCG_UNUSED__PROD 0x00000000 /* */ +#define NV_PFIFO_SCHED_DISABLE 0x00002630 /* RW-4R */ +#define NV_PFIFO_SCHED_DISABLE_RUNLIST(i) (i):(i) /* */ +#define NV_PFIFO_SCHED_DISABLE_RUNLIST__SIZE_1 13 /* */ +#define NV_PFIFO_SCHED_DISABLE_FALSE 0x00000000 /* */ +#define NV_PFIFO_SCHED_DISABLE_TRUE 0x00000001 /* */ +#define NV_PFIFO_SCHED_DISABLE_RUNLIST_MASK 12:0 /* RWEVF */ +#define NV_PFIFO_SCHED_DISABLE_RUNLIST_MASK_INIT 0 /* RWE-V */ +#define NV_PFIFO_PREEMPT 0x00002634 /* RW-4R */ +#define NV_PFIFO_PREEMPT_ID 11:0 /* */ +#define NV_PFIFO_PREEMPT_ID_NULL 0x00000000 /* */ +#define NV_PFIFO_PREEMPT_ID_HW 11:0 /* RWEUF */ +#define NV_PFIFO_PREEMPT_ID_HW_NULL 0x00000000 /* RWE-V */ +#define NV_PFIFO_PREEMPT_PENDING 20:20 /* R-EVF */ +#define NV_PFIFO_PREEMPT_PENDING_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_PREEMPT_TYPE 25:24 /* RWEVF */ +#define NV_PFIFO_PREEMPT_TYPE_CHANNEL 0x00000000 /* RWE-V */ +#define NV_PFIFO_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */ +#define NV_PFIFO_RUNLIST_PREEMPT 0x00002638 /* RW-4R */ +#define NV_PFIFO_RUNLIST_PREEMPT_RUNLIST(i) (i):(i) /* */ +#define NV_PFIFO_RUNLIST_PREEMPT_RUNLIST__SIZE_1 32 /* */ +#define NV_PFIFO_RUNLIST_PREEMPT_PENDING 0x00000001 /* */ +#define NV_PFIFO_RUNLIST_PREEMPT_DONE 0x00000000 /* */ +#define NV_PFIFO_RUNLIST_PREEMPT_RUNLISTS 13-1:0 /* RWEUF */ +#define NV_PFIFO_RUNLIST_PREEMPT_RUNLISTS_INIT 0x00000000 /* RWE-V */ +#define NV_PFIFO_SCHED_STATUS 0x0000263C /* R--4R */ +#define NV_PFIFO_SCHED_STATUS_CHSW 1:1 /* R-EVF */ +#define NV_PFIFO_SCHED_STATUS_CHSW_NOT_IN_PROGRESS 0x00000000 /* R-E-V */ +#define NV_PFIFO_SCHED_STATUS_CHSW_IN_PROGRESS 0x00000001 /* R---V */ +#define NV_PFIFO_SCHED_STATUS_RUNLIST_FETCH 2:2 /* R-EVF */ +#define NV_PFIFO_SCHED_STATUS_RUNLIST_FETCH_IDLE 0x00000000 /* R-E-V */ +#define NV_PFIFO_SCHED_STATUS_RUNLIST_FETCH_BUSY 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS(i) (0x00002640+(i)*8) /* R--4A */ +#define NV_PFIFO_ENGINE_STATUS__SIZE_1 15 /* */ +#define NV_PFIFO_ENGINE_STATUS_ID 11:0 /* */ +#define NV_PFIFO_ENGINE_STATUS_ID_ZERO 0x00000000 /* */ +#define NV_PFIFO_ENGINE_STATUS_ID_HW 11:0 /* R-XUF */ +#define NV_PFIFO_ENGINE_STATUS_ID_HW_ZERO 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE 12:12 /* R-XVF */ +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_CHID 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_ID_TYPE_TSGID 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS 15:13 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_INVALID 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_VALID 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_LOAD 0x00000005 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SAVE 0x00000006 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_CTX_STATUS_CTXSW_SWITCH 0x00000007 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID 27:16 /* */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_ZERO 0x00000000 /* */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_HW 27:16 /* R-XUF */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_HW_ZERO 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE 28:28 /* R-XVF */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_CHID 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_ID_TYPE_TSGID 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_ENG_RELOAD 29:29 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_ENG_RELOAD_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_ENG_RELOAD_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_FAULTED 30:30 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_FAULTED_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_FAULTED_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_ENGINE 31:31 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_ENGINE_IDLE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_ENGINE_BUSY 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_CTXSW 15:15 /* */ +#define NV_PFIFO_ENGINE_STATUS_CTXSW_NOT_IN_PROGRESS 0x00000000 /* */ +#define NV_PFIFO_ENGINE_STATUS_CTXSW_IN_PROGRESS 0x00000001 /* */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG(i) (0x00002644+(i)*8) /* R--4A */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG__SIZE_1 15 /* */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_IF_EN 0:0 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_IF_EN_DISABLED 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_IF_EN_ENABLED 0x00000001 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_INTR 4:4 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_INTR_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_INTR_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS 8:8 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE0_WFI 12:12 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE0_WFI_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE0_WFI_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS 16:16 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE1_WFI 20:20 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE1_WFI_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_DEBUG_PIPE1_WFI_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_INST(i) (0x00003100+(i)*4) /* R--4A */ +#define NV_PFIFO_ENGINE_STATUS_INST__SIZE_1 15 /* */ +#define NV_PFIFO_ENGINE_STATUS_INST_PTR 27:0 /* R-XUF */ +#define NV_PFIFO_ENGINE_STATUS_INST_PTR_ZERO 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_INST_TARGET 29:28 /* R-XUF */ +#define NV_PFIFO_ENGINE_STATUS_INST_TARGET_VID_MEM 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_INST_VALID 31:31 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_INST_VALID_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_INST_VALID_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST(i) (0x00003000+(i)*4) /* R--4A */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST__SIZE_1 15 /* */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_PTR 27:0 /* R-XUF */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_PTR_ZERO 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_TARGET 29:28 /* R-XUF */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_TARGET_VID_MEM 0x00000000 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_VALID 31:31 /* R-EVF */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_VALID_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_ENGINE_STATUS_NEXT_INST_VALID_TRUE 0x00000001 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS(i) (0x00003080+(i)*4) /* R--4A */ +#define NV_PFIFO_PBDMA_STATUS__SIZE_1 14 /* */ +#define NV_PFIFO_PBDMA_STATUS_ID 11:0 /* */ +#define NV_PFIFO_PBDMA_STATUS_ID_ZERO 0x00000000 /* */ +#define NV_PFIFO_PBDMA_STATUS_ID_HW 11:0 /* R-XUF */ +#define NV_PFIFO_PBDMA_STATUS_ID_HW_ZERO 0x00000000 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE 12:12 /* R-XVF */ +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_CHID 0x00000000 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_ID_TYPE_TSGID 0x00000001 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS 15:13 /* R-EVF */ +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_INVALID 0x00000000 /* R-E-V */ +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_VALID 0x00000001 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_LOAD 0x00000005 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SAVE 0x00000006 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_CHAN_STATUS_CHSW_SWITCH 0x00000007 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID 27:16 /* */ +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_ZERO 0x00000000 /* */ +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_HW 27:16 /* R-XUF */ +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_HW_ZERO 0x00000000 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE 28:28 /* R-XVF */ +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_CHID 0x00000000 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_NEXT_ID_TYPE_TSGID 0x00000001 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_CHSW 15:15 /* */ +#define NV_PFIFO_PBDMA_STATUS_CHSW_NOT_IN_PROGRESS 0x00000000 /* */ +#define NV_PFIFO_PBDMA_STATUS_CHSW_IN_PROGRESS 0x00000001 /* */ +#define NV_PFIFO_PBDMA_STATUS_INST(i) (0x00002790+(i)*4) /* R--4A */ +#define NV_PFIFO_PBDMA_STATUS_INST__SIZE_1 14 /* */ +#define NV_PFIFO_PBDMA_STATUS_INST_PTR 27:0 /* R-XUF */ +#define NV_PFIFO_PBDMA_STATUS_INST_PTR_ZERO 0x00000000 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_INST_TARGET 29:28 /* R-XUF */ +#define NV_PFIFO_PBDMA_STATUS_INST_TARGET_VID_MEM 0x00000000 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */ +#define NV_PFIFO_PBDMA_STATUS_INST_VALID 31:31 /* R-EVF */ +#define NV_PFIFO_PBDMA_STATUS_INST_VALID_FALSE 0x00000000 /* R-E-V */ +#define NV_PFIFO_PBDMA_STATUS_INST_VALID_TRUE 0x00000001 /* R---V */ diff --git a/Host-Fifo/volta/gv100/dev_master.ref.txt b/Host-Fifo/volta/gv100/dev_master.ref.txt new file mode 100644 index 0000000..8ae6133 --- /dev/null +++ b/Host-Fifo/volta/gv100/dev_master.ref.txt @@ -0,0 +1,363 @@ +Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +#define NV_PMC_BOOT_0 0x00000000 /* R--4R */ +#define NV_PMC_BOOT_0_ID 31:0 /* */ +#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */ +#define NV_PMC_BOOT_0_MINOR_REVISION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_10 0x0000000A /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_11 0x0000000B /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_12 0x0000000C /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_13 0x0000000D /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_14 0x0000000E /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_15 0x0000000F /* R---V */ +#define NV_PMC_BOOT_0_MINOR_REVISION_INIT 0x00000001 /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_0_MAJOR_REVISION_INIT 0x00000000 /* R---V */ +#define NV_PMC_BOOT_0_RESERVED_0 11:8 /* */ +#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 /* R--VF */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_0 0x00000000 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_0_IMPLEMENTATION_INIT 0x00000000 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GF100 0x0000000C /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GF110 0x0000000D /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GK100 0x0000000E /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GK110 0x0000000F /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GK200 0x00000010 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GM000 0x00000011 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GM100 0x00000011 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GM200 0x00000012 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GP100 0x00000013 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GV100 0x00000014 /* R---V */ +#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 0x00000015 /* R---V */ +#define NV_PMC_BOOT_1 0x00000004 /* RW-4R */ +#define NV_PMC_BOOT_1_VGPU8 8:8 /* R--VF */ +#define NV_PMC_BOOT_1_VGPU8_REAL 0x00000000 /* R---V */ +#define NV_PMC_BOOT_1_VGPU8_VIRTUAL 0x00000001 /* R---V */ +#define NV_PMC_BOOT_1_VGPU16 16:16 /* R--VF */ +#define NV_PMC_BOOT_1_VGPU16_REAL 0x00000000 /* R---V */ +#define NV_PMC_BOOT_1_VGPU16_VIRTUAL 0x00000001 /* R---V */ +#define NV_PMC_BOOT_2 0x00000008 /* R--4R */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION 3:0 /* R-XVF */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_2_FAB_ID 7:4 /* R-XVF */ +#define NV_PMC_BOOT_2_FAB_ID_0 0x00000000 /* R---V */ +#define NV_PMC_BOOT_2_FAB_ID_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_2_FAB_ID_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_2_FAB_ID_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */ +#define NV_PMC_BOOT_42_MINOR_REVISION_1 0x00000001 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_2 0x00000002 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_3 0x00000003 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_4 0x00000004 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_5 0x00000005 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_6 0x00000006 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_7 0x00000007 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_8 0x00000008 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_9 0x00000009 /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_10 0x0000000A /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_11 0x0000000B /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_12 0x0000000C /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_13 0x0000000D /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_14 0x0000000E /* R---V */ +#define NV_PMC_BOOT_42_MINOR_REVISION_15 0x0000000F /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_A 0x0000000A /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_B 0x0000000B /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_C 0x0000000C /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_D 0x0000000D /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_E 0x0000000E /* R---V */ +#define NV_PMC_BOOT_42_MAJOR_REVISION_F 0x0000000F /* R---V */ +#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_0 0x00000000 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_1 0x00000001 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_2 0x00000002 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_3 0x00000003 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_4 0x00000004 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_5 0x00000005 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_6 0x00000006 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_7 0x00000007 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_8 0x00000008 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_9 0x00000009 /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_A 0x0000000A /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_B 0x0000000B /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_C 0x0000000C /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_D 0x0000000D /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_E 0x0000000E /* */ +#define NV_PMC_BOOT_42_IMPLEMENTATION_F 0x0000000F /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_GP100 0x00000013 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_GV100 0x00000014 /* */ +#define NV_PMC_BOOT_42_ARCHITECTURE_GV110 0x00000015 /* */ +#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */ +#define NV_PMC_BOOT_42_CHIP_ID_GP000 0x00000131 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP100 0x00000130 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP102 0x00000132 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP104 0x00000134 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP104V 0x00000139 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP106 0x00000136 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP107 0x00000137 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP108 0x00000138 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GP108V 0x0000013A /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GV100 0x00000140 /* R---V */ +#define NV_PMC_BOOT_42_CHIP_ID_GV10B 0x0000014B /* R---V */ +#define NV_PMC_INTR(i) (0x00000100+(i)*4) /* R--4A */ +#define NV_PMC_INTR__SIZE_1 4 /* */ +#define NV_PMC_INTR_DEVICE(i) (i):(i) /* */ +#define NV_PMC_INTR_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_INTR_DEVICE_NOT_PENDING 0x00000000 /* */ +#define NV_PMC_INTR_DEVICE_PENDING 0x00000001 /* */ +#define NV_PMC_INTR_PFIFO 8:8 /* R--VF */ +#define NV_PMC_INTR_PFIFO_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PFIFO_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_HUB 9:9 /* R--VF */ +#define NV_PMC_INTR_HUB_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_HUB_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PFB 13:13 /* R--VF */ +#define NV_PMC_INTR_PFB_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PFB_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_THERMAL 18:18 /* R--VF */ +#define NV_PMC_INTR_THERMAL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_THERMAL_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_HDACODEC 19:19 /* R--VF */ +#define NV_PMC_INTR_HDACODEC_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_HDACODEC_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PTIMER 20:20 /* R--VF */ +#define NV_PMC_INTR_PTIMER_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PTIMER_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PMGR 21:21 /* R--VF */ +#define NV_PMC_INTR_PMGR_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PMGR_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_DFD 23:23 /* R--VF */ +#define NV_PMC_INTR_DFD_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_DFD_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PMU 24:24 /* R--VF */ +#define NV_PMC_INTR_PMU_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PMU_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_LTC_ALL 25:25 /* R--VF */ +#define NV_PMC_INTR_LTC_ALL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_LTC_ALL_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PDISP 26:26 /* R--VF */ +#define NV_PMC_INTR_PDISP_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PDISP_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PBUS 28:28 /* R--VF */ +#define NV_PMC_INTR_PBUS_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PBUS_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_XVE 29:29 /* R--VF */ +#define NV_PMC_INTR_XVE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_XVE_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_PRIV_RING 30:30 /* R--VF */ +#define NV_PMC_INTR_PRIV_RING_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_PRIV_RING_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_SOFTWARE 31:31 /* R--VF */ +#define NV_PMC_INTR_SOFTWARE_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_SOFTWARE_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_MODE(i) (0x00000120+(i)*4) /* R--4A */ +#define NV_PMC_INTR_MODE__SIZE_1 4 /* */ +#define NV_PMC_INTR_MODE_BIT(i) (i):(i) /* */ +#define NV_PMC_INTR_MODE_BIT__SIZE_1 32 /* */ +#define NV_PMC_INTR_MODE_BIT_LEVEL 0x00000000 /* */ +#define NV_PMC_INTR_MODE_BIT_EDGE 0x00000001 /* */ +#define NV_PMC_INTR_MODE_VALUE 31:0 /* C--VF */ +#define NV_PMC_INTR_MODE_VALUE_INIT 0x00000000 /* C---V */ +#define NV_PMC_INTR_EN(i) (0x00000140+(i)*4) /* R--4A */ +#define NV_PMC_INTR_EN__SIZE_1 4 /* */ +#define NV_PMC_INTR_EN_DEVICE(i) (i):(i) /* */ +#define NV_PMC_INTR_EN_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_INTR_EN_DEVICE_DISABLED 0x00000000 /* */ +#define NV_PMC_INTR_EN_DEVICE_ENABLED 0x00000001 /* */ +#define NV_PMC_INTR_EN_VALUE 31:0 /* R-IVF */ +#define NV_PMC_INTR_EN_VALUE_INIT 0x00000000 /* R-I-V */ +#define NV_PMC_INTR_EN_SET(i) (0x00000160+(i)*4) /* -W-4A */ +#define NV_PMC_INTR_EN_SET__SIZE_1 4 /* */ +#define NV_PMC_INTR_EN_SET_DEVICE(i) (i):(i) /* */ +#define NV_PMC_INTR_EN_SET_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_INTR_EN_SET_DEVICE_SET 0x00000001 /* */ +#define NV_PMC_INTR_EN_SET_VALUE 31:0 /* -W-VF */ +#define NV_PMC_INTR_EN_CLEAR(i) (0x00000180+(i)*4) /* -W-4A */ +#define NV_PMC_INTR_EN_CLEAR__SIZE_1 4 /* */ +#define NV_PMC_INTR_EN_CLEAR_DEVICE(i) (i):(i) /* */ +#define NV_PMC_INTR_EN_CLEAR_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_INTR_EN_CLEAR_DEVICE_SET 0x00000001 /* */ +#define NV_PMC_INTR_EN_CLEAR_VALUE 31:0 /* -W-VF */ +#define NV_PMC_INTR_SW(i) (0x000001A0+(i)*4) /* RW-4A */ +#define NV_PMC_INTR_SW__SIZE_1 4 /* */ +#define NV_PMC_INTR_SW_ASSERT 0:0 /* RWIVF */ +#define NV_PMC_INTR_SW_ASSERT_TRUE 0x00000001 /* RW--V */ +#define NV_PMC_INTR_SW_ASSERT_FALSE 0x00000000 /* RWI-V */ +#define NV_PMC_INTR_LTC 0x000001C0 /* R--4R */ +#define NV_PMC_INTR_LTC_PART_MASK 16:0 /* R--VF */ +#define NV_PMC_INTR_LTC_PART_MASK_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_LTC_PART_MASK_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_LTC_PART(i) (i):(i) /* */ +#define NV_PMC_INTR_LTC_PART__SIZE_1 16 /* */ +#define NV_PMC_INTR_LTC_PART_NOT_PENDING 0x00000000 /* */ +#define NV_PMC_INTR_LTC_PART_PENDING 0x00000001 /* */ +#define NV_PMC_INTR_FBPA 0x000001D0 /* R--4R */ +#define NV_PMC_INTR_FBPA_PART_MASK 16:0 /* R--VF */ +#define NV_PMC_INTR_FBPA_PART_MASK_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_FBPA_PART_MASK_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL 30:30 /* R--VF */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL 31:31 /* R--VF */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL_PENDING 0x00000001 /* R---V */ +#define NV_PMC_INTR_FBPA_PART(i) (i):(i) /* */ +#define NV_PMC_INTR_FBPA_PART__SIZE_1 16 /* */ +#define NV_PMC_INTR_FBPA_PART_NOT_PENDING 0x00000000 /* */ +#define NV_PMC_INTR_FBPA_PART_PENDING 0x00000001 /* */ +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ +#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */ +#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */ +#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */ +#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */ +#define NV_PMC_ENABLE_PRIV_RING 5:5 /* RWIVF */ +#define NV_PMC_ENABLE_PRIV_RING_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PRIV_RING_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PFIFO_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PFIFO_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_HOST_SCHEDULER 8:8 /* */ +#define NV_PMC_ENABLE_HOST_SCHEDULER_DISABLED 0x00000000 /* */ +#define NV_PMC_ENABLE_HOST_SCHEDULER_ENABLED 0x00000001 /* */ +#define NV_PMC_ENABLE_NVLINK 25:25 /* RWIVF */ +#define NV_PMC_ENABLE_NVLINK_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_NVLINK_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_ZPW 26:26 /* RWIVF */ +#define NV_PMC_ENABLE_ZPW_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_ZPW_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_BLG 27:27 /* RWIVF */ +#define NV_PMC_ENABLE_BLG_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_BLG_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */ +#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */ +#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */ +#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB 0x00000204 /* RW-4R */ +#define NV_PMC_ENABLE_PB_0 0:0 /* RWIVF */ +#define NV_PMC_ENABLE_PB_0_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_0_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_1 1:1 /* RWIVF */ +#define NV_PMC_ENABLE_PB_1_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_1_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_2 2:2 /* RWIVF */ +#define NV_PMC_ENABLE_PB_2_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_2_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_3 3:3 /* RWIVF */ +#define NV_PMC_ENABLE_PB_3_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_3_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_4 4:4 /* RWIVF */ +#define NV_PMC_ENABLE_PB_4_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_4_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_5 5:5 /* RWIVF */ +#define NV_PMC_ENABLE_PB_5_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_5_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_6 6:6 /* RWIVF */ +#define NV_PMC_ENABLE_PB_6_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_6_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_7 7:7 /* RWIVF */ +#define NV_PMC_ENABLE_PB_7_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_7_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_8 8:8 /* RWIVF */ +#define NV_PMC_ENABLE_PB_8_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_8_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_9 9:9 /* RWIVF */ +#define NV_PMC_ENABLE_PB_9_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_9_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_10 10:10 /* RWIVF */ +#define NV_PMC_ENABLE_PB_10_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_10_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_11 11:11 /* RWIVF */ +#define NV_PMC_ENABLE_PB_11_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_11_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_12 12:12 /* RWIVF */ +#define NV_PMC_ENABLE_PB_12_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_12_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_13 13:13 /* RWIVF */ +#define NV_PMC_ENABLE_PB_13_DISABLED 0x00000000 /* RW--V */ +#define NV_PMC_ENABLE_PB_13_ENABLED 0x00000001 /* RWI-V */ +#define NV_PMC_ENABLE_PB_SEL(i) (i):(i) /* */ +#define NV_PMC_ENABLE_PB_SEL__SIZE_1 14 /* */ diff --git a/Host-Fifo/volta/gv100/dev_pbdma.ref.txt b/Host-Fifo/volta/gv100/dev_pbdma.ref.txt new file mode 100644 index 0000000..bc5163a --- /dev/null +++ b/Host-Fifo/volta/gv100/dev_pbdma.ref.txt @@ -0,0 +1,4261 @@ +Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +1 - INTRODUCTION +================== + + A Host's PBDMA unit fetches pushbuffer data from memory, generates +commands, called "methods", from the fetched data, executes some of the +generated methods itself, and sends the remainder of the methods to engines. + This manual describes the Host PBDMA register space and all Host methods. +The NV_PPBDMA space defines registers that are contained within each of Host's +PBDMA units. Each PBDMA unit is allocated a 8KB address space for its +registers. + The NV_UDMA space defines the Host methods. A method consists of an +address doubleword and a data doubleword. The address specifies the operation +to be performed. The data is an operand. The NV_UDMA address space contains +the addresses of the methods that are executed by a PBDMA unit. +GP_ENTRY0 and GP_ENTRY1 - GP-Entry Memory Format + + A pushbuffer contains the specifications of the operations that a GPU +context is to perform for a particular client. Pushbuffers are stored in +memory. A doubleword-sized (4-byte) unit of pushbuffer data is known as a +pushbuffer entry. GP entries indicate the location of the pushbuffer data in +memory. GP entries themselves are also stored in memory. + A GP entry specifies the location and size of a pushbuffer segment (a +contiguous block of PB entries) in memory. See "FIFO_DMA" in dev_ram.ref for +details about pushbuffer segments and the format of pushbuffer data. + + The NV_PPBDMA_GP_ENTRY0_GET and NV_PPBDMA_GP_ENTRY1_GET_HI fields of a GP +entry specify the 38-bit dword-address (which would make a 40-bit byte-address) +of the first pushbuffer entry of the GP entry's pushbuffer segment. Because +each pushbuffer entry (and by extension each pushbuffer segment) is doubleword +aligned (4-byte aligned), the least significant 2 bits of the 40-bit +byte-address are not stored. The byte-address of the first pushbuffer entry in +a GP entry's pushbuffer segment is +(GP_ENTRY1_GET_HI << 32) + (GP_ENTRY0_GET << 2). + The NV_PPBDMA_GP_ENTRY1_LENGTH field, when non-zero, indicates the number +of pushbuffer entries contained within the GP entry's pushbuffer segment. The +byte-address of the first pushbuffer entry beyond the pushbuffer segment is +(GP_ENTRY1_GET_HI << 32) + (GP_ENTRY0_GET << 2) + (GP_ENTRY1_LENGTH * 4). + If NV_PPBDMA_GP_ENTRY1_LENGTH is CONTROL (0), then the GP entry is a +"control" entry, meaning this GP entry will not cause any PB data to be fetched +or executed. In this case, the NV_PPBDMA_GP_ENTRY1_OPCODE field specifies an +operation to perform, and the NV_PPBDMA_GP_ENTRY0_OPERAND field contains the +operand. The available operations are as follows: + + * NV_PPBDMA_GP_ENTRY1_OPCODE_NOP: no operation will be performed, but note + that the SYNC field is still respected--see below. + + * NV_PPBDMA_GP_ENTRY1_OPCODE_GP_CRC: the ENTRY0_OPERAND field is compared + with the cyclic redundancy check value that was calculated over previous + GP entries (NV_PPBDMA_GP_CRC). After each comparison, the + NV_PPBDMA_GP_CRC is cleared, whether they match or differ. If they + differ, then Host initiates an interrupt (NV_PPBDMA_INTR_0_GPCRC). For + recovery, clearing the interrupt will cause the PBDMA to continue as if + the control entry was OPCODE_NOP. + + * NV_PPBDMA_GP_ENTRY1_OPCODE_PB_CRC: the ENTRY0_OPERAND is compared + with the CRC value that was calculated over the previous pushbuffer + segment (NV_PPBDMA_PB_CRC). The PB CRC resets to 0 with each pushbuffer + segment. If the two CRCs differ, Host will raise the + NV_PPBDMA_INTR_0_PBCRC interrupt. For recovery, clearing the interrupt + will continue as if the control entry was OPCODE_NOP. Note the PB_CRC is + indeterminate if an END_PB_SEGMENT PB control entry was used in the prior + segment or if SSDM disabled the device and the segment had conditional + fetching enabled. + + Host supports two privilege levels for channels: privileged and +non-privileged. The privilege level is determined by the +NV_PPBDMA_CONFIG_AUTH_LEVEL field set from the corresponding NV_RAMFC_CONFIG +dword in the RAMFC. Non-privileged channels cannot execute privileged methods, +but privileged channels can. Any attempt to run a privileged operation from a +non-privileged channel will result in PB raising NV_PPBDMA_INTR_0_METHOD. + + + The NV_PPBDMA_GP_ENTRY1_SYNC field specifies whether a pushbuffer may be +fetched before Host has finished processing the preceding PB segment. If this +field is SYNC_PROCEED, then Host does not wait for the preceding PB segment to +be processed. If this field is SYNC_WAIT, then Host waits until the preceding +PB segment has been processed by Host before beginning to fetch the current PB +segment. + Host's processing of a PB segment consists of parsing PB entries into PB +instructions, decoding those instructions into control entries or method +headers, generating methods from method headers, determining whether methods are +to be executed by Host or by an engine, executing Host methods, and sending +non-Host methods and SetObject methods to engines. + Note that in the case where the final PB entry of the preceding PB segment +is a method header representing a PB compressed method sequence of nonzero +length--that is, the compressed method sequence is split across PB segments with +all of its method data entries in the PB segment for which SYNC_WAIT is +set--then Host is considered to have finished processing the preceding PB +segment once that method header is read. However, splitting a PB compressed +method sequence for software methods is not supported because Host will issue +the DEVICE interrupt indicating the SW method as soon as it processess the +method header, which happens prior to fetching the method data entries for that +compressed method sequence. Thus SW cannot actually execute any of the methods +in the sequence because the method data is not yet available, leaving the PBDMA +wedged. + When SYNC_WAIT is set, Host does not wait for any engine methods generated +from the preceding PB segment to complete. Host does not automatically wait +until an engine is done processing all methods generated from that PB segment. +If software desires that the engine finish processing all methods generated from +one PB segment before a second PB segment is fetched, then software may place +Host methods that wait until the engine is idle in the first PB segment (like +WFI, SET_REF, or SEM_EXECUTE with RELEASE_WFI_EN set). Alternatively, software +might put a semaphore acquire at the end of the first PB segment, and have an +engine release the semaphore. In both cases, SYNC_WAIT must be set on the +second PB segment. This field applies even if the NV_PPBDMA_GP_ENTRY1_LENGTH +field is zero; if SYNC_WAIT is specified in this case, no further GP entries +will be processed until the wait finishes. + + Some parts of a pushbuffer may not be executed depending on the value of +the NV_PPBDMA_SUBDEVICE_ID and SUBDEVICE_MASK. If an entire PB segment will not +be executed due to conditional execution, Host need not even bother fetching the +PB segment. + The NV_PPBDMA_GP_ENTRY0_FETCH field indicates whether the PB segment +specified by the GP entry should be fetched unconditionally or fetched +conditionally. If this field is FETCH_UNCONDITIONAL, then the PB segment is +fetched unconditionally. If this field is FETCH_CONDITIONAL, then the PB +segment is only fetched if the NV_PPBDMA_SUBDEVICE_STATUS field is +STATUS_ACTIVE. + +******************************************************************************** +Warning: When using subdevice masking, one must take care to synchronize +properly with any later GP entries marked FETCH_CONDITIONAL. If GP fetching +gets too far ahead of PB processing, it is possible for a later conditional PB +segment to be discarded prior to reaching an SSDM command that sets +SUBDEVICE_STATUS to ACTIVE. This would cause Host to execute garbage data. One +way to avoid this would be to set the SYNC_WAIT flag on any FETCH_CONDITIONAL +segments following a subdevice reenable. +******************************************************************************** + + If the PB segment is not fetched then it behaves as an OPCODE_NOP control +entry. If a PB segment contains a SET_SUBDEVICE_MASK PB instruction that Host +must see, then the GP entry for that PB segment must specify +FETCH_UNCONDITIONAL. + If the PB segment specifies FETCH_CONDITIONAL and the subdevice mask shows +STATUS_ACTIVE, but the PB segment contains a SET_SUBDEVICE_MASK PB instruction +that will disable the mask, the rest of the PB segment will be discarded. In +that case, an arbitrary number of entries past the SSDM may have already updated +the PB CRC, rendering the PB CRC indeterminate. + If Host must wait for a previous PB segment's Host processing to be +completed before examining NV_PPBDMA_SUBDEVICE_STATUS, then the GP entry should +also have its SYNC_WAIT field set. + A PB segment marked FETCH_CONDITIONAL must not have a PB compressed method +sequence that crosses a PB segment boundary (with its header in previous non- +conditional PB segment and its final valid data in a conditional PB segment)-- +doing so will cause a NV_PPBDMA_INTR_0_PBSEG interrupt. + + Software may monitor Host's progress through the pushbuffer by reading the +channel's NV_RAMUSERD_TOP_LEVEL_GET entry from USERD, which is backed by Host's +NV_PPBDMA_TOP_LEVEL_GET register. See "NV_PFIFO_USERD_WRITEBACK" in +dev_fifo.ref for information about how frequently this information is written +back into USERD. If a PB segment occurs multiple times within a pushbuffer +(like a commonly used subroutine), then progress through that segment may be +less useful for monitoring, because software will not know which occurrence of +the segment is being processed. + The NV_PPBDMA_GP_ENTRY_LEVEL field specifies whether progress through the +GP entry's PB segment should be indicated in NV_RAMUSERD_TOP_LEVEL_GET. If this +field is LEVEL_MAIN, then progress through the PB segment will be reported -- +NV_RAMUSERD_TOP_LEVEL_GET will equal NV_RAMUSERD_GET. If this field is +LEVEL_SUBROUTINE, then progress through this PB segment is not reported -- Host +will not alter NV_RAMUSERD_TOP_LEVEL_GET. If this field is LEVEL_SUBROUTINE, +reads of NV_RAMUSERD_TOP_LEVEL_GET will return the last value of NV_RAMUSERD_GET +from a PB segment at LEVEL_MAIN. + + If the GP entry's opcode is OPCODE_ILLEGAL or an invalid opcode, Host will +initiate an interrupt (NV_PPBDMA_INTR_0_GPENTRY). If a GP entry specifies a PB +segment that crosses the end of the virtual address space (0xFFFFFFFFFF), then +Host will initiate an interrupt (NV_PPBDMA_INTR_0_GPENTRY). Invalid GP entries +are treated like traps: they will set the interrupt and freeze the PBDMA, but +the invalid GP entry is discarded. Once the interrupt is cleared, the PBDMA +unit will simply continue with the next GP entry. + Note a corner case exists where the PB segment described by a GP entry is +at the end of the virtual address space, or in other words, the last PB entry in +the described PB segment is the last dword in the virtual address space. This +type of GP entry is not valid and will generate a GPENTRY interrupt. The +PBDMA's PUT pointer describes the address of the first dword beyond the PB +segment, thus making the last dword in the virtual address space unusable for +storing a pbentry. + + + +#define NV_PPBDMA_GP_ENTRY__SIZE 8 /* */ + +#define NV_PPBDMA_GP_ENTRY0 0x10000000 /* RW-4R */ + +#define NV_PPBDMA_GP_ENTRY0_OPERAND 31:0 /* RWXUF */ +#define NV_PPBDMA_GP_ENTRY0_FETCH 0:0 /* */ +#define NV_PPBDMA_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000 /* */ +#define NV_PPBDMA_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001 /* */ +#define NV_PPBDMA_GP_ENTRY0_GET 31:2 /* */ + +#define NV_PPBDMA_GP_ENTRY1 0x10000004 /* RW-4R */ + +#define NV_PPBDMA_GP_ENTRY1_GET_HI 7:0 /* RWXUF */ + + +#define NV_PPBDMA_GP_ENTRY1_LEVEL 9:9 /* RWXUF */ +#define NV_PPBDMA_GP_ENTRY1_LEVEL_MAIN 0x00000000 /* RW--V */ +#define NV_PPBDMA_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001 /* RW--V */ +#define NV_PPBDMA_GP_ENTRY1_LENGTH 30:10 /* RWXUF */ +#define NV_PPBDMA_GP_ENTRY1_LENGTH_CONTROL 0x00000000 /* RW--V */ +#define NV_PPBDMA_GP_ENTRY1_SYNC 31:31 /* RWXUF */ +#define NV_PPBDMA_GP_ENTRY1_SYNC_PROCEED 0x00000000 /* RW--V */ +#define NV_PPBDMA_GP_ENTRY1_SYNC_WAIT 0x00000001 /* RW--V */ +#define NV_PPBDMA_GP_ENTRY1_OPCODE 7:0 /* RWXUF */ +#define NV_PPBDMA_GP_ENTRY1_OPCODE_NOP 0x00000000 /* RW--V */ +#define NV_PPBDMA_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001 /* RW--V */ +#define NV_PPBDMA_GP_ENTRY1_OPCODE_GP_CRC 0x00000002 /* RW--V */ +#define NV_PPBDMA_GP_ENTRY1_OPCODE_PB_CRC 0x00000003 /* RW--V */ + + + + + +Number of NOPs for self-modifying gpfifo + +This is a formula for SW to estimate the number of NOPs needed to pad the gpfifo +such that the modification of a gp entry by the engine or by the CPU can take +effect. Here, NV_PFIFO_LB_GPBUF_CONTROL_SIZE(eng) refers to the SIZE field in the +NV_PFIFO_LB_GPBUF_CONTROL(eng) register.(More info about the register in dev_fifo.ref) + +NUM_GP_NOPS(eng) = ((NV_PFIFO_LB_GPBUF_CONTROL_SIZE(eng)+1) * NV_PFIFO_LB_ENTRY_SIZE)/ NV_PPBDMA_GP_ENTRY__SIZE + + + + + +GP_BASE - Base and Limit of the Circular Buffer of GP Entries + + GP entries are stored in a buffer in memory. The NV_PPBDMA_GP_BASE_OFFSET +and NV_PPBDMA_GP_BASE_HI_OFFSET fields specify the 37-bit address in 8-byte +granularity of the start of a circular buffer that contains GP entries (GPFIFO). +This address is a virtual (not a physical) address. GP entries are always +GP_ENTRY__SIZE-byte aligned, so the least significant three bits of the byte +address are not stored. The byte address of the GPFIFO base pointer is thus: + + gpfifo_base_ptr = GP_BASE + (GP_BASE_HI_OFFSET << 32) + + The number of GP entries in the circular buffer is always a power of 2. +The NV_PPBDMA_GP_BASE_HI_LIMIT2 field specifies the number of bits used to count +the memory allocated to the GP FIFO. The LIMIT2 value specified in these +registers is Log base 2 of the number of entries in the GP FIFO. For example, +if the number of entries is 2^16--indicating a memory area of +(2^16)*GP_ENTRY__SIZE bytes--then the value written in LIMIT2 is 16. + The circular buffer containing GP entries cannot cross the maximum address. +If OFFSET + (1< 0xFFFFFFFFFF, then Host will +initiate a CPU interrupt (NV_PPBDMA_INTR_0_GPFIFO). + The NV_PPBDMA_GP_PUT, NV_PPBDMA_GP_GET, and NV_PPBDMA_GP_FETCH registers +(and their associated NV_RAMFC and NV_RAMUSERD entries) are relative to the +value of this register. + These registers are part of a GPU context's state. On a switch, the values +of these registers are saved to, and restored from, the NV_RAMFC_GP_BASE and +NV_RAMFC_GP_BASE_HI entries in the RAMFC part of the GPU context's GPU-instance +block. + Typically, software initializes the information in NV_RAMFC_GP_BASE and +NV_RAMFC_GP_BASE_HI when the GPU context's GPU-instance block is first created. +These registers are available to software only for debug. Software should use +them only if the GPU context is assigned to a PBDMA unit and that PBDMA unit is +stalled. While a GPU context's Host context is not contained within a PBDMA +unit, software should use the RAMFC entries to access this information. + A pair of these registers exists for each of Host's PBDMA units. These +registers run on Host's internal bus clock. + + +#define NV_PPBDMA_GP_BASE(i) (0x00040048+(i)*8192) /* RW-4A */ +#define NV_PPBDMA_GP_BASE__SIZE_1 14 /* */ + +#define NV_PPBDMA_GP_BASE_OFFSET 31:3 /* RW-UF */ +#define NV_PPBDMA_GP_BASE_OFFSET_ZERO 0x00000000 /* RW--V */ +#define NV_PPBDMA_GP_BASE_RSVD 2:0 /* RW-UF */ +#define NV_PPBDMA_GP_BASE_RSVD_ZERO 0x00000000 /* RW--V */ + +#define NV_PPBDMA_GP_BASE_HI(i) (0x0004004c+(i)*8192) /* RW-4A */ +#define NV_PPBDMA_GP_BASE_HI__SIZE_1 14 /* */ + +#define NV_PPBDMA_GP_BASE_HI_OFFSET 7:0 /* RW-UF */ +#define NV_PPBDMA_GP_BASE_HI_OFFSET_ZERO 0x00000000 /* RW--V */ +#define NV_PPBDMA_GP_BASE_HI_LIMIT2 20:16 /* RW-UF */ +#define NV_PPBDMA_GP_BASE_HI_LIMIT2_ZERO 0x00000000 /* RW--V */ +#define NV_PPBDMA_GP_BASE_HI_RSVDA 15:8 /* RW-UF */ +#define NV_PPBDMA_GP_BASE_HI_RSVDA_ZERO 0x00000000 /* RW--V */ +#define NV_PPBDMA_GP_BASE_HI_RSVDB 31:21 /* RW-UF */ +#define NV_PPBDMA_GP_BASE_HI_RSVDB_ZERO 0x00000000 /* RW--V */ + + +GP_FETCH - Pointer to the next GP-Entry to be Fetched + + Host does not fetch all GP entries with a single request to the memory +subsystem. Host fetches GP entries in batches. The NV_PPBDMA_GP_FETCH register +indicates index of the next GP entry to be fetched by Host. The actual 40-bit +virtual address of the specified GP entry is computed as follows: + fetch address = GP_FETCH_ENTRY * NV_PPBDMA_GP_ENTRY__SIZE + GP_BASE + If NV_PPBDMA_GP_PUT==NV_PPBDMA_GP_FETCH, then requests to fetch the entire +GP circular buffer have been issued, and Host cannot make more requests until +NV_PPBDMA_GP_PUT is changed. Host may finish fetching GP entries long before it +has finished processing the PB segments specified by those entries. +Software should not use NV_PPBDMA_GP_FETCH (it should use NV_PPBDMA_GP_GET), to +determine whether the GP circular buffer is full. NV_PPBDMA_GP_FETCH represents +the current extent of prefetching of GP entries; prefetched entries may be +discarded and refetched later. + This register is part of a GPU context's state. On a switch, the value of +this register is saved to, and restored from, the NV_RAMFC_GP_FETCH entry of +the RAMFC part of the GPU context's GPU-instance block. + A PBDMA unit maintains this register. Typically, software does not need to +access this register. This register is available to software only for debug. +Because Host may fetch GP entries long before it is ready to process the +entries, and because Host may discard GP entries that it has fetched, software +should not use NV_PPBDMA_GP_FETCH to monitor Host's progress (software should +use NV_PPBDMA_GP_GET for monitoring). Software should use this register only if +the GPU context is assigned to a PBDMA unit and that PBDMA unit is stalled. +While a GPU context's Host context is not contained within a PBDMA unit, +software should use NV_RAMFC_GP_FETCH to access this information. + If after a PRI write, or after this register has been restored from RAMFC +memory, the value equals or exceeds the size of the circular buffer that stores +GP entries (1<= PV), +where SV is the semaphore value in memory, PV is the payload value, and >= is +an unsigned greater-than-or-equal-to comparison. + If OPERATION is ACQ_CIRC_GEQ, the acquire succeeds when the two's +complement signed representation of the semaphore value minus the payload value +is non-negative; that is, when the semaphore value is within half a range +greater than or equal to the payload value, modulo that range. The +PAYLOAD_SIZE field determines if Host is doing a 32 bit comparison or a 64 bit +comparison. So in other words, the condition is met when the PAYLOAD_SIZE is +32BIT and the semaphore value is within the range [payload, +((payload+(2^(32-1)))-1)], modulo 2^32, or when the PAYLOAD_SIZE is 64BIT and +the semaphore value is within the range [payload, ((payload+(2^(64-1)))-1)], +modulo 2^64. + If OPERATION is ACQ_AND, the acquire succeeds when the bitwise-AND of the +semaphore value and the payload value is not zero. The PAYLOAD_SIZE field +determines if a 32 bit or 64 bit value is read from memory, and compared to. + If OPERATION is ACQ_NOR, the acquire succeeds when the bitwise-NOR of the +semaphore value and the payload value is not zero. PAYLOAD_SIZE determines if +a 32 bit or 64 bit value is read from memory, and compared to. + If OPERATION is RELEASE, then Host simply writes the payload value to the +semaphore structure in memory at the SEM_ADDR_LO/_HI address. The exact value +written depends on the operation defined. If PAYLOAD_SIZE is 32BIT then a 32 +bit payload value from PAYLOAD_LO is used. If PAYLOAD_SIZE is 64BIT then a 64 +bit payload specified by PAYLOAD_LO/_HI is used. + If OPERATION is REDUCTION, then Host sends the memory system an +instruction to perform the atomic reduction operation specified in the +REDUCTION field on the memory value, using the PAYLOAD_LO/_HI payload value as +the operand. The OPERATION_PAYLOAD_SIZE field determines if a 32 bit or 64 bit +reduction is performed. Note that if the semaphore address refers to a page +whose PTE has ATOMIC_DISABLE set, the operation will result in an +ATOMIC_VIOLATION fault; + Note that if the PAYLOAD_SIZE is 64BIT, the semaphore address is required +to be 8-byte aligned. If RELEASE_TIMESTAMP is EN while the operation is a +RELEASE or REDUCTION operation, the semaphore address is required to be 16-byte +aligned. The semaphore address is not required to be 16-byte aligned during an +acquire operation. If the semaphore address is not aligned according to the +field values Host will raise the NV_PPBDMA_INTR_0 interrupt. + For iGPU cases where a semaphore release can be mapped to an onchip syncpoint, +the SIZE must be 4Bytes to avoid double incrementing the target syncpoint. +Timestamping should also be disabled to avoid unwanted behavior. + +Semaphore switch option: + + The NV_UDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG field specifies whether or not +Host should switch to processing another TSG if the acquire fails. If every +channel within the same TSG has no work (is waiting on a semaphore acquire, is +idle, is unbound, or is disabled), the TSG can make no further progress until +one of the relevant semaphores is released. Because it may be a long time +before the release, it may be more efficient for the PBDMA unit to switch off +the blocked TSG prior to the runqueue timeslice expiring, so that it can serve +a different TSG that is not waiting, or so that it can poll other semaphores on +other TSGs whose channels are waiting on acquires. + When a semaphore acquire fails, the PBDMA unit will always switch to +another channel within the same TSG, provided that it has not completed a +traversal through all the TSG's channels. If every pending channel in the TSG +is waiting on a semaphore acquire, the Host scheduler is able identify a lack +of progress for the entire TSG by the time it has completed a traversal through +all those channels. In this case the value of ACQUIRE_SWITCH_TSG for each of +these channels determines whether the PBDMA will switch to another TSG or start +another traversal through the same TSG. + If ACQUIRE_SWITCH_TSG is DIS for any of the channels in the TSG, the Host +scheduler will ignore any lack of progress and continue processing the TSG, +until either every channel in the TSG runs out of work or the timeslice +expires. If ACQUIRE_SWITCH_TSG is EN for every pending channel in the TSG, the +Host scheduler will recognize a lack of progress for the whole TSG, and will +switch to the next serviceable TSG on the runqueue, if possible. + In the case described above, if there isn't a different serviceable TSG +on the runlist, then the current channel's TSG will continue to be scheduled +and the acquire retry will be naturally delayed by the time it takes for Host's +runlist processing to return to the same channel. This retry delay may be too +short, in which case the runlist search can be throttled to increase the delay +by configuring NV_PFIFO_ACQ_PRETEST; see dev_fifo.ref. Note that if the +channel remains switched in, the prefetched pushbuffer data is not discarded, +so setting ACQUIRE_SWITCH_TSG_EN cannot deterministically be depended on to +cause the discarding of prefetched pushbuffer data. + Also note that when switching between channels within a TSG, Host does not +wait on any timer (such as NV_PFIFO_ACQ_PRETEST or NV_PPBDMA_ACQUIRE_RETRY), +but is instead throttled by the time it takes to switch channels. Host will +honor the ACQUIRE_RETRY time, but only if the same channel is rescheduled +without a channel switch. + +Semaphore wait-for-idle option: + + The NV_UDMA_SEM_EXECUTE_RELEASE_WFI field applies only to releases and +reductions. It specifies whether Host should wait until the engine to which +the channel last sent methods is idle (in other words, until all previous +methods in the channel have been completed) before writing to memory as part of +the release or reduction operation. If this field is RELEASE_WFI_EN, then Host +waits for the engine to be idle, inserts a system memory barrier, and then +updates the value in memory. If this field is RELEASE_WFI_DIS, Host performs +the semaphore operation on the memory without waiting for the engine to be +idle, and without using a system memory barrier. + +Semaphore timestamp option: + + The NV_UDMA_SEM_EXECUTE_RELEASE_TIMESTAMP specifies whether a timestamp +should be written by a release in addition to the payload. If +RELEASE_TIMESTAMP is DIS, then only the semaphore payload will be written. If +the field is EN then both the semaphore payload and a nanosecond timestamp will +be written. In this case, the semaphore address must be 16-byte aligned; see +the related note at NV_UDMA_SEM_ADDR_LO. If RELEASE_TIMESTAMP is EN and +SEM_ADDR_LO is not 16-byte aligned, then Host will initiate an interrupt +(NV_PPBDMA_INTR_0_SEMAPHORE). When a 16-byte semaphore is written, the +semaphore timestamp will be written before the semaphore payload so that when +an acquire succeeds, the timestamp write will have completed. This ensures SW +will not get an out-of-date timestamp on platforms which guarantee ordering +within a 16-byte aligned region. The timestamp value is snapped from the +NV_PTIMER_TIME_1/0 registers; see dev_timer.ref. + For iGPU cases where a semaphore release can be mapped to an onchip syncpoint, +the SIZE must be 4Bytes to avoid double incrementing the target syncpoint. +Timestamping should also be disabled for a synpoint backed releast to avoid +unexpected behavior. + + Below is the little endian format of 16-byte semaphores in memory: + + ---- ------------------- ------------------- + byte Data(Little endian) Data(Little endian) + PAYLOAD_SIZE=32BIT PAYLOAD_SIZE=64BIT + ---- ------------------- ------------------- + 0 Payload[ 7: 0] Payload[ 7: 0] + 1 Payload[15: 8] Payload[15: 8] + 2 Payload[23:16] Payload[23:16] + 3 Payload[31:24] Payload[31:24] + 4 0 Payload[39:32] + 5 0 Payload[47:40] + 6 0 Payload[55:48] + 7 0 Payload[63:56] + 8 timer[ 7: 0] timer[ 7: 0] + 9 timer[15: 8] timer[15: 8] + 10 timer[23:16] timer[23:16] + 11 timer[31:24] timer[31:24] + 12 timer[39:32] timer[39:32] + 13 timer[47:40] timer[47:40] + 14 timer[55:48] timer[55:48] + 15 timer[63:56] timer[63:56] + ---- ------------------- ------------------- + + +Semaphore reduction operations: + + The NV_UDMA_SEM_EXECUTE_REDUCTION field specifies the reduction operation +to perform on the semaphore memory value, using the semaphore payload from +SEM_PAYLOAD_LO/HI as an operand, when the OPERATION field is +OPERATION_REDUCTION. Based on the PAYLOAD_SIZE field the semaphore value and +the payload are interpreted as 32bit or 64bit integers and the reduction +operation is performed according to the signedness specified via the +REDUCTION_FORMAT field described below. The reduction operation leaves the +modified value in the semaphore memory according to the operation as follows: + +REDUCTION_IMIN - the minimum of the value and payload +REDUCTION_IMAX - the maximum of the value and payload +REDUCTION_IXOR - the bitwise exclusive or (XOR) of the value and payload +REDUCTION_IAND - the bitwise AND of the value and payload +REDUCTION_IOR - bitwise OR of the value and payload +REDUCTION_IADD - the sum of the value and payload +REDUCTION_INC - the value incremented by 1, or reset to 0 if the incremented + value would exceed the payload +REDUCTION_DEC - the value decremented by 1, or reset back to the payload + if the original value is already 0 or exceeds the payload + +Note that INC and DEC are somewhat surprising: they can be used to repeatedly +loop the semaphore value when performed successively with the same payload p. +INC repeatedly iterates from 0 to p inclusive, resetting to 0 once exceeding p. +DEC repeatedly iterates down from p to 0 inclusive, resetting back to p once +the value would otherwise underflow. Therefore, an INC or DEC reduction with +payload 0 effectively releases a semaphore by setting its value to 0. + +The reduction opcode assignment matches the enumeration in the XBAR translator +(to avoid extra remapping of hardware), but this does not match the graphics FE +reduction opcodes used by graphics backend semaphores. The reduction operation +itself is performed by L2. + +Semaphore signedness option: + + The NV_UDMA_SEM_EXECUTE_REDUCTION_FORMAT field specifies whether the +values involved in a reduction operation will be interpreted as signed or +unsigned. + +The following table summarizes each reduction operation, and the signedness and +payload size supported for each operation: + + signedness + r op 32b 64b function (v = memory value, p = semaphore payload) + -----+-----+-----+--------------------------------------------------- + IMIN U,S U,S v = (v < p) ? v : p + IMAX U,S U,S v = (v > p) ? v : p + IXOR N/A N/A v = v ^ p + IAND N/A N/A v = v & p + IOR N/A N/A v = v | p + IADD U,S U v = v + p + INC U inv v = (v >= p) ? 0 : v + 1 + DEC U inv v = (v == 0 || v > p) ? p : v - 1 (from L2 IAS) + +An operation with signedness "N/A" will ignore the value of REDUCTION_FORMAT +when executing, and either value of REDUCTION_FORMAT is valid. If an operation +is "U only" this means a signed version of this operation is not supported, and +if it is marked "inv" then it is unsupported for any signedness. If Host sees +an unsupported reduction op (in other words, is expected to run a reduction op +while PAYLOAD_SIZE and REDUCTION_FORMAT are set to unsupported values for that +op), Host will raise the NV_PPBDMA_INTR_0_SEMAPHORE interrupt. + +Example: A signed 32-bit IADD reduction operation is valid. A signed 64-bit +IADD reduction operation is unsupported and will trigger an interrupt if sent to +Host. A 64-bit INC (or DEC) operation is not supported and will trigger an +interrupt if sent to Host. + +Legal semaphore operation combinations: + + For iGPU cases where a semaphore release can be mapped to an onchip syncpoint, +the SIZE must be 4Bytes to avoid double incrementing the target syncpoint. +Timestamping should also be disabled for a synpoint backed release to avoid +unexpected behavior. + + The following table diagrams the types of semaphore operations that are +possible. In the columns, "x" matches any field value. ACQ refers to any of +the ACQUIRE, ACQ_STRICT_GEQ, ACQ_CIRC_GEQ, ACQ_AND, and ACQ_NOR operations. +REL refers to either a RELEASE or a REDUCTION operation. + + OP SWITCH WFI PAYLOAD_SIZE TIMESTAMP Description + --- ------ --- ------------ --------- -------------------------------------------------------------- + ACQ 0 x 0 x acquire; 4B (32 bit comparison); retry on fail + ACQ 0 x 1 x acquire; 8B (64 bit comparison); retry on fail + ACQ 1 x 0 x acquire; 4B (32 bit comparison); switch on fail + ACQ 1 x 1 x acquire; 8B (64 bit comparison); switch on fail + REL x 0 0 1 WFI & release 4B payload + timestamp semaphore + REL x 0 1 1 WFI & release 8B payload + timestamp semaphore + REL x 1 0 1 do not WFI & release 4B payload + timestamp semaphore + REL x 1 1 1 do not WFI & release 8B payload + timestamp semaphore + REL x 0 0 0 WFI & release doubleword (4B) semaphore payload + REL x 0 1 0 WFI & release quadword (8B) semaphore payload + REL x 1 0 0 do not WFI & release doubleword (4B) semaphore payload + REL x 1 1 0 do not WFI & release quadword (8B) semaphore payload + --- ------ --- ------------ --------- -------------------------------------------------------------- + + While the channel is loaded on a PBDMA unit, information from this method +is stored in the NV_PPBDMA_SEM_EXECUTE register. Otherwise, this information +is stored in the NV_RAMFC_SEM_EXECUTE field of the RAMFC part of the channel's +instance block. + +Undefined bits: + + Bits in the NV_UDMA_SEM_EXECUTE method data that are not used by the +specified OPERATION should be set to 0. When non-zero, their behavior is +undefined. + + + +#define NV_UDMA_SEM_EXECUTE 0x0000006C /* -W-4R */ + +#define NV_UDMA_SEM_EXECUTE_OPERATION 2:0 /* -W-VF */ +#define NV_UDMA_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_OPERATION_RELEASE 0x00000001 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_OPERATION_ACQ_STRICT_GEQ 0x00000002 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_OPERATION_ACQ_CIRC_GEQ 0x00000003 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_OPERATION_ACQ_AND 0x00000004 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_OPERATION_ACQ_NOR 0x00000005 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_OPERATION_REDUCTION 0x00000006 /* -W--V */ + +#define NV_UDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG 12:12 /* -W-VF */ +#define NV_UDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_DIS 0x00000000 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_ACQUIRE_SWITCH_TSG_EN 0x00000001 /* -W--V */ + +#define NV_UDMA_SEM_EXECUTE_RELEASE_WFI 20:20 /* -W-VF */ +#define NV_UDMA_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_RELEASE_WFI_EN 0x00000001 /* -W--V */ + +#define NV_UDMA_SEM_EXECUTE_PAYLOAD_SIZE 24:24 /* -W-VF */ +#define NV_UDMA_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_PAYLOAD_SIZE_64BIT 0x00000001 /* -W--V */ + +#define NV_UDMA_SEM_EXECUTE_RELEASE_TIMESTAMP 25:25 /* -W-VF */ +#define NV_UDMA_SEM_EXECUTE_RELEASE_TIMESTAMP_DIS 0x00000000 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_RELEASE_TIMESTAMP_EN 0x00000001 /* -W--V */ + +#define NV_UDMA_SEM_EXECUTE_REDUCTION 30:27 /* -W-VF */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_IMIN 0x00000000 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_IMAX 0x00000001 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_IXOR 0x00000002 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_IAND 0x00000003 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_IOR 0x00000004 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_IADD 0x00000005 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_INC 0x00000006 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_DEC 0x00000007 /* -W--V */ + +#define NV_UDMA_SEM_EXECUTE_REDUCTION_FORMAT 31:31 /* -W-VF */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_FORMAT_SIGNED 0x00000000 /* -W--V */ +#define NV_UDMA_SEM_EXECUTE_REDUCTION_FORMAT_UNSIGNED 0x00000001 /* -W--V */ + + +NON_STALL_INT [method] - Non-Stalling Interrupt Method + + The NON_STALL_INT method causes the NV_PFIFO_INTR_0_CHANNEL_INTR field +to be set to PENDING in the channel's interrupt register, as well as +NV_PFIFO_INTR_HIER_* registers. This will cause an interrupt if it is +enabled. Host does not stall the execution of the GPU context's +method, does not switch out the GPU context, and does not disable switching the +GPU context. + A NON_STALL_INT method's data (NV_UDMA_NON_STALL_INT_HANDLE) is ignored. + Software should handle all of a channel's non-stalling interrupts before it +unbinds the channel from the GPU context. + + +#define NV_UDMA_NON_STALL_INT 0x00000020 /* -W-4R */ + +#define NV_UDMA_NON_STALL_INT_HANDLE 31:0 /* -W-VF */ + + + + +MEM_OP methods: membars, and cache and TLB management. + + MEM_OP_A, MEM_OP_B, and MEM_OP_C set up state for performing a memory +operation. MEM_OP_D sets additional state, specifies the type of memory +operation to perform, and triggers sending the mem op to HUB. To avoid +unexpected behavior for future revisions of the MEM_OP methods, all 4 methods +should be sent for each requested mem op, with irrelevant fields set to 0. +Note that hardware does not enforce the requirement that unrelated fields be set +to 0, but ignoring this advice could break forward compatibility. + Host does not wait until an engine is idle before beginning to execute +this method. + While a GPU context is bound to a channel and assigned to a PBDMA unit, +the NV_UDMA_MEM_OP_A-C values are stored in the NV_PPBDMA_MEM_OP_A-C registers +respectively. While the GPU context is not assigned to a PBDMA unit, these +values are stored in the respective NV_RAMFC_MEM_OP_A-C fields of the RAMFC part +of the GPU context's instance block in memory. + +Usage, operations, and configuration: + + MEM_OP_D_OPERATION specifies the type of memory operation to perform. This +field determines the value of the opcode on the Host/FB interface. When Host +encounters the MEM_OP_D method, Host sends the specified request to the FB and +waits for an indication that the request has completed before beginning to +process the next method. To issue a memory operation, first issue the 3 +MEM_OP_A-C methods to configure the operation as documented below. Then send +MEM_OP_D to complete the configuration and trigger the operation. The +operations available for MEM_OP_D_OPERATION are as follows: + MEMBAR - perform a memory barrier; see below. + MMU_TLB_INVALIDATE - invalidate page translation and attribute data from +the given page directory that are cached in the Memory-Management Unit TLBs. + MMU_TLB_INVALIDATE_TARGETED - invalidate page translation and attributes +data corresponding to a specific page in a given page directory. + L2_SYSMEM_INVALIDATE - invalidate data from system memory cached in L2. + L2_PEERMEM_INVALIDATE - invalidate peer-to-peer data in the L2 cache. + L2_CLEAN_COMPTAGS - clean the L2 compression tag cache. + L2_FLUSH_DIRTY - flush dirty lines from L2. + L2_WAIT_FOR_SYS_PENDING_READS - ensure all sysmem reads are past the point +of being modified by a write through a reflected mapping. To do this, L2 drains +all sysmem reads to the point where they cannot be modified by future +non-blocking writes to reflected sysmem. L2 will block any new sysmem read +requests and drain out all read responses. Note VC's with sysmem read requests +at the head would stall any request till the flush is complete. The niso-nb vc +does not have sysmem read requests so it would continue to flow. L2 will ack +that the sys flush is complete and unblock all VC's. Note this operation is a +NOP on tegra chips. + ACCESS_COUNTER_CLR - clear page access counters. + + Depending on the operation given in MEM_OP_D_OPERATION, the other fields of +all four MEM_OP methods are interpreted differently: + +MMU_TLB_INVALIDATE* +------------------- + + When the operation is MMU_TLB_INVALIDATE or MMU_TLB_INVALIDATE_TARGETED, +then Host will initiate a TLB invalidate as described above. The MEM_OP +configuration fields specify what to invalidate, where to perform the +invalidate, and optionally trigger a replay or cancel event for replayable +faults buffered within the TLBs as part of UVM page management. + When the operation is MMU_TLB_INVALIDATE_TARGETED, +MEM_OP_C_TLB_INVALIDATE_PDB must be ONE, and the TLB_INVALIDATE_TARGET_ADDR_LO +and HI fields must be filled in to specify the target page. + These operations are privileged and can only be executed from channels +with NV_PPBDMA_CONFIG_AUTH_LEVEL set to PRIVILEGED. This is configured via the +NV_RAMFC_CONFIG dword in the channel's RAMFC during channel setup. + + MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID and +MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID identify the GPC and uTLB +within that GPC respectively that should perform the cancel operation when +MEM_OP_C_TLB_INVALIDATE_REPLAY is CANCEL_TARGETED. These field values should be +copied from the GPC_ID and CLIENT fields from the associated +NV_UVM_FAULT_BUF_ENTRY packet or NV_PFIFO_INTR_MMU_FAULT_INFO(i) entry. The +CLIENT_UNIT_ID corresponds to the values specified by NV_PFAULT_CLIENT_GPC_* in +dev_fault.ref. These fields are used with the CANCEL_TARGETED operation. The +fields also overlap with CANCEL_MMU_ENGINE_ID, and are interpreted as +CANCEL_MMU_ENGINE_ID during reply of type REPLAY_CANCEL_VA_GLOBAL. For other +replay operations, these fields must be 0. + + MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID specifies the associated +MMU_ENGINE_ID of the requests targeted by a REPLAY_CANCEL_VA_GLOBAL +operation. The field is ignored if the replay operation is not +REPLAY_CANCEL_VA_GLOBAL. This field overlaps with CANCEL_TARGET_GPC_ID and +CANCEL_TARGET_CLIENT_UNIT_ID field. + + MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE is aliased/repurposed + with MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID field + when MEM_OP_C_TLB_INVALIDATE_REPLAY (below) is anything other + than CANCEL_TARGETED or CANCEL_VA_GLOBAL or + CANCEL_VA_TARGETED. In the invalidation size enabled replay type + cases, actual region to be invalidated iscalculated as + 4K*(2^INVALIDATION_SIZE) i.e., + 4K*(2^CANCEL_TARGET_CLIENT_UNIT_ID); client unit id and gpc id + are not applicable. + + MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR controls whether a Hub SYSMEMBAR +operation is performed after waiting for all outstanding acks to complete, after +the TLB is invalidated. Note if ACK_TYPE is ACK_TYPE_NONE then this field is +ignored and no MEMBAR will be performed. This is provided as a SW optimization +so that SW does not need to perform a NV_UDMA_MEM_OP_D_OPERATION_MEMBAR op with +MEMBAR_TYPE SYS_MEMBAR after the TLB_INVALIDATE. This field must be 0 if +TLB_INVALIDATE_GPC is DISABLE. + + MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI:MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO +specifies the 4k aligned virtual address of the page whose translation to +invalidate within the TLBs. These fields are valid only when OPERATION is +MMU_TLB_INVALIDATE_TARGETED; otherwise, they must be set to 0. + + MEM_OP_C_TLB_INVALIDATE_PDB controls whether a TLB invalidate should apply +to a particular page directory or to all of them. If PDB is ALL, then all page +directories are invalidated. If PDB is ONE, then the PDB address and aperture +are specified in the PDB_ADDR_LO:PDB_ADDR_HI and PDB_APERTURE fields. +Note that ALL does not make sense when OPERATION is MMU_TLB_INVALIDATE_TARGETED; +the behavior in that case is undefined. + + MEM_OP_C_TLB_INVALIDATE_GPC controls whether the GPC-MMU and uTLB entries +should be invalidated in addition to the Hub-MMU TLB (Note: the Hub TLB is +always invalidated). Set it to INVALIDATE_GPC_ENABLE to invalidate the GPC TLBs. +The REPLAY, ACK_TYPE, and SYSMEMBAR fields are only used by the GPC TLB and so +are ignored if INVALIDATE_GPC is DISABLE. + + MEM_OP_C_TLB_INVALIDATE_REPLAY specifies the type of replay to perform in +addition to the invalidate. A replay causes all replayable faults outstanding +in the TLB to attempt their translations again. Once a TLB acks a replay, that +TLB may start accepting new translations again. The replay flavors are as +follows: + NONE - do not replay any replayable faults on invalidate. + START - initiate a replay across all TLBs, but don't wait for completion. + The replay will be acked as soon as the invalidate is processed, but + replays themselves are in flight and not necessarily translated. + START_ACK_ALL - initiate the replay and wait until it completes. + The replay will be acked after all pending transactions in the replay + fifo have been translated. New requests will remain stalled in the + gpcmmu until all transactions in the replay fifo have completed and + there are no pending faults left in the replay fifo. + CANCEL_TARGETED - initiate a cancel-replay on a targeted uTLB, causing any + replayable translations buffered in that uTLB to become non-replayable + if they fault again. In this case, the first faulting translation + will be reported in the NV_PFIFO_INTR_MMU_FAULT registers and will + raise PFIFO_INTR_0_MMU_FAULT. The specific TLB to target for the + cancel is specified in the CANCEL_TARGET fields. Note the TLB + invalidate still applies globally to all TLBs. + CANCEL_GLOBAL - like CANCEL_TARGETED, but all TLBs will cancel-replay. + CANCEL_VA_GLOBAL - initiates a cancel operation that cancels all requests + with the matching mmu_engine_id and access_type that land in the + specified 4KB aligned virtual address within the scope of specified + PDB. All other requests are replayed. If the specified engine is not + bound, or if the PDB of the specified engine does not match the + specified PDB, all requests will be replayed and none will be canceled. + + MEM_OP_C_TLB_INVALIDATE_ACK_TYPE controls which sort of ACK the uTLBs wait +for after having issued a membar to L2. ACK_TYPE_NONE does not perform any sort +of membar. ACK_TYPE_INTRANODE waits for an ack from the XBAR. +ACK_TYPE_GLOBALLY waits for an L2 ACK. ACK_TYPE_GLOBALLY is equivalent to a +MEMBAR operation from the engine, or a SYS_MEMBAR if +MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR is EN. + + MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL specifies which levels in the page +directory hierarchy of the TLB cache to invalidate. The levels are numbered +from the bottom up, with the PTE being at the bottom with level 1. The +specified level and all those below it in the hierarchy -- that is, all those +with a lower numbered level -- are invalidated. ALL (the 0 default) is +special-cased to indicate the top level; this causes the invalidate to apply to +the entire page mapping structure. The field is ignored if the replay operation +is REPLAY_CANCEL_VA_GLOBAL. + + MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE specifies the associated ACCESS_TYPE of +the requests targeted by a REPLAY_CANCEL_VA_GLOBAL operation. This field +overlaps with the INVALIDATE_PAGE_TABLE_LEVEL field, and is ignored if the +replay operation is not REPLAY_CANCEL_VA_GLOBAL. The ACCESS_TYPE field can get +one of the following values: + READ - the cancel_va_global should be performed on all pending read requests. + WRITE - the cancel_va_global should be performed on all pending write requests. + ATOMIC_STRONG - the cancel_va_global should be performed on all pending + strong atomic requests. + ATOMIC_WEAK - the cancel_va_global should be performed on all pending + weak atomic requests. + ATOMIC_ALL - the cancel_va_global should be performed on all pending atomic + requests. + WRITE_AND_ATOMIC - the cancel_va_global should be performed on all pending + write and atomic requests. + ALL - the cancel_va_global should be performed on all pending requests. + + + MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE specifies the target aperture of the +page directory for which TLB entries should be invalidated. This field must be +0 when TLB_INVALIDATE_PDB is ALL. + + MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO specifies the low 20 bits of the +4k-block-aligned PDB (base address of the page directory) when +TLB_INVALIDATE_PDB is ONE; otherwise this field must be 0. The PDB byte address +should be 4k aligned and right-shifted by 12 before being split and packed into +the ADDR fields. Note that the PDB_ADDR_LO field starts at bit 12, so it is +possible to set MEM_OP_C to the low 32 bits of the byte address, mask off the +low 12, and then or in the rest of the configuration fields. + + MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI contains the high bits of the PDB when +TLB_INVALIDATE_PDB is ONE. Otherwise this field must be 0. + +UVM handling of replayable faults: + + The following example illustrates how TLB invalidate may be used by the +UVM driver: + 1. When the TLB invalidate completes, all memory accesses using the old + TLB entries prior to the invalidate will finish translation (but not + completion), and any new virtual accesses will trigger new + translations. The outstanding in-flight translations are allowed to + fault but will not indefinitely stall the invalidate. + 2. When the TLB invalidate completes, in-flight memory accesses using the + old physical translations may not yet be visible to other GPU clients + (such as CopyEngine) or to the CPU. Accesses coming from clients that + support recoverable faults (such as TEX and GCC) can be made visible by + requesting the MMU to perform a membar using the ACK_TYPE and SYSMEMBAR + fields. + a. If ACK_TYPE is NONE the SYSMEMBAR field is ignored and no membar + is performed. + b. If ACK_TYPE is INTRANODE the invalidate will wait until all + in-flight physical accesses using the old translations are visible + to XBAR clients on the blocking VC. + c. If ACK_TYPE is GLOBALLY the invalidate will wait until all + in-flight physical accesses using the old translations are at the + point of coherence in L2, meaning writes will be visible to all + other GPU clients and reads will not be mutable by them. + d. If the SYSMEMBAR field is set to EN then a Hub SYSMEMBAR will also + be performed following the ACK_TYPE membar. This is the equivalent + of performing a NV_UDMA_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR. + 3. If fault replay was requested then all pending recoverable faults in + the TLB replay list will be retranslated. This includes all faults + discovered while the invalidate was pending. This replay may generate + more recoverable faults. + 4. If fault replay cancel was requested then another replay is attempted of + all pending replayable faults on the targeted TLB(s). If any of these + re-fault they are discarded (sticky NACK or ACK/TRAP sent back to the + client depending on the setting of NV_PGPC_PRI_MMU_DEBUG_CTRL). + + + +MEMBAR +------ + + When the operation is MEMBAR, Host will perform a memory barrier operation. +All other fields must be set to 0 except for MEM_OP_C_MEMBAR_TYPE. When +MEMBAR_TYPE is MEMBAR, then a memory barrier will be performed with respect to +other clients on the GPU. When it is SYS_MEMBAR, the memory barrier will also be +performed with respect to the CPU and peer GPUs. + + MEMBAR - This issues a MEMBAR operation following all reads, writes, and +atomics currently in flight from the PBDMA. The MEMBAR operation will push all +such accesses already in flight on the same VC as the PBDMA to a point of GPU +coherence before proceeding. After this operation is complete, reads from any +GPU client will see prior writes from this PBDMA, and writes from any GPU client +cannot modify the return data of earlier reads from this PBDMA. This is true +regardless of whether those accesses target vidmem, sysmem, or peer mem. + WARNING: This only guarantees accesses from the same VC as the PBDMA that +are already in flight are coherent. Accesses from clients such as SM or a +non-PBDMA engine need already be at some point of coherency before this +operation to be coherent. + + SYS_MEMBAR - This implies the MEMBAR type above but in addition to having +accesses reach coherence with all GPU clients, this further waits for accesses +to be coherent with respect to the CPU and peer GPUs as well. After this +operation is complete, reads from the CPU or peer GPUs will see prior writes +from this PBDMA, and writes from the CPU or peer GPUs cannot modify the return +data of earlier reads from this PBDMA (with the exception of CPU reflected +writes, which can modify earlier reads). Note SYS_MEMBAR is really only needed +to guarantee ordering with off-chip clients. For on-chip clients such as the +graphics engine or copy engine, accesses to sysmem will be coherent with just a +MEMBAR operation. SYS_MEMBAR provides the same function as +OPERATION_SYSMEMBAR_FLUSH on previous architectures. + WARNING: As described above, SYS_MEMBAR will not prevent CPU reflected +writes issued after the SYS_MEMBAR from clobbering the return data of reads +issued before the SYS_MEMBAR. To handle this case, the invalidate must be +followed with a separate L2_WAIT_FOR_SYS_PENDING_READS mem op. + + + +L2* +--- + + These values initiate a cache management operation -- see above. All other +fields must be 0; there are no configuration options. + + + + +The ACCESS_COUNTER_CLR operation +-------------------------------- + When MEM_OP_D_OPERATION is ACCESS_COUNTER_CLR, Host will request to clear +the the page access counters. There are two types of access counters - MIMC and +MOMC. This operation can be issued to clear all counters of all types, all +counters of a specified type (MIMC or MOMC), or a specific counter indicated by +counter type, bank and notify tag. + This operation is privileged and can only be executed from channels with +NV_PPBDMA_CONFIG_AUTH_LEVEL set to PRIVILEGED. This is configured via the +NV_RAMFC_CONFIG dword in the channel's RAMFC during channel setup. + +The operation uses the following fields in the MEM_OP_* methods: +ACCESS_COUNTER_CLR_TYPE (TY) : type of the access counter clear + operation +ACCESS_COUNTER_CLR_TARGETED_TYPE (T) : type of the access counter for + targeted operation +ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG : 20 bits notify tag of the access + counter for targeted operation +ACCESS_COUNTER_CLR_TARGETED_BANK : 4 bits bank number of the access + counter for targeted operation + + + + + +MEM_OP method field defines: + +MEM_OP_A [method] - Memory Operation Method 1/4 - see above for documentation + +#define NV_UDMA_MEM_OP_A 0x00000028 /* -W-4R */ + +#define NV_UDMA_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 /* -W-VF */ +#define NV_UDMA_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 /* -W-VF */ +#define NV_UDMA_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 /* -W-VF */ +#define NV_UDMA_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 6:0 /* -W-VF */ +#define NV_UDMA_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11 /* -W-VF */ +#define NV_UDMA_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001 /* -W--V */ +#define NV_UDMA_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12 /* -W-VF */ + + +MEM_OP_B [method] - Memory Operation Method 2/4 - see above for documentation + +#define NV_UDMA_MEM_OP_B 0x0000002c /* -W-4R */ + +#define NV_UDMA_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0 /* -W-VF */ + + +MEM_OP_C [method] - Memory Operation Method 3/4 - see above for documentation + +#define NV_UDMA_MEM_OP_C 0x00000030 /* -W-4R */ + +Membar configuration field. Note: overlaps MMU_TLB_INVALIDATE* config fields. +#define NV_UDMA_MEM_OP_C_MEMBAR_TYPE 2:0 /* -W-VF */ +#define NV_UDMA_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001 /* -W--V */ +Invalidate TLB entries for ONE page directory base, or for ALL of them. +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PDB 0:0 /* -W-VF */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 /* -W--V */ +Invalidate GPC MMU TLB entries or not (Hub-MMU entries are always invalidated). +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_GPC 1:1 /* -W-VF */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 /* -W-VF */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 /* -W-VF */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 /* -W-VF */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 /* -W-VF */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 /* -W-VF */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002 /* -W--V */ +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 /* -W--V */ +Address[31:12] of page directory for which TLB entries should be invalidated. +#define NV_UDMA_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 /* -W-VF */ + +#define NV_UDMA_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0 /* -W-VF */ + +MEM_OP_D [method] - Memory Operation Method 4/4 - see above for documentation +(Must be preceded by MEM_OP_A-C.) + +#define NV_UDMA_MEM_OP_D 0x00000034 /* -W-4R */ + +Address[58:32] of page directory for which TLB entries should be invalidated. +#define NV_UDMA_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 /* -W-VF */ +#define NV_UDMA_MEM_OP_D_OPERATION 31:27 /* -W-VF */ +#define NV_UDMA_MEM_OP_D_OPERATION_MEMBAR 0x00000005 /* -W--V */ +#define NV_UDMA_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009 /* -W--V */ +#define NV_UDMA_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a /* -W--V */ +#define NV_UDMA_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d /* -W--V */ +#define NV_UDMA_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e /* -W--V */ +#define NV_UDMA_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f /* -W--V */ +#define NV_UDMA_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010 /* -W--V */ +#define NV_UDMA_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015 /* -W--V */ + +#define NV_UDMA_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016 /* -W--V */ + +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0 /* -W-VF */ +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001 /* -W--V */ +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002 /* -W--V */ +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003 /* -W--V */ + +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2 /* -W-VF */ +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000 /* -W--V */ +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001 /* -W--V */ + +#define NV_UDMA_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3 /* -W-VF */ + + +SET_REF [method] - Set Reference Count Method + + The SET_REF method allows the user to set the reference count +(NV_PPBDMA_REF_CNT) to a value. The reference count may be monitored to track +Host's progress through the pushbuffer. Instead of monitoring +NV_RAMUSERD_TOP_LEVEL_GET, software may put into the method stream SET_REF +methods that set the reference count to ever increasing values, and then read +NV_RAMUSERD_REF to determine how far in the stream Host has gone. + Before the reference count value is altered, Host waits for the engine to +be idle (to have completed executing all earlier methods), issues a SysMemBar +flush, and waits for the flush to complete. + While the GPU context is bound to a channel and assigned to a PBDMA unit, +the reference count value is stored in the NV_PPBDMA_REF register. While the +GPU context is not assigned to a PBDMA unit, the reference count value is stored +in the NV_RAMFC_REF field of the RAMFC portion of the GPU context's GPU-instance +block. + + +#define NV_UDMA_SET_REF 0x00000050 /* -W-4R */ + +#define NV_UDMA_SET_REF_CNT 31:0 /* -W-VF */ + + + +CRC_CHECK [method] - Method-CRC Check Method + + When debugging a problem in a real chip, it may be useful to determine +whether a PBDMA unit has sent the proper methods toward the engine. The +CRC_CHECK method checks whether the cyclic redundancy check value +calculated over previous methods has an expected value. If the value in the +NV_PPBDMA_METHOD_CRC register is not equal to NV_UDMA_CRC_CHECK_VALUE, then +Host initiates an interrupt (NV_PPBDMA_INTR_0_METHODCRC) and stalls. After +each comparison, the NV_PPBDMA_METHOD_CRC register is cleared. + The IEEE 802.3 CRC-32 polynomial (0x04c11db7) is used to calculate CRC +values. The CRC is calculated over the method subchannel, method address, and +method data of methods sent to an engine. Host can set both single and dual +methods to engines. The CRC is calculated as if dual methods were sent as +two single methods. The CRC is calculated on the byte-stream in little-endian +order. + + +Pseudocode for CRC calculation is: + + static NVR_U32 table[256]; + void init() { + for (NVR_U32 i = 0; i < 256; i++) { // create crc value for every byte + NVR_U32 crc = i << 24; + for (int j = 0; j < 8; j++) { // for every bit in the byte + if (crc & 0x80000000) crc = (crc << 1) ^ 0x04c11db7 + else crc = (crc << 1); + } + table[i] = crc; + } + } + NVR_U32 new_crc(unsigned char byte, NVR_U32 old_crc) { + NVR_U32 crc_top_byte = old_crc >> 24; + crc_top_byte ^= byte; + NVR_U32 new_crc = (old_crc << 8) ^ table[crc_top_byte]; + return new_crc; + } + + This method is used for debug. + This method was added in Fermi. + + +#define NV_UDMA_CRC_CHECK 0x0000007c /* -W-4R */ + +#define NV_UDMA_CRC_CHECK_VALUE 31:0 /* -W-VF */ + + +YIELD [method] - Yield Method + + The YIELD method causes a channel to yield the remainder of its timeslice. +The method's OP field specifies whether the channels' PBDMA timeslice, the +channel's runlist timeslice, or no timeslice is yielded. + If YIELD_OP_RUNLIST_TIMESLICE, then Host will act as if the channel's +runlist or TSG timeslice expired. Host will exit the TSG and switch to the next +channel after the TSG on the runlist. If there is no such channel to switch to, +then YIELD_OP_RUNLIST_TIMESLICE will not cause a switch. + When the PBDMA executes a YIELD_OP_RUNLIST_TIMESLICE method, it guarantees +that it will not execute further methods from the same channel or TSG until the +channel is restarted by the scheduler. However, note that this does not yield +the engine timeslice; if the engine is preemptable, the context will continue +to run on the engine until the remainder of its timeslice expires before Host +will attempt to preempt it. Also if there is an outstanding ctx load either +due to ctx_reload or from the other PBDMA in the SCG case, then yielding won't +take place until the outstanding ctx load finishes or aborts due to a preempt. +When the ctx load does complete on the other PBDMA, it is possible for that +PBDMA to execute some small number of additional methods before the runlist +yield takes effect and that PBDMA halts work for its channel. + If NV_UDMA_YIELD_OP_TSG, and if the channel is part of a TSG, then Host +will switch to the next channel in the same TSG, and if the channel is not part +of the TSG then this will be treated similar to YIELD_OP_NOP. If there is only +one channel with work in the TSG, Host will simply reschedule the same channel +in the TSG. YIELD_OP_TSG does not cause the scheduler to leave the TSG. The TSG +timeslice (TSG timeslice is equivalent to runlist timeslice for TSGs) counter +continues to increment through the channel switch and does not restart after +executing the yield method. When the PBDMA executes a Yield method, it +guarantees that it will not execute the method following that Yield until the +channel is restarted by the scheduler. + YIELD_OP_NOP is simply a NOP. Neither timeslice is yielded. This was kept +for compatibility with existing tests; NV_UDMA_NOP is the preferred NOP, but +also see the universal NOP PB instruction. See the description of +NV_FIFO_DMA_NOP in the "FIFO_DMA" section of dev_ram.ref. + + If an unknown OP is specified, Host will raise an NV_PPBDMA_INTR_*_METHOD +interrupt. + + +#define NV_UDMA_YIELD 0x00000080 /* -W-4R */ + +#define NV_UDMA_YIELD_OP 1:0 /* -W-VF */ +#define NV_UDMA_YIELD_OP_NOP 0x00000000 /* -W--V */ +#define NV_UDMA_YIELD_OP_RUNLIST_TIMESLICE 0x00000002 /* -W--V */ +#define NV_UDMA_YIELD_OP_TSG 0x00000003 /* -W--V */ + + +WFI [method] - Wait-for-Idle Method + + The WFI (Wait-For-Idle) method will stall Host from processing any more +methods on the channel until the engine to which the channel last sent methods +is idle. Note that the subchannel encoded in the method header is ignored (as +it is for all Host-only methods) and does NOT specify which engine to idle. In +Kepler, this is only relevant on runlists that serve multiple engines +(specifically, the graphics runlist, which also serves GR COPY). + The WFI method has a single field SCOPE which specifies the level of WFI +the Host method performs. ALL waits for all work in the engine from the same +context to be idle across all classes and subchannels. CURRENT_VEID causes the +WFI to only apply to work from the same VEID as the current channel. Note for +engines that do not support VEIDs, CURRENT_VEID works identically to ALL. + Note that Host methods ignore the subchannel field in the method. A Host +WFI method always applies to the engine the channel last sent methods to. If a +WFI with ALL is specified and the channel last sent work to the GRCE, this will +only guarantee that GRCE has no work in progress. It is possible that the GR +context will have work in progress from other VEIDs, or even the current VEID if +the current channel targets GRCE and has never sent FE methods before. This +means that if SW wants to idle the graphics pipe for all VEIDs, SW must send a +method to GR immediately before the WFI method. A GR_NOP is sufficient. + Note also that even if the current NV_PPBDMA_TARGET is GRAPHICS and not +GRCE, there are cases where Host can trivially complete a WFI without sending +the NV_PMETHOD_HOST_WFI internal method to FE. This can happen when + +1. the runlist timeslices to a different TSG just before the WFI method, +2. the other TSG does a ctxsw request due to methods for FE, and +3. FECS reports non-preempted in the ctx ack, so CTX_RELOAD doesn't get set. + +In that case, when the channel switches back onto the PBDMA, the PBDMA rightly +concludes that there is no way the context could be non-idle for that channel, +and therefore filters out the WFI, even if the other PBDMA is sending work to +other VEIDs. As in the subchannel case, a GR_NOP preceding the WFI is +sufficient to ensure that a SCOPE_ALL_VEID WFI will be sent to FE regardless of +timeslicing as long as the NOP and the WFI are submitted as part of the same +GP_PUT update. This is ensured by the semantics of the channel state +SHOULD_SEND_HOST_TSG_EVENT behaving like CTX_RELOAD: the GR_NOP causes the PBDMA +to set the SHOULD_SEND_HOST_TSG_EVENT state, so even a channel or context switch +will still result in the PBDMA having the engine context loaded. Thus the WFI +will cause the HOST_WFI internal method to be sent to FE. + + +#define NV_UDMA_WFI 0x00000078 /* -W-4R */ + +#define NV_UDMA_WFI_SCOPE 0:0 /* -W-VF */ +#define NV_UDMA_WFI_SCOPE_CURRENT_VEID 0x00000000 /* -W--V */ +#define NV_UDMA_WFI_SCOPE_ALL 0x00000001 /* -W--V */ +#define NV_UDMA_WFI_SCOPE_ALL_VEID 0x00000001 /* */ + + + +CLEAR_FAULTED [method] - Clear Faulted Method + + The CLEAR_FAULTED method clears a channel's PCCSR PBDMA_FAULTED or +ENG_FAULTED bit. These bits are set by Host in response to a PBDMA fault or +engine fault respectively on the specified channel; see dev_fifo.ref. + + The CHID field specifies the ID of the channel whose FAULTED bit is to be +cleared. + + The TYPE field specifies which FAULTED bit is to be cleared: either +PBDMA_FAULTED or ENG_FAULTED. + + When Host receives a CLEAR_FAULTED method for a channel, the corresponding +PCCSR FAULTED bit for the channel should be set. However, due to a race between +SW seeing the fault message from MMU and handling the fault and sending the +CLEAR_FAULT method verses Host seeing the fault from CE or MMU and setting the +FAULTED bit, it is possible for the CLEAR_FAULTED method to arrive before the +FAULTED bit is set. Host will handle a CLEAR_FAULTED method according to the +following cases: + + a. The FAULTED bit specified by TYPE is set. Host will clear the bit and +retire the CLEAR_FAULTED method. + + b. If the bit is not set, the PBDMA will continue to retry the +CLEAR_FAULTED method on every PTIMER microsecond tick by rechecking the FAULTED +bit of the target channel. Once the bit is set, the PBDMA will clear the bit and +retire the method. The execution of the fault handling channel will stall on the +CLEAR_FAULTED method until the FAULTED bit for the target channel is set. The +PBDMA will retry the CLEAR_FAULTED method approximately every microsecond. + + c. If the fault handling channel's timeslice expires while stalled on a +CLEAR_FAULTED method, the channel will switch out. Once rescheduled, the +channel will resume retrying the CLEAR_FAULTED method. + + d. To avoid indefinitely waiting for the CLEAR_FAULTED method to retire +(likely due to wrongly injected CLEAR_FAULTED method due to a SW bug), Host +has a timeout mechanism to inform SW of a potential bug. This timeout is +controlled by NV_PFIFO_CLEAR_FAULTED_TIMEOUT; see dev_fifo.ref for details. + + e. When a CLEAR_FAULTED timeout is detected, Host will raise a stalling +interrupt by setting the NV_PPBDMA_INTR_0_CLEAR_FAULTED_ERROR field. The +address of the invalid CLEAR_FAULTED method will be in NV_PPBDMA_METHOD0, and +its payload will be in NV_PPBDMA_DATA0. + + Note Setting the timeout value too low could result in false stalling +interrupts to SW. The timeout should be set equal to NV_PFIFO_FB_TIMEOUT_PERIOD. + + Note the CLEAR_FAULTED timeout mechanism uses the same PBDMA registers and +RAMFC fields as the semaphore acquire timeout mechanism: +NV_PPBDMA_SEM_EXECUTE_ACQUIRE_FAIL is set TRUE when the first attempt fails, and +the NV_PPBDMA_ACQUIRE_DEADLINE is loaded with the sum of the current PTIMER and +the NV_PFIFO_CLEAR_FAULTED_TIMEOUT. The ACQUIRE_FAIL bit is reset to FALSE when +the CLEAR_FAULTED method times out or succeeds. + + +#define NV_UDMA_CLEAR_FAULTED 0x00000084 /* -W-4R */ + +#define NV_UDMA_CLEAR_FAULTED_CHID 11:0 /* -W-VF */ +#define NV_UDMA_CLEAR_FAULTED_TYPE 31:31 /* -W-VF */ +#define NV_UDMA_CLEAR_FAULTED_TYPE_PBDMA_FAULTED 0x00000000 /* -W--V */ +#define NV_UDMA_CLEAR_FAULTED_TYPE_ENG_FAULTED 0x00000001 /* -W--V */ + + + + Addresses that are not defined in this device are reserved. Those below +0x100 are reserved for future Host methods. Addresses 0x100 and beyond are +reserved for the engines served by Host. diff --git a/Host-Fifo/volta/gv100/dev_ram.ref.txt b/Host-Fifo/volta/gv100/dev_ram.ref.txt new file mode 100644 index 0000000..e80d9c0 --- /dev/null +++ b/Host-Fifo/volta/gv100/dev_ram.ref.txt @@ -0,0 +1,1269 @@ +Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +2 - GPU INSTANCE RAM (RAMIN) +============================== + + A GPU contains a block called "XVE" that manages the interface with PCI, a +block called "Host" that fetches graphics instructions, blocks called "engines" +that execute graphics instructions, and blocks that manage the interface with +memory. + + .-----. .------. + | |<------------------>| | + | | | | + | | .---------. | | + | |<--->| Engine1 |<---| | + | | `---------' | | +.---------. | | | | +| GPU | | | .---------. | Host | +| Local |<-->| FB |<--->| Engine2 |<---| | +| Memory | | MMU | `---------' | | +`---------' | Hub | ... | | .--------. + | | .---------. | | | System | + | |<--->| EngineN |<---| | | Memory | + | | `---------' `------' `--------' + | | ^ ^ + | | | | +.---------. | | .--V--. PCI .--V--. .-----. +| Display |<-->| |<------------------>| XVE |<--->| NB |<--->| CPU | +`---------' `-----' `-----' `-----' `-----' + + A GPU context is a virtualization of the GPU for a particular software +application. A GPU instance block is a block of memory that contains the state +for a GPU context. A GPU context's instance block consists of Host state, +pointers to each engine's state, and memory management state. A GPU instance +block also contains a pointer to a block of memory that contains that part of a +GPU context's state that a user-level driver may access. A GPU instance block +fits within a single 4K-byte page of memory. + + Run List Channel-Map RAM + .----------. Ch Id .----------------. + | RL Entry0 |----. |Ch0 Inst Blk Ptr| + | RL Entry1 | | |Ch1 Inst Blk Ptr| + | RL Entry2 | | | ... | + | ... | `--->|ChI Inst Blk Ptr|----. + | RL EntryN | | ... | | + `-----------' |ChN Inst Blk Ptr| | + `----------------' | + | + .-----------------------------------------------' + | + | GPU Instance Block GPFIFO + `-->.-----------------. GP_GET .--------. PB Seg + | |------------------------------>|GP Entry| .--------. + | Host State | |GP Entry|--->|PB Entry| + | (RAMFC) | User-Driver State | | |PB Entry| + | | .-------. |GP Entry| | ... | + | |------------->|(USERD)| GP_PUT |GP Entry| |PB Entry| + | | | |------->`--------' `--------' + | | | | + +-----------------+ | | + | Memory | `-------' + | Management |----------. Page Directory Page Table + | State | | .-------. .-------. + +-----------------+ `-->| PDE | | PTE | + | Pointer to | | PDE |------->| PTE | + | Engine0 |--------. | ... | | ... | + | State | | | PDE | | PTE | + +-----------------+ | `-------' `-------' + | Pointer to | | + | Engine1 |-----. | Engine0 State + | State | | | .-------. + +-----------------+ | `---->| | + ... | `-------' + +-----------------+ | + | Pointer to | | Engine1 State + | EngineN |--. | .-------. + | State | | `------->| | + `-----------------' | `-------' + | ... + | + | EngineN State + | .-------. + `---------->| | + `-------' + + The GPU context's Host state occupies the first 128 double words of an +instance block. A GPU context's Host state is called "RAMFC". Please see +the NV_RAMFC section below for a description of Host state. + + The GPU context's memory-management state defines the virtual address space +that the GPU context uses. Memory management state consists of page and +directory tables (that specify the mapping between virtual addresses and +physical addresses, and the attributes of memory pages), and the limit of the +virtual address space. The NV_RAMIN_PAGE_DIR_BASE entry contains the address of +base of the GPU context's page directory table (PDB). NV_RAMIN_PAGE_DIR_BASE is +4K-byte aligned. + + The NV_RAMIN_ENG*_WFI_PTR entry contains the address of a block of memory +for storing an engine's context state. Blocks of memory that contain engine state +are 4K-byte aligned. Only one engine context is supported per instance block. + + The NV_RAMIN_ENG*_CS field is deprecated, it was used to indicate whether +GPU state should be restored from the FGCS pointer or from the WFI CS pointer. +Engines only need/support one CTXSW pointer and all state is stored there +whether a WFI CS or other form of preemption was performed. This field must +always be set to WFI for legacy reasons, and will eventually be deleted. + + +#define NV_RAMIN /* ----G */ + +// The instance block must be 4k-aligned. +#define NV_RAMIN_BASE_SHIFT 12 /* */ + +// The instance block size fits within a single 4k block. +#define NV_RAMIN_ALLOC_SIZE 4096 /* */ + +// Host State +#define NV_RAMIN_RAMFC (127*32+31):(0*32+0) /* RWXUF */ + +// Memory-Management State + + The following fields are used for non-VEID engines. The NV_RAMIN_SC_* described later + are used for VEID engines. + + NV_RAMIN_PAGE_DIR_BASE_TARGET determines if the top level of the page tables + is in video memory or system memory (peer is not allowed), and the CPU cache + coherency for system memory. + Using INVALID, unbinds the selected engine. + +#define NV_RAMIN_PAGE_DIR_BASE_TARGET (128*32+1):(128*32+0) /* RWXUF */ +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_INVALID 0x00000001 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ + + NV_RAMIN_PAGE_DIR_BASE_VOL identifies the volatile behavior + of top level of the page table (whether local L2 can cache it or not). + +#define NV_RAMIN_PAGE_DIR_BASE_VOL (128*32+2):(128*32+2) /* RWXUF */ +#define NV_RAMIN_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */ + + + These bits specify whether the MMU will treats faults as replayable or not. + The engine will send these bits to the MMU as part of the instance bind. + +#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX (128*32+4):(128*32+4) /* RWXUF */ +#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX_DISABLED 0x00000000 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_TEX_ENABLED 0x00000001 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC (128*32+5):(128*32+5) /* RWXUF */ +#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC_DISABLED 0x00000000 /* RW--V */ +#define NV_RAMIN_PAGE_DIR_BASE_FAULT_REPLAY_GCC_ENABLED 0x00000001 /* RW--V */ + + NV_RAMIN_USE_NEW_PT_FORMAT determines which page table format to use. + When NV_RAMIN_USE_NEW_PT_FORMAT is false, the page table uses the old format. + When NV_RAMIN_USE_NEW_PT_FORMAT is true, the page table uses the new format. + + Volta only supports the new format. Selecting the old format results in an UNBOUND_INSTANCE fault. + + +#define NV_RAMIN_USE_VER2_PT_FORMAT (128*32+10):(128*32+10) /* */ +#define NV_RAMIN_USE_VER2_PT_FORMAT_FALSE 0x00000000 /* */ +#define NV_RAMIN_USE_VER2_PT_FORMAT_TRUE 0x00000001 /* */ + + When NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE is bit TRUE, the bit selects the big page size. + When NV_PFB_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE is bit FALSE, NV_PFB_PRI_MMU_CTRL_VM_PG_SIZE selects the big page size. + + Volta only supports 64KB for big pages. Selecting 128KB for big pages results in an UNBOUND_INSTANCE fault. + +#define NV_RAMIN_BIG_PAGE_SIZE (128*32+11):(128*32+11) /* RWXUF */ +#define NV_RAMIN_BIG_PAGE_SIZE_128KB 0x00000000 /* RW--V */ +#define NV_RAMIN_BIG_PAGE_SIZE_64KB 0x00000001 /* RW--V */ + + NV_RAMIN_PAGE_DIR_BASE_LO and NV_RAMIN_PAGE_DIR_BASE_HI + identify the page directory base (start of the page table) + location for this context. + +#define NV_RAMIN_PAGE_DIR_BASE_LO (128*32+31):(128*32+12) /* RWXUF */ +#define NV_RAMIN_PAGE_DIR_BASE_HI (129*32+31):(129*32+0) /* RWXUF */ + +// Single engine pointer channels cannot support multiple +// engines with CTXSW pointers +#define NV_RAMIN_ENGINE_CS (132*32+3):(132*32+3) /* */ +#define NV_RAMIN_ENGINE_CS_WFI 0x00000000 /* */ +#define NV_RAMIN_ENGINE_CS_FG 0x00000001 /* */ +#define NV_RAMIN_ENGINE_WFI_TARGET (132*32+1):(132*32+0) /* */ +#define NV_RAMIN_ENGINE_WFI_TARGET_LOCAL_MEM 0x00000000 /* */ +#define NV_RAMIN_ENGINE_WFI_TARGET_SYS_MEM_COHERENT 0x00000002 /* */ +#define NV_RAMIN_ENGINE_WFI_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* */ +#define NV_RAMIN_ENGINE_WFI_MODE (132*32+2):(132*32+2) /* */ +#define NV_RAMIN_ENGINE_WFI_MODE_PHYSICAL 0x00000000 /* */ +#define NV_RAMIN_ENGINE_WFI_MODE_VIRTUAL 0x00000001 /* */ +#define NV_RAMIN_ENGINE_WFI_PTR_LO (132*32+31):(132*32+12) /* */ +#define NV_RAMIN_ENGINE_WFI_PTR_HI (133*32+7):(133*32+0) /* */ + +#define NV_RAMIN_ENGINE_WFI_VEID (134*32+(6-1)):(134*32+0) /* */ +#define NV_RAMIN_ENABLE_ATS (135*32+31):(135*32+31) /* RWXUF */ +#define NV_RAMIN_ENABLE_ATS_TRUE 0x00000001 /* RW--V */ +#define NV_RAMIN_ENABLE_ATS_FALSE 0x00000000 /* RW--V */ +#define NV_RAMIN_PASID (135*32+(20-1)):(135*32+0) /* RWXUF */ + + + Pointer to a method buffer in BAR2 memory where a faulted engine can save +out methods. BAR2 accesses are assumed to be virtual, so the address saved here +is a virtual address. + +#define NV_RAMIN_ENG_METHOD_BUFFER_ADDR_LO (136*32+31):(136*32+0) /* RWXUF */ +#define NV_RAMIN_ENG_METHOD_BUFFER_ADDR_HI (137*32+(((49-1)-32))):(137*32+0) /* RWXUF */ + + + + These entries are used to inform FECS which of the below array of PDBs are + valid/filled in and need to subsequently be bound. + + This needs to reserve at least NV_LITTER_NUM_SUBCTX entries. Currently + there is enough space reserved for 64 subcontexts. +#define NV_RAMIN_SC_PDB_VALID(i) (166*32+i):(166*32+i) /* RWXUF */ +#define NV_RAMIN_SC_PDB_VALID__SIZE_1 64 /* */ +#define NV_RAMIN_SC_PDB_VALID_FALSE 0x00000000 /* RW--V */ +#define NV_RAMIN_SC_PDB_VALID_TRUE 0x00000001 /* RW--V */ + +// Memory-Management VEID array + + The NV_RAMIN_SC_PAGE_DIR_BASE_* entries are an array of page table settings + for each subcontext. When a context supports subcontexts, the page table + information for a given VEID/Subcontext needs to be filled in or else page + faults will result on access. + + These properties for the page table must be filled in for all channels + sharing the same context as any channel's NV_RAMIN may be used to load the + context. + + The non-subcontext page table information such as NV_RAMIN_PAGE_DIR_BASE* + are used by non-subcontext engines and clients such as Host, CE, or the + video engines. + + NV_RAMIN_SC_PAGE_DIR_BASE_TARGET(i) determines if the top level of the page tables + is in video memory or system memory (peer is not allowed), and the CPU cache + coherency for system memory. + Using INVALID, unbinds the selected subcontext. + +#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET(i) ((168+(i)*4)*32+1):((168+(i)*4)*32+0) /* RWXUF */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET__SIZE_1 64 /* */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_VID_MEM 0x00000000 /* RW--V */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_INVALID 0x00000001 /* RW--V */ // Note: INVALID should match PEER +#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ + + NV_RAMIN_SC_PAGE_DIR_BASE_VOL(i) identifies the volatile behavior + of the top level of the page table (whether local L2 can cache it or not). + +#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL(i) ((168+(i)*4)*32+2):((168+(i)*4)*32+2) /* RWXUF */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL__SIZE_1 64 /* */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL_TRUE 0x00000001 /* RW--V */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_VOL_FALSE 0x00000000 /* RW--V */ + + NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX(i) and + NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC(i) bits specify whether + the MMU will treats faults from TEX and GCC as replayable or + not. Based on that fault packets are written into replayable fault + buffer (or not) and faulting requests are put into replay request + buffer (or not). + The last bind that does not unbind a sub-context determines the REPLAY_TEX and REPLAY_GCC for all sub-contexts. + +#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX(i) ((168+(i)*4)*32+4):((168+(i)*4)*32+4) /* RWXUF */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX__SIZE_1 64 /* */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX_DISABLED 0x00000000 /* RW--V */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_TEX_ENABLED 0x00000001 /* RW--V */ + +#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC(i) ((168+(i)*4)*32+5):((168+(i)*4)*32+5) /* RWXUF */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC__SIZE_1 64 /* */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC_DISABLED 0x00000000 /* RW--V */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_FAULT_REPLAY_GCC_ENABLED 0x00000001 /* RW--V */ + + NV_RAMIN_SC_USE_VER2_PT_FORMAT determines which page table format to use. + When NV_RAMIN_SC_USE_VER2_PT_FORMAT is false, the page table uses + the old format(2-level page table). When + NV_RAMIN_SC_USE_VER2_PT_FORMAT is true, the page table uses the + new format (5-level 49-bit VA format). + The last bind that does not unbind a sub-context determines the page table format for all sub-contexts. + Volta only supports the new format. Selecting the old format results in an UNBOUND_INSTANCE fault. + +#define NV_RAMIN_SC_USE_VER2_PT_FORMAT(i) ((168+(i)*4)*32+10):((168+(i)*4)*32+10) /* RWXUF */ +#define NV_RAMIN_SC_USE_VER2_PT_FORMAT__SIZE_1 64 /* */ +#define NV_RAMIN_SC_USE_VER2_PT_FORMAT_FALSE 0x00000000 /* RW--V */ +#define NV_RAMIN_SC_USE_VER2_PT_FORMAT_TRUE 0x00000001 /* RW--V */ + + The last bind that does not unbind a sub-context determines the big page size for all sub-contexts. + Volta only supports 64KB for big pages. + +#define NV_RAMIN_SC_BIG_PAGE_SIZE(i) ((168+(i)*4)*32+11):((168+(i)*4)*32+11) /* RWXUF */ +#define NV_RAMIN_SC_BIG_PAGE_SIZE__SIZE_1 64 /* */ +#define NV_RAMIN_SC_BIG_PAGE_SIZE_64KB 0x00000001 /* RW--V */ + + NV_RAMIN_SC_PAGE_DIR_BASE_LO(i) and NV_RAMIN_SC_PAGE_DIR_BASE_HI(i) + identify the page directory base (start of the page table) + location for subcontext i. + +#define NV_RAMIN_SC_PAGE_DIR_BASE_LO(i) ((168+(i)*4)*32+31):((168+(i)*4)*32+12) /* RWXUF */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_LO__SIZE_1 64 /* */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_HI(i) ((169+(i)*4)*32+31):((169+(i)*4)*32+0) /* RWXUF */ +#define NV_RAMIN_SC_PAGE_DIR_BASE_HI__SIZE_1 64 /* */ + + + + + + NV_RAMIN_SC_ENABLE_ATS(i) tells whether subcontext i is ATS + enabled or not. In case, set to TRUE, GMMU will look for VA->PA + translations into both GMMU and ATS page tables. + ATS can be enabled or disabled per subcontext. + +#define NV_RAMIN_SC_ENABLE_ATS(i) ((170+(i)*4)*32+31):((170+(i)*4)*32+31) /* RWXUF */ + + NV_RAMIN_SC_PASID(i) identifies the PASID (process address space + ID) in CPU for subcontext i. PASID is used to get ATS + translation when ATS page table lookup is needed. During ATS TLB + shootdown, PASID is also used to match against the one coming with + shootdown request. + +#define NV_RAMIN_SC_PASID(i) ((170+(i)*4)*32+(20-1)):((170+(i)*4)*32+0) /* RWXUF */ + + + + +3 - FIFO CONTEXT RAM (RAMFC) +============================== + + + The NV_RAMFC part of a GPU-instance block contains Host's part of a virtual +GPU's state. Host is referred to as "FIFO". "FC" stands for FIFO Context. +When Host switches from serving one GPU context to serving a second, Host saves +state for the first GPU context to the first GPU context's RAMFC area, and loads +state for the second GPU context from the second GPU context's RAMFC area. + + RAMFC is located at NV_RAMIN_RAMFC within the GPU instance block. In +Kepler, this is at the start of the block. RAMFC is 4KB aligned. + + Every Host word entry in RAMFC directly corresponds to a PRI-accessible +register. For a description of the contents of a RAMFC entry, please see the +description of the corresponding register in "manuals/dev_pbdma.ref". The +offsets of the fields within each entry in RAMFC match those of the +corresponding register in the associated PBDMA unit's PRI space. + + + RAMFC Entry PBDMA Register + ------------------------------- ---------------------------------- + NV_RAMFC_SIGNATURE NV_PPBDMA_SIGNATURE(i) + NV_RAMFC_GP_BASE NV_PPBDMA_GP_BASE(i) + NV_RAMFC_GP_BASE_HI NV_PPBDMA_GP_BASE_HI(i) + NV_RAMFC_GP_FETCH NV_PPBDMA_GP_FETCH(i) + NV_RAMFC_GP_GET NV_PPBDMA_GP_GET(i) + NV_RAMFC_GP_PUT NV_PPBDMA_GP_PUT(i) + NV_RAMFC_PB_FETCH NV_PPBDMA_PB_FETCH(i) + NV_RAMFC_PB_FETCH_HI NV_PPBDMA_PB_FETCH_HI(i) + NV_RAMFC_PB_GET NV_PPBDMA_GET(i) + NV_RAMFC_PB_GET_HI NV_PPBDMA_GET_HI(i) + NV_RAMFC_PB_PUT NV_PPBDMA_PUT(i) + NV_RAMFC_PB_PUT_HI NV_PPBDMA_PUT_HI(i) + NV_RAMFC_PB_TOP_LEVEL_GET NV_PPBDMA_TOP_LEVEL_GET(i) + NV_RAMFC_PB_TOP_LEVEL_GET_HI NV_PPBDMA_TOP_LEVEL_GET_HI(i) + NV_RAMFC_GP_CRC NV_PPBDMA_GP_CRC(i) + NV_RAMFC_PB_HEADER NV_PPBDMA_PB_HEADER(i) + NV_RAMFC_PB_COUNT NV_PPBDMA_PB_COUNT(i) + NV_RAMFC_PB_CRC NV_PPBDMA_PB_CRC(i) + NV_RAMFC_SUBDEVICE NV_PPBDMA_SUBDEVICE(i) + NV_RAMFC_METHOD0 NV_PPBDMA_METHOD0(i) + NV_RAMFC_METHOD1 NV_PPBDMA_METHOD1(i) + NV_RAMFC_METHOD2 NV_PPBDMA_METHOD2(i) + NV_RAMFC_METHOD3 NV_PPBDMA_METHOD3(i) + NV_RAMFC_DATA0 NV_PPBDMA_DATA0(i) + NV_RAMFC_DATA1 NV_PPBDMA_DATA1(i) + NV_RAMFC_DATA2 NV_PPBDMA_DATA2(i) + NV_RAMFC_DATA3 NV_PPBDMA_DATA3(i) + NV_RAMFC_TARGET NV_PPBDMA_TARGET(i) + NV_RAMFC_METHOD_CRC NV_PPBDMA_METHOD_CRC(i) + NV_RAMFC_REF NV_PPBDMA_REF(i) + NV_RAMFC_RUNTIME NV_PPBDMA_RUNTIME(i) + NV_RAMFC_SEM_ADDR_LO NV_PPBDMA_SEM_ADDR_LO(i) + NV_RAMFC_SEM_ADDR_HI NV_PPBDMA_SEM_ADDR_HI(i) + NV_RAMFC_SEM_PAYLOAD_LO NV_PPBDMA_SEM_PAYLOAD_LO(i) + NV_RAMFC_SEM_PAYLOAD_HI NV_PPBDMA_SEM_PAYLOAD_HI(i) + NV_RAMFC_SEM_EXECUTE NV_PPBDMA_SEM_EXECUTE(i) + NV_RAMFC_ACQUIRE_DEADLINE NV_PPBDMA_ACQUIRE_DEADLINE(i) + NV_RAMFC_ACQUIRE NV_PPBDMA_ACQUIRE(i) + NV_RAMFC_MEM_OP_A NV_PPBDMA_MEM_OP_A(i) + NV_RAMFC_MEM_OP_B NV_PPBDMA_MEM_OP_B(i) + NV_RAMFC_MEM_OP_C NV_PPBDMA_MEM_OP_C(i) + NV_RAMFC_USERD NV_PPBDMA_USERD(i) + NV_RAMFC_USERD_HI NV_PPBDMA_USERD_HI(i) + NV_RAMFC_HCE_CTRL NV_PPBDMA_HCE_CTRL(i) + NV_RAMFC_CONFIG NV_PPBDMA_CONFIG(i) + NV_RAMFC_SET_CHANNEL_INFO NV_PPBDMA_SET_CHANNEL_INFO(i) + ------------------------------- ---------------------------------- + +#define NV_RAMFC /* ----G */ +#define NV_RAMFC_GP_PUT (0*32+31):(0*32+0) /* RWXUF */ +#define NV_RAMFC_MEM_OP_A (1*32+31):(1*32+0) /* RWXUF */ +#define NV_RAMFC_USERD (2*32+31):(2*32+0) /* RWXUF */ +#define NV_RAMFC_USERD_HI (3*32+31):(3*32+0) /* RWXUF */ +#define NV_RAMFC_SIGNATURE (4*32+31):(4*32+0) /* RWXUF */ +#define NV_RAMFC_GP_GET (5*32+31):(5*32+0) /* RWXUF */ +#define NV_RAMFC_PB_GET (6*32+31):(6*32+0) /* RWXUF */ +#define NV_RAMFC_PB_GET_HI (7*32+31):(7*32+0) /* RWXUF */ +#define NV_RAMFC_PB_TOP_LEVEL_GET (8*32+31):(8*32+0) /* RWXUF */ +#define NV_RAMFC_PB_TOP_LEVEL_GET_HI (9*32+31):(9*32+0) /* RWXUF */ +#define NV_RAMFC_REF (10*32+31):(10*32+0) /* RWXUF */ +#define NV_RAMFC_RUNTIME (11*32+31):(11*32+0) /* RWXUF */ +#define NV_RAMFC_ACQUIRE (12*32+31):(12*32+0) /* RWXUF */ +#define NV_RAMFC_ACQUIRE_DEADLINE (13*32+31):(13*32+0) /* RWXUF */ +#define NV_RAMFC_SEM_ADDR_HI (14*32+31):(14*32+0) /* RWXUF */ +#define NV_RAMFC_SEM_ADDR_LO (15*32+31):(15*32+0) /* RWXUF */ +#define NV_RAMFC_SEM_PAYLOAD_LO (16*32+31):(16*32+0) /* RWXUF */ +#define NV_RAMFC_SEM_EXECUTE (17*32+31):(17*32+0) /* RWXUF */ +#define NV_RAMFC_GP_BASE (18*32+31):(18*32+0) /* RWXUF */ +#define NV_RAMFC_GP_BASE_HI (19*32+31):(19*32+0) /* RWXUF */ +#define NV_RAMFC_GP_FETCH (20*32+31):(20*32+0) /* RWXUF */ +#define NV_RAMFC_PB_FETCH (21*32+31):(21*32+0) /* RWXUF */ +#define NV_RAMFC_PB_FETCH_HI (22*32+31):(22*32+0) /* RWXUF */ +#define NV_RAMFC_PB_PUT (23*32+31):(23*32+0) /* RWXUF */ +#define NV_RAMFC_PB_PUT_HI (24*32+31):(24*32+0) /* RWXUF */ +#define NV_RAMFC_MEM_OP_B (25*32+31):(25*32+0) /* RWXUF */ +#define NV_RAMFC_RESERVED26 (26*32+31):(26*32+0) /* RWXUF */ +#define NV_RAMFC_RESERVED27 (27*32+31):(27*32+0) /* RWXUF */ +#define NV_RAMFC_RESERVED28 (28*32+31):(28*32+0) /* RWXUF */ +#define NV_RAMFC_GP_CRC (29*32+31):(29*32+0) /* RWXUF */ +#define NV_RAMFC_PB_HEADER (33*32+31):(33*32+0) /* RWXUF */ +#define NV_RAMFC_PB_COUNT (34*32+31):(34*32+0) /* RWXUF */ +#define NV_RAMFC_SUBDEVICE (37*32+31):(37*32+0) /* RWXUF */ +#define NV_RAMFC_PB_CRC (38*32+31):(38*32+0) /* RWXUF */ +#define NV_RAMFC_SEM_PAYLOAD_HI (39*32+31):(39*32+0) /* RWXUF */ +#define NV_RAMFC_MEM_OP_C (40*32+31):(40*32+0) /* RWXUF */ +#define NV_RAMFC_RESERVED20 (41*32+31):(41*32+0) /* RWXUF */ +#define NV_RAMFC_RESERVED21 (42*32+31):(42*32+0) /* RWXUF */ +#define NV_RAMFC_TARGET (43*32+31):(43*32+0) /* RWXUF */ +#define NV_RAMFC_METHOD_CRC (44*32+31):(44*32+0) /* RWXUF */ +#define NV_RAMFC_METHOD0 (48*32+31):(48*32+0) /* RWXUF */ +#define NV_RAMFC_DATA0 (49*32+31):(49*32+0) /* RWXUF */ +#define NV_RAMFC_METHOD1 (50*32+31):(50*32+0) /* RWXUF */ +#define NV_RAMFC_DATA1 (51*32+31):(51*32+0) /* RWXUF */ +#define NV_RAMFC_METHOD2 (52*32+31):(52*32+0) /* RWXUF */ +#define NV_RAMFC_DATA2 (53*32+31):(53*32+0) /* RWXUF */ +#define NV_RAMFC_METHOD3 (54*32+31):(54*32+0) /* RWXUF */ +#define NV_RAMFC_DATA3 (55*32+31):(55*32+0) /* RWXUF */ +#define NV_RAMFC_HCE_CTRL (57*32+31):(57*32+0) /* RWXUF */ +#define NV_RAMFC_CONFIG (61*32+31):(61*32+0) /* RWXUF */ +#define NV_RAMFC_SET_CHANNEL_INFO (63*32+31):(63*32+0) /* RWXUF */ + +#define NV_RAMFC_BASE_SHIFT 12 /* */ + + Size of the full range of RAMFC in bytes. +#define NV_RAMFC_SIZE_VAL 0x00000200 /* ----C */ + +4 - USER-DRIVER ACCESSIBLE RAM (RAMUSERD) +========================================= + + A user-level driver is allowed to access only a small portion of a GPU +context's state. The portion of a GPU context's state that a user-level driver +can access is stored in a block of memory called NV_RAMUSERD. NV_RAMUSERD is a +user-level driver's window into NV_RAMFC. The NV_RAMUSERD state for each GPU +context is stored in an aligned NV_RAMUSERD_CHAN_SIZE-byte block of memory. + + To submit more methods, a user driver writes a PB segment to +memory, writes a GP entry that points to the PB segment, updates GP_PUT in +RAMUSERD, and writes the channel's handle to the +NV_USERMODE_NOTIFY_CHANNEL_PENDING register (see dev_usermode.ref). + + The RAMUSERD data structure is updated at regular intervals as controlled +by the NV_PFIFO_USERD_WRITEBACK setting (see dev_fifo.ref). For a particular +channel, RAMUSERD writeback can be disabled and it is reccomended that SW track +pushbuffer and channel progress via Host WFI_DIS semaphores rather than reading +the RAMUSERD data structure. + + When write-back is enabled a user driver can check the GPU progress in +executing a channel's PB segments. The driver can use: + * GP_GET to monitor the index of the next GP entry the GPU will process + * PB_GET to monitor the address of the next PB entry the GPU will process + * TOP_LEVEL_GET (see NV_PPBDMA_TOP_LEVEL_GET) to monitor the address of the + next "top-level" (non-SUBROUTINE) PB entry the GPU will process + * REF to monitor the current "reference count" value see NV_PPBDMA_REF. + + Each entry in RAMUSERD corresponds to a PRI-accessible PBDMA register in Host. +For a description of the behavior and contents of a RAMUSERD entry, please see +the description of the corresponding register in "manuals/dev_pbdma.ref". + + RAMUSERD Entry PBDMA Register Access + ------------------------------- ----------------------------- ---------- + NV_RAMUSERD_GP_PUT NV_PPBDMA_GP_PUT(i) Read/Write + NV_RAMUSERD_GP_GET NV_PPBDMA_GP_GET(i) Read-only + NV_RAMUSERD_GET NV_PPBDMA_GET(i) Read-only + NV_RAMUSERD_GET_HI NV_PPBDMA_GET_HI(i) Read-only + NV_RAMUSERD_PUT NV_PPBDMA_PUT(i) Read-only + NV_RAMUSERD_PUT_HI NV_PPBDMA_PUT_HI(i) Read-only + NV_RAMUSERD_TOP_LEVEL_GET NV_PPBDMA_TOP_LEVEL_GET(i) Read-only + NV_RAMUSERD_TOP_LEVEL_GET_HI NV_PPBDMA_TOP_LEVEL_GET_HI(i) Read-only + NV_RAMUSERD_REF NV_PPBDMA_REF(i) Read-only + ------------------------------- ----------------------------- ---------- + + A user driver may write to NV_RAMUSERD_GP_PUT to kick off more work in a +channel. Although writes to the other, read-only, entries can alter memory, +writes to those entries will not affect the operation of the GPU, and can be +overwritten by the GPU. + + When Host loads its part of a GPU context's state from RAMFC memory, it +may not immediately read RAMUSERD_GP_PUT. Host can use the GP_PUT values from +RAMFC directly from RAMFC while waiting for the RAMUSERD_GP_PUT to synchronize. +Because reads of RAMUSERD_GP_PUT can be delayed, the value in NV_PPBDMA_GP_PUT +can be older than the value in NV_RAMUSERD_GP_PUT. + + When Host saves a GPU context's state to NV_RAMFC, it also writes to +NV_RAMUSERD the values of the entries other than GP_PUT. +Because Host does not continuously write the read-only RAMFC entries, the +read-only values in USERD memory can be older than the values in the Host PBDMA +unit. + +#define NV_RAMUSERD /* ----G */ +#define NV_RAMUSERD_PUT (16*32+31):(16*32+0) /* RWXUF */ +#define NV_RAMUSERD_GET (17*32+31):(17*32+0) /* RWXUF */ +#define NV_RAMUSERD_REF (18*32+31):(18*32+0) /* RWXUF */ +#define NV_RAMUSERD_PUT_HI (19*32+31):(19*32+0) /* RWXUF */ +#define NV_RAMUSERD_TOP_LEVEL_GET (22*32+31):(22*32+0) /* RWXUF */ +#define NV_RAMUSERD_TOP_LEVEL_GET_HI (23*32+31):(23*32+0) /* RWXUF */ +#define NV_RAMUSERD_GET_HI (24*32+31):(24*32+0) /* RWXUF */ +#define NV_RAMUSERD_GP_GET (34*32+31):(34*32+0) /* RWXUF */ +#define NV_RAMUSERD_GP_PUT (35*32+31):(35*32+0) /* RWXUF */ +#define NV_RAMUSERD_BASE_SHIFT 9 /* */ +#define NV_RAMUSERD_CHAN_SIZE 512 /* */ + + + + +5 - RUN-LIST RAM (RAMRL) +======================== + + Software specifies the GPU contexts that hardware should "run" by writing a +list of entries (known as a "runlist") to a 4k-aligned area of memory (beginning +at NV_PFIFO_RUNLIST_BASE), and by notifying Host that a new list is available +(by writing to NV_PFIFO_RUNLIST). + Submission of a new runlist causes Host to expire the timeslice of all work +scheduled by the previous runlist, allowing it to schedule the channels present +in the new runlist once they are fetched. SW can check the status of the runlist +by polling NV_PFIFO_ENG_RUNLIST_PENDING. (see dev_fifo.ref NV_PFIFO_RUNLIST for +a full description of the runlist submit mechanism). + Runlists can be stored in system memory or video memory (as specified by +NV_PFIFO_RUNLIST_BASE_TARGET). If a runlist is stored in video memory, software +will have to execute flush or read the last entry written before submitting the +runlist to Host to guarantee coherency . + The size of a runlist entry data structure is 16 bytes. Each entry +specifies either a channel entry or a TSG header; the type is determined by the +NV_RAMRL_ENTRY_TYPE. + + +Runlist Channel Entry Type: + + A runlist entry of type NV_RAMRL_ENTRY_TYPE_CHAN specifies a channel to +run. All such entries must occur within the span of some TSG as specified by +the NV_RAMRL_ENTRY_TYPE_TSG described below. If a channel entry is encountered +outside a TSG, Host will raise the NV_PFIFO_INTR_SCHED_ERROR_CODE_BAD_TSG +interrupt. + + The fields available in a channel runlist entry are as follows (Fig 5.1): + + ENTRY_TYPE (T) : type of this entry: ENTRY_TYPE_CHAN + CHID (ID) : identifier of the channel to run (overlays ENTRY_ID) + RUNQUEUE_SELECTOR (Q) : selects which PBDMA should run this channel if + more than one PBDMA is supported by the runlist + + INST_PTR_LO : lower 20 bits of the 4k-aligned instance block pointer + INST_PTR_HI : upper 32 bit of instance block pointer + INST_TARGET (TGI) : aperture of the instance block + + USERD_PTR_LO : upper 24 bits of the low 32 bits, of the 512-byte-aligned USERD pointer + USERD_PTR_HI : upper 32 bits of USERD pointer + USERD_TARGET (TGU) : aperture of the USERD data structure + + CHID is a channel identifier that uniquely specifies the channel described +by this runlist entry to the scheduling hardware and is reported in various +status registers. + RUNQUEUE_SELECTOR determines to which runqueue the channel belongs, and +thereby which PBDMA will run the channel. Increasing values select increasingly +numbered PBDMA IDs serving the runlist. If the selector value exceeds the +number of PBDMAs on the runlist, the hardware will silently reassign the channel +to run on the first PBDMA as though RUNQUEUE_SELECTOR had been set to 0. (In +current hardware, this is used by SCG on the graphics runlist only to determine +which FE pipe should service a given channel. A value of 0 targets the first FE +pipe, which can process all FE driven engines: Graphics, Compute, Inline2Memory, +and TwoD. A value of 1 targets the second FE pipe, which can only process +Compute work. Note that GRCE work is allowed on either runqueue.) + The INST fields specify the physical address of the channel's instance +block, the in-memory data structure that stores the context state. +The target aperture of the instance block is given by INST_TARGET, and the byte +offset within that aperture is calculated as + + (INST_PTR_HI << 32) | (INST_PTR_LO << NV_RAMRL_ENTRY_CHAN_INST_PTR_ALIGN_SHIFT) + +This address should match the one specified in the channel RAM's +NV_PCCSR_CHANNEL_INST register; see NV_RAMIN and NV_RAMFC for the format of the +instance block. The hardware ignores the RAMRL INST fields, but in future +chips the instance pointer may be removed from the channel RAM and the RAMRL +INST fields used instead, resulting in smaller hardware. + The USERD fields specify the physical address of the USERD memory region +used by software to submit additional work to the channel. The target aperture +of the USERD region is given by USERD_TARGET, and the byte offset within that +aperture is calculated as + + (USERD_PTR_HI << 32) | (USERD_PTR_LO << NV_RAMRL_ENTRY_CHAN_USERD_PTR_ALIGN_SHIFT) + + +SW uses the NV_RAMUSERD_CHAN_SIZE define to allocate and align a channel's +RAMUSERD data structure. See the documentation for NV_RAMUSERD for a +description of the use of USERD and its format. This address and it's +alignment must match the one specified in the RAMFC's NV_RAMFC_USERD and +NV_RAMFC_USERD_HI fields which are backed by NV_PPBDMA_USERD in dev_pbdma.ref. +The hardware ignores the RAMRL USERD fields, but in future chips the USERD +pointer may be read from these fields in the runlist entry instead of the RAMFC +to avoid the extra level of indirection in fetching the USERD data that +currently results in a dependent read. + + +Runlist TSG Entry Type: + + The other type of runlist entry is Timeslice Group (TSG) header entry +(Fig 5.2). This type of entry is specified by NV_RAMRL_ENTRY_TYPE_TSG. A TSG +entry describes a collection of channels all of which share the same context and +are scheduled as a single unit by Host. All runlists support this type of entry. + + The fields available in a TSG header runlist entry are as follows (Fig 5.2): + + ENTRY_TYPE (T) : type of this entry: ENTRY_TYPE_TSG + TSGID : identifier of the Timeslice group (overlays ENTRY_ID) + TSG_LENGTH : number of channels that are part of this timeslice group + TIMESLICE_SCALE : scale factor for the TSG's timeslice + TIMESLICE_TIMEOUT : timeout amount for the TSG's timeslice + + A timeslice group entry consists of an integer identifier along with a +length which specifies the number of channels in the TSG. After a TSG header +runlist entry, the next TSG_LENGTH runlist entries are considered to be part of +the timeslice group. Note that the minimum length of a TSG is at least one entry. + All channels in a TSG share the same runlist timeslice which specifies how +long a single context runs on an engine or PBDMA before being swapped for a +different context. The timeslice period is set in the TSG header by specifying +TSG_TIMESLICE_TIMEOUT and TSG_TIMESLICE_SCALE. The TSG timeslice period is +calculated as follows: + + timeslice = (TSG_TIMESLICE_TIMEOUT << TSG_TIMESLICE_SCALE) * 1024 nanoseconds + + The timeslice period should normally not be set to zero. A timeslice of +zero will be treated as a timeslice period of one . The runlist +timeslice period begins after the context has been loaded on a PBDMA but is +paused while the channel has an outstanding context load to an engine. Time +spent switching a context into an engine is not part of the runlist timeslice. + + If Host reaches the end of the runlist or receives another entry of type +NV_RAMRL_ENTRY_TYPE_TSG before processing TSG_LENGTH additional runlist entries, +or if it encounters a TSG of length 0, a SCHED_ERROR interrupt will be generated +with ERROR_CODE_BAD_TSG. + + +Host Scheduling Memory Layout: + +Example of graphics runlist entry to GPU context mapping via channel id: + + + .------Ints_ptr -------. + | | + Graphics Runlist | Channel-Map RAM | GPU Instance Block + .------------ . | .----------------. | .-------------------. + | TSG Hdr L=m |--.----' |Ch0 Inst Blk Ptr|--'------->| Host State | + | RL Entry T1 | | |Ch1 Inst Blk Ptr| .------| Memory State | + | RL Entry T2 | | | ... | | | Engine0 State Ptr | + | ... | |-chid->|ChI Inst Blk Ptr| | | Engine1 State Ptr | + | RL Entry Tm | | | ... | | | ... | + | TSG Hdr L=n | | |ChN Inst Blk Ptr| | .-| EngineN State Ptr | + | RL Entry T1 | | `----------------' | | `-------------------' + | RL Entry T2 |userd_ptr | | + | ... | | .--------------. | | .--------------. + | RL Entry Tn | | | USERD | | | | Engine Ctx | + | | '------->| |<----' '-->| State N | + `-------------' | | | | + `--------------' `--------------' + +Runlist Diagram Description: + Here we have (M+N) number of channel type (ENTRY_TYPE_CHID) runlist entries +grouped together within two TSGs. The first entry in the runlist is a TSG header +entry (ENTRY_TYPE_TSG) that describes the first TSG. The TSG header specifies m +as the length of the TSG. The header would also contain the timeslice +information for the TSG (SCALE/TIMEOUT), as well as the TSG id specified in the +TSGID field. + Because the length here is M, the Runlist *must* contain M additional +runlist entries of type ENTRY_TYPE_CHAN that will be part of this TSG. +Similarly, the next (N+1) number of entries, a TSG header entry followed by N +number of regular channel entry, correspond to the second TSG. + +#define NV_RAMRL_ENTRY /* ----G */ +#define NV_RAMRL_ENTRY_RANGE 0xF:0x00000000 /* RW--M */ +#define NV_RAMRL_ENTRY_SIZE 16 /* */ +// Runlist base must be 4k-aligned. +#define NV_RAMRL_ENTRY_BASE_SHIFT 12 /* */ + + +#define NV_RAMRL_ENTRY_TYPE (0+0*32):(0+0*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_TYPE_CHAN 0x00000000 /* RW--V */ +#define NV_RAMRL_ENTRY_TYPE_TSG 0x00000001 /* RW--V */ + +#define NV_RAMRL_ENTRY_ID (11+2*32):(0+2*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_ID_HW 11:0 /* RWXUF */ +#define NV_RAMRL_ENTRY_ID_MAX (4096-1) /* RW--V */ + + + + + +#define NV_RAMRL_ENTRY_CHAN_RUNQUEUE_SELECTOR (1+0*32):(1+0*32) /* RWXUF */ + +#define NV_RAMRL_ENTRY_CHAN_INST_TARGET (5+0*32):(4+0*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_VID_MEM 0x00000000 /* RW--V */ +#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_RAMRL_ENTRY_CHAN_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ + +#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET (7+0*32):(6+0*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_VID_MEM 0x00000000 /* RW--V */ +#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_VID_MEM_NVLINK_COHERENT 0x00000001 /* RW--V */ +#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */ +#define NV_RAMRL_ENTRY_CHAN_USERD_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ + +#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_LO (31+0*32):(8+0*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_HI (31+1*32):(0+1*32) /* RWXUF */ + +#define NV_RAMRL_ENTRY_CHAN_CHID (11+2*32):(0+2*32) /* RWXUF */ + +#define NV_RAMRL_ENTRY_CHAN_INST_PTR_LO (31+2*32):(12+2*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_CHAN_INST_PTR_HI (31+3*32):(0+3*32) /* RWXUF */ + + + +// Macros for shifting out low bits of INST_PTR and USERD_PTR. +#define NV_RAMRL_ENTRY_CHAN_INST_PTR_ALIGN_SHIFT 12 /* ----C */ +#define NV_RAMRL_ENTRY_CHAN_USERD_PTR_ALIGN_SHIFT 8 /* ----C */ + + + + + + + +#define NV_RAMRL_ENTRY_TSG_TIMESLICE_SCALE (19+0*32):(16+0*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_TSG_TIMESLICE_SCALE_3 0x00000003 /* RWI-V */ +#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT (31+0*32):(24+0*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT_128 0x00000080 /* RWI-V */ + + +#define NV_RAMRL_ENTRY_TSG_TIMESLICE_TIMEOUT_1US 0x00000000 /* */ + +#define NV_RAMRL_ENTRY_TSG_LENGTH (7+1*32):(0+1*32) /* RWXUF */ +#define NV_RAMRL_ENTRY_TSG_LENGTH_INIT 0x00000000 /* RW--V */ +#define NV_RAMRL_ENTRY_TSG_LENGTH_MIN 0x00000001 /* RW--V */ +#define NV_RAMRL_ENTRY_TSG_LENGTH_MAX 0x00000080 /* RW--V */ + +#define NV_RAMRL_ENTRY_TSG_TSGID (11+2*32):(0+2*32) /* RWXUF */ + + + +6 - Host Pushbuffer Format (FIFO_DMA) +======================================= + + "FIFO" refers to Host. "FIFO_DMA" means data that Host reads from memory: +the pushbuffer. Host autonomously reads pushbuffer data from memory and +generates method address/data pairs from the data. + + Pushbuffer terminology: + + - A channel is the logical sequence of instructions associated with a GPU + context. + + - The pushbuffer is a stream of data in memory containing the + specifications of the operations that a channel is to perform for a + particular client. Pushbuffer data consists of pushbuffer entries. + + - A pushbuffer entry (PB entry) is a 32-bit (doubleword) sized unit of + pushbuffer data. This is the smallest granularity at which Host consumes + pushbuffer data. A PB entry is either a PB instruction (which is either + a PB control entry or a PB method header), or a method data entry. + + - A pushbuffer segment (PB segment) is a contiguous block of memory + containing pushbuffer entries. The location and size of a pushbuffer + segment is defined by its respective GP entry in the GPFIFO. + + - A pushbuffer control entry (PB control entry) is a single PB entry of + type SET_SUBDEVICE_MASK, STORE_SUBDEVICE_MASK, USE_SUBDEVICE_MASK, + END_PB_SEGMENT, or a universal NOP (NV_FIFO_DMA_NOP). + + - A pushbuffer compressed method sequence is a sequence of pushbuffer + entries starting with a method header and a variable-length sequence of + method data entries (the length being defined by the method header). A + single PB compressed method sequence expands into one or more methods. + This may also be known as a "pushbuffer method" (PB method), but that + terminology is ambiguous and not preferred. + + - A pushbuffer method header (PB method header) is the first PB entry found + in a PB compressed method sequence. A PB method header is a PB + instruction performed on method data entries. + + - A pushbuffer instruction (PB instruction) is a PB entry that is not a PB + method data entry. A PB instruction is either a PB control entry or a PB + method header. + + - A method is an address/data pair representing an operation to perform. + + - A method data entry is the 32-bit operand for its corresponding method. + + + +#define NV_FIFO_PB_ENTRY_SIZE 4 /* */ + + + Some engines such as Graphics internally support a double-wide method FIFO; +these are known as "data-hi" methods. It is Host that performs the packing of +two methods into one double-wide entry. Host will only generate data-hi methods +if the following conditions are satisfied: + + 1. The two methods come from the same PB method (in other words they share + the same method header). + + 2. The method header specifies a non-incrementing method, an incrementing + method, or an increment-once method. + + 3. The paired methods either have the same method address, or the first + method has an even NV_FIFO_DMA_METHOD_ADDRESS field and the second + (data-hi) method is the increment of the first. (That is, the + left-shifted method address as listed in the class files must be + divisible by 8 for this condition to hold.) + + 4. The second method is available at the time of pushing the first one into + the engine's method FIFO. In other words, Host will not wait to pack + methods. Note that if the engine's method fifo is full, the + back-pressure will in itself create a "wait time". + +The first three conditions are under SW's control. Only the graphics engine +supports data-hi methods. + + +Types of PB Entries + + PB entries can be classified into three types: PB method headers, PB +control entries, and PB method data. Different types of PB entries have +different formats. Because PB compressed method sequences are of variable +length, it is impossible to determine the type of a PB entry without tracking +the pushbuffer from the beginning or from the location of a PB entry that is +known to not be a PB method data entry. + + A PB method data entry is always found in a method data sequence +immediately following a PB method header in the logical stream of PB entries. +The PB method header contains a NV_FIFO_DMA_METHOD_COUNT field, the value of +which is equal to the length of the method data sequence. Note a PB method +header does not necessarily come with PB method data entries (see details below +about immediate-data method headers and method headers for which COUNT is zero). +Also note the PB method data entries may be located in a PB segment separate +from their corresponding method header. The format of any given PB method data +entry is defined in the "NV_UDMA" section of dev_pbdma.ref. + + A PB entry that is either a PB method header or PB control entry is known +as a PB instruction. The type of a PB instruction is specified by the +NV_FIFO_DMA_SEC_OP field and the NV_FIFO_DMA_TERT_OP field. + + secondary tertiary + opcode opcode entry type + --------- -------- -------------------------------- + 000 01 SET_SUBDEVICE_MASK + 000 10 STORE_SUBDEVICE_MASK + 000 11 USE_SUBDEVICE_MASK + 001 xx incrementing method header + 011 xx non-incrementing method header + 100 xx immediate-data method header + 101 xx increment-once method header + 111 xx END_PB_SEGMENT + --------- -------- -------------------------------- + + Types of methods: + + - A Host method is a method whose address is defined in the NV_UDMA device + range. + + - A Host-only method is any Host method excluding SetObject (also known as + NV_UDMA_OBJECT). + + - An engine method is a method whose address is not defined within the + NV_UDMA device range. There are multiple engines designated by a + subchannel ID. Software methods are included in this category. + + - A software method (SW method) is a method which causes an interrupt for + the express purpose of being handled by software. For details see the + section on software methods below. + + For more information about types of methods see "HOST METHODS" and +"RESERVED METHOD ADDRESSES" in dev_pbdma.ref. + + The method address in a PB method header (stored in the +NV_FIFO_DMA_METHOD_ADDRESS field) is a dword-address, not a byte-address. In +other words the least significant two bits of the address are not stored because +the byte-address is dword-aligned (thus the least significant two bits are +always zero). + + The subchannel in a PB method header (stored in the +NV_FIFO_DMA_*_SUBCHANNEL field) determines the engine to which a method will be +sent if the method is SetObject or an engine method (otherwise, the SUBCHANNEL +field is ignored). SetObject enables SW to request HW to check the expectation +that a given subchannel serves the specified class ID; see the description of +"NV_UDMA_OBJECT" in dev_pbdma.ref. + + The mapping between subchannels and engines is fixed. A subchannel is +bound to a given class according to the runlist. Each engine method is applied +to an "object," which itself is an instance of an NV class as defined by the +master MFS class files. Each object belongs to an engine. For SetObject and +engine methods, the engine is determined entirely by the SUBCHANNEL field of +the method's header via a fixed mapping that depends on the runlist on which the +method arrives. + + Methods on subchannels 0-4 are handled by the primary engine served by the +runlist, except that subchannel 4 targets GRCOPY0 and GRCOPY1 on the graphics +runlist. For Graphics/Compute, SetObject associates subchannels 0, 1, 2, and 3 +with class identifiers for 3D, compute, I2M, and 2D respectively. On other +runlists, the subchannel is ignored, and Host does not send the subchannel ID to +the engine. It is recommended that SW only use subchannel 4 on the dedicated +copy engines for consistency with GRCOPY usage. + + Subchannels 5-7 are for software methods. Any methods on these subchannels +(including SetObject methods) are kicked back to software for handling via the +SW method dispatch mechanism using the NV_PPBDMA_INTR_*_DEVICE interrupt. SW +may choose to send a SetObject method to each engine subchannel before sending +any methods on that particular subchannel in order to support multiple software +classes. + + If a method stream subchannel-switches from targeting graphics/compute to a +copy engine or vice-versa, that is, to or from subchannel 4 on GR, Host will: + + 1. Wait until the first engine has completed all its methods, + + 2. Wait until that engine indicates that it is idle (WFI), and + + 3. Send a sysmem barrier flush and wait until it completes. + +Only then will Host send methods to the newly targeted engine. + + Note that this WFI will not occur for sending Host-only methods on the new +subchannel, since Host-only methods ignore the subchannel field. Additionally, +when switching from CE to graphics/compute, Host forces FE to perform a cache +invalidate. Other subchannel switch semantics may be provided by the engines +themselves, such as switching between subchannels 0-3 within FE. + + +#define NV_FIFO_DMA /* ----G */ +#define NV_FIFO_DMA_METHOD_ADDRESS_OLD 12:2 /* RWXUF */ +#define NV_FIFO_DMA_METHOD_ADDRESS 11:0 /* RWXUF */ + +#define NV_FIFO_DMA_SUBDEVICE_MASK 15:4 /* RWXUF */ + +#define NV_FIFO_DMA_METHOD_SUBCHANNEL 15:13 /* RWXUF */ + +#define NV_FIFO_DMA_TERT_OP 17:16 /* RWXUF */ +#define NV_FIFO_DMA_TERT_OP_GRP0_SET_SUB_DEV_MASK 0x00000001 /* RW--V */ +#define NV_FIFO_DMA_TERT_OP_GRP0_STORE_SUB_DEV_MASK 0x00000002 /* RW--V */ +#define NV_FIFO_DMA_TERT_OP_GRP0_USE_SUB_DEV_MASK 0x00000003 /* RW--V */ + +#define NV_FIFO_DMA_METHOD_COUNT_OLD 28:18 /* RWXUF */ +#define NV_FIFO_DMA_METHOD_COUNT 28:16 /* RWXUF */ +#define NV_FIFO_DMA_IMMD_DATA 28:16 /* RWXUF */ + +#define NV_FIFO_DMA_SEC_OP 31:29 /* RWXUF */ +#define NV_FIFO_DMA_SEC_OP_GRP0_USE_TERT 0x00000000 /* RW--V */ +#define NV_FIFO_DMA_SEC_OP_INC_METHOD 0x00000001 /* RW--V */ +#define NV_FIFO_DMA_SEC_OP_NON_INC_METHOD 0x00000003 /* RW--V */ +#define NV_FIFO_DMA_SEC_OP_IMMD_DATA_METHOD 0x00000004 /* RW--V */ +#define NV_FIFO_DMA_SEC_OP_ONE_INC 0x00000005 /* RW--V */ +#define NV_FIFO_DMA_SEC_OP_RESERVED6 0x00000006 /* RW--V */ +#define NV_FIFO_DMA_SEC_OP_END_PB_SEGMENT 0x00000007 /* RW--V */ + + +Incrementing PB Method Header Format + + An incrementing PB method header specifies that Host generate a sequence of +methods. The length of the sequence is defined by the method header. The +method data for each method in this sequence is found in a sequence of PB +entries immediately following the method header. + + The dword-address of the first method is specified by the method header, +and the dword-address of each subsequent method is equal to the dword-address of +the previous method plus one. Or in other words, the byte-address of each +subsequent method is equal to the byte-address of the previous method plus four. + +Example sequence of methods generated from an incrementing method header: + + addr data0 + addr+1 data1 + addr+2 data2 + addr+3 data3 + ... ... + + The NV_FIFO_DMA_INCR_COUNT field contains the number of methods in the +generated sequence. This is the same as the number of method data entries that +follow the method header. If the COUNT field is zero, the other fields are +ignored, and the PB method effectively becomes a no-op with no method data +entries following it. + + The NV_FIFO_DMA_INCR_SUBCHANNEL field contains the subchannel to use for +the methods generated from the method header. See the documentation above for +NV_FIFO_DMA_*_SUBCHANNEL. + + The NV_FIFO_DMA_INCR_ADDRESS field contains the method address for the +first method in the generated sequence. The dword-address of the method is +incremented by one each time a method is generated. A method address specifies +an operation to be performed. Note that because the ADDRESS is a dword-address +and not a byte-address, the least two significant bits of the method's +byte-address are not stored. + + The NV_FIFO_DMA_INCR_DATA fields contain the method data for the methods in +the generated sequence. The number of method data entries is defined by the +COUNT field. A method data entry contains an operand for its respective method. + + Bit 12 is reserved for the future expansion of either the subchannel or the +address fields. + + +#define NV_FIFO_DMA_INCR /* ----G */ +#define NV_FIFO_DMA_INCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */ +#define NV_FIFO_DMA_INCR_OPCODE_VALUE 0x00000001 /* ----V */ +#define NV_FIFO_DMA_INCR_COUNT (0*32+28):(0*32+16) /* RWXUF */ +#define NV_FIFO_DMA_INCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */ +#define NV_FIFO_DMA_INCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */ +#define NV_FIFO_DMA_INCR_DATA (1*32+31):(1*32+0) /* RWXUF */ + + +Non-Incrementing PB Method Header Format + + A non-incrementing PB method header specifies that Host generate a sequence +of methods. The length of the sequence is defined by the method header. The +method data for each method in this sequence is contained within the PB entries +immediately following the method header. + + Unlike with the incrementing PB method header, the sequence of methods +generated all have the same method address. The dword-address of every method +in this sequence is specified by the method header. Although the methods all +have the same address, the method data entries may be different. + +Example sequence of methods generated from a non-incrementing method header: + + addr data0 + addr data1 + addr data2 + addr data3 + ... ... + + The NV_FIFO_DMA_NONINCR_COUNT field contains the number of methods +in the generated sequence. This is the same as the number of method data +entries that follow the method header. If the COUNT field is zero, the other +fields are ignored, and the PB method effectively becomes a no-op with no method +data entries following it. + + The NV_FIFO_DMA_NONINCR_SUBCHANNEL field contains the subchannel to use for +the methods generated from the method header. See the documentation above for +NV_FIFO_DMA_*_SUBCHANNEL. + + The NV_FIFO_DMA_NONINCR_ADDRESS field contains the method address for every +method in the generated sequence. A method address specifies an operation to be +performed. Note that because the ADDRESS field is a dword-address and not a +byte-address, the least two significant bits of the method's byte-address are +not stored. + + The NV_FIFO_DMA_NONINCR_DATA fields contain the method data for the methods +in the generated sequence. The number of method data entries is defined by the +COUNT field. A method data entry contains an operand for its respective method. + + Bit 12 is reserved for the future expansion of either the subchannel or the +address fields. + + +#define NV_FIFO_DMA_NONINCR /* ----G */ +#define NV_FIFO_DMA_NONINCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */ +#define NV_FIFO_DMA_NONINCR_OPCODE_VALUE 0x00000003 /* ----V */ +#define NV_FIFO_DMA_NONINCR_COUNT (0*32+28):(0*32+16) /* RWXUF */ +#define NV_FIFO_DMA_NONINCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */ +#define NV_FIFO_DMA_NONINCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */ +#define NV_FIFO_DMA_NONINCR_DATA (1*32+31):(1*32+0) /* RWXUF */ + + +Increment-Once PB Method Header Format + + An increment-once PB method header specifies that Host generate a sequence +of methods. The length of the sequence is defined by the method header. The +method data for each method in this sequence is found in a sequence of PB +entries immediately following the method header. + + The dword-address of the first method is specified by the method header. +The address of the second and all following methods is equal to the +dword-address of the first method plus one. In other words, the byte-address of +the second and all following methods is equal to the byte-address of the first +method plus four. + +Example sequence of methods generated from an increment-once method header: + + addr data0 + addr+1 data1 + addr+1 data2 + addr+1 data3 + ... ... + + The NV_FIFO_DMA_ONEINCR_COUNT field contains the number of methods in the +generated sequence. This is the same as the number of method data entries that +follow the method header. If the COUNT field is zero, the other fields are +ignored, and the PB method effectively becomes a no-op method with no method +data entries following it. + + The NV_FIFO_DMA_ONEINCR_SUBCHANNEL field contains the subchannel to use for +the methods generated from the method header. See the documentation above for +NV_FIFO_DMA_*_SUBCHANNEL. + + The NV_FIFO_DMA_ONEINCR_ADDRESS field contains the method address for the +first method in the generated sequence. A method address specifies an operation +to be performed. Note that because the ADDRESS is a dword-address and not a +byte-address, the least two significant bits of the method's byte-address are +not stored. + + The NV_FIFO_DMA_ONEINCR_DATA fields contain the method data for the methods +in the generated sequence. The number of method data entries is defined by the +COUNT field. A method data entry contains an operand for its respective method. + + Bit 12 is reserved for the future expansion of either the subchannel or the +address fields. + + +#define NV_FIFO_DMA_ONEINCR /* ----G */ +#define NV_FIFO_DMA_ONEINCR_OPCODE (0*32+31):(0*32+29) /* RWXUF */ +#define NV_FIFO_DMA_ONEINCR_OPCODE_VALUE 0x00000005 /* ----V */ +#define NV_FIFO_DMA_ONEINCR_COUNT (0*32+28):(0*32+16) /* RWXUF */ +#define NV_FIFO_DMA_ONEINCR_SUBCHANNEL (0*32+15):(0*32+13) /* RWXUF */ +#define NV_FIFO_DMA_ONEINCR_ADDRESS (0*32+11):(0*32+0) /* RWXUF */ +#define NV_FIFO_DMA_ONEINCR_DATA (1*32+31):(1*32+0) /* RWXUF */ + + +No-Operation PB Instruction Formats + + The method header for a no-op PB method may be specified in multiple ways, +but the preferred way is to set the PB instruction to NV_FIFO_DMA_NOP. +In any case NV_FIFO_DMA_NOP is a universal NOP entry that bypasses any method +header format check, and is not considered a method header. + + +#define NV_FIFO_DMA_NOP 0x00000000 /* ----C */ + + +Immediate-Data PB Method Header Format + + If a method's operand fits within 13 bits, a PB method may be specified in +a single PB entry, using the immediate-data PB method header format. Exactly +one method is generated from this method header. + + The NV_FIFO_DMA_IMMD_SUBCHANNEL field contains the subchannel to use for +the method generated from the method header. See the documentation above for +NV_FIFO_DMA_*_SUBCHANNEL. + + The NV_FIFO_DMA_IMMD_ADDRESS field contains the method address for the +single generated method. A method address specifies an operation to be +performed. Note that because the ADDRESS is a dword-address and not a +byte-address, the least two significant bits of the method's byte-address are +not stored. + + The single NV_FIFO_DMA_IMMD_DATA field contains the method data for the +generated method. This method data contains an operand for the generated +method. + + +#define NV_FIFO_DMA_IMMD /* ----G */ +#define NV_FIFO_DMA_IMMD_ADDRESS 11:0 /* RWXUF */ +#define NV_FIFO_DMA_IMMD_SUBCHANNEL 15:13 /* RWXUF */ +#define NV_FIFO_DMA_IMMD_DATA 28:16 /* RWXUF */ +#define NV_FIFO_DMA_IMMD_OPCODE 31:29 /* RWXUF */ +#define NV_FIFO_DMA_IMMD_OPCODE_VALUE 0x00000004 /* ----V */ + + +Set Sub-Device Mask PB Control Entry Format + + The SET_SUBDEVICE_MASK (SSDM) PB control entry is used when multiple GPU +contexts are using the same pushbuffer (for example, for SLI or for stereo +rendering) and there is data in the push buffer that is for only a subset of the +GPU contexts. This instruction allows the pushbuffer to tell a specific GPU +context to use or ignore methods following the SET_SUBDEVICE_MASK. While the +logical-AND of NV_FIFO_DMA_SET_SUBDEVICE_MASK_VALUE and the GPU context's +NV_PPBDMA_SUBDEVICE_ID value is zero, methods are ignored. Pushbuffer control +entries (like SET_SUBDEVICE_MASK) are not ignored. + +******************************************************************************** +Warning: When using subdevice masking, one must take care to synchronize +properly with any later GP entries marked FETCH_CONDITIONAL. If GP fetching +gets too far ahead of PB processing, it is possible for a later conditional PB +segment to be discarded prior to reaching an SSDM command that sets +SUBDEVICE_STATUS to ACTIVE. This would cause Host to execute garbage data. One +way to avoid this would be to set the SYNC_WAIT flag on any FETCH_CONDITIONAL +segments following a subdevice reenable. +******************************************************************************** + + + +#define NV_FIFO_DMA_SET_SUBDEVICE_MASK /* ----G */ +#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_VALUE 15:4 /* RWXUF */ +#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */ +#define NV_FIFO_DMA_SET_SUBDEVICE_MASK_OPCODE_VALUE 0x00000001 /* ----V */ + + +Store Sub-Device Mask PB Control Entry Format + + The STORE_SUBDEVICE_MASK PB control entry is used to save a subdevice mask +value to be used later by a USE_SUBDEVICE_MASK PB instruction. + + +#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK /* ----G */ +#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_VALUE 15:4 /* RWXUF */ +#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */ +#define NV_FIFO_DMA_STORE_SUBDEVICE_MASK_OPCODE_VALUE 0x00000002 /* ----V */ + + +Use Sub-Device Mask PB Control Entry Format + + The USE_SUBDEVICE_MASK PB control entry is used to apply the subdevice mask +value saved by a STORE_SUBDEVICE_MASK PB instruction. The effect of the mask is +the same as for a SET_SUBDEVICE_MASK PB instruction. + + +#define NV_FIFO_DMA_USE_SUBDEVICE_MASK /* ----G */ +#define NV_FIFO_DMA_USE_SUBDEVICE_MASK_OPCODE 31:16 /* RWXUF */ +#define NV_FIFO_DMA_USE_SUBDEVICE_MASK_OPCODE_VALUE 0x00000003 /* ----V */ + + +End-PB-Segment PB Control Entry Format + + Engines may write PB segments themselves, but they cannot write GP entries. +Because they cannot write GP entries, they cannot alter the size of a PB +segment. If an engine is writing a PB segment, and if it does not need to fill +the entire PB segment it was allocated, instead of filling the remainder of the +PB segment with no-op PB instructions, it may write a single End-PB-Segment +control entry to indicate that the pushbuffer data contains no further valid +data. No further PB entries from that PB segment will be decoded or processed. +Host may have already issued requests to fetch the remainder of the PB segment +before an End-PB-Segment PB instruction is processed. Host may or may not fetch +the remainder of the PB segment. Also note that doing a PB CRC check on this +segment via NV_PPBDMA_GP_ENTRY1_OPCODE_PB_CRC will be indeterminate. + + +#define NV_FIFO_DMA_ENDSEG_OPCODE 31:29 /* RWXUF */ +#define NV_FIFO_DMA_ENDSEG_OPCODE_VALUE 0x00000007 /* ----V */ + + diff --git a/Host-Fifo/volta/gv100/dev_timer.ref.txt b/Host-Fifo/volta/gv100/dev_timer.ref.txt new file mode 100644 index 0000000..3f56b3b --- /dev/null +++ b/Host-Fifo/volta/gv100/dev_timer.ref.txt @@ -0,0 +1,79 @@ +Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + +#define NV_PTIMER_PRI_TIMEOUT 0x00009080 /* RW-4R */ +#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 /* RWIVF */ +#define NV_PTIMER_PRI_TIMEOUT_PERIOD_MIN 0x00000003 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_PERIOD_MAX 0x00ffffff /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_PERIOD_RTL 0x0000000a /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_PERIOD_SHORT 0x00000006 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_PERIOD_INIT 0x00000100 /* RWI-V */ +#define NV_PTIMER_PRI_TIMEOUT_PERIOD__PROD 0x00002000 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 /* RWIVF */ +#define NV_PTIMER_PRI_TIMEOUT_EN_DISABLED 0x00000000 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_EN_ENABLED 0x00000001 /* RWI-V */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x00009084 /* RW-4R */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO 0:0 /* RWXVF */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_ERROR 0x1 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_CLEAR 0x0 /* -W--V */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_NONE 0x0 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE 1:1 /* RWXVF */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE_TRUE 0x1 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE_FALSE 0x0 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_ADDR 23:2 /* RWXVF */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT 31:31 /* RWXVF */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT_TRUE 0x1 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT_FALSE 0x0 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x00009088 /* RW-4R */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1_DATA 31:0 /* RWXVF */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_1_DATA_WAS_READ 0x0 /* RW--V */ +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x0000908C /* RW-4R */ +#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE_DATA 31:0 /* RWXVF */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_3 0x00009090 /* RW-4R */ +#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID 3:0 /* R-XVF */ +#define NV_PTIMER_INTR_0 0x00009100 /* RW-4R */ +#define NV_PTIMER_INTR_0_ALARM 0:0 /* RWXVF */ +#define NV_PTIMER_INTR_0_ALARM_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PTIMER_INTR_0_ALARM_PENDING 0x00000001 /* R---V */ +#define NV_PTIMER_INTR_0_ALARM_RESET 0x00000001 /* -W--C */ +#define NV_PTIMER_INTR_0_TIMER 1:1 /* RWXVF */ +#define NV_PTIMER_INTR_0_TIMER_NOT_PENDING 0x00000000 /* R---V */ +#define NV_PTIMER_INTR_0_TIMER_PENDING 0x00000001 /* R---V */ +#define NV_PTIMER_INTR_0_TIMER_RESET 0x00000001 /* -W--C */ +#define NV_PTIMER_INTR_EN_0 0x00009140 /* RW-4R */ +#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* RWIVF */ +#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* RWI-V */ +#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* RW--V */ +#define NV_PTIMER_INTR_EN_0_TIMER 1:1 /* RWIVF */ +#define NV_PTIMER_INTR_EN_0_TIMER_DISABLED 0x00000000 /* RWI-V */ +#define NV_PTIMER_INTR_EN_0_TIMER_ENABLED 0x00000001 /* RW--V */ +#define NV_PTIMER_GR_TICK_FREQ 0x00009480 /* RW-4R */ +#define NV_PTIMER_GR_TICK_FREQ_SELECT 2:0 /* RWIUF */ +#define NV_PTIMER_GR_TICK_FREQ_SELECT_MAX 0x00000000 /* RW--V */ +#define NV_PTIMER_GR_TICK_FREQ_SELECT_DEFAULT 0x00000005 /* RWI-V */ +#define NV_PTIMER_GR_TICK_FREQ_SELECT_MIN 0x00000007 /* RW--V */ +#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */ +#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWIUF */ +#define NV_PTIMER_ALARM_0_NSEC_INIT 0x0 /* RWI-V */ +#define NV_PTIMER_TIMER_0 0x00009428 /* RW-4R */ +#define NV_PTIMER_TIMER_0_NSEC 31:0 /* */ +#define NV_PTIMER_TIMER_0_USEC 31:10 /* RWIUF */ +#define NV_PTIMER_TIMER_0_USEC_INIT 0x0 /* RWI-V */ diff --git a/Host-Fifo/volta/gv100/dev_usermode.ref.txt b/Host-Fifo/volta/gv100/dev_usermode.ref.txt new file mode 100644 index 0000000..cb98f96 --- /dev/null +++ b/Host-Fifo/volta/gv100/dev_usermode.ref.txt @@ -0,0 +1,134 @@ +Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. + +Permission is hereby granted, free of charge, to any person obtaining a +copy of this software and associated documentation files (the "Software"), +to deal in the Software without restriction, including without limitation +the rights to use, copy, modify, merge, publish, distribute, sublicense, +and/or sell copies of the Software, and to permit persons to whom the +Software is furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. +-------------------------------------------------------------------------------- + + This manual describes the USERMODE device. USERMODE is a mappable range of +registers for use by usermode drivers. The range is 64KB aligned and 64KB in +size to match the maximum page size of systems supported by NVIDIA hardware. + + Note that accesses to undefined registers in this device range do not cause +PRI_TIMEOUT interrupts to be raised. This is different from other PRI devices. +Writes to undefined registers are silently thrown away. Reads from undefined +registers return 0. + +Mnemonic Description Size Interface +------- ----------- ---- --------- +USERMODE Usermode region 64K HOST + +#define NV_USERMODE 0x0081FFFF:0x00810000 /* RW--D */ + + Table 1-1 Local Devices + + + +2 - IDENTIFICATION AND CAPABILITIES REGISTERS +=============================================================================== + + The first 128 bytes of the NV_USERMODE device are reserved for up to 32 +configuration and capabilities registers. + + +CFG0 - Config register 0: Class ID for the NV_USERMODE class + + The USERMODE_CLASS_ID field of the CFG0 register contains the class ID for +the class corresponding to the NV_USERMODE device. In gv100, this is the class +volta_usermode_a. + + +#define NV_USERMODE_CFG0 0x00810000 /* R--4R */ +#define NV_USERMODE_CFG0_USERMODE_CLASS_ID 15:0 /* R-IUF */ +#define NV_USERMODE_CFG0_USERMODE_CLASS_ID_VALUE 50017 /* R-I-V */ + +// Note: addresses up to 0x810080 are reserved for CGF and capabilities registers + + +3 - PTIMER CURRENT TIME REGISTERS +=============================================================================== + + The TIME registers contain the current time as kept by the PTIMER; see +dev_timer.ref. The current time is expressed in elapsed nanoseconds since the +UNIX epoch, 00:00 GMT, January 1, 1970 (zero hour). It generally has a +resolution of 32 nanoseconds. + + Note: To query the current time, read TIME_1, then TIME_0, and then TIME_1 +again. If the two readings of TIME_1 do not match, repeat the procedure. This +avoids incorrectly retrieving an incorrect time referring to a point up to 4 +seconds in the future: if one were to simply read TIME_0 and then TIME_1, TIME_0 +may overflow between the two reads. + + TIME_0 contains the low 32 bits of the timer. The least significant 5 bits +are always zero. The NSEC field contains the low order bits in 32ns +granularity. + + TIME_1 contains the high order bits. The NSEC field contains the upper 29 +bits of the timer. + + +TIME_0 Register - Timer Low Bits + + +#define NV_USERMODE_TIME_0 0x00810080 /* R--4R */ +#define NV_USERMODE_TIME_0_NSEC 31:5 /* R-XUF */ + + +TIME_1 Register - Timer High Bits + + +#define NV_USERMODE_TIME_1 0x00810084 /* R--4R */ +#define NV_USERMODE_TIME_1_NSEC 28:0 /* R-XUF */ + +// Note: addresses 0x810088 and 0x81008c are reserved for future TIME registers + + + +4 - CHANNEL WORK SUBMISSION REGISTERS +=============================================================================== + +NOTIFY_CHANNEL_PENDING - Notify Host that a channel has new work available + + Writing a channel ID to the ID field of NOTIFY_CHANNEL_PENDING tells Host +that new work is available to run on that channel. This causes the PENDING +status to be set in the NV_PCCSR_CHANNEL_STATUS field for that channel and +behaves identically to writing NV_PCCSR_CHANNEL_FORCE_PENDING, but is accessible +to usermode drivers. Setting pending will cause Host to schedule the channel +the next time it comes up in the runlist. Once the channel is scheduled, the +PBDMA will read GP_PUT from USERD to determine whether work is actually +available for the channel. + + Submitting new work to a channel involves these steps: + + 1. Write methods to the pushbuffer space + 2. Construct a new gp_fifo entry pointing to that pushbuffer space + 3. Update GP_PUT in USERD to indicate the new gp_fifo entry is ready + 4. Write the channel's handle to NV_USERMODE_NOTIFY_CHANNEL_PENDING_ID + + Note that if the ID refers to a non-existent channel, the write will be +ignored. Moreover, a write to an ID that exceeds the maximum supported channel +ID will have no effect (it will not overflow, causing some other channel to go +pending). + + Note that if the ID refers to a channel for which GP_PUT == GP_GET, Host will +still schedule the channel in order to determine the current status of its +GP_PUT, at which point it will discover there is no new work and move on to the +next channel. + + +#define NV_USERMODE_NOTIFY_CHANNEL_PENDING 0x00810090 /* -W-4R */ +#define NV_USERMODE_NOTIFY_CHANNEL_PENDING_ID 31:0 /* -W-UF */ diff --git a/MemoryClockTable/MemoryClockTable.html b/MemoryClockTable/MemoryClockTable.html new file mode 100644 index 0000000..d995e11 --- /dev/null +++ b/MemoryClockTable/MemoryClockTable.html @@ -0,0 +1,711 @@ + + + + + +NVIDIA Memory Clock Table Specifications + + + + +
+
+
+
+

Purpose

+
+

This document describes the VBIOS Memory clock table entries. +The Memory Clock Table starts with a header, followed immediately by an array of entries.

+

Memory Clock Table Header

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldName Size (in bits) Description

Version

8

+
+Memory Clock Table Version (0x11) +
+
+
+

Header Size

8

+
+Size of Memory Clock Table Header in bytes (26) +
+
+
+

Base Entry Size

8

+
+Size of Memory Clock Table Base Entry in bytes (20) +
+
+
+

Strap Entry Size

8

+
+Size of Memory Clock Table Strap Entry in bytes (26) +
+
+
+

Strap Entry Count

8

+
+Number of Memory Clock Table Strap Entries per Memory Clock Table Entry +
+
+
+

Entry Count

8

+
+Number of Memory Clock Table Entries (combined Base Entry plus Strap Entry Count of Strap Entries) +
+
+
+

Reserved

160

+
+

Memory Clock Table Base Entry

+

Each entry is made up of a single Base Entry and multiple Strap Entries. The entire size of an entry is given by ( MemoryClockTableHeader.BaseEntrySize + MemoryClockTableHeader.StrapEntrySize × MemoryClockTableHeader.StrapEntryCount ). Each entry provides information needed for operating the memory at a frequency between MemoryClockTableBaseEntry.Minimum.Frequency and MemoryClockTableBaseEntry.Maximum.Frequency, inclusively.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldName Size (in bits) Description

Min Frequency

16

+
+[15:14] = Reserved +
+
+[13:0] = Frequency (MHz) +
+
+
+

Max Frequency

16

+
+[15:14] = Reserved +
+
+[13:0] = Frequency(MHz) +
+
+
+

Reserved

40

Read/Write Config0

32

+
+[8:0] = Read Setting0 +
+
+[17:9] = Write Settings0 +
+
+[19:18] = Reserved +
+
+[24:20] = ReadSettings1 +
+
+[31:25] = Reserved +
+
+
+

Read/Write Config1

32

+
+[3:0] = Read Settings0 +
+
+[7:4] = Write Settings0 +
+
+[11:8] = Read Settings1 +
+
+[15:12] = Write Settings1 +
+
+[19:16] = Read Settings2 +
+
+[23:20] = Write Settings2 +
+
+[31:24] = Timing Settings0 +
+
+
+

Reserved

24

+
+

Memory Clock Table Strap Entry

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldName Size (in bits) Description

MemTweak Index

8

+
+[7:0] MemTweak Index +
+
+
+

Flags0

8

+
+[6:0] = Reserved +
+
+[7:7] = Alignment Mode +
+
+

+ 0x0 = Phase detector (Default)
+ 0x1 = Pin +

+
+

Reserved

48

Flags4

8

+
+[6:0] = Reserved +
+
+[7:7] = MRS7 GDDR5 +
+
+

+ 0x0 = Disable (Default)
+ 0x1 = Enable +

+
+

Reserved

8

Flags5

8

+
+[5:0] = Reserved +
+
+[6:6] = GDDR5x Internal VrefC +
+
+

+ 0x0 = Disable (Default) (70% VrefC)
+ 0x1 = Enable (50% VrefC) +

+
+
+[7:7] = Reserved +
+
+
+

Reserved

120

+
+
+ + + diff --git a/MemoryTweakTable/MemoryTweakTable.html b/MemoryTweakTable/MemoryTweakTable.html new file mode 100644 index 0000000..bb36740 --- /dev/null +++ b/MemoryTweakTable/MemoryTweakTable.html @@ -0,0 +1,763 @@ + + + + + +NVIDIA Memory Tweak Table Specifications + + + + +
+
+
+
+

Purpose

+
+

This document describes the VBIOS Memory tweak table entries.

+

Memory Tweak Table Header

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldName Size (in bits) Description
Version

8

+
+Memory Tweak Table Version (0x20) +
+
+
+
Header Size

8

+
+Size of Memory Tweak Table Header in bytes (6) +
+
+
+
Base Entry Size

8

+
+Size of Memory Tweak Table Base Entry in bytes (76) +
+
+
+
Extended Entry Size

8

+
+Size of Memory Tweak Table Extended Entry in bytes (12) +
+
+
+
Extended Entry Count

8

+
+Number of Memory Tweak Table Extended Entries per Memory Tweak Table Entry +
+
+
+
Entry Count

8

+
+Number of Memory Tweak Table Entries (combined Base Entry plus Extended Entry Count of Extended Entries) +
+
+
+
+
+

Memory Tweak Table Entry

+

Each entry is made up of a single Base Entry and multiple Extended Entries. The entire size of an entry is given by ( MemoryTweakTableHeader.BaseEntrySize + MemoryTweakTableHeader.ExtendedEntrySize × MemoryTweakTableHeader.ExtendedEntryCount ).

+

Memory Tweak Table Base Entry

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldName Size (in bits) Description

CONFIG0

32

+
+Field Definitions +
+
+

+ [7:0] = RC
+ [16:8] = RFC
+ [23:17]= RAS
+ [30:24]= RP
+ [31:31]= Reserved +

+
+

CONFIG1

32

+
+Field Definitions +
+
+

+ [6:0] = CL
+ [13:7] = WL
+ [19:14]= RD_RCD
+ [25:20]= WR_RCD
+ [31:26]= Reserved +

+
+

CONFIG2

32

+
+Field Definitions +
+
+

+ [3:0] = RPRE
+ [7:4] = WPRE
+ [14:8] = CDLR
+ [22:16] = WR
+ [27:24] = W2R_BUS
+ [31:28] = R2W_BUS +

+
+

CONFIG3

32

+
+Field Definitions +
+
+

+ [4:0] = PDEX
+ [8:5] = PDEN2PDEX
+ [16:9] = FAW
+ [23:17] = AOND
+ [27:24] = CCDL
+ [31:28] = CCDS +

+
+

CONFIG4

32

+
+Field Definitions +
+
+

+ [2:0] = REFRESH_LO
+ [14:3] = REFRESH
+ [20:15] = RRD
+ [26:21] = DELAY0
+ [31:27] = Reserved
+

+
+

CONFIG5

32

+
+Field Definitions +
+
+

+ [2:0] = ADR_MIN
+ [3:3] = Reserved
+ [10:4] = WRCRC
+ [11:11] = Reserved
+ [17:12] = OFFSET0
+ [19:18] = DELAY0_MSB
+ [23:20] = OFFSET1
+ [27:24] = OFFSET2
+ [31:28] = DELAY0 +

+
+

Reserved

184

Drive Strength

2

+
+Drive strength value to program depending on memory type +
+
+

+ SDDR2: MR1[1:1] - Output Driver Impedence Control
+ SDDR3: Unused
+ GDDR3: MR1[1:0] = Driver Strength
+ GDDR5: MR1[1:0] = Driver Strength +

+
+

Voltage0

3

Voltage1

3

Voltage2

3

R2P

5

+
+Minimum number of cycles from a read command to a precharge command for the same bank. +
+
+
+

Voltage3

3

Reserved

1

Voltage4

3

Reserved

1

Voltage5

3

Reserved

5

RDCRC

4

Reserved

36

TIMING22

32

+
+
Field Definitions
+
+
+
+
[9:0]   = RFCSBA
+
+
+
+
[17:10] = RFCSBR
+
+
+
+
[31:18] = Reserved
+

Reserved

128

+
+

Memory Tweak Table Extended Entry

+
+ ++++ + + + + + + + + + + + + + +
FieldName Size (in bits) Description

Reserved

96

+
+
+ + + diff --git a/Shader-Program-Header/Shader-Program-Header.html b/Shader-Program-Header/Shader-Program-Header.html new file mode 100644 index 0000000..3ae0dfa --- /dev/null +++ b/Shader-Program-Header/Shader-Program-Header.html @@ -0,0 +1,2550 @@ + + + + + +Shader Program Header Specification + + + + + +
+
+

Purpose

+
+

The first 80 bytes of a GPU program, known as the Shader Program Header (SPH), +contains information about the program, which the GPU uses to determine how to +execute the instructions.

+
+
+
+

SPH Overall Structure

+
+

Some portions of the SPH are interpreted differently depending on which stage +of the pipeline the program is used with (e.g., Vertex or Fragment), whereas +some portions are always interpreted the same way — they are common for all +program types.

+

There are two main types of programs; PS and VTG. PS is used for +pixel/fragment shaders, and VTG is used for everything else. When PS is used, +field SphType in CommonWord0 must be set to 1; similarly, when VTG is used, +SphType in CommonWord0 must be set to 2.

+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 1. SPH Type 1 Definition
Field Bit width Type

CommonWord0

32

struct CommonWord0

CommonWord1

32

struct CommonWord1

CommonWord2

32

struct CommonWord2

CommonWord3

32

struct CommonWord3

CommonWord4

32

struct CommonWord4

ImapSystemValuesA

24

struct ImapSystemValuesA

ImapSystemValuesB

8

struct ImapSystemValuesB

ImapGenericVector[32]

128

struct ImapVector

ImapColor

16

struct ImapColor

ImapSystemValuesC

16

struct ImapSystemValuesC

ImapFixedFncTexture[10]

40

struct ImapTexture

ImapReserved

8

-

OmapSystemValuesA

24

struct OmapSystemValuesA

OmapSystemValuesB

8

struct OmapSystemValuesB

OmapGenericVector[32]

128

struct OmapVector

OmapColor

16

struct OmapColor

OmapSystemValuesC

16

struct OmapSystemValuesC

OmapFixedFncTexture[10]

40

struct OmapTexture

OmapReserved

8

-

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 2. SPH Type 2 Definition
Field Bit width Type

CommonWord0

32

struct CommonWord0

CommonWord1

32

struct CommonWord1

CommonWord2

32

struct CommonWord2

CommonWord3

32

struct CommonWord3

CommonWord4

32

struct CommonWord4

ImapSystemValuesA

24

struct ImapSystemValuesA

ImapSystemValuesB

8

struct ImapSystemValuesB

ImapGenericVector[32]

256

struct ImapPixelVector

ImapColor

16

struct ImapPixelColor

ImapSystemValuesC

16

struct ImapSystemValuesC

ImapFixedFncTexture[10]

80

struct ImapPixelTexture

ImapReserved

16

-

OmapTarget[8]

32

struct OmapTarget

OmapSampleMask

1

bool

OmapDepth

1

bool

OmapReserved

30

-

+
+
+
+
+

SPH Common Word Definitions

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 3. CommonWord0 Definition
Field Bit width Type

SphType

5

enum

Version

5

U05

ShaderType

4

enum

MrtEnable

1

bool

KillsPixels

1

bool

DoesGlobalStore

1

bool

SassVersion

4

U04

Reserved

5

-

DoesLoadOrStore

1

bool

DoesFp64

1

bool

StreamOutMask

4

U04

+
+
    +
  • +

    +The SPH field SphType sets the type of shader, where the type is either + TYPE_01_VTG or TYPE_02_PS. +

    +
    • +
+
+ +++ + + + + + + + + + + + + + + + +
Name Value

VTG

1

PS

2

+
+
    +
  • +

    +The SPH field Version sets is used during development to pick the version. +

    +
    • +
  • +

    +The SPH field ShaderType sets the type (e.g, VERTEX, TESSELLATION, GEOMETRY, or PIXEL) + of shader for the shader program. +

    +
    • +
+
+ +++ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Value

VERTEX

1

TESSELLATION_INIT

2

TESSELLATION

3

GEOMETRY

4

PIXEL

5

+
+
    +
  • +

    +The SPH field MrtEnable, when TRUE indicates that the pixel shader outputs + multiple colors (the number being controlled by the SPH Omap). It is always + AND’d with SetCtMrtEnable.V(eff) to allow the driver to dynamically override the + MRT (Multiple Render Target) behavior of the pixel shader. If the result is + TRUE, then the pixel shader outputs will each be sent to its corresponding + enabled target. If the result is FALSE, then pixel shader output 0 + will be sent to each enabled target. This override of MRT is necessary to + support OGL’s DrawBuffer call (which is inherently non-MRT) when an MRT + enabled pixel shader is active. This field has no effect on the blending + enables; that is, whether MrtEnable result is TRUE or FALSE, each color + target still has an independent blend enable (unless + SetSingleRopControl.Enable is TRUE). This SPH field is only used for pixel + shaders. +

    +
    • +
  • +

    +The SPH field KillsPixels, if TRUE, enables pixel shader programs to kill pixels. When + set to FALSE, pixel shaders KIL instructions become no-operations and trigger + a hardware exception. Also, when this field is TRUE, EarlyZ is turned off, + and Zcull’s visible pixel counting acceleration is turned off. This field + has no effect on the texture color key operations. This SPH field is only + used for pixels shaders. +

    +
    • +
  • +

    +The SPH field DoesGlobalStore indicates the shader might perform a global store. +

    +
    • +
+
+ + + +
+
Note
+		When SPH.DoesGlobalStore == 0, any global store instructions (ST/ATOM/SUST) are +noop’d and a hardware exception is generated. The STL instruction may still +be used for local stores.
+
+
    +
  • +

    +The SPH field StreamOutMask selects which GS output streams are enbled + as outputs from the GS. There are four GS output streams, numbered 0 to 3. + If a stream is disabled in StreamOutMask, it is never written even if a buffer + is bound to it. +

    +
    • +
  • +

    +The SPH field DoesLoadOrStore is used to enable power optimizations by disabling the load/store + path if it is not being used. If a shader unit is only running pixel work that + has DoesLoadOrStore set to FALSE, and it has declared no additional CallReturnStack + by setting ShaderLocalMemoryCrsSize to zero, the load-store path can be + safely shut down temporarily. When DoesLoadOrStore == FALSE, LD, ST, and all the + variations thereof in the ISA, will be noop’ed by the HW. +

    +
    • +
  • +

    +The SPH field DoesFp64 is used power-off the double precision math if the compiler can + guarantee it will never be used. If all of the work running on a given Shader unit + has DoesFp64 set to FALSE, this math block will be powered down. Any double precision + instruction encountered when DoesFp64 is FALSE will be noop’ed by the HW. +

    +
    • +
+
+ + ++++ + + + + + + + + + + + + + + + + + + +
Table 4. CommonWord1 Definition
Field Bit width Type

ShaderLocalMemoryLowSize

24

U24

PerPatchAttributeCount

8

U08

+
+
    +
  • +

    +The SPH fields ShaderLocalMemoryLowSize and ShaderLocalMemoryHighSize set the + required size of thread-private memory, for variable storage, needed by the + shader program. +

    +
    • +
  • +

    +The SPH field PerPatchAttributeCount indicates the number of per-patch attributes + that are written by the tesselation init shader (and read by the subsequent tesselation + shader). Per-patch attributes are in addition to per-vertex attributes. + This field is only used on tesselation init shaders. +

    +
    • +
+
+ + + +
+
Note
+		Triangles generated by the geometry shader always have all their edge flags set +to TRUE.
+
+
+ + ++++ + + + + + + + + + + + + + + + + + + +
Table 5. CommonWord2 Definition
Field Bit width Type

ShaderLocalMemoryHighSize

24

U24

ThreadsPerInputPrimitive

8

U08

+
+
    +
  • +

    +The SPH field ThreadsPerInputPrimitive sets the maximum number of threads that + are invoked for a primitive, thereby allowing the work of one shader + to be divided amongst several shaders. This is the number of "instanced" + shaders. This field has the following shader-specific meanings: +

    +
    • +
+
+ +++ + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Program Type Meaning

VERTEX

Unused

TESSELLATION_INIT

Sets the number of threads run per patch

TESSELLATION

Unused

GEOMETRY

Sets the number of threads run per primitive

PIXEL

Unused

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + +
Table 6. CommonWord3 Definition
Field Bit width Type

ShaderLocalMemoryCrsSize

24

U24

OutputTopology

4

enum

Reserved

4

-

+
+
    +
  • +

    +The SPH field ShaderLocalMemoryCrsSize sets the additional (off chip) call/return stack size (CRS_SZ). + Units are in Bytes/Warp. Minimum value 0, maximum 1 megabyte. Must be multiples of 512 bytes. +

    +
    • +
  • +

    +The SPH field OutputTopology sets the primitive topology of the vertices that are output from the + pipe stage. This field is only used with geometry shaders, where the value must be greater than zero and + has a maximum of 1024. The allowed values are: +

    +
    • +
+
+ +++ + + + + + + + + + + + + + + + + + + + +
Name Value

POINTLIST

1

LINESTRIP

6

TRIANGLESTRIP

7

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 7. CommonWord4 Definition
Field Bit width Type

MaxOutputVertexCount

12

U12

StoreReqStart

8

U08

Reserved

4

-

StoreReqEnd

8

U08

+
+
    +
  • +

    +The SPH field MaxOutputVertexCount sets the maximum number of vertices that can be output by + one shader thread. This field is only used with geometry shaders, where the + value sets the maximum number of vertices output per thread, and OUT instructions + beyond this are noop’ed. +

    +
    • +
  • +

    +The SPH fields StoreReqStart and StoreReqEnd set a range of attributes + whose corresponding Odmap values of ST or ST_LAST are treated as ST_REQ. + Normally, for an attribute whose Omap bit is TRUE and Odmap value is ST, when + the shader writes data to this output, it can not count on being able to read + it back, since the next downstream shader might have its Imap bit FALSE, + thereby causing the Bmap bit to be FALSE. By including a ST type of attribute + in the range of StoreReqStart and StoreReqEnd, the attribute’s Odmap value + is treated as ST_REQ, so an Omap bit being TRUE causes the Bmap bit to + be TRUE. This guarantees the shader program can output the value and + then read it back later. This will save register space. +

    +
    • +
  • +

    +The SPH field StoreReqStart sets the first attribute whose ST or ST_LAST + Odmap values are treated as ST_REQ. Note that Odmap values of discard are + not affected. +

    +
    • +
  • +

    +The SPH field StoreReqEnd sets the last attribute whose ST of ST_LAST Odmap + values are treated as ST_REQ. If no attributes are to have their Odmap value + treated as ST_REQ, then the SPH needs to have StoreReqStart greater + than StoreReqEnd. +

    +
    • +
+
+ + + +
+
Note
+		SPH fields StoreReqStart and StoreReqEnd are ignored for geometry and pixel +shaders. For geometry shaders, ALD.O is disallowed because a single geometry +shader thread can output multiple vertices, so it is not possible to read back +every attribute that was previously written (unlike vertex, tesselation and +tesselation init shaders).
+
+
+
+
+

SPH IMAP Definitions

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 8. ImapSystemValuesA Definition
Field Bit width Type

Reserved

4

-

ImapTessellationLodLeft

1

bool

ImapTessellationLodRight

1

bool

ImapTessellationLodBottom

1

bool

ImapTessellationLodTop

1

bool

ImapTessellationInteriorU

1

bool

ImapTessellationInteriorV

1

bool

Reserved

14

-

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 9. ImapSystemValuesB Definition
Field Bit width Type

ImapPrimitiveId

1

bool

ImapRtArrayIndex

1

bool

ImapViewportIndex

1

bool

ImapPointSize

1

bool

ImapPositionX

1

bool

ImapPositionY

1

bool

ImapPositionZ

1

bool

ImapPositionW

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 10. ImapColor Definition
Field Bit width Type

ImapColorFrontDiffuseRed

1

bool

ImapColorFrontDiffuseGreen

1

bool

ImapColorFrontDiffuseBlue

1

bool

ImapColorFrontDiffuseAlpha

1

bool

ImapColorFrontSpecularRed

1

bool

ImapColorFrontSpecularGreen

1

bool

ImapColorFrontSpecularBlue

1

bool

ImapColorFrontSpecularAlpha

1

bool

ImapColorBackDiffuseRed

1

bool

ImapColorBackDiffuseGreen

1

bool

ImapColorBackDiffuseBlue

1

bool

ImapColorBackDiffuseAlpha

1

bool

ImapColorBackSpecularRed

1

bool

ImapColorBackSpecularGreen

1

bool

ImapColorBackSpecularBlue

1

bool

ImapColorBackSpecularAlpha

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 11. ImapSystemValuesC Definition
Field Bit width Type

ImapClipDistance0

1

bool

ImapClipDistance1

1

bool

ImapClipDistance2

1

bool

ImapClipDistance3

1

bool

ImapClipDistance4

1

bool

ImapClipDistance5

1

bool

ImapClipDistance6

1

bool

ImapClipDistance7

1

bool

ImapPointSpriteS

1

bool

ImapPointSpriteT

1

bool

ImapFogCoordinate

1

bool

Reserved

1

bool

ImapTessellationEvaluationPointU

1

bool

ImapTessellationEvaluationPointV

1

bool

ImapInstanceId

1

bool

ImapVertexId

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 12. ImapPixelColor Definition
Field Bit width Type

ImapColorDiffuseRed

2

enum PixelImap

ImapColorDiffuseGreen

2

enum PixelImap

ImapColorDiffuseBlue

2

enum PixelImap

ImapColorDiffuseAlpha

2

enum PixelImap

ImapColorSpecularRed

2

enum PixelImap

ImapColorSpecularGreen

2

enum PixelImap

ImapColorSpecularBlue

2

enum PixelImap

ImapColorSpecularAlpha

2

enum PixelImap

+
+
+ + +++ + + + + + + + + + + + + + + + + + + + + + + + +
Table 13. PixelImap enum definition
Name Value

Unused

0

Constant

1

Perspective

2

ScreenLinear

3

+
+
+
+
+

SPH OMAP Definitions

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 14. OmapSystemValuesA Definition
Field Bit width Type

Reserved

4

-

OmapTessellationLodLeft

1

bool

OmapTessellationLodRight

1

bool

OmapTessellationLodBottom

1

bool

OmapTessellationLodTop

1

bool

OmapTessellationInteriorU

1

bool

OmapTessellationInteriorV

1

bool

Reserved

14

-

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 15. OmapSystemValuesB Definition
Field Bit width Type

OmapPrimitiveId

1

bool

OmapRtArrayIndex

1

bool

OmapViewportIndex

1

bool

OmapPointSize

1

bool

OmapPositionX

1

bool

OmapPositionY

1

bool

OmapPositionZ

1

bool

OmapPositionW

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 16. OmapColor Definition
Field Bit width Type

OmapColorFrontDiffuseRed

1

bool

OmapColorFrontDiffuseGreen

1

bool

OmapColorFrontDiffuseBlue

1

bool

OmapColorFrontDiffuseAlpha

1

bool

OmapColorFrontSpecularRed

1

bool

OmapColorFrontSpecularGreen

1

bool

OmapColorFrontSpecularBlue

1

bool

OmapColorFrontSpecularAlpha

1

bool

OmapColorBackDiffuseRed

1

bool

OmapColorBackDiffuseGreen

1

bool

OmapColorBackDiffuseBlue

1

bool

OmapColorBackDiffuseAlpha

1

bool

OmapColorBackSpecularRed

1

bool

OmapColorBackSpecularGreen

1

bool

OmapColorBackSpecularBlue

1

bool

OmapColorBackSpecularAlpha

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 17. OmapSystemValuesC Definition
Field Bit width Type

OmapClipDistance0

1

bool

OmapClipDistance1

1

bool

OmapClipDistance2

1

bool

OmapClipDistance3

1

bool

OmapClipDistance4

1

bool

OmapClipDistance5

1

bool

OmapClipDistance6

1

bool

OmapClipDistance7

1

bool

OmapPointSpriteS

1

bool

OmapPointSpriteT

1

bool

OmapFogCoordinate

1

bool

OmapSystemValuesReserved17

1

bool

OmapTessellationEvaluationPointU

1

bool

OmapTessellationEvaluationPointV

1

bool

OmapInstanceId

1

bool

OmapVertexId

1

bool

+
+
+
+
+

SPH Vector Definitions

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 18. ImapVector Definition
Field Bit width Type

ImapX

1

bool

ImapY

1

bool

ImapZ

1

bool

ImapW

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 19. OmapVector Definition
Field Bit width Type

OmapX

1

bool

OmapY

1

bool

OmapZ

1

bool

OmapW

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 20. ImapPixelVector Definition
Field Bit width Type

ImapX

2

enum PixelImap

ImapY

2

enum PixelImap

ImapZ

2

enum PixelImap

ImapW

2

enum PixelImap

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 21. ImapTexture Definition
Field Bit width Type

ImapS

1

bool

ImapT

1

bool

ImapR

1

bool

ImapQ

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 22. OmapTexture Definition
Field Bit width Type

OmapS

1

bool

OmapT

1

bool

OmapR

1

bool

OmapQ

1

bool

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 23. ImapPixelTexture Definition
Field Bit width Type

ImapS

2

enum PixelImap

ImapT

2

enum PixelImap

ImapR

2

enum PixelImap

ImapQ

2

enum PixelImap

+
+
+ + ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Table 24. OmapTarget Definition
Field Bit width Type

OmapRed

1

bool

OmapGreen

1

bool

OmapBlue

1

bool

OmapAlpha

1

bool

+
+
+
+
+
+ + + diff --git a/gk104-disable-graphics-power-gating/gk104-disable-graphics-power-gating.txt b/gk104-disable-graphics-power-gating/gk104-disable-graphics-power-gating.txt new file mode 100644 index 0000000..fe93c72 --- /dev/null +++ b/gk104-disable-graphics-power-gating/gk104-disable-graphics-power-gating.txt @@ -0,0 +1,113 @@ +Synopsis: + +How to disable on-boot power-gating (PGOB) of the graphics engine on some +GK104 and GK106 based notebook products. + +Description: + +The GK104 and GK106 GPUs used in some notebook products are configured such +that the graphics engine is power-gated at boot time. This on-boot +power-gating feature needs to be disabled using the sequence described below +before the graphics engine can be initialized and used by a GPU driver. + +The NVIDIA Accelerated Linux GPU Driver enables the graphics engine as needed. +However, independently developed drivers also need to enable the engine +before attempting to communicate with it. + +Sequence: + +All register write accesses described in this section are read-modify-write +operations. That is, changes to fields within the affected registers must not +change the value of other, reserved fields within the same registers. + + 1) Set NV_PMC_ENABLE_PGRAPH to DISABLED. + 2) Read NV_PMC_ENABLE. + + 3) Set NV_PMC_ENABLE_BLG to ENABLED. + 4) Delay 50ms. + + 5) Set NV_PPWR_PMU_PG_PSW_MASK_CLAMPVAL_0 to 1. + 6) Set NV_PPWR_PMU_PG_PSW_MASK_CLAMPMSK_0 to ENABLE. + 7) Set NV_PPWR_PMU_PG_PSW_MASK_CLAMPMSK_0 to DISABLE. + + 8) Set NV_THERM_CTRL_1_PGOB_OVERRIDE_VALUE to OFF. + 9) Set NV_THERM_CTRL_1_PGOB_OVERRIDE to ENABLED. + 10) Delay 50ms. + + 11) Set NV_PPWR_PMU_PG_PSW_MASK_CLAMPVAL_0 to 0. + 12) Set NV_PPWR_PMU_PG_PSW_MASK_CLAMPMSK_0 to ENABLE. + 13) Set NV_PPWR_PMU_PG_PSW_MASK_CLAMPMSK_0 to DISABLE. + + 14) Set NV_PMC_ENABLE.BLG to DISABLED. + + 15) Set NV_PMC_ENABLE_PGRAPH to ENABLED. + 16) Read NV_PMC_ENABLE. + +Scope: + +The sequence is required on certain GK104 and GK106 based notebooks. However, +it may be safely applied on all GK104 and GK106 GPUs. + +Register Description: + + The ENABLE register is used to enable or disable an engine. The disabled +state is the same as a software reset. While an engine is disabled, the +engine's reset signal is active. + +31 24 23 16 15 8 7 0 +.-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +| | 0 0 0 0 0 0| |0 0| | | |0 0| |0 0 0| |0 0| | | | | | | ENABLE +`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + +#define NV_PMC_ENABLE 0x00000200 /* RW-4R */ + +The PGRAPH bit specifies the Graphics Engine is enabled. + +#define NV_PMC_ENABLE_PGRAPH 12:12 /* RWIVF */ +#define NV_PMC_ENABLE_PGRAPH_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_PGRAPH_ENABLED 0x00000001 /* RW--V */ + +The BLG bit specifies whether the Block Level Power Gating (BLPG) and Block +Level Clock Gating (BLCG) controllers within the graphics engine are +enabled. + +#define NV_PMC_ENABLE_BLG 27:27 /* RWIVF */ +#define NV_PMC_ENABLE_BLG_DISABLED 0x00000000 /* RWI-V */ +#define NV_PMC_ENABLE_BLG_ENABLED 0x00000001 /* RW--V */ + + +CLAMPMSK - Decides whether or not to mask the clamp enable signal for that engine. +CLAMPVAL - Decides what value to set clamp enable signal to when CLAMPMSK is 1. + + 31 24 23 16 15 8 7 0 +.-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +| | | | | | | | | PG_PSW_MASK +`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + +#define NV_PPWR_PMU_PG_PSW_MASK 0x0010a78c /* RW-4R */ + +#define NV_PPWR_PMU_PG_PSW_MASK_CLAMPMSK_0 0:0 /* RWIUF */ +#define NV_PPWR_PMU_PG_PSW_MASK_CLAMPMSK_0_INIT 0x00000000 /* RWI-V */ +#define NV_PPWR_PMU_PG_PSW_MASK_CLAMPMSK_0_ENABLE 0x00000001 /* RW--V */ +#define NV_PPWR_PMU_PG_PSW_MASK_CLAMPMSK_0_DISABLE 0x00000000 /* RW--V */ +#define NV_PPWR_PMU_PG_PSW_MASK_CLAMPVAL_0 1:1 /* RWIUF */ +#define NV_PPWR_PMU_PG_PSW_MASK_CLAMPVAL_0_INIT 0x00000000 /* RWI-V */ +#define NV_PPWR_PMU_PG_PSW_MASK_CLAMPVAL_0_FALSE 0x00000000 /* RW--V */ +#define NV_PPWR_PMU_PG_PSW_MASK_CLAMPVAL_0_TRUE 0x00000001 /* RW--V */ + + + 31 24 23 16 15 8 7 0 +.-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +|0 0| | | | | | |0 0 0| |0 0 0| |0 0 0| |0| | | | | | | | | | | | CTRL_1 +`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + +#define NV_THERM_CTRL_1 0x00020004 /* RW-4R */ + +#define NV_THERM_CTRL_1_PGOB_OVERRIDE 30:30 /* RWIVF */ +#define NV_THERM_CTRL_1_PGOB_OVERRIDE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_CTRL_1_PGOB_OVERRIDE_DISABLED 0x00000000 /* RW--V */ +#define NV_THERM_CTRL_1_PGOB_OVERRIDE_ENABLED 0x00000001 /* RW--V */ +#define NV_THERM_CTRL_1_PGOB_OVERRIDE_VALUE 31:31 /* RWIVF */ +#define NV_THERM_CTRL_1_PGOB_OVERRIDE_VALUE_INIT 0x00000000 /* RWI-V */ +#define NV_THERM_CTRL_1_PGOB_OVERRIDE_VALUE_OFF 0x00000000 /* RW--V */ +#define NV_THERM_CTRL_1_PGOB_OVERRIDE_VALUE_ON 0x00000001 /* RW--V */ diff --git a/gk104-disable-underflow-reporting/gk104-disable-underflow-reporting.txt b/gk104-disable-underflow-reporting/gk104-disable-underflow-reporting.txt new file mode 100644 index 0000000..1519c33 --- /dev/null +++ b/gk104-disable-underflow-reporting/gk104-disable-underflow-reporting.txt @@ -0,0 +1,89 @@ +Synopsis: + +How to address an intermittent problem observed on some GK104-based products. + +Description: + +A diagnostic setting was inadvertently left enabled in the production VBIOS +builds on some NVIDIA GK104-based graphics cards. This setting can result in a +red screen being displayed in some rare cases, for example in response to +certain mode-set operations. + +The setting in question is used as part of the product engineering process to +make display engine underflows more easily human-detectable. This is a scenario +in which the bandwidth provided by the GPU's video memory interface, in the +current performance state (at relevant clock frequencies defined by this state), +is insufficient to satisfy the current isochronous streaming requirements of the +display engine. + +The NVIDIA Accelerated Linux Graphics Driver disables this setting when it +initializes the GPU. However, it is NVIDIA's suggestion that independently +developed drivers also disable it. + +Workaround: + +The underflow detection setting can be disabled by means of the per-head +register NV_PDISP_RG_UNDERFLOW(i), accessible via the GPUs' BAR0 (where 'i' is +the head index): + + NV_PDISP_RG_UNDERFLOW(i) (0x00616308 + (i) * 2048) + +Since the affected GPUs implement four heads, four such registers are +available. To disable the underflow detection, the registers need to be +programmed with the value 0. + +Scope: + +The problem described above affects GK104-based products with VBIOS versions +below 80.04.63.00.00. This includes (but may not be limited to) the following +products: + + PCI ID Product Name + ------- ----------------- + 0x11a0 GeForce GTX 680M + 0x11a1 GeForce GTX 670MX + 0x11a2 GeForce GTX 675MX + 0x11a3 GeForce GTX 680MX + 0x11bc Quadro K5000M + 0x11bd Quadro K4000M + 0x11be Quadro K3000M + +Register Description: + +This register is used for detecting underflows and also determines what action +the hw should take when an underflow occurs. + +ENABLE Turns on underflow reporting. Note that this has no effect on the +underflow mode. The underflow mode (what to do when an underflow occurs, REPEAT +or RED, is always active). + +UNDERFLOWED Indicates whether an underflow has occurred. This is a "sticky" bit. +To clear it, software writes a '1' to this bit. UNDERFLOWED is active +only when the above ENABLE bit is set. + +UNDERFLOW_MODE Indicates what to do when an underflow occurs. If REPEAT +is set, then the raster generator will repeat the last pixel, when a new +pixel is not available. If RED is set, the raster generator will display +bright red for any missing pixels. + + 31 24 23 16 15 8 7 0 +.-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-. +| |0 0 0 0 0 0 0| | RG_UNDERFLOW +`-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-' + +#define NV_PDISP_RG_UNDERFLOW(i) (0x00616308+(i)*2048) /* RW-4A */ +#define NV_PDISP_RG_UNDERFLOW__SIZE_1 4 /* */ +#define NV_PDISP_RG_UNDERFLOW_ENABLE 0:0 /* RWIVF */ +#define NV_PDISP_RG_UNDERFLOW_ENABLE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNDERFLOW_ENABLE_ENABLE 0x00000001 /* RW--V */ +#define NV_PDISP_RG_UNDERFLOW_ENABLE_DISABLE 0x00000000 /* RW--V */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED 4:4 /* RWIVF */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_CLR 0x00000001 /* -W--V */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_YES 0x00000001 /* R---V */ +#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_NO 0x00000000 /* R---V */ +#define NV_PDISP_RG_UNDERFLOW_MODE 8:8 /* RWIVF */ +#define NV_PDISP_RG_UNDERFLOW_MODE_INIT 0x00000000 /* RWI-V */ +#define NV_PDISP_RG_UNDERFLOW_MODE_REPEAT 0x00000000 /* RW--V */ +#define NV_PDISP_RG_UNDERFLOW_MODE_RED 0x00000001 /* RW--V */ + diff --git a/pascal/BIT_DISPLAY_PTRS-U-BIT_DP_PTRS-d.pdf b/pascal/BIT_DISPLAY_PTRS-U-BIT_DP_PTRS-d.pdf new file mode 100644 index 0000000..9029f0c Binary files /dev/null and b/pascal/BIT_DISPLAY_PTRS-U-BIT_DP_PTRS-d.pdf differ diff --git a/pascal/gp100-fbpa.txt b/pascal/gp100-fbpa.txt new file mode 100644 index 0000000..6258f06 --- /dev/null +++ b/pascal/gp100-fbpa.txt @@ -0,0 +1,92 @@ +-------------------------------------------------------------------------------- + +Synopsis: + +Description of changes made to the framebuffer partition addressing (FBPA) in +Pascal and later NVIDIA architectures. + +-------------------------------------------------------------------------------- + +Description: + +NVIDIA moved and expanded the MMIO space used for accessing the per-partition +information on Pascal and later architectures. Relative offsets to specific +controls remain the same as for prior architectures, for the most part. + +-------------------------------------------------------------------------------- + +Summary: + +These MMIO ranges have been moved and expanded from 0x1000 to 0x4000 in size: + +Name Old Range New Range +NV_PFB_FBPA 0x10F000 (0x1000) 0x9A0000 (0x4000) +NV_PFB_FBPA[i] 0x110000+(i * 0x1000) 0x900000+(i * 0x4000) +NV_PFB_FBPA_MC[i] 0x11D000+(i * 0x1000) 0x980000+(i * 0x4000) + +The number of NV_PFB_FBPA[i] ranges is increased to a maximum of 16. +The number of NV_PFB_FBPA_MC[i] ranges remains 3. + +Memory partition sizing and programming is the same as in prior NVIDIA +architectures. + +FBPAs are grouped into logical FBP units. In most prior NVIDIA architectures +(except GF108) each logical FBP mapped to one FBPA. To support High Bandwidth +Memory (HBM) GP100 groups 2 FBPAs into each logical FBP. This is noted here to +be clear that the number of logical FBPs does not necessarily equate to the number +of physical FBPAs. The register NV_PTOP_SCAL_NUM_FBPA_PER_FBP (0x22458) defines +this relationship in Pascal and later architectures. + +Per-partition memory size detection works similarly to the way it has in prior +NVIDIA architectures: + +1) Determine maximum number of possible FBPAs by reading + NV_PTOP_SCAL_NUM_FBPAS (0x2243C) +2) Determine number of FBPAs per FBP by reading + NV_PTOP_SCAL_NUM_FBPA_PER_FBP (0x22458) +3) Determine maximum number of LTCs per FBP by reading + NV_FUSE_STATUS_OPT_ROP_L2_FBP(i) (0x21d70+(i)*4) +4) For each bit not set in NV_FUSE_STATUS_OPT_FBIO (0x21C14) + a. Read the partition memory size from + NV_PFB_FBPA[i] + _CSTATUS_RAMAMOUNT (0x20C) + b. Up to the number of possible FBPAs determined in #1 +5) Any difference in the per-partition memory size indicates a "mixed memory" + configuration (Fermi & Kepler). +6) Any difference in the per-partition LTC coverage effectively indicates a + "mixed memory" configuration (Maxwell and later). +7) For "mixed memory" configurations: + a. Set NV_PFB_FBHUB_NUM_ACTIVE_FBPS (0x100800) bit 4 to 1. + b. Treat GPU FB address space as split into lower and upper sections. + The lower size is common partition size * FBPA count and is + based at 0. The upper section starts at either 0x2'00000000 + (Fermi/Kepler) or 0x10'00000000 (Maxwell & later) PLUS the + common partition size. Its size is the remaining GPU FB not + already mapped in the lower section. + c. The upper section of memory should not be used for displayable or + compression-related surfaces. + +-------------------------------------------------------------------------------- + +Definitions: + +#define NV_PTOP_SCAL_NUM_FBPAS 0x0002243C /* R--4R */ + +#define NV_PTOP_SCAL_NUM_FBPAS_VALUE 4:0 /* R-IVF */ + + +#define NV_PTOP_SCAL_NUM_FBPA_PER_FBP 0x00022458 /* R--4R */ + +#define NV_PTOP_SCAL_NUM_FBPA_PER_FBP_VALUE 4:0 /* R-IVF */ + + +#define NV_FUSE_STATUS_OPT_ROP_L2_FBP(i) (0x00021d70+(i)*4) /* R-I4A */ +#define NV_FUSE_STATUS_OPT_ROP_L2_FBP__SIZE_1 16 /* */ +#define NV_FUSE_STATUS_OPT_ROP_L2_FBP_DATA 31:0 /* R-IVF */ + +#define NV_FUSE_STATUS_OPT_FBIO 0x00021C14 /* R-I4R */ +#define NV_FUSE_STATUS_OPT_FBIO_DATA 15:0 /* R-IVF */ + +#define NV_PFB_FBHUB_NUM_ACTIVE_FBPS 0x00100800 /* RW-4R */ +#define NV_PFB_FBHUB_NUM_ACTIVE_FBPS_MIXED_MEM_DENSITY 4:4 /* */ + +-------------------------------------------------------------------------------- diff --git a/pascal/gp100-mmu-format.pdf b/pascal/gp100-mmu-format.pdf new file mode 100644 index 0000000..f55dff4 Binary files /dev/null and b/pascal/gp100-mmu-format.pdf differ diff --git a/pascal/gp100-msi-intr.txt b/pascal/gp100-msi-intr.txt new file mode 100644 index 0000000..1081e3b --- /dev/null +++ b/pascal/gp100-msi-intr.txt @@ -0,0 +1,76 @@ +-------------------------------------------------------------------------------- + +Synopsis: + +Description of changes made to the interrupt controller in Pascal and later +NVIDIA architectures. + +-------------------------------------------------------------------------------- + +Description: + +NVIDIA replaced the old interrupt control tree in Pascal and later architectures +to migrate away from a legacy PCI interrupt based scheme toward MSI-X interrupts. + +-------------------------------------------------------------------------------- + +Summary: + +These registers no longer exist in Pascal and later architectures: +#define NV_PMC_INTR_2 0x00000108 /* */ +#define NV_PMC_INTR_LTC 0x0000017c /* R--4R */ +#define NV_PMC_INTR_FBPA 0x00000180 /* R--4R */ +#define NV_PMC_INTR_READ(i) (0x00000160+(i)*4) /* R--4A */ +#define NV_PMC_INTR_IMSK(i) (0x00000640+(i)*4) /* RW-4A */ + +These registers are added in Pascal and later architectures: +#define NV_PMC_INTR_MODE(i) (0x00000120+(i)*4) /* R--4A */ +#define NV_PMC_INTR_EN_SET(i) (0x00000160+(i)*4) /* -W-4A */ +#define NV_PMC_INTR_EN_CLEAR(i) (0x00000180+(i)*4) /* -W-4A */ +#define NV_PMC_INTR_SW(i) (0x000001A0+(i)*4) /* RW-4A */ +#define NV_PMC_INTR_LTC 0x000001C0 /* R--4R */ +#define NV_PMC_INTR_FBPA 0x000001D0 /* R--4R */ + +The fields of the device interrupt pending register are no longer writable. +#define NV_PMC_INTR(i) (0x00000100+(i)*4) + +The function of this register has changed. It is now a read-only status register +reporting the per-device interrupt enable state. +#define NV_PMC_INTR_EN(i) (0x00000140+(i)*4) + +Furthermore, the NV_PMC_INTR(2) has been removed. Only INTR(0) and INTR(1) exist +on Pascal and later architectures. + +Each bit of NV_PMC_INTR_MODE(i) defines whether the corresponding device interrupt +is LEVEL trigger (0) or EDGE trigger (1). + +NV_PMC_INTR_EN(i) is now read-only and no longer used to enable/disable interrupts. +That task is now handled by NV_PMC_INTR_EN_SET(i) and NV_PMC_INTR_EN_CLEAR(i). +Each bit corresponds with a GPU device. + +The mapping of devices to interrupts is best determined by parsing the PTOP +DEVICE_INFO structure, however legacy devices still map to the same bitfields +as in pre-Pascal architectures. + +Device Bit# +NVENC1 1 +CE5 2 +NVENC2 4 +CE0 5 +CE1 6 +CE2/GRCOPY 7 +PFIFO 8 +REPLAYABLE_FAULT 9 +CE3 10 +CE4 11 +PGRAPH 12 +PFB 13 +SEC 15 +NVENC0 16 +NVDEC 17 +THERMAL 18 +PTIMER 20 +PMU 24 +LTC 25 +SW 31 + diff --git a/qmd/cla0c0qmd.h b/qmd/cla0c0qmd.h new file mode 100644 index 0000000..c0829f1 --- /dev/null +++ b/qmd/cla0c0qmd.h @@ -0,0 +1,660 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLA0C0QMD_H__ +#define __CLA0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_06 + */ + +#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_06_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200) +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223) +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512) +#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543) +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599) +#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600) +#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607) +#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610) +#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618) +#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632) +#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA0C0QMD_H__ diff --git a/qmd/cla1c0qmd.h b/qmd/cla1c0qmd.h new file mode 100644 index 0000000..b322988 --- /dev/null +++ b/qmd/cla1c0qmd.h @@ -0,0 +1,451 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLA1C0QMD_H__ +#define __CLA1C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVA1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVA1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVA1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVA1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVA1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_THROTTLED MW(372:372) +#define NVA1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVA1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVA1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVA1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVA1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVA1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVA1C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVA1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVA1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVA1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVA1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVA1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVA1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA1C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVA1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVA1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVA1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVA1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVA1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVA1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVA1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVA1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVA1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVA1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVA1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVA1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVA1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVA1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVA1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVA1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVA1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVA1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVA1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVA1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVA1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVA1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVA1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVA1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVA1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVA1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVA1C0_QMDV01_07_QMD_RESERVED_A MW(199:198) +#define NVA1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVA1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVA1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVA1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVA1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVA1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVA1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVA1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVA1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVA1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVA1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVA1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVA1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVA1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVA1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVA1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVA1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVA1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVA1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVA1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVA1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVA1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVA1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVA1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVA1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVA1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVA1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVA1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVA1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVA1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVA1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVA1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVA1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVA1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVA1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVA1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVA1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVA1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVA1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVA1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVA1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVA1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVA1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVA1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVA1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVA1C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVA1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVA1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVA1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVA1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVA1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVA1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVA1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVA1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVA1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVA1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVA1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVA1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVA1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVA1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVA1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLA1C0QMD_H__ diff --git a/qmd/clb0c0qmd.h b/qmd/clb0c0qmd.h new file mode 100644 index 0000000..c68e893 --- /dev/null +++ b/qmd/clb0c0qmd.h @@ -0,0 +1,454 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB0C0QMD_H__ +#define __CLB0C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVB0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVB0C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVB0C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVB0C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVB0C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_THROTTLED MW(372:372) +#define NVB0C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVB0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB0C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVB0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVB0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVB0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVB0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVB0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVB0C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVB0C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVB0C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVB0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVB0C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVB0C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVB0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVB0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB0C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVB0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB0C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVB0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVB0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB0C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVB0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVB0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVB0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVB0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVB0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVB0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVB0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVB0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVB0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVB0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVB0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVB0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVB0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVB0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVB0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVB0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVB0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVB0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVB0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVB0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVB0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVB0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVB0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVB0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVB0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVB0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVB0C0_QMDV01_07_QMD_RESERVED_A MW(198:198) +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVB0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVB0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVB0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVB0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVB0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVB0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVB0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVB0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVB0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVB0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVB0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVB0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVB0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVB0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVB0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVB0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVB0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVB0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVB0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVB0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVB0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVB0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVB0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVB0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVB0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVB0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVB0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVB0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVB0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVB0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVB0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVB0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVB0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVB0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVB0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVB0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVB0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVB0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVB0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVB0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVB0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVB0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLB0C0QMD_H__ diff --git a/qmd/clb1c0qmd.h b/qmd/clb1c0qmd.h new file mode 100644 index 0000000..ca98206 --- /dev/null +++ b/qmd/clb1c0qmd.h @@ -0,0 +1,454 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLB1C0QMD_H__ +#define __CLB1C0QMD_H__ + +/* +** Queue Meta Data, Version 00_06 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127) +#define NVB1C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192) +#define NVB1C0_QMDV00_06_QMD_RESERVED_A MW(199:197) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_B MW(207:204) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224) +#define NVB1C0_QMDV00_06_QMD_RESERVED_C MW(249:249) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_PROGRAM_OFFSET MW(287:256) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320) +#define NVB1C0_QMDV00_06_QMD_RESERVED_D MW(335:328) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352) +#define NVB1C0_QMDV00_06_QMD_RESERVED_E MW(365:358) +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368) +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_THROTTLED MW(372:372) +#define NVB1C0_QMDV00_06_THROTTLED_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_THROTTLED_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376) +#define NVB1C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377) +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB1C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB1C0_QMDV00_06_SAMPLER_INDEX MW(382:382) +#define NVB1C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB1C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383) +#define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384) +#define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416) +#define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432) +#define NVB1C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB1C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB1C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512) +#define NVB1C0_QMDV00_06_QMD_RESERVED_F MW(542:536) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544) +#define NVB1C0_QMDV00_06_QMD_RESERVED_G MW(575:562) +#define NVB1C0_QMDV00_06_QMD_VERSION MW(579:576) +#define NVB1C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580) +#define NVB1C0_QMDV00_06_QMD_RESERVED_H MW(591:584) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB1C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_QMD_RESERVED_I MW(668:648) +#define NVB1C0_QMDV00_06_L1_CONFIGURATION MW(671:669) +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB1C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672) +#define NVB1C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704) +#define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB1C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB1C0_QMDV00_06_QMD_RESERVED_J MW(783:776) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV00_06_QMD_RESERVED_K MW(791:791) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800) +#define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB1C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB1C0_QMDV00_06_QMD_RESERVED_L MW(879:872) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV00_06_QMD_RESERVED_M MW(887:887) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB1C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464) +#define NVB1C0_QMDV00_06_BARRIER_COUNT MW(1471:1467) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB1C0_QMDV00_06_REGISTER_COUNT MW(1503:1496) +#define NVB1C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB1C0_QMDV00_06_SASS_VERSION MW(1535:1528) +#define NVB1C0_QMDV00_06_QMD_SPARE_A MW(1567:1536) +#define NVB1C0_QMDV00_06_QMD_SPARE_B MW(1599:1568) +#define NVB1C0_QMDV00_06_QMD_SPARE_C MW(1631:1600) +#define NVB1C0_QMDV00_06_QMD_SPARE_D MW(1663:1632) +#define NVB1C0_QMDV00_06_QMD_SPARE_E MW(1695:1664) +#define NVB1C0_QMDV00_06_QMD_SPARE_F MW(1727:1696) +#define NVB1C0_QMDV00_06_QMD_SPARE_G MW(1759:1728) +#define NVB1C0_QMDV00_06_QMD_SPARE_H MW(1791:1760) +#define NVB1C0_QMDV00_06_QMD_SPARE_I MW(1823:1792) +#define NVB1C0_QMDV00_06_QMD_SPARE_J MW(1855:1824) +#define NVB1C0_QMDV00_06_QMD_SPARE_K MW(1887:1856) +#define NVB1C0_QMDV00_06_QMD_SPARE_L MW(1919:1888) +#define NVB1C0_QMDV00_06_QMD_SPARE_M MW(1951:1920) +#define NVB1C0_QMDV00_06_QMD_SPARE_N MW(1983:1952) +#define NVB1C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984) +#define NVB1C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 01_07 + */ + +#define NVB1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVB1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVB1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVB1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVB1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVB1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVB1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVB1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVB1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVB1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVB1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVB1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVB1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVB1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVB1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVB1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVB1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVB1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVB1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVB1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVB1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVB1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVB1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVB1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVB1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVB1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVB1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVB1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVB1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVB1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVB1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVB1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVB1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVB1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVB1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVB1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVB1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVB1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVB1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVB1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVB1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVB1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVB1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVB1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVB1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVB1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVB1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVB1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVB1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVB1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVB1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVB1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVB1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVB1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVB1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVB1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVB1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVB1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVB1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVB1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVB1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVB1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVB1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVB1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVB1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVB1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVB1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVB1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVB1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVB1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVB1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLB1C0QMD_H__ diff --git a/qmd/clc0c0qmd.h b/qmd/clc0c0qmd.h new file mode 100644 index 0000000..040bdcd --- /dev/null +++ b/qmd/clc0c0qmd.h @@ -0,0 +1,665 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC0C0QMD_H__ +#define __CLC0C0QMD_H__ + +/* +** Queue Meta Data, Version 01_07 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC0C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVC0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV01_07_INNER_GET MW(94:64) +#define NVC0C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVC0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC0C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVC0C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVC0C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC0C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_THROTTLED MW(372:372) +#define NVC0C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVC0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVC0C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVC0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVC0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVC0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVC0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVC0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVC0C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVC0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVC0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVC0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVC0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVC0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVC0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVC0C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVC0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC0C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVC0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVC0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_00 + */ + +#define NVC0C0_QMDV02_00_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV02_00_OUTER_GET MW(62:32) +#define NVC0C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV02_00_INNER_GET MW(94:64) +#define NVC0C0_QMDV02_00_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV02_00_INNER_PUT MW(126:96) +#define NVC0C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC0C0_QMDV02_00_QMD_GROUP_ID MW(197:192) +#define NVC0C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_IS_QUEUE MW(200:200) +#define NVC0C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_QMD_RESERVED_B MW(223:208) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC0C0_QMDV02_00_QMD_RESERVED_C MW(249:249) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV02_00_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_THROTTLED MW(372:372) +#define NVC0C0_QMDV02_00_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV02_00_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV02_00_QMD_RESERVED13A MW(447:432) +#define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) +#define NVC0C0_QMDV02_00_QMD_RESERVED14A MW(479:464) +#define NVC0C0_QMDV02_00_QMD_RESERVED15A MW(511:480) +#define NVC0C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV02_00_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV02_00_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV02_00_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_QMD_RESERVED_I MW(671:648) +#define NVC0C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV02_00_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_00_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV02_00_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_00_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC0C0_QMDV02_00_QMD_RESERVED_N MW(954:952) +#define NVC0C0_QMDV02_00_BARRIER_COUNT MW(959:955) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC0C0_QMDV02_00_REGISTER_COUNT MW(991:984) +#define NVC0C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC0C0_QMDV02_00_SASS_VERSION MW(1023:1016) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC0C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC0C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC0C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC0C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC0C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC0C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) +#define NVC0C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) +#define NVC0C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) +#define NVC0C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_01 + */ + +#define NVC0C0_QMDV02_01_OUTER_PUT MW(30:0) +#define NVC0C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) +#define NVC0C0_QMDV02_01_OUTER_GET MW(62:32) +#define NVC0C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC0C0_QMDV02_01_INNER_GET MW(94:64) +#define NVC0C0_QMDV02_01_INNER_OVERFLOW MW(95:95) +#define NVC0C0_QMDV02_01_INNER_PUT MW(126:96) +#define NVC0C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC0C0_QMDV02_01_QMD_GROUP_ID MW(133:128) +#define NVC0C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_IS_QUEUE MW(136:136) +#define NVC0C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_QMD_RESERVED_B MW(159:144) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC0C0_QMDV02_01_QMD_RESERVED_C MW(185:185) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC0C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC0C0_QMDV02_01_QMD_RESERVED_D MW(335:328) +#define NVC0C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC0C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_THROTTLED MW(372:372) +#define NVC0C0_QMDV02_01_THROTTLED_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_THROTTLED_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC0C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC0C0_QMDV02_01_SAMPLER_INDEX MW(382:382) +#define NVC0C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC0C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC0C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) +#define NVC0C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) +#define NVC0C0_QMDV02_01_QMD_RESERVED13A MW(447:432) +#define NVC0C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) +#define NVC0C0_QMDV02_01_QMD_RESERVED14A MW(479:464) +#define NVC0C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC0C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC0C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC0C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) +#define NVC0C0_QMDV02_01_QMD_RESERVED_G MW(575:562) +#define NVC0C0_QMDV02_01_QMD_VERSION MW(579:576) +#define NVC0C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) +#define NVC0C0_QMDV02_01_QMD_RESERVED_H MW(591:584) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC0C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_QMD_RESERVED_I MW(671:648) +#define NVC0C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC0C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC0C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC0C0_QMDV02_01_QMD_RESERVED_J MW(783:776) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_01_QMD_RESERVED_K MW(791:791) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) +#define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC0C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC0C0_QMDV02_01_QMD_RESERVED_L MW(879:872) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC0C0_QMDV02_01_QMD_RESERVED_M MW(887:887) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC0C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC0C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC0C0_QMDV02_01_QMD_RESERVED_N MW(954:952) +#define NVC0C0_QMDV02_01_BARRIER_COUNT MW(959:955) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC0C0_QMDV02_01_REGISTER_COUNT MW(991:984) +#define NVC0C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC0C0_QMDV02_01_SASS_VERSION MW(1023:1016) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC0C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) +#define NVC0C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) +#define NVC0C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC0C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC0C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC0C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC0C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC0C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC0C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC0C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) +#define NVC0C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) +#define NVC0C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) +#define NVC0C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) +#define NVC0C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) +#define NVC0C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) +#define NVC0C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) +#define NVC0C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) +#define NVC0C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) +#define NVC0C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC0C0QMD_H__ diff --git a/qmd/clc1c0qmd.h b/qmd/clc1c0qmd.h new file mode 100644 index 0000000..41f68a4 --- /dev/null +++ b/qmd/clc1c0qmd.h @@ -0,0 +1,665 @@ +/******************************************************************************* + Copyright (c) 2016 NVIDIA Corporation + + Permission is hereby granted, free of charge, to any person obtaining a copy + of this software and associated documentation files (the "Software"), to + deal in the Software without restriction, including without limitation the + rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + sell copies of the Software, and to permit persons to whom the Software is + furnished to do so, subject to the following conditions: + + The above copyright notice and this permission notice shall be + included in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + DEALINGS IN THE SOFTWARE. + +*******************************************************************************/ + +/* AUTO GENERATED FILE -- DO NOT EDIT */ + +#ifndef __CLC1C0QMD_H__ +#define __CLC1C0QMD_H__ + +/* +** Queue Meta Data, Version 01_07 + */ + +// The below C preprocessor definitions describe "multi-word" structures, where +// fields may have bit numbers beyond 32. For example, MW(127:96) means +// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)" +// syntax is to distinguish from similar "X:Y" single-word definitions: the +// macros historically used for single-word definitions would fail with +// multi-word definitions. +// +// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel +// interface layer of nvidia.ko for an example of how to manipulate +// these MW(X:Y) definitions. + +#define NVC1C0_QMDV01_07_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV01_07_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV01_07_OUTER_GET MW(62:32) +#define NVC1C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV01_07_INNER_GET MW(94:64) +#define NVC1C0_QMDV01_07_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV01_07_INNER_PUT MW(126:96) +#define NVC1C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC1C0_QMDV01_07_QMD_GROUP_ID MW(197:192) +#define NVC1C0_QMDV01_07_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_IS_QUEUE MW(200:200) +#define NVC1C0_QMDV01_07_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_QMD_RESERVED_B MW(223:208) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC1C0_QMDV01_07_QMD_RESERVED_C MW(249:249) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV01_07_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_THROTTLED MW(372:372) +#define NVC1C0_QMDV01_07_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376) +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000 +#define NVC1C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001 +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377) +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000 +#define NVC1C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001 +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379) +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000 +#define NVC1C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001 +#define NVC1C0_QMDV01_07_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383) +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000 +#define NVC1C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001 +#define NVC1C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432) +#define NVC1C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448) +#define NVC1C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480) +#define NVC1C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496) +#define NVC1C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV01_07_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV01_07_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV01_07_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_QMD_RESERVED_I MW(668:648) +#define NVC1C0_QMDV01_07_L1_CONFIGURATION MW(671:669) +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001 +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002 +#define NVC1C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003 +#define NVC1C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV01_07_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV01_07_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV01_07_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV01_07_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64)) +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64)) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440) +#define NVC1C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464) +#define NVC1C0_QMDV01_07_BARRIER_COUNT MW(1471:1467) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472) +#define NVC1C0_QMDV01_07_REGISTER_COUNT MW(1503:1496) +#define NVC1C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504) +#define NVC1C0_QMDV01_07_SASS_VERSION MW(1535:1528) +#define NVC1C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC1C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC1C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC1C0_QMDV01_07_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC1C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC1C0_QMDV01_07_QMD_SPARE_E MW(1695:1664) +#define NVC1C0_QMDV01_07_QMD_SPARE_F MW(1727:1696) +#define NVC1C0_QMDV01_07_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV01_07_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV01_07_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV01_07_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV01_07_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV01_07_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV01_07_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV01_07_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_00 + */ + +#define NVC1C0_QMDV02_00_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV02_00_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV02_00_OUTER_GET MW(62:32) +#define NVC1C0_QMDV02_00_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV02_00_INNER_GET MW(94:64) +#define NVC1C0_QMDV02_00_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV02_00_INNER_PUT MW(126:96) +#define NVC1C0_QMDV02_00_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV02_00_QMD_RESERVED_A_A MW(159:128) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_POINTER MW(191:160) +#define NVC1C0_QMDV02_00_QMD_GROUP_ID MW(197:192) +#define NVC1C0_QMDV02_00_SM_GLOBAL_CACHING_ENABLE MW(198:198) +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION MW(199:199) +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_IS_QUEUE MW(200:200) +#define NVC1C0_QMDV02_00_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201) +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0 MW(202:202) +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1 MW(203:203) +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS MW(204:204) +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE MW(206:206) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY MW(207:207) +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_QMD_RESERVED_B MW(223:208) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_SIZE MW(248:224) +#define NVC1C0_QMDV02_00_QMD_RESERVED_C MW(249:249) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252) +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE MW(253:253) +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE MW(254:254) +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255) +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV02_00_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV02_00_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_00_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_THROTTLED MW(372:372) +#define NVC1C0_QMDV02_00_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV02_00_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV02_00_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV02_00_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV02_00_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV02_00_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV02_00_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV02_00_QMD_RESERVED13A MW(447:432) +#define NVC1C0_QMDV02_00_CTA_RASTER_DEPTH MW(463:448) +#define NVC1C0_QMDV02_00_QMD_RESERVED14A MW(479:464) +#define NVC1C0_QMDV02_00_QMD_RESERVED15A MW(511:480) +#define NVC1C0_QMDV02_00_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV02_00_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV02_00_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV02_00_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV02_00_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV02_00_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV02_00_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV02_00_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_QMD_RESERVED_I MW(671:648) +#define NVC1C0_QMDV02_00_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV02_00_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV02_00_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV02_00_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV02_00_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_00_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV02_00_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV02_00_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV02_00_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_00_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_00_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_00_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC1C0_QMDV02_00_QMD_RESERVED_N MW(954:952) +#define NVC1C0_QMDV02_00_BARRIER_COUNT MW(959:955) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC1C0_QMDV02_00_REGISTER_COUNT MW(991:984) +#define NVC1C0_QMDV02_00_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC1C0_QMDV02_00_SASS_VERSION MW(1023:1016) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC1C0_QMDV02_00_HW_ONLY_INNER_GET MW(1566:1536) +#define NVC1C0_QMDV02_00_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567) +#define NVC1C0_QMDV02_00_HW_ONLY_INNER_PUT MW(1598:1568) +#define NVC1C0_QMDV02_00_HW_ONLY_SCG_TYPE MW(1599:1599) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600) +#define NVC1C0_QMDV02_00_QMD_RESERVED_Q MW(1630:1630) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631) +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_00_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_00_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632) +#define NVC1C0_QMDV02_00_CTA_RASTER_WIDTH_RESUME MW(1695:1664) +#define NVC1C0_QMDV02_00_CTA_RASTER_HEIGHT_RESUME MW(1711:1696) +#define NVC1C0_QMDV02_00_CTA_RASTER_DEPTH_RESUME MW(1727:1712) +#define NVC1C0_QMDV02_00_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV02_00_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV02_00_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV02_00_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV02_00_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV02_00_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV02_00_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV02_00_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV02_00_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV02_00_DEBUG_ID_LOWER MW(2047:2016) + + +/* +** Queue Meta Data, Version 02_01 + */ + +#define NVC1C0_QMDV02_01_OUTER_PUT MW(30:0) +#define NVC1C0_QMDV02_01_OUTER_OVERFLOW MW(31:31) +#define NVC1C0_QMDV02_01_OUTER_GET MW(62:32) +#define NVC1C0_QMDV02_01_OUTER_STICKY_OVERFLOW MW(63:63) +#define NVC1C0_QMDV02_01_INNER_GET MW(94:64) +#define NVC1C0_QMDV02_01_INNER_OVERFLOW MW(95:95) +#define NVC1C0_QMDV02_01_INNER_PUT MW(126:96) +#define NVC1C0_QMDV02_01_INNER_STICKY_OVERFLOW MW(127:127) +#define NVC1C0_QMDV02_01_QMD_GROUP_ID MW(133:128) +#define NVC1C0_QMDV02_01_SM_GLOBAL_CACHING_ENABLE MW(134:134) +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION MW(135:135) +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RUN_CTA_IN_ONE_SM_PARTITION_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_IS_QUEUE MW(136:136) +#define NVC1C0_QMDV02_01_IS_QUEUE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_IS_QUEUE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(137:137) +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0 MW(138:138) +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1 MW(139:139) +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS MW(140:140) +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE MW(141:141) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE MW(142:142) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE_QUEUE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_TYPE_GRID 0x00000001 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY MW(143:143) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_QMD_RESERVED_B MW(159:144) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_SIZE MW(184:160) +#define NVC1C0_QMDV02_01_QMD_RESERVED_C MW(185:185) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE MW(186:186) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(187:187) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE MW(188:188) +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE MW(189:189) +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE MW(190:190) +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE MW(191:191) +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CTA_RASTER_WIDTH_RESUME MW(223:192) +#define NVC1C0_QMDV02_01_CTA_RASTER_HEIGHT_RESUME MW(239:224) +#define NVC1C0_QMDV02_01_CTA_RASTER_DEPTH_RESUME MW(255:240) +#define NVC1C0_QMDV02_01_PROGRAM_OFFSET MW(287:256) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320) +#define NVC1C0_QMDV02_01_QMD_RESERVED_D MW(335:328) +#define NVC1C0_QMDV02_01_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_ID MW(357:352) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358) +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE MW(366:366) +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE MW(369:368) +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_NONE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001 +#define NVC1C0_QMDV02_01_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003 +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS MW(370:370) +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371) +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_THROTTLED MW(372:372) +#define NVC1C0_QMDV02_01_THROTTLED_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_THROTTLED_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT MW(378:378) +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT__32 0x00000000 +#define NVC1C0_QMDV02_01_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001 +#define NVC1C0_QMDV02_01_SAMPLER_INDEX MW(382:382) +#define NVC1C0_QMDV02_01_SAMPLER_INDEX_INDEPENDENTLY 0x00000000 +#define NVC1C0_QMDV02_01_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001 +#define NVC1C0_QMDV02_01_CTA_RASTER_WIDTH MW(415:384) +#define NVC1C0_QMDV02_01_CTA_RASTER_HEIGHT MW(431:416) +#define NVC1C0_QMDV02_01_QMD_RESERVED13A MW(447:432) +#define NVC1C0_QMDV02_01_CTA_RASTER_DEPTH MW(463:448) +#define NVC1C0_QMDV02_01_QMD_RESERVED14A MW(479:464) +#define NVC1C0_QMDV02_01_DEPENDENT_QMD_POINTER MW(511:480) +#define NVC1C0_QMDV02_01_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512) +#define NVC1C0_QMDV02_01_COALESCE_WAITING_PERIOD MW(529:522) +#define NVC1C0_QMDV02_01_SHARED_MEMORY_SIZE MW(561:544) +#define NVC1C0_QMDV02_01_QMD_RESERVED_G MW(575:562) +#define NVC1C0_QMDV02_01_QMD_VERSION MW(579:576) +#define NVC1C0_QMDV02_01_QMD_MAJOR_VERSION MW(583:580) +#define NVC1C0_QMDV02_01_QMD_RESERVED_H MW(591:584) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION0 MW(607:592) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION1 MW(623:608) +#define NVC1C0_QMDV02_01_CTA_THREAD_DIMENSION2 MW(639:624) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_QMD_RESERVED_I MW(671:648) +#define NVC1C0_QMDV02_01_SM_DISABLE_MASK_LOWER MW(703:672) +#define NVC1C0_QMDV02_01_SM_DISABLE_MASK_UPPER MW(735:704) +#define NVC1C0_QMDV02_01_RELEASE0_ADDRESS_LOWER MW(767:736) +#define NVC1C0_QMDV02_01_RELEASE0_ADDRESS_UPPER MW(775:768) +#define NVC1C0_QMDV02_01_QMD_RESERVED_J MW(783:776) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP MW(790:788) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_01_QMD_RESERVED_K MW(791:791) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT MW(793:792) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE MW(794:794) +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE MW(799:799) +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE0_PAYLOAD MW(831:800) +#define NVC1C0_QMDV02_01_RELEASE1_ADDRESS_LOWER MW(863:832) +#define NVC1C0_QMDV02_01_RELEASE1_ADDRESS_UPPER MW(871:864) +#define NVC1C0_QMDV02_01_QMD_RESERVED_L MW(879:872) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP MW(886:884) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_INC 0x00000003 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_AND 0x00000005 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_OR 0x00000006 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007 +#define NVC1C0_QMDV02_01_QMD_RESERVED_M MW(887:887) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT MW(889:888) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE MW(890:890) +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE MW(895:895) +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 +#define NVC1C0_QMDV02_01_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001 +#define NVC1C0_QMDV02_01_RELEASE1_PAYLOAD MW(927:896) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_LOW_SIZE MW(951:928) +#define NVC1C0_QMDV02_01_QMD_RESERVED_N MW(954:952) +#define NVC1C0_QMDV02_01_BARRIER_COUNT MW(959:955) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(983:960) +#define NVC1C0_QMDV02_01_REGISTER_COUNT MW(991:984) +#define NVC1C0_QMDV02_01_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1015:992) +#define NVC1C0_QMDV02_01_SASS_VERSION MW(1023:1016) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_ADDR_LOWER(i) MW((1055+(i)*64):(1024+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_ADDR_UPPER(i) MW((1072+(i)*64):(1056+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((1073+(i)*64):(1073+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE(i) MW((1074+(i)*64):(1074+(i)*64)) +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_CONSTANT_BUFFER_SIZE_SHIFTED4(i) MW((1087+(i)*64):(1075+(i)*64)) +#define NVC1C0_QMDV02_01_QMD_RESERVED_R MW(1567:1536) +#define NVC1C0_QMDV02_01_QMD_RESERVED_S MW(1599:1568) +#define NVC1C0_QMDV02_01_HW_ONLY_INNER_GET MW(1630:1600) +#define NVC1C0_QMDV02_01_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1631:1631) +#define NVC1C0_QMDV02_01_HW_ONLY_INNER_PUT MW(1662:1632) +#define NVC1C0_QMDV02_01_HW_ONLY_SCG_TYPE MW(1663:1663) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1693:1664) +#define NVC1C0_QMDV02_01_QMD_RESERVED_Q MW(1694:1694) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1695:1695) +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000 +#define NVC1C0_QMDV02_01_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001 +#define NVC1C0_QMDV02_01_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1727:1696) +#define NVC1C0_QMDV02_01_QMD_SPARE_G MW(1759:1728) +#define NVC1C0_QMDV02_01_QMD_SPARE_H MW(1791:1760) +#define NVC1C0_QMDV02_01_QMD_SPARE_I MW(1823:1792) +#define NVC1C0_QMDV02_01_QMD_SPARE_J MW(1855:1824) +#define NVC1C0_QMDV02_01_QMD_SPARE_K MW(1887:1856) +#define NVC1C0_QMDV02_01_QMD_SPARE_L MW(1919:1888) +#define NVC1C0_QMDV02_01_QMD_SPARE_M MW(1951:1920) +#define NVC1C0_QMDV02_01_QMD_SPARE_N MW(1983:1952) +#define NVC1C0_QMDV02_01_DEBUG_ID_UPPER MW(2015:1984) +#define NVC1C0_QMDV02_01_DEBUG_ID_LOWER MW(2047:2016) + + + +#endif // #ifndef __CLC1C0QMD_H__ diff --git a/virtual-p-state-table/virtual-P-state-table.html b/virtual-p-state-table/virtual-P-state-table.html new file mode 100644 index 0000000..af9bc50 --- /dev/null +++ b/virtual-p-state-table/virtual-P-state-table.html @@ -0,0 +1,1004 @@ + + + + + +NVIDIA Virtual P-state Table Specification + + + + + +
+
+

Purpose

+
+

This document describes the Virtual P-state (vP-state) Table in the NVIDIA VBIOS.

+

The Virtual P-state (vP-state) Table maps discreet points on the Voltage/Frequency curve to vP-states. +These vP-states are typically used as caps (limits).

+
+ + + +
+
Note
+		This specification only provides the details about vP-state entry which is required to fetch base clock.
+
+
+
+
+

Virtual P-state Table

+
+

The Virtual P-state Table starts with a header, followed immediately by an array of entries.

+

It consist of following sections:

+
    +
  • +

    +Header – The version number, header size, size of each vP-state entry, number of vP-state entries, etc. +

    +
    • +
  • +

    +Entry – One for each vP-state. It consist of associated P-state. +

    +
    • +
  • +

    +Domain frequencies – Sub-table in vP-state entry table consisting of limits for domain frequencies. +

    +
    • +
+

The vP-state table is a part of BIOS information table’s (BIT) Performance table entry (ID = ‘P’ i.e. 0x50 and version = 2) +and its location is extracted by reading 32 bit dword from an offset 0x38 from the performance table (refer to sample code).

+
+

Virtual P-state Table Version

+

This document describes vP-state table version 1.0 which is supported only on GPU families GF11X through GM20X +(i.e. NVC0 through NV110 families as per nouveau’s code names).

+
+ + + +
+
Note
+		Table version and structure will change in Pascal and later GPUs.
+
+
+
+

Virtual P-state Table Header Structure

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Name Bit width Meaning and (Values)

Version

8

Virtual P-state Table Version (0x10)

Header Size

8

Size of Virtual P-state Table Header in bytes (20)

Base Entry Size

8

Size of Virtual P-state Table Entry in bytes, not including the domain frequencies (5)

Domain Freq Size

8

Size of each Virtual P-state Domain Frequency Entry in bytes (2)

Domain Freq Count

8

Number of Virtual P-state Domain Frequencies allocated

Entry Count

8

Number of Virtual P-state Table Entries

Reserved

88

Index of Rated TDP vP-state (Base Clock)

8

Fastest thermally sustainable vP-state for the TDP app on worst case silicon, worst case conditions (also known as base clock)

Reserved

40

+
+
+
+

Virtual P-state Table Entry Structure

+
+ ++++ + + + + + + + + + + + + + + + + + + +
Name Bit width Values and Meaning

P-state

8

P-state associated with this vP-state. A value of 0xff indicates SKIP ENTRY.

Reserved

32

+
+
+
+

Virtual P-state Domain Frequency Entry Structure

+

This is a sub-table in Virtual P-state Table Entry. Domain frequency entries are indexed as per clock domain enumeration.

+
+ ++++ + + + + + + + + + + + + + +
Name Bit width Values and Meaning

Domain Frequency

16

Domain frequency associated with this vP-state in MHz. A value of 0 indicates that vP-states do not specify a limit for this domain.

+
+

It is safe to assume that there will always be one domain frequency entry per vP-state table entry. Non-zero value of this entry belongs to GPC clock domain.

+
+
+
+
+

Sample code

+
+

Sample code to read base clock from vP-state table.

+
+ + + +
+
Note
+		this code is based on nouveau driver which is capable of reading various entries from BIT.
+
+
+
+
    1: void read_vpstate_table(struct nvkm_bios *bios)
+    2: {
+    3:         struct bit_entry bit_P;
+    4:         u16 vpstate_tbl = 0x0000, offset, domain_clk;
+    5:         u8 ver, i, hdr_size, base_entry_size, domain_freq_size, domain_freq_count, base_clk_idx;
+    6:
+    7:         if (!bit_entry(bios, 'P', &bit_P)) {
+    8:                 if (bit_P.version == 2)
+    9:                         vpstate_tbl = nvbios_rd16(bios, bit_P.offset + 0x38);
+   10:                 else
+   11:                         return;
+   12:
+   13:                 if (vpstate_tbl) {
+   14:                         ver = nvbios_rd08(bios, vpstate_tbl + 0);
+   15:                         printk("vP-state entry version = 0x%x\n", ver);
+   16:                         switch (ver) {
+   17:                         case 0x10:
+   18:                                 printk("vP-state header size = %d\n",
+   19:                                         hdr_size = nvbios_rd08(bios, vpstate_tbl + 1));
+   20:                                 printk("base entry size = %d\n",
+   21:                                         base_entry_size = nvbios_rd08(bios, vpstate_tbl + 2));
+   22:                                 printk("domain freq entry size = %d\n",
+   23:                                         domain_freq_size = nvbios_rd08(bios, vpstate_tbl + 3));
+   24:                                 printk("domain freq entries count = %d\n",
+   25:                                         domain_freq_count = nvbios_rd08(bios, vpstate_tbl + 4));
+   26:
+   27:
+   28:                                 base_clk_idx = nvbios_rd08(bios, vpstate_tbl + 17);
+   29:                                 printk("base clk index = %d\n", base_clk_idx);
+   30:
+   31:
+   32:                                 offset = vpstate + hdr_size +
+   33:                                         ((base_entry_size + (domain_freq_size * domain_freq_count)) * base_clk);
+   34:                                 printk("offset = %d\n", offset);
+   35:
+   36:
+   37:                                 printk("p-state for base clk = %d",
+   38:                                         nvbios_rd08(bios, offset + 0));
+   39:
+   40:                                 for (i = 0; i < domain_freq_count; i++) {
+   41:                                         domain_clk = nvbios_rd16(bios, offset + base_entry_size +
+   42:                                                                  (i * domain_freq_size));
+   43:                                         printk("domain clock index = %d, domain clock limit value = %d MHz\n",
+   44:                                                 i, domain_clk);
+   45:                                 }
+   46:
+   47:                                 return;
+   48:                         default:
+   49:                                 return;
+   50:                         }
+   51:                 }
+   52:         }
+   53:
+   54:         return;
+   55: }
+
+
+
+
+ + + -- cgit v1.2.3