From 60b67c31fcad6d0dc9603a034994a12efe3d5202 Mon Sep 17 00:00:00 2001 From: John Hubbard Date: Sun, 21 Apr 2019 17:09:24 -0700 Subject: Open doc files, version 1 of everything This copies over files from: http://download.nvidia.com/open-gpu-doc/ with a few overrides from local, as-yet-to-be-published files (generally just a file suffix and licensing tweak). Here's the script that was used to create this commit: wget -r http://download.nvidia.com/open-gpu-doc/ mv download.nvidia.com/open-gpu-doc/* . rm -rf download.nvidia.com/ find . -name index.html | xargs rm -f find . -name Thumbs.db | xargs rm -f find . -type f | grep -v \.git | xargs file | grep CRLF | cut -f1 -d: | xargs dos2unix for f in `find . -name 1 | cut -f2 -d "/"`; do pushd $f; mv 1/* .; popd; done find . -name 1 | xargs rmdir rm -rf Host-Fifo/volta/gv100 mkdir -p Host-Fifo/volta/gv100 cp $sw/docs/Public_Devel_Docs/release/Host-Fifo/volta/gv100/* Host-Fifo/volta/gv100/ rm Display-Ref-Manuals/gv100/dev_display.ref cp $sw/docs/Public_Devel_Docs/release/Display-Ref-Manuals/1/gv100/dev_display.ref \ Display-Ref-Manuals/gv100/dev_display.ref.txt git add . git mv DCB/DCB-4.0-Specification.html DCB/DCB-4.x-Specification.html git reset HEAD Display-Class-Methods/2 git reset HEAD DCB/2 git commit Reviewed-by: Andy Ritger --- MemoryClockTable/MemoryClockTable.html | 711 +++++++++++++++++++++++++++++++++ 1 file changed, 711 insertions(+) create mode 100644 MemoryClockTable/MemoryClockTable.html (limited to 'MemoryClockTable/MemoryClockTable.html') diff --git a/MemoryClockTable/MemoryClockTable.html b/MemoryClockTable/MemoryClockTable.html new file mode 100644 index 0000000..d995e11 --- /dev/null +++ b/MemoryClockTable/MemoryClockTable.html @@ -0,0 +1,711 @@ + + + + + +NVIDIA Memory Clock Table Specifications + + + + +
+
+
+
+

Purpose

+
+

This document describes the VBIOS Memory clock table entries. +The Memory Clock Table starts with a header, followed immediately by an array of entries.

+

Memory Clock Table Header

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldName Size (in bits) Description

Version

8

+
+Memory Clock Table Version (0x11) +
+
+
+

Header Size

8

+
+Size of Memory Clock Table Header in bytes (26) +
+
+
+

Base Entry Size

8

+
+Size of Memory Clock Table Base Entry in bytes (20) +
+
+
+

Strap Entry Size

8

+
+Size of Memory Clock Table Strap Entry in bytes (26) +
+
+
+

Strap Entry Count

8

+
+Number of Memory Clock Table Strap Entries per Memory Clock Table Entry +
+
+
+

Entry Count

8

+
+Number of Memory Clock Table Entries (combined Base Entry plus Strap Entry Count of Strap Entries) +
+
+
+

Reserved

160

+
+

Memory Clock Table Base Entry

+

Each entry is made up of a single Base Entry and multiple Strap Entries. The entire size of an entry is given by ( MemoryClockTableHeader.BaseEntrySize + MemoryClockTableHeader.StrapEntrySize × MemoryClockTableHeader.StrapEntryCount ). Each entry provides information needed for operating the memory at a frequency between MemoryClockTableBaseEntry.Minimum.Frequency and MemoryClockTableBaseEntry.Maximum.Frequency, inclusively.

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldName Size (in bits) Description

Min Frequency

16

+
+[15:14] = Reserved +
+
+[13:0] = Frequency (MHz) +
+
+
+

Max Frequency

16

+
+[15:14] = Reserved +
+
+[13:0] = Frequency(MHz) +
+
+
+

Reserved

40

Read/Write Config0

32

+
+[8:0] = Read Setting0 +
+
+[17:9] = Write Settings0 +
+
+[19:18] = Reserved +
+
+[24:20] = ReadSettings1 +
+
+[31:25] = Reserved +
+
+
+

Read/Write Config1

32

+
+[3:0] = Read Settings0 +
+
+[7:4] = Write Settings0 +
+
+[11:8] = Read Settings1 +
+
+[15:12] = Write Settings1 +
+
+[19:16] = Read Settings2 +
+
+[23:20] = Write Settings2 +
+
+[31:24] = Timing Settings0 +
+
+
+

Reserved

24

+
+

Memory Clock Table Strap Entry

+
+ ++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FieldName Size (in bits) Description

MemTweak Index

8

+
+[7:0] MemTweak Index +
+
+
+

Flags0

8

+
+[6:0] = Reserved +
+
+[7:7] = Alignment Mode +
+
+

+ 0x0 = Phase detector (Default)
+ 0x1 = Pin +

+
+

Reserved

48

Flags4

8

+
+[6:0] = Reserved +
+
+[7:7] = MRS7 GDDR5 +
+
+

+ 0x0 = Disable (Default)
+ 0x1 = Enable +

+
+

Reserved

8

Flags5

8

+
+[5:0] = Reserved +
+
+[6:6] = GDDR5x Internal VrefC +
+
+

+ 0x0 = Disable (Default) (70% VrefC)
+ 0x1 = Enable (50% VrefC) +

+
+
+[7:7] = Reserved +
+
+
+

Reserved

120

+
+
+ + + -- cgit v1.2.3