path: root/Display-Ref-Manuals/gv100/dev_display.ref.txt

Copyright (c) 2018 NVIDIA Corporation

Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
deal in the Software without restriction, including without limitation the
rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
sell copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be
included in all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
--------------------------------------------------------------------------------

#define NV_PDISP_FE                                                0x00615FFF:0x00610000 /* RW--D */
#define NV_PDISP_HEADS                                                                 8 /*       */
#define NV_PDISP_SORS                                                                  8 /*       */
#define NV_PDISP_PIORS                                                                 4 /*       */
#define NV_PDISP_MAX_HEAD                                                             4 /*       */
#define NV_PDISP_MAX_DAC                                                              0 /*       */
#define NV_PDISP_MAX_SOR                                                              4 /*       */
#define NV_PDISP_MAX_PIOR                                                             3 /*       */
#define NV_PDISP_CHANNELS                                                             84 /*       */
#define NV_PDISP_CHN_NUM_CORE                                                          0 /*       */
#define NV_PDISP_CHN_NUM_WIN(i)                                                  (1+(i)) /*       */
#define NV_PDISP_CHN_NUM_WIN__SIZE_1                                                  32 /*       */
#define NV_PDISP_CHN_NUM_WINIM(i)                                               (33+(i)) /*       */
#define NV_PDISP_CHN_NUM_WINIM__SIZE_1                                                32 /*       */
#define NV_PDISP_CHN_NUM_CURS(i)                                                (73+(i)) /*       */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1                                                  8 /*       */
#define NV_PDISP_CHN_NUM_PCALC                                                        82 /*       */
#define NV_PDISP_CHN_NUM_SUPERVISOR                                                   83 /*       */
#define NV_PDISP_EXCEPT_CHN_NUM_CORE                                                   0 /*       */
#define NV_PDISP_EXCEPT_CHN_NUM_WIN(i)                                           (1+(i)) /*       */
#define NV_PDISP_EXCEPT_CHN_NUM_WIN__SIZE_1                                           32 /*       */
#define NV_PDISP_FE_CLASSES                                                   0x00610000 /* R--4R */
#define NV_PDISP_FE_CLASSES_HW_REV                                                   3:0 /* R--UF */
#define NV_PDISP_FE_CLASSES_API_REV                                                  7:4 /* R--UF */
#define NV_PDISP_FE_CLASSES_CLASS_REV                                               15:8 /* R--UF */
#define NV_PDISP_FE_CLASSES_CLASS_ID                                               31:16 /* R--UF */
#define NV_PDISP_FE_CLASSES_0                                            3278897936 /*       */
#define NV_PDISP_FE_INST_MEM0                                                 0x00610010 /* RW-4R */
#define NV_PDISP_FE_INST_MEM0_TARGET                                                 1:0 /* RWIVF */
#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_INIT                                0x00000001 /* RWI-V */
#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_NVM                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_PCI                                 0x00000002 /* RW--V */
#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_PCI_COHERENT                        0x00000003 /* RW--V */
#define NV_PDISP_FE_INST_MEM0_STATUS                                                 3:3 /* RWIVF */
#define NV_PDISP_FE_INST_MEM0_STATUS_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_INST_MEM0_STATUS_INVALID                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_INST_MEM0_STATUS_VALID                                    0x00000001 /* RW--V */
#define NV_PDISP_FE_INST_MEM1                                                 0x00610014 /* RW-4R */
#define NV_PDISP_FE_INST_MEM1_ADDR                                                  30:0 /* RWIUF */
#define NV_PDISP_FE_INST_MEM1_ADDR_INIT                                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_IP_VER                                                    0x00610018 /* R--4R */
#define NV_PDISP_FE_IP_VER_DEV                                                       7:0 /* R-IVF */
#define NV_PDISP_FE_IP_VER_DEV_INIT                                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_IP_VER_ECO                                                      15:8 /* R-IVF */
#define NV_PDISP_FE_IP_VER_ECO_INIT                                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_IP_VER_MINOR                                                   23:16 /* R-IVF */
#define NV_PDISP_FE_IP_VER_MINOR_INIT                                         0x00000001 /* R-I-V */
#define NV_PDISP_FE_IP_VER_MAJOR                                                   31:24 /* R-IVF */
#define NV_PDISP_FE_IP_VER_MAJOR_INIT                                         0x00000003 /* R-I-V */
#define NV_PDISP_FE_ACQ_DELAY                                                 0x00610040 /* RW-4R */
#define NV_PDISP_FE_ACQ_DELAY_SEMA                                                   7:0 /* RWIUF */
#define NV_PDISP_FE_ACQ_DELAY_SEMA_INIT                                       0x0000000a /* RWI-V */
#define NV_PDISP_FE_ACQ_DELAY_SEMA_10US                                       0x0000000a /* RW--V */
#define NV_PDISP_FE_ACQ_DELAY_SYNCPT                                                15:8 /* RWIUF */
#define NV_PDISP_FE_ACQ_DELAY_SYNCPT_INIT                                     0x0000000a /* RWI-V */
#define NV_PDISP_FE_ACQ_DELAY_SYNCPT_10US                                     0x0000000a /* RW--V */
#define NV_PDISP_FE_HW_SYS_CAP                                                0x00610060 /* R--4R */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS                                          0:0 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS                                          1:1 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS                                          2:2 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS                                          3:3 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS                                          4:4 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS                                          5:5 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS                                          6:6 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS                                          7:7 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i)                            (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1                                     8 /*       */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS                                           8:8 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS                                           9:9 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS                                         10:10 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS                                         11:11 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS                                         12:12 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS                                         13:13 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS                                         14:14 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS                                         15:15 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS_NO                                 0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS_YES                                0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS(i)                             (8+(i)):(8+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS__SIZE_1                                      8 /*       */
#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS_NO                                  0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS_YES                                 0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB                                                0x00610064 /* R--4R */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS                                        0:0 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS                                        1:1 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS                                        2:2 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS                                        3:3 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS                                        4:4 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS                                        5:5 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS                                        6:6 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS                                        7:7 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS                                        8:8 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS                                        9:9 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS                                     10:10 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS                                     11:11 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS                                     12:12 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS                                     13:13 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS                                     14:14 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS                                     15:15 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS                                     16:16 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS                                     17:17 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS                                     18:18 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS                                     19:19 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS                                     20:20 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS                                     21:21 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS                                     22:22 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS                                     23:23 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS                                     24:24 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS                                     25:25 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS                                     26:26 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS                                     27:27 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS                                     28:28 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS                                     29:29 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS                                     30:30 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS                                     31:31 /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS(i)                          (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS__SIZE_1                                  32 /*       */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS_NO                               0x00000000 /* R---V */
#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS_YES                              0x00000001 /* R---V */
#define NV_PDISP_FE_HW_LOCK_PIN_CAP                                           0x00610068 /* R--4R */
#define NV_PDISP_FE_HW_LOCK_PIN_CAP_FLIP_LOCK_PINS                                   3:0 /* R--UF */
#define NV_PDISP_FE_HW_LOCK_PIN_CAP_SCAN_LOCK_PINS                                   7:4 /* R--UF */
#define NV_PDISP_FE_HW_LOCK_PIN_CAP_STEREO_PINS                                     11:8 /* R--UF */
#define NV_PDISP_FE_MISC_CONFIGA                                              0x00610074 /* R--4R */
#define NV_PDISP_FE_MISC_CONFIGA_NUM_HEADS                                           3:0 /* R--UF */
#define NV_PDISP_FE_MISC_CONFIGA_NUM_SORS                                           11:8 /* R--UF */
#define NV_PDISP_FE_MISC_CONFIGA_NUM_WINDOWS                                       25:20 /* R--UF */
#define NV_PDISP_FE_LOCK_CAPS                                                 0x00610078 /* RWI4R */
#define NV_PDISP_FE_LOCK_CAPS_LOCK                                                   0:0 /* RWIVF */
#define NV_PDISP_FE_LOCK_CAPS_LOCK_INIT                                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_LOCK_CAPS_LOCK_UNLOCKED                                   0x00000000 /* RW--V */
#define NV_PDISP_FE_LOCK_CAPS_LOCK_LOCKED                                     0x00000001 /* RW--V */
#define NV_PDISP_FE_TRAP(i)                                           (0x00610360+(i)*4) /* RW-4A */
#define NV_PDISP_FE_TRAP__SIZE_1                                                      32 /*       */
#define NV_PDISP_FE_TRAP_METHOD                                                     13:2 /* RWIUF */
#define NV_PDISP_FE_TRAP_METHOD_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_TRAP_CHN_NUM                                                   22:16 /* RWIUF */
#define NV_PDISP_FE_TRAP_CHN_NUM_INIT                                         0x00000000 /* RWI-V */
#define NV_PDISP_FE_TRAP_CHN_TYPE                                                  22:16 /* RWIUF */
#define NV_PDISP_FE_TRAP_CHN_TYPE_INIT                                        0x00000000 /* RWI-V */
#define NV_PDISP_FE_TRAP_CHN_TYPE_CORE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_TRAP_CHN_TYPE_WIN                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_TRAP_CHN_TYPE_WRBK                                        0x00000002 /* RW--V */
#define NV_PDISP_FE_TRAP_MODE                                                      30:28 /* RWIVF */
#define NV_PDISP_FE_TRAP_MODE_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_TRAP_MODE_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_TRAP_MODE_METHOD_CHANNEL                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_TRAP_MODE_METHOD_CHANNEL_TYPE                             0x00000002 /* RW--V */
#define NV_PDISP_FE_TRAP_MODE_ALL_CHANNEL                                     0x00000003 /* RW--V */
#define NV_PDISP_FE_TRAP_MODE_ALL_CHANNEL_TYPE                                0x00000004 /* RW--V */
#define NV_PDISP_FE_ERRMASK(i)                                        (0x006103E0+(i)*8) /* RW-4A */
#define NV_PDISP_FE_ERRMASK__SIZE_1                                                   32 /*       */
#define NV_PDISP_FE_ERRMASK_METHOD                                                  13:2 /* RWIUF */
#define NV_PDISP_FE_ERRMASK_METHOD_INIT                                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_ERRMASK_CHN_MODE                                               16:16 /* RWIUF */
#define NV_PDISP_FE_ERRMASK_CHN_MODE_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_ERRMASK_CHN_MODE_INSTANCE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_ERRMASK_CHN_MODE_TYPE                                     0x00000001 /* RW--V */
#define NV_PDISP_FE_ERRMASK_CHN_NUM                                                26:20 /* RWIUF */
#define NV_PDISP_FE_ERRMASK_CHN_NUM_INIT                                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_ERRMASK_CHN_TYPE                                               26:20 /* RWIUF */
#define NV_PDISP_FE_ERRMASK_CHN_TYPE_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_ERRMASK_CHN_TYPE_CORE                                     0x00000000 /* RW--V */
#define NV_PDISP_FE_ERRMASK_CHN_TYPE_WIN                                      0x00000001 /* RW--V */
#define NV_PDISP_FE_ERRMASK_CHN_TYPE_WRBK                                     0x00000002 /* RW--V */
#define NV_PDISP_FE_ERRMASK_MODE                                                   31:29 /* RWIVF */
#define NV_PDISP_FE_ERRMASK_MODE_INIT                                         0x00000000 /* RWI-V */
#define NV_PDISP_FE_ERRMASK_MODE_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_ERRMASK_MODE_ALL                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_ERRMASK_MODE_ALL_ARG                                      0x00000002 /* RW--V */
#define NV_PDISP_FE_ERRMASK_MODE_ALL_STATE                                    0x00000003 /* RW--V */
#define NV_PDISP_FE_ERRMASK_MODE_METHOD_ARG                                   0x00000004 /* RW--V */
#define NV_PDISP_FE_ERRMASK_MODE_STATE_CODE                                   0x00000005 /* RW--V */
#define NV_PDISP_FE_ERRMASKCODE(i)                                    (0x006103E4+(i)*8) /* RW-4A */
#define NV_PDISP_FE_ERRMASKCODE__SIZE_1                                               32 /*       */
#define NV_PDISP_FE_ERRMASKCODE_CODE                                                23:0 /* RWIUF */
#define NV_PDISP_FE_ERRMASKCODE_CODE_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_ERRMASKCODE_CODE_NONE                                     0x00000000 /* RW--V */
#define NV_PDISP_FE_ERRMASKCODE_MASK_SIZE                                          28:24 /* RWIUF */
#define NV_PDISP_FE_ERRMASKCODE_MASK_SIZE_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE                                               0x006104E0 /* RW-4R */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION                                           0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_DEALLOCATE                         0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_ALLOCATE                           0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION                                           1:1 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_DISCONNECT                         0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_CONNECT                            0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE                                         4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_DISABLE                          0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_ENABLE                           0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_EFI                                                  5:5 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_EFI_INIT                                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_EFI_DISABLE                                   0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_EFI_ENABLE                                    0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF                                           9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_DISABLE                            0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_ENABLE                             0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK                                   11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_INIT                         0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED                         12:12 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_NO                 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_YES                0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE                                         14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_DISABLE                            0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_ONLY                         0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_AND_ABORT                    0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN                                 15:15 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_DISABLE                    0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_ENABLE                     0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN(i)                                     (0x006104E4+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WIN__SIZE_1                                                32 /*       */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION                                            0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_DEALLOCATE                          0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_ALLOCATE                            0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION                                            1:1 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_DISCONNECT                          0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_CONNECT                             0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE                                          4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_DISABLE                           0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_ENABLE                            0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT                                        6:6 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_DISABLE                         0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_ENABLE                          0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP                                      7:7 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_DISABLE                       0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_ENABLE                        0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI                                             8:8 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_DISABLE                              0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_ENABLE                               0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF                                            9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_DISABLE                             0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_ENABLE                              0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA                                           10:10 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_DISABLE                              0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_ENABLE                               0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK                                    11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_DISABLE                       0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_ENABLE                        0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE                                          14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_DISABLE                             0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_ONLY                          0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_AND_ABORT                     0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM(i)                                   (0x00610564+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WINIM__SIZE_1                                              32 /*       */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION                                          0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_DEALLOCATE                        0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_ALLOCATE                          0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION                                          1:1 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_DISCONNECT                        0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_CONNECT                           0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE                                        4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_DISABLE                         0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_ENABLE                          0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK                                  11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_INIT                        0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_DISABLE                     0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_ENABLE                      0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE                                        14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_DISABLE                           0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_ONLY                        0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_AND_ABORT                   0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS(i)                                    (0x00610604+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_CURS__SIZE_1                                                8 /*       */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION                                           0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_DEALLOCATE                         0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_ALLOCATE                           0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO                                        4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_DISABLE                         0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_ENABLE                          0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK                                   11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_INIT                         0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE                                         14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_DISABLE                            0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_ONLY                         0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_AND_ABORT                    0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNSTATUS_CORE                                            0x00610630 /* R--4R */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE                                        3:0 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_INIT                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_IDLE                            0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_READ_METHOD                     0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_REQ_METHOD_INFO                 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CHK_METHOD_INFO                 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CHK_CTXDMA                      0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CTX_DMA_LOOKUP                  0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_WAIT_FOR_STG2                   0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_WAIT_FOR_UPD                    0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_EXCEPTION                       0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE                                        7:4 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_INIT                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_IDLE                            0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_PUBLIC                     0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_MISC                       0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_LIMIT                      0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_BASE                       0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_SETPARAMSCRSR              0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE                                           20:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC                              0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC_LIMBO                        0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT1                          0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT2                          0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_OPERATION                      0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT1                            0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT2                            0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_OPERATION                        0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_UNCONNECTED                          0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT1                                0x00000009 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT2                                0x0000000A /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_IDLE                                 0x0000000B /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_BUSY                                 0x0000000C /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN1                            0x0000000D /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN2                            0x0000000E /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME                                       24:24 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_INIT                             0x00000001 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_NO                               0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_YES                              0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO                              25:25 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_INIT                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_EMPTY                   0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_NOTEMPTY                0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING                             26:26 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_INIT                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_NO                     0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_YES                    0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING                      27:27 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_INIT            0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_NO              0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_YES             0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS                                29:29 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_INIT                      0x00000001 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_INACTIVE                  0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_ACTIVE                    0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT                                30:30 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_INIT                      0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_NO                        0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_YES                       0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC                              31:31 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_INIT                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_IDLE                    0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_RUNNING                 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN(i)                                  (0x00610664+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WIN__SIZE_1                                             32 /*       */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE                                         3:0 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_INIT                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_IDLE                             0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_READ_METHOD                      0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_REQ_METHOD_INFO                  0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CHK_METHOD_INFO                  0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CHK_CTXDMA                       0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CTX_DMA_LOOKUP                   0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_WAIT_FOR_STG2                    0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_WAIT_FOR_UPD                     0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_EXCEPTION                        0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE                                         7:4 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_INIT                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_IDLE                             0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_PUBLIC                      0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_MISC                        0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_LIMIT                       0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_BASE                        0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_WIN_SETCONFIG               0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE                                         11:8 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_INIT                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_IDLE                              0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_BLOCK                        0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_MPI                          0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_PH_1                     0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_STATE_ERRCHK                 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_RDY_TO_FLIP                  0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_PH_2                     0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_CHECK_PEND_LOADV                  0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_SEND_UPD                          0x00000009 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_PRM                          0x0000000a /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_EXCEPTION                         0x0000000b /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_ABORT                    0x0000000c /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE                                            19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_DEALLOC                               0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_UNCONNECTED                           0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT1                                 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT2                                 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_IDLE                                  0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_BUSY                                  0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN1                             0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN2                             0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME                                        24:24 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_INIT                              0x00000001 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_NO                                0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_YES                               0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO                               25:25 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_INIT                     0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_EMPTY                    0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_NOTEMPTY                 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING                              26:26 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_INIT                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_NO                      0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_YES                     0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING                             27:27 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_INIT                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_NO                     0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_YES                    0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS                                 29:29 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_INIT                       0x00000001 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_INACTIVE                   0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_ACTIVE                     0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT                                 30:30 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_INIT                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_NO                         0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_YES                        0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC                               31:31 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_INIT                     0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_IDLE                     0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_RUNNING                  0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM(i)                                (0x006106E4+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WINIM__SIZE_1                                           32 /*       */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE                                         3:0 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_INIT                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_IDLE                             0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_EXCEPT                           0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_SEND_PUBLIC                      0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_ILK1                        0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_FLIP                        0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_ILK2                        0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_LOADV                       0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_SEND_UPDATE                      0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_PRM                         0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE                                          19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_DEALLOC                             0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_UNCONNECTED                         0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT1                               0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT2                               0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_IDLE                                0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_BUSY                                0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN1                           0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN2                           0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME                                      24:24 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_INIT                            0x00000001 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_NO                              0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_YES                             0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO                             25:25 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_INIT                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_EMPTY                  0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_NOTEMPTY               0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING                            26:26 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_INIT                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_NO                    0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_YES                   0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING                           27:27 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_INIT                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_NO                   0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_YES                  0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS                               29:29 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_INIT                     0x00000001 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_INACTIVE                 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_ACTIVE                   0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT                               30:30 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_INIT                     0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_NO                       0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_YES                      0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC                             31:31 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_INIT                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_IDLE                   0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_RUNNING                0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS(i)                                 (0x00610784+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_CURS__SIZE_1                                             8 /*       */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE                                          3:0 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_INIT                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_IDLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_PBERR                             0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_RSVD                              0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_SND_PUBLIC                        0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_WAIT_PUBLIC                       0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK1_START                        0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK1_WAIT                         0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK2_START                        0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK2_WAIT                         0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_CHECK_PEND_LOADV                  0x00000009 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_SEND_UPD                          0x0000000a /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_WAIT_PRM                          0x0000000b /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME                                       24:24 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_INIT                             0x00000001 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_NO                               0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_YES                              0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE                                           18:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_DEALLOC                              0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_INIT1                                0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_IDLE                                 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_BUSY                                 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC                              31:31 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_INIT                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_IDLE                    0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_RUNNING                 0x00000001 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_MAIN                                           0x006107A8 /* RW-4R */
#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH                                      4:4 /* R--VF */
#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH_NOT_IN_PROGRESS               0x00000000 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH_IN_PROGRESS                   0x00000001 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT                                24:24 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_NO                        0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_YES                       0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT                                 25:25 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_NO                         0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_YES                        0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART                                        31:31 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_INIT                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_DONE                              0x00000000 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_PENDING                           0x00000001 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_TRIGGER                           0x00000001 /* -W--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD(i)                                (0x006107AC+(i)*4) /* RW-4A */
#define NV_PDISP_FE_SUPERVISOR_HEAD__SIZE_1                                            8 /*       */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK                                       8:8 /* R-IVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_INIT                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_NO                             0x00000000 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_YES                            0x00000001 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK                                      9:9 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_NO                            0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_YES                           0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK                                  10:10 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_INIT                        0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_NO                          0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_YES                         0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN                                  12:12 /* R-IVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_INIT                        0x00000000 /* R-I-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_NO                          0x00000000 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_YES                         0x00000001 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN                                 13:13 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_NO                         0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_YES                        0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN                               14:14 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_NO                       0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_YES                      0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL                               16:16 /* R-IVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_INIT                     0x00000000 /* R-I-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_NO                       0x00000000 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_YES                      0x00000001 /* R---V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL                              17:17 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_INIT                    0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_NO                      0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_YES                     0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL                            18:18 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_NO                    0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_YES                   0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP                           20:20 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_NO                   0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_YES                  0x00000001 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN                         21:21 /* RWIVF */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_NO                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_YES                0x00000001 /* RW--V */
#define NV_PDISP_FE_PBBASEHI_REGBASE                                          0x00000b20 /*       */
#define NV_PDISP_FE_PBBASE_REGBASE                                            0x00000b24 /*       */
#define NV_PDISP_FE_PBSUBDEV_REGBASE                                          0x00000b28 /*       */
#define NV_PDISP_FE_PBCLIENT_REGBASE                                          0x00000b2c /*       */
#define NV_PDISP_FE_PBBASEHI(i)                    (0x00610B20+(i)*16) /* RW-4A */
#define NV_PDISP_FE_PBBASEHI__SIZE_1                                                  73 /*       */
#define NV_PDISP_FE_PBBASEHI_PUSHBUFFER_ADDR                                         6:0 /* RWIUF */
#define NV_PDISP_FE_PBBASEHI_PUSHBUFFER_ADDR_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_PBBASE(i)                        (0x00610B24+(i)*16) /* RW-4A */
#define NV_PDISP_FE_PBBASE__SIZE_1                                                    73 /*       */
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET                                         1:0 /* RWIVF */
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_INIT                        0x00000001 /* RWI-V */
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_NVM                         0x00000001 /* RW--V */
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_PCI                         0x00000002 /* RW--V */
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_PCI_COHERENT                0x00000003 /* RW--V */
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_ADDR                                          31:4 /* RWIUF */
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_ADDR_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_PBSUBDEV(i)                    (0x00610B28+(i)*16) /* RW-4A */
#define NV_PDISP_FE_PBSUBDEV__SIZE_1                                                  73 /*       */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID                                           11:0 /* RWIVF */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_INIT                                0x00000001 /* RWI-V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_0                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_1                                   0x00000002 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_2                                   0x00000004 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_3                                   0x00000008 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_4                                   0x00000010 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_5                                   0x00000020 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_6                                   0x00000040 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_7                                   0x00000080 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_8                                   0x00000100 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_9                                   0x00000200 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_10                                  0x00000400 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_11                                  0x00000800 /* RW--V */
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_ALL                                 0x00000FFF /* RW--V */
#define NV_PDISP_FE_PBCLIENT(i)                    (0x00610B2C+(i)*16) /* RW-4A */
#define NV_PDISP_FE_PBCLIENT__SIZE_1                                                  73 /*       */
#define NV_PDISP_FE_PBCLIENT_CLIENT_ID                                              13:0 /* RWIUF */
#define NV_PDISP_FE_PBCLIENT_CLIENT_ID_INIT                                   0x00000000 /* RWI-V */
#define NV_PDISP_FE_PBBASEHI_CORE                  (0x00610B20+0*16) /*       */
#define NV_PDISP_FE_PBBASE_CORE                      (0x00610B24+0*16) /*       */
#define NV_PDISP_FE_PBSUBDEV_CORE                  (0x00610B28+0*16) /*       */
#define NV_PDISP_FE_PBCLIENT_CORE                  (0x00610B2C+0*16) /*       */
#define NV_PDISP_FE_PBBASEHI_WIN(i)              (0x00610B20+(1+(i))*16) /*       */
#define NV_PDISP_FE_PBBASEHI_WIN__SIZE_1                                                                32 /*       */
#define NV_PDISP_FE_PBBASE_WIN(i)                  (0x00610B24+(1+(i))*16) /*       */
#define NV_PDISP_FE_PBBASE_WIN__SIZE_1                                                                  32 /*       */
#define NV_PDISP_FE_PBSUBDEV_WIN(i)              (0x00610B28+(1+(i))*16) /*       */
#define NV_PDISP_FE_PBSUBDEV_WIN__SIZE_1                                                                32 /*       */
#define NV_PDISP_FE_PBCLIENT_WIN(i)              (0x00610B2C+(1+(i))*16) /*       */
#define NV_PDISP_FE_PBCLIENT_WIN__SIZE_1                                                                32 /*       */
#define NV_PDISP_FE_PBBASEHI_WINIM(i)          (0x00610B20+(33+(i))*16) /*       */
#define NV_PDISP_FE_PBBASEHI_WINIM__SIZE_1                                                              32 /*       */
#define NV_PDISP_FE_PBBASE_WINIM(i)              (0x00610B24+(33+(i))*16) /*       */
#define NV_PDISP_FE_PBBASE_WINIM__SIZE_1                                                                32 /*       */
#define NV_PDISP_FE_PBSUBDEV_WINIM(i)          (0x00610B28+(33+(i))*16) /*       */
#define NV_PDISP_FE_PBSUBDEV_WINIM__SIZE_1                                                              32 /*       */
#define NV_PDISP_FE_PBCLIENT_WINIM(i)          (0x00610B2C+(33+(i))*16) /*       */
#define NV_PDISP_FE_PBCLIENT_WINIM__SIZE_1                                                              32 /*       */
#define NV_PDISP_FE_PBBASEHI_WRBK(i)            (0x00610B20+(65+(i))*16) /*       */
#define NV_PDISP_FE_PBBASEHI_WRBK__SIZE_1                                                                8 /*       */
#define NV_PDISP_FE_PBBASE_WRBK(i)                (0x00610B24+(65+(i))*16) /*       */
#define NV_PDISP_FE_PBBASE_WRBK__SIZE_1                                                                  8 /*       */
#define NV_PDISP_FE_PBSUBDEV_WRBK(i)            (0x00610B28+(65+(i))*16) /*       */
#define NV_PDISP_FE_PBSUBDEV_WRBK__SIZE_1                                                                8 /*       */
#define NV_PDISP_FE_PBCLIENT_WRBK(i)            (0x00610B2C+(65+(i))*16) /*       */
#define NV_PDISP_FE_PBCLIENT_WRBK__SIZE_1                                                                8 /*       */
#define NV_PDISP_FE_EXCEPT(i)                                        (0x00611020+(i)*12) /* RW-4A */
#define NV_PDISP_FE_EXCEPT__SIZE_1                                                    81 /*       */
#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET                                            11:0 /* R--VF */
#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET_PBERR_INVALOP                        0x00000000 /* R---V */
#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET_PBERR_PROTFAULT                      0x00000000 /* R---V */
#define NV_PDISP_FE_EXCEPT_REASON                                                  14:12 /* R--VF */
#define NV_PDISP_FE_EXCEPT_REASON_NONE                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EXCEPT_REASON_PUSHBUFFER_ERR                              0x00000001 /* R---V */
#define NV_PDISP_FE_EXCEPT_REASON_TRAP                                        0x00000002 /* R---V */
#define NV_PDISP_FE_EXCEPT_REASON_RESERVED_METHOD                             0x00000003 /* R---V */
#define NV_PDISP_FE_EXCEPT_REASON_INVALID_ARG                                 0x00000004 /* R---V */
#define NV_PDISP_FE_EXCEPT_REASON_INVALID_STATE                               0x00000005 /* R---V */
#define NV_PDISP_FE_EXCEPT_REASON_UNRESOLVABLE_HANDLE                         0x00000007 /* R---V */
#define NV_PDISP_FE_EXCEPT_RESTART_MODE                                            29:28 /* RWIVF */
#define NV_PDISP_FE_EXCEPT_RESTART_MODE_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_EXCEPT_RESTART_MODE_RESUME                                0x00000000 /* RW--V */
#define NV_PDISP_FE_EXCEPT_RESTART_MODE_SKIP                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_EXCEPT_RESTART_MODE_REPLAY                                0x00000002 /* RW--V */
#define NV_PDISP_FE_EXCEPT_RESTART                                                 31:31 /* RWIVF */
#define NV_PDISP_FE_EXCEPT_RESTART_INIT                                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_EXCEPT_RESTART_DONE                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EXCEPT_RESTART_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_EXCEPT_RESTART_TRIGGER                                    0x00000001 /* -W--V */
#define NV_PDISP_FE_EXCEPTARG(i)                                     (0x00611024+(i)*12) /* RW-4A */
#define NV_PDISP_FE_EXCEPTARG__SIZE_1                                                 41 /*       */
#define NV_PDISP_FE_EXCEPTARG_RDARG                                                 31:0 /* RWIVF */
#define NV_PDISP_FE_EXCEPTARG_RDARG_INIT                                      0x00000000 /* R-I-V */
#define NV_PDISP_FE_EXCEPTARG_RDARG_PBERR_INVALOP                             0x00000000 /* R---V */
#define NV_PDISP_FE_EXCEPTARG_RDARG_PBERR_PROTFAULT                           0x00000400 /* R---V */
#define NV_PDISP_FE_EXCEPTARG_WRARG                                                 31:0 /* -W-VF */
#define NV_PDISP_FE_EXCEPTERR(i)                                     (0x00611028+(i)*12) /* R--4A */
#define NV_PDISP_FE_EXCEPTERR__SIZE_1                                                 41 /*       */
#define NV_PDISP_FE_EXCEPTERR_CODE                                                  23:0 /* R-IVF */
#define NV_PDISP_FE_EXCEPTERR_CODE_INIT                                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_EXCEPTERR_CODE_NONE                                       0x00000000 /* R---V */
#define NV_PDISP_FE_TIMEOUT                                                   0x00611400 /* RW-4R */
#define NV_PDISP_FE_TIMEOUT_PRI_VALUE                                                7:0 /* RWIVF */
#define NV_PDISP_FE_TIMEOUT_PRI_VALUE_INIT                                    0x00000064 /* RWI-V */
#define NV_PDISP_FE_TIMEOUT_BB_VALUE                                                15:8 /* RWIVF */
#define NV_PDISP_FE_TIMEOUT_BB_VALUE_INIT                                     0x00000064 /* RWI-V */
#define NV_PDISP_FE_TIMEOUT_STATUS_SRC                                               0:0 /* R--VF */
#define NV_PDISP_FE_TIMEOUT_STATUS_SRC_EXTERNAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_TIMEOUT_STATUS_SRC_INTERNAL                               0x00000001 /* R---V */
#define NV_PDISP_FE_TIMEOUT_STATUS_REQTYPE                                           1:1 /* R--VF */
#define NV_PDISP_FE_TIMEOUT_STATUS_REQTYPE_READ                               0x00000000 /* R---V */
#define NV_PDISP_FE_TIMEOUT_STATUS_REQTYPE_WRITE                              0x00000001 /* R---V */
#define NV_PDISP_FE_TIMEOUT_STATUS_ADDR                                             21:2 /* R--VF */
#define NV_PDISP_FE_TIMEOUT_STATUS_ERR                                             31:31 /* R-IVF */
#define NV_PDISP_FE_TIMEOUT_STATUS_ERR_NOT_PENDING                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_TIMEOUT_STATUS_ERR_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0                                            0x00611408 /* RW-4R */
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE                                                0:0 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_INIT                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_NORMAL                                  0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_LOCKED                                  0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_UNLOCK                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB                                              1:1 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA                                               2:2 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_NORMAL                                 0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_LOCKED                                 0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_UNLOCK                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC                                              3:3 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0                                             8:8 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1                                             9:9 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2                                           10:10 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3                                           11:11 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4                                           12:12 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5                                           13:13 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6                                           14:14 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7                                           15:15 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD(i)                               (8+(i)):(8+(i)) /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD__SIZE_1                                        8 /*       */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0                                            16:16 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1                                            17:17 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2                                            18:18 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3                                            19:19 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4                                            20:20 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5                                            21:21 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6                                            22:22 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7                                            23:23 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR(i)                              (16+(i)):(16+(i)) /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR__SIZE_1                                         8 /*       */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_NORMAL                                 0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_LOCKED                                 0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_UNLOCK                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1                                            0x0061140C /* RW-4R */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0                                              0:0 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1                                              1:1 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2                                              2:2 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3                                              3:3 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4                                              4:4 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5                                              5:5 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6                                              6:6 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7                                              7:7 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8                                              8:8 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9                                              9:9 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_NORMAL                                0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_LOCKED                                0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_UNLOCK                                0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10                                           10:10 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11                                           11:11 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12                                           12:12 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13                                           13:13 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14                                           14:14 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15                                           15:15 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16                                           16:16 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17                                           17:17 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18                                           18:18 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19                                           19:19 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20                                           20:20 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21                                           21:21 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22                                           22:22 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23                                           23:23 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24                                           24:24 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25                                           25:25 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26                                           26:26 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27                                           27:27 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28                                           28:28 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29                                           29:29 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30                                           30:30 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31                                           31:31 /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_NORMAL                               0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_LOCKED                               0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_UNLOCK                               0x00000001 /* -W--V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN(i)                                (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN__SIZE_1                                        32 /*       */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_NORMAL                                 0x00000000 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_LOCKED                                 0x00000001 /* R---V */
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_UNLOCK                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_CMGR_LOCK_DELAY                                           0x00611704 /* RW-4R */
#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL                                            15:0 /* RWIUF */
#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL_INIT                                 0x00000064 /* RWI-V */
#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL_100US                                0x00000064 /* RW--V */
#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL                                       31:16 /* RWIUF */
#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL_INIT                             0x000000C8 /* RWI-V */
#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL_200US                            0x000000C8 /* RW--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING(i)                                           (0x00611800+(i)*4) /* RW-4A */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING__SIZE_1                                                       8 /*       */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV                                                       0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_INIT                                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_RESET                                          0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA                                                   1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_INIT                                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_RESET                                      0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK                                                      2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_INIT                                          0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_NOT_PENDING                                   0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_PENDING                                       0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_RESET                                         0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK                                        3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOT_PENDING                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_PENDING                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_RESET                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL                                                    4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_INIT                                        0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_NOT_PENDING                                 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_PENDING                                     0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_RESET                                       0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A                                                   5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_INIT                                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_RESET                                      0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B                                                   6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_INIT                                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_RESET                                      0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE                                        7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE_INIT                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE_NOT_PENDING                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE_PENDING                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SD3_BUCKET_WALK_DONE_RESET                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY                                                  8:8 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_INIT                                      0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_NOT_PENDING                               0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_PENDING                                   0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_RESET                                     0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC                                                        0x00611840 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0                                              0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0_NOT_PENDING                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_0_RESET                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1                                              1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1_NOT_PENDING                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_1_RESET                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2                                              2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2_NOT_PENDING                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_2_RESET                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3                                              3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3_NOT_PENDING                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_3_RESET                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4                                              4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4_NOT_PENDING                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_4_RESET                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5                                              5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5_NOT_PENDING                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_5_RESET                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6                                              6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6_NOT_PENDING                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_6_RESET                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7                                              7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7_NOT_PENDING                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_7_RESET                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW(i)                                 (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW__SIZE_1                                          8 /*       */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_INIT                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_NOT_PENDING                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_PENDING                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_OBUF_UNDERFLOW_RESET                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0                                               8:8 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_0_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1                                               9:9 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_1_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2                                             10:10 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_2_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3                                             11:11 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_3_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4                                             12:12 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_4_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5                                             13:13 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_5_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6                                             14:14 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_6_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7                                             15:15 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_7_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW(i)                                  (8+(i)):(8+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW__SIZE_1                                           8 /*       */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_INIT                                     0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_NOT_PENDING                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_PENDING                                  0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_RBUF_OVERFLOW_RESET                                    0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0                                             16:16 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_0_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1                                             17:17 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_1_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2                                             18:18 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_2_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3                                             19:19 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_3_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4                                             20:20 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_4_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5                                             21:21 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_5_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6                                             22:22 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_6_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7                                             23:23 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_7_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW(i)                                (16+(i)):(16+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW__SIZE_1                                           8 /*       */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_INIT                                     0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_NOT_PENDING                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_PENDING                                  0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_BBUF_OVERFLOW_RESET                                    0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0                                                   24:24 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0_INIT                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_0_RESET                                        0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1                                                   25:25 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1_INIT                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_1_RESET                                        0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2                                                   26:26 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2_INIT                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_2_RESET                                        0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3                                                   27:27 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3_INIT                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_3_RESET                                        0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4                                                   28:28 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4_INIT                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_4_RESET                                        0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5                                                   29:29 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5_INIT                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_5_RESET                                        0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6                                                   30:30 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6_INIT                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_6_RESET                                        0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7                                                   31:31 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7_INIT                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_7_RESET                                        0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT(i)                                      (24+(i)):(24+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT__SIZE_1                                                 8 /*       */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_INIT                                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DSC_TIMEOUT_RESET                                          0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP                                                       0x00611848 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0                                               0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1                                               1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2                                               2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3                                               3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4                                               4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5                                               5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6                                               6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7                                               7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW(i)                                  (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW__SIZE_1                                           8 /*       */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_INIT                                     0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_NOT_PENDING                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_PENDING                                  0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_RESET                                    0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT                                                16:16 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT_INIT                                      0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT_NOT_PENDING                               0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT_PENDING                                   0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_TIMEOUT_RESET                                     0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT                                             17:17 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_NOT_PENDING                            0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_RESET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN                                                          0x0061184C /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0                                                            0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1                                                            1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2                                                            2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3                                                            3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4                                                            4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5                                                            5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6                                                            6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7                                                            7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8                                                            8:8 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9                                                            9:9 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10                                                         10:10 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11                                                         11:11 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12                                                         12:12 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13                                                         13:13 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14                                                         14:14 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15                                                         15:15 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16                                                         16:16 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17                                                         17:17 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18                                                         18:18 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19                                                         19:19 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20                                                         20:20 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21                                                         21:21 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22                                                         22:22 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23                                                         23:23 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24                                                         24:24 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25                                                         25:25 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26                                                         26:26 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27                                                         27:27 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28                                                         28:28 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29                                                         29:29 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30                                                         30:30 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31                                                         31:31 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH(i)                                               (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH__SIZE_1                                                       32 /*       */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_INIT                                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_NOT_PENDING                                           0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_PENDING                                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_RESET                                                 0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM                                                        0x00611850 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0                                                          0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1                                                          1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2                                                          2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3                                                          3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4                                                          4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5                                                          5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6                                                          6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7                                                          7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8                                                          8:8 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9                                                          9:9 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10                                                       10:10 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11                                                       11:11 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12                                                       12:12 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13                                                       13:13 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14                                                       14:14 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15                                                       15:15 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16                                                       16:16 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17                                                       17:17 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18                                                       18:18 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19                                                       19:19 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20                                                       20:20 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21                                                       21:21 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22                                                       22:22 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23                                                       23:23 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24                                                       24:24 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25                                                       25:25 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26                                                       26:26 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27                                                       27:27 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28                                                       28:28 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29                                                       29:29 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30                                                       30:30 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31                                                       31:31 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH(i)                                             (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH__SIZE_1                                                     32 /*       */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_INIT                                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_NOT_PENDING                                         0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_RESET                                               0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER                                                        0x00611854 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE                                                          0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0                                                      16:16 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1                                                      17:17 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2                                                      18:18 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3                                                      19:19 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4                                                      20:20 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5                                                      21:21 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6                                                      22:22 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7                                                      23:23 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS(i)                                         (16+(i)):(16+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS__SIZE_1                                                    8 /*       */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_INIT                                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_RESET                                             0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN                                                       0x00611858 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0                                                         0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1                                                         1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2                                                         2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3                                                         3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4                                                         4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5                                                         5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6                                                         6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7                                                         7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8                                                         8:8 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9                                                         9:9 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_INIT                                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_RESET                                            0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10                                                      10:10 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11                                                      11:11 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12                                                      12:12 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13                                                      13:13 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14                                                      14:14 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15                                                      15:15 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16                                                      16:16 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17                                                      17:17 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18                                                      18:18 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19                                                      19:19 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20                                                      20:20 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21                                                      21:21 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22                                                      22:22 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23                                                      23:23 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24                                                      24:24 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25                                                      25:25 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26                                                      26:26 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27                                                      27:27 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28                                                      28:28 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29                                                      29:29 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30                                                      30:30 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31                                                      31:31 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_INIT                                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_RESET                                           0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH(i)                                            (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH__SIZE_1                                                    32 /*       */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_INIT                                               0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_RESET                                              0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER                                                     0x0061185C /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE                                                       0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_INIT                                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_RESET                                          0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP                                                        0x00611860 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1                                                   0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_INIT                                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_RESET                                      0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2                                                   1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_INIT                                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_RESET                                      0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3                                                   2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_INIT                                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_RESET                                      0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR(i)                                     (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR__SIZE_1                                              3 /*       */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_INIT                                        0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_NOT_PENDING                                 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_PENDING                                     0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_RESET                                       0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE                                                 3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_INIT                                     0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_NOT_PENDING                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_PENDING                                  0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_RESET                                    0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A                                                  4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_INIT                                      0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_NOT_PENDING                               0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_PENDING                                   0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_RESET                                     0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B                                                  5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_INIT                                      0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_NOT_PENDING                               0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_PENDING                                   0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_RESET                                     0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN                                                       6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_INIT                                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_RESET                                          0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR                                                               0x00611864 /* RW-4R */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_0                                                                0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_INIT                                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_NOT_PENDING                                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_PENDING                                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_RESET                                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_1                                                                1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_INIT                                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_NOT_PENDING                                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_PENDING                                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_RESET                                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_2                                                                2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_INIT                                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_NOT_PENDING                                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_PENDING                                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_RESET                                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_3                                                                3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_INIT                                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_NOT_PENDING                                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_PENDING                                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_RESET                                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_4                                                                4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_INIT                                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_NOT_PENDING                                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_PENDING                                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_RESET                                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_5                                                                5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_INIT                                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_NOT_PENDING                                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_PENDING                                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_RESET                                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_6                                                                6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_INIT                                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_NOT_PENDING                                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_PENDING                                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_RESET                                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_7                                                                7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_INIT                                                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_NOT_PENDING                                             0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_PENDING                                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_RESET                                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR(i)                                                   (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_STAT_OR_SOR__SIZE_1                                                            8 /*       */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_INIT                                                      0x00000000 /* R-I-V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_NOT_PENDING                                               0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_PENDING                                                   0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_STAT_OR_SOR_RESET                                                     0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP                                                     0x00611948 /* RW-4R */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0                                             0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1                                             1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2                                             2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3                                             3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4                                             4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5                                             5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6                                             6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7                                             7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW(i)                                (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW__SIZE_1                                         8 /*       */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_INIT                                   0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_DISABLE                                0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_ENABLE                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_CLEAR                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT                                              16:16 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT_INIT                                    0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT_DISABLE                                 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT_ENABLE                                  0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_TIMEOUT_CLEAR                                   0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT                                           17:17 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_CLEAR                                0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP                                                     0x006119C8 /* RW-4R */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0                                             0:0 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1                                             1:1 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2                                             2:2 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3                                             3:3 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4                                             4:4 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5                                             5:5 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6                                             6:6 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7                                             7:7 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW(i)                                (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW__SIZE_1                                         8 /*       */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_INIT                                   0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_DISABLE                                0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_ENABLE                                 0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_SET                                    0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT                                              16:16 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT_INIT                                    0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT_DISABLE                                 0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT_ENABLE                                  0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_TIMEOUT_SET                                     0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT                                           17:17 /* RWIVF */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_INIT                                 0x00000001 /* R-I-V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_DISABLE                              0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_ENABLE                               0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_SET                                  0x00000001 /* -W--V */
#define NV_PDISP_FE_EVT_DISPATCH                                                              0x00611A00 /* R--4R */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0                                                       0:0 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1                                                       1:1 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2                                                       2:2 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3                                                       3:3 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4                                                       4:4 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5                                                       5:5 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6                                                       6:6 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7                                                       7:7 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING(i)                                          (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING__SIZE_1                                                   8 /*       */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_0                                                        8:8 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_0_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_0_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_1                                                        9:9 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_1_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_1_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_2                                                      10:10 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_2_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_2_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_3                                                      11:11 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_3_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_3_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_4                                                      12:12 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_4_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_4_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_5                                                      13:13 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_5_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_5_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_6                                                      14:14 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_6_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_6_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_7                                                      15:15 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_7_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_7_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS(i)                                           (8+(i)):(8+(i)) /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS__SIZE_1                                                    8 /*       */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_HEAD_NVDPS_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DSC                                                         16:16 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DSC_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DSC_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_FP16                                                        17:17 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_FP16_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_FP16_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP                                                        18:18 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN                                                           19:19 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN_NOT_PENDING                                          0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN_PENDING                                              0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM                                                         20:20 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER                                                         21:21 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN                                                        22:22 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN_NOT_PENDING                                       0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN_PENDING                                           0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER                                                      23:23 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER_NOT_PENDING                                     0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER_PENDING                                         0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP                                                         24:24 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP_NOT_PENDING                                        0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP_PENDING                                            0x00000001 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_OR                                                                25:25 /* R--VF */
#define NV_PDISP_FE_EVT_DISPATCH_OR_NOT_PENDING                                               0x00000000 /* R---V */
#define NV_PDISP_FE_EVT_DISPATCH_OR_PENDING                                                   0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP                                                    0x00611C30 /* R--4R */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1                                               0:0 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1_NOT_PENDING                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2                                               1:1 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2_NOT_PENDING                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3                                               2:2 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3_NOT_PENDING                            0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3_PENDING                                0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR(i)                                 (0+(i)):(0+(i)) /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR__SIZE_1                                          3 /*       */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR_NOT_PENDING                             0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR_PENDING                                 0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE                                             3:3 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_NOT_PENDING                          0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_PENDING                              0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A                                              4:4 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A_NOT_PENDING                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B                                              5:5 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B_NOT_PENDING                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B_PENDING                               0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN                                                   6:6 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN_NOT_PENDING                                0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR                                                     7:7 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR_NOT_PENDING                                  0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN                                                    8:8 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING                                 0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING                                     0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR                                                           0x00611C34 /* R--4R */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0                                                            0:0 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0_NOT_PENDING                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1                                                            1:1 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1_NOT_PENDING                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2                                                            2:2 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2_NOT_PENDING                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3                                                            3:3 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3_NOT_PENDING                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4                                                            4:4 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4_NOT_PENDING                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5                                                            5:5 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5_NOT_PENDING                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6                                                            6:6 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6_NOT_PENDING                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7                                                            7:7 /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7_NOT_PENDING                                         0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7_PENDING                                             0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR(i)                                               (0+(i)):(0+(i)) /* R-IVF */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR__SIZE_1                                                        8 /*       */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_NOT_PENDING                                           0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_PENDING                                               0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING(i)                                        (0x00611CC0+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING__SIZE_1                                                    8 /*       */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV                                                    0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_INIT                                        0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_DISABLE                                     0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_ENABLE                                      0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA                                                1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_INIT                                    0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK                                                   2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_INIT                                       0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_DISABLE                                    0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_ENABLE                                     0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK                                     3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL                                                 4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_INIT                                     0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_DISABLE                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_ENABLE                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A                                                5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_INIT                                    0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B                                                6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_INIT                                    0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SD3_BUCKET_WALK_DONE                                     7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SD3_BUCKET_WALK_DONE_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SD3_BUCKET_WALK_DONE_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SD3_BUCKET_WALK_DONE_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY                                               8:8 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_INIT                                   0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_DISABLE                                0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_ENABLE                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN                                                       0x00611CE4 /* RW-4R */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0                                                         0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1                                                         1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2                                                         2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3                                                         3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4                                                         4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5                                                         5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6                                                         6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7                                                         7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8                                                         8:8 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9                                                         9:9 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10                                                      10:10 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11                                                      11:11 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12                                                      12:12 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13                                                      13:13 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14                                                      14:14 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15                                                      15:15 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16                                                      16:16 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17                                                      17:17 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18                                                      18:18 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19                                                      19:19 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20                                                      20:20 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21                                                      21:21 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22                                                      22:22 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23                                                      23:23 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24                                                      24:24 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25                                                      25:25 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26                                                      26:26 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27                                                      27:27 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28                                                      28:28 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29                                                      29:29 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30                                                      30:30 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31                                                      31:31 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH(i)                                            (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH__SIZE_1                                                    32 /*       */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_INIT                                               0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_DISABLE                                            0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_ENABLE                                             0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM                                                     0x00611CE8 /* RW-4R */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0                                                       0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1                                                       1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2                                                       2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3                                                       3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4                                                       4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5                                                       5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6                                                       6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7                                                       7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8                                                       8:8 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9                                                       9:9 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10                                                    10:10 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11                                                    11:11 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12                                                    12:12 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13                                                    13:13 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14                                                    14:14 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15                                                    15:15 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16                                                    16:16 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17                                                    17:17 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18                                                    18:18 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19                                                    19:19 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20                                                    20:20 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21                                                    21:21 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22                                                    22:22 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23                                                    23:23 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24                                                    24:24 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25                                                    25:25 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26                                                    26:26 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27                                                    27:27 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28                                                    28:28 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29                                                    29:29 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30                                                    30:30 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31                                                    31:31 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH(i)                                          (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH__SIZE_1                                                  32 /*       */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_INIT                                             0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER                                                     0x00611CEC /* RW-4R */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE                                                       0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0                                                   16:16 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1                                                   17:17 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2                                                   18:18 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3                                                   19:19 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4                                                   20:20 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5                                                   21:21 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6                                                   22:22 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7                                                   23:23 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS(i)                                      (16+(i)):(16+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS__SIZE_1                                                 8 /*       */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_INIT                                           0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP                                                     0x00611CF0 /* RW-4R */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1                                                0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_INIT                                    0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2                                                1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_INIT                                    0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3                                                2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_INIT                                    0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR(i)                                  (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR__SIZE_1                                           3 /*       */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_INIT                                     0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_DISABLE                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_ENABLE                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE                                              3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_INIT                                  0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_DISABLE                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_ENABLE                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A                                               4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_INIT                                   0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_DISABLE                                0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_ENABLE                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B                                               5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_INIT                                   0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_DISABLE                                0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_ENABLE                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN                                                    6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_INIT                                        0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_DISABLE                                     0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_ENABLE                                      0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR                                                      7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_INIT                                          0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN                                                     8:8 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_INIT                                         0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR                                                            0x00611CF4 /* RW-4R */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0                                                             0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_INIT                                                 0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_DISABLE                                              0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_ENABLE                                               0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1                                                             1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_INIT                                                 0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_DISABLE                                              0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_ENABLE                                               0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2                                                             2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_INIT                                                 0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_DISABLE                                              0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_ENABLE                                               0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3                                                             3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_INIT                                                 0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_DISABLE                                              0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_ENABLE                                               0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4                                                             4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_INIT                                                 0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_DISABLE                                              0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_ENABLE                                               0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5                                                             5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_INIT                                                 0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_DISABLE                                              0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_ENABLE                                               0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6                                                             6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_INIT                                                 0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_DISABLE                                              0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_ENABLE                                               0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7                                                             7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_INIT                                                 0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_DISABLE                                              0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_ENABLE                                               0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR(i)                                                (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR__SIZE_1                                                         8 /*       */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_INIT                                                   0x00000001 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_DISABLE                                                0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_ENABLE                                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(i)                                         (0x00611D80+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING__SIZE_1                                                     8 /*       */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV                                                     0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_INIT                                         0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA                                                 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_DISABLE                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_ENABLE                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK                                                    2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_INIT                                        0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_DISABLE                                     0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_ENABLE                                      0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK                                      3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL                                                  4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_INIT                                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_DISABLE                                   0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_ENABLE                                    0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A                                                 5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_DISABLE                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_ENABLE                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B                                                 6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_DISABLE                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_ENABLE                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SD3_BUCKET_WALK_DONE                                      7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SD3_BUCKET_WALK_DONE_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SD3_BUCKET_WALK_DONE_DISABLE                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SD3_BUCKET_WALK_DONE_ENABLE                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY                                                8:8 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN                                                        0x00611DA4 /* RW-4R */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0                                                          0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1                                                          1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2                                                          2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3                                                          3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4                                                          4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5                                                          5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6                                                          6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7                                                          7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8                                                          8:8 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9                                                          9:9 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10                                                       10:10 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11                                                       11:11 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12                                                       12:12 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13                                                       13:13 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14                                                       14:14 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15                                                       15:15 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16                                                       16:16 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17                                                       17:17 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18                                                       18:18 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19                                                       19:19 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20                                                       20:20 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21                                                       21:21 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22                                                       22:22 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23                                                       23:23 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24                                                       24:24 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25                                                       25:25 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26                                                       26:26 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27                                                       27:27 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28                                                       28:28 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29                                                       29:29 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30                                                       30:30 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31                                                       31:31 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_INIT                                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_DISABLE                                          0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_ENABLE                                           0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH(i)                                             (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH__SIZE_1                                                     32 /*       */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_INIT                                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_DISABLE                                             0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_ENABLE                                              0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM                                                      0x00611DA8 /* RW-4R */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0                                                        0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1                                                        1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2                                                        2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3                                                        3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4                                                        4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5                                                        5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6                                                        6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7                                                        7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8                                                        8:8 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9                                                        9:9 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10                                                     10:10 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11                                                     11:11 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12                                                     12:12 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13                                                     13:13 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14                                                     14:14 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15                                                     15:15 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16                                                     16:16 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17                                                     17:17 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18                                                     18:18 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19                                                     19:19 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20                                                     20:20 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21                                                     21:21 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22                                                     22:22 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23                                                     23:23 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24                                                     24:24 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25                                                     25:25 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26                                                     26:26 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27                                                     27:27 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28                                                     28:28 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29                                                     29:29 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30                                                     30:30 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31                                                     31:31 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH(i)                                           (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH__SIZE_1                                                   32 /*       */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_INIT                                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_DISABLE                                           0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_ENABLE                                            0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER                                                      0x00611DAC /* RW-4R */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE                                                        0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0                                                    16:16 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1                                                    17:17 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2                                                    18:18 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3                                                    19:19 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4                                                    20:20 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5                                                    21:21 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6                                                    22:22 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7                                                    23:23 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS(i)                                       (16+(i)):(16+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS__SIZE_1                                                  8 /*       */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_INIT                                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_DISABLE                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_ENABLE                                          0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP                                                      0x00611DB0 /* RW-4R */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1                                                 0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_DISABLE                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_ENABLE                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2                                                 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_DISABLE                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_ENABLE                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3                                                 2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_DISABLE                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_ENABLE                                   0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR(i)                                   (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR__SIZE_1                                            3 /*       */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_INIT                                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_DISABLE                                   0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_ENABLE                                    0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE                                               3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_INIT                                   0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_DISABLE                                0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_ENABLE                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A                                                4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B                                                5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN                                                     6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_INIT                                         0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_DISABLE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_ENABLE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR                                                       7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_INIT                                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_DISABLE                                        0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_ENABLE                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN                                                      8:8 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_DISABLE                                       0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_ENABLE                                        0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR                                                             0x00611DB4 /* RW-4R */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0                                                              0:0 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_INIT                                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_DISABLE                                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_ENABLE                                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1                                                              1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_INIT                                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_DISABLE                                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_ENABLE                                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2                                                              2:2 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_INIT                                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_DISABLE                                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_ENABLE                                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3                                                              3:3 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_INIT                                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_DISABLE                                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_ENABLE                                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4                                                              4:4 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_INIT                                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_DISABLE                                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_ENABLE                                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5                                                              5:5 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_INIT                                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_DISABLE                                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_ENABLE                                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6                                                              6:6 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_INIT                                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_DISABLE                                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_ENABLE                                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7                                                              7:7 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_INIT                                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_DISABLE                                               0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_ENABLE                                                0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR(i)                                                 (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR__SIZE_1                                                          8 /*       */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_INIT                                                    0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_DISABLE                                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_ENABLE                                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_RM_INTR_DISPATCH                                                          0x00611EC0 /* R--4R */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0                                                   0:0 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1                                                   1:1 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2                                                   2:2 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3                                                   3:3 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4                                                   4:4 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5                                                   5:5 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6                                                   6:6 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7                                                   7:7 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7_NOT_PENDING                                0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7_PENDING                                    0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i)                                      (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING__SIZE_1                                               8 /*       */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING                                  0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_PENDING                                      0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_NVDPS                                                      8:8 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_NVDPS_NOT_PENDING                                   0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_NVDPS_PENDING                                       0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN                                                         9:9 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN_NOT_PENDING                                      0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN_PENDING                                          0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM                                                     10:10 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER                                                     11:11 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP                                                     12:12 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP_NOT_PENDING                                    0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP_PENDING                                        0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_OR                                                            13:13 /* R--VF */
#define NV_PDISP_FE_RM_INTR_DISPATCH_OR_NOT_PENDING                                           0x00000000 /* R---V */
#define NV_PDISP_FE_RM_INTR_DISPATCH_OR_PENDING                                               0x00000001 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_RG(i)                                    (0x00612200+(i)*2048) /* RW-4A */
#define NV_PDISP_FE_CMGR_CLK_RG__SIZE_1                                                   8 /*       */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV                                                     3:0 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_INIT                                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_1                                         0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_2                                         0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_3                                         0x00000002 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_4                                         0x00000003 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_5                                         0x00000004 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_6                                         0x00000005 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_7                                         0x00000006 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_8                                         0x00000007 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_9                                         0x00000008 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_10                                        0x00000009 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_11                                        0x0000000a /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_12                                        0x0000000b /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_13                                        0x0000000c /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_14                                        0x0000000d /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_15                                        0x0000000e /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_DIV_BY_16                                        0x0000000f /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_MODE                                                    7:6 /* R--VF */
#define NV_PDISP_FE_CMGR_CLK_RG_MODE_NORMAL                                      0x00000001 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_RG_MODE_SAFE                                        0x00000002 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE                                            11:11 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_DISABLE                               0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_ENABLE                                0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_RG_STATE                                                 23:23 /* R--VF */
#define NV_PDISP_FE_CMGR_CLK_RG_STATE_DISABLE                                    0x00000000 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_RG_STATE_ENABLE                                     0x00000001 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR(i)                                (0x00612300+(i)*2048) /* RW-4A */
#define NV_PDISP_FE_CMGR_CLK_SOR__SIZE_1                                               8 /*       */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV                                                 3:0 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_1                                     0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_2                                     0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_3                                     0x00000002 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_4                                     0x00000003 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_5                                     0x00000004 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_6                                     0x00000005 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_7                                     0x00000006 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_8                                     0x00000007 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_9                                     0x00000008 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_10                                    0x00000009 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_11                                    0x0000000a /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_12                                    0x0000000b /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_13                                    0x0000000c /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_14                                    0x0000000d /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_15                                    0x0000000e /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_DIV_BY_16                                    0x0000000f /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE                                                7:6 /* R--VF */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_NORMAL                                  0x00000001 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_SAFE                                    0x00000002 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV                                        11:8 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_1                             0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_2                             0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_3                             0x00000002 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_4                             0x00000003 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_5                             0x00000004 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_6                             0x00000005 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_7                             0x00000006 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_8                             0x00000007 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_9                             0x00000008 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_10                            0x00000009 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_11                            0x0000000a /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_12                            0x0000000b /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_13                            0x0000000c /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_14                            0x0000000d /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_15                            0x0000000e /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_PLL_REF_DIV_BY_16                            0x0000000f /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD                                              15:12 /* R--VF */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_NONE                                    0x0000000F /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_0                                       0x00000000 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_1                                       0x00000001 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_2                                       0x00000002 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_3                                       0x00000003 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_4                                       0x00000004 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_5                                       0x00000005 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_6                                       0x00000006 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_7                                       0x00000007 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS                                       17:16 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_NONE                             0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_DP_NORMAL                        0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_DP_SAFE                          0x00000002 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_FEEDBACK                         0x00000003 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED                                        22:18 /* RWIUF */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_INIT                              0x00000006 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_1_62GHZ                        0x00000006 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_2_70GHZ                        0x0000000A /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_5_40GHZ                        0x00000014 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_8_10GHZ                        0x0000001E /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_2_16GHZ                       0x00000008 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_2_43GHZ                       0x00000009 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_3_24GHZ                       0x0000000C /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_4_32GHZ                       0x00000010 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_TMDS                              0x0000000A /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_TMDS_HIGH_SPEED                   0x00000014 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_LVDS                              0x00000007 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_STATE                                             23:23 /* R--VF */
#define NV_PDISP_FE_CMGR_CLK_SOR_STATE_DISABLE                                0x00000000 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_STATE_ENABLE                                 0x00000001 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE                                        25:24 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_SINGLE_PCLK                       0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_DIFF_PCLK                         0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_SINGLE_DPCLK                      0x00000002 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_DIFF_DPCLK                        0x00000003 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL__SIZE_1                                          8 /*       */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR                                    2:2 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_INIT                        0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_DISABLE                     0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_ENABLE                      0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE                               5:3 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPA                   0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPB                   0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPC                   0x00000002 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPD                   0x00000003 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPE                   0x00000004 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPF                   0x00000005 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPG                   0x00000006 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL(i)                           (0x00612308+(i)*128) /* RW-4A */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL__SIZE_1                                         6 /*       */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND                                      3:0 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_NONE                          0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR0                          0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR1                          0x00000002 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR2                          0x00000003 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR3                          0x00000004 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR4                          0x00000005 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR5                          0x00000006 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR6                          0x00000007 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR7                          0x00000008 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR                                  4:4 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_PRIMARY                   0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_SECONDARY                 0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL                                  5:5 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_PRIMARY                   0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_SECONDARY                 0x00000001 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT                                  7:7 /* R--VF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT_LOW                       0x00000000 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT_HIGH                      0x00000001 /* R---V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ                                 11:8 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ_INIT                      0x00000008 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ_500OHM                    0x00000000 /* RW--V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_MODE                            16:16 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_MODE_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_DIV                             17:17 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_DIV_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_SEL                             20:18 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_SEL_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_PRBS_SEL                        22:21 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_PRBS_SEL_INIT              0x00000000 /* RWI-V */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CLK_EN_DIFF_DET                             23:23 /* RWIVF */
#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CLK_EN_DIFF_DET_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION(i)                    (0x00612050+(i)*2048) /* RW-4A */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION__SIZE_1                                   8 /*       */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_VALUE                                  15:0 /* RWIVF */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_VALUE_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_WRITE_MODE                            28:28 /* RWIVF */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_WRITE_MODE_ACTIVE                0x00000000 /* RW--V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_WRITE_MODE_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_WRITE_MODE_ASSEMBLY              0x00000001 /* RW--V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_UPDATE                                29:29 /* RWIVF */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_UPDATE_IMMEDIATE                 0x00000000 /* RW--V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_UPDATE_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_UPDATE_CORE                      0x00000001 /* RW--V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_STATUS                                31:30 /* R-IVF */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_STATUS_ACTIVE                    0x00000000 /* R-I-V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_STATUS_ARMED                     0x00000001 /* R---V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_DURATION_STATUS_ASSEMBLY                  0x00000002 /* R---V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY(i)                        (0x00612054+(i)*2048) /* RW-4A */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY__SIZE_1                                       8 /*       */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_VALUE                                      15:0 /* RWIVF */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_VALUE_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE                                28:28 /* RWIVF */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_ACTIVE                    0x00000000 /* RW--V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_ASSEMBLY                  0x00000001 /* RW--V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE                                    29:29 /* RWIVF */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_IMMEDIATE                     0x00000000 /* RW--V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_CORE                          0x00000001 /* RW--V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS                                    31:30 /* R--VF */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ACTIVE                        0x00000000 /* R---V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ARMED                         0x00000001 /* R---V */
#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ASSEMBLY                      0x00000002 /* R---V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK(i)                   (0x00612058+(i)*2048) /* RW-4A */
#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK__SIZE_1                                  8 /*       */
#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_VALUE                                 15:0 /* RWIVF */
#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_VALUE_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_MASK                                 30:30 /* RWIVF */
#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_MASK_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_MASK_DISABLE                    0x00000000 /* RW--V */
#define NV_PDISP_FE_MEMFETCH_VBLANK_WATERMARK_MASK_ENABLE                     0x00000001 /* RW--V */
#define NV_PDISP_FE_ELV_BLOCK(i)                                   (0x00612068+(i)*2048) /* RW-4A */
#define NV_PDISP_FE_ELV_BLOCK__SIZE_1                                                  8 /*       */
#define NV_PDISP_FE_ELV_BLOCK_CTRL                                                   0:0 /* RWIVF */
#define NV_PDISP_FE_ELV_BLOCK_CTRL_INIT                                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_ELV_BLOCK_CTRL_DISABLE                                    0x00000000 /* RW--V */
#define NV_PDISP_FE_ELV_BLOCK_CTRL_ENABLE                                     0x00000001 /* RW--V */
#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV                                          1:1 /* RWIVF */
#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_INIT                              0x00000000 /* R-I-V */
#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_DONE                              0x00000000 /* R---V */
#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_PENDING                           0x00000001 /* R---V */
#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_TRIGGER                           0x00000001 /* -W--V */
#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV                                   2:2 /* RWIVF */
#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_INIT                       0x00000000 /* R-I-V */
#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_DONE                       0x00000000 /* R---V */
#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_PENDING                    0x00000001 /* R---V */
#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_TRIGGER                    0x00000001 /* -W--V */
#define NV_PDISP_FE_FLIPLOCK                                                  0x0061206C /* RW-4R */
#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME                                           23:0 /* RWIVF */
#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME_INIT                                0x00000080 /* RWI-V */
#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME_32NS                                0x00000020 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP                                                0x00640000 /* RW-4R */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS                                          0:0 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_NO                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_YES                               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS                                          1:1 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_NO                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_YES                               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS                                          2:2 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_NO                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_YES                               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS                                          3:3 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_NO                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_YES                               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS                                          4:4 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_NO                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_YES                               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS                                          5:5 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_NO                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_YES                               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS                                          6:6 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_NO                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_YES                               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS                                          7:7 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_NO                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_YES                               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS(i)                            (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS__SIZE_1                                     8 /*       */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS                                           8:8 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS                                           9:9 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS                                         10:10 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS                                         11:11 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS                                         12:12 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS                                         13:13 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS                                         14:14 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS                                         15:15 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_NO                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_YES                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS(i)                             (8+(i)):(8+(i)) /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS__SIZE_1                                      8 /*       */
#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_NO                                  0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_YES                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB                                                0x00640004 /* RW-4R */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS                                        0:0 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS                                        1:1 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS                                        2:2 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS                                        3:3 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS                                        4:4 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS                                        5:5 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS                                        6:6 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS                                        7:7 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS                                        8:8 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS                                        9:9 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_NO                              0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_YES                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS                                     10:10 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS                                     11:11 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS                                     12:12 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS                                     13:13 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS                                     14:14 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS                                     15:15 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS                                     16:16 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS                                     17:17 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS                                     18:18 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS                                     19:19 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS                                     20:20 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS                                     21:21 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS                                     22:22 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS                                     23:23 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS                                     24:24 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS                                     25:25 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS                                     26:26 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS                                     27:27 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS                                     28:28 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS                                     29:29 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS                                     30:30 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS                                     31:31 /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_NO                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_YES                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS(i)                          (0+(i)):(0+(i)) /* RWIVF */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS__SIZE_1                                  32 /*       */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_NO                               0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_YES                              0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_LOCK_PIN_CAP                                           0x00640008 /* RW-4R */
#define NV_PDISP_FE_SW_LOCK_PIN_CAP_FLIP_LOCK_PINS                                   3:0 /* RWIVF */
#define NV_PDISP_FE_SW_LOCK_PIN_CAP_FLIP_LOCK_PINS_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_LOCK_PIN_CAP_SCAN_LOCK_PINS                                   7:4 /* RWIVF */
#define NV_PDISP_FE_SW_LOCK_PIN_CAP_SCAN_LOCK_PINS_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_LOCK_PIN_CAP_STEREO_PINS                                     11:8 /* RWIVF */
#define NV_PDISP_FE_SW_LOCK_PIN_CAP_STEREO_PINS_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA                                       0x00640010 /* RW-4R */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES                             15:0 /* RWIUF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH                        17:16 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_INIT              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B               0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B              0x00000002 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B              0x00000003 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA                                20:20 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE                     0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE                      0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION                21:21 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_INIT      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE     0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE      0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG                               22:22 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE                    0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE                     0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH                        23:23 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_INIT              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE              0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR                                24:24 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_FALSE                     0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_TRUE                      0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE                                25:25 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_FALSE                     0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_TRUE                      0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT                      26:26 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_INIT            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE           0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION         31:30 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPB                                       0x00640014 /* RW-4R */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC                                       0x00640018 /* RW-4R */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE                           1:0 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B               0x00000002 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B               0x00000003 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED                           6:4 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE               0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR               0x00000002 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT              0x00000003 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN            0x00000004 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE                10:8 /* RWIVF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_INIT     0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_NONE     0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_ONE      0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_TWO      0x00000002 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_THREE    0x00000003 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_FOUR     0x00000004 /* RW--V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD                                       0x0064001C /* RW-4R */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD_REORDER_BUFFER_DEPTH                        15:0 /* RWIUF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD_REORDER_BUFFER_DEPTH_INIT             0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD_RDOUT_BUFFER_SIZE                          31:16 /* RWIUF */
#define NV_PDISP_FE_SW_IHUB_COMMON_CAPD_RDOUT_BUFFER_SIZE_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPA(i)                                  (0x00640030+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_CAPA__SIZE_1                                               8 /*       */
#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER                                              0:0 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_TRUE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_FALSE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_HAS_YUV422                                   1:1 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_HAS_YUV422_TRUE                       0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_HAS_YUV422_FALSE                      0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_SCALER_HAS_YUV422_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPA_HSAT                                                2:2 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPA_HSAT_TRUE                                    0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_HSAT_FALSE                                   0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_HSAT_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPA_OCSC                                                3:3 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPA_OCSC_TRUE                                    0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_OCSC_FALSE                                   0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_OCSC_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPA_YUV422                                              4:4 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPA_YUV422_TRUE                                  0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_YUV422_FALSE                                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_YUV422_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE                                            6:5 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE_NONE                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE_257                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE_1025                                0x00000002 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_TYPE_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_LOCATION                                        7:7 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_LOCATION_EARLY                           0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_LOCATION_LATE                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_CAPA_LUT_LOCATION_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPB(i)                                  (0x00640034+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_CAPB__SIZE_1                                               8 /*       */
#define NV_PDISP_FE_SW_HEAD_CAPB_MAX_PIXELS_5TAP422                                 15:0 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CAPB_MAX_PIXELS_5TAP422_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPB_MAX_PIXELS_5TAP444                                31:16 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CAPB_MAX_PIXELS_5TAP444_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPC(i)                                  (0x00640038+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_CAPC__SIZE_1                                               8 /*       */
#define NV_PDISP_FE_SW_HEAD_CAPC_MAX_PIXELS_3TAP422                                 15:0 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CAPC_MAX_PIXELS_3TAP422_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPC_MAX_PIXELS_3TAP444                                31:16 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CAPC_MAX_PIXELS_3TAP444_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPD(i)                                  (0x0064003C+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_CAPD__SIZE_1                                               8 /*       */
#define NV_PDISP_FE_SW_HEAD_CAPD_MAX_PIXELS_2TAP422                                 15:0 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CAPD_MAX_PIXELS_2TAP422_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPD_MAX_PIXELS_2TAP444                                31:16 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CAPD_MAX_PIXELS_2TAP444_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPE(i)                                  (0x00640040+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_CAPE__SIZE_1                                               8 /*       */
#define NV_PDISP_FE_SW_HEAD_CAPE_MAX_PIXELS_1TAP422                                 15:0 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CAPE_MAX_PIXELS_1TAP422_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPE_MAX_PIXELS_1TAP444                                31:16 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_CAPE_MAX_PIXELS_1TAP444_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPF(i)                                  (0x00640044+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_CAPF__SIZE_1                                               8 /*       */
#define NV_PDISP_FE_SW_HEAD_CAPF_FULL_WIDTH                                          3:0 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPF_FULL_WIDTH_INIT                             0x000000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPF_UNIT_WIDTH                                          7:4 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPF_UNIT_WIDTH_INIT                             0x000000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPF_SCLR_WIDTH                                         11:8 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPF_SCLR_WIDTH_INIT                             0x000000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPF_HSAT_WIDTH                                        15:12 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPF_HSAT_WIDTH_INIT                             0x000000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPF_LUT_WIDTH                                         19:16 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPF_LUT_WIDTH_INIT                              0x000000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPF_OCSC_WIDTH                                        23:20 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPF_OCSC_WIDTH_INIT                             0x000000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPF_OLPF_WIDTH                                        27:24 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPF_OLPF_WIDTH_INIT                             0x000000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_CAPF_TZ_WIDTH                                          31:28 /* RWIVF */
#define NV_PDISP_FE_SW_HEAD_CAPF_TZ_WIDTH_INIT                               0x000000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_RG_CAPA(i)                               (0x00640048+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_HEAD_RG_CAPA__SIZE_1                                            8 /*       */
#define NV_PDISP_FE_SW_HEAD_RG_CAPA_SUPPORT_DSC                                    16:16 /* RWIUF */
#define NV_PDISP_FE_SW_HEAD_RG_CAPA_SUPPORT_DSC_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_HEAD_RG_CAPA_SUPPORT_DSC_TRUE                          0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_HEAD_RG_CAPA_SUPPORT_DSC_FALSE                         0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP(i)                                     (0x00640144+(i)*8) /* RW-4A */
#define NV_PDISP_FE_SW_SOR_CAP__SIZE_1                                                 8 /*       */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18                                        0:0 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_FALSE                           0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_TRUE                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24                                        1:1 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_FALSE                           0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_TRUE                            0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18                                          2:2 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_FALSE                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_TRUE                              0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24                                          3:3 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_FALSE                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_TRUE                              0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A                                         8:8 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_FALSE                            0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_TRUE                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B                                         9:9 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_FALSE                            0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_TRUE                             0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS                                           11:11 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_FALSE                                0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_TRUE                                 0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE                                   13:13 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_INIT                         0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_FALSE                        0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_TRUE                         0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SDI                                                 16:16 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_SDI_INIT                                       0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_SDI_FALSE                                      0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_SDI_TRUE                                       0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_A                                                24:24 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_DP_A_INIT                                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_A_FALSE                                     0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_A_TRUE                                      0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_B                                                25:25 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_DP_B_INIT                                      0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_B_FALSE                                     0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_B_TRUE                                      0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE                                        26:26 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_FALSE                             0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_TRUE                              0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES                                          27:27 /* RWIVF */
#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_FALSE                               0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_TRUE                                0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA(i)                      (0x006401E4+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA__SIZE_1                                  32 /*       */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_FULL_WIDTH                              3:0 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_FULL_WIDTH_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_UNIT_WIDTH                              7:4 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_UNIT_WIDTH_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_SCLR_WIDTH                             11:8 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_SCLR_WIDTH_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_YUV_WIDTH                             15:12 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_YUV_WIDTH_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_LUT_WIDTH                             19:16 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_LUT_WIDTH_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_CGMT_WIDTH                            23:20 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPA_CGMT_WIDTH_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB(i)                      (0x006401E8+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB__SIZE_1                                  32 /*       */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE                             9:8 /* RWIVF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_NONE                 0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_NORMAL               0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_WIDE                 0x00000002 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE                              13:12 /* RWIVF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_INIT                    0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_NONE                    0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_257                     0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_1025                    0x00000002 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT                          14:14 /* RWIVF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_NO                  0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_YES                 0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT                          15:15 /* RWIVF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_NO                  0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_YES                 0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_DEGAMMA_SUPPORT                       16:16 /* RWIVF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_DEGAMMA_SUPPORT_INIT             0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_DEGAMMA_SUPPORT_NO               0x00000000 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPB_DEGAMMA_SUPPORT_YES              0x00000001 /* RW--V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC(i)                      (0x006401EC+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC__SIZE_1                                  32 /*       */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP422                     15:0 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP422_INIT          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP444                    31:16 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP444_INIT          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD(i)                      (0x006401F0+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD__SIZE_1                                  32 /*       */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP422                     15:0 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP422_INIT          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP444                    31:16 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP444_INIT          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE(i)                      (0x006401F4+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE__SIZE_1                                  32 /*       */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP422                     15:0 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP422_INIT          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP444                    31:16 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP444_INIT          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF(i)                      (0x006401F8+(i)*32) /* RW-4A */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF__SIZE_1                                  32 /*       */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP422                     15:0 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP422_INIT          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP444                    31:16 /* RWIUF */
#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP444_INIT          0x00000000 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CLK_CAP(i)                                 (0x00640608+(i)*4) /* RW-4A */
#define NV_PDISP_FE_SW_SOR_CLK_CAP__SIZE_1                                             8 /*       */
#define NV_PDISP_FE_SW_SOR_CLK_CAP_DP_MAX                                            7:0 /* RWIUF */
#define NV_PDISP_FE_SW_SOR_CLK_CAP_DP_MAX_INIT                                0x00000036 /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CLK_CAP_TMDS_MAX                                        23:16 /* RWIUF */
#define NV_PDISP_FE_SW_SOR_CLK_CAP_TMDS_MAX_INIT                              0x0000003C /* RWI-V */
#define NV_PDISP_FE_SW_SOR_CLK_CAP_LVDS_MAX                                        31:24 /* RWIUF */
#define NV_PDISP_FE_SW_SOR_CLK_CAP_LVDS_MAX_INIT                              0x00000000 /* RWI-V */
#define NV_UDISP_HASH                                              0x00001FFF:0x00000000 /* RW--M */
#define NV_UDISP_HASH_BASE                                                    0x00000000 /*       */
#define NV_UDISP_HASH_LIMIT                                                   0x00001FFF /*       */
#define NV_UDISP_OBJ_MEM                                           0x0000FFFF:0x00002000 /* RW--M */
#define NV_UDISP_OBJ_MEM_BASE                                                 0x00002000 /*       */
#define NV_UDISP_OBJ_MEM_LIMIT                                                0x0000FFFF /*       */
#define NV_UDISP_HASH_TBL                                                                /* ----G */
#define NV_UDISP_HASH_TBL_HANDLE                                      (0*32+31):(0*32+0) /* RWXVF */
#define NV_UDISP_HASH_TBL_CLIENT_ID                                   (1*32+13):(1*32+0) /* RWXVF */
#define NV_UDISP_HASH_TBL_INSTANCE                                   (1*32+24):(1*32+14) /* RWXUF */
#define NV_UDISP_HASH_TBL_INSTANCE_INVALID                                    0x00000000 /* RW--V */
#define NV_UDISP_HASH_TBL_CHN                                        (1*32+31):(1*32+25) /* RWXUF */
#define NV_DMA                                                                           /* ----G */
#define NV_DMA_TARGET_NODE                                             (0*32+1):(0*32+0) /* RWXVF */
#define NV_DMA_TARGET_NODE_PHYSICAL_NVM                                       0x00000001 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI                                       0x00000002 /* RW--V */
#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT                              0x00000003 /* RW--V */
#define NV_DMA_ACCESS                                                  (0*32+2):(0*32+2) /* RWXVF */
#define NV_DMA_ACCESS_READ_ONLY                                               0x00000000 /* RW--V */
#define NV_DMA_ACCESS_READ_AND_WRITE                                          0x00000001 /* RW--V */
#define NV_DMA_PAGE_SIZE                                              (0*32+6):(0*32+6) /* RWXUF */
#define NV_DMA_PAGE_SIZE_BIG                                                 0x00000000 /* RW--V */
#define NV_DMA_PAGE_SIZE_SMALL                                               0x00000001 /* RW--V */
#define NV_DMA_KIND                                                  (0*32+20):(0*32+20) /* RWXVF */
#define NV_DMA_KIND_PITCH                                                     0x00000000 /* RW--V */
#define NV_DMA_KIND_BLOCKLINEAR                                               0x00000001 /* RW--V */
#define NV_DMA_ADDRESS_BASE_LO                                        (1*32+31):(1*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_BASE_HI                                         (2*32+6):(2*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_LO                                       (3*32+31):(3*32+0) /* RWXUF */
#define NV_DMA_ADDRESS_LIMIT_HI                                        (4*32+6):(4*32+0) /* RWXUF */
#define NV_DMA__SIZE                                                                  20 /*       */
#define NV_DMA__ALIGN                                                                 32 /*       */
#define NV_DMA__ADDRESS_BASE_SHIFT                                                     8 /*       */
#define NV_PDISP_IHUB_COMMON_CAPA                                               0x0062E000 /* R--4R */
#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES                                     15:0 /* R--UF */
#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH                                17:16 /* R--VF */
#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B                       0x00000000 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B                       0x00000001 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B                      0x00000002 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B                      0x00000003 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA                                        20:20 /* R--VF */
#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE                             0x00000000 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE                              0x00000001 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION                 31:30 /* R--VF */
#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B        0x00000000 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B        0x00000001 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B       0x00000002 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B       0x00000003 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPB                                               0x0062E004 /* R--4R */
#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS             17:12 /* R--UF */
#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS             23:18 /* R--UF */
#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_422_ROTATION_THREAD_GROUPS              29:24 /* R--UF */
#define NV_PDISP_IHUB_COMMON_CAPC                                               0x0062E008 /* R--4R */
#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE                                   1:0 /* R--VF */
#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B                        0x00000000 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B                        0x00000001 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B                       0x00000002 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B                       0x00000003 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED                                   6:4 /* R--VF */
#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE                       0x00000000 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO                        0x00000001 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR                       0x00000002 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT                      0x00000003 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN                    0x00000004 /* R---V */
#define NV_PDISP_IHUB_COMMON_CAPD                                               0x0062E00C /* R--4R */
#define NV_PDISP_IHUB_COMMON_CAPD_REORDER_BUFFER_DEPTH                                15:0 /* R--UF */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL                                     0x0062E018 /* RW-4R */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_WINDOW_INSTANCE                            4:0 /* RWIUF */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_WINDOW_INSTANCE_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_HEAD_INSTANCE                              7:5 /* RWIUF */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_HEAD_INSTANCE_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_SELECT                                     8:8 /* RWIVF */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_SELECT_INIT                         0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_SELECT_WINDOW                       0x00000000 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_SELECT_HEAD                         0x00000001 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE                                      10:9 /* RWIVF */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_IMMEDIATE                      0x00000000 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_STRICT                         0x00000001 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_SEMI_STRICT                    0x00000002 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_NO_UPDATE_WAIT                           11:11 /* RWIVF */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_NO_UPDATE_WAIT_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_NO_UPDATE_WAIT_DISABLE              0x00000000 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_NO_UPDATE_WAIT_ENABLE               0x00000001 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE                                   31:31 /* RWIVF */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_INIT                         0x00000000 /* R-I-V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_DONE                         0x00000000 /* R---V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_PENDING                      0x00000001 /* R---V */
#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_TRIGGER                      0x00000001 /* -W--T */
#define NV_PDISP_IHUB_COMMON_MISC_CTL                                           0x0062E024 /* RW-4R */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH                                           1:1 /* RWIVF */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_DISABLE                            0x00000000 /* RW--V */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_ENABLE                             0x00000001 /* RW--V */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT                                      30:30 /* RWIVF */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_INIT                            0x00000001 /* RWI-V */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_ENABLE                          0x00000001 /* RW--V */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_DISABLE                         0x00000000 /* RW--V */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER                                    31:31 /* RWIVF */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_INIT                          0x00000001 /* RWI-V */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_ENABLE                        0x00000001 /* RW--V */
#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_DISABLE                       0x00000000 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG                                             0x0062E02C /* RW-4R */
#define NV_PDISP_IHUB_COMMON_CONFIG_REQUEST_BATCH_SIZE                                 2:0 /* RWIVF */
#define NV_PDISP_IHUB_COMMON_CONFIG_REQUEST_BATCH_SIZE_1                        0x00000000 /* RW--V */
#define NV_PDISP_IHUB_COMMON_CONFIG_REQUEST_BATCH_SIZE_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG(i)                           (0x00628000+(i)*512) /* RW-4A */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG__SIZE_1                                        32 /*       */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_ENTRIES                                      15:0 /* RWIUF */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_ENTRIES_INIT                           0x00000278 /* RWI-V */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE                                      16:16 /* RWIVF */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_GLOBAL                          0x00000000 /* RW--V */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_IDLE                            0x00000001 /* RW--V */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS                                      31:31 /* R--VF */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS_DONE                            0x00000000 /* R---V */
#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS_PENDING                         0x00000001 /* R---V */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER(i)                           (0x00628004+(i)*512) /* RW-4A */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER__SIZE_1                                        32 /*       */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS                                         7:0 /* RWIUF */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_INIT                             0x00000001 /* RWI-V */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_ONE                              0x00000001 /* RW--V */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_MAX                              0x0000000F /* RW--V */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE                                      16:16 /* RWIVF */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_GLOBAL                          0x00000000 /* RW--V */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_IDLE                            0x00000001 /* RW--V */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS                                      31:31 /* R--VF */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS_DONE                            0x00000000 /* R---V */
#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS_PENDING                         0x00000001 /* R---V */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT(i)                             (0x0062800C+(i)*512) /* RW-4A */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT__SIZE_1                                          32 /*       */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT                                          11:0 /* RWIUF */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT_INIT                               0x00000FFF /* RWI-V */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT_MAX                                0x00000FFF /*       */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE                                        16:16 /* RWIVF */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_GLOBAL                            0x00000000 /* RW--V */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_IDLE                              0x00000001 /* RW--V */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS                                        31:31 /* R--VF */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS_DONE                              0x00000000 /* R---V */
#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS_PENDING                           0x00000001 /* R---V */
#define NV_PDISP_IHUB_WINDOW_OCC(i)                                   (0x00628028+(i)*512) /* R--4A */
#define NV_PDISP_IHUB_WINDOW_OCC__SIZE_1                                                32 /*       */
#define NV_PDISP_IHUB_WINDOW_OCC_BYTES                                                28:0 /* R--UF */
#define NV_PDISP_IHUB_WINDOW_OCC_PIXELS                                               28:0 /* ----- */
#define NV_PDISP_IHUB_WINDOW_REQ(i)                                   (0x00628078+(i)*512) /* R--4A */
#define NV_PDISP_IHUB_WINDOW_REQ__SIZE_1                                                32 /*       */
#define NV_PDISP_IHUB_WINDOW_REQ_LINE                                                 15:0 /* R--UF */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG(i)                             (0x0062C000+(i)*512) /* RW-4A */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG__SIZE_1                                           8 /*       */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_ENTRIES                                        15:0 /* RWIUF */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_ENTRIES_INIT                             0x00000010 /* RWI-V */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE                                        16:16 /* RWIVF */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_GLOBAL                            0x00000000 /* RW--V */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_IDLE                              0x00000001 /* RW--V */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS                                        31:31 /* R--VF */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS_DONE                              0x00000000 /* R---V */
#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS_PENDING                           0x00000001 /* R---V */
#define NV_PDISP_IHUB_CURS_FETCH_METER(i)                             (0x0062C004+(i)*512) /* RW-4A */
#define NV_PDISP_IHUB_CURS_FETCH_METER__SIZE_1                                           8 /*       */
#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS                                           7:0 /* RWIUF */
#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_INIT                               0x00000001 /* RWI-V */
#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_ONE                                0x00000001 /* RW--V */
#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_MAX                                0x0000000F /* RW--V */
#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE                                        16:16 /* RWIVF */
#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_GLOBAL                            0x00000000 /* RW--V */
#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_IDLE                              0x00000001 /* RW--V */
#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS                                        31:31 /* R--VF */
#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS_DONE                              0x00000000 /* R---V */
#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS_PENDING                           0x00000001 /* R---V */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT(i)                               (0x0062C008+(i)*512) /* RW-4A */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT__SIZE_1                                             8 /*       */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT                                            11:0 /* RWIUF */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT_INIT                                 0x00000FFF /* RWI-V */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT_MAX                                  0x00000FFF /*       */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE                                          16:16 /* RWIVF */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_GLOBAL                              0x00000000 /* RW--V */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_IDLE                                0x00000001 /* RW--V */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS                                          31:31 /* R--VF */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS_DONE                                0x00000000 /* R---V */
#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS_PENDING                             0x00000001 /* R---V */
#define NV_PDISP_IHUB_CURS_OCC(i)                                     (0x0062C028+(i)*512) /* R--4A */
#define NV_PDISP_IHUB_CURS_OCC__SIZE_1                                                   8 /*       */
#define NV_PDISP_IHUB_CURS_OCC_BYTES                                                  28:0 /* R--UF */
#define NV_PDISP_IHUB_CURS_OCC_PIXELS                                                 28:0 /* ----- */
#define NV_PDISP_IHUB_CURS_REQ(i)                                     (0x0062C078+(i)*512) /* R--4A */
#define NV_PDISP_IHUB_CURS_REQ__SIZE_1                                                   8 /*       */
#define NV_PDISP_IHUB_CURS_REQ_LINE                                                   15:0 /* R--UF */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER(i)                               (0x00630020+(i)*2048) /* RW-4A */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER__SIZE_1                                             32 /*       */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_VAL                                               15:0 /* RWIUF */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_VAL_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO                                            15:14 /* RWIUF */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_1                           0x00000000 /* RW--V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_2                           0x00000001 /* RW--V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_4                           0x00000002 /* RW--V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_8                           0x00000003 /* RW--V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_PXVAL                                             13:0 /* RWIUF */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_PXVAL_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE                                       28:28 /* RWIVF */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_ACTIVE                           0x00000000 /* RW--V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_ASSEMBLY                         0x00000001 /* RW--V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE                                           29:29 /* RWIVF */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_IMMEDIATE                            0x00000000 /* RW--V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_CORE                                 0x00000001 /* RW--V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS                                           31:30 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ACTIVE                               0x00000000 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ARMED                                0x00000001 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ASSEMBLY                             0x00000002 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA(i)                                (0x00630050+(i)*2048) /* R--4A */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA__SIZE_1                                              32 /*       */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_FULL_WIDTH                                          3:0 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_UNIT_WIDTH                                          7:4 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_SCLR_WIDTH                                         11:8 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_YUV_WIDTH                                         15:12 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_LUT_WIDTH                                         19:16 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPA_CGMT_WIDTH                                        23:20 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB(i)                                (0x00630054+(i)*2048) /* R--4A */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB__SIZE_1                                              32 /*       */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE                                         9:8 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_NONE                             0x00000000 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_SCALER_TYPE_NORMAL                           0x00000001 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE                                          13:12 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_NONE                                0x00000000 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_LUT_TYPE_1025                                0x00000002 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT                                      14:14 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_NO                              0x00000000 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_CGMT_PRESENT_YES                             0x00000001 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT                                      15:15 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_NO                              0x00000000 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPB_FP16_SUPPORT_YES                             0x00000001 /* R---V */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPC(i)                                (0x00630058+(i)*2048) /* R--4A */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPC__SIZE_1                                              32 /*       */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP422                                 15:0 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPC_MAX_PIXELS_5TAP444                                31:16 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPD(i)                                (0x0063005C+(i)*2048) /* R--4A */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPD__SIZE_1                                              32 /*       */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP422                                 15:0 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPD_MAX_PIXELS_3TAP444                                31:16 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPE(i)                                (0x00630060+(i)*2048) /* R--4A */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPE__SIZE_1                                              32 /*       */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP422                                 15:0 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPE_MAX_PIXELS_2TAP444                                31:16 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPF(i)                                (0x00630064+(i)*2048) /* R--4A */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPF__SIZE_1                                              32 /*       */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP422                                 15:0 /* R--VF */
#define NV_PDISP_PRECOMP_WIN_PIPE_CAPF_MAX_PIXELS_1TAP444                                31:16 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA(i)                                (0x00616100+(i)*2048) /* R--4A */
#define NV_PDISP_POSTCOMP_HEAD_CAPA__SIZE_1                                               8 /*       */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER                                              0:0 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_TRUE                                  0x00000001 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_FALSE                                 0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_HAS_YUV422                                   1:1 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_HAS_YUV422_TRUE                       0x00000001 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_SCALER_HAS_YUV422_FALSE                      0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_HSAT                                                2:2 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_HSAT_TRUE                                    0x00000001 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_HSAT_FALSE                                   0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_OCSC                                                3:3 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_OCSC_TRUE                                    0x00000001 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_OCSC_FALSE                                   0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_YUV422                                              4:4 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_YUV422_TRUE                                  0x00000001 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_YUV422_FALSE                                 0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_TYPE                                            6:5 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_TYPE_NONE                                0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_TYPE_257                                 0x00000001 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_TYPE_1025                                0x00000002 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_LOCATION                                        7:7 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_LOCATION_EARLY                           0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_LUT_LOCATION_LATE                            0x00000001 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_TZ                                                  8:8 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_TZ_TRUE                                      0x00000001 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPA_TZ_FALSE                                     0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_CAPB(i)                                (0x00616104+(i)*2048) /* R--4A */
#define NV_PDISP_POSTCOMP_HEAD_CAPB__SIZE_1                                               8 /*       */
#define NV_PDISP_POSTCOMP_HEAD_CAPB_MAX_PIXELS_5TAP422                                 15:0 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPB_MAX_PIXELS_5TAP444                                31:16 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPC(i)                                (0x00616108+(i)*2048) /* R--4A */
#define NV_PDISP_POSTCOMP_HEAD_CAPC__SIZE_1                                               8 /*       */
#define NV_PDISP_POSTCOMP_HEAD_CAPC_MAX_PIXELS_3TAP422                                 15:0 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPC_MAX_PIXELS_3TAP444                                31:16 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPD(i)                                (0x0061610C+(i)*2048) /* R--4A */
#define NV_PDISP_POSTCOMP_HEAD_CAPD__SIZE_1                                               8 /*       */
#define NV_PDISP_POSTCOMP_HEAD_CAPD_MAX_PIXELS_2TAP422                                 15:0 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPD_MAX_PIXELS_2TAP444                                31:16 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPE(i)                                (0x00616110+(i)*2048) /* R--4A */
#define NV_PDISP_POSTCOMP_HEAD_CAPE__SIZE_1                                               8 /*       */
#define NV_PDISP_POSTCOMP_HEAD_CAPE_MAX_PIXELS_1TAP422                                 15:0 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPE_MAX_PIXELS_1TAP444                                31:16 /* R--UF */
#define NV_PDISP_POSTCOMP_HEAD_CAPF(i)                                (0x00616114+(i)*2048) /* R--4A */
#define NV_PDISP_POSTCOMP_HEAD_CAPF__SIZE_1                                               8 /*       */
#define NV_PDISP_POSTCOMP_HEAD_CAPF_FULL_WIDTH                                          3:0 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_CAPF_UNIT_WIDTH                                          7:4 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_CAPF_SCLR_WIDTH                                         11:8 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_CAPF_HSAT_WIDTH                                        15:12 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_CAPF_LUT_WIDTH                                         19:16 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_CAPF_OCSC_WIDTH                                        23:20 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_CAPF_OLPF_WIDTH                                        27:24 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_CAPF_TZ_WIDTH                                          31:28 /* R--VF */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER(i)                    (0x0061611C+(i)*2048) /* RW-4A */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER__SIZE_1                                   8 /*       */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE                                  31:0 /* RWIUF */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_ZERO                       0x00000000 /* RW--V */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_HW                         0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_SW                         0x00000000 /* -W--V */
#define NV_PDISP_RG_HEAD_CAPA(i)                                      (0x00616300+(i)*2048) /* R--4A */
#define NV_PDISP_RG_HEAD_CAPA__SIZE_1                                                     8 /*       */
#define NV_PDISP_RG_HEAD_CAPA_REORDER_BANK_WIDTH_SIZE_MAX                              13:0 /* R-IUF */
#define NV_PDISP_RG_HEAD_CAPA_REORDER_BANK_WIDTH_SIZE_MAX_INIT                   0x00000A00 /* R-I-V */
#define NV_PDISP_RG_HEAD_CAPA_SUPPORT_DSC                                             16:16 /* R-IUF */
#define NV_PDISP_RG_HEAD_CAPA_SUPPORT_DSC_INIT                                   0x00000000 /* R-I-V */
#define NV_PDISP_RG_HEAD_CAPA_SUPPORT_DSC_TRUE                                   0x00000001 /* R---V */
#define NV_PDISP_RG_HEAD_CAPA_SUPPORT_DSC_FALSE                                  0x00000000 /* R---V */
#define NV_PDISP_RG_SWAP_LOCKOUT(i)                                (0x00616304+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_SWAP_LOCKOUT__SIZE_1                                               8 /*       */
#define NV_PDISP_RG_SWAP_LOCKOUT_START                                              15:0 /* RWIUF */
#define NV_PDISP_RG_SWAP_LOCKOUT_START_INIT                                   0x00000004 /* RWI-V */
#define NV_PDISP_RG_ELV(i)                                         (0x00616308+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_ELV__SIZE_1                                                        8 /*       */
#define NV_PDISP_RG_ELV_START                                                       14:0 /* RWIUF */
#define NV_PDISP_RG_ELV_START_INIT                                            0x00000001 /* RWI-V */
#define NV_PDISP_RG_UNDERFLOW(i)                                  (0x0061630C+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_UNDERFLOW__SIZE_1                                                 8 /*       */
#define NV_PDISP_RG_UNDERFLOW_ENABLE                                                0:0 /* RWIVF */
#define NV_PDISP_RG_UNDERFLOW_ENABLE_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_RG_UNDERFLOW_ENABLE_ENABLE                                  0x00000001 /* RW--V */
#define NV_PDISP_RG_UNDERFLOW_ENABLE_DISABLE                                 0x00000000 /* RW--V */
#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED                                           4:4 /* RWIVF */
#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_CLR                                0x00000001 /* -W--V */
#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_YES                                0x00000001 /* R---V */
#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_NO                                 0x00000000 /* R---V */
#define NV_PDISP_RG_UNDERFLOW_MODE                                                  8:8 /* RWIVF */
#define NV_PDISP_RG_UNDERFLOW_MODE_INIT                                      0x00000000 /* RWI-V */
#define NV_PDISP_RG_UNDERFLOW_MODE_REPEAT                                    0x00000000 /* RW--V */
#define NV_PDISP_RG_UNDERFLOW_MODE_RED                                       0x00000001 /* RW--V */
#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED                                      23:16 /* R-IVF */
#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_INIT                            0x00000000 /* R-I-V */
#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST                                  24:24 /* RWIVF */
#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_INIT                        0x00000000 /* R-I-V */
#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_DONE                    0x00000000 /* R---V */
#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_PENDING                 0x00000001 /* R---V */
#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_TRIGGER                 0x00000001 /* -W--V */
#define NV_PDISP_RG_UNDERFLOW_PIXEL__SIZE_1                                           8 /*       */
#define NV_PDISP_RG_UNDERFLOW_PIXEL_CNT                                             31:0 /* RWIVF */
#define NV_PDISP_RG_UNDERFLOW_PIXEL_CNT_INIT                                  0x00000000 /* R-I-V */
#define NV_PDISP_RG_UNDERFLOW_PIXEL_CNT_CLR                                   0x00000000 /* -W--V */
#define NV_PDISP_RG_STATUS(i)                                     (0x00616314+(i)*2048) /* R--4A */
#define NV_PDISP_RG_STATUS__SIZE_1                                                    8 /*       */
#define NV_PDISP_RG_STATUS_STALLED                                                  3:3 /* R--VF */
#define NV_PDISP_RG_STATUS_STALLED_NO                                        0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_STALLED_YES                                       0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_EXTERNAL_UNSTALL_EVENT_CNT                               8:5 /* R-IVF */
#define NV_PDISP_RG_STATUS_EXTERNAL_UNSTALL_EVENT_CNT_INIT                   0x00000000 /* R-I-V */
#define NV_PDISP_RG_STATUS_RG_UNSTALL_CNT                                          12:9 /* R-IVF */
#define NV_PDISP_RG_STATUS_RG_UNSTALL_CNT_INIT                               0x00000000 /* R-I-V */
#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE                                        15:14 /* R--VF */
#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_SLEEP                             0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_SNOOZE                            0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_AWAKE                             0x00000002 /* R---V */
#define NV_PDISP_RG_STATUS_HSYNC                                                  16:16 /* R--VF */
#define NV_PDISP_RG_STATUS_HSYNC_INACTIVE                                    0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_HSYNC_ACTIVE                                      0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_HBLNK                                                  17:17 /* R--VF */
#define NV_PDISP_RG_STATUS_HBLNK_INACTIVE                                    0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_HBLNK_ACTIVE                                      0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_VSYNC                                                  20:20 /* R--VF */
#define NV_PDISP_RG_STATUS_VSYNC_INACTIVE                                    0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_VSYNC_ACTIVE                                      0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_VBLNK                                                  21:21 /* R--VF */
#define NV_PDISP_RG_STATUS_VBLNK_INACTIVE                                    0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_VBLNK_ACTIVE                                      0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_FID                                                    22:22 /* R--UF */
#define NV_PDISP_RG_STATUS_FID_FLD0                                          0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_FID_FLD1                                          0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_BLNK                                                   24:24 /* R--VF */
#define NV_PDISP_RG_STATUS_BLNK_INACTIVE                                     0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_BLNK_ACTIVE                                       0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_VACT_SPACE                                             25:25 /* R--VF */
#define NV_PDISP_RG_STATUS_VACT_SPACE_INACTIVE                               0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_VACT_SPACE_ACTIVE                                 0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_STEREO                                                 27:27 /* R--VF */
#define NV_PDISP_RG_STATUS_STEREO_RIGHT                                      0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_STEREO_LEFT                                       0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_VIEWPORT                                               28:28 /* R--VF */
#define NV_PDISP_RG_STATUS_VIEWPORT_INACTIVE                                 0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_VIEWPORT_ACTIVE                                   0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_BORDER                                                 29:29 /* R--VF */
#define NV_PDISP_RG_STATUS_BORDER_INACTIVE                                   0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_BORDER_ACTIVE                                     0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_LOCKED                                                 30:30 /* R--VF */
#define NV_PDISP_RG_STATUS_LOCKED_FALSE                                      0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_LOCKED_TRUE                                       0x00000001 /* R---V */
#define NV_PDISP_RG_STATUS_FLIPLOCKED                                             31:31 /* R--VF */
#define NV_PDISP_RG_STATUS_FLIPLOCKED_FALSE                                  0x00000000 /* R---V */
#define NV_PDISP_RG_STATUS_FLIPLOCKED_TRUE                                   0x00000001 /* R---V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP(i)                            (0x00616318+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_UNSTALL_SPOOLUP__SIZE_1                                           8 /*       */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_VALUE                                          19:0 /* RWIUF */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_VALUE_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE                                    28:28 /* RWIUF */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_ACTIVE                        0x00000000 /* RW--V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_ASSEMBLY                      0x00000001 /* RW--V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE                                        29:29 /* RWIUF */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_IMMEDIATE                         0x00000000 /* RW--V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_CORE                              0x00000001 /* RW--V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS                                        31:30 /* R--UF */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ACTIVE                            0x00000000 /* R---V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ARMED                             0x00000001 /* R---V */
#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ASSEMBLY                          0x00000002 /* R---V */
#define NV_PDISP_RG_IN_LOADV_COUNTER(i)                            (0x00616320+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_IN_LOADV_COUNTER__SIZE_1                                           8 /*       */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE                                          31:0 /* RWIUF */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_ZERO                               0x00000000 /* RW--V */
#define NV_PDISP_RG_DPCA(i)                                       (0x00616330+(i)*2048) /* R--4A */
#define NV_PDISP_RG_DPCA__SIZE_1                                                      8 /*       */
#define NV_PDISP_RG_DPCA_LINE_CNT                                                  15:0 /* R--UF */
#define NV_PDISP_RG_DPCA_FRM_CNT                                                  31:16 /* R--UF */
#define NV_PDISP_RG_DPCB(i)                                       (0x00616334+(i)*2048) /* R--4A */
#define NV_PDISP_RG_DPCB__SIZE_1                                                      8 /*       */
#define NV_PDISP_RG_DPCB_PIXEL_CNT                                                 15:0 /* R--UF */
#define NV_PDISP_RG_LINE_A_INTR(i)                                  (0x00616348+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_LINE_A_INTR__SIZE_1                                                 8 /*       */
#define NV_PDISP_RG_LINE_A_INTR_LINE_CNT                                             15:0 /* RWIUF */
#define NV_PDISP_RG_LINE_A_INTR_LINE_CNT_INIT                                  0x0000FFFF /* RWI-V */
#define NV_PDISP_RG_LINE_A_INTR_ENABLE                                              31:31 /* RWIUF */
#define NV_PDISP_RG_LINE_A_INTR_ENABLE_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_RG_LINE_A_INTR_ENABLE_NO                                      0x00000000 /* RW--V */
#define NV_PDISP_RG_LINE_A_INTR_ENABLE_YES                                     0x00000001 /* RW--V */
#define NV_PDISP_RG_LINE_B_INTR(i)                              (0x0061634C+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_LINE_B_INTR__SIZE_1                                             8 /*       */
#define NV_PDISP_RG_LINE_B_INTR_LINE_CNT                                         15:0 /* RWIUF */
#define NV_PDISP_RG_LINE_B_INTR_LINE_CNT_INIT                              0x0000FFFF /* RWI-V */
#define NV_PDISP_RG_LINE_B_INTR_ENABLE                                          31:31 /* RWIUF */
#define NV_PDISP_RG_LINE_B_INTR_ENABLE_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_RG_LINE_B_INTR_ENABLE_NO                                  0x00000000 /* RW--V */
#define NV_PDISP_RG_LINE_B_INTR_ENABLE_YES                                 0x00000001 /* RW--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH(i)                  (0x00616360+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH__SIZE_1                                8 /*       */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_HEIGHT                        13:0 /* R-IUF */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_HEIGHT_INIT             0x00000000 /* R-I-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE                       14:14 /* R-IVF */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_INIT             0x00000000 /* R-I-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_NO               0x00000000 /* R---V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_YES              0x00000001 /* R---V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_DBG                                 15:15 /* RWIUF */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_DBG_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_HEIGHT                          29:16 /* RWIUF */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_HEIGHT_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE                          30:30 /* RWIVF */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_NO                  0x00000000 /* RW--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_YES                 0x00000001 /* RW--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE                              31:31 /* RW-VF */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_DONE                    0x00000000 /* R---V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_PENDING                 0x00000001 /* R---V */
#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_TRIGGER                 0x00000001 /* -W--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH(i)                 (0x00616364+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH__SIZE_1                                8 /*       */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_HEIGHT                       13:0 /* R-IUF */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_HEIGHT_INIT            0x00000000 /* R-I-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE                      14:14 /* R-IVF */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_INIT            0x00000000 /* R-I-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_NO              0x00000000 /* R---V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_YES             0x00000001 /* R---V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_DBG                                15:15 /* RWIUF */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_DBG_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_HEIGHT                         29:16 /* RWIUF */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_HEIGHT_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE                         30:30 /* RWIVF */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_NO                 0x00000000 /* RW--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_YES                0x00000001 /* RW--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE                             31:31 /* RW-VF */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_DONE                   0x00000000 /* R---V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_PENDING                0x00000001 /* R---V */
#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_TRIGGER                0x00000001 /* -W--V */
#define NV_PDISP_RG_RASTER_EXTEND(i)                              (0x00616368+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_RASTER_EXTEND__SIZE_1                                             8 /*       */
#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_WIDTH                                     13:0 /* R-IUF */
#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_WIDTH_INIT                          0x00000000 /* R-I-V */
#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE                                   14:14 /* R-IVF */
#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_INIT                         0x00000000 /* R-I-V */
#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_NO                           0x00000000 /* R---V */
#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_YES                          0x00000001 /* R---V */
#define NV_PDISP_RG_RASTER_EXTEND_DBG                                             15:15 /* RWIUF */
#define NV_PDISP_RG_RASTER_EXTEND_DBG_INIT                                   0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_EXTEND_SET_WIDTH                                       29:16 /* RWIUF */
#define NV_PDISP_RG_RASTER_EXTEND_SET_WIDTH_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE                                      30:30 /* RWIVF */
#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_NO                              0x00000000 /* RW--V */
#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_YES                             0x00000001 /* RW--V */
#define NV_PDISP_RG_RASTER_EXTEND_UPDATE                                          31:31 /* RW-VF */
#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_DONE                                0x00000000 /* R---V */
#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_PENDING                             0x00000001 /* R---V */
#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_TRIGGER                             0x00000001 /* -W--V */
#define NV_PDISP_RG_HEAD_CLK_CAP(i)                                        (0x006163C0+(i)*2048) /* R--4A */
#define NV_PDISP_RG_HEAD_CLK_CAP__SIZE_1                                                       8 /*       */
#define NV_PDISP_RG_HEAD_CLK_CAP_PCLK_MAX                                                    7:0 /* R-IUF */
#define NV_PDISP_RG_HEAD_CLK_CAP_PCLK_MAX_INIT                                        0x00000085 /* R-I-V */
#define NV_PDISP_RG_MISC_CTL(i)                                     (0x006163C4+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_MISC_CTL__SIZE_1                                                    8 /*       */
#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL                                            4:4 /* RWIVF */
#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_INIT                                0x00000000 /* R-I-V */
#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_DONE                                0x00000000 /* R---V */
#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_PENDING                             0x00000001 /* R---V */
#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_TRIGGER                             0x00000001 /* -W--V */
#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST                                        13:13 /* RWIVF */
#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_INIT                              0x00000000 /* R-I-V */
#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_DONE                              0x00000000 /* R---V */
#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_PENDING                           0x00000001 /* R---V */
#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_TRIGGER                           0x00000001 /* -W--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY(i)                     (0x006163C8+(i)*2048) /* RW-4A */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY__SIZE_1                                    8 /*       */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH                               3:0 /* RWIUF */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_TWO                     0x00000001/* RW--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_NONE                   0x00000000 /* RW--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH                               7:4 /* RWIUF */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_TWO                    0x00000001 /* RW--V */
#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_NONE                   0x00000000 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER(i)                               (0x00616208+(i)*2048) /* RW-4A */
#define NV_PDISP_CURSOR_PIPE_METER__SIZE_1                                              8 /*       */
#define NV_PDISP_CURSOR_PIPE_METER_VAL                                               15:0 /* RWIUF */
#define NV_PDISP_CURSOR_PIPE_METER_VAL_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_CURSOR_PIPE_METER_RATIO                                            15:14 /* RWIUF */
#define NV_PDISP_CURSOR_PIPE_METER_RATIO_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_1                     0x00000000 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_2                     0x00000001 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_4                     0x00000002 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_8                     0x00000003 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER_PXVAL                                             13:0 /* RWIUF */
#define NV_PDISP_CURSOR_PIPE_METER_PXVAL_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE                                       28:28 /* RWIVF */
#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_ACTIVE                           0x00000000 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_ASSEMBLY                         0x00000001 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER_UPDATE                                           29:29 /* RWIVF */
#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_IMMEDIATE                            0x00000000 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_CORE                                 0x00000001 /* RW--V */
#define NV_PDISP_CURSOR_PIPE_METER_STATUS                                           31:30 /* R--VF */
#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ACTIVE                               0x00000000 /* R---V */
#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ARMED                                0x00000001 /* R---V */
#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ASSEMBLY                             0x00000002 /* R---V */
#define NV_PDISP_SF_TEST(i)                                       (0x0061650C+(i)*2048) /* R--4A */
#define NV_PDISP_SF_TEST__SIZE_1                                                      8 /*       */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE                                           9:8 /* R--UF */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_SLEEP                              0x00000000 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_SNOOZE                             0x00000001 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_AWAKE                              0x00000002 /* R---V */
#define NV_PDISP_SF_TEST_OWNER_MASK                                             13:10 /* R--UF */
#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD0                                  0x00000001 /* R---V */
#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD1                                  0x00000002 /* R---V */
#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD2                                  0x00000004 /* R---V */
#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD3                                  0x00000008 /* R---V */
#define NV_PDISP_SF_TEST_OWNER_MASK_NONE                                   0x00000000 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG(i)               (2*(i)+15):(2*(i)+14) /* R--UF */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG__SIZE_1                              2 /*       */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG_SLEEP                       0x00000000 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG_SNOOZE                      0x00000001 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG_AWAKE                       0x00000002 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG0                                 15:14 /* R--UF */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG0_SLEEP                      0x00000000 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG0_SNOOZE                     0x00000001 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG0_AWAKE                      0x00000002 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG1                                 17:16 /* R--UF */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG1_SLEEP                      0x00000000 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG1_SNOOZE                     0x00000001 /* R---V */
#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_DEBUG1_AWAKE                      0x00000002 /* R---V */
#define NV_PDISP_SF_AUDIO_CNTRL0(i)                               (0x00616528+(i)*2048) /* RW-4A */
#define NV_PDISP_SF_AUDIO_CNTRL0__SIZE_1                                              8 /*       */
#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY                                       6:4 /* RWIVF */
#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_INIT                           0x00000007 /* RWI-V */
#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_NONE                           0x00000007 /* RW--V */
#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_ZERO                           0x00000000 /* RW--V */
#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_ONE                            0x00000001 /* RW--V */
#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_TWO                            0x00000002 /* RW--V */
#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_THREE                          0x00000003 /* RW--V */
#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH                                      12:12 /* RWIVF */
#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_INIT                            0x00000001 /* RWI-V */
#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_ENABLED                         0x00000001 /* RW--V */
#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_DISABLED                        0x00000000 /* RW--V */
#define NV_PDISP_SF_SPARE0(i)                                     (0x00616530+(i)*2048) /* RWI4A */
#define NV_PDISP_SF_SPARE0__SIZE_1                                                    8 /*       */
#define NV_PDISP_SF_SPARE0_DP_VERSION                                               0:0 /* RWIVF */
#define NV_PDISP_SF_SPARE0_DP_VERSION_INIT                                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_SPARE0_DP_VERSION_11                                     0x00000000 /* RW--V */
#define NV_PDISP_SF_SPARE0_DP_VERSION_12                                     0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL(i)                                 (0x00616540+(i)*2048) /* RW-4A */
#define NV_PDISP_SF_DP_LINKCTL__SIZE_1                                                8 /*       */
#define NV_PDISP_SF_DP_LINKCTL_ENABLE                                               0:0 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_ENABLE_INIT                                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_ENABLE_YES                                    0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_ENABLE_NO                                     0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_TUSIZE                                               8:2 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_TUSIZE_INIT                                   0x00000040 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE                                           10:10 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_ENABLE                               0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_DISABLE                              0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT                                     11:11 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_PRIMARY                        0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_SECONDARY                      0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_RESERVED                                   13:12 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_RESERVED_INIT                         0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME                                      14:14 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_DISABLE                         0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_ENABLE                          0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL                                        15:15 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_NO                                0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_YES                               0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT                                          23:16 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_ZERO                                0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_ONE                                 0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_TWO                                 0x00000003 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_FOUR                                0x0000000F /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_EIGHT                               0x000000FF /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE                           24:24 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_NO                   0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_YES                  0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE                             25:25 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_LOADV                  0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_IMMEDIATE              0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN                                  26:26 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_INIT                        0x00000000 /* R-I-V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_DONE                        0x00000000 /* R---V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_PENDING                     0x00000001 /* R---V */
#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_TRIGGER                     0x00000001 /* -W--T */
#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST                                    27:27 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_DISABLE                       0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_ENABLE                        0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE                                        30:30 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_SINGLE_STREAM                     0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_MULTI_STREAM                      0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE                      31:31 /* RWIVF */
#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_INIT            0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_NO              0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_YES             0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_MN(i)                                      (0x0061654C+(i)*2048) /* RW-4A */
#define NV_PDISP_SF_DP_MN__SIZE_1                                                     8 /*       */
#define NV_PDISP_SF_DP_MN_N_VAL                                                    23:0 /* RWIVF */
#define NV_PDISP_SF_DP_MN_N_VAL_INIT                                         0x00008000 /* RWI-V */
#define NV_PDISP_SF_DP_MN_M_DELTA                                                 27:24 /* RWIVF */
#define NV_PDISP_SF_DP_MN_M_DELTA_INIT                                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE                                      28:28 /* RWIVF */
#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_DISABLE                         0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_ENABLE                          0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_MN_M_MOD                                                   31:30 /* RWIVF */
#define NV_PDISP_SF_DP_MN_M_MOD_INIT                                         0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_MN_M_MOD_NONE                                         0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_MN_M_MOD_INC                                          0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_MN_M_MOD_DEC                                          0x00000002 /* RW--V */
#define NV_PDISP_SF_DP_CONFIG(i)                                  (0x00616550+(i)*2048) /* RW-4A */
#define NV_PDISP_SF_DP_CONFIG__SIZE_1                                                 8 /*       */
#define NV_PDISP_SF_DP_CONFIG_WATERMARK                                             5:0 /* RWIVF */
#define NV_PDISP_SF_DP_CONFIG_WATERMARK_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_COUNT                                      14:8 /* RWIVF */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_COUNT_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_FRAC                                      19:16 /* RWIVF */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_FRAC_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY                                  24:24 /* RWIVF */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_INIT                        0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE                    0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE                    0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE                                 27:26 /* RWIVF */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_INIT                       0x00000002 /* RWI-V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_DISABLE                    0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_LEGACY                     0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_AUTO                       0x00000002 /* RW--V */
#define NV_PDISP_SF_DP_AUDIO_CTRL(i)                              (0x00616560+(i)*2048) /* RWI4A */
#define NV_PDISP_SF_DP_AUDIO_CTRL__SIZE_1                                             8 /*       */
#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE                                            0:0 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_INIT                                0x00000001 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_NO                                  0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_YES                                 0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE                                              3:2 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_AUTO                                  0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_DISABLE                               0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_ENABLE                                0x00000002 /* RW--V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_PACKETID                                         15:8 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_CTRL_PACKETID_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS                                     21:21 /* R--VF */
#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS_ENABLE                         0x00000001 /* R---V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS_DISABLE                        0x00000000 /* R---V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS                                    31:31 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_INIT                          0x00000000 /* R-I-V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_DONE                          0x00000000 /* R---V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_PENDING                       0x00000001 /* R---V */
#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_TRIGGER                       0x00000001 /* -W--T */
#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS(i)                    (0x00616568+(i)*2048) /* RWI4A */
#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS__SIZE_1                                   8 /*       */
#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_VALUE                                  16:0 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_VALUE_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS(i)                    (0x0061656C+(i)*2048) /* RWI4A */
#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS__SIZE_1                                   8 /*       */
#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_VALUE                                  20:0 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_VALUE_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_STREAM_CTL(i)                              (0x00616578+(i)*2048) /* RW-4A */
#define NV_PDISP_SF_DP_STREAM_CTL__SIZE_1                                             8 /*       */
#define NV_PDISP_SF_DP_STREAM_CTL_START                                             5:0 /* RWIVF */
#define NV_PDISP_SF_DP_STREAM_CTL_START_INIT                                 0x00000001 /* RWI-V */
#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH                                           13:8 /* RWIVF */
#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_STREAM_CTL_START_ACTIVE                                    21:16 /* R-IVF */
#define NV_PDISP_SF_DP_STREAM_CTL_START_ACTIVE_INIT                          0x00000001 /* R-I-V */
#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_ACTIVE                                   29:24 /* R-IVF */
#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_ACTIVE_INIT                         0x00000000 /* R-I-V */
#define NV_PDISP_SF_DP_STREAM_BW(i)                               (0x0061657C+(i)*2048) /* RW-4A */
#define NV_PDISP_SF_DP_STREAM_BW__SIZE_1                                              8 /*       */
#define NV_PDISP_SF_DP_STREAM_BW_ALLOCATED                                         15:0 /* RWIVF */
#define NV_PDISP_SF_DP_STREAM_BW_ALLOCATED_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_STREAM_BW_TIMESLICE                                        31:16 /* RWIVF */
#define NV_PDISP_SF_DP_STREAM_BW_TIMESLICE_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED__SIZE_1                                    8 /*       */
#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED__SIZE_2                                    6 /*       */
#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED_VALUE                                   31:0 /* RWIVF */
#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED_VALUE_INIT                        0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_STREAM_BW_RESERVED__SIZE_1                                     8 /*       */
#define NV_PDISP_SF_DP_STREAM_BW_RESERVED__SIZE_2                                     6 /*       */
#define NV_PDISP_SF_DP_STREAM_BW_RESERVED_VALUE                                    31:0 /* RWIVF */
#define NV_PDISP_SF_DP_STREAM_BW_RESERVED_VALUE_INIT                         0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY(i,j) (((j)==0)?(0x00616578+(i)*2048):(0x00616584+(i)*2048)+((j)-1)*8) /*       */
#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY__SIZE_1                                                                               8 /*       */
#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY__SIZE_2                                                                               2 /*       */
#define NV_PDISP_SF_DP_STREAM_BW_ARRAY(i,j)    (((j)==0)?(0x0061657C+(i)*2048):(0x00616588+(i)*2048)+((j)-1)*8) /*       */
#define NV_PDISP_SF_DP_STREAM_BW_ARRAY__SIZE_1                                                                                8 /*       */
#define NV_PDISP_SF_DP_STREAM_BW_ARRAY__SIZE_2                                                                                2 /*       */
#define NV_PDISP_SF_HDMI_CTRL(i)                                  (0x006165C0+(i)*2048) /* RWX4A */
#define NV_PDISP_SF_HDMI_CTRL__SIZE_1                                                 8 /*       */
#define NV_PDISP_SF_HDMI_CTRL_REKEY                                                 6:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_CTRL_REKEY_INIT                                     0x00000038 /* RWI-V */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT                                          8:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_2CH                               0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_8CH                               0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT                                 10:10 /* RWIVF */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT_HW_BASED                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT_SW_BASED                   0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT                                         12:12 /* RWIVF */
#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT_CLR                                0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT_SET                                0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_CTRL_MAX_AC_PACKET                                       20:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_CTRL_MAX_AC_PACKET_INIT                             0x00000002 /* RWI-V */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO                                               24:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO_DIS                                      0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_CTRL_AUDIO_EN                                       0x00000001 /* RWI-V */
#define NV_PDISP_SF_HDMI_CTRL_ENABLE                                              30:30 /* RWIVF */
#define NV_PDISP_SF_HDMI_CTRL_ENABLE_NO                                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_CTRL_ENABLE_YES                                     0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_CTRL_ENABLE_DIS                                     0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_CTRL_ENABLE_EN                                      0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW(i)                          (0x006165C8+(i)*2048) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW__SIZE_1                                         8 /*       */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_END                                           9:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_END_INIT                               0x00000210 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_START                                       25:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_START_INIT                             0x00000200 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE                                      31:31 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_NO                              0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_YES                             0x00000001 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_DIS                             0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_EN                              0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL(i)                    (0x006F0000+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1                                   8 /*       */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE                                  0:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO                        0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES                       0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS                       0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN                        0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER                                   4:4 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS                        0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN                         0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE                                  8:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN                        0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW                               9:9 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE                 0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE                0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT                   0x00000001 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS(i)                  (0x006F0004+(i)*1024) /* R--4A */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT                                  0:0 /* R-IVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE                      0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING                   0x00000000 /* R---V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT                      0x00000000 /* R-I-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER(i)                  (0x006F0008+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB0                                   7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB1                                  15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB2                                 23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i)            (0x006F000C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1                           8 /*       */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0                             7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1                            15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2                           23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3                           31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i)           (0x006F0010+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1                          8 /*       */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4                            7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5                           15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6                          23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i)            (0x006F0014+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1                           8 /*       */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7                             7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8                            15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9                           23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10                          31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT                0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i)           (0x006F0018+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1                          8 /*       */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11                           7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12                          15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13                         23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL(i)                          (0x006F0040+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL__SIZE_1                                         8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE                                        0:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_NO                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_YES                             0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_DIS                             0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_EN                              0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER                                         4:4 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER_DIS                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER_EN                               0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE                                        8:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE_DIS                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE_EN                              0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK                                      12:12 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK_DIS                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK_EN                              0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GENERIC_STATUS(i)                        (0x006F0044+(i)*1024) /* R--4A */
#define NV_PDISP_SF_HDMI_GENERIC_STATUS__SIZE_1                                       8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT                                        0:0 /* R-IVF */
#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_DONE                            0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_WAITING                         0x00000000 /* R---V */
#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_INIT                            0x00000000 /* R-I-V */
#define NV_PDISP_SF_HDMI_GENERIC_HEADER(i)                        (0x006F0048+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_HEADER__SIZE_1                                       8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB0                                         7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB0_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB1                                        15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB1_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB2                                       23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB2_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW(i)                  (0x006F004C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0                                   7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1                                  15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2                                 23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3                                 31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH(i)                 (0x006F0050+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1                                8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4                                  7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5                                 15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6                                23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW(i)                  (0x006F0054+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7                                   7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8                                  15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9                                 23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10                                31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH(i)                 (0x006F0058+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1                                8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11                                 7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12                                15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13                               23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW(i)                  (0x006F005C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14                                  7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15                                 15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16                                23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17                                31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH(i)                 (0x006F0060+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1                                8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18                                 7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19                                15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20                               23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW(i)                  (0x006F0064+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21                                  7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22                                 15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23                                23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24                                31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH(i)                 (0x006F0068+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1                                8 /*       */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25                                 7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26                                15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27                               23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_ACR_CTRL(i)                              (0x006F0080+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_ACR_CTRL__SIZE_1                                             8 /*       */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE                                     0:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_NO                           0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_YES                          0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_DIS                          0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_EN                           0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE                                    16:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_NO                            0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_YES                           0x00000001 /* RWI-V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_DIS                           0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_EN                            0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY                                        20:20 /* RWIVF */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_HIGH                              0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_LOW                               0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS                                           27:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_INIT                                 0x00000002 /* RWI-V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_32KHZ                                0x00000003 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_44_1KHZ                              0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_48KHZ                                0x00000002 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_88_2KHZ                              0x00000008 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_96KHZ                                0x0000000A /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_176_4KHZ                             0x0000000C /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_192KHZ                               0x0000000E /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE                                      31:31 /* RWIVF */
#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_INIT                            0x00000001 /* RWI-V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_HW                              0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_SW                              0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_GCP_CTRL(i)                              (0x006F00C0+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GCP_CTRL__SIZE_1                                             8 /*       */
#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE                                            0:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_NO                                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_YES                                 0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_DIS                                 0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_EN                                  0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER                                             4:4 /* RWIVF */
#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER_DIS                                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER_EN                                   0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE                                            8:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE_DIS                                 0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE_EN                                  0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GCP_STATUS(i)                            (0x006F00C4+(i)*1024) /* R--4A */
#define NV_PDISP_SF_HDMI_GCP_STATUS__SIZE_1                                           8 /*       */
#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT                                            0:0 /* R-IVF */
#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_DONE                                0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_WAITING                             0x00000000 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_INIT                                0x00000000 /* R-I-V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP                                 6:4 /* R--VF */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_0                        0x00000004 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_1                        0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_2                        0x00000002 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_3                        0x00000003 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP                                  10:8 /* R--VF */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_0                          0x00000004 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_1                          0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_2                          0x00000002 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_3                          0x00000003 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP                                14:12 /* R--VF */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_0                         0x00000004 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_1                         0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_2                         0x00000002 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_3                         0x00000003 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP                                  18:16 /* R--VF */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_0                           0x00000004 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_1                           0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_2                           0x00000002 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_3                           0x00000003 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP                                22:20 /* R--VF */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_0                         0x00000004 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_1                         0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_2                         0x00000002 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_3                         0x00000003 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP                                  26:24 /* R--VF */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_0                           0x00000004 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_1                           0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_2                           0x00000002 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_3                           0x00000003 /* R---V */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK(i)                           (0x006F00CC+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK__SIZE_1                                          8 /*       */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0                                            7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_INIT                                0x00000001 /* RWI-V */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE                          0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE                          0x00000010 /* RW--V */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1                                           15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB2                                          23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB2_INIT                                0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_CTRL(i)                          (0x006F0100+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_CTRL__SIZE_1                                         8 /*       */
#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE                                        0:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_NO                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_YES                             0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_DIS                             0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_EN                              0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER                                         4:4 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER_DIS                              0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER_EN                               0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE                                        8:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE_DIS                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE_EN                              0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW                                     9:9 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_EN                           0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_DIS                          0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT                                   16:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_SW_CONTROLLED                0x00000000 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_HW_CONTROLLED                0x00000001 /* RW--V */
#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_STATUS(i)                        (0x006F0104+(i)*1024) /* R--4A */
#define NV_PDISP_SF_HDMI_VSI_STATUS__SIZE_1                                       8 /*       */
#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT                                        0:0 /* R-IVF */
#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_DONE                            0x00000001 /* R---V */
#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_WAITING                         0x00000000 /* R---V */
#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_INIT                            0x00000000 /* R-I-V */
#define NV_PDISP_SF_HDMI_VSI_HEADER(i)                        (0x006F0108+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_HEADER__SIZE_1                                       8 /*       */
#define NV_PDISP_SF_HDMI_VSI_HEADER_HB0                                         7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_HEADER_HB0_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_HEADER_HB1                                        15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_HEADER_HB1_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_HEADER_HB2                                       23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_HEADER_HB2_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW(i)                  (0x006F010C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB0                                   7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB1                                  15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB2                                 23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB3                                 31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH(i)                 (0x006F0110+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1                                8 /*       */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4                                  7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB5                                 15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB6                                23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW(i)                  (0x006F0114+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB7                                   7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB8                                  15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB9                                 23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB10                                31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH(i)                 (0x006F0118+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1                                8 /*       */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB11                                 7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB12                                15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB13                               23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW(i)                  (0x006F011C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB14                                  7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB15                                 15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB16                                23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB17                                31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH(i)                 (0x006F0120+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1                                8 /*       */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB18                                 7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB19                                15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB20                               23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW(i)                  (0x006F0124+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB21                                  7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB22                                 15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB23                                23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB24                                31:24 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT                      0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH(i)                 (0x006F0128+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1                                8 /*       */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB25                                 7:0 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB26                                15:8 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB27                               23:16 /* RWIVF */
#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL(i)                  (0x006F0300+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE                                0:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_YES                     0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_NO                      0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_INIT                    0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE                             1:1 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_INIT                 0x00000000 /* R-I-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_DONE                 0x00000000 /* R---V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_PENDING              0x00000001 /* R---V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_TRIGGER              0x00000001 /* -W--T */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE                   2:2 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_YES        0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_NO         0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_INIT       0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER(i)                (0x006F0304+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER__SIZE_1                               8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB0                                 7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB0_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB1                                15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB1_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB2                               23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB2_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB3                               31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB3_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0(i)              (0x006F0308+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB0                               7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB0_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB1                              15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB1_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB2                             23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB2_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB3                             31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB3_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1(i)              (0x006F030C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB4                               7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB4_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB5                              15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB5_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB6                             23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB6_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB7                             31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB7_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2(i)              (0x006F0310+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB8                               7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB8_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB9                              15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB9_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB10                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB10_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB11                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB11_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3(i)              (0x006F0314+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB12                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB12_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB13                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB13_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB14                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB14_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB15                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB15_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4(i)              (0x006F0318+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB16                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB16_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB17                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB17_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB18                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB18_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB19                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB19_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5(i)              (0x006F031C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB20                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB20_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB21                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB21_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB22                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB22_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB23                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB23_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6(i)              (0x006F0320+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB24                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB24_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB25                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB25_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB26                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB26_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB27                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB27_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7(i)              (0x006F0324+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB28                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB28_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB29                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB29_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB30                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB30_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB31                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB31_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL(i)                     (0x006F0330+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL__SIZE_1                                    8 /*       */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE                          4:4 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_ENABLE            0x00000001 /* RW--V */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_DISABLE           0x00000000 /* RW--V */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_INIT              0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER(i)                  (0x006F0334+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER__SIZE_1                                 8 /*       */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB0                                   7:0 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB0_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB1                                  15:8 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB1_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB2                                 23:16 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB2_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB3                                 31:24 /* RWIVF */
#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB3_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER(i)                (0x006F0344+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER__SIZE_1                               8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB0                                 7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB0_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB1                                15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB1_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB2                               23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB2_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB3                               31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB3_INIT                     0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0(i)              (0x006F0348+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB0                               7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB0_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB1                              15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB1_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB2                             23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB2_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB3                             31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB3_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1(i)              (0x006F034C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB4                               7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB4_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB5                              15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB5_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB6                             23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB6_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB7                             31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB7_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2(i)              (0x006F0350+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB8                               7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB8_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB9                              15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB9_INIT                   0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB10                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB10_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB11                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB11_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3(i)              (0x006F0354+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB12                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB12_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB13                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB13_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB14                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB14_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB15                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB15_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4(i)              (0x006F0358+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB16                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB16_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB17                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB17_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB18                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB18_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB19                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB19_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5(i)              (0x006F035C+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB20                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB20_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB21                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB21_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB22                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB22_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB23                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB23_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6(i)              (0x006F0360+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB24                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB24_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB25                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB25_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB26                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB26_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB27                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB27_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7(i)              (0x006F0364+(i)*1024) /* RWX4A */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7__SIZE_1                             8 /*       */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB28                              7:0 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB28_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB29                             15:8 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB29_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB30                            23:16 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB30_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB31                            31:24 /* RWIVF */
#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB31_INIT                  0x00000000 /* RWI-V */
#define NV_PDISP_SOR_CAP(i)                                       (0x0061C000+(i)*2048) /* R--4A */
#define NV_PDISP_SOR_CAP__SIZE_1                                                      8 /*       */
#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18                                             0:0 /* R--VF */
#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18_FALSE                                0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18_TRUE                                 0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24                                             1:1 /* R--VF */
#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24_FALSE                                0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24_TRUE                                 0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_DUAL_LVDS_18                                               2:2 /* R--VF */
#define NV_PDISP_SOR_CAP_DUAL_LVDS_18_FALSE                                  0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_DUAL_LVDS_18_TRUE                                   0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_DUAL_LVDS_24                                               3:3 /* R--VF */
#define NV_PDISP_SOR_CAP_DUAL_LVDS_24_FALSE                                  0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_DUAL_LVDS_24_TRUE                                   0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A                                              8:8 /* R--VF */
#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A_FALSE                                 0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A_TRUE                                  0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B                                              9:9 /* R--VF */
#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B_FALSE                                 0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B_TRUE                                  0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_DUAL_TMDS                                                11:11 /* R--VF */
#define NV_PDISP_SOR_CAP_DUAL_TMDS_FALSE                                     0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_DUAL_TMDS_TRUE                                      0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE                                        13:13 /* R--VF */
#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE_FALSE                             0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE_TRUE                              0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_SDI                                                      16:16 /* R--VF */
#define NV_PDISP_SOR_CAP_SDI_FALSE                                           0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_SDI_TRUE                                            0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_DP_A                                                     24:24 /* R--VF */
#define NV_PDISP_SOR_CAP_DP_A_FALSE                                          0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_DP_A_TRUE                                           0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_DP_B                                                     25:25 /* R--VF */
#define NV_PDISP_SOR_CAP_DP_B_FALSE                                          0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_DP_B_TRUE                                           0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_DP_INTERLACE                                             26:26 /* R--VF */
#define NV_PDISP_SOR_CAP_DP_INTERLACE_FALSE                                  0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_DP_INTERLACE_TRUE                                   0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_DP_8_LANES                                               27:27 /* R--VF */
#define NV_PDISP_SOR_CAP_DP_8_LANES_FALSE                                    0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_DP_8_LANES_TRUE                                     0x00000001 /* R---V */
#define NV_PDISP_SOR_CAP_LVDS_ONLY                                                31:31 /* R--VF */
#define NV_PDISP_SOR_CAP_LVDS_ONLY_FALSE                                     0x00000000 /* R---V */
#define NV_PDISP_SOR_CAP_LVDS_ONLY_TRUE                                      0x00000001 /* R---V */
#define NV_PDISP_SOR_PWR(i)                                       (0x0061C004+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_PWR__SIZE_1                                                      8 /*       */
#define NV_PDISP_SOR_PWR_NORMAL_STATE                                               0:0 /* RWIVF */
#define NV_PDISP_SOR_PWR_NORMAL_STATE_INIT                                   0x00000000 /* RWI-V */
#define NV_PDISP_SOR_PWR_NORMAL_STATE_PD                                     0x00000000 /* RW--V */
#define NV_PDISP_SOR_PWR_NORMAL_STATE_PU                                     0x00000001 /* RW--V */
#define NV_PDISP_SOR_PWR_NORMAL_START                                               1:1 /* RWIVF */
#define NV_PDISP_SOR_PWR_NORMAL_START_INIT                                   0x00000000 /* RWI-V */
#define NV_PDISP_SOR_PWR_NORMAL_START_NORMAL                                 0x00000000 /* RW--V */
#define NV_PDISP_SOR_PWR_NORMAL_START_ALT                                    0x00000001 /* RW--V */
#define NV_PDISP_SOR_PWR_SAFE_STATE                                               16:16 /* RWIVF */
#define NV_PDISP_SOR_PWR_SAFE_STATE_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_SOR_PWR_SAFE_STATE_PD                                       0x00000000 /* RW--V */
#define NV_PDISP_SOR_PWR_SAFE_STATE_PU                                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_PWR_SAFE_START                                               17:17 /* RWIVF */
#define NV_PDISP_SOR_PWR_SAFE_START_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_SOR_PWR_SAFE_START_NORMAL                                   0x00000000 /* RW--V */
#define NV_PDISP_SOR_PWR_SAFE_START_ALT                                      0x00000001 /* RW--V */
#define NV_PDISP_SOR_PWR_HALT_DELAY                                               24:24 /* R--VF */
#define NV_PDISP_SOR_PWR_HALT_DELAY_DONE                                     0x00000000 /* R---V */
#define NV_PDISP_SOR_PWR_HALT_DELAY_ACTIVE                                   0x00000001 /* R---V */
#define NV_PDISP_SOR_PWR_MODE                                                     28:28 /* R-IVF */
#define NV_PDISP_SOR_PWR_MODE_INIT                                           0x00000001 /* R-I-V */
#define NV_PDISP_SOR_PWR_MODE_NORMAL                                         0x00000000 /* R---V */
#define NV_PDISP_SOR_PWR_MODE_SAFE                                           0x00000001 /* R---V */
#define NV_PDISP_SOR_PWR_SETTING_NEW                                              31:31 /* RWIVF */
#define NV_PDISP_SOR_PWR_SETTING_NEW_INIT                                    0x00000000 /* R-I-V */
#define NV_PDISP_SOR_PWR_SETTING_NEW_DONE                                    0x00000000 /* R---V */
#define NV_PDISP_SOR_PWR_SETTING_NEW_PENDING                                 0x00000001 /* R---V */
#define NV_PDISP_SOR_PWR_SETTING_NEW_TRIGGER                                 0x00000001 /* -W--V */
#define NV_PDISP_SOR_TEST(i)                                      (0x0061C008+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_TEST__SIZE_1                                                     8 /*       */
#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE                                           9:8 /* R--UF */
#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_SLEEP                              0x00000000 /* R---V */
#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE                             0x00000001 /* R---V */
#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_AWAKE                              0x00000002 /* R---V */
#define NV_PDISP_SOR_TEST_OWNER_MASK                                              13:10 /* R--UF */
#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD0                                   0x00000001 /* R---V */
#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD1                                   0x00000002 /* R---V */
#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD2                                   0x00000004 /* R---V */
#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD3                                   0x00000008 /* R---V */
#define NV_PDISP_SOR_TEST_OWNER_MASK_NONE                                    0x00000000 /* R---V */
#define NV_PDISP_SOR_PWM_DIV(i)                                   (0x0061C080+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_PWM_DIV__SIZE_1                                                  8 /*       */
#define NV_PDISP_SOR_PWM_DIV_DIVIDE                                                23:0 /* RWIUF */
#define NV_PDISP_SOR_PWM_DIV_DIVIDE_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_SOR_PWM_CTL(i)                                   (0x0061C084+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_PWM_CTL__SIZE_1                                                  8 /*       */
#define NV_PDISP_SOR_PWM_CTL_DUTY_CYCLE                                            23:0 /* RWIUF */
#define NV_PDISP_SOR_PWM_CTL_DUTY_CYCLE_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_SOR_PWM_CTL_CLKSEL                                               30:30 /* RWIUF */
#define NV_PDISP_SOR_PWM_CTL_CLKSEL_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_SOR_PWM_CTL_CLKSEL_PCLK                                     0x00000000 /* RW--V */
#define NV_PDISP_SOR_PWM_CTL_CLKSEL_XTAL                                     0x00000001 /* RW--V */
#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW                                          31:31 /* RWIVF */
#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_INIT                                0x00000000 /* R-I-V */
#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_DONE                                0x00000000 /* R---V */
#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_PENDING                             0x00000001 /* R---V */
#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_TRIGGER                             0x00000001 /* -W--V */
#define NV_PDISP_SOR_DP_LINKCTL(i,j)                      (0x0061C10C+(i)*2048+(j)*128) /* RW-4A */
#define NV_PDISP_SOR_DP_LINKCTL__SIZE_1                                               8 /*       */
#define NV_PDISP_SOR_DP_LINKCTL__SIZE_2                                               2 /*       */
#define NV_PDISP_SOR_DP_LINKCTL_ENABLE                                              0:0 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_INIT                                  0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_YES                                   0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_NO                                    0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK                                    1:1 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_INIT                        0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_DISABLE                     0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_ENABLE                      0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME                                     14:14 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT                                         23:16 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_ZERO                               0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_ONE                                0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_TWO                                0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_FOUR                               0x0000000F /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_EIGHT                              0x000000FF /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN                                     27:26 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_INIT                           0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_NOPATTERN                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_D102                           0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_SBLERRRATE                     0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_PRBS7                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE                                       30:30 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_INIT                             0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_SINGLE_STREAM                    0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_MULTI_STREAM                     0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN                                   31:31 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_INIT                         0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO                           0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0__SIZE_1                                              8 /*       */
#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE                                             0:0 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_YES                                  0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_NO                                   0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK                                   1:1 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_DISABLE                    0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_ENABLE                     0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME                                    14:14 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_DISABLE                       0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_ENABLE                        0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT                                        23:16 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_ZERO                              0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_ONE                               0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_TWO                               0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_FOUR                              0x0000000F /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_EIGHT                             0x000000FF /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN                                    27:26 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_NOPATTERN                     0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_D102                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_SBLERRRATE                    0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_PRBS7                         0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE                                      30:30 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_SINGLE_STREAM                   0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_MULTI_STREAM                    0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN                                  31:31 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_INIT                        0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_NO                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_YES                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1__SIZE_1                                              8 /*       */
#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE                                             0:0 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_INIT                                 0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_YES                                  0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_NO                                   0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK                                   1:1 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_INIT                       0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_DISABLE                    0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_ENABLE                     0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME                                    14:14 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_DISABLE                       0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_ENABLE                        0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT                                        23:16 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_ZERO                              0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_ONE                               0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_TWO                               0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_FOUR                              0x0000000F /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_EIGHT                             0x000000FF /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN                                    27:26 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_INIT                          0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_NOPATTERN                     0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_D102                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_SBLERRRATE                    0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_PRBS7                         0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE                                      30:30 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_INIT                            0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_SINGLE_STREAM                   0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_MULTI_STREAM                    0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN                                  31:31 /* RWIVF */
#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_INIT                        0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_NO                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_YES                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG(i,j)                           (0x0061C110+(i)*2048+(j)*28) /* RW-4A */
#define NV_PDISP_SOR_DP_TPG__SIZE_1                                                   8 /*       */
#define NV_PDISP_SOR_DP_TPG__SIZE_2                                                   2 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN                                           3:0 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN                                       4:4 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING                                     6:6 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN                                          11:8 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN                                     12:12 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING                                   14:14 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN                                         19:16 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN                                     20:20 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING                                   22:22 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN                                         27:24 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN                                     28:28 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING                                   30:30 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN(i)                           (3+(i)*8):((i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN__SIZE_1                                      4 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_NOPATTERN                           0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING1                           0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING2                           0x00000002 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING3                           0x00000003 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_D102                                0x00000004 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_SBLERRRATE                          0x00000005 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_PRBS7                               0x00000006 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CSTM                                0x00000007 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_HBR2_COMPLIANCE                     0x00000008 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CP2520_PAT1                         0x00000009 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CP2520_PAT3                         0x0000000A /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING4                           0x0000000B /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN(i)                     (4+(i)*8):(4+(i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN__SIZE_1                                  4 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_INIT                            0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_ENABLE                          0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_DISABLE                         0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING(i)                   (6+(i)*8):(6+(i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING__SIZE_1                                4 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_INIT                          0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_ENABLE                        0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_DISABLE                       0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG0__SIZE_1                                                   8 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN                                           3:0 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN                                       4:4 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING                                     6:6 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN                                          11:8 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN                                     12:12 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING                                   14:14 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN                                         19:16 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN                                     20:20 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING                                   22:22 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN                                         27:24 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN                                     28:28 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING                                   30:30 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN(i)                           (3+(i)*8):((i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN__SIZE_1                                      4 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_NOPATTERN                           0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING1                           0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING2                           0x00000002 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING3                           0x00000003 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_D102                                0x00000004 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_SBLERRRATE                          0x00000005 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_PRBS7                               0x00000006 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CSTM                                0x00000007 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_HBR2_COMPLIANCE                     0x00000008 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CP2520_PAT1                         0x00000009 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CP2520_PAT3                         0x0000000A /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING4                           0x0000000B /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN(i)                     (4+(i)*8):(4+(i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN__SIZE_1                                  4 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_INIT                            0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_ENABLE                          0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_DISABLE                         0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING(i)                   (6+(i)*8):(6+(i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING__SIZE_1                                4 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_INIT                          0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_ENABLE                        0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_DISABLE                       0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG1__SIZE_1                                                   8 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN                                           3:0 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN                                       4:4 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING                                     6:6 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN                                          11:8 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN                                     12:12 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING                                   14:14 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN                                         19:16 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN                                     20:20 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING                                   22:22 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN                                         27:24 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_INIT                               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_NOPATTERN                          0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING1                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING2                          0x00000002 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING3                          0x00000003 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_D102                               0x00000004 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_SBLERRRATE                         0x00000005 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_PRBS7                              0x00000006 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CSTM                               0x00000007 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_HBR2_COMPLIANCE                    0x00000008 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CP2520_PAT1                        0x00000009 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CP2520_PAT3                        0x0000000A /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING4                          0x0000000B /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN                                     28:28 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING                                   30:30 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_ENABLE                       0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_DISABLE                      0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN(i)                           (3+(i)*8):((i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN__SIZE_1                                      4 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_NOPATTERN                           0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING1                           0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING2                           0x00000002 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING3                           0x00000003 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_D102                                0x00000004 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_SBLERRRATE                          0x00000005 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_PRBS7                               0x00000006 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CSTM                                0x00000007 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_HBR2_COMPLIANCE                     0x00000008 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CP2520_PAT1                         0x00000009 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CP2520_PAT3                         0x0000000A /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING4                           0x0000000B /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN(i)                     (4+(i)*8):(4+(i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN__SIZE_1                                  4 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_INIT                            0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_ENABLE                          0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_DISABLE                         0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING(i)                   (6+(i)*8):(6+(i)*8) /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING__SIZE_1                                4 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_INIT                          0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_ENABLE                        0x00000001 /*       */
#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_DISABLE                       0x00000000 /*       */
#define NV_PDISP_SOR_DP_TPG_CONFIG(i)                             (0x0061C114+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_DP_TPG_CONFIG__SIZE_1                                            8 /*       */
#define NV_PDISP_SOR_DP_TPG_CONFIG_HBR2_COMPLIANCE_PERIOD                          16:0 /* RWIVF */
#define NV_PDISP_SOR_DP_TPG_CONFIG_HBR2_COMPLIANCE_PERIOD_INIT               0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_MS_CTL(i)                                 (0x0061C150+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_DP_MS_CTL__SIZE_1                                                8 /*       */
#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT                                            0:0 /* RWIVF */
#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_INIT                                0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_DISABLE                             0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_ENABLE                              0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_MS_CTL_SF_MASK                                             11:8 /* RWIVF */
#define NV_PDISP_SOR_DP_MS_CTL_SF_MASK_INIT                                  0x0000000F /* RWI-V */
#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE              29:29 /* RWIVF */
#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_INIT   0x00000000  /* R-I-V */
#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_YES    0x00000001  /* R---V */
#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_NO     0x00000000  /* R---V */
#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_RESET  0x00000000  /* -W--V */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH                                     30:30 /* RWIVF */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_INIT                           0x00000001 /* RWI-V */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_ENABLE                         0x00000001 /* RW--V */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_DISABLE                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE                                     31:31 /* RWIVF */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_INIT                           0x00000000 /* R-I-V */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_DONE                           0x00000000 /* R---V */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_PENDING                        0x00000001 /* R---V */
#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_TRIGGER                        0x00000001 /* -W--V */
#define NV_PDISP_SOR_DP_LQ_CSTM(i,j)                        (0x0061C154+(i)*2048+(j)*4) /* RW-4A */
#define NV_PDISP_SOR_DP_LQ_CSTM__SIZE_1                                               8 /*       */
#define NV_PDISP_SOR_DP_LQ_CSTM__SIZE_2                                               3 /*       */
#define NV_PDISP_SOR_DP_LQ_CSTM_SYM                                                31:0 /* RWIUF */
#define NV_PDISP_SOR_DP_LQ_CSTM_SYM_INIT                                     0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LQ_CSTM0(i)                               (0x0061C154+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_DP_LQ_CSTM0__SIZE_1                                              8 /*       */
#define NV_PDISP_SOR_DP_LQ_CSTM0_SYM                                               31:0 /* RWIUF */
#define NV_PDISP_SOR_DP_LQ_CSTM0_SYM_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LQ_CSTM1(i)                               (0x0061C158+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_DP_LQ_CSTM1__SIZE_1                                              8 /*       */
#define NV_PDISP_SOR_DP_LQ_CSTM1_SYM                                               31:0 /* RWIUF */
#define NV_PDISP_SOR_DP_LQ_CSTM1_SYM_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_LQ_CSTM2(i)                               (0x0061C15C+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_DP_LQ_CSTM2__SIZE_1                                              8 /*       */
#define NV_PDISP_SOR_DP_LQ_CSTM2_SYM                                               31:0 /* RWIUF */
#define NV_PDISP_SOR_DP_LQ_CSTM2_SYM_INIT                                    0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_ECF0(i)                                     (0x0061C160+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_DP_ECF0__SIZE_1                                                    8 /*       */
#define NV_PDISP_SOR_DP_ECF0_VALUE                                                   31:0 /* RWIVF */
#define NV_PDISP_SOR_DP_ECF0_VALUE_INIT                                        0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_ECF0_VALUE_ZERO                                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_ECF1(i)                                     (0x0061C164+(i)*2048) /* RW-4A */
#define NV_PDISP_SOR_DP_ECF1__SIZE_1                                                    8 /*       */
#define NV_PDISP_SOR_DP_ECF1_VALUE                                                   30:0 /* RWIVF */
#define NV_PDISP_SOR_DP_ECF1_VALUE_INIT                                        0x00000000 /* RWI-V */
#define NV_PDISP_SOR_DP_ECF1_VALUE_ZERO                                        0x00000000 /* RW--V */
#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS                                           31:31 /* RWIVF */
#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_INIT                                 0x00000000 /* R-I-V */
#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_DONE                                 0x00000000 /* R---V */
#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_PENDING                              0x00000001 /* R---V */
#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_TRIGGER                              0x00000001 /* -W--V */
#define NV_PDISP_SOR_HDMI2_CTRL(i)                                (0x0061C5BC+(i)*2048) /* RWX4A */
#define NV_PDISP_SOR_HDMI2_CTRL__SIZE_1                                               8 /*       */
#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE                                            0:0 /* RWIVF */
#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE                              0x00000001 /* RW--V */
#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_DISABLE                             0x00000000 /* RWI-V */
#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE                                          1:1 /* RWIVF */
#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE_NORMAL                            0x00000000 /* RWI-V */
#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4                          0x00000001 /* RW--V */
#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV                                   2:2 /* RWIVF */
#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV_DISABLE                    0x00000000 /* RWI-V */
#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV_ENABLE                     0x00000001 /* RW--V */
#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_LENGTH                                         7:4 /* RWIVF */
#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_LENGTH_INIT                             0x00000008 /* RWI-V */
#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_START                                        31:16 /* RWIVF */
#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_START_INIT                              0x00000214 /* RWI-V */
#define NV_PDISP_VGA_INDIRECT_SCRATCH(i)                             (0x00625E00+(i)*4) /* RW-4A */
#define NV_PDISP_VGA_INDIRECT_SCRATCH__SIZE_1                                        16 /*       */
#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE3                                       31:24 /* RWX-F */
#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE2                                       23:16 /* RWX-F */
#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE1                                        15:8 /* RWX-F */
#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE0                                         7:0 /* RWX-F */
#define NV_PDISP_VGA_BASE                                                    0x00625F00 /* RW-4R */
#define NV_PDISP_VGA_BASE_TARGET                                                    1:0 /* RWIVF */
#define NV_PDISP_VGA_BASE_TARGET_PHYS_INIT                                   0x00000001 /* RWI-V */
#define NV_PDISP_VGA_BASE_TARGET_PHYS_NVM                                    0x00000001 /* RW--V */
#define NV_PDISP_VGA_BASE_TARGET_PHYS_PCI                                    0x00000002 /* RW--V */
#define NV_PDISP_VGA_BASE_TARGET_PHYS_PCI_COHERENT                           0x00000003 /* RW--V */
#define NV_PDISP_VGA_BASE_STATUS                                                    3:3 /* RWIVF */
#define NV_PDISP_VGA_BASE_STATUS_INIT                                        0x00000000 /* RWI-V */
#define NV_PDISP_VGA_BASE_STATUS_INVALID                                     0x00000000 /* RW--V */
#define NV_PDISP_VGA_BASE_STATUS_VALID                                       0x00000001 /* RW--V */
#define NV_PDISP_VGA_BASE_ADDR                                                    31:10 /* RWIVF */
#define NV_PDISP_VGA_BASE_ADDR_INIT                                          0x00000000 /* RWI-V */
#define NV_PDISP_VGA_WORKSPACE_BASE                                          0x00625F04 /* RW-4R */
#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET                                          1:0 /* RWIVF */
#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_INIT                         0x00000001 /* RWI-V */
#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_NVM                          0x00000001 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_PCI                          0x00000002 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_PCI_COHERENT                 0x00000003 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS                                          3:3 /* RWIVF */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_INIT                              0x00000000 /* RWI-V */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_INVALID                           0x00000000 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID                             0x00000001 /* RW--V */
#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR                                           31:8 /* RWIVF */
#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR_INIT                                0x00000000 /* RWI-V */
#define NV_UDISP                                                   0x006FFFFF:0x00670000 /* RW--D */
#define NV_UDISP_PVT                                               0x0067FFFF:0x00670000 /* RW--D */
#define NV_UDISP_CORE                                              0x0068FFFF:0x00680000 /* RW--D */
#define NV_UDISP_REMAP                                             0x006FFFFF:0x00690000 /* RW--D */
#define NV_UDISP_REMAP_PAGE0                                       0x0069FFFF:0x00690000 /* RW--D */
#define NV_UDISP_REMAP_PAGE1                                       0x006AFFFF:0x006A0000 /* RW--D */
#define NV_UDISP_REMAP_PAGE2                                       0x006BFFFF:0x006B0000 /* RW--D */
#define NV_UDISP_REMAP_PAGE3                                       0x006CFFFF:0x006C0000 /* RW--D */
#define NV_UDISP_REMAP_PAGE4                                       0x006DFFFF:0x006D0000 /* RW--D */
#define NV_UDISP_REMAP_PAGE5                                       0x006EFFFF:0x006E0000 /* RW--D */
#define NV_UDISP_REMAP_PAGE6                                       0x006FFFFF:0x006F0000 /* RW--D */
#define NV_UDISP_FE_CORE_PUT                                                  0x00680000 /* RW-4R */
#define NV_UDISP_FE_CORE_PUT_POINTER                                                11:2 /* RWIUF */
#define NV_UDISP_FE_CORE_PUT_POINTER_INIT                                     0x00000000 /* RWI-V */
#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS                                        31:31 /* R-IVF */
#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_INIT                              0x00000001 /* R-I-V */
#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_WRITABLE                          0x00000000 /* R---V */
#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_LOCKED                            0x00000001 /* R---V */
#define NV_UDISP_FE_CORE_GET                                                  0x00680004 /* R--4R */
#define NV_UDISP_FE_CORE_GET_POINTER                                                11:2 /* R--UF */
#define NV_UDISP_FE_SAT_PUT(i)                                     (0x00690000+(i)*4096) /* RW-4A */
#define NV_UDISP_FE_SAT_PUT__SIZE_1                                                   72 /*       */
#define NV_UDISP_FE_SAT_PUT_POINTER                                                 11:2 /* RWIUF */
#define NV_UDISP_FE_SAT_PUT_POINTER_INIT                                      0x00000000 /* RWI-V */
#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS                                         31:31 /* R-IVF */
#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_INIT                               0x00000001 /* R-I-V */
#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_WRITABLE                           0x00000000 /* R---V */
#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_LOCKED                             0x00000001 /* R---V */
#define NV_UDISP_FE_SAT_GET(i)                                     (0x00690004+(i)*4096) /* R--4A */
#define NV_UDISP_FE_SAT_GET__SIZE_1                                                   72 /*       */
#define NV_UDISP_FE_SAT_GET_POINTER                                                 11:2 /* R--UF */
#define NV_UDISP_FE_PUT(i)     ((i)>0?((0x00690000+((i-1)*4096))):0x00680000) /*       */
#define NV_UDISP_FE_PUT__SIZE_1                                                       73 /*       */
#define NV_UDISP_FE_PUT_POINTER                                                     11:2 /*       */
#define NV_UDISP_FE_PUT_POINTER_INIT                                          0x00000000 /*       */
#define NV_UDISP_FE_PUT_POINTER_STATUS                                             31:31 /*       */
#define NV_UDISP_FE_PUT_POINTER_STATUS_INIT                                   0x00000001 /*       */
#define NV_UDISP_FE_PUT_POINTER_STATUS_WRITABLE                               0x00000000 /*       */
#define NV_UDISP_FE_PUT_POINTER_STATUS_LOCKED                                 0x00000001 /*       */
#define NV_UDISP_FE_GET(i)     ((i)>0?((0x00690004+((i-1)*4096))):0x00680004) /*       */
#define NV_UDISP_FE_GET__SIZE_1                                                       73 /*       */
#define NV_UDISP_FE_GET_POINTER                                                     11:2 /*       */
#define NV_UDISP_FE_CHN_ARMED_PCALC                                           0x00670000 /* R--4R */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN_PVT(i)                    (0x00674000+(i)*1024) /* R--4A */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN_PVT__SIZE_1                                  32 /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN_PVT(i)                   (0x00674200+(i)*1024) /* R--4A */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN_PVT__SIZE_1                                 32 /*       */
#define NV_UDISP_FE_CHN_ASSY_CORE_PVT                                         0x0067E000 /* R--4R */
#define NV_UDISP_FE_CHN_ARMED_CORE_PVT                                        0x0067E800 /* R--4R */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE                           0x00680000 /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE                  (0x00680000+32768) /*       */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i)                     ((0x00690000+(i)*4096)) /*       */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN__SIZE_1                                      32 /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN(i)               ((0x00690000+(i)*4096)+2048) /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN__SIZE_1                                     32 /*       */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i)              ((0x00690000+((i+32)*4096))) /*       */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM__SIZE_1                                    32 /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WINIM(i)        ((0x00690000+((i+32)*4096))+2048) /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WINIM__SIZE_1                                   32 /*       */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i)                       (0x006D8000+(i)*4096) /* RW-4A */
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS__SIZE_1                                      8 /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_CURS(i)                      (0x006D8800+(i)*4096) /* R--4A */
#define NV_UDISP_FE_CHN_ARMED_BASEADR_CURS__SIZE_1                                     8 /*       */
#define NV_UDISP_FE_CHN_ASSY_BASEADR(i)         ((i)>0?(((0x00690000+(i-1)*4096))):0x00680000) /*       */
#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1                                          81 /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR(i)        ((i)>0?(((0x00690000+(i-1)*4096)+2048)):(0x00680000+32768)) /*       */
#define NV_UDISP_FE_CHN_ARMED_BASEADR__SIZE_1                                         81 /*       */
#define NV_UDISP_FE_CHN_PCALC                                0x00670000 /* R--4R */
#define NV_UDISP_FE_CHN_CORE_PVT                           0x0067E000 /* R--4R */
#define NV_UDISP_FE_CHN_WIN_PVT(i)               (0x00674000+(i)*1024) /* R--4A */
#define NV_UDISP_FE_CHN_WIN_PVT__SIZE_1                                               32 /*       */
#define NV_UDISP_FE_CHN_CORE_VARIABLES                                        0x0067E400 /* R--4R */
#define NV_UDISP_FE_CHN_LOCAL                                                 0x0067E800 /* R--4R */
#define NV_UDISP_FE_CHN_CORE                           0x00680000 /*       */
#define NV_UDISP_FE_CHN_WIN(i)                     (((0x00690000+(i)*4096))) /*       */
#define NV_UDISP_FE_CHN_WIN__SIZE_1                                                   32 /*       */
#define NV_UDISP_FE_CHN_WINIM(i)                 (((0x00690000+((i+32)*4096)))) /*       */
#define NV_UDISP_FE_CHN_WINIM__SIZE_1                                                 32 /*       */
#define NV_UDISP_FE_CHN_CURS(i)                   ((0x006D8000+(i)*4096)) /*       */
#define NV_UDISP_FE_CHN_CURS__SIZE_1                                                   8 /*       */
#define NV_UDISP_FE_CHN_CORE_BASEADR                   0x00680000 /*       */
#define NV_UDISP_FE_CHN_WIN_BASEADR(i)             (((0x00690000+(i)*4096))) /*       */
#define NV_UDISP_FE_CHN_WIN_BASEADR__SIZE_1                                           32 /*       */
#define NV_UDISP_FE_CHN_WINIM_BASEADR(i)         (((0x00690000+((i+32)*4096)))) /*       */
#define NV_UDISP_FE_CHN_WINIM_BASEADR__SIZE_1                                         32 /*       */
#define NV_UDISP_FE_CHN_CURS_BASEADR(i)           ((0x006D8000+(i)*4096)) /*       */
#define NV_UDISP_FE_CHN_CURS_BASEADR__SIZE_1                                           8 /*       */
#define NV_UDISP_DMA                                                                     /* ----G */
#define NV_UDISP_DMA_OPCODE                                                        31:29 /* RWXVF */
#define NV_UDISP_DMA_OPCODE_METHOD                                            0x00000000 /* RW--V */
#define NV_UDISP_DMA_OPCODE_JUMP                                              0x00000001 /* RW--V */
#define NV_UDISP_DMA_OPCODE_NONINC_METHOD                                     0x00000002 /* RW--V */
#define NV_UDISP_DMA_OPCODE_SET_SUBDEVICE_MASK                                0x00000003 /* RW--V */
#define NV_UDISP_DMA_METHOD_COUNT                                                  27:18 /* RWXUF */
#define NV_UDISP_DMA_METHOD_OFFSET                                                  13:2 /* RWXUF */
#define NV_UDISP_DMA_DATA                                                           31:0 /* RWXUF */
#define NV_UDISP_DMA_DATA_NOP                                                 0x00000000 /* RW--V */
#define NV_UDISP_DMA_JUMP_OFFSET                                                    11:2 /* RWXUF */
#define NV_UDISP_DMA_SET_SUBDEVICE_MASK_VALUE                                       11:0 /* RWXUF */