diff options
Diffstat (limited to 'arch/arm/include/asm/arch-mxs')
23 files changed, 0 insertions, 6081 deletions
diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h deleted file mode 100644 index ee56d10..0000000 --- a/arch/arm/include/asm/arch-mxs/clock.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23/i.MX28 Clock - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __CLOCK_H__ -#define __CLOCK_H__ - -enum mxc_clock { - MXC_ARM_CLK = 0, - MXC_AHB_CLK, - MXC_IPG_CLK, - MXC_EMI_CLK, - MXC_GPMI_CLK, - MXC_IO0_CLK, - MXC_IO1_CLK, - MXC_XTAL_CLK, - MXC_SSP0_CLK, -#ifdef CONFIG_MX28 - MXC_SSP1_CLK, - MXC_SSP2_CLK, - MXC_SSP3_CLK, -#endif -}; - -enum mxs_ioclock { - MXC_IOCLK0 = 0, - MXC_IOCLK1, -}; - -enum mxs_sspclock { - MXC_SSPCLK0 = 0, -#ifdef CONFIG_MX28 - MXC_SSPCLK1, - MXC_SSPCLK2, - MXC_SSPCLK3, -#endif -}; - -uint32_t mxc_get_clock(enum mxc_clock clk); - -void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq); -void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal); -void mxs_set_ssp_busclock(unsigned int bus, uint32_t freq); -void mxs_set_lcdclk(uint32_t __maybe_unused lcd_base, uint32_t freq); - -/* Compatibility with the FEC Ethernet driver */ -#define imx_get_fecclk() mxc_get_clock(MXC_AHB_CLK) - -#endif /* __CLOCK_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/gpio.h b/arch/arm/include/asm/arch-mxs/gpio.h deleted file mode 100644 index 34fa421..0000000 --- a/arch/arm/include/asm/arch-mxs/gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 GPIO - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __MX28_GPIO_H__ -#define __MX28_GPIO_H__ - -#ifdef CONFIG_MXS_GPIO -void mxs_gpio_init(void); -#else -inline void mxs_gpio_init(void) {} -#endif - -#endif /* __MX28_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h deleted file mode 100644 index f853c48..0000000 --- a/arch/arm/include/asm/arch-mxs/imx-regs.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23/i.MX28 Registers - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __IMX_REGS_H__ -#define __IMX_REGS_H__ - -#include <asm/mach-imx/regs-apbh.h> -#include <asm/arch/regs-base.h> -#include <asm/mach-imx/regs-bch.h> -#include <asm/arch/regs-digctl.h> -#include <asm/mach-imx/regs-gpmi.h> -#include <asm/mach-imx/regs-lcdif.h> -#include <asm/arch/regs-i2c.h> -#include <asm/arch/regs-lradc.h> -#include <asm/arch/regs-ocotp.h> -#include <asm/arch/regs-pinctrl.h> -#include <asm/arch/regs-rtc.h> -#include <asm/arch/regs-ssp.h> -#include <asm/arch/regs-timrot.h> -#include <asm/arch/regs-usb.h> -#include <asm/arch/regs-usbphy.h> - -#ifdef CONFIG_MX23 -#include <asm/arch/regs-clkctrl-mx23.h> -#include <asm/arch/regs-power-mx23.h> -#endif - -#ifdef CONFIG_MX28 -#include <asm/arch/regs-clkctrl-mx28.h> -#include <asm/arch/regs-power-mx28.h> -#endif - -#endif /* __IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx23.h b/arch/arm/include/asm/arch-mxs/iomux-mx23.h deleted file mode 100644 index 2706efa..0000000 --- a/arch/arm/include/asm/arch-mxs/iomux-mx23.h +++ /dev/null @@ -1,349 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - */ - -#ifndef __MACH_IOMUX_MX23_H__ -#define __MACH_IOMUX_MX23_H__ - -#include <asm/arch/iomux.h> - -/* - * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) -#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0) -#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0) - -#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) - -#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0) -#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) -#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0) -#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0) -#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0) - -#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) -#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1) -#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1) - -#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1) -#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1) -#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1) -#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1) -#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2) -#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2) -#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2) - -#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2) -#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2) -#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2) -#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2) -#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX23_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D08__GPIO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D09__GPIO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D10__GPIO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D11__GPIO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D12__GPIO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D13__GPIO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D14__GPIO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_D15__GPIO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CLE__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_ALE__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY0__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY1__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY2__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDY3__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WPN__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_WRN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_RDN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_CTS__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RTS__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_RX__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_AUART1_TX__GPIO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SCL__GPIO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_I2C_SDA__GPIO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO) - -#define MX23_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RESET__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_RS__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_WR__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_CS__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_DOTCK__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_ENABLE__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_HSYNC__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_LCD_VSYNC__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM0__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM1__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM2__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM3__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_PWM4__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) - -#define MX23_PAD_SSP1_CMD__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DETECT__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA0__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA1__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA2__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_DATA3__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX23_PAD_SSP1_SCK__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYA__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX23_PAD_ROTARYB__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A00__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A01__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A02__GPIO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A03__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A04__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A05__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A06__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A07__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A08__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A09__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A10__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A11__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_A12__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA0__GPIO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_BA1__GPIO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CASN__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE0N__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CE1N__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE1N__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) -#define MX23_PAD_GPMI_CE0N__GPIO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_CKE__GPIO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_RASN__GPIO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO) -#define MX23_PAD_EMI_WEN__GPIO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX23_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/iomux-mx28.h b/arch/arm/include/asm/arch-mxs/iomux-mx28.h deleted file mode 100644 index 00356f0..0000000 --- a/arch/arm/include/asm/arch-mxs/iomux-mx28.h +++ /dev/null @@ -1,531 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010 Freescale Semiconductor, Inc. - */ - -#ifndef __MACH_IOMUX_MX28_H__ -#define __MACH_IOMUX_MX28_H__ - -#include <asm/arch/iomux.h> - -/* - * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode> - * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> - * See also iomux.h - * - * BANK PIN MUX - */ -/* MUXSEL_0 */ -#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0) -#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0) - -#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0) -#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0) -#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0) -#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0) -#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0) -#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0) -#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0) - -#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0) -#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0) -#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0) -#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0) -#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0) - -#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0) -#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0) -#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0) -#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0) -#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0) -#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0) -#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0) -#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0) -#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0) -#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0) -#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0) -#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0) -#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0) -#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0) -#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0) - -#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0) -#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0) -#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0) -#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0) - -#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0) -#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0) -#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0) -#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0) -#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0) -#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0) - -/* MUXSEL_1 */ -#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1) -#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1) - -#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1) -#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1) -#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1) -#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1) -#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1) -#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1) - -#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1) -#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1) -#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1) -#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1) -#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1) - -#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1) -#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1) -#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1) -#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1) -#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1) -#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1) -#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1) -#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1) -#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1) -#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1) -#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1) -#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1) - -#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1) -#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1) - -/* MUXSEL_2 */ -#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2) -#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2) - -#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2) -#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2) -#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2) -#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2) -#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2) -#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2) - -#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2) -#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2) -#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2) -#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2) - -#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2) -#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2) -#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2) -#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2) -#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2) -#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2) -#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2) -#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2) -#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2) -#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2) -#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2) -#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2) - -#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2) -#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2) - -/* MUXSEL_GPIO */ -#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO) - -#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO) - -#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO) - -#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO) -#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO) -#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO) -#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO) -#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO) -#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO) - -#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO) -#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO) -#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO) - -#endif /* __MACH_IOMUX_MX28_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h deleted file mode 100644 index a9896e1..0000000 --- a/arch/arm/include/asm/arch-mxs/iomux.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH, - * <armlinux@phytec.de> - * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MACH_MXS_IOMUX_H__ -#define __MACH_MXS_IOMUX_H__ - -#ifndef __ASSEMBLY__ - -#include <asm/types.h> - -/* - * IOMUX/PAD Bit field definitions - * - * PAD_BANK: 0..2 (3) - * PAD_PIN: 3..7 (5) - * PAD_MUXSEL: 8..9 (2) - * PAD_MA: 10..11 (2) - * PAD_MA_VALID: 12 (1) - * PAD_VOL: 13 (1) - * PAD_VOL_VALID: 14 (1) - * PAD_PULL: 15 (1) - * PAD_PULL_VALID: 16 (1) - * RESERVED: 17..31 (15) - */ -typedef u32 iomux_cfg_t; - -#define MXS_PAD_BANK_SHIFT 0 -#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT) -#define MXS_PAD_PIN_SHIFT 3 -#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT) -#define MXS_PAD_MUXSEL_SHIFT 8 -#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT) -#define MXS_PAD_MA_SHIFT 10 -#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT) -#define MXS_PAD_MA_VALID_SHIFT 12 -#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT) -#define MXS_PAD_VOL_SHIFT 13 -#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT) -#define MXS_PAD_VOL_VALID_SHIFT 14 -#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT) -#define MXS_PAD_PULL_SHIFT 15 -#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT) -#define MXS_PAD_PULL_VALID_SHIFT 16 -#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT) - -#define PAD_MUXSEL_0 0 -#define PAD_MUXSEL_1 1 -#define PAD_MUXSEL_2 2 -#define PAD_MUXSEL_GPIO 3 - -#define PAD_4MA 0 -#define PAD_8MA 1 -#define PAD_12MA 2 -#define PAD_16MA 3 - -#define PAD_1V8 0 -#if defined(CONFIG_MX28) -#define PAD_3V3 1 -#else -#define PAD_3V3 0 -#endif - -#define PAD_NOPULL 0 -#define PAD_PULLUP 1 - -#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) -#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \ - MXS_PAD_MA_VALID_MASK) - -#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) -#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \ - MXS_PAD_VOL_VALID_MASK) - -#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) -#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \ - MXS_PAD_PULL_VALID_MASK) - -/* generic pad control used in most cases */ -#define MXS_PAD_CTRL (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL) - -#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \ - (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \ - ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \ - ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \ - ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \ - ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \ - ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT)) - -/* - * A pad becomes naked, when none of mA, vol or pull - * validity bits is set. - */ -#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \ - MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0) - -static inline unsigned int PAD_BANK(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT; -} - -static inline unsigned int PAD_PIN(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT; -} - -static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT; -} - -static inline unsigned int PAD_MA(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT; -} - -static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT; -} - -static inline unsigned int PAD_VOL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT; -} - -static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT; -} - -static inline unsigned int PAD_PULL(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT; -} - -static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad) -{ - return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT; -} - -/* - * configures a single pad in the iomuxer - */ -int mxs_iomux_setup_pad(iomux_cfg_t pad); - -/* - * configures multiple pads - * convenient way to call the above function with tables - */ -int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count); - -#endif /* __ASSEMBLY__ */ -#endif /* __MACH_MXS_IOMUX_H__*/ diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h deleted file mode 100644 index 44d40ca..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-base.h +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23/i.MX28 Peripheral Base Addresses - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright (C) 2008 Embedded Alley Solutions Inc. - * - * (C) Copyright 2009-2010 Freescale Semiconductor, Inc. - */ - -#ifndef __MXS_REGS_BASE_H__ -#define __MXS_REGS_BASE_H__ - -/* - * Register base addresses for i.MX23 - */ -#if defined(CONFIG_MX23) -#define MXS_ICOLL_BASE 0x80000000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_ECC8_BASE 0x80008000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_ETM_BASE 0x80014000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_EMI_BASE 0x80020000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_SSP1_BASE 0x80034000 -#define MXS_TVENC_BASE 0x80038000 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_AUDIOOUT_BASE 0x80048000 -#define MXS_AUDIOIN_BASE 0x8004C000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_RTC_BASE 0x8005C000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006C000 -#define MXS_UARTAPP1_BASE 0x8006E000 -#define MXS_UARTDBG_BASE 0x80070000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_DRAM_BASE 0x800E0000 - -/* - * Register base addresses for i.MX28 - */ -#elif defined(CONFIG_MX28) -#define MXS_ICOL_BASE 0x80000000 -#define MXS_HSADC_BASE 0x80002000 -#define MXS_APBH_BASE 0x80004000 -#define MXS_PERFMON_BASE 0x80006000 -#define MXS_BCH_BASE 0x8000A000 -#define MXS_GPMI_BASE 0x8000C000 -#define MXS_SSP0_BASE 0x80010000 -#define MXS_SSP1_BASE 0x80012000 -#define MXS_SSP2_BASE 0x80014000 -#define MXS_SSP3_BASE 0x80016000 -#define MXS_PINCTRL_BASE 0x80018000 -#define MXS_DIGCTL_BASE 0x8001C000 -#define MXS_ETM_BASE 0x80022000 -#define MXS_APBX_BASE 0x80024000 -#define MXS_DCP_BASE 0x80028000 -#define MXS_PXP_BASE 0x8002A000 -#define MXS_OCOTP_BASE 0x8002C000 -#define MXS_AXI_AHB0_BASE 0x8002E000 -#define MXS_LCDIF_BASE 0x80030000 -#define MXS_CAN0_BASE 0x80032000 -#define MXS_CAN1_BASE 0x80034000 -#define MXS_SIMDBG_BASE 0x8003C000 -#define MXS_SIMGPMISEL_BASE 0x8003C200 -#define MXS_SIMSSPSEL_BASE 0x8003C300 -#define MXS_SIMMEMSEL_BASE 0x8003C400 -#define MXS_GPIOMON_BASE 0x8003C500 -#define MXS_SIMENET_BASE 0x8003C700 -#define MXS_ARMJTAG_BASE 0x8003C800 -#define MXS_CLKCTRL_BASE 0x80040000 -#define MXS_SAIF0_BASE 0x80042000 -#define MXS_POWER_BASE 0x80044000 -#define MXS_SAIF1_BASE 0x80046000 -#define MXS_LRADC_BASE 0x80050000 -#define MXS_SPDIF_BASE 0x80054000 -#define MXS_RTC_BASE 0x80056000 -#define MXS_I2C0_BASE 0x80058000 -#define MXS_I2C1_BASE 0x8005A000 -#define MXS_PWM_BASE 0x80064000 -#define MXS_TIMROT_BASE 0x80068000 -#define MXS_UARTAPP0_BASE 0x8006A000 -#define MXS_UARTAPP1_BASE 0x8006C000 -#define MXS_UARTAPP2_BASE 0x8006E000 -#define MXS_UARTAPP3_BASE 0x80070000 -#define MXS_UARTAPP4_BASE 0x80072000 -#define MXS_UARTDBG_BASE 0x80074000 -#define MXS_USBPHY0_BASE 0x8007C000 -#define MXS_USBPHY1_BASE 0x8007E000 -#define MXS_USBCTRL0_BASE 0x80080000 -#define MXS_USBCTRL1_BASE 0x80090000 -#define MXS_DFLPT_BASE 0x800C0000 -#define MXS_DRAM_BASE 0x800E0000 -#define MXS_ENET0_BASE 0x800F0000 -#define MXS_ENET1_BASE 0x800F4000 -#else -#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28 -#endif - -#endif /* __MXS_REGS_BASE_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h deleted file mode 100644 index 6e9ffeb..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx23.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23 CLKCTRL Register Definitions - * - * Copyright (C) 2012 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX23_REGS_CLKCTRL_H__ -#define __MX23_REGS_CLKCTRL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ - uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x20 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x30 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x40 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x50 */ - mxs_reg_32(hw_clkctrl_pix) /* 0x60 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x70 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0x80 */ - mxs_reg_32(hw_clkctrl_spdif) /* 0x90 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xa0 */ - - uint32_t reserved1[4]; - - mxs_reg_32(hw_clkctrl_saif0) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_tv) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_etm) /* 0xe0 */ - mxs_reg_8(hw_clkctrl_frac0) /* 0xf0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x100 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x110 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x120 */ - mxs_reg_32(hw_clkctrl_status) /* 0x130 */ - mxs_reg_32(hw_clkctrl_version) /* 0x140 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 16) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_BUSY (1 << 29) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 28) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_AUTO_SLOW_MODE (1 << 20) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_FILT_CLK24M_GATE (1 << 30) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_DRI_CLK24M_GATE (1 << 28) -#define CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE (1 << 27) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_PIX_CLKGATE (1 << 31) -#define CLKCTRL_PIX_BUSY (1 << 29) -#define CLKCTRL_PIX_DIV_FRAC_EN (1 << 12) -#define CLKCTRL_PIX_DIV_MASK 0xfff -#define CLKCTRL_PIX_DIV_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_IR_CLKGATE (1 << 31) -#define CLKCTRL_IR_AUTO_DIV (1 << 29) -#define CLKCTRL_IR_IR_BUSY (1 << 28) -#define CLKCTRL_IR_IROV_BUSY (1 << 27) -#define CLKCTRL_IR_IROV_DIV_MASK (0x1ff << 16) -#define CLKCTRL_IR_IROV_DIV_OFFSET 16 -#define CLKCTRL_IR_IR_DIV_MASK 0x3ff -#define CLKCTRL_IR_IR_DIV_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_TV_CLK_TV108M_GATE (1 << 31) -#define CLKCTRL_TV_CLK_TV_GATE (1 << 30) - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 6) -#define CLKCTRL_ETM_DIV_MASK 0x3f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_PIX 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_VID 3 - -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_IR (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_PIX (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF (1 << 0) - -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX23_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h deleted file mode 100644 index 01e0a7a..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h +++ /dev/null @@ -1,282 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 CLKCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_CLKCTRL_H__ -#define __MX28_REGS_CLKCTRL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ - uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ - mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ - uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */ - uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */ - mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ - mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ - mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ - mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ - mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ - mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ - mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ - mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ - mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ - mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ - mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ - - uint32_t reserved[16]; - - mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ - mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ - mxs_reg_32(hw_clkctrl_version) /* 0x200 */ -}; -#endif - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL0CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL0CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL0CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL0CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL0CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL0CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL0CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL0CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL0CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL0CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL0CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL0CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL1CTRL0_CLKGATEEMI (1 << 31) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL1CTRL0_LFR_SEL_DEFAULT (0x0 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_2 (0x1 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_TIMES_05 (0x2 << 28) -#define CLKCTRL_PLL1CTRL0_LFR_SEL_UNDEFINED (0x3 << 28) -#define CLKCTRL_PLL1CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL1CTRL0_CP_SEL_DEFAULT (0x0 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_2 (0x1 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_TIMES_05 (0x2 << 24) -#define CLKCTRL_PLL1CTRL0_CP_SEL_UNDEFINED (0x3 << 24) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_MASK (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_OFFSET 20 -#define CLKCTRL_PLL1CTRL0_DIV_SEL_DEFAULT (0x0 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWER (0x1 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_LOWEST (0x2 << 20) -#define CLKCTRL_PLL1CTRL0_DIV_SEL_UNDEFINED (0x3 << 20) -#define CLKCTRL_PLL1CTRL0_EN_USB_CLKS (1 << 18) -#define CLKCTRL_PLL1CTRL0_POWER (1 << 17) - -#define CLKCTRL_PLL1CTRL1_LOCK (1 << 31) -#define CLKCTRL_PLL1CTRL1_FORCE_LOCK (1 << 30) -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_MASK 0xffff -#define CLKCTRL_PLL1CTRL1_LOCK_COUNT_OFFSET 0 - -#define CLKCTRL_PLL2CTRL0_CLKGATE (1 << 31) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_MASK (0x3 << 28) -#define CLKCTRL_PLL2CTRL0_LFR_SEL_OFFSET 28 -#define CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B (1 << 26) -#define CLKCTRL_PLL2CTRL0_CP_SEL_MASK (0x3 << 24) -#define CLKCTRL_PLL2CTRL0_CP_SEL_OFFSET 24 -#define CLKCTRL_PLL2CTRL0_POWER (1 << 23) - -#define CLKCTRL_CPU_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_CPU_BUSY_REF_CPU (1 << 28) -#define CLKCTRL_CPU_DIV_XTAL_FRAC_EN (1 << 26) -#define CLKCTRL_CPU_DIV_XTAL_MASK (0x3ff << 16) -#define CLKCTRL_CPU_DIV_XTAL_OFFSET 16 -#define CLKCTRL_CPU_INTERRUPT_WAIT (1 << 12) -#define CLKCTRL_CPU_DIV_CPU_FRAC_EN (1 << 10) -#define CLKCTRL_CPU_DIV_CPU_MASK 0x3f -#define CLKCTRL_CPU_DIV_CPU_OFFSET 0 - -#define CLKCTRL_HBUS_ASM_BUSY (1 << 31) -#define CLKCTRL_HBUS_DCP_AS_ENABLE (1 << 30) -#define CLKCTRL_HBUS_PXP_AS_ENABLE (1 << 29) -#define CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE (1 << 27) -#define CLKCTRL_HBUS_APBHDMA_AS_ENABLE (1 << 26) -#define CLKCTRL_HBUS_APBXDMA_AS_ENABLE (1 << 25) -#define CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE (1 << 24) -#define CLKCTRL_HBUS_TRAFFIC_AS_ENABLE (1 << 23) -#define CLKCTRL_HBUS_CPU_DATA_AS_ENABLE (1 << 22) -#define CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE (1 << 21) -#define CLKCTRL_HBUS_ASM_ENABLE (1 << 20) -#define CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE (1 << 19) -#define CLKCTRL_HBUS_SLOW_DIV_MASK (0x7 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_OFFSET 16 -#define CLKCTRL_HBUS_SLOW_DIV_BY1 (0x0 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY2 (0x1 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY4 (0x2 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY8 (0x3 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY16 (0x4 << 16) -#define CLKCTRL_HBUS_SLOW_DIV_BY32 (0x5 << 16) -#define CLKCTRL_HBUS_DIV_FRAC_EN (1 << 5) -#define CLKCTRL_HBUS_DIV_MASK 0x1f -#define CLKCTRL_HBUS_DIV_OFFSET 0 - -#define CLKCTRL_XBUS_BUSY (1 << 31) -#define CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE (1 << 11) -#define CLKCTRL_XBUS_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_XBUS_DIV_MASK 0x3ff -#define CLKCTRL_XBUS_DIV_OFFSET 0 - -#define CLKCTRL_XTAL_UART_CLK_GATE (1 << 31) -#define CLKCTRL_XTAL_PWM_CLK24M_GATE (1 << 29) -#define CLKCTRL_XTAL_TIMROT_CLK32K_GATE (1 << 26) -#define CLKCTRL_XTAL_DIV_UART_MASK 0x3 -#define CLKCTRL_XTAL_DIV_UART_OFFSET 0 - -#define CLKCTRL_SSP_CLKGATE (1 << 31) -#define CLKCTRL_SSP_BUSY (1 << 29) -#define CLKCTRL_SSP_DIV_FRAC_EN (1 << 9) -#define CLKCTRL_SSP_DIV_MASK 0x1ff -#define CLKCTRL_SSP_DIV_OFFSET 0 - -#define CLKCTRL_GPMI_CLKGATE (1 << 31) -#define CLKCTRL_GPMI_BUSY (1 << 29) -#define CLKCTRL_GPMI_DIV_FRAC_EN (1 << 10) -#define CLKCTRL_GPMI_DIV_MASK 0x3ff -#define CLKCTRL_GPMI_DIV_OFFSET 0 - -#define CLKCTRL_SPDIF_CLKGATE (1 << 31) - -#define CLKCTRL_EMI_CLKGATE (1 << 31) -#define CLKCTRL_EMI_SYNC_MODE_EN (1 << 30) -#define CLKCTRL_EMI_BUSY_REF_XTAL (1 << 29) -#define CLKCTRL_EMI_BUSY_REF_EMI (1 << 28) -#define CLKCTRL_EMI_BUSY_REF_CPU (1 << 27) -#define CLKCTRL_EMI_BUSY_SYNC_MODE (1 << 26) -#define CLKCTRL_EMI_BUSY_DCC_RESYNC (1 << 17) -#define CLKCTRL_EMI_DCC_RESYNC_ENABLE (1 << 16) -#define CLKCTRL_EMI_DIV_XTAL_MASK (0xf << 8) -#define CLKCTRL_EMI_DIV_XTAL_OFFSET 8 -#define CLKCTRL_EMI_DIV_EMI_MASK 0x3f -#define CLKCTRL_EMI_DIV_EMI_OFFSET 0 - -#define CLKCTRL_SAIF0_CLKGATE (1 << 31) -#define CLKCTRL_SAIF0_BUSY (1 << 29) -#define CLKCTRL_SAIF0_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF0_DIV_MASK 0xffff -#define CLKCTRL_SAIF0_DIV_OFFSET 0 - -#define CLKCTRL_SAIF1_CLKGATE (1 << 31) -#define CLKCTRL_SAIF1_BUSY (1 << 29) -#define CLKCTRL_SAIF1_DIV_FRAC_EN (1 << 16) -#define CLKCTRL_SAIF1_DIV_MASK 0xffff -#define CLKCTRL_SAIF1_DIV_OFFSET 0 - -#define CLKCTRL_DIS_LCDIF_CLKGATE (1 << 31) -#define CLKCTRL_DIS_LCDIF_BUSY (1 << 29) -#define CLKCTRL_DIS_LCDIF_DIV_FRAC_EN (1 << 13) -#define CLKCTRL_DIS_LCDIF_DIV_MASK 0x1fff -#define CLKCTRL_DIS_LCDIF_DIV_OFFSET 0 - -#define CLKCTRL_ETM_CLKGATE (1 << 31) -#define CLKCTRL_ETM_BUSY (1 << 29) -#define CLKCTRL_ETM_DIV_FRAC_EN (1 << 7) -#define CLKCTRL_ETM_DIV_MASK 0x7f -#define CLKCTRL_ETM_DIV_OFFSET 0 - -#define CLKCTRL_ENET_SLEEP (1 << 31) -#define CLKCTRL_ENET_DISABLE (1 << 30) -#define CLKCTRL_ENET_STATUS (1 << 29) -#define CLKCTRL_ENET_BUSY_TIME (1 << 27) -#define CLKCTRL_ENET_DIV_TIME_MASK (0x3f << 21) -#define CLKCTRL_ENET_DIV_TIME_OFFSET 21 -#define CLKCTRL_ENET_TIME_SEL_MASK (0x3 << 19) -#define CLKCTRL_ENET_TIME_SEL_OFFSET 19 -#define CLKCTRL_ENET_TIME_SEL_XTAL (0x0 << 19) -#define CLKCTRL_ENET_TIME_SEL_PLL (0x1 << 19) -#define CLKCTRL_ENET_TIME_SEL_RMII_CLK (0x2 << 19) -#define CLKCTRL_ENET_TIME_SEL_UNDEFINED (0x3 << 19) -#define CLKCTRL_ENET_CLK_OUT_EN (1 << 18) -#define CLKCTRL_ENET_RESET_BY_SW_CHIP (1 << 17) -#define CLKCTRL_ENET_RESET_BY_SW (1 << 16) - -#define CLKCTRL_HSADC_RESETB (1 << 30) -#define CLKCTRL_HSADC_FREQDIV_MASK (0x3 << 28) -#define CLKCTRL_HSADC_FREQDIV_OFFSET 28 - -#define CLKCTRL_FLEXCAN_STOP_CAN0 (1 << 30) -#define CLKCTRL_FLEXCAN_CAN0_STATUS (1 << 29) -#define CLKCTRL_FLEXCAN_STOP_CAN1 (1 << 28) -#define CLKCTRL_FLEXCAN_CAN1_STATUS (1 << 27) - -#define CLKCTRL_FRAC_CLKGATE (1 << 7) -#define CLKCTRL_FRAC_STABLE (1 << 6) -#define CLKCTRL_FRAC_FRAC_MASK 0x3f -#define CLKCTRL_FRAC_FRAC_OFFSET 0 -#define CLKCTRL_FRAC0_CPU 0 -#define CLKCTRL_FRAC0_EMI 1 -#define CLKCTRL_FRAC0_IO1 2 -#define CLKCTRL_FRAC0_IO0 3 -#define CLKCTRL_FRAC1_PIX 0 -#define CLKCTRL_FRAC1_HSADC 1 -#define CLKCTRL_FRAC1_GPMI 2 - -#define CLKCTRL_CLKSEQ_BYPASS_CPU (1 << 18) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF (1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_BYPASS (0x1 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF_PFD (0x0 << 14) -#define CLKCTRL_CLKSEQ_BYPASS_ETM (1 << 8) -#define CLKCTRL_CLKSEQ_BYPASS_EMI (1 << 7) -#define CLKCTRL_CLKSEQ_BYPASS_SSP3 (1 << 6) -#define CLKCTRL_CLKSEQ_BYPASS_SSP2 (1 << 5) -#define CLKCTRL_CLKSEQ_BYPASS_SSP1 (1 << 4) -#define CLKCTRL_CLKSEQ_BYPASS_SSP0 (1 << 3) -#define CLKCTRL_CLKSEQ_BYPASS_GPMI (1 << 2) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF1 (1 << 1) -#define CLKCTRL_CLKSEQ_BYPASS_SAIF0 (1 << 0) - -#define CLKCTRL_RESET_WDOG_POR_DISABLE (1 << 5) -#define CLKCTRL_RESET_EXTERNAL_RESET_ENABLE (1 << 4) -#define CLKCTRL_RESET_THERMAL_RESET_ENABLE (1 << 3) -#define CLKCTRL_RESET_THERMAL_RESET_DEFAULT (1 << 2) -#define CLKCTRL_RESET_CHIP (1 << 1) -#define CLKCTRL_RESET_DIG (1 << 0) - -#define CLKCTRL_STATUS_CPU_LIMIT_MASK (0x3 << 30) -#define CLKCTRL_STATUS_CPU_LIMIT_OFFSET 30 - -#define CLKCTRL_VERSION_MAJOR_MASK (0xff << 24) -#define CLKCTRL_VERSION_MAJOR_OFFSET 24 -#define CLKCTRL_VERSION_MINOR_MASK (0xff << 16) -#define CLKCTRL_VERSION_MINOR_OFFSET 16 -#define CLKCTRL_VERSION_STEP_MASK 0xffff -#define CLKCTRL_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_CLKCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h deleted file mode 100644 index 219f58b..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-digctl.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 DIGCTL Register Definitions - * - * Copyright (C) 2012 Robert Delien <robert@delien.nl> - */ - -#ifndef __MX28_REGS_DIGCTL_H__ -#define __MX28_REGS_DIGCTL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_digctl_regs { - mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ - mxs_reg_32(hw_digctl_status) /* 0x010 */ - mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ - mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ - mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ - mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ - uint32_t hw_digctl_writeonce; /* 0x060 */ - uint32_t reserved_writeonce[3]; - mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ - mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ - uint32_t hw_digctl_entropy; /* 0x090 */ - uint32_t reserved_entropy[3]; - uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ - uint32_t reserved_entropy_latched[3]; - - uint32_t reserved1[4]; - - mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ - uint32_t hw_digctl_dbgrd; /* 0x0d0 */ - uint32_t reserved_hw_digctl_dbgrd[3]; - uint32_t hw_digctl_dbg; /* 0x0e0 */ - uint32_t reserved_hw_digctl_dbg[3]; - - uint32_t reserved2[4]; - - mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ - mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ - mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ - mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ - mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ - mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ - mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ - mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ - mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ - mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ - mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ - mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ - mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ - mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ - mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ - - uint32_t reserved3[36]; - - uint32_t hw_digctl_scratch0; /* 0x280 */ - uint32_t reserved_hw_digctl_scratch0[3]; - uint32_t hw_digctl_scratch1; /* 0x290 */ - uint32_t reserved_hw_digctl_scratch1[3]; - uint32_t hw_digctl_armcache; /* 0x2a0 */ - uint32_t reserved_hw_digctl_armcache[3]; - mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ - uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ - uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; - uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ - uint32_t reserved_hw_digctl_debug_trap_l0_addr_high[3]; - uint32_t hw_digctl_debug_trap_l3_addr_low; /* 0x2e0 */ - uint32_t reserved_hw_digctl_debug_trap_l3_addr_low[3]; - uint32_t hw_digctl_debug_trap_l3_addr_high; /* 0x2f0 */ - uint32_t reserved_hw_digctl_debug_trap_l3_addr_high[3]; - uint32_t hw_digctl_fsl; /* 0x300 */ - uint32_t reserved_hw_digctl_fsl[3]; - uint32_t hw_digctl_chipid; /* 0x310 */ - uint32_t reserved_hw_digctl_chipid[3]; - - uint32_t reserved4[4]; - - uint32_t hw_digctl_ahb_stats_select; /* 0x330 */ - uint32_t reserved_hw_digctl_ahb_stats_select[3]; - - uint32_t reserved5[12]; - - uint32_t hw_digctl_l1_ahb_active_cycles; /* 0x370 */ - uint32_t reserved_hw_digctl_l1_ahb_active_cycles[3]; - uint32_t hw_digctl_l1_ahb_data_stalled; /* 0x380 */ - uint32_t reserved_hw_digctl_l1_ahb_data_stalled[3]; - uint32_t hw_digctl_l1_ahb_data_cycles; /* 0x390 */ - uint32_t reserved_hw_digctl_l1_ahb_data_cycles[3]; - uint32_t hw_digctl_l2_ahb_active_cycles; /* 0x3a0 */ - uint32_t reserved_hw_digctl_l2_ahb_active_cycles[3]; - uint32_t hw_digctl_l2_ahb_data_stalled; /* 0x3b0 */ - uint32_t reserved_hw_digctl_l2_ahb_data_stalled[3]; - uint32_t hw_digctl_l2_ahb_data_cycles; /* 0x3c0 */ - uint32_t reserved_hw_digctl_l2_ahb_data_cycles[3]; - uint32_t hw_digctl_l3_ahb_active_cycles; /* 0x3d0 */ - uint32_t reserved_hw_digctl_l3_ahb_active_cycles[3]; - uint32_t hw_digctl_l3_ahb_data_stalled; /* 0x3e0 */ - uint32_t reserved_hw_digctl_l3_ahb_data_stalled[3]; - uint32_t hw_digctl_l3_ahb_data_cycles; /* 0x3f0 */ - uint32_t reserved_hw_digctl_l3_ahb_data_cycles[3]; - - uint32_t reserved6[64]; - - uint32_t hw_digctl_mpte0_loc; /* 0x500 */ - uint32_t reserved_hw_digctl_mpte0_loc[3]; - uint32_t hw_digctl_mpte1_loc; /* 0x510 */ - uint32_t reserved_hw_digctl_mpte1_loc[3]; - uint32_t hw_digctl_mpte2_loc; /* 0x520 */ - uint32_t reserved_hw_digctl_mpte2_loc[3]; - uint32_t hw_digctl_mpte3_loc; /* 0x530 */ - uint32_t reserved_hw_digctl_mpte3_loc[3]; - uint32_t hw_digctl_mpte4_loc; /* 0x540 */ - uint32_t reserved_hw_digctl_mpte4_loc[3]; - uint32_t hw_digctl_mpte5_loc; /* 0x550 */ - uint32_t reserved_hw_digctl_mpte5_loc[3]; - uint32_t hw_digctl_mpte6_loc; /* 0x560 */ - uint32_t reserved_hw_digctl_mpte6_loc[3]; - uint32_t hw_digctl_mpte7_loc; /* 0x570 */ - uint32_t reserved_hw_digctl_mpte7_loc[3]; - uint32_t hw_digctl_mpte8_loc; /* 0x580 */ - uint32_t reserved_hw_digctl_mpte8_loc[3]; - uint32_t hw_digctl_mpte9_loc; /* 0x590 */ - uint32_t reserved_hw_digctl_mpte9_loc[3]; - uint32_t hw_digctl_mpte10_loc; /* 0x5a0 */ - uint32_t reserved_hw_digctl_mpte10_loc[3]; - uint32_t hw_digctl_mpte11_loc; /* 0x5b0 */ - uint32_t reserved_hw_digctl_mpte11_loc[3]; - uint32_t hw_digctl_mpte12_loc; /* 0x5c0 */ - uint32_t reserved_hw_digctl_mpte12_loc[3]; - uint32_t hw_digctl_mpte13_loc; /* 0x5d0 */ - uint32_t reserved_hw_digctl_mpte13_loc[3]; - uint32_t hw_digctl_mpte14_loc; /* 0x5e0 */ - uint32_t reserved_hw_digctl_mpte14_loc[3]; - uint32_t hw_digctl_mpte15_loc; /* 0x5f0 */ - uint32_t reserved_hw_digctl_mpte15_loc[3]; -}; -#endif - -/* Product code identification */ -#define HW_DIGCTL_CHIPID_MASK (0xffff << 16) -#define HW_DIGCTL_CHIPID_MX23 (0x3780 << 16) -#define HW_DIGCTL_CHIPID_MX28 (0x2800 << 16) - -#endif /* __MX28_REGS_DIGCTL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h deleted file mode 100644 index 4cc2e0b..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-i2c.h +++ /dev/null @@ -1,193 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 I2C Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __MX28_REGS_I2C_H__ -#define __MX28_REGS_I2C_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_i2c_regs { - mxs_reg_32(hw_i2c_ctrl0) - mxs_reg_32(hw_i2c_timing0) - mxs_reg_32(hw_i2c_timing1) - mxs_reg_32(hw_i2c_timing2) - mxs_reg_32(hw_i2c_ctrl1) - mxs_reg_32(hw_i2c_stat) - mxs_reg_32(hw_i2c_queuectrl) - mxs_reg_32(hw_i2c_queuestat) - mxs_reg_32(hw_i2c_queuecmd) - mxs_reg_32(hw_i2c_queuedata) - mxs_reg_32(hw_i2c_data) - mxs_reg_32(hw_i2c_debug0) - mxs_reg_32(hw_i2c_debug1) - mxs_reg_32(hw_i2c_version) -}; -#endif - -#define I2C_CTRL_SFTRST (1 << 31) -#define I2C_CTRL_CLKGATE (1 << 30) -#define I2C_CTRL_RUN (1 << 29) -#define I2C_CTRL_PREACK (1 << 27) -#define I2C_CTRL_ACKNOWLEDGE (1 << 26) -#define I2C_CTRL_SEND_NAK_ON_LAST (1 << 25) -#define I2C_CTRL_MULTI_MASTER (1 << 23) -#define I2C_CTRL_CLOCK_HELD (1 << 22) -#define I2C_CTRL_RETAIN_CLOCK (1 << 21) -#define I2C_CTRL_POST_SEND_STOP (1 << 20) -#define I2C_CTRL_PRE_SEND_START (1 << 19) -#define I2C_CTRL_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_CTRL_MASTER_MODE (1 << 17) -#define I2C_CTRL_DIRECTION (1 << 16) -#define I2C_CTRL_XFER_COUNT_MASK 0xffff -#define I2C_CTRL_XFER_COUNT_OFFSET 0 - -#define I2C_TIMING0_HIGH_COUNT_MASK (0x3ff << 16) -#define I2C_TIMING0_HIGH_COUNT_OFFSET 16 -#define I2C_TIMING0_RCV_COUNT_MASK 0x3ff -#define I2C_TIMING0_RCV_COUNT_OFFSET 0 - -#define I2C_TIMING1_LOW_COUNT_MASK (0x3ff << 16) -#define I2C_TIMING1_LOW_COUNT_OFFSET 16 -#define I2C_TIMING1_XMIT_COUNT_MASK 0x3ff -#define I2C_TIMING1_XMIT_COUNT_OFFSET 0 - -#define I2C_TIMING2_BUS_FREE_MASK (0x3ff << 16) -#define I2C_TIMING2_BUS_FREE_OFFSET 16 -#define I2C_TIMING2_LEADIN_COUNT_MASK 0x3ff -#define I2C_TIMING2_LEADIN_COUNT_OFFSET 0 - -#define I2C_CTRL1_RD_QUEUE_IRQ (1 << 30) -#define I2C_CTRL1_WR_QUEUE_IRQ (1 << 29) -#define I2C_CTRL1_CLR_GOT_A_NAK (1 << 28) -#define I2C_CTRL1_ACK_MODE (1 << 27) -#define I2C_CTRL1_FORCE_DATA_IDLE (1 << 26) -#define I2C_CTRL1_FORCE_CLK_IDLE (1 << 25) -#define I2C_CTRL1_BCAST_SLAVE_EN (1 << 24) -#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_MASK (0xff << 16) -#define I2C_CTRL1_SLAVE_ADDRESS_BYTE_OFFSET 16 -#define I2C_CTRL1_BUS_FREE_IRQ_EN (1 << 15) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN (1 << 14) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN (1 << 13) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN (1 << 12) -#define I2C_CTRL1_EARLY_TERM_IRQ_EN (1 << 11) -#define I2C_CTRL1_MASTER_LOSS_IRQ_EN (1 << 10) -#define I2C_CTRL1_SLAVE_STOP_IRQ_EN (1 << 9) -#define I2C_CTRL1_SLAVE_IRQ_EN (1 << 8) -#define I2C_CTRL1_BUS_FREE_IRQ (1 << 7) -#define I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ (1 << 6) -#define I2C_CTRL1_NO_SLAVE_ACK_IRQ (1 << 5) -#define I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ (1 << 4) -#define I2C_CTRL1_EARLY_TERM_IRQ (1 << 3) -#define I2C_CTRL1_MASTER_LOSS_IRQ (1 << 2) -#define I2C_CTRL1_SLAVE_STOP_IRQ (1 << 1) -#define I2C_CTRL1_SLAVE_IRQ (1 << 0) - -#define I2C_STAT_MASTER_PRESENT (1 << 31) -#define I2C_STAT_SLAVE_PRESENT (1 << 30) -#define I2C_STAT_ANY_ENABLED_IRQ (1 << 29) -#define I2C_STAT_GOT_A_NAK (1 << 28) -#define I2C_STAT_RCVD_SLAVE_ADDR_MASK (0xff << 16) -#define I2C_STAT_RCVD_SLAVE_ADDR_OFFSET 16 -#define I2C_STAT_SLAVE_ADDR_EQ_ZERO (1 << 15) -#define I2C_STAT_SLAVE_FOUND (1 << 14) -#define I2C_STAT_SLAVE_SEARCHING (1 << 13) -#define I2C_STAT_DATA_ENGING_DMA_WAIT (1 << 12) -#define I2C_STAT_BUS_BUSY (1 << 11) -#define I2C_STAT_CLK_GEN_BUSY (1 << 10) -#define I2C_STAT_DATA_ENGINE_BUSY (1 << 9) -#define I2C_STAT_SLAVE_BUSY (1 << 8) -#define I2C_STAT_BUS_FREE_IRQ_SUMMARY (1 << 7) -#define I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY (1 << 6) -#define I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY (1 << 5) -#define I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY (1 << 4) -#define I2C_STAT_EARLY_TERM_IRQ_SUMMARY (1 << 3) -#define I2C_STAT_MASTER_LOSS_IRQ_SUMMARY (1 << 2) -#define I2C_STAT_SLAVE_STOP_IRQ_SUMMARY (1 << 1) -#define I2C_STAT_SLAVE_IRQ_SUMMARY (1 << 0) - -#define I2C_QUEUECTRL_RD_THRESH_MASK (0x1f << 16) -#define I2C_QUEUECTRL_RD_THRESH_OFFSET 16 -#define I2C_QUEUECTRL_WR_THRESH_MASK (0x1f << 8) -#define I2C_QUEUECTRL_WR_THRESH_OFFSET 8 -#define I2C_QUEUECTRL_QUEUE_RUN (1 << 5) -#define I2C_QUEUECTRL_RD_CLEAR (1 << 4) -#define I2C_QUEUECTRL_WR_CLEAR (1 << 3) -#define I2C_QUEUECTRL_PIO_QUEUE_MODE (1 << 2) -#define I2C_QUEUECTRL_RD_QUEUE_IRQ_EN (1 << 1) -#define I2C_QUEUECTRL_WR_QUEUE_IRQ_EN (1 << 0) - -#define I2C_QUEUESTAT_RD_QUEUE_FULL (1 << 14) -#define I2C_QUEUESTAT_RD_QUEUE_EMPTY (1 << 13) -#define I2C_QUEUESTAT_RD_QUEUE_CNT_MASK (0x1f << 8) -#define I2C_QUEUESTAT_RD_QUEUE_CNT_OFFSET 8 -#define I2C_QUEUESTAT_WR_QUEUE_FULL (1 << 6) -#define I2C_QUEUESTAT_WR_QUEUE_EMPTY (1 << 5) -#define I2C_QUEUESTAT_WR_QUEUE_CNT_MASK 0x1f -#define I2C_QUEUESTAT_WR_QUEUE_CNT_OFFSET 0 - -#define I2C_QUEUECMD_PREACK (1 << 27) -#define I2C_QUEUECMD_ACKNOWLEDGE (1 << 26) -#define I2C_QUEUECMD_SEND_NAK_ON_LAST (1 << 25) -#define I2C_QUEUECMD_MULTI_MASTER (1 << 23) -#define I2C_QUEUECMD_CLOCK_HELD (1 << 22) -#define I2C_QUEUECMD_RETAIN_CLOCK (1 << 21) -#define I2C_QUEUECMD_POST_SEND_STOP (1 << 20) -#define I2C_QUEUECMD_PRE_SEND_START (1 << 19) -#define I2C_QUEUECMD_SLAVE_ADDRESS_ENABLE (1 << 18) -#define I2C_QUEUECMD_MASTER_MODE (1 << 17) -#define I2C_QUEUECMD_DIRECTION (1 << 16) -#define I2C_QUEUECMD_XFER_COUNT_MASK 0xffff -#define I2C_QUEUECMD_XFER_COUNT_OFFSET 0 - -#define I2C_QUEUEDATA_DATA_MASK 0xffffffff -#define I2C_QUEUEDATA_DATA_OFFSET 0 - -#define I2C_DATA_DATA_MASK 0xffffffff -#define I2C_DATA_DATA_OFFSET 0 - -#define I2C_DEBUG0_DMAREQ (1 << 31) -#define I2C_DEBUG0_DMAENDCMD (1 << 30) -#define I2C_DEBUG0_DMAKICK (1 << 29) -#define I2C_DEBUG0_DMATERMINATE (1 << 28) -#define I2C_DEBUG0_STATE_VALUE_MASK (0x3 << 26) -#define I2C_DEBUG0_STATE_VALUE_OFFSET 26 -#define I2C_DEBUG0_DMA_STATE_MASK (0x3ff << 16) -#define I2C_DEBUG0_DMA_STATE_OFFSET 16 -#define I2C_DEBUG0_START_TOGGLE (1 << 15) -#define I2C_DEBUG0_STOP_TOGGLE (1 << 14) -#define I2C_DEBUG0_GRAB_TOGGLE (1 << 13) -#define I2C_DEBUG0_CHANGE_TOGGLE (1 << 12) -#define I2C_DEBUG0_STATE_LATCH (1 << 11) -#define I2C_DEBUG0_SLAVE_HOLD_CLK (1 << 10) -#define I2C_DEBUG0_STATE_STATE_MASK 0x3ff -#define I2C_DEBUG0_STATE_STATE_OFFSET 0 - -#define I2C_DEBUG1_I2C_CLK_IN (1 << 31) -#define I2C_DEBUG1_I2C_DATA_IN (1 << 30) -#define I2C_DEBUG1_DMA_BYTE_ENABLES_MASK (0xf << 24) -#define I2C_DEBUG1_DMA_BYTE_ENABLES_OFFSET 24 -#define I2C_DEBUG1_CLK_GEN_STATE_MASK (0xff << 16) -#define I2C_DEBUG1_CLK_GEN_STATE_OFFSET 16 -#define I2C_DEBUG1_LST_MODE_MASK (0x3 << 9) -#define I2C_DEBUG1_LST_MODE_OFFSET 9 -#define I2C_DEBUG1_LOCAL_SLAVE_TEST (1 << 8) -#define I2C_DEBUG1_FORCE_CLK_ON (1 << 4) -#define I2C_DEBUG1_FORCE_ABR_LOSS (1 << 3) -#define I2C_DEBUG1_FORCE_RCV_ACK (1 << 2) -#define I2C_DEBUG1_FORCE_I2C_DATA_OE (1 << 1) -#define I2C_DEBUG1_FORCE_I2C_CLK_OE (1 << 0) - -#define I2C_VERSION_MAJOR_MASK (0xff << 24) -#define I2C_VERSION_MAJOR_OFFSET 24 -#define I2C_VERSION_MINOR_MASK (0xff << 16) -#define I2C_VERSION_MINOR_OFFSET 16 -#define I2C_VERSION_STEP_MASK 0xffff -#define I2C_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_I2C_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-lradc.h b/arch/arm/include/asm/arch-mxs/regs-lradc.h deleted file mode 100644 index a48f7a4..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-lradc.h +++ /dev/null @@ -1,386 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 LRADC Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_LRADC_H__ -#define __MX28_REGS_LRADC_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_lradc_regs { - mxs_reg_32(hw_lradc_ctrl0); - mxs_reg_32(hw_lradc_ctrl1); - mxs_reg_32(hw_lradc_ctrl2); - mxs_reg_32(hw_lradc_ctrl3); - mxs_reg_32(hw_lradc_status); - mxs_reg_32(hw_lradc_ch0); - mxs_reg_32(hw_lradc_ch1); - mxs_reg_32(hw_lradc_ch2); - mxs_reg_32(hw_lradc_ch3); - mxs_reg_32(hw_lradc_ch4); - mxs_reg_32(hw_lradc_ch5); - mxs_reg_32(hw_lradc_ch6); - mxs_reg_32(hw_lradc_ch7); - mxs_reg_32(hw_lradc_delay0); - mxs_reg_32(hw_lradc_delay1); - mxs_reg_32(hw_lradc_delay2); - mxs_reg_32(hw_lradc_delay3); - mxs_reg_32(hw_lradc_debug0); - mxs_reg_32(hw_lradc_debug1); - mxs_reg_32(hw_lradc_conversion); - mxs_reg_32(hw_lradc_ctrl4); - mxs_reg_32(hw_lradc_treshold0); - mxs_reg_32(hw_lradc_treshold1); - mxs_reg_32(hw_lradc_version); -}; -#endif - -#define LRADC_CTRL0_SFTRST (1 << 31) -#define LRADC_CTRL0_CLKGATE (1 << 30) -#define LRADC_CTRL0_ONCHIP_GROUNDREF (1 << 26) -#define LRADC_CTRL0_BUTTON1_DETECT_ENABLE (1 << 25) -#define LRADC_CTRL0_BUTTON0_DETECT_ENABLE (1 << 24) -#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23) -#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22) -#define LRADC_CTRL0_YNLRSW (1 << 21) -#define LRADC_CTRL0_YPLLSW_MASK (0x3 << 19) -#define LRADC_CTRL0_YPLLSW_OFFSET 19 -#define LRADC_CTRL0_XNURSW_MASK (0x3 << 17) -#define LRADC_CTRL0_XNURSW_OFFSET 17 -#define LRADC_CTRL0_XPULSW (1 << 16) -#define LRADC_CTRL0_SCHEDULE_MASK 0xff -#define LRADC_CTRL0_SCHEDULE_OFFSET 0 - -#define LRADC_CTRL1_BUTTON1_DETECT_IRQ_EN (1 << 28) -#define LRADC_CTRL1_BUTTON0_DETECT_IRQ_EN (1 << 27) -#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ_EN (1 << 26) -#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ_EN (1 << 25) -#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) -#define LRADC_CTRL1_LRADC7_IRQ_EN (1 << 23) -#define LRADC_CTRL1_LRADC6_IRQ_EN (1 << 22) -#define LRADC_CTRL1_LRADC5_IRQ_EN (1 << 21) -#define LRADC_CTRL1_LRADC4_IRQ_EN (1 << 20) -#define LRADC_CTRL1_LRADC3_IRQ_EN (1 << 19) -#define LRADC_CTRL1_LRADC2_IRQ_EN (1 << 18) -#define LRADC_CTRL1_LRADC1_IRQ_EN (1 << 17) -#define LRADC_CTRL1_LRADC0_IRQ_EN (1 << 16) -#define LRADC_CTRL1_BUTTON1_DETECT_IRQ (1 << 12) -#define LRADC_CTRL1_BUTTON0_DETECT_IRQ (1 << 11) -#define LRADC_CTRL1_THRESHOLD1_DETECT_IRQ (1 << 10) -#define LRADC_CTRL1_THRESHOLD0_DETECT_IRQ (1 << 9) -#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) -#define LRADC_CTRL1_LRADC7_IRQ (1 << 7) -#define LRADC_CTRL1_LRADC6_IRQ (1 << 6) -#define LRADC_CTRL1_LRADC5_IRQ (1 << 5) -#define LRADC_CTRL1_LRADC4_IRQ (1 << 4) -#define LRADC_CTRL1_LRADC3_IRQ (1 << 3) -#define LRADC_CTRL1_LRADC2_IRQ (1 << 2) -#define LRADC_CTRL1_LRADC1_IRQ (1 << 1) -#define LRADC_CTRL1_LRADC0_IRQ (1 << 0) - -#define LRADC_CTRL2_DIVIDE_BY_TWO_MASK (0xff << 24) -#define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 -#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) -#define LRADC_CTRL2_VTHSENSE_MASK (0x3 << 13) -#define LRADC_CTRL2_VTHSENSE_OFFSET 13 -#define LRADC_CTRL2_DISABLE_MUXAMP_BYPASS (1 << 12) -#define LRADC_CTRL2_TEMP_SENSOR_IENABLE1 (1 << 9) -#define LRADC_CTRL2_TEMP_SENSOR_IENABLE0 (1 << 8) -#define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4) -#define LRADC_CTRL2_TEMP_ISRC1_OFFSET 4 -#define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4) -#define LRADC_CTRL2_TEMP_ISRC1_280 (0xe << 4) -#define LRADC_CTRL2_TEMP_ISRC1_260 (0xd << 4) -#define LRADC_CTRL2_TEMP_ISRC1_240 (0xc << 4) -#define LRADC_CTRL2_TEMP_ISRC1_220 (0xb << 4) -#define LRADC_CTRL2_TEMP_ISRC1_200 (0xa << 4) -#define LRADC_CTRL2_TEMP_ISRC1_180 (0x9 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_160 (0x8 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_140 (0x7 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_120 (0x6 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_100 (0x5 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_80 (0x4 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_60 (0x3 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_40 (0x2 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_20 (0x1 << 4) -#define LRADC_CTRL2_TEMP_ISRC1_ZERO (0x0 << 4) -#define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0) -#define LRADC_CTRL2_TEMP_ISRC0_OFFSET 0 -#define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0) -#define LRADC_CTRL2_TEMP_ISRC0_280 (0xe << 0) -#define LRADC_CTRL2_TEMP_ISRC0_260 (0xd << 0) -#define LRADC_CTRL2_TEMP_ISRC0_240 (0xc << 0) -#define LRADC_CTRL2_TEMP_ISRC0_220 (0xb << 0) -#define LRADC_CTRL2_TEMP_ISRC0_200 (0xa << 0) -#define LRADC_CTRL2_TEMP_ISRC0_180 (0x9 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_160 (0x8 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_140 (0x7 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_120 (0x6 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_100 (0x5 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_80 (0x4 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_60 (0x3 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_40 (0x2 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_20 (0x1 << 0) -#define LRADC_CTRL2_TEMP_ISRC0_ZERO (0x0 << 0) - -#define LRADC_CTRL3_DISCARD_MASK (0x3 << 24) -#define LRADC_CTRL3_DISCARD_OFFSET 24 -#define LRADC_CTRL3_DISCARD_1_SAMPLE (0x1 << 24) -#define LRADC_CTRL3_DISCARD_2_SAMPLES (0x2 << 24) -#define LRADC_CTRL3_DISCARD_3_SAMPLES (0x3 << 24) -#define LRADC_CTRL3_FORCE_ANALOG_PWUP (1 << 23) -#define LRADC_CTRL3_FORCE_ANALOG_PWDN (1 << 22) -#define LRADC_CTRL3_CYCLE_TIME_MASK (0x3 << 8) -#define LRADC_CTRL3_CYCLE_TIME_OFFSET 8 -#define LRADC_CTRL3_CYCLE_TIME_6MHZ (0x0 << 8) -#define LRADC_CTRL3_CYCLE_TIME_4MHZ (0x1 << 8) -#define LRADC_CTRL3_CYCLE_TIME_3MHZ (0x2 << 8) -#define LRADC_CTRL3_CYCLE_TIME_2MHZ (0x3 << 8) -#define LRADC_CTRL3_HIGH_TIME_MASK (0x3 << 4) -#define LRADC_CTRL3_HIGH_TIME_OFFSET 4 -#define LRADC_CTRL3_HIGH_TIME_42NS (0x0 << 4) -#define LRADC_CTRL3_HIGH_TIME_83NS (0x1 << 4) -#define LRADC_CTRL3_HIGH_TIME_125NS (0x2 << 4) -#define LRADC_CTRL3_HIGH_TIME_250NS (0x3 << 4) -#define LRADC_CTRL3_DELAY_CLOCK (1 << 1) -#define LRADC_CTRL3_INVERT_CLOCK (1 << 0) - -#define LRADC_STATUS_BUTTON1_PRESENT (1 << 28) -#define LRADC_STATUS_BUTTON0_PRESENT (1 << 27) -#define LRADC_STATUS_TEMP1_PRESENT (1 << 26) -#define LRADC_STATUS_TEMP0_PRESENT (1 << 25) -#define LRADC_STATUS_TOUCH_PANEL_PRESENT (1 << 24) -#define LRADC_STATUS_CHANNEL7_PRESENT (1 << 23) -#define LRADC_STATUS_CHANNEL6_PRESENT (1 << 22) -#define LRADC_STATUS_CHANNEL5_PRESENT (1 << 21) -#define LRADC_STATUS_CHANNEL4_PRESENT (1 << 20) -#define LRADC_STATUS_CHANNEL3_PRESENT (1 << 19) -#define LRADC_STATUS_CHANNEL2_PRESENT (1 << 18) -#define LRADC_STATUS_CHANNEL1_PRESENT (1 << 17) -#define LRADC_STATUS_CHANNEL0_PRESENT (1 << 16) -#define LRADC_STATUS_BUTTON1_DETECT_RAW (1 << 2) -#define LRADC_STATUS_BUTTON0_DETECT_RAW (1 << 1) -#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) - -#define LRADC_CH_TOGGLE (1 << 31) -#define LRADC_CH7_TESTMODE_TOGGLE (1 << 30) -#define LRADC_CH_ACCUMULATE (1 << 29) -#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) -#define LRADC_CH_NUM_SAMPLES_OFFSET 24 -#define LRADC_CH_VALUE_MASK 0x3ffff -#define LRADC_CH_VALUE_OFFSET 0 - -#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) -#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 -#define LRADC_DELAY_KICK (1 << 20) -#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) -#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 -#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) -#define LRADC_DELAY_LOOP_COUNT_OFFSET 11 -#define LRADC_DELAY_DELAY_MASK 0x7ff -#define LRADC_DELAY_DELAY_OFFSET 0 - -#define LRADC_DEBUG0_READONLY_MASK (0xffff << 16) -#define LRADC_DEBUG0_READONLY_OFFSET 16 -#define LRADC_DEBUG0_STATE_MASK (0xfff << 0) -#define LRADC_DEBUG0_STATE_OFFSET 0 - -#define LRADC_DEBUG1_REQUEST_MASK (0xff << 16) -#define LRADC_DEBUG1_REQUEST_OFFSET 16 -#define LRADC_DEBUG1_TESTMODE_COUNT_MASK (0x1f << 8) -#define LRADC_DEBUG1_TESTMODE_COUNT_OFFSET 8 -#define LRADC_DEBUG1_TESTMODE6 (1 << 2) -#define LRADC_DEBUG1_TESTMODE5 (1 << 1) -#define LRADC_DEBUG1_TESTMODE (1 << 0) - -#define LRADC_CONVERSION_AUTOMATIC (1 << 20) -#define LRADC_CONVERSION_SCALE_FACTOR_MASK (0x3 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_OFFSET 16 -#define LRADC_CONVERSION_SCALE_FACTOR_NIMH (0x0 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_DUAL_NIMH (0x1 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_LI_ION (0x2 << 16) -#define LRADC_CONVERSION_SCALE_FACTOR_ALT_LI_ION (0x3 << 16) -#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x3ff -#define LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0 - -#define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28) -#define LRADC_CTRL4_LRADC7SELECT_OFFSET 28 -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL0 (0x0 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL1 (0x1 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL2 (0x2 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL3 (0x3 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL4 (0x4 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL5 (0x5 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL6 (0x6 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL7 (0x7 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL8 (0x8 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL9 (0x9 << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL10 (0xa << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL11 (0xb << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL12 (0xc << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL13 (0xd << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL14 (0xe << 28) -#define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28) -#define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24) -#define LRADC_CTRL4_LRADC6SELECT_OFFSET 24 -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL0 (0x0 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL1 (0x1 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL2 (0x2 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL3 (0x3 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL4 (0x4 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL5 (0x5 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL6 (0x6 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL7 (0x7 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL8 (0x8 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL9 (0x9 << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL10 (0xa << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL11 (0xb << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL12 (0xc << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL13 (0xd << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL14 (0xe << 24) -#define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24) -#define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20) -#define LRADC_CTRL4_LRADC5SELECT_OFFSET 20 -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL0 (0x0 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL1 (0x1 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL2 (0x2 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL3 (0x3 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL4 (0x4 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL5 (0x5 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL6 (0x6 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL7 (0x7 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL8 (0x8 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL9 (0x9 << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL10 (0xa << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL11 (0xb << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL12 (0xc << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL13 (0xd << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL14 (0xe << 20) -#define LRADC_CTRL4_LRADC5SELECT_CHANNEL15 (0xf << 20) -#define LRADC_CTRL4_LRADC4SELECT_MASK (0xf << 16) -#define LRADC_CTRL4_LRADC4SELECT_OFFSET 16 -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL0 (0x0 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL1 (0x1 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL2 (0x2 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL3 (0x3 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL4 (0x4 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL5 (0x5 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL6 (0x6 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL7 (0x7 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL8 (0x8 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL9 (0x9 << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL10 (0xa << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL11 (0xb << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL12 (0xc << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL13 (0xd << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL14 (0xe << 16) -#define LRADC_CTRL4_LRADC4SELECT_CHANNEL15 (0xf << 16) -#define LRADC_CTRL4_LRADC3SELECT_MASK (0xf << 12) -#define LRADC_CTRL4_LRADC3SELECT_OFFSET 12 -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL0 (0x0 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL1 (0x1 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL2 (0x2 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL3 (0x3 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL4 (0x4 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL5 (0x5 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL6 (0x6 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL7 (0x7 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL8 (0x8 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL9 (0x9 << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL10 (0xa << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL11 (0xb << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL12 (0xc << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL13 (0xd << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL14 (0xe << 12) -#define LRADC_CTRL4_LRADC3SELECT_CHANNEL15 (0xf << 12) -#define LRADC_CTRL4_LRADC2SELECT_MASK (0xf << 8) -#define LRADC_CTRL4_LRADC2SELECT_OFFSET 8 -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL0 (0x0 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL1 (0x1 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL2 (0x2 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL3 (0x3 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL4 (0x4 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL5 (0x5 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL6 (0x6 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL7 (0x7 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL8 (0x8 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL9 (0x9 << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL10 (0xa << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL11 (0xb << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL12 (0xc << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL13 (0xd << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL14 (0xe << 8) -#define LRADC_CTRL4_LRADC2SELECT_CHANNEL15 (0xf << 8) -#define LRADC_CTRL4_LRADC1SELECT_MASK (0xf << 4) -#define LRADC_CTRL4_LRADC1SELECT_OFFSET 4 -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL0 (0x0 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL1 (0x1 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL2 (0x2 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL3 (0x3 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL4 (0x4 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL5 (0x5 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL6 (0x6 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL7 (0x7 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL8 (0x8 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL9 (0x9 << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL10 (0xa << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL11 (0xb << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL12 (0xc << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL13 (0xd << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL14 (0xe << 4) -#define LRADC_CTRL4_LRADC1SELECT_CHANNEL15 (0xf << 4) -#define LRADC_CTRL4_LRADC0SELECT_MASK 0xf -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL0 (0x0 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL1 (0x1 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL2 (0x2 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL3 (0x3 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL4 (0x4 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL5 (0x5 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL6 (0x6 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL7 (0x7 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL8 (0x8 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL9 (0x9 << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL10 (0xa << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL11 (0xb << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL12 (0xc << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL13 (0xd << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL14 (0xe << 0) -#define LRADC_CTRL4_LRADC0SELECT_CHANNEL15 (0xf << 0) - -#define LRADC_THRESHOLD_ENABLE (1 << 24) -#define LRADC_THRESHOLD_BATTCHRG_DISABLE (1 << 23) -#define LRADC_THRESHOLD_CHANNEL_SEL_MASK (0x7 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_OFFSET 20 -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL0 (0x0 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL1 (0x1 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL2 (0x2 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL3 (0x3 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL4 (0x4 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL5 (0x5 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL6 (0x6 << 20) -#define LRADC_THRESHOLD_CHANNEL_SEL_CHANNEL7 (0x7 << 20) -#define LRADC_THRESHOLD_SETTING_MASK (0x3 << 18) -#define LRADC_THRESHOLD_SETTING_OFFSET 18 -#define LRADC_THRESHOLD_SETTING_NO_COMPARE (0x0 << 18) -#define LRADC_THRESHOLD_SETTING_DETECT_LOW (0x1 << 18) -#define LRADC_THRESHOLD_SETTING_DETECT_HIGH (0x2 << 18) -#define LRADC_THRESHOLD_SETTING_RESERVED (0x3 << 18) -#define LRADC_THRESHOLD_VALUE_MASK 0x3ffff -#define LRADC_THRESHOLD_VALUE_OFFSET 0 - -#define LRADC_VERSION_MAJOR_MASK (0xff << 24) -#define LRADC_VERSION_MAJOR_OFFSET 24 -#define LRADC_VERSION_MINOR_MASK (0xff << 16) -#define LRADC_VERSION_MINOR_OFFSET 16 -#define LRADC_VERSION_STEP_MASK 0xffff -#define LRADC_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_LRADC_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h deleted file mode 100644 index 8bfbd19..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-ocotp.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 OCOTP Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_OCOTP_H__ -#define __MX28_REGS_OCOTP_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_ocotp_regs { - mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ - mxs_reg_32(hw_ocotp_data) /* 0x10 */ - mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ - mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ - mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ - mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ - mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ - mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ - mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ - mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ - mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ - mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ - mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ - mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ - mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ - mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ - mxs_reg_32(hw_ocotp_swcap) /* 0x100 */ - mxs_reg_32(hw_ocotp_custcap) /* 0x110 */ - mxs_reg_32(hw_ocotp_lock) /* 0x120 */ - mxs_reg_32(hw_ocotp_ops0) /* 0x130 */ - mxs_reg_32(hw_ocotp_ops1) /* 0x140 */ - mxs_reg_32(hw_ocotp_ops2) /* 0x150 */ - mxs_reg_32(hw_ocotp_ops3) /* 0x160 */ - mxs_reg_32(hw_ocotp_un0) /* 0x170 */ - mxs_reg_32(hw_ocotp_un1) /* 0x180 */ - mxs_reg_32(hw_ocotp_un2) /* 0x190 */ - mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */ - mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */ - mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */ - mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */ - mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */ - mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */ - mxs_reg_32(hw_ocotp_rom6) /* 0x200 */ - mxs_reg_32(hw_ocotp_rom7) /* 0x210 */ - mxs_reg_32(hw_ocotp_srk0) /* 0x220 */ - mxs_reg_32(hw_ocotp_srk1) /* 0x230 */ - mxs_reg_32(hw_ocotp_srk2) /* 0x240 */ - mxs_reg_32(hw_ocotp_srk3) /* 0x250 */ - mxs_reg_32(hw_ocotp_srk4) /* 0x260 */ - mxs_reg_32(hw_ocotp_srk5) /* 0x270 */ - mxs_reg_32(hw_ocotp_srk6) /* 0x280 */ - mxs_reg_32(hw_ocotp_srk7) /* 0x290 */ - mxs_reg_32(hw_ocotp_version) /* 0x2a0 */ -}; -#endif - -#define OCOTP_CTRL_WR_UNLOCK_MASK (0xffff << 16) -#define OCOTP_CTRL_WR_UNLOCK_OFFSET 16 -#define OCOTP_CTRL_WR_UNLOCK_KEY (0x3e77 << 16) -#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 13) -#define OCOTP_CTRL_RD_BANK_OPEN (1 << 12) -#define OCOTP_CTRL_ERROR (1 << 9) -#define OCOTP_CTRL_BUSY (1 << 8) -#define OCOTP_CTRL_ADDR_MASK 0x3f -#define OCOTP_CTRL_ADDR_OFFSET 0 - -#define OCOTP_DATA_DATA_MASK 0xffffffff -#define OCOTP_DATA_DATA_OFFSET 0 - -#define OCOTP_CUST_BITS_MASK 0xffffffff -#define OCOTP_CUST_BITS_OFFSET 0 - -#define OCOTP_CRYPTO_BITS_MASK 0xffffffff -#define OCOTP_CRYPTO_BITS_OFFSET 0 - -#define OCOTP_HWCAP_BITS_MASK 0xffffffff -#define OCOTP_HWCAP_BITS_OFFSET 0 - -#define OCOTP_SWCAP_BITS_MASK 0xffffffff -#define OCOTP_SWCAP_BITS_OFFSET 0 - -#define OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT (1 << 2) -#define OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT (1 << 1) - -#define OCOTP_LOCK_ROM7 (1 << 31) -#define OCOTP_LOCK_ROM6 (1 << 30) -#define OCOTP_LOCK_ROM5 (1 << 29) -#define OCOTP_LOCK_ROM4 (1 << 28) -#define OCOTP_LOCK_ROM3 (1 << 27) -#define OCOTP_LOCK_ROM2 (1 << 26) -#define OCOTP_LOCK_ROM1 (1 << 25) -#define OCOTP_LOCK_ROM0 (1 << 24) -#define OCOTP_LOCK_HWSW_SHADOW_ALT (1 << 23) -#define OCOTP_LOCK_CRYPTODCP_ALT (1 << 22) -#define OCOTP_LOCK_CRYPTOKEY_ALT (1 << 21) -#define OCOTP_LOCK_PIN (1 << 20) -#define OCOTP_LOCK_OPS (1 << 19) -#define OCOTP_LOCK_UN2 (1 << 18) -#define OCOTP_LOCK_UN1 (1 << 17) -#define OCOTP_LOCK_UN0 (1 << 16) -#define OCOTP_LOCK_SRK (1 << 15) -#define OCOTP_LOCK_UNALLOCATED_MASK (0x7 << 12) -#define OCOTP_LOCK_UNALLOCATED_OFFSET 12 -#define OCOTP_LOCK_SRK_SHADOW (1 << 11) -#define OCOTP_LOCK_ROM_SHADOW (1 << 10) -#define OCOTP_LOCK_CUSTCAP (1 << 9) -#define OCOTP_LOCK_HWSW (1 << 8) -#define OCOTP_LOCK_CUSTCAP_SHADOW (1 << 7) -#define OCOTP_LOCK_HWSW_SHADOW (1 << 6) -#define OCOTP_LOCK_CRYPTODCP (1 << 5) -#define OCOTP_LOCK_CRYPTOKEY (1 << 4) -#define OCOTP_LOCK_CUST3 (1 << 3) -#define OCOTP_LOCK_CUST2 (1 << 2) -#define OCOTP_LOCK_CUST1 (1 << 1) -#define OCOTP_LOCK_CUST0 (1 << 0) - -#define OCOTP_OPS_BITS_MASK 0xffffffff -#define OCOTP_OPS_BITS_OFFSET 0 - -#define OCOTP_UN_BITS_MASK 0xffffffff -#define OCOTP_UN_BITS_OFFSET 0 - -#define OCOTP_ROM_BOOT_MODE_MASK (0xff << 24) -#define OCOTP_ROM_BOOT_MODE_OFFSET 24 -#define OCOTP_ROM_SD_MMC_MODE_MASK (0x3 << 22) -#define OCOTP_ROM_SD_MMC_MODE_OFFSET 22 -#define OCOTP_ROM_SD_POWER_GATE_GPIO_MASK (0x3 << 20) -#define OCOTP_ROM_SD_POWER_GATE_GPIO_OFFSET 20 -#define OCOTP_ROM_SD_POWER_UP_DELAY_MASK (0x3f << 14) -#define OCOTP_ROM_SD_POWER_UP_DELAY_OFFSET 14 -#define OCOTP_ROM_SD_BUS_WIDTH_MASK (0x3 << 12) -#define OCOTP_ROM_SD_BUS_WIDTH_OFFSET 12 -#define OCOTP_ROM_SSP_SCK_INDEX_MASK (0xf << 8) -#define OCOTP_ROM_SSP_SCK_INDEX_OFFSET 8 -#define OCOTP_ROM_EMMC_USE_DDR (1 << 7) -#define OCOTP_ROM_DISABLE_SPI_NOR_FAST_READ (1 << 6) -#define OCOTP_ROM_ENABLE_USB_BOOT_SERIAL_NUM (1 << 5) -#define OCOTP_ROM_ENABLE_UNENCRYPTED_BOOT (1 << 4) -#define OCOTP_ROM_SD_MBR_BOOT (1 << 3) - -#define OCOTP_SRK_BITS_MASK 0xffffffff -#define OCOTP_SRK_BITS_OFFSET 0 - -#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) -#define OCOTP_VERSION_MAJOR_OFFSET 24 -#define OCOTP_VERSION_MINOR_MASK (0xff << 16) -#define OCOTP_VERSION_MINOR_OFFSET 16 -#define OCOTP_VERSION_STEP_MASK 0xffff -#define OCOTP_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_OCOTP_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h deleted file mode 100644 index 134d436..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h +++ /dev/null @@ -1,1270 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 PINCTRL Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_PINCTRL_H__ -#define __MX28_REGS_PINCTRL_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_pinctrl_regs { - mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */ - - uint32_t reserved1[60]; - - mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ - mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ - mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ - mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ - mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ - mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ - mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ - mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ - mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ - mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ - mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ - mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ - mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ - mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ - - uint32_t reserved2[72]; - - mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */ - mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */ - mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */ - mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */ - mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */ - mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */ - mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */ - mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */ - mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */ - mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */ - mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ - mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ - mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ - mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ - mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ - mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ - mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */ - mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */ - mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */ - mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */ - - uint32_t reserved3[112]; - - mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */ - mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */ - mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */ - mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */ - mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */ - mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */ - mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */ - - uint32_t reserved4[36]; - - mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */ - mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */ - mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */ - mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */ - mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */ - - uint32_t reserved5[108]; - - mxs_reg_32(hw_pinctrl_din0) /* 0x900 */ - mxs_reg_32(hw_pinctrl_din1) /* 0x910 */ - mxs_reg_32(hw_pinctrl_din2) /* 0x920 */ - mxs_reg_32(hw_pinctrl_din3) /* 0x930 */ - mxs_reg_32(hw_pinctrl_din4) /* 0x940 */ - - uint32_t reserved6[108]; - - mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */ - mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */ - mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */ - mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */ - mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */ - - uint32_t reserved7[300]; - - mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ - mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ - mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ - mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ - mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ - - uint32_t reserved8[44]; - - mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ - mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ - mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ - mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ - mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ - - uint32_t reserved9[44]; - - mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ - mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ - mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ - mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ - mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ - - uint32_t reserved10[44]; - - mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ - mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ - mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ - mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ - mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ - - uint32_t reserved11[44]; - - mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ - mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ - mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ - mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ - mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ - - uint32_t reserved12[380]; - - mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ - - uint32_t reserved13[76]; - - mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ -}; -#endif - -#define PINCTRL_CTRL_SFTRST (1 << 31) -#define PINCTRL_CTRL_CLKGATE (1 << 30) -#define PINCTRL_CTRL_PRESENT4 (1 << 24) -#define PINCTRL_CTRL_PRESENT3 (1 << 23) -#define PINCTRL_CTRL_PRESENT2 (1 << 22) -#define PINCTRL_CTRL_PRESENT1 (1 << 21) -#define PINCTRL_CTRL_PRESENT0 (1 << 20) -#define PINCTRL_CTRL_IRQOUT4 (1 << 4) -#define PINCTRL_CTRL_IRQOUT3 (1 << 3) -#define PINCTRL_CTRL_IRQOUT2 (1 << 2) -#define PINCTRL_CTRL_IRQOUT1 (1 << 1) -#define PINCTRL_CTRL_IRQOUT0 (1 << 0) - -#define PINCTRL_MUXSEL0_BANK0_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL0_BANK0_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL0_BANK0_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL0_BANK0_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL0_BANK0_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL0_BANK0_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL0_BANK0_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL0_BANK0_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL0_BANK0_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL0_BANK0_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL0_BANK0_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL0_BANK0_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL0_BANK0_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL0_BANK0_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL0_BANK0_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL0_BANK0_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL1_BANK0_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL1_BANK0_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL1_BANK0_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL1_BANK0_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL1_BANK0_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL1_BANK0_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL1_BANK0_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL1_BANK0_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL1_BANK0_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL1_BANK0_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL1_BANK0_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL1_BANK0_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL1_BANK0_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL1_BANK0_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL1_BANK0_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL1_BANK0_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL1_BANK0_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL1_BANK0_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL1_BANK0_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL1_BANK0_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL1_BANK0_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL1_BANK0_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL1_BANK0_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL1_BANK0_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL1_BANK0_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL1_BANK0_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL2_BANK1_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL2_BANK1_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL2_BANK1_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL2_BANK1_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL2_BANK1_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL2_BANK1_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL2_BANK1_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL2_BANK1_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL2_BANK1_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL2_BANK1_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL2_BANK1_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL2_BANK1_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL2_BANK1_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL2_BANK1_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL2_BANK1_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL2_BANK1_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL2_BANK1_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL2_BANK1_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL2_BANK1_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL2_BANK1_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL2_BANK1_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL2_BANK1_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL2_BANK1_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL2_BANK1_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL2_BANK1_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL2_BANK1_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL2_BANK1_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL2_BANK1_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL2_BANK1_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL2_BANK1_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL2_BANK1_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL2_BANK1_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL3_BANK1_PIN31_MASK (0x3 << 30) -#define PINCTRL_MUXSEL3_BANK1_PIN31_OFFSET 30 -#define PINCTRL_MUXSEL3_BANK1_PIN30_MASK (0x3 << 28) -#define PINCTRL_MUXSEL3_BANK1_PIN30_OFFSET 28 -#define PINCTRL_MUXSEL3_BANK1_PIN29_MASK (0x3 << 26) -#define PINCTRL_MUXSEL3_BANK1_PIN29_OFFSET 26 -#define PINCTRL_MUXSEL3_BANK1_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL3_BANK1_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL3_BANK1_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL3_BANK1_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL3_BANK1_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL3_BANK1_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL3_BANK1_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL3_BANK1_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL3_BANK1_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL3_BANK1_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL3_BANK1_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL3_BANK1_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL3_BANK1_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL3_BANK1_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL3_BANK1_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL3_BANK1_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL3_BANK1_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL3_BANK1_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL3_BANK1_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL3_BANK1_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL3_BANK1_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL3_BANK1_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL3_BANK1_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL3_BANK1_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL3_BANK1_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL3_BANK1_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL4_BANK2_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL4_BANK2_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL4_BANK2_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL4_BANK2_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL4_BANK2_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL4_BANK2_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL4_BANK2_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL4_BANK2_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL4_BANK2_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL4_BANK2_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL4_BANK2_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL4_BANK2_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL4_BANK2_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL4_BANK2_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL4_BANK2_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL4_BANK2_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL4_BANK2_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL4_BANK2_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL4_BANK2_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL4_BANK2_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL4_BANK2_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL4_BANK2_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL4_BANK2_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL4_BANK2_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL4_BANK2_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL4_BANK2_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL4_BANK2_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL4_BANK2_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL4_BANK2_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL4_BANK2_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL5_BANK2_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL5_BANK2_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL5_BANK2_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL5_BANK2_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL5_BANK2_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL5_BANK2_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL5_BANK2_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL5_BANK2_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL5_BANK2_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL5_BANK2_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL5_BANK2_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL5_BANK2_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL5_BANK2_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL5_BANK2_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL5_BANK2_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL5_BANK2_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL5_BANK2_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL5_BANK2_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL5_BANK2_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL5_BANK2_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL6_BANK3_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL6_BANK3_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL6_BANK3_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL6_BANK3_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL6_BANK3_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL6_BANK3_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL6_BANK3_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL6_BANK3_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL6_BANK3_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL6_BANK3_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL6_BANK3_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL6_BANK3_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL6_BANK3_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL6_BANK3_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL6_BANK3_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL6_BANK3_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL6_BANK3_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL6_BANK3_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL6_BANK3_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL6_BANK3_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL6_BANK3_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL6_BANK3_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL6_BANK3_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL6_BANK3_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL6_BANK3_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL6_BANK3_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL6_BANK3_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL6_BANK3_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL6_BANK3_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL6_BANK3_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL6_BANK3_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL6_BANK3_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL7_BANK3_PIN30_MASK (0x3 << 28) -#define PINCTRL_MUXSEL7_BANK3_PIN30_OFFSET 28 -#define PINCTRL_MUXSEL7_BANK3_PIN29_MASK (0x3 << 26) -#define PINCTRL_MUXSEL7_BANK3_PIN29_OFFSET 26 -#define PINCTRL_MUXSEL7_BANK3_PIN28_MASK (0x3 << 24) -#define PINCTRL_MUXSEL7_BANK3_PIN28_OFFSET 24 -#define PINCTRL_MUXSEL7_BANK3_PIN27_MASK (0x3 << 22) -#define PINCTRL_MUXSEL7_BANK3_PIN27_OFFSET 22 -#define PINCTRL_MUXSEL7_BANK3_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL7_BANK3_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL7_BANK3_PIN25_MASK (0x3 << 18) -#define PINCTRL_MUXSEL7_BANK3_PIN25_OFFSET 18 -#define PINCTRL_MUXSEL7_BANK3_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL7_BANK3_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL7_BANK3_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL7_BANK3_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL7_BANK3_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL7_BANK3_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL7_BANK3_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL7_BANK3_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL7_BANK3_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL7_BANK3_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL7_BANK3_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL7_BANK3_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL7_BANK3_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL7_BANK3_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL7_BANK3_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL7_BANK3_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL8_BANK4_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL8_BANK4_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL8_BANK4_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL8_BANK4_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL8_BANK4_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL8_BANK4_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL8_BANK4_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL8_BANK4_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL8_BANK4_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL8_BANK4_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL8_BANK4_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL8_BANK4_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL8_BANK4_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL8_BANK4_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL8_BANK4_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL8_BANK4_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL8_BANK4_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL8_BANK4_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL8_BANK4_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL8_BANK4_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL8_BANK4_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL8_BANK4_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL8_BANK4_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL8_BANK4_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL8_BANK4_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL8_BANK4_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL8_BANK4_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL8_BANK4_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL8_BANK4_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL8_BANK4_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL8_BANK4_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL8_BANK4_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL9_BANK4_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL9_BANK4_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL9_BANK4_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL9_BANK4_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL10_BANK5_PIN15_MASK (0x3 << 30) -#define PINCTRL_MUXSEL10_BANK5_PIN15_OFFSET 30 -#define PINCTRL_MUXSEL10_BANK5_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL10_BANK5_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL10_BANK5_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL10_BANK5_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL10_BANK5_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL10_BANK5_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL10_BANK5_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL10_BANK5_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL10_BANK5_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL10_BANK5_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL10_BANK5_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL10_BANK5_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL10_BANK5_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL10_BANK5_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL10_BANK5_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL10_BANK5_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL10_BANK5_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL10_BANK5_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL10_BANK5_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL10_BANK5_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL10_BANK5_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL10_BANK5_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL10_BANK5_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL10_BANK5_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL10_BANK5_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL10_BANK5_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL10_BANK5_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL10_BANK5_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL10_BANK5_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL10_BANK5_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL11_BANK5_PIN26_MASK (0x3 << 20) -#define PINCTRL_MUXSEL11_BANK5_PIN26_OFFSET 20 -#define PINCTRL_MUXSEL11_BANK5_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL11_BANK5_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL11_BANK5_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL11_BANK5_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL11_BANK5_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL11_BANK5_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL11_BANK5_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL11_BANK5_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL11_BANK5_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL11_BANK5_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL11_BANK5_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL11_BANK5_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL11_BANK5_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL11_BANK5_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL11_BANK5_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL11_BANK5_PIN16_OFFSET 0 - -#define PINCTRL_MUXSEL12_BANK6_PIN14_MASK (0x3 << 28) -#define PINCTRL_MUXSEL12_BANK6_PIN14_OFFSET 28 -#define PINCTRL_MUXSEL12_BANK6_PIN13_MASK (0x3 << 26) -#define PINCTRL_MUXSEL12_BANK6_PIN13_OFFSET 26 -#define PINCTRL_MUXSEL12_BANK6_PIN12_MASK (0x3 << 24) -#define PINCTRL_MUXSEL12_BANK6_PIN12_OFFSET 24 -#define PINCTRL_MUXSEL12_BANK6_PIN11_MASK (0x3 << 22) -#define PINCTRL_MUXSEL12_BANK6_PIN11_OFFSET 22 -#define PINCTRL_MUXSEL12_BANK6_PIN10_MASK (0x3 << 20) -#define PINCTRL_MUXSEL12_BANK6_PIN10_OFFSET 20 -#define PINCTRL_MUXSEL12_BANK6_PIN09_MASK (0x3 << 18) -#define PINCTRL_MUXSEL12_BANK6_PIN09_OFFSET 18 -#define PINCTRL_MUXSEL12_BANK6_PIN08_MASK (0x3 << 16) -#define PINCTRL_MUXSEL12_BANK6_PIN08_OFFSET 16 -#define PINCTRL_MUXSEL12_BANK6_PIN07_MASK (0x3 << 14) -#define PINCTRL_MUXSEL12_BANK6_PIN07_OFFSET 14 -#define PINCTRL_MUXSEL12_BANK6_PIN06_MASK (0x3 << 12) -#define PINCTRL_MUXSEL12_BANK6_PIN06_OFFSET 12 -#define PINCTRL_MUXSEL12_BANK6_PIN05_MASK (0x3 << 10) -#define PINCTRL_MUXSEL12_BANK6_PIN05_OFFSET 10 -#define PINCTRL_MUXSEL12_BANK6_PIN04_MASK (0x3 << 8) -#define PINCTRL_MUXSEL12_BANK6_PIN04_OFFSET 8 -#define PINCTRL_MUXSEL12_BANK6_PIN03_MASK (0x3 << 6) -#define PINCTRL_MUXSEL12_BANK6_PIN03_OFFSET 6 -#define PINCTRL_MUXSEL12_BANK6_PIN02_MASK (0x3 << 4) -#define PINCTRL_MUXSEL12_BANK6_PIN02_OFFSET 4 -#define PINCTRL_MUXSEL12_BANK6_PIN01_MASK (0x3 << 2) -#define PINCTRL_MUXSEL12_BANK6_PIN01_OFFSET 2 -#define PINCTRL_MUXSEL12_BANK6_PIN00_MASK (0x3 << 0) -#define PINCTRL_MUXSEL12_BANK6_PIN00_OFFSET 0 - -#define PINCTRL_MUXSEL13_BANK6_PIN24_MASK (0x3 << 16) -#define PINCTRL_MUXSEL13_BANK6_PIN24_OFFSET 16 -#define PINCTRL_MUXSEL13_BANK6_PIN23_MASK (0x3 << 14) -#define PINCTRL_MUXSEL13_BANK6_PIN23_OFFSET 14 -#define PINCTRL_MUXSEL13_BANK6_PIN22_MASK (0x3 << 12) -#define PINCTRL_MUXSEL13_BANK6_PIN22_OFFSET 12 -#define PINCTRL_MUXSEL13_BANK6_PIN21_MASK (0x3 << 10) -#define PINCTRL_MUXSEL13_BANK6_PIN21_OFFSET 10 -#define PINCTRL_MUXSEL13_BANK6_PIN20_MASK (0x3 << 8) -#define PINCTRL_MUXSEL13_BANK6_PIN20_OFFSET 8 -#define PINCTRL_MUXSEL13_BANK6_PIN19_MASK (0x3 << 6) -#define PINCTRL_MUXSEL13_BANK6_PIN19_OFFSET 6 -#define PINCTRL_MUXSEL13_BANK6_PIN18_MASK (0x3 << 4) -#define PINCTRL_MUXSEL13_BANK6_PIN18_OFFSET 4 -#define PINCTRL_MUXSEL13_BANK6_PIN17_MASK (0x3 << 2) -#define PINCTRL_MUXSEL13_BANK6_PIN17_OFFSET 2 -#define PINCTRL_MUXSEL13_BANK6_PIN16_MASK (0x3 << 0) -#define PINCTRL_MUXSEL13_BANK6_PIN16_OFFSET 0 - -#define PINCTRL_DRIVE0_BANK0_PIN07_V (1 << 30) -#define PINCTRL_DRIVE0_BANK0_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE0_BANK0_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE0_BANK0_PIN06_V (1 << 26) -#define PINCTRL_DRIVE0_BANK0_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE0_BANK0_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE0_BANK0_PIN05_V (1 << 22) -#define PINCTRL_DRIVE0_BANK0_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE0_BANK0_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE0_BANK0_PIN04_V (1 << 18) -#define PINCTRL_DRIVE0_BANK0_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE0_BANK0_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE0_BANK0_PIN03_V (1 << 14) -#define PINCTRL_DRIVE0_BANK0_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE0_BANK0_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE0_BANK0_PIN02_V (1 << 10) -#define PINCTRL_DRIVE0_BANK0_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE0_BANK0_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE0_BANK0_PIN01_V (1 << 6) -#define PINCTRL_DRIVE0_BANK0_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE0_BANK0_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE0_BANK0_PIN00_V (1 << 2) -#define PINCTRL_DRIVE0_BANK0_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE0_BANK0_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE2_BANK0_PIN23_V (1 << 30) -#define PINCTRL_DRIVE2_BANK0_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE2_BANK0_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE2_BANK0_PIN22_V (1 << 26) -#define PINCTRL_DRIVE2_BANK0_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE2_BANK0_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE2_BANK0_PIN21_V (1 << 22) -#define PINCTRL_DRIVE2_BANK0_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE2_BANK0_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE2_BANK0_PIN20_V (1 << 18) -#define PINCTRL_DRIVE2_BANK0_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE2_BANK0_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE2_BANK0_PIN19_V (1 << 14) -#define PINCTRL_DRIVE2_BANK0_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE2_BANK0_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE2_BANK0_PIN18_V (1 << 10) -#define PINCTRL_DRIVE2_BANK0_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE2_BANK0_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE2_BANK0_PIN17_V (1 << 6) -#define PINCTRL_DRIVE2_BANK0_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE2_BANK0_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE2_BANK0_PIN16_V (1 << 2) -#define PINCTRL_DRIVE2_BANK0_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE2_BANK0_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE3_BANK0_PIN28_V (1 << 18) -#define PINCTRL_DRIVE3_BANK0_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE3_BANK0_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE3_BANK0_PIN27_V (1 << 14) -#define PINCTRL_DRIVE3_BANK0_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE3_BANK0_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE3_BANK0_PIN26_V (1 << 10) -#define PINCTRL_DRIVE3_BANK0_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE3_BANK0_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE3_BANK0_PIN25_V (1 << 6) -#define PINCTRL_DRIVE3_BANK0_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE3_BANK0_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE3_BANK0_PIN24_V (1 << 2) -#define PINCTRL_DRIVE3_BANK0_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE3_BANK0_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE4_BANK1_PIN07_V (1 << 30) -#define PINCTRL_DRIVE4_BANK1_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE4_BANK1_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE4_BANK1_PIN06_V (1 << 26) -#define PINCTRL_DRIVE4_BANK1_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE4_BANK1_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE4_BANK1_PIN05_V (1 << 22) -#define PINCTRL_DRIVE4_BANK1_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE4_BANK1_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE4_BANK1_PIN04_V (1 << 18) -#define PINCTRL_DRIVE4_BANK1_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE4_BANK1_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE4_BANK1_PIN03_V (1 << 14) -#define PINCTRL_DRIVE4_BANK1_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE4_BANK1_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE4_BANK1_PIN02_V (1 << 10) -#define PINCTRL_DRIVE4_BANK1_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE4_BANK1_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE4_BANK1_PIN01_V (1 << 6) -#define PINCTRL_DRIVE4_BANK1_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE4_BANK1_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE4_BANK1_PIN00_V (1 << 2) -#define PINCTRL_DRIVE4_BANK1_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE4_BANK1_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE5_BANK1_PIN15_V (1 << 30) -#define PINCTRL_DRIVE5_BANK1_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE5_BANK1_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE5_BANK1_PIN14_V (1 << 26) -#define PINCTRL_DRIVE5_BANK1_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE5_BANK1_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE5_BANK1_PIN13_V (1 << 22) -#define PINCTRL_DRIVE5_BANK1_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE5_BANK1_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE5_BANK1_PIN12_V (1 << 18) -#define PINCTRL_DRIVE5_BANK1_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE5_BANK1_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE5_BANK1_PIN11_V (1 << 14) -#define PINCTRL_DRIVE5_BANK1_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE5_BANK1_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE5_BANK1_PIN10_V (1 << 10) -#define PINCTRL_DRIVE5_BANK1_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE5_BANK1_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE5_BANK1_PIN09_V (1 << 6) -#define PINCTRL_DRIVE5_BANK1_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE5_BANK1_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE5_BANK1_PIN08_V (1 << 2) -#define PINCTRL_DRIVE5_BANK1_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE5_BANK1_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE6_BANK1_PIN23_V (1 << 30) -#define PINCTRL_DRIVE6_BANK1_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE6_BANK1_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE6_BANK1_PIN22_V (1 << 26) -#define PINCTRL_DRIVE6_BANK1_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE6_BANK1_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE6_BANK1_PIN21_V (1 << 22) -#define PINCTRL_DRIVE6_BANK1_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE6_BANK1_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE6_BANK1_PIN20_V (1 << 18) -#define PINCTRL_DRIVE6_BANK1_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE6_BANK1_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE6_BANK1_PIN19_V (1 << 14) -#define PINCTRL_DRIVE6_BANK1_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE6_BANK1_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE6_BANK1_PIN18_V (1 << 10) -#define PINCTRL_DRIVE6_BANK1_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE6_BANK1_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE6_BANK1_PIN17_V (1 << 6) -#define PINCTRL_DRIVE6_BANK1_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE6_BANK1_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE6_BANK1_PIN16_V (1 << 2) -#define PINCTRL_DRIVE6_BANK1_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE6_BANK1_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE7_BANK1_PIN31_V (1 << 30) -#define PINCTRL_DRIVE7_BANK1_PIN31_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE7_BANK1_PIN31_MA_OFFSET 28 -#define PINCTRL_DRIVE7_BANK1_PIN30_V (1 << 26) -#define PINCTRL_DRIVE7_BANK1_PIN30_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE7_BANK1_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE7_BANK1_PIN29_V (1 << 22) -#define PINCTRL_DRIVE7_BANK1_PIN29_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE7_BANK1_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE7_BANK1_PIN28_V (1 << 18) -#define PINCTRL_DRIVE7_BANK1_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE7_BANK1_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE7_BANK1_PIN27_V (1 << 14) -#define PINCTRL_DRIVE7_BANK1_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE7_BANK1_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE7_BANK1_PIN26_V (1 << 10) -#define PINCTRL_DRIVE7_BANK1_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE7_BANK1_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE7_BANK1_PIN25_V (1 << 6) -#define PINCTRL_DRIVE7_BANK1_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE7_BANK1_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE7_BANK1_PIN24_V (1 << 2) -#define PINCTRL_DRIVE7_BANK1_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE7_BANK1_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE8_BANK2_PIN07_V (1 << 30) -#define PINCTRL_DRIVE8_BANK2_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE8_BANK2_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE8_BANK2_PIN06_V (1 << 26) -#define PINCTRL_DRIVE8_BANK2_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE8_BANK2_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE8_BANK2_PIN05_V (1 << 22) -#define PINCTRL_DRIVE8_BANK2_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE8_BANK2_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE8_BANK2_PIN04_V (1 << 18) -#define PINCTRL_DRIVE8_BANK2_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE8_BANK2_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE8_BANK2_PIN03_V (1 << 14) -#define PINCTRL_DRIVE8_BANK2_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE8_BANK2_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE8_BANK2_PIN02_V (1 << 10) -#define PINCTRL_DRIVE8_BANK2_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE8_BANK2_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE8_BANK2_PIN01_V (1 << 6) -#define PINCTRL_DRIVE8_BANK2_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE8_BANK2_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE8_BANK2_PIN00_V (1 << 2) -#define PINCTRL_DRIVE8_BANK2_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE8_BANK2_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE9_BANK2_PIN15_V (1 << 30) -#define PINCTRL_DRIVE9_BANK2_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE9_BANK2_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE9_BANK2_PIN14_V (1 << 26) -#define PINCTRL_DRIVE9_BANK2_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE9_BANK2_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE9_BANK2_PIN13_V (1 << 22) -#define PINCTRL_DRIVE9_BANK2_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE9_BANK2_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE9_BANK2_PIN12_V (1 << 18) -#define PINCTRL_DRIVE9_BANK2_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE9_BANK2_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE9_BANK2_PIN10_V (1 << 10) -#define PINCTRL_DRIVE9_BANK2_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE9_BANK2_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE9_BANK2_PIN09_V (1 << 6) -#define PINCTRL_DRIVE9_BANK2_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE9_BANK2_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE9_BANK2_PIN08_V (1 << 2) -#define PINCTRL_DRIVE9_BANK2_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE9_BANK2_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE10_BANK2_PIN21_V (1 << 22) -#define PINCTRL_DRIVE10_BANK2_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE10_BANK2_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE10_BANK2_PIN20_V (1 << 18) -#define PINCTRL_DRIVE10_BANK2_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE10_BANK2_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE10_BANK2_PIN19_V (1 << 14) -#define PINCTRL_DRIVE10_BANK2_PIN19_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE10_BANK2_PIN19_MA_OFFSET 12 -#define PINCTRL_DRIVE10_BANK2_PIN18_V (1 << 10) -#define PINCTRL_DRIVE10_BANK2_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE10_BANK2_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE10_BANK2_PIN17_V (1 << 6) -#define PINCTRL_DRIVE10_BANK2_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE10_BANK2_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE10_BANK2_PIN16_V (1 << 2) -#define PINCTRL_DRIVE10_BANK2_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE10_BANK2_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE11_BANK2_PIN27_V (1 << 14) -#define PINCTRL_DRIVE11_BANK2_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE11_BANK2_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE11_BANK2_PIN26_V (1 << 10) -#define PINCTRL_DRIVE11_BANK2_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE11_BANK2_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE11_BANK2_PIN25_V (1 << 6) -#define PINCTRL_DRIVE11_BANK2_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE11_BANK2_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE11_BANK2_PIN24_V (1 << 2) -#define PINCTRL_DRIVE11_BANK2_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE11_BANK2_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE12_BANK3_PIN07_V (1 << 30) -#define PINCTRL_DRIVE12_BANK3_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE12_BANK3_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE12_BANK3_PIN06_V (1 << 26) -#define PINCTRL_DRIVE12_BANK3_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE12_BANK3_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE12_BANK3_PIN05_V (1 << 22) -#define PINCTRL_DRIVE12_BANK3_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE12_BANK3_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE12_BANK3_PIN04_V (1 << 18) -#define PINCTRL_DRIVE12_BANK3_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE12_BANK3_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE12_BANK3_PIN03_V (1 << 14) -#define PINCTRL_DRIVE12_BANK3_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE12_BANK3_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE12_BANK3_PIN02_V (1 << 10) -#define PINCTRL_DRIVE12_BANK3_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE12_BANK3_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE12_BANK3_PIN01_V (1 << 6) -#define PINCTRL_DRIVE12_BANK3_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE12_BANK3_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE12_BANK3_PIN00_V (1 << 2) -#define PINCTRL_DRIVE12_BANK3_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE12_BANK3_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE13_BANK3_PIN15_V (1 << 30) -#define PINCTRL_DRIVE13_BANK3_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE13_BANK3_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE13_BANK3_PIN14_V (1 << 26) -#define PINCTRL_DRIVE13_BANK3_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE13_BANK3_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE13_BANK3_PIN13_V (1 << 22) -#define PINCTRL_DRIVE13_BANK3_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE13_BANK3_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE13_BANK3_PIN12_V (1 << 18) -#define PINCTRL_DRIVE13_BANK3_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE13_BANK3_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE13_BANK3_PIN11_V (1 << 14) -#define PINCTRL_DRIVE13_BANK3_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE13_BANK3_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE13_BANK3_PIN10_V (1 << 10) -#define PINCTRL_DRIVE13_BANK3_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE13_BANK3_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE13_BANK3_PIN09_V (1 << 6) -#define PINCTRL_DRIVE13_BANK3_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE13_BANK3_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE13_BANK3_PIN08_V (1 << 2) -#define PINCTRL_DRIVE13_BANK3_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE13_BANK3_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE14_BANK3_PIN23_V (1 << 30) -#define PINCTRL_DRIVE14_BANK3_PIN23_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE14_BANK3_PIN23_MA_OFFSET 28 -#define PINCTRL_DRIVE14_BANK3_PIN22_V (1 << 26) -#define PINCTRL_DRIVE14_BANK3_PIN22_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE14_BANK3_PIN22_MA_OFFSET 24 -#define PINCTRL_DRIVE14_BANK3_PIN21_V (1 << 22) -#define PINCTRL_DRIVE14_BANK3_PIN21_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE14_BANK3_PIN21_MA_OFFSET 20 -#define PINCTRL_DRIVE14_BANK3_PIN20_V (1 << 18) -#define PINCTRL_DRIVE14_BANK3_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE14_BANK3_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE14_BANK3_PIN18_V (1 << 10) -#define PINCTRL_DRIVE14_BANK3_PIN18_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE14_BANK3_PIN18_MA_OFFSET 8 -#define PINCTRL_DRIVE14_BANK3_PIN17_V (1 << 6) -#define PINCTRL_DRIVE14_BANK3_PIN17_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE14_BANK3_PIN17_MA_OFFSET 4 -#define PINCTRL_DRIVE14_BANK3_PIN16_V (1 << 2) -#define PINCTRL_DRIVE14_BANK3_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE14_BANK3_PIN16_MA_OFFSET 0 - -#define PINCTRL_DRIVE15_BANK3_PIN30_V (1 << 26) -#define PINCTRL_DRIVE15_BANK3_PIN30_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE15_BANK3_PIN30_MA_OFFSET 24 -#define PINCTRL_DRIVE15_BANK3_PIN29_V (1 << 22) -#define PINCTRL_DRIVE15_BANK3_PIN29_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE15_BANK3_PIN29_MA_OFFSET 20 -#define PINCTRL_DRIVE15_BANK3_PIN28_V (1 << 18) -#define PINCTRL_DRIVE15_BANK3_PIN28_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE15_BANK3_PIN28_MA_OFFSET 16 -#define PINCTRL_DRIVE15_BANK3_PIN27_V (1 << 14) -#define PINCTRL_DRIVE15_BANK3_PIN27_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE15_BANK3_PIN27_MA_OFFSET 12 -#define PINCTRL_DRIVE15_BANK3_PIN26_V (1 << 10) -#define PINCTRL_DRIVE15_BANK3_PIN26_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE15_BANK3_PIN26_MA_OFFSET 8 -#define PINCTRL_DRIVE15_BANK3_PIN25_V (1 << 6) -#define PINCTRL_DRIVE15_BANK3_PIN25_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE15_BANK3_PIN25_MA_OFFSET 4 -#define PINCTRL_DRIVE15_BANK3_PIN24_V (1 << 2) -#define PINCTRL_DRIVE15_BANK3_PIN24_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE15_BANK3_PIN24_MA_OFFSET 0 - -#define PINCTRL_DRIVE16_BANK4_PIN07_V (1 << 30) -#define PINCTRL_DRIVE16_BANK4_PIN07_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE16_BANK4_PIN07_MA_OFFSET 28 -#define PINCTRL_DRIVE16_BANK4_PIN06_V (1 << 26) -#define PINCTRL_DRIVE16_BANK4_PIN06_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE16_BANK4_PIN06_MA_OFFSET 24 -#define PINCTRL_DRIVE16_BANK4_PIN05_V (1 << 22) -#define PINCTRL_DRIVE16_BANK4_PIN05_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE16_BANK4_PIN05_MA_OFFSET 20 -#define PINCTRL_DRIVE16_BANK4_PIN04_V (1 << 18) -#define PINCTRL_DRIVE16_BANK4_PIN04_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE16_BANK4_PIN04_MA_OFFSET 16 -#define PINCTRL_DRIVE16_BANK4_PIN03_V (1 << 14) -#define PINCTRL_DRIVE16_BANK4_PIN03_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE16_BANK4_PIN03_MA_OFFSET 12 -#define PINCTRL_DRIVE16_BANK4_PIN02_V (1 << 10) -#define PINCTRL_DRIVE16_BANK4_PIN02_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE16_BANK4_PIN02_MA_OFFSET 8 -#define PINCTRL_DRIVE16_BANK4_PIN01_V (1 << 6) -#define PINCTRL_DRIVE16_BANK4_PIN01_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE16_BANK4_PIN01_MA_OFFSET 4 -#define PINCTRL_DRIVE16_BANK4_PIN00_V (1 << 2) -#define PINCTRL_DRIVE16_BANK4_PIN00_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE16_BANK4_PIN00_MA_OFFSET 0 - -#define PINCTRL_DRIVE17_BANK4_PIN15_V (1 << 30) -#define PINCTRL_DRIVE17_BANK4_PIN15_MA_MASK (0x3 << 28) -#define PINCTRL_DRIVE17_BANK4_PIN15_MA_OFFSET 28 -#define PINCTRL_DRIVE17_BANK4_PIN14_V (1 << 26) -#define PINCTRL_DRIVE17_BANK4_PIN14_MA_MASK (0x3 << 24) -#define PINCTRL_DRIVE17_BANK4_PIN14_MA_OFFSET 24 -#define PINCTRL_DRIVE17_BANK4_PIN13_V (1 << 22) -#define PINCTRL_DRIVE17_BANK4_PIN13_MA_MASK (0x3 << 20) -#define PINCTRL_DRIVE17_BANK4_PIN13_MA_OFFSET 20 -#define PINCTRL_DRIVE17_BANK4_PIN12_V (1 << 18) -#define PINCTRL_DRIVE17_BANK4_PIN12_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE17_BANK4_PIN12_MA_OFFSET 16 -#define PINCTRL_DRIVE17_BANK4_PIN11_V (1 << 14) -#define PINCTRL_DRIVE17_BANK4_PIN11_MA_MASK (0x3 << 12) -#define PINCTRL_DRIVE17_BANK4_PIN11_MA_OFFSET 12 -#define PINCTRL_DRIVE17_BANK4_PIN10_V (1 << 10) -#define PINCTRL_DRIVE17_BANK4_PIN10_MA_MASK (0x3 << 8) -#define PINCTRL_DRIVE17_BANK4_PIN10_MA_OFFSET 8 -#define PINCTRL_DRIVE17_BANK4_PIN09_V (1 << 6) -#define PINCTRL_DRIVE17_BANK4_PIN09_MA_MASK (0x3 << 4) -#define PINCTRL_DRIVE17_BANK4_PIN09_MA_OFFSET 4 -#define PINCTRL_DRIVE17_BANK4_PIN08_V (1 << 2) -#define PINCTRL_DRIVE17_BANK4_PIN08_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE17_BANK4_PIN08_MA_OFFSET 0 - -#define PINCTRL_DRIVE18_BANK4_PIN20_V (1 << 18) -#define PINCTRL_DRIVE18_BANK4_PIN20_MA_MASK (0x3 << 16) -#define PINCTRL_DRIVE18_BANK4_PIN20_MA_OFFSET 16 -#define PINCTRL_DRIVE18_BANK4_PIN16_V (1 << 2) -#define PINCTRL_DRIVE18_BANK4_PIN16_MA_MASK (0x3 << 0) -#define PINCTRL_DRIVE18_BANK4_PIN16_MA_OFFSET 0 - -#define PINCTRL_PULL0_BANK0_PIN28 (1 << 28) -#define PINCTRL_PULL0_BANK0_PIN27 (1 << 27) -#define PINCTRL_PULL0_BANK0_PIN26 (1 << 26) -#define PINCTRL_PULL0_BANK0_PIN25 (1 << 25) -#define PINCTRL_PULL0_BANK0_PIN24 (1 << 24) -#define PINCTRL_PULL0_BANK0_PIN23 (1 << 23) -#define PINCTRL_PULL0_BANK0_PIN22 (1 << 22) -#define PINCTRL_PULL0_BANK0_PIN21 (1 << 21) -#define PINCTRL_PULL0_BANK0_PIN20 (1 << 20) -#define PINCTRL_PULL0_BANK0_PIN19 (1 << 19) -#define PINCTRL_PULL0_BANK0_PIN18 (1 << 18) -#define PINCTRL_PULL0_BANK0_PIN17 (1 << 17) -#define PINCTRL_PULL0_BANK0_PIN16 (1 << 16) -#define PINCTRL_PULL0_BANK0_PIN07 (1 << 7) -#define PINCTRL_PULL0_BANK0_PIN06 (1 << 6) -#define PINCTRL_PULL0_BANK0_PIN05 (1 << 5) -#define PINCTRL_PULL0_BANK0_PIN04 (1 << 4) -#define PINCTRL_PULL0_BANK0_PIN03 (1 << 3) -#define PINCTRL_PULL0_BANK0_PIN02 (1 << 2) -#define PINCTRL_PULL0_BANK0_PIN01 (1 << 1) -#define PINCTRL_PULL0_BANK0_PIN00 (1 << 0) - -#define PINCTRL_PULL1_BANK1_PIN31 (1 << 31) -#define PINCTRL_PULL1_BANK1_PIN30 (1 << 30) -#define PINCTRL_PULL1_BANK1_PIN29 (1 << 29) -#define PINCTRL_PULL1_BANK1_PIN28 (1 << 28) -#define PINCTRL_PULL1_BANK1_PIN27 (1 << 27) -#define PINCTRL_PULL1_BANK1_PIN26 (1 << 26) -#define PINCTRL_PULL1_BANK1_PIN25 (1 << 25) -#define PINCTRL_PULL1_BANK1_PIN24 (1 << 24) -#define PINCTRL_PULL1_BANK1_PIN23 (1 << 23) -#define PINCTRL_PULL1_BANK1_PIN22 (1 << 22) -#define PINCTRL_PULL1_BANK1_PIN21 (1 << 21) -#define PINCTRL_PULL1_BANK1_PIN20 (1 << 20) -#define PINCTRL_PULL1_BANK1_PIN19 (1 << 19) -#define PINCTRL_PULL1_BANK1_PIN18 (1 << 18) -#define PINCTRL_PULL1_BANK1_PIN17 (1 << 17) -#define PINCTRL_PULL1_BANK1_PIN16 (1 << 16) -#define PINCTRL_PULL1_BANK1_PIN15 (1 << 15) -#define PINCTRL_PULL1_BANK1_PIN14 (1 << 14) -#define PINCTRL_PULL1_BANK1_PIN13 (1 << 13) -#define PINCTRL_PULL1_BANK1_PIN12 (1 << 12) -#define PINCTRL_PULL1_BANK1_PIN11 (1 << 11) -#define PINCTRL_PULL1_BANK1_PIN10 (1 << 10) -#define PINCTRL_PULL1_BANK1_PIN09 (1 << 9) -#define PINCTRL_PULL1_BANK1_PIN08 (1 << 8) -#define PINCTRL_PULL1_BANK1_PIN07 (1 << 7) -#define PINCTRL_PULL1_BANK1_PIN06 (1 << 6) -#define PINCTRL_PULL1_BANK1_PIN05 (1 << 5) -#define PINCTRL_PULL1_BANK1_PIN04 (1 << 4) -#define PINCTRL_PULL1_BANK1_PIN03 (1 << 3) -#define PINCTRL_PULL1_BANK1_PIN02 (1 << 2) -#define PINCTRL_PULL1_BANK1_PIN01 (1 << 1) -#define PINCTRL_PULL1_BANK1_PIN00 (1 << 0) - -#define PINCTRL_PULL2_BANK2_PIN27 (1 << 27) -#define PINCTRL_PULL2_BANK2_PIN26 (1 << 26) -#define PINCTRL_PULL2_BANK2_PIN25 (1 << 25) -#define PINCTRL_PULL2_BANK2_PIN24 (1 << 24) -#define PINCTRL_PULL2_BANK2_PIN21 (1 << 21) -#define PINCTRL_PULL2_BANK2_PIN20 (1 << 20) -#define PINCTRL_PULL2_BANK2_PIN19 (1 << 19) -#define PINCTRL_PULL2_BANK2_PIN18 (1 << 18) -#define PINCTRL_PULL2_BANK2_PIN17 (1 << 17) -#define PINCTRL_PULL2_BANK2_PIN16 (1 << 16) -#define PINCTRL_PULL2_BANK2_PIN15 (1 << 15) -#define PINCTRL_PULL2_BANK2_PIN14 (1 << 14) -#define PINCTRL_PULL2_BANK2_PIN13 (1 << 13) -#define PINCTRL_PULL2_BANK2_PIN12 (1 << 12) -#define PINCTRL_PULL2_BANK2_PIN10 (1 << 10) -#define PINCTRL_PULL2_BANK2_PIN09 (1 << 9) -#define PINCTRL_PULL2_BANK2_PIN08 (1 << 8) -#define PINCTRL_PULL2_BANK2_PIN07 (1 << 7) -#define PINCTRL_PULL2_BANK2_PIN06 (1 << 6) -#define PINCTRL_PULL2_BANK2_PIN05 (1 << 5) -#define PINCTRL_PULL2_BANK2_PIN04 (1 << 4) -#define PINCTRL_PULL2_BANK2_PIN03 (1 << 3) -#define PINCTRL_PULL2_BANK2_PIN02 (1 << 2) -#define PINCTRL_PULL2_BANK2_PIN01 (1 << 1) -#define PINCTRL_PULL2_BANK2_PIN00 (1 << 0) - -#define PINCTRL_PULL3_BANK3_PIN30 (1 << 30) -#define PINCTRL_PULL3_BANK3_PIN29 (1 << 29) -#define PINCTRL_PULL3_BANK3_PIN28 (1 << 28) -#define PINCTRL_PULL3_BANK3_PIN27 (1 << 27) -#define PINCTRL_PULL3_BANK3_PIN26 (1 << 26) -#define PINCTRL_PULL3_BANK3_PIN25 (1 << 25) -#define PINCTRL_PULL3_BANK3_PIN24 (1 << 24) -#define PINCTRL_PULL3_BANK3_PIN23 (1 << 23) -#define PINCTRL_PULL3_BANK3_PIN22 (1 << 22) -#define PINCTRL_PULL3_BANK3_PIN21 (1 << 21) -#define PINCTRL_PULL3_BANK3_PIN20 (1 << 20) -#define PINCTRL_PULL3_BANK3_PIN18 (1 << 18) -#define PINCTRL_PULL3_BANK3_PIN17 (1 << 17) -#define PINCTRL_PULL3_BANK3_PIN16 (1 << 16) -#define PINCTRL_PULL3_BANK3_PIN15 (1 << 15) -#define PINCTRL_PULL3_BANK3_PIN14 (1 << 14) -#define PINCTRL_PULL3_BANK3_PIN13 (1 << 13) -#define PINCTRL_PULL3_BANK3_PIN12 (1 << 12) -#define PINCTRL_PULL3_BANK3_PIN11 (1 << 11) -#define PINCTRL_PULL3_BANK3_PIN10 (1 << 10) -#define PINCTRL_PULL3_BANK3_PIN09 (1 << 9) -#define PINCTRL_PULL3_BANK3_PIN08 (1 << 8) -#define PINCTRL_PULL3_BANK3_PIN07 (1 << 7) -#define PINCTRL_PULL3_BANK3_PIN06 (1 << 6) -#define PINCTRL_PULL3_BANK3_PIN05 (1 << 5) -#define PINCTRL_PULL3_BANK3_PIN04 (1 << 4) -#define PINCTRL_PULL3_BANK3_PIN03 (1 << 3) -#define PINCTRL_PULL3_BANK3_PIN02 (1 << 2) -#define PINCTRL_PULL3_BANK3_PIN01 (1 << 1) -#define PINCTRL_PULL3_BANK3_PIN00 (1 << 0) - -#define PINCTRL_PULL4_BANK4_PIN20 (1 << 20) -#define PINCTRL_PULL4_BANK4_PIN16 (1 << 16) -#define PINCTRL_PULL4_BANK4_PIN15 (1 << 15) -#define PINCTRL_PULL4_BANK4_PIN14 (1 << 14) -#define PINCTRL_PULL4_BANK4_PIN13 (1 << 13) -#define PINCTRL_PULL4_BANK4_PIN12 (1 << 12) -#define PINCTRL_PULL4_BANK4_PIN11 (1 << 11) -#define PINCTRL_PULL4_BANK4_PIN10 (1 << 10) -#define PINCTRL_PULL4_BANK4_PIN09 (1 << 9) -#define PINCTRL_PULL4_BANK4_PIN08 (1 << 8) -#define PINCTRL_PULL4_BANK4_PIN07 (1 << 7) -#define PINCTRL_PULL4_BANK4_PIN06 (1 << 6) -#define PINCTRL_PULL4_BANK4_PIN05 (1 << 5) -#define PINCTRL_PULL4_BANK4_PIN04 (1 << 4) -#define PINCTRL_PULL4_BANK4_PIN03 (1 << 3) -#define PINCTRL_PULL4_BANK4_PIN02 (1 << 2) -#define PINCTRL_PULL4_BANK4_PIN01 (1 << 1) -#define PINCTRL_PULL4_BANK4_PIN00 (1 << 0) - -#define PINCTRL_PULL5_BANK5_PIN26 (1 << 26) -#define PINCTRL_PULL5_BANK5_PIN23 (1 << 23) -#define PINCTRL_PULL5_BANK5_PIN22 (1 << 22) -#define PINCTRL_PULL5_BANK5_PIN21 (1 << 21) -#define PINCTRL_PULL5_BANK5_PIN20 (1 << 20) -#define PINCTRL_PULL5_BANK5_PIN19 (1 << 19) -#define PINCTRL_PULL5_BANK5_PIN18 (1 << 18) -#define PINCTRL_PULL5_BANK5_PIN17 (1 << 17) -#define PINCTRL_PULL5_BANK5_PIN16 (1 << 16) -#define PINCTRL_PULL5_BANK5_PIN15 (1 << 15) -#define PINCTRL_PULL5_BANK5_PIN14 (1 << 14) -#define PINCTRL_PULL5_BANK5_PIN13 (1 << 13) -#define PINCTRL_PULL5_BANK5_PIN12 (1 << 12) -#define PINCTRL_PULL5_BANK5_PIN11 (1 << 11) -#define PINCTRL_PULL5_BANK5_PIN10 (1 << 10) -#define PINCTRL_PULL5_BANK5_PIN09 (1 << 9) -#define PINCTRL_PULL5_BANK5_PIN08 (1 << 8) -#define PINCTRL_PULL5_BANK5_PIN07 (1 << 7) -#define PINCTRL_PULL5_BANK5_PIN06 (1 << 6) -#define PINCTRL_PULL5_BANK5_PIN05 (1 << 5) -#define PINCTRL_PULL5_BANK5_PIN04 (1 << 4) -#define PINCTRL_PULL5_BANK5_PIN03 (1 << 3) -#define PINCTRL_PULL5_BANK5_PIN02 (1 << 2) -#define PINCTRL_PULL5_BANK5_PIN01 (1 << 1) -#define PINCTRL_PULL5_BANK5_PIN00 (1 << 0) - -#define PINCTRL_PULL6_BANK6_PIN24 (1 << 24) -#define PINCTRL_PULL6_BANK6_PIN23 (1 << 23) -#define PINCTRL_PULL6_BANK6_PIN22 (1 << 22) -#define PINCTRL_PULL6_BANK6_PIN21 (1 << 21) -#define PINCTRL_PULL6_BANK6_PIN20 (1 << 20) -#define PINCTRL_PULL6_BANK6_PIN19 (1 << 19) -#define PINCTRL_PULL6_BANK6_PIN18 (1 << 18) -#define PINCTRL_PULL6_BANK6_PIN17 (1 << 17) -#define PINCTRL_PULL6_BANK6_PIN16 (1 << 16) -#define PINCTRL_PULL6_BANK6_PIN14 (1 << 14) -#define PINCTRL_PULL6_BANK6_PIN13 (1 << 13) -#define PINCTRL_PULL6_BANK6_PIN12 (1 << 12) -#define PINCTRL_PULL6_BANK6_PIN11 (1 << 11) -#define PINCTRL_PULL6_BANK6_PIN10 (1 << 10) -#define PINCTRL_PULL6_BANK6_PIN09 (1 << 9) -#define PINCTRL_PULL6_BANK6_PIN08 (1 << 8) -#define PINCTRL_PULL6_BANK6_PIN07 (1 << 7) -#define PINCTRL_PULL6_BANK6_PIN06 (1 << 6) -#define PINCTRL_PULL6_BANK6_PIN05 (1 << 5) -#define PINCTRL_PULL6_BANK6_PIN04 (1 << 4) -#define PINCTRL_PULL6_BANK6_PIN03 (1 << 3) -#define PINCTRL_PULL6_BANK6_PIN02 (1 << 2) -#define PINCTRL_PULL6_BANK6_PIN01 (1 << 1) -#define PINCTRL_PULL6_BANK6_PIN00 (1 << 0) - -#define PINCTRL_DOUT0_DOUT_MASK 0x1fffffff -#define PINCTRL_DOUT0_DOUT_OFFSET 0 - -#define PINCTRL_DOUT1_DOUT_MASK 0xffffffff -#define PINCTRL_DOUT1_DOUT_OFFSET 0 - -#define PINCTRL_DOUT2_DOUT_MASK 0xfffffff -#define PINCTRL_DOUT2_DOUT_OFFSET 0 - -#define PINCTRL_DOUT3_DOUT_MASK 0x7fffffff -#define PINCTRL_DOUT3_DOUT_OFFSET 0 - -#define PINCTRL_DOUT4_DOUT_MASK 0x1fffff -#define PINCTRL_DOUT4_DOUT_OFFSET 0 - -#define PINCTRL_DIN0_DIN_MASK 0x1fffffff -#define PINCTRL_DIN0_DIN_OFFSET 0 - -#define PINCTRL_DIN1_DIN_MASK 0xffffffff -#define PINCTRL_DIN1_DIN_OFFSET 0 - -#define PINCTRL_DIN2_DIN_MASK 0xfffffff -#define PINCTRL_DIN2_DIN_OFFSET 0 - -#define PINCTRL_DIN3_DIN_MASK 0x7fffffff -#define PINCTRL_DIN3_DIN_OFFSET 0 - -#define PINCTRL_DIN4_DIN_MASK 0x1fffff -#define PINCTRL_DIN4_DIN_OFFSET 0 - -#define PINCTRL_DOE0_DOE_MASK 0x1fffffff -#define PINCTRL_DOE0_DOE_OFFSET 0 - -#define PINCTRL_DOE1_DOE_MASK 0xffffffff -#define PINCTRL_DOE1_DOE_OFFSET 0 - -#define PINCTRL_DOE2_DOE_MASK 0xfffffff -#define PINCTRL_DOE2_DOE_OFFSET 0 - -#define PINCTRL_DOE3_DOE_MASK 0x7fffffff -#define PINCTRL_DOE3_DOE_OFFSET 0 - -#define PINCTRL_DOE4_DOE_MASK 0x1fffff -#define PINCTRL_DOE4_DOE_OFFSET 0 - -#define PINCTRL_PIN2IRQ0_PIN2IRQ_MASK 0x1fffffff -#define PINCTRL_PIN2IRQ0_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ1_PIN2IRQ_MASK 0xffffffff -#define PINCTRL_PIN2IRQ1_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ2_PIN2IRQ_MASK 0xfffffff -#define PINCTRL_PIN2IRQ2_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ3_PIN2IRQ_MASK 0x7fffffff -#define PINCTRL_PIN2IRQ3_PIN2IRQ_OFFSET 0 - -#define PINCTRL_PIN2IRQ4_PIN2IRQ_MASK 0x1fffff -#define PINCTRL_PIN2IRQ4_PIN2IRQ_OFFSET 0 - -#define PINCTRL_IRQEN0_IRQEN_MASK 0x1fffffff -#define PINCTRL_IRQEN0_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN1_IRQEN_MASK 0xffffffff -#define PINCTRL_IRQEN1_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN2_IRQEN_MASK 0xfffffff -#define PINCTRL_IRQEN2_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN3_IRQEN_MASK 0x7fffffff -#define PINCTRL_IRQEN3_IRQEN_OFFSET 0 - -#define PINCTRL_IRQEN4_IRQEN_MASK 0x1fffff -#define PINCTRL_IRQEN4_IRQEN_OFFSET 0 - -#define PINCTRL_IRQLEVEL0_IRQLEVEL_MASK 0x1fffffff -#define PINCTRL_IRQLEVEL0_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL1_IRQLEVEL_MASK 0xffffffff -#define PINCTRL_IRQLEVEL1_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL2_IRQLEVEL_MASK 0xfffffff -#define PINCTRL_IRQLEVEL2_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL3_IRQLEVEL_MASK 0x7fffffff -#define PINCTRL_IRQLEVEL3_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQLEVEL4_IRQLEVEL_MASK 0x1fffff -#define PINCTRL_IRQLEVEL4_IRQLEVEL_OFFSET 0 - -#define PINCTRL_IRQPOL0_IRQPOL_MASK 0x1fffffff -#define PINCTRL_IRQPOL0_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL1_IRQPOL_MASK 0xffffffff -#define PINCTRL_IRQPOL1_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL2_IRQPOL_MASK 0xfffffff -#define PINCTRL_IRQPOL2_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL3_IRQPOL_MASK 0x7fffffff -#define PINCTRL_IRQPOL3_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQPOL4_IRQPOL_MASK 0x1fffff -#define PINCTRL_IRQPOL4_IRQPOL_OFFSET 0 - -#define PINCTRL_IRQSTAT0_IRQSTAT_MASK 0x1fffffff -#define PINCTRL_IRQSTAT0_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT1_IRQSTAT_MASK 0xffffffff -#define PINCTRL_IRQSTAT1_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT2_IRQSTAT_MASK 0xfffffff -#define PINCTRL_IRQSTAT2_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT3_IRQSTAT_MASK 0x7fffffff -#define PINCTRL_IRQSTAT3_IRQSTAT_OFFSET 0 - -#define PINCTRL_IRQSTAT4_IRQSTAT_MASK 0x1fffff -#define PINCTRL_IRQSTAT4_IRQSTAT_OFFSET 0 - -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_MASK (0x3 << 26) -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_CALIB_OFFSET 26 -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_MASK (0x3 << 24) -#define PINCTRL_EMI_ODT_CTRL_ADDRESS_TLOAD_OFFSET 24 -#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_MASK (0x3 << 22) -#define PINCTRL_EMI_ODT_CTRL_CONTROL_CALIB_OFFSET 22 -#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_MASK (0x3 << 20) -#define PINCTRL_EMI_ODT_CTRL_CONTROL_TLOAD_OFFSET 20 -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_MASK (0x3 << 18) -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_CALIB_OFFSET 18 -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_MASK (0x3 << 16) -#define PINCTRL_EMI_ODT_CTRL_DUALPAD_TLOAD_OFFSET 16 -#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_MASK (0x3 << 14) -#define PINCTRL_EMI_ODT_CTRL_SLICE3_CALIB_OFFSET 14 -#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_MASK (0x3 << 12) -#define PINCTRL_EMI_ODT_CTRL_SLICE3_TLOAD_OFFSET 12 -#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_MASK (0x3 << 10) -#define PINCTRL_EMI_ODT_CTRL_SLICE2_CALIB_OFFSET 10 -#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_MASK (0x3 << 8) -#define PINCTRL_EMI_ODT_CTRL_SLICE2_TLOAD_OFFSET 8 -#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_MASK (0x3 << 6) -#define PINCTRL_EMI_ODT_CTRL_SLICE1_CALIB_OFFSET 6 -#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_MASK (0x3 << 4) -#define PINCTRL_EMI_ODT_CTRL_SLICE1_TLOAD_OFFSET 4 -#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_MASK (0x3 << 2) -#define PINCTRL_EMI_ODT_CTRL_SLICE0_CALIB_OFFSET 2 -#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_MASK (0x3 << 0) -#define PINCTRL_EMI_ODT_CTRL_SLICE0_TLOAD_OFFSET 0 - -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_MASK (0x3 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_OFFSET 16 -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_mDDR (0x0 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_GPIO (0x1 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_LVDDR2 (0x2 << 16) -#define PINCTRL_EMI_DS_CTRL_DDR_MODE_DDR2 (0x3 << 16) -#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_MASK (0x3 << 12) -#define PINCTRL_EMI_DS_CTRL_ADDRESS_MA_OFFSET 12 -#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_MASK (0x3 << 10) -#define PINCTRL_EMI_DS_CTRL_CONTROL_MA_OFFSET 10 -#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_MASK (0x3 << 8) -#define PINCTRL_EMI_DS_CTRL_DUALPAD_MA_OFFSET 8 -#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_MASK (0x3 << 6) -#define PINCTRL_EMI_DS_CTRL_SLICE3_MA_OFFSET 6 -#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_MASK (0x3 << 4) -#define PINCTRL_EMI_DS_CTRL_SLICE2_MA_OFFSET 4 -#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_MASK (0x3 << 2) -#define PINCTRL_EMI_DS_CTRL_SLICE1_MA_OFFSET 2 -#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_MASK (0x3 << 0) -#define PINCTRL_EMI_DS_CTRL_SLICE0_MA_OFFSET 0 - -#endif /* __MX28_REGS_PINCTRL_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h b/arch/arm/include/asm/arch-mxs/regs-power-mx23.h deleted file mode 100644 index a0dc781..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx23.h +++ /dev/null @@ -1,344 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23 Power Controller Register Definitions - * - * Copyright (C) 2012 Marek Vasut <marex@denx.de> - */ - -#ifndef __MX23_REGS_POWER_H__ -#define __MX23_REGS_POWER_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_power_regs { - mxs_reg_32(hw_power_ctrl) - mxs_reg_32(hw_power_5vctrl) - mxs_reg_32(hw_power_minpwr) - mxs_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mxs_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mxs_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; - - uint32_t reserved1[4]; - - mxs_reg_32(hw_power_reset) - - uint32_t reserved2[4]; - - mxs_reg_32(hw_power_special) - mxs_reg_32(hw_power_version) -}; -#endif - -#define POWER_CTRL_CLKGATE (1 << 30) -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) - -#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 28 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 28) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 28) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x1 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) - -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_VDAC_DUMP_CTRL (1 << 13) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) - -#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_CHARGER_RESISTORS (1 << 21) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_USE_EXTERN_R (1 << 17) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 - -#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0 - -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0 - -#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0 - -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0 - -#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 - -#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) - -#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 - -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3 - -#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) - -#define POWER_SPEED_STATUS_MASK (0xff << 16) -#define POWER_SPEED_STATUS_OFFSET 16 -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3 - -#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 - -#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) - -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) - -#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0 - -#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0 - -#endif /* __MX23_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h deleted file mode 100644 index 39250c5..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h +++ /dev/null @@ -1,399 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 Power Controller Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - */ - -#ifndef __MX28_REGS_POWER_H__ -#define __MX28_REGS_POWER_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_power_regs { - mxs_reg_32(hw_power_ctrl) - mxs_reg_32(hw_power_5vctrl) - mxs_reg_32(hw_power_minpwr) - mxs_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mxs_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mxs_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; - - uint32_t reserved[4]; - - mxs_reg_32(hw_power_reset) - mxs_reg_32(hw_power_debug) - mxs_reg_32(hw_power_thermal) - mxs_reg_32(hw_power_usb1ctrl) - mxs_reg_32(hw_power_special) - mxs_reg_32(hw_power_version) - mxs_reg_32(hw_power_anaclkctrl) - mxs_reg_32(hw_power_refctrl) -}; -#endif - -#define POWER_CTRL_PSWITCH_MID_TRAN (1 << 27) -#define POWER_CTRL_DCDC4P2_BO_IRQ (1 << 24) -#define POWER_CTRL_ENIRQ_DCDC4P2_BO (1 << 23) -#define POWER_CTRL_VDD5V_DROOP_IRQ (1 << 22) -#define POWER_CTRL_ENIRQ_VDD5V_DROOP (1 << 21) -#define POWER_CTRL_PSWITCH_IRQ (1 << 20) -#define POWER_CTRL_PSWITCH_IRQ_SRC (1 << 19) -#define POWER_CTRL_POLARITY_PSWITCH (1 << 18) -#define POWER_CTRL_ENIRQ_PSWITCH (1 << 17) -#define POWER_CTRL_POLARITY_DC_OK (1 << 16) -#define POWER_CTRL_DC_OK_IRQ (1 << 15) -#define POWER_CTRL_ENIRQ_DC_OK (1 << 14) -#define POWER_CTRL_BATT_BO_IRQ (1 << 13) -#define POWER_CTRL_ENIRQ_BATT_BO (1 << 12) -#define POWER_CTRL_VDDIO_BO_IRQ (1 << 11) -#define POWER_CTRL_ENIRQ_VDDIO_BO (1 << 10) -#define POWER_CTRL_VDDA_BO_IRQ (1 << 9) -#define POWER_CTRL_ENIRQ_VDDA_BO (1 << 8) -#define POWER_CTRL_VDDD_BO_IRQ (1 << 7) -#define POWER_CTRL_ENIRQ_VDDD_BO (1 << 6) -#define POWER_CTRL_POLARITY_VBUSVALID (1 << 5) -#define POWER_CTRL_VBUS_VALID_IRQ (1 << 4) -#define POWER_CTRL_ENIRQ_VBUS_VALID (1 << 3) -#define POWER_CTRL_POLARITY_VDD5V_GT_VDDIO (1 << 2) -#define POWER_CTRL_VDD5V_GT_VDDIO_IRQ (1 << 1) -#define POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO (1 << 0) - -#define POWER_5VCTRL_VBUSDROOP_TRSH_MASK (0x3 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_OFFSET 30 -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V3 (0x0 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V4 (0x1 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V5 (0x2 << 30) -#define POWER_5VCTRL_VBUSDROOP_TRSH_4V7 (0x3 << 30) -#define POWER_5VCTRL_HEADROOM_ADJ_MASK (0x7 << 24) -#define POWER_5VCTRL_HEADROOM_ADJ_OFFSET 24 -#define POWER_5VCTRL_PWD_CHARGE_4P2_MASK (0x3 << 20) -#define POWER_5VCTRL_PWD_CHARGE_4P2_OFFSET 20 -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK (0x3f << 12) -#define POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET 12 -#define POWER_5VCTRL_VBUSVALID_TRSH_MASK (0x7 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_OFFSET 8 -#define POWER_5VCTRL_VBUSVALID_TRSH_2V9 (0x0 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V0 (0x1 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V1 (0x2 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V2 (0x3 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V3 (0x4 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V4 (0x5 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V5 (0x6 << 8) -#define POWER_5VCTRL_VBUSVALID_TRSH_4V6 (0x7 << 8) -#define POWER_5VCTRL_PWDN_5VBRNOUT (1 << 7) -#define POWER_5VCTRL_ENABLE_LINREG_ILIMIT (1 << 6) -#define POWER_5VCTRL_DCDC_XFER (1 << 5) -#define POWER_5VCTRL_VBUSVALID_5VDETECT (1 << 4) -#define POWER_5VCTRL_VBUSVALID_TO_B (1 << 3) -#define POWER_5VCTRL_ILIMIT_EQ_ZERO (1 << 2) -#define POWER_5VCTRL_PWRUP_VBUS_CMPS (1 << 1) -#define POWER_5VCTRL_ENABLE_DCDC (1 << 0) - -#define POWER_MINPWR_LOWPWR_4P2 (1 << 14) -#define POWER_MINPWR_PWD_BO (1 << 12) -#define POWER_MINPWR_USE_VDDXTAL_VBG (1 << 11) -#define POWER_MINPWR_PWD_ANA_CMPS (1 << 10) -#define POWER_MINPWR_ENABLE_OSC (1 << 9) -#define POWER_MINPWR_SELECT_OSC (1 << 8) -#define POWER_MINPWR_VBG_OFF (1 << 7) -#define POWER_MINPWR_DOUBLE_FETS (1 << 6) -#define POWER_MINPWR_HALFFETS (1 << 5) -#define POWER_MINPWR_LESSANA_I (1 << 4) -#define POWER_MINPWR_PWD_XTAL24 (1 << 3) -#define POWER_MINPWR_DC_STOPCLK (1 << 2) -#define POWER_MINPWR_EN_DC_PFM (1 << 1) -#define POWER_MINPWR_DC_HALFCLK (1 << 0) - -#define POWER_CHARGE_ADJ_VOLT_MASK (0x7 << 24) -#define POWER_CHARGE_ADJ_VOLT_OFFSET 24 -#define POWER_CHARGE_ADJ_VOLT_M025P (0x1 << 24) -#define POWER_CHARGE_ADJ_VOLT_P050P (0x2 << 24) -#define POWER_CHARGE_ADJ_VOLT_M075P (0x3 << 24) -#define POWER_CHARGE_ADJ_VOLT_P025P (0x4 << 24) -#define POWER_CHARGE_ADJ_VOLT_M050P (0x5 << 24) -#define POWER_CHARGE_ADJ_VOLT_P075P (0x6 << 24) -#define POWER_CHARGE_ADJ_VOLT_M100P (0x7 << 24) -#define POWER_CHARGE_ENABLE_LOAD (1 << 22) -#define POWER_CHARGE_ENABLE_FAULT_DETECT (1 << 20) -#define POWER_CHARGE_CHRG_STS_OFF (1 << 19) -#define POWER_CHARGE_LIION_4P1 (1 << 18) -#define POWER_CHARGE_PWD_BATTCHRG (1 << 16) -#define POWER_CHARGE_ENABLE_CHARGER_USB1 (1 << 13) -#define POWER_CHARGE_ENABLE_CHARGER_USB0 (1 << 12) -#define POWER_CHARGE_STOP_ILIMIT_MASK (0xf << 8) -#define POWER_CHARGE_STOP_ILIMIT_OFFSET 8 -#define POWER_CHARGE_STOP_ILIMIT_10MA (0x1 << 8) -#define POWER_CHARGE_STOP_ILIMIT_20MA (0x2 << 8) -#define POWER_CHARGE_STOP_ILIMIT_50MA (0x4 << 8) -#define POWER_CHARGE_STOP_ILIMIT_100MA (0x8 << 8) -#define POWER_CHARGE_BATTCHRG_I_MASK 0x3f -#define POWER_CHARGE_BATTCHRG_I_OFFSET 0 -#define POWER_CHARGE_BATTCHRG_I_10MA 0x01 -#define POWER_CHARGE_BATTCHRG_I_20MA 0x02 -#define POWER_CHARGE_BATTCHRG_I_50MA 0x04 -#define POWER_CHARGE_BATTCHRG_I_100MA 0x08 -#define POWER_CHARGE_BATTCHRG_I_200MA 0x10 -#define POWER_CHARGE_BATTCHRG_I_400MA 0x20 - -#define POWER_VDDDCTRL_ADJTN_MASK (0xf << 28) -#define POWER_VDDDCTRL_ADJTN_OFFSET 28 -#define POWER_VDDDCTRL_PWDN_BRNOUT (1 << 23) -#define POWER_VDDDCTRL_DISABLE_STEPPING (1 << 22) -#define POWER_VDDDCTRL_ENABLE_LINREG (1 << 21) -#define POWER_VDDDCTRL_DISABLE_FET (1 << 20) -#define POWER_VDDDCTRL_LINREG_OFFSET_MASK (0x3 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_OFFSET 16 -#define POWER_VDDDCTRL_LINREG_OFFSET_0STEPS (0x0 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 16) -#define POWER_VDDDCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 16) -#define POWER_VDDDCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDDCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDDCTRL_TRG_MASK 0x1f -#define POWER_VDDDCTRL_TRG_OFFSET 0 - -#define POWER_VDDACTRL_PWDN_BRNOUT (1 << 19) -#define POWER_VDDACTRL_DISABLE_STEPPING (1 << 18) -#define POWER_VDDACTRL_ENABLE_LINREG (1 << 17) -#define POWER_VDDACTRL_DISABLE_FET (1 << 16) -#define POWER_VDDACTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDACTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDACTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDACTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDACTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDACTRL_TRG_MASK 0x1f -#define POWER_VDDACTRL_TRG_OFFSET 0 - -#define POWER_VDDIOCTRL_ADJTN_MASK (0xf << 20) -#define POWER_VDDIOCTRL_ADJTN_OFFSET 20 -#define POWER_VDDIOCTRL_PWDN_BRNOUT (1 << 18) -#define POWER_VDDIOCTRL_DISABLE_STEPPING (1 << 17) -#define POWER_VDDIOCTRL_DISABLE_FET (1 << 16) -#define POWER_VDDIOCTRL_LINREG_OFFSET_MASK (0x3 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_OFFSET 12 -#define POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS (0x0 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_ABOVE (0x1 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW (0x2 << 12) -#define POWER_VDDIOCTRL_LINREG_OFFSET_2STEPS_BELOW (0x3 << 12) -#define POWER_VDDIOCTRL_BO_OFFSET_MASK (0x7 << 8) -#define POWER_VDDIOCTRL_BO_OFFSET_OFFSET 8 -#define POWER_VDDIOCTRL_TRG_MASK 0x1f -#define POWER_VDDIOCTRL_TRG_OFFSET 0 - -#define POWER_VDDMEMCTRL_PULLDOWN_ACTIVE (1 << 10) -#define POWER_VDDMEMCTRL_ENABLE_ILIMIT (1 << 9) -#define POWER_VDDMEMCTRL_ENABLE_LINREG (1 << 8) -#define POWER_VDDMEMCTRL_BO_OFFSET_MASK (0x7 << 5) -#define POWER_VDDMEMCTRL_BO_OFFSET_OFFSET 5 -#define POWER_VDDMEMCTRL_TRG_MASK 0x1f -#define POWER_VDDMEMCTRL_TRG_OFFSET 0 - -#define POWER_DCDC4P2_DROPOUT_CTRL_MASK (0xf << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_OFFSET 28 -#define POWER_DCDC4P2_DROPOUT_CTRL_200MV (0x3 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_100MV (0x2 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_50MV (0x1 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_25MV (0x0 << 30) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2 (0x0 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_4P2_LT_BATT (0x1 << 28) -#define POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL (0x2 << 28) -#define POWER_DCDC4P2_ISTEAL_THRESH_MASK (0x3 << 24) -#define POWER_DCDC4P2_ISTEAL_THRESH_OFFSET 24 -#define POWER_DCDC4P2_ENABLE_4P2 (1 << 23) -#define POWER_DCDC4P2_ENABLE_DCDC (1 << 22) -#define POWER_DCDC4P2_HYST_DIR (1 << 21) -#define POWER_DCDC4P2_HYST_THRESH (1 << 20) -#define POWER_DCDC4P2_TRG_MASK (0x7 << 16) -#define POWER_DCDC4P2_TRG_OFFSET 16 -#define POWER_DCDC4P2_TRG_4V2 (0x0 << 16) -#define POWER_DCDC4P2_TRG_4V1 (0x1 << 16) -#define POWER_DCDC4P2_TRG_4V0 (0x2 << 16) -#define POWER_DCDC4P2_TRG_3V9 (0x3 << 16) -#define POWER_DCDC4P2_TRG_BATT (0x4 << 16) -#define POWER_DCDC4P2_BO_MASK (0x1f << 8) -#define POWER_DCDC4P2_BO_OFFSET 8 -#define POWER_DCDC4P2_CMPTRIP_MASK 0x1f -#define POWER_DCDC4P2_CMPTRIP_OFFSET 0 - -#define POWER_MISC_FREQSEL_MASK (0x7 << 4) -#define POWER_MISC_FREQSEL_OFFSET 4 -#define POWER_MISC_FREQSEL_20MHZ (0x1 << 4) -#define POWER_MISC_FREQSEL_24MHZ (0x2 << 4) -#define POWER_MISC_FREQSEL_19MHZ (0x3 << 4) -#define POWER_MISC_FREQSEL_14MHZ (0x4 << 4) -#define POWER_MISC_FREQSEL_18MHZ (0x5 << 4) -#define POWER_MISC_FREQSEL_21MHZ (0x6 << 4) -#define POWER_MISC_FREQSEL_17MHZ (0x7 << 4) -#define POWER_MISC_DISABLE_FET_BO_LOGIC (1 << 3) -#define POWER_MISC_DELAY_TIMING (1 << 2) -#define POWER_MISC_TEST (1 << 1) -#define POWER_MISC_SEL_PLLCLK (1 << 0) - -#define POWER_DCLIMITS_POSLIMIT_BUCK_MASK (0x7f << 8) -#define POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET 8 -#define POWER_DCLIMITS_NEGLIMIT_MASK 0x7f -#define POWER_DCLIMITS_NEGLIMIT_OFFSET 0 - -#define POWER_LOOPCTRL_TOGGLE_DIF (1 << 20) -#define POWER_LOOPCTRL_HYST_SIGN (1 << 19) -#define POWER_LOOPCTRL_EN_CM_HYST (1 << 18) -#define POWER_LOOPCTRL_EN_DF_HYST (1 << 17) -#define POWER_LOOPCTRL_CM_HYST_THRESH (1 << 16) -#define POWER_LOOPCTRL_DF_HYST_THRESH (1 << 15) -#define POWER_LOOPCTRL_RCSCALE_THRESH (1 << 14) -#define POWER_LOOPCTRL_EN_RCSCALE_MASK (0x3 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_OFFSET 12 -#define POWER_LOOPCTRL_EN_RCSCALE_DIS (0x0 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_2X (0x1 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_4X (0x2 << 12) -#define POWER_LOOPCTRL_EN_RCSCALE_8X (0x3 << 12) -#define POWER_LOOPCTRL_DC_FF_MASK (0x7 << 8) -#define POWER_LOOPCTRL_DC_FF_OFFSET 8 -#define POWER_LOOPCTRL_DC_R_MASK (0xf << 4) -#define POWER_LOOPCTRL_DC_R_OFFSET 4 -#define POWER_LOOPCTRL_DC_C_MASK 0x3 -#define POWER_LOOPCTRL_DC_C_OFFSET 0 -#define POWER_LOOPCTRL_DC_C_MAX 0x0 -#define POWER_LOOPCTRL_DC_C_2X 0x1 -#define POWER_LOOPCTRL_DC_C_4X 0x2 -#define POWER_LOOPCTRL_DC_C_MIN 0x3 - -#define POWER_STS_PWRUP_SOURCE_MASK (0x3f << 24) -#define POWER_STS_PWRUP_SOURCE_OFFSET 24 -#define POWER_STS_PWRUP_SOURCE_5V (0x20 << 24) -#define POWER_STS_PWRUP_SOURCE_RTC (0x10 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_HIGH (0x02 << 24) -#define POWER_STS_PWRUP_SOURCE_PSWITCH_MID (0x01 << 24) -#define POWER_STS_PSWITCH_MASK (0x3 << 20) -#define POWER_STS_PSWITCH_OFFSET 20 -#define POWER_STS_THERMAL_WARNING (1 << 19) -#define POWER_STS_VDDMEM_BO (1 << 18) -#define POWER_STS_AVALID0_STATUS (1 << 17) -#define POWER_STS_BVALID0_STATUS (1 << 16) -#define POWER_STS_VBUSVALID0_STATUS (1 << 15) -#define POWER_STS_SESSEND0_STATUS (1 << 14) -#define POWER_STS_BATT_BO (1 << 13) -#define POWER_STS_VDD5V_FAULT (1 << 12) -#define POWER_STS_CHRGSTS (1 << 11) -#define POWER_STS_DCDC_4P2_BO (1 << 10) -#define POWER_STS_DC_OK (1 << 9) -#define POWER_STS_VDDIO_BO (1 << 8) -#define POWER_STS_VDDA_BO (1 << 7) -#define POWER_STS_VDDD_BO (1 << 6) -#define POWER_STS_VDD5V_GT_VDDIO (1 << 5) -#define POWER_STS_VDD5V_DROOP (1 << 4) -#define POWER_STS_AVALID0 (1 << 3) -#define POWER_STS_BVALID0 (1 << 2) -#define POWER_STS_VBUSVALID0 (1 << 1) -#define POWER_STS_SESSEND0 (1 << 0) - -#define POWER_SPEED_STATUS_MASK (0xffff << 8) -#define POWER_SPEED_STATUS_OFFSET 8 -#define POWER_SPEED_STATUS_SEL_MASK (0x3 << 6) -#define POWER_SPEED_STATUS_SEL_OFFSET 6 -#define POWER_SPEED_STATUS_SEL_DCDC_STAT (0x0 << 6) -#define POWER_SPEED_STATUS_SEL_CORE_STAT (0x1 << 6) -#define POWER_SPEED_STATUS_SEL_ARM_STAT (0x2 << 6) -#define POWER_SPEED_CTRL_MASK 0x3 -#define POWER_SPEED_CTRL_OFFSET 0 -#define POWER_SPEED_CTRL_SS_OFF 0x0 -#define POWER_SPEED_CTRL_SS_ON 0x1 -#define POWER_SPEED_CTRL_SS_ENABLE 0x3 - -#define POWER_BATTMONITOR_BATT_VAL_MASK (0x3ff << 16) -#define POWER_BATTMONITOR_BATT_VAL_OFFSET 16 -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN (1 << 11) -#define POWER_BATTMONITOR_EN_BATADJ (1 << 10) -#define POWER_BATTMONITOR_PWDN_BATTBRNOUT (1 << 9) -#define POWER_BATTMONITOR_BRWNOUT_PWD (1 << 8) -#define POWER_BATTMONITOR_BRWNOUT_LVL_MASK 0x1f -#define POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET 0 - -#define POWER_RESET_UNLOCK_MASK (0xffff << 16) -#define POWER_RESET_UNLOCK_OFFSET 16 -#define POWER_RESET_UNLOCK_KEY (0x3e77 << 16) -#define POWER_RESET_FASTFALL_PSWITCH_OFF (1 << 2) -#define POWER_RESET_PWD_OFF (1 << 1) -#define POWER_RESET_PWD (1 << 0) - -#define POWER_DEBUG_VBUSVALIDPIOLOCK (1 << 3) -#define POWER_DEBUG_AVALIDPIOLOCK (1 << 2) -#define POWER_DEBUG_BVALIDPIOLOCK (1 << 1) -#define POWER_DEBUG_SESSENDPIOLOCK (1 << 0) - -#define POWER_THERMAL_TEST (1 << 8) -#define POWER_THERMAL_PWD (1 << 7) -#define POWER_THERMAL_LOW_POWER (1 << 6) -#define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) -#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 -#define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) -#define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 -#define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 - -#define POWER_USB1CTRL_AVALID1 (1 << 3) -#define POWER_USB1CTRL_BVALID1 (1 << 2) -#define POWER_USB1CTRL_VBUSVALID1 (1 << 1) -#define POWER_USB1CTRL_SESSEND1 (1 << 0) - -#define POWER_SPECIAL_TEST_MASK 0xffffffff -#define POWER_SPECIAL_TEST_OFFSET 0 - -#define POWER_VERSION_MAJOR_MASK (0xff << 24) -#define POWER_VERSION_MAJOR_OFFSET 24 -#define POWER_VERSION_MINOR_MASK (0xff << 16) -#define POWER_VERSION_MINOR_OFFSET 16 -#define POWER_VERSION_STEP_MASK 0xffff -#define POWER_VERSION_STEP_OFFSET 0 - -#define POWER_ANACLKCTRL_CLKGATE_0 (1 << 31) -#define POWER_ANACLKCTRL_OUTDIV_MASK (0x7 << 28) -#define POWER_ANACLKCTRL_OUTDIV_OFFSET 28 -#define POWER_ANACLKCTRL_INVERT_OUTCLK (1 << 27) -#define POWER_ANACLKCTRL_CLKGATE_I (1 << 26) -#define POWER_ANACLKCTRL_DITHER_OFF (1 << 10) -#define POWER_ANACLKCTRL_SLOW_DITHER (1 << 9) -#define POWER_ANACLKCTRL_INVERT_INCLK (1 << 8) -#define POWER_ANACLKCTRL_INCLK_SHIFT_MASK (0x3 << 4) -#define POWER_ANACLKCTRL_INCLK_SHIFT_OFFSET 4 -#define POWER_ANACLKCTRL_INDIV_MASK 0x7 -#define POWER_ANACLKCTRL_INDIV_OFFSET 0 - -#define POWER_REFCTRL_FASTSETTLING (1 << 26) -#define POWER_REFCTRL_RAISE_REF (1 << 25) -#define POWER_REFCTRL_XTAL_BGR_BIAS (1 << 24) -#define POWER_REFCTRL_VBG_ADJ_MASK (0x7 << 20) -#define POWER_REFCTRL_VBG_ADJ_OFFSET 20 -#define POWER_REFCTRL_LOW_PWR (1 << 19) -#define POWER_REFCTRL_BIAS_CTRL_MASK (0x3 << 16) -#define POWER_REFCTRL_BIAS_CTRL_OFFSET 16 -#define POWER_REFCTRL_VDDXTAL_TO_VDDD (1 << 14) -#define POWER_REFCTRL_ADJ_ANA (1 << 13) -#define POWER_REFCTRL_ADJ_VAG (1 << 12) -#define POWER_REFCTRL_ANA_REFVAL_MASK (0xf << 8) -#define POWER_REFCTRL_ANA_REFVAL_OFFSET 8 -#define POWER_REFCTRL_VAG_VAL_MASK (0xf << 4) -#define POWER_REFCTRL_VAG_VAL_OFFSET 4 - -#endif /* __MX28_REGS_POWER_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h deleted file mode 100644 index 8d6ba57..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-rtc.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 RTC Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __MX28_REGS_RTC_H__ -#define __MX28_REGS_RTC_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_rtc_regs { - mxs_reg_32(hw_rtc_ctrl) - mxs_reg_32(hw_rtc_stat) - mxs_reg_32(hw_rtc_milliseconds) - mxs_reg_32(hw_rtc_seconds) - mxs_reg_32(hw_rtc_rtc_alarm) - mxs_reg_32(hw_rtc_watchdog) - mxs_reg_32(hw_rtc_persistent0) - mxs_reg_32(hw_rtc_persistent1) - mxs_reg_32(hw_rtc_persistent2) - mxs_reg_32(hw_rtc_persistent3) - mxs_reg_32(hw_rtc_persistent4) - mxs_reg_32(hw_rtc_persistent5) - mxs_reg_32(hw_rtc_debug) - mxs_reg_32(hw_rtc_version) -}; -#endif - -#define RTC_CTRL_SFTRST (1 << 31) -#define RTC_CTRL_CLKGATE (1 << 30) -#define RTC_CTRL_SUPPRESS_COPY2ANALOG (1 << 6) -#define RTC_CTRL_FORCE_UPDATE (1 << 5) -#define RTC_CTRL_WATCHDOGEN (1 << 4) -#define RTC_CTRL_ONEMSEC_IRQ (1 << 3) -#define RTC_CTRL_ALARM_IRQ (1 << 2) -#define RTC_CTRL_ONEMSEC_IRQ_EN (1 << 1) -#define RTC_CTRL_ALARM_IRQ_EN (1 << 0) - -#define RTC_STAT_RTC_PRESENT (1 << 31) -#define RTC_STAT_ALARM_PRESENT (1 << 30) -#define RTC_STAT_WATCHDOG_PRESENT (1 << 29) -#define RTC_STAT_XTAL32000_PRESENT (1 << 28) -#define RTC_STAT_XTAL32768_PRESENT (1 << 27) -#define RTC_STAT_STALE_REGS_MASK (0xff << 16) -#define RTC_STAT_STALE_REGS_OFFSET 16 -#define RTC_STAT_NEW_REGS_MASK (0xff << 8) -#define RTC_STAT_NEW_REGS_OFFSET 8 - -#define RTC_MILLISECONDS_COUNT_MASK 0xffffffff -#define RTC_MILLISECONDS_COUNT_OFFSET 0 - -#define RTC_SECONDS_COUNT_MASK 0xffffffff -#define RTC_SECONDS_COUNT_OFFSET 0 - -#define RTC_ALARM_VALUE_MASK 0xffffffff -#define RTC_ALARM_VALUE_OFFSET 0 - -#define RTC_WATCHDOG_COUNT_MASK 0xffffffff -#define RTC_WATCHDOG_COUNT_OFFSET 0 - -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_MASK (0xf << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_OFFSET 28 -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V83 (0x0 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V78 (0x1 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V73 (0x2 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V68 (0x3 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V62 (0x4 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V57 (0x5 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V52 (0x6 << 28) -#define RTC_PERSISTENT0_ADJ_POSLIMITBUCK_2V48 (0x7 << 28) -#define RTC_PERSISTENT0_EXTERNAL_RESET (1 << 21) -#define RTC_PERSISTENT0_THERMAL_RESET (1 << 20) -#define RTC_PERSISTENT0_ENABLE_LRADC_PWRUP (1 << 18) -#define RTC_PERSISTENT0_AUTO_RESTART (1 << 17) -#define RTC_PERSISTENT0_DISABLE_PSWITCH (1 << 16) -#define RTC_PERSISTENT0_LOWERBIAS_MASK (0xf << 14) -#define RTC_PERSISTENT0_LOWERBIAS_OFFSET 14 -#define RTC_PERSISTENT0_LOWERBIAS_NOMINAL (0x0 << 14) -#define RTC_PERSISTENT0_LOWERBIAS_M25P (0x1 << 14) -#define RTC_PERSISTENT0_LOWERBIAS_M50P (0x3 << 14) -#define RTC_PERSISTENT0_DISABLE_XTALOK (1 << 13) -#define RTC_PERSISTENT0_MSEC_RES_MASK (0x1f << 8) -#define RTC_PERSISTENT0_MSEC_RES_OFFSET 8 -#define RTC_PERSISTENT0_MSEC_RES_1MS (0x01 << 8) -#define RTC_PERSISTENT0_MSEC_RES_2MS (0x02 << 8) -#define RTC_PERSISTENT0_MSEC_RES_4MS (0x04 << 8) -#define RTC_PERSISTENT0_MSEC_RES_8MS (0x08 << 8) -#define RTC_PERSISTENT0_MSEC_RES_16MS (0x10 << 8) -#define RTC_PERSISTENT0_ALARM_WAKE (1 << 7) -#define RTC_PERSISTENT0_XTAL32_FREQ (1 << 6) -#define RTC_PERSISTENT0_XTAL32KHZ_PWRUP (1 << 5) -#define RTC_PERSISTENT0_XTAL24KHZ_PWRUP (1 << 4) -#define RTC_PERSISTENT0_LCK_SECS (1 << 3) -#define RTC_PERSISTENT0_ALARM_EN (1 << 2) -#define RTC_PERSISTENT0_ALARM_WAKE_EN (1 << 1) -#define RTC_PERSISTENT0_CLOCKSOURCE (1 << 0) - -#define RTC_PERSISTENT1_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT1_GENERAL_OFFSET 0 -#define RTC_PERSISTENT1_GENERAL_OTG_ALT_ROLE 0x0080 -#define RTC_PERSISTENT1_GENERAL_OTG_HNP 0x0100 -#define RTC_PERSISTENT1_GENERAL_USB_LPM 0x0200 -#define RTC_PERSISTENT1_GENERAL_SKIP_CHECKDISK 0x0400 -#define RTC_PERSISTENT1_GENERAL_USB_BOOT_PLAYER 0x0800 -#define RTC_PERSISTENT1_GENERAL_ENUM_500MA_2X 0x1000 - -#define RTC_PERSISTENT2_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT2_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT3_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT3_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT4_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT4_GENERAL_OFFSET 0 - -#define RTC_PERSISTENT5_GENERAL_MASK 0xffffffff -#define RTC_PERSISTENT5_GENERAL_OFFSET 0 - -#define RTC_DEBUG_WATCHDOG_RESET_MASK (1 << 1) -#define RTC_DEBUG_WATCHDOG_RESET (1 << 0) - -#define RTC_VERSION_MAJOR_MASK (0xff << 24) -#define RTC_VERSION_MAJOR_OFFSET 24 -#define RTC_VERSION_MINOR_MASK (0xff << 16) -#define RTC_VERSION_MINOR_OFFSET 16 -#define RTC_VERSION_STEP_MASK 0xffff -#define RTC_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_RTC_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h deleted file mode 100644 index eeb7e7f..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ /dev/null @@ -1,415 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 SSP Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_SSP_H__ -#define __MX28_REGS_SSP_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -#if defined(CONFIG_MX23) -struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_status) - - uint32_t reserved1[12]; - - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) -}; -#elif defined(CONFIG_MX28) -struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_xfer_size) - mxs_reg_32(hw_ssp_block_size) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_ddr_ctrl) - mxs_reg_32(hw_ssp_dll_ctrl) - mxs_reg_32(hw_ssp_status) - mxs_reg_32(hw_ssp_dll_sts) - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) -}; -#endif - -static inline int mxs_ssp_bus_id_valid(int bus) -{ -#if defined(CONFIG_MX23) - const unsigned int mxs_ssp_chan_count = 2; -#elif defined(CONFIG_MX28) - const unsigned int mxs_ssp_chan_count = 4; -#endif - - if (bus >= mxs_ssp_chan_count) - return 0; - - if (bus < 0) - return 0; - - return 1; -} - -static inline int mxs_ssp_clock_by_bus(unsigned int clock) -{ -#if defined(CONFIG_MX23) - return 0; -#elif defined(CONFIG_MX28) - return clock; -#endif -} - -static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port) -{ - switch (port) { - case 0: - return (struct mxs_ssp_regs *)MXS_SSP0_BASE; - case 1: - return (struct mxs_ssp_regs *)MXS_SSP1_BASE; -#ifdef CONFIG_MX28 - case 2: - return (struct mxs_ssp_regs *)MXS_SSP2_BASE; - case 3: - return (struct mxs_ssp_regs *)MXS_SSP3_BASE; -#endif - default: - return NULL; - } -} -#endif - -#define SSP_CTRL0_SFTRST (1 << 31) -#define SSP_CTRL0_CLKGATE (1 << 30) -#define SSP_CTRL0_RUN (1 << 29) -#define SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28) -#define SSP_CTRL0_LOCK_CS (1 << 27) -#define SSP_CTRL0_IGNORE_CRC (1 << 26) -#define SSP_CTRL0_READ (1 << 25) -#define SSP_CTRL0_DATA_XFER (1 << 24) -#define SSP_CTRL0_BUS_WIDTH_MASK (0x3 << 22) -#define SSP_CTRL0_BUS_WIDTH_OFFSET 22 -#define SSP_CTRL0_BUS_WIDTH_ONE_BIT (0x0 << 22) -#define SSP_CTRL0_BUS_WIDTH_FOUR_BIT (0x1 << 22) -#define SSP_CTRL0_BUS_WIDTH_EIGHT_BIT (0x2 << 22) -#define SSP_CTRL0_WAIT_FOR_IRQ (1 << 21) -#define SSP_CTRL0_WAIT_FOR_CMD (1 << 20) -#define SSP_CTRL0_LONG_RESP (1 << 19) -#define SSP_CTRL0_CHECK_RESP (1 << 18) -#define SSP_CTRL0_GET_RESP (1 << 17) -#define SSP_CTRL0_ENABLE (1 << 16) - -#ifdef CONFIG_MX23 -#define SSP_CTRL0_XFER_COUNT_OFFSET 0 -#define SSP_CTRL0_XFER_COUNT_MASK 0xffff -#endif - -#define SSP_CMD0_SOFT_TERMINATE (1 << 26) -#define SSP_CMD0_DBL_DATA_RATE_EN (1 << 25) -#define SSP_CMD0_PRIM_BOOT_OP_EN (1 << 24) -#define SSP_CMD0_BOOT_ACK_EN (1 << 23) -#define SSP_CMD0_SLOW_CLKING_EN (1 << 22) -#define SSP_CMD0_CONT_CLKING_EN (1 << 21) -#define SSP_CMD0_APPEND_8CYC (1 << 20) -#if defined(CONFIG_MX23) -#define SSP_CMD0_BLOCK_SIZE_MASK (0xf << 16) -#define SSP_CMD0_BLOCK_SIZE_OFFSET 16 -#define SSP_CMD0_BLOCK_COUNT_MASK (0xff << 8) -#define SSP_CMD0_BLOCK_COUNT_OFFSET 8 -#endif -#define SSP_CMD0_CMD_MASK 0xff -#define SSP_CMD0_CMD_OFFSET 0 -#define SSP_CMD0_CMD_MMC_GO_IDLE_STATE 0x00 -#define SSP_CMD0_CMD_MMC_SEND_OP_COND 0x01 -#define SSP_CMD0_CMD_MMC_ALL_SEND_CID 0x02 -#define SSP_CMD0_CMD_MMC_SET_RELATIVE_ADDR 0x03 -#define SSP_CMD0_CMD_MMC_SET_DSR 0x04 -#define SSP_CMD0_CMD_MMC_RESERVED_5 0x05 -#define SSP_CMD0_CMD_MMC_SWITCH 0x06 -#define SSP_CMD0_CMD_MMC_SELECT_DESELECT_CARD 0x07 -#define SSP_CMD0_CMD_MMC_SEND_EXT_CSD 0x08 -#define SSP_CMD0_CMD_MMC_SEND_CSD 0x09 -#define SSP_CMD0_CMD_MMC_SEND_CID 0x0a -#define SSP_CMD0_CMD_MMC_READ_DAT_UNTIL_STOP 0x0b -#define SSP_CMD0_CMD_MMC_STOP_TRANSMISSION 0x0c -#define SSP_CMD0_CMD_MMC_SEND_STATUS 0x0d -#define SSP_CMD0_CMD_MMC_BUSTEST_R 0x0e -#define SSP_CMD0_CMD_MMC_GO_INACTIVE_STATE 0x0f -#define SSP_CMD0_CMD_MMC_SET_BLOCKLEN 0x10 -#define SSP_CMD0_CMD_MMC_READ_SINGLE_BLOCK 0x11 -#define SSP_CMD0_CMD_MMC_READ_MULTIPLE_BLOCK 0x12 -#define SSP_CMD0_CMD_MMC_BUSTEST_W 0x13 -#define SSP_CMD0_CMD_MMC_WRITE_DAT_UNTIL_STOP 0x14 -#define SSP_CMD0_CMD_MMC_SET_BLOCK_COUNT 0x17 -#define SSP_CMD0_CMD_MMC_WRITE_BLOCK 0x18 -#define SSP_CMD0_CMD_MMC_WRITE_MULTIPLE_BLOCK 0x19 -#define SSP_CMD0_CMD_MMC_PROGRAM_CID 0x1a -#define SSP_CMD0_CMD_MMC_PROGRAM_CSD 0x1b -#define SSP_CMD0_CMD_MMC_SET_WRITE_PROT 0x1c -#define SSP_CMD0_CMD_MMC_CLR_WRITE_PROT 0x1d -#define SSP_CMD0_CMD_MMC_SEND_WRITE_PROT 0x1e -#define SSP_CMD0_CMD_MMC_ERASE_GROUP_START 0x23 -#define SSP_CMD0_CMD_MMC_ERASE_GROUP_END 0x24 -#define SSP_CMD0_CMD_MMC_ERASE 0x26 -#define SSP_CMD0_CMD_MMC_FAST_IO 0x27 -#define SSP_CMD0_CMD_MMC_GO_IRQ_STATE 0x28 -#define SSP_CMD0_CMD_MMC_LOCK_UNLOCK 0x2a -#define SSP_CMD0_CMD_MMC_APP_CMD 0x37 -#define SSP_CMD0_CMD_MMC_GEN_CMD 0x38 -#define SSP_CMD0_CMD_SD_GO_IDLE_STATE 0x00 -#define SSP_CMD0_CMD_SD_ALL_SEND_CID 0x02 -#define SSP_CMD0_CMD_SD_SEND_RELATIVE_ADDR 0x03 -#define SSP_CMD0_CMD_SD_SET_DSR 0x04 -#define SSP_CMD0_CMD_SD_IO_SEND_OP_COND 0x05 -#define SSP_CMD0_CMD_SD_SELECT_DESELECT_CARD 0x07 -#define SSP_CMD0_CMD_SD_SEND_CSD 0x09 -#define SSP_CMD0_CMD_SD_SEND_CID 0x0a -#define SSP_CMD0_CMD_SD_STOP_TRANSMISSION 0x0c -#define SSP_CMD0_CMD_SD_SEND_STATUS 0x0d -#define SSP_CMD0_CMD_SD_GO_INACTIVE_STATE 0x0f -#define SSP_CMD0_CMD_SD_SET_BLOCKLEN 0x10 -#define SSP_CMD0_CMD_SD_READ_SINGLE_BLOCK 0x11 -#define SSP_CMD0_CMD_SD_READ_MULTIPLE_BLOCK 0x12 -#define SSP_CMD0_CMD_SD_WRITE_BLOCK 0x18 -#define SSP_CMD0_CMD_SD_WRITE_MULTIPLE_BLOCK 0x19 -#define SSP_CMD0_CMD_SD_PROGRAM_CSD 0x1b -#define SSP_CMD0_CMD_SD_SET_WRITE_PROT 0x1c -#define SSP_CMD0_CMD_SD_CLR_WRITE_PROT 0x1d -#define SSP_CMD0_CMD_SD_SEND_WRITE_PROT 0x1e -#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_START 0x20 -#define SSP_CMD0_CMD_SD_ERASE_WR_BLK_END 0x21 -#define SSP_CMD0_CMD_SD_ERASE_GROUP_START 0x23 -#define SSP_CMD0_CMD_SD_ERASE_GROUP_END 0x24 -#define SSP_CMD0_CMD_SD_ERASE 0x26 -#define SSP_CMD0_CMD_SD_LOCK_UNLOCK 0x2a -#define SSP_CMD0_CMD_SD_IO_RW_DIRECT 0x34 -#define SSP_CMD0_CMD_SD_IO_RW_EXTENDED 0x35 -#define SSP_CMD0_CMD_SD_APP_CMD 0x37 -#define SSP_CMD0_CMD_SD_GEN_CMD 0x38 - -#define SSP_CMD1_CMD_ARG_MASK 0xffffffff -#define SSP_CMD1_CMD_ARG_OFFSET 0 - -#if defined(CONFIG_MX28) -#define SSP_XFER_SIZE_XFER_COUNT_MASK 0xffffffff -#define SSP_XFER_SIZE_XFER_COUNT_OFFSET 0 - -#define SSP_BLOCK_SIZE_BLOCK_COUNT_MASK (0xffffff << 4) -#define SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET 4 -#define SSP_BLOCK_SIZE_BLOCK_SIZE_MASK 0xf -#define SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET 0 -#endif - -#define SSP_COMPREF_REFERENCE_MASK 0xffffffff -#define SSP_COMPREF_REFERENCE_OFFSET 0 - -#define SSP_COMPMASK_MASK_MASK 0xffffffff -#define SSP_COMPMASK_MASK_OFFSET 0 - -#define SSP_TIMING_TIMEOUT_MASK (0xffff << 16) -#define SSP_TIMING_TIMEOUT_OFFSET 16 -#define SSP_TIMING_CLOCK_DIVIDE_MASK (0xff << 8) -#define SSP_TIMING_CLOCK_DIVIDE_OFFSET 8 -#define SSP_TIMING_CLOCK_RATE_MASK 0xff -#define SSP_TIMING_CLOCK_RATE_OFFSET 0 - -#define SSP_CTRL1_SDIO_IRQ (1 << 31) -#define SSP_CTRL1_SDIO_IRQ_EN (1 << 30) -#define SSP_CTRL1_RESP_ERR_IRQ (1 << 29) -#define SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27) -#define SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25) -#define SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24) -#define SSP_CTRL1_DATA_CRC_IRQ (1 << 23) -#define SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22) -#define SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21) -#define SSP_CTRL1_FIFO_UNDERRUN_EN (1 << 20) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ (1 << 19) -#define SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN (1 << 18) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17) -#define SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15) -#define SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14) -#define SSP_CTRL1_DMA_ENABLE (1 << 13) -#define SSP_CTRL1_CEATA_CCS_ERR_EN (1 << 12) -#define SSP_CTRL1_SLAVE_OUT_DISABLE (1 << 11) -#define SSP_CTRL1_PHASE (1 << 10) -#define SSP_CTRL1_POLARITY (1 << 9) -#define SSP_CTRL1_SLAVE_MODE (1 << 8) -#define SSP_CTRL1_WORD_LENGTH_MASK (0xf << 4) -#define SSP_CTRL1_WORD_LENGTH_OFFSET 4 -#define SSP_CTRL1_WORD_LENGTH_RESERVED0 (0x0 << 4) -#define SSP_CTRL1_WORD_LENGTH_RESERVED1 (0x1 << 4) -#define SSP_CTRL1_WORD_LENGTH_RESERVED2 (0x2 << 4) -#define SSP_CTRL1_WORD_LENGTH_FOUR_BITS (0x3 << 4) -#define SSP_CTRL1_WORD_LENGTH_EIGHT_BITS (0x7 << 4) -#define SSP_CTRL1_WORD_LENGTH_SIXTEEN_BITS (0xf << 4) -#define SSP_CTRL1_SSP_MODE_MASK 0xf -#define SSP_CTRL1_SSP_MODE_OFFSET 0 -#define SSP_CTRL1_SSP_MODE_SPI 0x0 -#define SSP_CTRL1_SSP_MODE_SSI 0x1 -#define SSP_CTRL1_SSP_MODE_SD_MMC 0x3 -#define SSP_CTRL1_SSP_MODE_MS 0x4 - -#define SSP_DATA_DATA_MASK 0xffffffff -#define SSP_DATA_DATA_OFFSET 0 - -#define SSP_SDRESP0_RESP0_MASK 0xffffffff -#define SSP_SDRESP0_RESP0_OFFSET 0 - -#define SSP_SDRESP1_RESP1_MASK 0xffffffff -#define SSP_SDRESP1_RESP1_OFFSET 0 - -#define SSP_SDRESP2_RESP2_MASK 0xffffffff -#define SSP_SDRESP2_RESP2_OFFSET 0 - -#define SSP_SDRESP3_RESP3_MASK 0xffffffff -#define SSP_SDRESP3_RESP3_OFFSET 0 - -#define SSP_DDR_CTRL_DMA_BURST_TYPE_MASK (0x3 << 30) -#define SSP_DDR_CTRL_DMA_BURST_TYPE_OFFSET 30 -#define SSP_DDR_CTRL_NIBBLE_POS (1 << 1) -#define SSP_DDR_CTRL_TXCLK_DELAY_TYPE (1 << 0) - -#define SSP_DLL_CTRL_REF_UPDATE_INT_MASK (0xf << 28) -#define SSP_DLL_CTRL_REF_UPDATE_INT_OFFSET 28 -#define SSP_DLL_CTRL_SLV_UPDATE_INT_MASK (0xff << 20) -#define SSP_DLL_CTRL_SLV_UPDATE_INT_OFFSET 20 -#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3f << 10) -#define SSP_DLL_CTRL_SLV_OVERRIDE_VAL_OFFSET 10 -#define SSP_DLL_CTRL_SLV_OVERRIDE (1 << 9) -#define SSP_DLL_CTRL_GATE_UPDATE (1 << 7) -#define SSP_DLL_CTRL_SLV_DLY_TARGET_MASK (0xf << 3) -#define SSP_DLL_CTRL_SLV_DLY_TARGET_OFFSET 3 -#define SSP_DLL_CTRL_SLV_FORCE_UPD (1 << 2) -#define SSP_DLL_CTRL_RESET (1 << 1) -#define SSP_DLL_CTRL_ENABLE (1 << 0) - -#define SSP_STATUS_PRESENT (1 << 31) -#define SSP_STATUS_MS_PRESENT (1 << 30) -#define SSP_STATUS_SD_PRESENT (1 << 29) -#define SSP_STATUS_CARD_DETECT (1 << 28) -#define SSP_STATUS_DMABURST (1 << 22) -#define SSP_STATUS_DMASENSE (1 << 21) -#define SSP_STATUS_DMATERM (1 << 20) -#define SSP_STATUS_DMAREQ (1 << 19) -#define SSP_STATUS_DMAEND (1 << 18) -#define SSP_STATUS_SDIO_IRQ (1 << 17) -#define SSP_STATUS_RESP_CRC_ERR (1 << 16) -#define SSP_STATUS_RESP_ERR (1 << 15) -#define SSP_STATUS_RESP_TIMEOUT (1 << 14) -#define SSP_STATUS_DATA_CRC_ERR (1 << 13) -#define SSP_STATUS_TIMEOUT (1 << 12) -#define SSP_STATUS_RECV_TIMEOUT_STAT (1 << 11) -#define SSP_STATUS_CEATA_CCS_ERR (1 << 10) -#define SSP_STATUS_FIFO_OVRFLW (1 << 9) -#define SSP_STATUS_FIFO_FULL (1 << 8) -#define SSP_STATUS_FIFO_EMPTY (1 << 5) -#define SSP_STATUS_FIFO_UNDRFLW (1 << 4) -#define SSP_STATUS_CMD_BUSY (1 << 3) -#define SSP_STATUS_DATA_BUSY (1 << 2) -#define SSP_STATUS_BUSY (1 << 0) - -#define SSP_DLL_STS_REF_SEL_MASK (0x3f << 8) -#define SSP_DLL_STS_REF_SEL_OFFSET 8 -#define SSP_DLL_STS_SLV_SEL_MASK (0x3f << 2) -#define SSP_DLL_STS_SLV_SEL_OFFSET 2 -#define SSP_DLL_STS_REF_LOCK (1 << 1) -#define SSP_DLL_STS_SLV_LOCK (1 << 0) - -#define SSP_DEBUG_DATACRC_ERR_MASK (0xf << 28) -#define SSP_DEBUG_DATACRC_ERR_OFFSET 28 -#define SSP_DEBUG_DATA_STALL (1 << 27) -#define SSP_DEBUG_DAT_SM_MASK (0x7 << 24) -#define SSP_DEBUG_DAT_SM_OFFSET 24 -#define SSP_DEBUG_DAT_SM_DSM_IDLE (0x0 << 24) -#define SSP_DEBUG_DAT_SM_DSM_WORD (0x2 << 24) -#define SSP_DEBUG_DAT_SM_DSM_CRC1 (0x3 << 24) -#define SSP_DEBUG_DAT_SM_DSM_CRC2 (0x4 << 24) -#define SSP_DEBUG_DAT_SM_DSM_END (0x5 << 24) -#define SSP_DEBUG_MSTK_SM_MASK (0xf << 20) -#define SSP_DEBUG_MSTK_SM_OFFSET 20 -#define SSP_DEBUG_MSTK_SM_MSTK_IDLE (0x0 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CKON (0x1 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS1 (0x2 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_TPC (0x3 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS2 (0x4 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_HDSHK (0x5 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS3 (0x6 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_RW (0x7 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CRC1 (0x8 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_CRC2 (0x9 << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_BS0 (0xa << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END1 (0xb << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END2W (0xc << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_END2R (0xd << 20) -#define SSP_DEBUG_MSTK_SM_MSTK_DONE (0xe << 20) -#define SSP_DEBUG_CMD_OE (1 << 19) -#define SSP_DEBUG_DMA_SM_MASK (0x7 << 16) -#define SSP_DEBUG_DMA_SM_OFFSET 16 -#define SSP_DEBUG_DMA_SM_DMA_IDLE (0x0 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DMAREQ (0x1 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DMAACK (0x2 << 16) -#define SSP_DEBUG_DMA_SM_DMA_STALL (0x3 << 16) -#define SSP_DEBUG_DMA_SM_DMA_BUSY (0x4 << 16) -#define SSP_DEBUG_DMA_SM_DMA_DONE (0x5 << 16) -#define SSP_DEBUG_DMA_SM_DMA_COUNT (0x6 << 16) -#define SSP_DEBUG_MMC_SM_MASK (0xf << 12) -#define SSP_DEBUG_MMC_SM_OFFSET 12 -#define SSP_DEBUG_MMC_SM_MMC_IDLE (0x0 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CMD (0x1 << 12) -#define SSP_DEBUG_MMC_SM_MMC_TRC (0x2 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RESP (0x3 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RPRX (0x4 << 12) -#define SSP_DEBUG_MMC_SM_MMC_TX (0x5 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CTOK (0x6 << 12) -#define SSP_DEBUG_MMC_SM_MMC_RX (0x7 << 12) -#define SSP_DEBUG_MMC_SM_MMC_CCS (0x8 << 12) -#define SSP_DEBUG_MMC_SM_MMC_PUP (0x9 << 12) -#define SSP_DEBUG_MMC_SM_MMC_WAIT (0xa << 12) -#define SSP_DEBUG_CMD_SM_MASK (0x3 << 10) -#define SSP_DEBUG_CMD_SM_OFFSET 10 -#define SSP_DEBUG_CMD_SM_CSM_IDLE (0x0 << 10) -#define SSP_DEBUG_CMD_SM_CSM_INDEX (0x1 << 10) -#define SSP_DEBUG_CMD_SM_CSM_ARG (0x2 << 10) -#define SSP_DEBUG_CMD_SM_CSM_CRC (0x3 << 10) -#define SSP_DEBUG_SSP_CMD (1 << 9) -#define SSP_DEBUG_SSP_RESP (1 << 8) -#define SSP_DEBUG_SSP_RXD_MASK 0xff -#define SSP_DEBUG_SSP_RXD_OFFSET 0 - -#define SSP_VERSION_MAJOR_MASK (0xff << 24) -#define SSP_VERSION_MAJOR_OFFSET 24 -#define SSP_VERSION_MINOR_MASK (0xff << 16) -#define SSP_VERSION_MINOR_OFFSET 16 -#define SSP_VERSION_STEP_MASK 0xffff -#define SSP_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_SSP_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h deleted file mode 100644 index 9e19aab..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ /dev/null @@ -1,258 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 TIMROT Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __MX28_REGS_TIMROT_H__ -#define __MX28_REGS_TIMROT_H__ - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_timrot_regs { - mxs_reg_32(hw_timrot_rotctrl) - mxs_reg_32(hw_timrot_rotcount) -#if defined(CONFIG_MX23) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_timcount0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_timcount1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_timcount2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_timcount3) -#elif defined(CONFIG_MX28) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_running_count0) - mxs_reg_32(hw_timrot_fixed_count0) - mxs_reg_32(hw_timrot_match_count0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_running_count1) - mxs_reg_32(hw_timrot_fixed_count1) - mxs_reg_32(hw_timrot_match_count1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_running_count2) - mxs_reg_32(hw_timrot_fixed_count2) - mxs_reg_32(hw_timrot_match_count2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_running_count3) - mxs_reg_32(hw_timrot_fixed_count3) - mxs_reg_32(hw_timrot_match_count3) -#endif - mxs_reg_32(hw_timrot_version) -}; -#endif - -#define TIMROT_ROTCTRL_SFTRST (1 << 31) -#define TIMROT_ROTCTRL_CLKGATE (1 << 30) -#define TIMROT_ROTCTRL_ROTARY_PRESENT (1 << 29) -#define TIMROT_ROTCTRL_TIM3_PRESENT (1 << 28) -#define TIMROT_ROTCTRL_TIM2_PRESENT (1 << 27) -#define TIMROT_ROTCTRL_TIM1_PRESENT (1 << 26) -#define TIMROT_ROTCTRL_TIM0_PRESENT (1 << 25) -#define TIMROT_ROTCTRL_STATE_MASK (0x7 << 22) -#define TIMROT_ROTCTRL_STATE_OFFSET 22 -#define TIMROT_ROTCTRL_DIVIDER_MASK (0x3f << 16) -#define TIMROT_ROTCTRL_DIVIDER_OFFSET 16 -#define TIMROT_ROTCTRL_RELATIVE (1 << 12) -#define TIMROT_ROTCTRL_OVERSAMPLE_MASK (0x3 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_OFFSET 10 -#define TIMROT_ROTCTRL_OVERSAMPLE_8X (0x0 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_4X (0x1 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_2X (0x2 << 10) -#define TIMROT_ROTCTRL_OVERSAMPLE_1X (0x3 << 10) -#define TIMROT_ROTCTRL_POLARITY_B (1 << 9) -#define TIMROT_ROTCTRL_POLARITY_A (1 << 8) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0x7 << 4) -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_B_MASK (0xf << 4) -#endif -#define TIMROT_ROTCTRL_SELECT_B_OFFSET 4 -#define TIMROT_ROTCTRL_SELECT_B_NEVER_TICK (0x0 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM0 (0x1 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM1 (0x2 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM2 (0x3 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM3 (0x4 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM4 (0x5 << 4) -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0x7 << 4) -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_B_PWM5 (0x6 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM6 (0x7 << 4) -#define TIMROT_ROTCTRL_SELECT_B_PWM7 (0x8 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYA (0x9 << 4) -#define TIMROT_ROTCTRL_SELECT_B_ROTARYB (0xa << 4) -#endif -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0x7 -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_A_MASK 0xf -#endif -#define TIMROT_ROTCTRL_SELECT_A_OFFSET 0 -#define TIMROT_ROTCTRL_SELECT_A_NEVER_TICK 0x0 -#define TIMROT_ROTCTRL_SELECT_A_PWM0 0x1 -#define TIMROT_ROTCTRL_SELECT_A_PWM1 0x2 -#define TIMROT_ROTCTRL_SELECT_A_PWM2 0x3 -#define TIMROT_ROTCTRL_SELECT_A_PWM3 0x4 -#define TIMROT_ROTCTRL_SELECT_A_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x6 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0x7 -#elif defined(CONFIG_MX28) -#define TIMROT_ROTCTRL_SELECT_A_PWM5 0x6 -#define TIMROT_ROTCTRL_SELECT_A_PWM6 0x7 -#define TIMROT_ROTCTRL_SELECT_A_PWM7 0x8 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYA 0x9 -#define TIMROT_ROTCTRL_SELECT_A_ROTARYB 0xa -#endif - -#define TIMROT_ROTCOUNT_UPDOWN_MASK 0xffff -#define TIMROT_ROTCOUNT_UPDOWN_OFFSET 0 - -#define TIMROT_TIMCTRLn_IRQ (1 << 15) -#define TIMROT_TIMCTRLn_IRQ_EN (1 << 14) -#if defined(CONFIG_MX28) -#define TIMROT_TIMCTRLn_MATCH_MODE (1 << 11) -#endif -#define TIMROT_TIMCTRLn_POLARITY (1 << 8) -#define TIMROT_TIMCTRLn_UPDATE (1 << 7) -#define TIMROT_TIMCTRLn_RELOAD (1 << 6) -#define TIMROT_TIMCTRLn_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRLn_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRLn_SELECT_MASK 0xf -#define TIMROT_TIMCTRLn_SELECT_OFFSET 0 -#define TIMROT_TIMCTRLn_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRLn_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRLn_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRLn_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRLn_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRLn_SELECT_PWM4 0x5 -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xc -#elif defined(CONFIG_MX28) -#define TIMROT_TIMCTRLn_SELECT_PWM5 0x6 -#define TIMROT_TIMCTRLn_SELECT_PWM6 0x7 -#define TIMROT_TIMCTRLn_SELECT_PWM7 0x8 -#define TIMROT_TIMCTRLn_SELECT_ROTARYA 0x9 -#define TIMROT_TIMCTRLn_SELECT_ROTARYB 0xa -#define TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL 0xb -#define TIMROT_TIMCTRLn_SELECT_8KHZ_XTAL 0xc -#define TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL 0xd -#define TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL 0xe -#define TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS 0xf -#endif - -#if defined(CONFIG_MX23) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 16 -#elif defined(CONFIG_MX28) -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK 0xffffffff -#define TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET 0 -#endif - -#if defined(CONFIG_MX23) -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#elif defined(CONFIG_MX28) -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK 0xffffffff -#define TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET 0 -#endif - -#if defined(CONFIG_MX28) -#define TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK 0xffffffff -#define TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET 0 -#endif - -#define TIMROT_TIMCTRL3_TEST_SIGNAL_MASK (0xf << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_OFFSET 16 -#define TIMROT_TIMCTRL3_TEST_SIGNAL_NEVER_TICK (0x0 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM0 (0x1 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM1 (0x2 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2 (0x3 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3 (0x4 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4 (0x5 << 16) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xc << 16) -#elif defined(CONFIG_MX28) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5 (0x6 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6 (0x7 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7 (0x8 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA (0x9 << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB (0xa << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL (0xb << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_8KHZ_XTAL (0xc << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL (0xd << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL (0xe << 16) -#define TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS (0xf << 16) -#endif -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_IRQ (1 << 15) -#define TIMROT_TIMCTRL3_IRQ_EN (1 << 14) -#define TIMROT_TIMCTRL3_DUTU_VALID (1 << 10) -#endif -#define TIMROT_TIMCTRL3_DUTY_CYCLE (1 << 9) -#if defined(CONFIG_MX23) -#define TIMROT_TIMCTRL3_POLARITY_MASK (0x1 << 8) -#define TIMROT_TIMCTRL3_POLARITY_OFFSET 8 -#define TIMROT_TIMCTRL3_POLARITY_POSITIVE (0x0 << 8) -#define TIMROT_TIMCTRL3_POLARITY_NEGATIVE (0x1 << 8) -#define TIMROT_TIMCTRL3_UPDATE (1 << 7) -#define TIMROT_TIMCTRL3_RELOAD (1 << 6) -#define TIMROT_TIMCTRL3_PRESCALE_MASK (0x3 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_OFFSET 4 -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_1 (0x0 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_2 (0x1 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_4 (0x2 << 4) -#define TIMROT_TIMCTRL3_PRESCALE_DIV_BY_8 (0x3 << 4) -#define TIMROT_TIMCTRL3_SELECT_MASK 0xf -#define TIMROT_TIMCTRL3_SELECT_OFFSET 0 -#define TIMROT_TIMCTRL3_SELECT_NEVER_TICK 0x0 -#define TIMROT_TIMCTRL3_SELECT_PWM0 0x1 -#define TIMROT_TIMCTRL3_SELECT_PWM1 0x2 -#define TIMROT_TIMCTRL3_SELECT_PWM2 0x3 -#define TIMROT_TIMCTRL3_SELECT_PWM3 0x4 -#define TIMROT_TIMCTRL3_SELECT_PWM4 0x5 -#define TIMROT_TIMCTRL3_SELECT_ROTARYA 0x6 -#define TIMROT_TIMCTRL3_SELECT_ROTARYB 0x7 -#define TIMROT_TIMCTRL3_SELECT_32KHZ_XTAL 0x8 -#define TIMROT_TIMCTRL3_SELECT_8KHZ_XTAL 0x9 -#define TIMROT_TIMCTRL3_SELECT_4KHZ_XTAL 0xa -#define TIMROT_TIMCTRL3_SELECT_1KHZ_XTAL 0xb -#define TIMROT_TIMCTRL3_SELECT_TICK_ALWAYS 0xc -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_MASK (0xffff << 16) -#define TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT_OFFSET 16 -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_MASK 0xffff -#define TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT_OFFSET 0 -#endif - -#define TIMROT_VERSION_MAJOR_MASK (0xff << 24) -#define TIMROT_VERSION_MAJOR_OFFSET 24 -#define TIMROT_VERSION_MINOR_MASK (0xff << 16) -#define TIMROT_VERSION_MINOR_OFFSET 16 -#define TIMROT_VERSION_STEP_MASK 0xffff -#define TIMROT_VERSION_STEP_OFFSET 0 - -#endif /* __MX28_REGS_TIMROT_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h deleted file mode 100644 index d89cf27..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-uartapp.h +++ /dev/null @@ -1,219 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale MXS UARTAPP Register Definitions - * - * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ARCH_ARM___MXS_UARTAPP_H -#define __ARCH_ARM___MXS_UARTAPP_H - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_uartapp_regs { - mxs_reg_32(hw_uartapp_ctrl0) - mxs_reg_32(hw_uartapp_ctrl1) - mxs_reg_32(hw_uartapp_ctrl2) - mxs_reg_32(hw_uartapp_linectrl) - mxs_reg_32(hw_uartapp_linectrl2) - mxs_reg_32(hw_uartapp_intr) - mxs_reg_32(hw_uartapp_data) - mxs_reg_32(hw_uartapp_stat) - mxs_reg_32(hw_uartapp_debug) - mxs_reg_32(hw_uartapp_version) - mxs_reg_32(hw_uartapp_autobaud) -}; -#endif - -#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) -#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) -#define UARTAPP_CTRL0_RUN_MASK (1 << 29) -#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) -#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) -#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 -#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) -#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL1_RUN_MASK (1 << 28) - -#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) -#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) -#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) -#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) -#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) -#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) -#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) -#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) -#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 -#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) - -#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) -#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 -#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) -#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) -#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) -#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) -#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) -#define UARTAPP_CTRL2_RTS_MASK (1 << 11) -#define UARTAPP_CTRL2_DTR_MASK (1 << 10) -#define UARTAPP_CTRL2_RXE_MASK (1 << 9) -#define UARTAPP_CTRL2_TXE_MASK (1 << 8) -#define UARTAPP_CTRL2_LBE_MASK (1 << 7) -#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) - -#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) -#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) -#define UARTAPP_CTRL2_UARTEN_MASK 0x01 - -#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) -#define UARTAPP_LINECTRL_BRK_MASK 1 - -#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) - -#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) -#define UARTAPP_INTR_OEIEN_MASK (1 << 26) -#define UARTAPP_INTR_BEIEN_MASK (1 << 25) -#define UARTAPP_INTR_PEIEN_MASK (1 << 24) -#define UARTAPP_INTR_FEIEN_MASK (1 << 23) -#define UARTAPP_INTR_RTIEN_MASK (1 << 22) -#define UARTAPP_INTR_TXIEN_MASK (1 << 21) -#define UARTAPP_INTR_RXIEN_MASK (1 << 20) -#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) -#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) -#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) -#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) - -#define UARTAPP_INTR_ABDIS_MASK (1 << 11) -#define UARTAPP_INTR_OEIS_MASK (1 << 10) -#define UARTAPP_INTR_BEIS_MASK (1 << 9) -#define UARTAPP_INTR_PEIS_MASK (1 << 8) -#define UARTAPP_INTR_FEIS_MASK (1 << 7) -#define UARTAPP_INTR_RTIS_MASK (1 << 6) -#define UARTAPP_INTR_TXIS_MASK (1 << 5) -#define UARTAPP_INTR_RXIS_MASK (1 << 4) -#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) -#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) -#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) -#define UARTAPP_INTR_RIMIS_MASK 0x1 - -#define UARTAPP_DATA_DATA_OFFSET 0 -#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF -#define UARTAPP_STAT_PRESENT_MASK (1 << 31) -#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) -#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) - -#define UARTAPP_STAT_HISPEED_MASK (1 << 30) -#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) -#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) - -#define UARTAPP_STAT_BUSY_MASK (1 << 29) -#define UARTAPP_STAT_CTS_MASK (1 << 28) -#define UARTAPP_STAT_TXFE_MASK (1 << 27) -#define UARTAPP_STAT_RXFF_MASK (1 << 26) -#define UARTAPP_STAT_TXFF_MASK (1 << 25) -#define UARTAPP_STAT_RXFE_MASK (1 << 24) -#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 -#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) - -#define UARTAPP_STAT_OERR_MASK (1 << 19) -#define UARTAPP_STAT_BERR_MASK (1 << 18) -#define UARTAPP_STAT_PERR_MASK (1 << 17) -#define UARTAPP_STAT_FERR_MASK (1 << 16) -#define UARTAPP_STAT_RXCOUNT_OFFSET 0 -#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF - -#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 -#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) - -#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 -#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) - -#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) -#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) -#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) -#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) -#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) -#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 - -#define UARTAPP_VERSION_MAJOR_OFFSET 24 -#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) - -#define UARTAPP_VERSION_MINOR_OFFSET 16 -#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) - -#define UARTAPP_VERSION_STEP_OFFSET 0 -#define UARTAPP_VERSION_STEP_MASK 0xFFFF - -#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 -#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) - -#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 -#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) - -#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) -#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) -#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) -#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) -#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 -#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/arch/arm/include/asm/arch-mxs/regs-usb.h b/arch/arm/include/asm/arch-mxs/regs-usb.h deleted file mode 100644 index 8d5168d..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-usb.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 USB OTG Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __REGS_USB_H__ -#define __REGS_USB_H__ - -struct mxs_usb_regs { - uint32_t hw_usbctrl_id; /* 0x000 */ - uint32_t hw_usbctrl_hwgeneral; /* 0x004 */ - uint32_t hw_usbctrl_hwhost; /* 0x008 */ - uint32_t hw_usbctrl_hwdevice; /* 0x00c */ - uint32_t hw_usbctrl_hwtxbuf; /* 0x010 */ - uint32_t hw_usbctrl_hwrxbuf; /* 0x014 */ - - uint32_t reserved1[26]; - - uint32_t hw_usbctrl_gptimer0ld; /* 0x080 */ - uint32_t hw_usbctrl_gptimer0ctrl; /* 0x084 */ - uint32_t hw_usbctrl_gptimer1ld; /* 0x088 */ - uint32_t hw_usbctrl_gptimer1ctrl; /* 0x08c */ - uint32_t hw_usbctrl_sbuscfg; /* 0x090 */ - - uint32_t reserved2[27]; - - uint32_t hw_usbctrl_caplength; /* 0x100 */ - uint32_t hw_usbctrl_hcsparams; /* 0x104 */ - uint32_t hw_usbctrl_hccparams; /* 0x108 */ - - uint32_t reserved3[5]; - - uint32_t hw_usbctrl_dciversion; /* 0x120 */ - uint32_t hw_usbctrl_dccparams; /* 0x124 */ - - uint32_t reserved4[6]; - - uint32_t hw_usbctrl_usbcmd; /* 0x140 */ - uint32_t hw_usbctrl_usbsts; /* 0x144 */ - uint32_t hw_usbctrl_usbintr; /* 0x148 */ - uint32_t hw_usbctrl_frindex; /* 0x14c */ - - uint32_t reserved5; - - union { - uint32_t hw_usbctrl_periodiclistbase; /* 0x154 */ - uint32_t hw_usbctrl_deviceaddr; /* 0x154 */ - }; - union { - uint32_t hw_usbctrl_asynclistaddr; /* 0x158 */ - uint32_t hw_usbctrl_endpointlistaddr; /* 0x158 */ - }; - - uint32_t hw_usbctrl_ttctrl; /* 0x15c */ - uint32_t hw_usbctrl_burstsize; /* 0x160 */ - uint32_t hw_usbctrl_txfilltuning; /* 0x164 */ - - uint32_t reserved6; - - uint32_t hw_usbctrl_ic_usb; /* 0x16c */ - uint32_t hw_usbctrl_ulpi; /* 0x170 */ - - uint32_t reserved7; - - uint32_t hw_usbctrl_endptnak; /* 0x178 */ - uint32_t hw_usbctrl_endptnaken; /* 0x17c */ - - uint32_t reserved8; - - uint32_t hw_usbctrl_portsc1; /* 0x184 */ - - uint32_t reserved9[7]; - - uint32_t hw_usbctrl_otgsc; /* 0x1a4 */ - uint32_t hw_usbctrl_usbmode; /* 0x1a8 */ - uint32_t hw_usbctrl_endptsetupstat; /* 0x1ac */ - uint32_t hw_usbctrl_endptprime; /* 0x1b0 */ - uint32_t hw_usbctrl_endptflush; /* 0x1b4 */ - uint32_t hw_usbctrl_endptstat; /* 0x1b8 */ - uint32_t hw_usbctrl_endptcomplete; /* 0x1bc */ - uint32_t hw_usbctrl_endptctrl0; /* 0x1c0 */ - uint32_t hw_usbctrl_endptctrl1; /* 0x1c4 */ - uint32_t hw_usbctrl_endptctrl2; /* 0x1c8 */ - uint32_t hw_usbctrl_endptctrl3; /* 0x1cc */ - uint32_t hw_usbctrl_endptctrl4; /* 0x1d0 */ - uint32_t hw_usbctrl_endptctrl5; /* 0x1d4 */ - uint32_t hw_usbctrl_endptctrl6; /* 0x1d8 */ - uint32_t hw_usbctrl_endptctrl7; /* 0x1dc */ -}; - -#define CLKCTRL_PLL0CTRL0_LFR_SEL_MASK (0x3 << 28) - -#define HW_USBCTRL_ID_CIVERSION_OFFSET 29 -#define HW_USBCTRL_ID_CIVERSION_MASK (0x7 << 29) -#define HW_USBCTRL_ID_VERSION_OFFSET 25 -#define HW_USBCTRL_ID_VERSION_MASK (0xf << 25) -#define HW_USBCTRL_ID_REVISION_OFFSET 21 -#define HW_USBCTRL_ID_REVISION_MASK (0xf << 21) -#define HW_USBCTRL_ID_TAG_OFFSET 16 -#define HW_USBCTRL_ID_TAG_MASK (0x1f << 16) -#define HW_USBCTRL_ID_NID_OFFSET 8 -#define HW_USBCTRL_ID_NID_MASK (0x3f << 8) -#define HW_USBCTRL_ID_ID_OFFSET 0 -#define HW_USBCTRL_ID_ID_MASK (0x3f << 0) - -#define HW_USBCTRL_HWGENERAL_SM_OFFSET 9 -#define HW_USBCTRL_HWGENERAL_SM_MASK (0x3 << 9) -#define HW_USBCTRL_HWGENERAL_PHYM_OFFSET 6 -#define HW_USBCTRL_HWGENERAL_PHYM_MASK (0x7 << 6) -#define HW_USBCTRL_HWGENERAL_PHYW_OFFSET 4 -#define HW_USBCTRL_HWGENERAL_PHYW_MASK (0x3 << 4) -#define HW_USBCTRL_HWGENERAL_BWT (1 << 3) -#define HW_USBCTRL_HWGENERAL_CLKC_OFFSET 1 -#define HW_USBCTRL_HWGENERAL_CLKC_MASK (0x3 << 1) -#define HW_USBCTRL_HWGENERAL_RT (1 << 0) - -#define HW_USBCTRL_HWHOST_TTPER_OFFSET 24 -#define HW_USBCTRL_HWHOST_TTPER_MASK (0xff << 24) -#define HW_USBCTRL_HWHOST_TTASY_OFFSET 16 -#define HW_USBCTRL_HWHOST_TTASY_MASK (0xff << 19) -#define HW_USBCTRL_HWHOST_NPORT_OFFSET 1 -#define HW_USBCTRL_HWHOST_NPORT_MASK (0x7 << 1) -#define HW_USBCTRL_HWHOST_HC (1 << 0) - -#define HW_USBCTRL_HWDEVICE_DEVEP_OFFSET 1 -#define HW_USBCTRL_HWDEVICE_DEVEP_MASK (0x1f << 1) -#define HW_USBCTRL_HWDEVICE_DC (1 << 0) - -#define HW_USBCTRL_HWTXBUF_TXLCR (1 << 31) -#define HW_USBCTRL_HWTXBUF_TXCHANADD_OFFSET 16 -#define HW_USBCTRL_HWTXBUF_TXCHANADD_MASK (0xff << 16) -#define HW_USBCTRL_HWTXBUF_TXADD_OFFSET 8 -#define HW_USBCTRL_HWTXBUF_TXADD_MASK (0xff << 8) -#define HW_USBCTRL_HWTXBUF_TXBURST_OFFSET 0 -#define HW_USBCTRL_HWTXBUF_TXBURST_MASK 0xff - -#define HW_USBCTRL_HWRXBUF_RXADD_OFFSET 8 -#define HW_USBCTRL_HWRXBUF_RXADD_MASK (0xff << 8) -#define HW_USBCTRL_HWRXBUF_RXBURST_OFFSET 0 -#define HW_USBCTRL_HWRXBUF_RXBURST_MASK 0xff - -#define HW_USBCTRL_GPTIMERLD_GPTLD_OFFSET 0 -#define HW_USBCTRL_GPTIMERLD_GPTLD_MASK 0xffffff - -#define HW_USBCTRL_GPTIMERCTRL_GPTRUN (1 << 31) -#define HW_USBCTRL_GPTIMERCTRL_GPTRST (1 << 30) -#define HW_USBCTRL_GPTIMERCTRL_GPTMODE (1 << 24) -#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_OFFSET 0 -#define HW_USBCTRL_GPTIMERCTRL_GPTCNT_MASK 0xffffff - -#define HW_USBCTRL_SBUSCFG_AHBBURST_OFFSET 0 -#define HW_USBCTRL_SBUSCFG_AHBBURST_MASK 0x7 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR 0x0 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR4 0x1 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR8 0x2 -#define HW_USBCTRL_SBUSCFG_AHBBURST_S_INCR16 0x3 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR4 0x5 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR8 0x6 -#define HW_USBCTRL_SBUSCFG_AHBBURST_U_INCR16 0x7 - -#endif /* __REGS_USB_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/arch/arm/include/asm/arch-mxs/regs-usbphy.h deleted file mode 100644 index 643feab..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-usbphy.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX28 USB PHY Register Definitions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __REGS_USBPHY_H__ -#define __REGS_USBPHY_H__ - -struct mxs_usbphy_regs { - mxs_reg_32(hw_usbphy_pwd) - mxs_reg_32(hw_usbphy_tx) - mxs_reg_32(hw_usbphy_rx) - mxs_reg_32(hw_usbphy_ctrl) - mxs_reg_32(hw_usbphy_status) - mxs_reg_32(hw_usbphy_debug) - mxs_reg_32(hw_usbphy_debug0_status) - mxs_reg_32(hw_usbphy_debug1) - mxs_reg_32(hw_usbphy_version) - mxs_reg_32(hw_usbphy_ip) -}; - -#define USBPHY_PWD_RXPWDRX (1 << 20) -#define USBPHY_PWD_RXPWDDIFF (1 << 19) -#define USBPHY_PWD_RXPWD1PT1 (1 << 18) -#define USBPHY_PWD_RXPWDENV (1 << 17) -#define USBPHY_PWD_TXPWDV2I (1 << 12) -#define USBPHY_PWD_TXPWDIBIAS (1 << 11) -#define USBPHY_PWD_TXPWDFS (1 << 10) - -#define USBPHY_TX_USBPHY_TX_EDGECTRL_OFFSET 26 -#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x7 << 26) -#define USBPHY_TX_USBPHY_TX_SYNC_INVERT (1 << 25) -#define USBPHY_TX_USBPHY_TX_SYNC_MUX (1 << 24) -#define USBPHY_TX_TXENCAL45DP (1 << 21) -#define USBPHY_TX_TXCAL45DP_OFFSET 16 -#define USBPHY_TX_TXCAL45DP_MASK (0xf << 16) -#define USBPHY_TX_TXENCAL45DM (1 << 13) -#define USBPHY_TX_TXCAL45DM_OFFSET 8 -#define USBPHY_TX_TXCAL45DM_MASK (0xf << 8) -#define USBPHY_TX_D_CAL_OFFSET 0 -#define USBPHY_TX_D_CAL_MASK 0xf - -#define USBPHY_RX_RXDBYPASS (1 << 22) -#define USBPHY_RX_DISCONADJ_OFFSET 4 -#define USBPHY_RX_DISCONADJ_MASK (0x7 << 4) -#define USBPHY_RX_ENVADJ_OFFSET 0 -#define USBPHY_RX_ENVADJ_MASK 0x7 - -#define USBPHY_CTRL_SFTRST (1 << 31) -#define USBPHY_CTRL_CLKGATE (1 << 30) -#define USBPHY_CTRL_UTMI_SUSPENDM (1 << 29) -#define USBPHY_CTRL_HOST_FORCE_LS_SE0 (1 << 28) -#define USBPHY_CTRL_ENAUTOSET_USBCLKS (1 << 26) -#define USBPHY_CTRL_ENAUTOCLR_USBCLKGATE (1 << 25) -#define USBPHY_CTRL_FSDLL_RST_EN (1 << 24) -#define USBPHY_CTRL_ENVBUSCHG_WKUP (1 << 23) -#define USBPHY_CTRL_ENIDCHG_WKUP (1 << 22) -#define USBPHY_CTRL_ENDPDMCHG_WKUP (1 << 21) -#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD (1 << 20) -#define USBPHY_CTRL_ENAUTOCLR_CLKGATE (1 << 19) -#define USBPHY_CTRL_ENAUTO_PWRON_PLL (1 << 18) -#define USBPHY_CTRL_WAKEUP_IRQ (1 << 17) -#define USBPHY_CTRL_ENIRQWAKEUP (1 << 16) -#define USBPHY_CTRL_ENUTMILEVEL3 (1 << 15) -#define USBPHY_CTRL_ENUTMILEVEL2 (1 << 14) -#define USBPHY_CTRL_DATA_ON_LRADC (1 << 13) -#define USBPHY_CTRL_DEVPLUGIN_IRQ (1 << 12) -#define USBPHY_CTRL_ENIRQDEVPLUGIN (1 << 11) -#define USBPHY_CTRL_RESUME_IRQ (1 << 10) -#define USBPHY_CTRL_ENIRQRESUMEDETECT (1 << 9) -#define USBPHY_CTRL_RESUMEIRQSTICKY (1 << 8) -#define USBPHY_CTRL_ENOTGIDDETECT (1 << 7) -#define USBPHY_CTRL_DEVPLUGIN_POLARITY (1 << 5) -#define USBPHY_CTRL_ENDEVPLUGINDETECT (1 << 4) -#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ (1 << 3) -#define USBPHY_CTRL_ENIRQHOSTDISCON (1 << 2) -#define USBPHY_CTRL_ENHOSTDISCONDETECT (1 << 1) - -#define USBPHY_STATUS_RESUME_STATUS (1 << 10) -#define USBPHY_STATUS_OTGID_STATUS (1 << 8) -#define USBPHY_STATUS_DEVPLUGIN_STATUS (1 << 6) -#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS (1 << 3) - -#define USBPHY_DEBUG_CLKGATE (1 << 30) -#define USBPHY_DEBUG_HOST_RESUME_DEBUG (1 << 29) -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_OFFSET 25 -#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0xf << 25) -#define USBPHY_DEBUG_ENSQUELCHRESET (1 << 24) -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_OFFSET 16 -#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1f << 16) -#define USBPHY_DEBUG_ENTX2RXCOUNT (1 << 12) -#define USBPHY_DEBUG_TX2RXCOUNT_OFFSET 8 -#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xf << 8) -#define USBPHY_DEBUG_ENHSTPULLDOWN_OFFSET 4 -#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x3 << 4) -#define USBPHY_DEBUG_HSTPULLDOWN_OFFSET 2 -#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0x3 << 2) -#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD (1 << 1) -#define USBPHY_DEBUG_OTGIDPIDLOCK (1 << 0) - -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_OFFSET 26 -#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0x3f << 26) -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_OFFSET 16 -#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_MASK (0x3ff << 16) -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_OFFSET 0 -#define USBPHY_DEBUG0_STATUS_LOOP_BACK_MASK 0xffff - -#define USBPHY_DEBUG1_ENTAILADJVD_OFFSET 13 -#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x3 << 13) -#define USBPHY_DEBUG1_ENTX2TX (1 << 12) -#define USBPHY_DEBUG1_DBG_ADDRESS_OFFSET 0 -#define USBPHY_DEBUG1_DBG_ADDRESS_MASK 0xf - -#define USBPHY_VERSION_MAJOR_MASK (0xff << 24) -#define USBPHY_VERSION_MAJOR_OFFSET 24 -#define USBPHY_VERSION_MINOR_MASK (0xff << 16) -#define USBPHY_VERSION_MINOR_OFFSET 16 -#define USBPHY_VERSION_STEP_MASK 0xffff -#define USBPHY_VERSION_STEP_OFFSET 0 - -#define USBPHY_IP_DIV_SEL_OFFSET 23 -#define USBPHY_IP_DIV_SEL_MASK (0x3 << 23) -#define USBPHY_IP_LFR_SEL_OFFSET 21 -#define USBPHY_IP_LFR_SEL_MASK (0x3 << 21) -#define USBPHY_IP_CP_SEL_OFFSET 19 -#define USBPHY_IP_CP_SEL_MASK (0x3 << 19) -#define USBPHY_IP_TSTI_TX_DP (1 << 18) -#define USBPHY_IP_TSTI_TX_DM (1 << 17) -#define USBPHY_IP_ANALOG_TESTMODE (1 << 16) -#define USBPHY_IP_EN_USB_CLKS (1 << 2) -#define USBPHY_IP_PLL_LOCKED (1 << 1) -#define USBPHY_IP_PLL_POWER (1 << 0) - -#endif /* __REGS_USBPHY_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h deleted file mode 100644 index 6478692..0000000 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23/i.MX28 specific functions - * - * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> - * on behalf of DENX Software Engineering GmbH - */ - -#ifndef __MXS_SYS_PROTO_H__ -#define __MXS_SYS_PROTO_H__ - -#include <asm/mach-imx/sys_proto.h> - -int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); - -#ifdef CONFIG_SPL_BUILD - -#if defined(CONFIG_MX23) -#include <asm/arch/iomux-mx23.h> -#elif defined(CONFIG_MX28) -#include <asm/arch/iomux-mx28.h> -#endif - -void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr, - const iomux_cfg_t *iomux_setup, - const unsigned int iomux_size); - -void mxs_power_switch_dcdc_clocksource(uint32_t freqsel); -#endif - -struct mxs_pair { - uint8_t boot_pads; - uint8_t boot_mask; - const char *mode; -}; - -static const struct mxs_pair mxs_boot_modes[] = { -#if defined(CONFIG_MX23) - { 0x00, 0x0f, "USB" }, - { 0x01, 0x1f, "I2C, master" }, - { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, - { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, - { 0x04, 0x1f, "NAND" }, - { 0x06, 0x1f, "JTAG" }, - { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, - { 0x09, 0x1f, "SSP SD/MMC #0" }, - { 0x0a, 0x1f, "SSP SD/MMC #1" }, - { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -#elif defined(CONFIG_MX28) - { 0x00, 0x0f, "USB #0" }, - { 0x01, 0x1f, "I2C #0, master, 3V3" }, - { 0x11, 0x1f, "I2C #0, master, 1V8" }, - { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" }, - { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" }, - { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" }, - { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, - { 0x04, 0x1f, "NAND, 3V3" }, - { 0x14, 0x1f, "NAND, 1V8" }, - { 0x06, 0x1f, "JTAG" }, - { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, - { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, - { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, - { 0x19, 0x1f, "SSP SD/MMC #0, 1V8" }, - { 0x0a, 0x1f, "SSP SD/MMC #1, 3V3" }, - { 0x1a, 0x1f, "SSP SD/MMC #1, 1V8" }, - { 0x00, 0x00, "Reserved/Unknown/Wrong" }, -#endif -}; - -#define MXS_BM_USB 0x00 -#define MXS_BM_I2C_MASTER_3V3 0x01 -#define MXS_BM_I2C_MASTER_1V8 0x11 -#define MXS_BM_SPI2_MASTER_3V3_NOR 0x02 -#define MXS_BM_SPI2_MASTER_1V8_NOR 0x12 -#define MXS_BM_SPI3_MASTER_3V3_NOR 0x03 -#define MXS_BM_SPI3_MASTER_1V8_NOR 0x13 -#define MXS_BM_NAND_3V3 0x04 -#define MXS_BM_NAND_1V8 0x14 -#define MXS_BM_JTAG 0x06 -#define MXS_BM_SPI3_MASTER_3V3_EEPROM 0x08 -#define MXS_BM_SPI3_MASTER_1V8_EEPROM 0x18 -#define MXS_BM_SDMMC0_3V3 0x09 -#define MXS_BM_SDMMC0_1V8 0x19 -#define MXS_BM_SDMMC1_3V3 0x0a -#define MXS_BM_SDMMC1_1V8 0x1a - -#define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200)) - -struct mxs_spl_data { - uint8_t boot_mode_idx; - uint32_t mem_dram_size; -}; - -int mxs_dram_init(void); - -#endif /* __SYS_PROTO_H__ */ |