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-rw-r--r--arch/arm/include/asm/arch-omap5/clock.h417
-rw-r--r--arch/arm/include/asm/arch-omap5/cpu.h133
-rw-r--r--arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h93
-rw-r--r--arch/arm/include/asm/arch-omap5/ehci.h29
-rw-r--r--arch/arm/include/asm/arch-omap5/gpio.h40
-rw-r--r--arch/arm/include/asm/arch-omap5/hardware.h30
-rw-r--r--arch/arm/include/asm/arch-omap5/i2c.h11
-rw-r--r--arch/arm/include/asm/arch-omap5/mem.h61
-rw-r--r--arch/arm/include/asm/arch-omap5/mmc_host_def.h38
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_dra7xx.h356
-rw-r--r--arch/arm/include/asm/arch-omap5/mux_omap5.h317
-rw-r--r--arch/arm/include/asm/arch-omap5/omap.h271
-rw-r--r--arch/arm/include/asm/arch-omap5/sata.h38
-rw-r--r--arch/arm/include/asm/arch-omap5/spl.h26
-rw-r--r--arch/arm/include/asm/arch-omap5/sys_proto.h92
15 files changed, 0 insertions, 1952 deletions
diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
deleted file mode 100644
index e261bd4..0000000
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ /dev/null
@@ -1,417 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- * Sricharan R <r.sricharan@ti.com>
- */
-#ifndef _CLOCKS_OMAP5_H_
-#define _CLOCKS_OMAP5_H_
-#include <common.h>
-#include <asm/omap_common.h>
-
-/*
- * Assuming a maximum of 1.5 GHz ARM speed and a minimum of 2 cycles per
- * loop, allow for a minimum of 2 ms wait (in reality the wait will be
- * much more than that)
- */
-#define LDELAY 1000000
-
-/* CM_DLL_CTRL */
-#define CM_DLL_CTRL_OVERRIDE_SHIFT 0
-#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0)
-#define CM_DLL_CTRL_NO_OVERRIDE 0
-
-/* CM_CLKMODE_DPLL */
-#define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11
-#define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
-#define CM_CLKMODE_DPLL_LPMODE_EN_SHIFT 10
-#define CM_CLKMODE_DPLL_LPMODE_EN_MASK (1 << 10)
-#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_SHIFT 9
-#define CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK (1 << 9)
-#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_SHIFT 8
-#define CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
-#define CM_CLKMODE_DPLL_RAMP_RATE_SHIFT 5
-#define CM_CLKMODE_DPLL_RAMP_RATE_MASK (0x7 << 5)
-#define CM_CLKMODE_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_EN_MASK (0x7 << 0)
-
-#define CM_CLKMODE_DPLL_DPLL_EN_SHIFT 0
-#define CM_CLKMODE_DPLL_DPLL_EN_MASK 7
-
-#define DPLL_EN_STOP 1
-#define DPLL_EN_MN_BYPASS 4
-#define DPLL_EN_LOW_POWER_BYPASS 5
-#define DPLL_EN_FAST_RELOCK_BYPASS 6
-#define DPLL_EN_LOCK 7
-
-/* CM_IDLEST_DPLL fields */
-#define ST_DPLL_CLK_MASK 1
-
-/* SGX */
-#define CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
-#define CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
-
-/* CM_CLKSEL_DPLL */
-#define CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT 24
-#define CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK (0xFF << 24)
-#define CM_CLKSEL_DPLL_M_SHIFT 8
-#define CM_CLKSEL_DPLL_M_MASK (0x7FF << 8)
-#define CM_CLKSEL_DPLL_N_SHIFT 0
-#define CM_CLKSEL_DPLL_N_MASK 0x7F
-#define CM_CLKSEL_DCC_EN_SHIFT 22
-#define CM_CLKSEL_DCC_EN_MASK (1 << 22)
-
-/* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK 7
-
-/* CM_CLKSEL_CORE */
-#define CLKSEL_CORE_SHIFT 0
-#define CLKSEL_L3_SHIFT 4
-#define CLKSEL_L4_SHIFT 8
-
-#define CLKSEL_CORE_X2_DIV_1 0
-#define CLKSEL_L3_CORE_DIV_2 1
-#define CLKSEL_L4_L3_DIV_2 1
-
-/* CM_ABE_PLL_REF_CLKSEL */
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT 0
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK 1
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK 0
-#define CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK 1
-
-/* CM_CLKSEL_ABE_PLL_SYS */
-#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_SHIFT 0
-#define CM_CLKSEL_ABE_PLL_SYS_CLKSEL_MASK 1
-#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK1 0
-#define CM_ABE_PLL_SYS_CLKSEL_SYSCLK2 1
-
-/* CM_BYPCLK_DPLL_IVA */
-#define CM_BYPCLK_DPLL_IVA_CLKSEL_SHIFT 0
-#define CM_BYPCLK_DPLL_IVA_CLKSEL_MASK 3
-
-#define DPLL_IVA_CLKSEL_CORE_X2_DIV_2 1
-
-/* CM_SHADOW_FREQ_CONFIG1 */
-#define SHADOW_FREQ_CONFIG1_FREQ_UPDATE_MASK 1
-#define SHADOW_FREQ_CONFIG1_DLL_OVERRIDE_MASK 4
-#define SHADOW_FREQ_CONFIG1_DLL_RESET_MASK 8
-
-#define SHADOW_FREQ_CONFIG1_DPLL_EN_SHIFT 8
-#define SHADOW_FREQ_CONFIG1_DPLL_EN_MASK (7 << 8)
-
-#define SHADOW_FREQ_CONFIG1_M2_DIV_SHIFT 11
-#define SHADOW_FREQ_CONFIG1_M2_DIV_MASK (0x1F << 11)
-
-/*CM_<clock_domain>__CLKCTRL */
-#define CD_CLKCTRL_CLKTRCTRL_SHIFT 0
-#define CD_CLKCTRL_CLKTRCTRL_MASK 3
-
-#define CD_CLKCTRL_CLKTRCTRL_NO_SLEEP 0
-#define CD_CLKCTRL_CLKTRCTRL_SW_SLEEP 1
-#define CD_CLKCTRL_CLKTRCTRL_SW_WKUP 2
-#define CD_CLKCTRL_CLKTRCTRL_HW_AUTO 3
-
-
-/* CM_<clock_domain>_<module>_CLKCTRL */
-#define MODULE_CLKCTRL_MODULEMODE_SHIFT 0
-#define MODULE_CLKCTRL_MODULEMODE_MASK 3
-#define MODULE_CLKCTRL_IDLEST_SHIFT 16
-#define MODULE_CLKCTRL_IDLEST_MASK (3 << 16)
-
-#define MODULE_CLKCTRL_MODULEMODE_SW_DISABLE 0
-#define MODULE_CLKCTRL_MODULEMODE_HW_AUTO 1
-#define MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN 2
-
-#define MODULE_CLKCTRL_IDLEST_FULLY_FUNCTIONAL 0
-#define MODULE_CLKCTRL_IDLEST_TRANSITIONING 1
-#define MODULE_CLKCTRL_IDLEST_IDLE 2
-#define MODULE_CLKCTRL_IDLEST_DISABLED 3
-
-/* CM_L4PER_GPIO4_CLKCTRL */
-#define GPIO4_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-
-/* CM_L3INIT_HSMMCn_CLKCTRL */
-#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
-#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (3 << 25)
-
-/* CM_L3INIT_SATA_CLKCTRL */
-#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-
-/* CM_WKUP_GPTIMER1_CLKCTRL */
-#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
-
-/* CM_CAM_ISS_CLKCTRL */
-#define ISS_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
-
-/* CM_DSS_DSS_CLKCTRL */
-#define DSS_CLKCTRL_OPTFCLKEN_MASK 0xF00
-
-/* CM_L3INIT_USBPHY_CLKCTRL */
-#define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK 8
-
-/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
-#define OPTFCLKEN_FUNC48M_CLK (1 << 15)
-#define OPTFCLKEN_HSIC480M_P2_CLK (1 << 14)
-#define OPTFCLKEN_HSIC480M_P1_CLK (1 << 13)
-#define OPTFCLKEN_HSIC60M_P2_CLK (1 << 12)
-#define OPTFCLKEN_HSIC60M_P1_CLK (1 << 11)
-#define OPTFCLKEN_UTMI_P3_CLK (1 << 10)
-#define OPTFCLKEN_UTMI_P2_CLK (1 << 9)
-#define OPTFCLKEN_UTMI_P1_CLK (1 << 8)
-#define OPTFCLKEN_HSIC480M_P3_CLK (1 << 7)
-#define OPTFCLKEN_HSIC60M_P3_CLK (1 << 6)
-
-/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
-#define OPTFCLKEN_USB_CH0_CLK_ENABLE (1 << 8)
-#define OPTFCLKEN_USB_CH1_CLK_ENABLE (1 << 9)
-#define OPTFCLKEN_USB_CH2_CLK_ENABLE (1 << 10)
-
-/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
-#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K (1 << 8)
-
-/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
-#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK (1 << 8)
-
-/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
-#define OTG_SS_CLKCTRL_MODULEMODE_HW (1 << 0)
-#define OPTFCLKEN_REFCLK960M (1 << 8)
-
-/* CM_L3INIT_OCP2SCP1_CLKCTRL */
-#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0)
-
-/* CM_MPU_MPU_CLKCTRL */
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK (3 << 24)
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT 26
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
-
-/* CM_WKUPAON_SCRM_CLKCTRL */
-#define OPTFCLKEN_SCRM_PER_SHIFT 9
-#define OPTFCLKEN_SCRM_PER_MASK (1 << 9)
-#define OPTFCLKEN_SCRM_CORE_SHIFT 8
-#define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
-
-/* CM_COREAON_IO_SRCOMP_CLKCTRL */
-#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8
-#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8)
-
-/* PRM_RSTTIME */
-#define RSTTIME1_SHIFT 0
-#define RSTTIME1_MASK (0x3ff << 0)
-
-/* Clock frequencies */
-#define OMAP_SYS_CLK_IND_38_4_MHZ 6
-
-/* PRM_VC_VAL_BYPASS */
-#define PRM_VC_I2C_CHANNEL_FREQ_KHZ 400
-
-/* CTRL_CORE_SRCOMP_NORTH_SIDE */
-#define USB2PHY_DISCHGDET (1 << 29)
-#define USB2PHY_AUTORESUME_EN (1 << 30)
-
-/* SMPS */
-#define SMPS_I2C_SLAVE_ADDR 0x12
-#define SMPS_REG_ADDR_12_MPU 0x23
-#define SMPS_REG_ADDR_45_IVA 0x2B
-#define SMPS_REG_ADDR_8_CORE 0x37
-
-/* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
-/* ES1.0 settings */
-#define VDD_MPU 1040
-#define VDD_MM 1040
-#define VDD_CORE 1040
-
-#define VDD_MPU_LOW 890
-#define VDD_MM_LOW 890
-#define VDD_CORE_LOW 890
-
-/* ES2.0 settings */
-#define VDD_MPU_ES2 1060
-#define VDD_MM_ES2 1025
-#define VDD_CORE_ES2 1040
-
-#define VDD_MPU_ES2_HIGH 1250
-#define VDD_MM_ES2_OD 1120
-
-/* Efuse register offsets for OMAP5 platform */
-#define OMAP5_ES2_EFUSE_BASE 0x4A002000
-#define OMAP5_ES2_PROD_REGBITS 16
-
-/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */
-#define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8)
-
-/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */
-#define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4)
-/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */
-#define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8)
-/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */
-#define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4)
-/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */
-#define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8)
-
-/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
-#define VDD_MPU_DRA7_NOM 1150
-#define VDD_CORE_DRA7_NOM 1150
-#define VDD_EVE_DRA7_NOM 1060
-#define VDD_GPU_DRA7_NOM 1060
-#define VDD_IVA_DRA7_NOM 1060
-
-/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
-#define VDD_EVE_DRA7_OD 1150
-#define VDD_GPU_DRA7_OD 1150
-#define VDD_IVA_DRA7_OD 1150
-
-/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
-#define VDD_EVE_DRA7_HIGH 1250
-#define VDD_GPU_DRA7_HIGH 1250
-#define VDD_IVA_DRA7_HIGH 1250
-
-/* Efuse register offsets for DRA7xx platform */
-#define DRA752_EFUSE_BASE 0x4A002000
-#define DRA752_EFUSE_REGBITS 16
-/* STD_FUSE_OPP_VMIN_IVA_2 */
-#define STD_FUSE_OPP_VMIN_IVA_NOM (DRA752_EFUSE_BASE + 0x05CC)
-/* STD_FUSE_OPP_VMIN_IVA_3 */
-#define STD_FUSE_OPP_VMIN_IVA_OD (DRA752_EFUSE_BASE + 0x05D0)
-/* STD_FUSE_OPP_VMIN_IVA_4 */
-#define STD_FUSE_OPP_VMIN_IVA_HIGH (DRA752_EFUSE_BASE + 0x05D4)
-/* STD_FUSE_OPP_VMIN_DSPEVE_2 */
-#define STD_FUSE_OPP_VMIN_DSPEVE_NOM (DRA752_EFUSE_BASE + 0x05E0)
-/* STD_FUSE_OPP_VMIN_DSPEVE_3 */
-#define STD_FUSE_OPP_VMIN_DSPEVE_OD (DRA752_EFUSE_BASE + 0x05E4)
-/* STD_FUSE_OPP_VMIN_DSPEVE_4 */
-#define STD_FUSE_OPP_VMIN_DSPEVE_HIGH (DRA752_EFUSE_BASE + 0x05E8)
-/* STD_FUSE_OPP_VMIN_CORE_2 */
-#define STD_FUSE_OPP_VMIN_CORE_NOM (DRA752_EFUSE_BASE + 0x05F4)
-/* STD_FUSE_OPP_VMIN_GPU_2 */
-#define STD_FUSE_OPP_VMIN_GPU_NOM (DRA752_EFUSE_BASE + 0x1B08)
-/* STD_FUSE_OPP_VMIN_GPU_3 */
-#define STD_FUSE_OPP_VMIN_GPU_OD (DRA752_EFUSE_BASE + 0x1B0C)
-/* STD_FUSE_OPP_VMIN_GPU_4 */
-#define STD_FUSE_OPP_VMIN_GPU_HIGH (DRA752_EFUSE_BASE + 0x1B10)
-/* STD_FUSE_OPP_VMIN_MPU_2 */
-#define STD_FUSE_OPP_VMIN_MPU_NOM (DRA752_EFUSE_BASE + 0x1B20)
-/* STD_FUSE_OPP_VMIN_MPU_3 */
-#define STD_FUSE_OPP_VMIN_MPU_OD (DRA752_EFUSE_BASE + 0x1B24)
-/* STD_FUSE_OPP_VMIN_MPU_4 */
-#define STD_FUSE_OPP_VMIN_MPU_HIGH (DRA752_EFUSE_BASE + 0x1B28)
-
-#if defined(CONFIG_DRA7_MPU_OPP_HIGH)
-#define DRA7_MPU_OPP OPP_HIGH
-#elif defined(CONFIG_DRA7_MPU_OPP_OD)
-#define DRA7_MPU_OPP OPP_OD
-#else /* OPP_NOM default */
-#define DRA7_MPU_OPP OPP_NOM
-#endif
-
-/* OPP_NOM only available option for CORE */
-#define DRA7_CORE_OPP OPP_NOM
-
-#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
-#define DRA7_DSPEVE_OPP OPP_HIGH
-#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
-#define DRA7_DSPEVE_OPP OPP_OD
-#else /* OPP_NOM default */
-#define DRA7_DSPEVE_OPP OPP_NOM
-#endif
-
-#if defined(CONFIG_DRA7_IVA_OPP_HIGH)
-#define DRA7_IVA_OPP OPP_HIGH
-#elif defined(CONFIG_DRA7_IVA_OPP_OD)
-#define DRA7_IVA_OPP OPP_OD
-#else /* OPP_NOM default */
-#define DRA7_IVA_OPP OPP_NOM
-#endif
-
-#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
-#define DRA7_GPU_OPP OPP_HIGH
-#elif defined(CONFIG_DRA7_GPU_OPP_OD)
-#define DRA7_GPU_OPP OPP_OD
-#else /* OPP_NOM default */
-#define DRA7_GPU_OPP OPP_NOM
-#endif
-
-/* Standard offset is 0.5v expressed in uv */
-#define PALMAS_SMPS_BASE_VOLT_UV 500000
-
-/* Offset is 0.73V for LP873x */
-#define LP873X_BUCK_BASE_VOLT_UV 730000
-
-/* Offset is 0.73V for LP87565 */
-#define LP87565_BUCK_BASE_VOLT_UV 730000
-
-/* TPS659038 */
-#define TPS659038_I2C_SLAVE_ADDR 0x58
-#define TPS659038_REG_ADDR_SMPS12 0x23
-#define TPS659038_REG_ADDR_SMPS45 0x2B
-#define TPS659038_REG_ADDR_SMPS6 0x2F
-#define TPS659038_REG_ADDR_SMPS7 0x33
-#define TPS659038_REG_ADDR_SMPS8 0x37
-
-/* TPS65917 */
-#define TPS65917_I2C_SLAVE_ADDR 0x58
-#define TPS65917_REG_ADDR_SMPS1 0x23
-#define TPS65917_REG_ADDR_SMPS2 0x27
-#define TPS65917_REG_ADDR_SMPS3 0x2F
-#define TPS65917_REG_ADDR_SMPS4 0x33
-
-/* LP873X */
-#define LP873X_I2C_SLAVE_ADDR 0x60
-#define LP873X_REG_ADDR_BUCK0 0x6
-#define LP873X_REG_ADDR_BUCK1 0x7
-#define LP873X_REG_ADDR_LDO1 0xA
-
-/* LP87565 */
-#define LP87565_I2C_SLAVE_ADDR 0x61
-#define LP87565_REG_ADDR_BUCK01 0xA
-#define LP87565_REG_ADDR_BUCK23 0xE
-
-/* TPS */
-#define TPS62361_I2C_SLAVE_ADDR 0x60
-#define TPS62361_REG_ADDR_SET0 0x0
-#define TPS62361_REG_ADDR_SET1 0x1
-#define TPS62361_REG_ADDR_SET2 0x2
-#define TPS62361_REG_ADDR_SET3 0x3
-#define TPS62361_REG_ADDR_CTRL 0x4
-#define TPS62361_REG_ADDR_TEMP 0x5
-#define TPS62361_REG_ADDR_RMP_CTRL 0x6
-#define TPS62361_REG_ADDR_CHIP_ID 0x8
-#define TPS62361_REG_ADDR_CHIP_ID_2 0x9
-
-#define TPS62361_BASE_VOLT_MV 500
-#define TPS62361_VSEL0_GPIO 7
-
-/* Defines for DPLL setup */
-#define DPLL_LOCKED_FREQ_TOLERANCE_0 0
-#define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ 500
-#define DPLL_LOCKED_FREQ_TOLERANCE_1_MHZ 1000
-
-#define DPLL_NO_LOCK 0
-#define DPLL_LOCK 1
-
-#if defined(CONFIG_DRA7XX)
-#define V_OSCK 20000000 /* Clock output from T2 */
-#else
-#define V_OSCK 19200000 /* Clock output from T2 */
-#endif
-
-#define V_SCLK V_OSCK
-
-/* CKO buffer control */
-#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28)
-
-/* AUXCLKx reg fields */
-#define AUXCLK_ENABLE_MASK (1 << 8)
-#define AUXCLK_SRCSELECT_SHIFT 1
-#define AUXCLK_SRCSELECT_MASK (3 << 1)
-#define AUXCLK_CLKDIV_SHIFT 16
-#define AUXCLK_CLKDIV_MASK (0xF << 16)
-
-#define AUXCLK_SRCSELECT_SYS_CLK 0
-#define AUXCLK_SRCSELECT_CORE_DPLL 1
-#define AUXCLK_SRCSELECT_PER_DPLL 2
-#define AUXCLK_SRCSELECT_ALTERNATE 3
-
-#endif /* _CLOCKS_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
deleted file mode 100644
index 9e56553..0000000
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2010
- * Texas Instruments, <www.ti.com>
- *
- * Aneesh V <aneesh@ti.com>
- */
-
-#ifndef _CPU_H
-#define _CPU_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <asm/arch/hardware.h>
-
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-#include <asm/ti-common/omap_wdt.h>
-
-struct gptimer {
- u32 tidr; /* 0x00 r */
- u8 res1[0xc];
- u32 tiocp_cfg; /* 0x10 rw */
- u8 res2[0x10];
- u32 tisr_raw; /* 0x24 r */
- u32 tisr; /* 0x28 rw */
- u32 tier; /* 0x2c rw */
- u32 ticr; /* 0x30 rw */
- u32 twer; /* 0x34 rw */
- u32 tclr; /* 0x38 rw */
- u32 tcrr; /* 0x3c rw */
- u32 tldr; /* 0x40 rw */
- u32 ttgr; /* 0x44 rw */
- u32 twpc; /* 0x48 r */
- u32 tmar; /* 0x4c rw */
- u32 tcar1; /* 0x50 r */
- u32 tcicr; /* 0x54 rw */
- u32 tcar2; /* 0x58 r */
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-/* enable sys_clk NO-prescale /1 */
-#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
-
-#define WDT_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
-/* Watchdog */
-#ifndef __KERNEL_STRICT_NAMES
-#ifndef __ASSEMBLY__
-struct watchdog {
- u8 res1[0x34];
- u32 wwps; /* 0x34 r */
- u8 res2[0x10];
- u32 wspr; /* 0x48 rw */
-};
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL_STRICT_NAMES */
-
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-#define TCLR_ST (0x1 << 0)
-#define TCLR_AR (0x1 << 1)
-#define TCLR_PRE (0x1 << 5)
-
-/* I2C base */
-#define I2C_BASE1 (OMAP54XX_L4_PER_BASE + 0x70000)
-#define I2C_BASE2 (OMAP54XX_L4_PER_BASE + 0x72000)
-#define I2C_BASE3 (OMAP54XX_L4_PER_BASE + 0x60000)
-#define I2C_BASE4 (OMAP54XX_L4_PER_BASE + 0x7A000)
-#define I2C_BASE5 (OMAP54XX_L4_PER_BASE + 0x7C000)
-
-/* MUSB base */
-#define MUSB_BASE (OMAP54XX_L4_CORE_BASE + 0xAB000)
-
-/* OMAP4 GPIO registers */
-#define OMAP_GPIO_REVISION 0x0000
-#define OMAP_GPIO_SYSCONFIG 0x0010
-#define OMAP_GPIO_SYSSTATUS 0x0114
-#define OMAP_GPIO_IRQSTATUS1 0x0118
-#define OMAP_GPIO_IRQSTATUS2 0x0128
-#define OMAP_GPIO_IRQENABLE2 0x012c
-#define OMAP_GPIO_IRQENABLE1 0x011c
-#define OMAP_GPIO_WAKE_EN 0x0120
-#define OMAP_GPIO_CTRL 0x0130
-#define OMAP_GPIO_OE 0x0134
-#define OMAP_GPIO_DATAIN 0x0138
-#define OMAP_GPIO_DATAOUT 0x013c
-#define OMAP_GPIO_LEVELDETECT0 0x0140
-#define OMAP_GPIO_LEVELDETECT1 0x0144
-#define OMAP_GPIO_RISINGDETECT 0x0148
-#define OMAP_GPIO_FALLINGDETECT 0x014c
-#define OMAP_GPIO_DEBOUNCE_EN 0x0150
-#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
-#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
-#define OMAP_GPIO_SETIRQENABLE1 0x0164
-#define OMAP_GPIO_CLEARWKUENA 0x0180
-#define OMAP_GPIO_SETWKUENA 0x0184
-#define OMAP_GPIO_CLEARDATAOUT 0x0190
-#define OMAP_GPIO_SETDATAOUT 0x0194
-
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE 0x4AE06000
-#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET 0x01
-#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
-#define PRM_RSTST_WARM_RESET_MASK 0x7FEA
-
-/* DRA7XX CPSW Config space */
-#define CPSW_BASE 0x48484000
-#define CPSW_MDIO_BASE 0x48485000
-
-/* gmii_sel register defines */
-#define GMII1_SEL_MII 0x0
-#define GMII1_SEL_RMII 0x1
-#define GMII1_SEL_RGMII 0x2
-#define GMII2_SEL_MII (GMII1_SEL_MII << 4)
-#define GMII2_SEL_RMII (GMII1_SEL_RMII << 4)
-#define GMII2_SEL_RGMII (GMII1_SEL_RGMII << 4)
-
-#define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
-#define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
-#define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
-
-#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h b/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
deleted file mode 100644
index 09edfad..0000000
--- a/arch/arm/include/asm/arch-omap5/dra7xx_iodelay.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2015
- * Texas Instruments Incorporated
- *
- * Lokesh Vutla <lokeshvutla@ti.com>
- */
-
-#ifndef _DRA7_IODELAY_H_
-#define _DRA7_IODELAY_H_
-
-#include <common.h>
-#include <asm/arch/sys_proto.h>
-
-/* CONFIG_REG_0 */
-#define CFG_REG_0_OFFSET 0xC
-#define CFG_REG_ROM_READ_SHIFT 1
-#define CFG_REG_ROM_READ_MASK (1 << 1)
-#define CFG_REG_CALIB_STRT_SHIFT 0
-#define CFG_REG_CALIB_STRT_MASK (1 << 0)
-#define CFG_REG_CALIB_STRT 1
-#define CFG_REG_CALIB_END 0
-#define CFG_REG_ROM_READ_START (1 << 1)
-#define CFG_REG_ROM_READ_END (0 << 1)
-
-/* CONFIG_REG_2 */
-#define CFG_REG_2_OFFSET 0x14
-#define CFG_REG_REFCLK_PERIOD_SHIFT 0
-#define CFG_REG_REFCLK_PERIOD_MASK (0xFFFF << 0)
-#define CFG_REG_REFCLK_PERIOD 0x2EF
-
-/* CONFIG_REG_8 */
-#define CFG_REG_8_OFFSET 0x2C
-#define CFG_IODELAY_UNLOCK_KEY 0x0000AAAA
-#define CFG_IODELAY_LOCK_KEY 0x0000AAAB
-
-/* CONFIG_REG_3/4 */
-#define CFG_REG_3_OFFSET 0x18
-#define CFG_REG_4_OFFSET 0x1C
-#define CFG_REG_DLY_CNT_SHIFT 16
-#define CFG_REG_DLY_CNT_MASK (0xFFFF << 16)
-#define CFG_REG_REF_CNT_SHIFT 0
-#define CFG_REG_REF_CNT_MASK (0xFFFF << 0)
-
-/* CTRL_CORE_SMA_SW_0 */
-#define CTRL_ISOLATE_SHIFT 2
-#define CTRL_ISOLATE_MASK (1 << 2)
-#define ISOLATE_IO 1
-#define DEISOLATE_IO 0
-
-/* CTRL_CORE_SMA_SW_1 */
-#define RGMII2_ID_MODE_N_MASK (1 << 26)
-#define RGMII1_ID_MODE_N_MASK (1 << 25)
-
-/* PRM_IO_PMCTRL */
-#define PMCTRL_ISOCLK_OVERRIDE_SHIFT 0
-#define PMCTRL_ISOCLK_OVERRIDE_MASK (1 << 0)
-#define PMCTRL_ISOCLK_STATUS_SHIFT 1
-#define PMCTRL_ISOCLK_STATUS_MASK (1 << 1)
-#define PMCTRL_ISOCLK_OVERRIDE_CTRL 1
-#define PMCTRL_ISOCLK_NOT_OVERRIDE_CTRL 0
-
-#define ERR_CALIBRATE_IODELAY 0x1
-#define ERR_DEISOLATE_IO 0x2
-#define ERR_ISOLATE_IO 0x4
-#define ERR_UPDATE_DELAY 0x8
-#define ERR_CPDE 0x3
-#define ERR_FPDE 0x5
-
-/* CFG_XXX */
-#define CFG_X_SIGNATURE_SHIFT 12
-#define CFG_X_SIGNATURE_MASK (0x3F << 12)
-#define CFG_X_LOCK_SHIFT 10
-#define CFG_X_LOCK_MASK (0x1 << 10)
-#define CFG_X_COARSE_DLY_SHIFT 5
-#define CFG_X_COARSE_DLY_MASK (0x1F << 5)
-#define CFG_X_FINE_DLY_SHIFT 0
-#define CFG_X_FINE_DLY_MASK (0x1F << 0)
-#define CFG_X_SIGNATURE 0x29
-#define CFG_X_LOCK 1
-
-void __recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
- struct iodelay_cfg_entry const *iodelay,
- int niodelays);
-void late_recalibrate_iodelay(struct pad_conf_entry const *pad, int npads,
- struct iodelay_cfg_entry const *iodelay,
- int niodelays);
-int __recalibrate_iodelay_start(void);
-void __recalibrate_iodelay_end(int ret);
-
-int do_set_iodelay(u32 base, struct iodelay_cfg_entry const *array,
- int niodelays);
-#endif
diff --git a/arch/arm/include/asm/arch-omap5/ehci.h b/arch/arm/include/asm/arch-omap5/ehci.h
deleted file mode 100644
index 1790b92..0000000
--- a/arch/arm/include/asm/arch-omap5/ehci.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com*
- * Author: Govindraj R <govindraj.raja@ti.com>
- */
-
-#ifndef _EHCI_H
-#define _EHCI_H
-
-#define OMAP_EHCI_BASE (OMAP54XX_L4_CORE_BASE + 0x64C00)
-#define OMAP_UHH_BASE (OMAP54XX_L4_CORE_BASE + 0x64000)
-#define OMAP_USBTLL_BASE (OMAP54XX_L4_CORE_BASE + 0x62000)
-
-/* TLL Register Set */
-#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
-#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
-#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
-#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
-#define OMAP_USBTLL_SYSSTATUS_RESETDONE 1
-
-#define OMAP_UHH_SYSCONFIG_SOFTRESET 1
-#define OMAP_UHH_SYSSTATUS_EHCI_RESETDONE (1 << 2)
-#define OMAP_UHH_SYSCONFIG_NOIDLE (1 << 2)
-#define OMAP_UHH_SYSCONFIG_NOSTDBY (1 << 4)
-
-#define OMAP_UHH_SYSCONFIG_VAL (OMAP_UHH_SYSCONFIG_NOIDLE | \
- OMAP_UHH_SYSCONFIG_NOSTDBY)
-
-#endif /* _EHCI_H */
diff --git a/arch/arm/include/asm/arch-omap5/gpio.h b/arch/arm/include/asm/arch-omap5/gpio.h
deleted file mode 100644
index 1e44fb5..0000000
--- a/arch/arm/include/asm/arch-omap5/gpio.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Copyright (c) 2009 Wind River Systems, Inc.
- * Tom Rix <Tom.Rix@windriver.com>
- *
- * This work is derived from the linux 2.6.27 kernel source
- * To fetch, use the kernel repository
- * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
- * Use the v2.6.27 tag.
- *
- * Below is the original's header including its copyright
- *
- * linux/arch/arm/plat-omap/gpio.c
- *
- * Support functions for OMAP GPIO
- *
- * Copyright (C) 2003-2005 Nokia Corporation
- * Written by Juha Yrjölä <juha.yrjola@nokia.com>
- */
-#ifndef _GPIO_OMAP5_H
-#define _GPIO_OMAP5_H
-
-#include <asm/omap_gpio.h>
-
-#define OMAP_MAX_GPIO 256
-
-#define OMAP54XX_GPIO1_BASE 0x4Ae10000
-#define OMAP54XX_GPIO2_BASE 0x48055000
-#define OMAP54XX_GPIO3_BASE 0x48057000
-#define OMAP54XX_GPIO4_BASE 0x48059000
-#define OMAP54XX_GPIO5_BASE 0x4805B000
-#define OMAP54XX_GPIO6_BASE 0x4805D000
-#define OMAP54XX_GPIO7_BASE 0x48051000
-#define OMAP54XX_GPIO8_BASE 0x48053000
-
-
-/* Get the GPIO index from the given bank number and bank gpio */
-#define GPIO_TO_PIN(bank, bank_gpio) (32 * (bank - 1) + (bank_gpio))
-
-#endif /* _GPIO_OMAP5_H */
diff --git a/arch/arm/include/asm/arch-omap5/hardware.h b/arch/arm/include/asm/arch-omap5/hardware.h
deleted file mode 100644
index b6d26e9..0000000
--- a/arch/arm/include/asm/arch-omap5/hardware.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * hardware.h
- *
- * hardware specific header
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#ifndef __OMAP_HARDWARE_H
-#define __OMAP_HARDWARE_H
-
-#include <asm/arch/omap.h>
-
-/*
- * Common hardware definitions
- */
-
-/* BCH Error Location Module */
-#define ELM_BASE 0x48078000
-
-/* GPMC Base address */
-#define GPMC_BASE 0x50000000
-
-/* EDMA3 Base address for DRA7XX and AM57XX */
-#if defined(CONFIG_DRA7XX)
-#define EDMA3_BASE 0x43300000
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap5/i2c.h b/arch/arm/include/asm/arch-omap5/i2c.h
deleted file mode 100644
index 9e1edcf..0000000
--- a/arch/arm/include/asm/arch-omap5/i2c.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2004-2010
- * Texas Instruments, <www.ti.com>
- */
-#ifndef _OMAP5_I2C_H_
-#define _OMAP5_I2C_H_
-
-#define I2C_DEFAULT_BASE I2C_BASE1
-
-#endif /* _OMAP5_I2C_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mem.h b/arch/arm/include/asm/arch-omap5/mem.h
deleted file mode 100644
index bd72fb6..0000000
--- a/arch/arm/include/asm/arch-omap5/mem.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2006-2008
- * Texas Instruments, <www.ti.com>
- *
- * Author
- * Mansoor Ahamed <mansoor.ahamed@ti.com>
- *
- * Initial Code from:
- * Richard Woodruff <r-woodruff2@ti.com>
- */
-
-#ifndef _MEM_H_
-#define _MEM_H_
-
-/*
- * GPMC settings -
- * Definitions is as per the following format
- * #define <PART>_GPMC_CONFIG<x> <value>
- * Where:
- * PART is the part name e.g. STNOR - Intel Strata Flash
- * x is GPMC config registers from 1 to 6 (there will be 6 macros)
- * Value is corresponding value
- *
- * For every valid PRCM configuration there should be only one definition of
- * the same. if values are independent of the board, this definition will be
- * present in this file if values are dependent on the board, then this should
- * go into corresponding mem-boardName.h file
- *
- * Currently valid part Names are (PART):
- * M_NAND - Micron NAND
- * STNOR - STMicrolelctronics M29W128GL
- */
-#define GPMC_SIZE_256M 0x0
-#define GPMC_SIZE_128M 0x8
-#define GPMC_SIZE_64M 0xC
-#define GPMC_SIZE_32M 0xE
-#define GPMC_SIZE_16M 0xF
-
-#define M_NAND_GPMC_CONFIG1 0x00000800
-#define M_NAND_GPMC_CONFIG2 0x001e1e00
-#define M_NAND_GPMC_CONFIG3 0x001e1e00
-#define M_NAND_GPMC_CONFIG4 0x16051807
-#define M_NAND_GPMC_CONFIG5 0x00151e1e
-#define M_NAND_GPMC_CONFIG6 0x16000f80
-#define M_NAND_GPMC_CONFIG7 0x00000008
-
-#define STNOR_GPMC_CONFIG1 0x00001000
-#define STNOR_GPMC_CONFIG2 0x001f1f00
-#define STNOR_GPMC_CONFIG3 0x001f1f01
-#define STNOR_GPMC_CONFIG4 0x1f011f01
-#define STNOR_GPMC_CONFIG5 0x001d1f1f
-#define STNOR_GPMC_CONFIG6 0x08070280
-#define STNOR_GPMC_CONFIG7 0x00000048
-
-/* max number of GPMC Chip Selects */
-#define GPMC_MAX_CS 8
-/* max number of GPMC regs */
-#define GPMC_MAX_REG 7
-
-#endif /* endif _MEM_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mmc_host_def.h b/arch/arm/include/asm/arch-omap5/mmc_host_def.h
deleted file mode 100644
index d067799..0000000
--- a/arch/arm/include/asm/arch-omap5/mmc_host_def.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- * Syed Mohammed Khasim <khasim@ti.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation's version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef MMC_HOST_DEF_H
-#define MMC_HOST_DEF_H
-
-#include <asm/omap_mmc.h>
-
-/*
- * OMAP HSMMC register definitions
- */
-
-#define OMAP_HSMMC1_BASE 0x4809C000
-#define OMAP_HSMMC2_BASE 0x480B4000
-#define OMAP_HSMMC3_BASE 0x480AD000
-
-#endif /* MMC_HOST_DEF_H */
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
deleted file mode 100644
index c7c118e..0000000
--- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated
- *
- * Nishant Kamat <nskamat@ti.com>
- * Lokesh Vutla <lokeshvutla@ti.com>
- */
-#ifndef _MUX_DRA7XX_H_
-#define _MUX_DRA7XX_H_
-
-#include <asm/types.h>
-
-#define PULL_ENA (0 << 16)
-#define PULL_DIS (1 << 16)
-#define PULL_UP (1 << 17)
-#define INPUT_EN (1 << 18)
-#define SLEWCONTROL (1 << 19)
-
-/* Active pin states */
-#define PIN_OUTPUT (0 | PULL_DIS)
-#define PIN_OUTPUT_PULLUP (PULL_UP)
-#define PIN_OUTPUT_PULLDOWN (0)
-#define PIN_INPUT (INPUT_EN | PULL_DIS)
-#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
-#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
-#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
-
-#define M0 0
-#define M1 1
-#define M2 2
-#define M3 3
-#define M4 4
-#define M5 5
-#define M6 6
-#define M7 7
-#define M8 8
-#define M9 9
-#define M10 10
-#define M11 11
-#define M12 12
-#define M13 13
-#define M14 14
-#define M15 15
-
-#define MODE_SELECT (1 << 8)
-#define DELAYMODE_SHIFT 4
-
-#define MANUAL_MODE MODE_SELECT
-
-#define VIRTUAL_MODE0 (MODE_SELECT | (0x0 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE1 (MODE_SELECT | (0x1 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE2 (MODE_SELECT | (0x2 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE3 (MODE_SELECT | (0x3 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE4 (MODE_SELECT | (0x4 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE5 (MODE_SELECT | (0x5 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE6 (MODE_SELECT | (0x6 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE7 (MODE_SELECT | (0x7 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE8 (MODE_SELECT | (0x8 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE9 (MODE_SELECT | (0x9 << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE10 (MODE_SELECT | (0xa << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE11 (MODE_SELECT | (0xb << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE12 (MODE_SELECT | (0xc << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE13 (MODE_SELECT | (0xd << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE14 (MODE_SELECT | (0xe << DELAYMODE_SHIFT))
-#define VIRTUAL_MODE15 (MODE_SELECT | (0xf << DELAYMODE_SHIFT))
-
-#define SAFE_MODE M15
-
-#define GPMC_AD0 0x000
-#define GPMC_AD1 0x004
-#define GPMC_AD2 0x008
-#define GPMC_AD3 0x00C
-#define GPMC_AD4 0x010
-#define GPMC_AD5 0x014
-#define GPMC_AD6 0x018
-#define GPMC_AD7 0x01C
-#define GPMC_AD8 0x020
-#define GPMC_AD9 0x024
-#define GPMC_AD10 0x028
-#define GPMC_AD11 0x02C
-#define GPMC_AD12 0x030
-#define GPMC_AD13 0x034
-#define GPMC_AD14 0x038
-#define GPMC_AD15 0x03C
-#define GPMC_A0 0x040
-#define GPMC_A1 0x044
-#define GPMC_A2 0x048
-#define GPMC_A3 0x04C
-#define GPMC_A4 0x050
-#define GPMC_A5 0x054
-#define GPMC_A6 0x058
-#define GPMC_A7 0x05C
-#define GPMC_A8 0x060
-#define GPMC_A9 0x064
-#define GPMC_A10 0x068
-#define GPMC_A11 0x06C
-#define GPMC_A12 0x070
-#define GPMC_A13 0x074
-#define GPMC_A14 0x078
-#define GPMC_A15 0x07C
-#define GPMC_A16 0x080
-#define GPMC_A17 0x084
-#define GPMC_A18 0x088
-#define GPMC_A19 0x08C
-#define GPMC_A20 0x090
-#define GPMC_A21 0x094
-#define GPMC_A22 0x098
-#define GPMC_A23 0x09C
-#define GPMC_A24 0x0A0
-#define GPMC_A25 0x0A4
-#define GPMC_A26 0x0A8
-#define GPMC_A27 0x0AC
-#define GPMC_CS1 0x0B0
-#define GPMC_CS0 0x0B4
-#define GPMC_CS2 0x0B8
-#define GPMC_CS3 0x0BC
-#define GPMC_CLK 0x0C0
-#define GPMC_ADVN_ALE 0x0C4
-#define GPMC_OEN_REN 0x0C8
-#define GPMC_WEN 0x0CC
-#define GPMC_BEN0 0x0D0
-#define GPMC_BEN1 0x0D4
-#define GPMC_WAIT0 0x0D8
-#define VIN1A_CLK0 0x0DC
-#define VIN1B_CLK1 0x0E0
-#define VIN1A_DE0 0x0E4
-#define VIN1A_FLD0 0x0E8
-#define VIN1A_HSYNC0 0x0EC
-#define VIN1A_VSYNC0 0x0F0
-#define VIN1A_D0 0x0F4
-#define VIN1A_D1 0x0F8
-#define VIN1A_D2 0x0FC
-#define VIN1A_D3 0x100
-#define VIN1A_D4 0x104
-#define VIN1A_D5 0x108
-#define VIN1A_D6 0x10C
-#define VIN1A_D7 0x110
-#define VIN1A_D8 0x114
-#define VIN1A_D9 0x118
-#define VIN1A_D10 0x11C
-#define VIN1A_D11 0x120
-#define VIN1A_D12 0x124
-#define VIN1A_D13 0x128
-#define VIN1A_D14 0x12C
-#define VIN1A_D15 0x130
-#define VIN1A_D16 0x134
-#define VIN1A_D17 0x138
-#define VIN1A_D18 0x13C
-#define VIN1A_D19 0x140
-#define VIN1A_D20 0x144
-#define VIN1A_D21 0x148
-#define VIN1A_D22 0x14C
-#define VIN1A_D23 0x150
-#define VIN2A_CLK0 0x154
-#define VIN2A_DE0 0x158
-#define VIN2A_FLD0 0x15C
-#define VIN2A_HSYNC0 0x160
-#define VIN2A_VSYNC0 0x164
-#define VIN2A_D0 0x168
-#define VIN2A_D1 0x16C
-#define VIN2A_D2 0x170
-#define VIN2A_D3 0x174
-#define VIN2A_D4 0x178
-#define VIN2A_D5 0x17C
-#define VIN2A_D6 0x180
-#define VIN2A_D7 0x184
-#define VIN2A_D8 0x188
-#define VIN2A_D9 0x18C
-#define VIN2A_D10 0x190
-#define VIN2A_D11 0x194
-#define VIN2A_D12 0x198
-#define VIN2A_D13 0x19C
-#define VIN2A_D14 0x1A0
-#define VIN2A_D15 0x1A4
-#define VIN2A_D16 0x1A8
-#define VIN2A_D17 0x1AC
-#define VIN2A_D18 0x1B0
-#define VIN2A_D19 0x1B4
-#define VIN2A_D20 0x1B8
-#define VIN2A_D21 0x1BC
-#define VIN2A_D22 0x1C0
-#define VIN2A_D23 0x1C4
-#define VOUT1_CLK 0x1C8
-#define VOUT1_DE 0x1CC
-#define VOUT1_FLD 0x1D0
-#define VOUT1_HSYNC 0x1D4
-#define VOUT1_VSYNC 0x1D8
-#define VOUT1_D0 0x1DC
-#define VOUT1_D1 0x1E0
-#define VOUT1_D2 0x1E4
-#define VOUT1_D3 0x1E8
-#define VOUT1_D4 0x1EC
-#define VOUT1_D5 0x1F0
-#define VOUT1_D6 0x1F4
-#define VOUT1_D7 0x1F8
-#define VOUT1_D8 0x1FC
-#define VOUT1_D9 0x200
-#define VOUT1_D10 0x204
-#define VOUT1_D11 0x208
-#define VOUT1_D12 0x20C
-#define VOUT1_D13 0x210
-#define VOUT1_D14 0x214
-#define VOUT1_D15 0x218
-#define VOUT1_D16 0x21C
-#define VOUT1_D17 0x220
-#define VOUT1_D18 0x224
-#define VOUT1_D19 0x228
-#define VOUT1_D20 0x22C
-#define VOUT1_D21 0x230
-#define VOUT1_D22 0x234
-#define VOUT1_D23 0x238
-#define MDIO_MCLK 0x23C
-#define MDIO_D 0x240
-#define RMII_MHZ_50_CLK 0x244
-#define UART3_RXD 0x248
-#define UART3_TXD 0x24C
-#define RGMII0_TXC 0x250
-#define RGMII0_TXCTL 0x254
-#define RGMII0_TXD3 0x258
-#define RGMII0_TXD2 0x25C
-#define RGMII0_TXD1 0x260
-#define RGMII0_TXD0 0x264
-#define RGMII0_RXC 0x268
-#define RGMII0_RXCTL 0x26C
-#define RGMII0_RXD3 0x270
-#define RGMII0_RXD2 0x274
-#define RGMII0_RXD1 0x278
-#define RGMII0_RXD0 0x27C
-#define USB1_DRVVBUS 0x280
-#define USB2_DRVVBUS 0x284
-#define GPIO6_14 0x288
-#define GPIO6_15 0x28C
-#define GPIO6_16 0x290
-#define XREF_CLK0 0x294
-#define XREF_CLK1 0x298
-#define XREF_CLK2 0x29C
-#define XREF_CLK3 0x2A0
-#define MCASP1_ACLKX 0x2A4
-#define MCASP1_FSX 0x2A8
-#define MCASP1_ACLKR 0x2AC
-#define MCASP1_FSR 0x2B0
-#define MCASP1_AXR0 0x2B4
-#define MCASP1_AXR1 0x2B8
-#define MCASP1_AXR2 0x2BC
-#define MCASP1_AXR3 0x2C0
-#define MCASP1_AXR4 0x2C4
-#define MCASP1_AXR5 0x2C8
-#define MCASP1_AXR6 0x2CC
-#define MCASP1_AXR7 0x2D0
-#define MCASP1_AXR8 0x2D4
-#define MCASP1_AXR9 0x2D8
-#define MCASP1_AXR10 0x2DC
-#define MCASP1_AXR11 0x2E0
-#define MCASP1_AXR12 0x2E4
-#define MCASP1_AXR13 0x2E8
-#define MCASP1_AXR14 0x2EC
-#define MCASP1_AXR15 0x2F0
-#define MCASP2_ACLKX 0x2F4
-#define MCASP2_FSX 0x2F8
-#define MCASP2_ACLKR 0x2FC
-#define MCASP2_FSR 0x300
-#define MCASP2_AXR0 0x304
-#define MCASP2_AXR1 0x308
-#define MCASP2_AXR2 0x30C
-#define MCASP2_AXR3 0x310
-#define MCASP2_AXR4 0x314
-#define MCASP2_AXR5 0x318
-#define MCASP2_AXR6 0x31C
-#define MCASP2_AXR7 0x320
-#define MCASP3_ACLKX 0x324
-#define MCASP3_FSX 0x328
-#define MCASP3_AXR0 0x32C
-#define MCASP3_AXR1 0x330
-#define MCASP4_ACLKX 0x334
-#define MCASP4_FSX 0x338
-#define MCASP4_AXR0 0x33C
-#define MCASP4_AXR1 0x340
-#define MCASP5_ACLKX 0x344
-#define MCASP5_FSX 0x348
-#define MCASP5_AXR0 0x34C
-#define MCASP5_AXR1 0x350
-#define MMC1_CLK 0x354
-#define MMC1_CMD 0x358
-#define MMC1_DAT0 0x35C
-#define MMC1_DAT1 0x360
-#define MMC1_DAT2 0x364
-#define MMC1_DAT3 0x368
-#define MMC1_SDCD 0x36C
-#define MMC1_SDWP 0x370
-#define GPIO6_10 0x374
-#define GPIO6_11 0x378
-#define MMC3_CLK 0x37C
-#define MMC3_CMD 0x380
-#define MMC3_DAT0 0x384
-#define MMC3_DAT1 0x388
-#define MMC3_DAT2 0x38C
-#define MMC3_DAT3 0x390
-#define MMC3_DAT4 0x394
-#define MMC3_DAT5 0x398
-#define MMC3_DAT6 0x39C
-#define MMC3_DAT7 0x3A0
-#define SPI1_SCLK 0x3A4
-#define SPI1_D1 0x3A8
-#define SPI1_D0 0x3AC
-#define SPI1_CS0 0x3B0
-#define SPI1_CS1 0x3B4
-#define SPI1_CS2 0x3B8
-#define SPI1_CS3 0x3BC
-#define SPI2_SCLK 0x3C0
-#define SPI2_D1 0x3C4
-#define SPI2_D0 0x3C8
-#define SPI2_CS0 0x3CC
-#define DCAN1_TX 0x3D0
-#define DCAN1_RX 0x3D4
-#define DCAN2_TX 0x3D8
-#define DCAN2_RX 0x3DC
-#define UART1_RXD 0x3E0
-#define UART1_TXD 0x3E4
-#define UART1_CTSN 0x3E8
-#define UART1_RTSN 0x3EC
-#define UART2_RXD 0x3F0
-#define UART2_TXD 0x3F4
-#define UART2_CTSN 0x3F8
-#define UART2_RTSN 0x3FC
-#define I2C1_SDA 0x400
-#define I2C1_SCL 0x404
-#define I2C2_SDA 0x408
-#define I2C2_SCL 0x40C
-#define I2C3_SDA 0x410
-#define I2C3_SCL 0x414
-#define WAKEUP0 0x418
-#define WAKEUP1 0x41C
-#define WAKEUP2 0x420
-#define WAKEUP3 0x424
-#define ON_OFF 0x428
-#define RTC_PORZ 0x42C
-#define TMS 0x430
-#define TDI 0x434
-#define TDO 0x438
-#define TCLK 0x43C
-#define TRSTN 0x440
-#define RTCK 0x444
-#define EMU0 0x448
-#define EMU1 0x44C
-#define EMU2 0x450
-#define EMU3 0x454
-#define EMU4 0x458
-#define RESETN 0x45C
-#define NMIN_DSP 0x460
-#define RSTOUTN 0x464
-
-#define MCAN_SEL_ALT_MASK 0x6000
-#define MCAN_SEL 0x2000
-
-#endif /* _MUX_DRA7XX_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h
deleted file mode 100644
index 2460646..0000000
--- a/arch/arm/include/asm/arch-omap5/mux_omap5.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2004-2009
- * Texas Instruments Incorporated
- * Richard Woodruff <r-woodruff2@ti.com>
- * Aneesh V <aneesh@ti.com>
- * Balaji Krishnamoorthy <balajitk@ti.com>
- */
-#ifndef _MUX_OMAP5_H_
-#define _MUX_OMAP5_H_
-
-#include <asm/types.h>
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_PD (1 << 12)
-#define OFF_PU (3 << 12)
-#define OFF_OUT_PTD (0 << 10)
-#define OFF_OUT_PTU (2 << 10)
-#define OFF_IN (1 << 10)
-#define OFF_OUT (0 << 10)
-#define OFF_EN (1 << 9)
-#else
-#define OFF_PD (0 << 12)
-#define OFF_PU (0 << 12)
-#define OFF_OUT_PTD (0 << 10)
-#define OFF_OUT_PTU (0 << 10)
-#define OFF_IN (0 << 10)
-#define OFF_OUT (0 << 10)
-#define OFF_EN (0 << 9)
-#endif
-
-#define IEN (1 << 8)
-#define IDIS (0 << 8)
-#define PTU (3 << 3)
-#define PTD (1 << 3)
-#define EN (1 << 3)
-#define DIS (0 << 3)
-
-#define M0 0
-#define M1 1
-#define M2 2
-#define M3 3
-#define M4 4
-#define M5 5
-#define M6 6
-#define M7 7
-
-#define SAFE_MODE M7
-
-#ifdef CONFIG_OFF_PADCONF
-#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN)
-#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN)
-#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN)
-#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN)
-#else
-#define OFF_IN_PD 0
-#define OFF_IN_PU 0
-#define OFF_OUT_PD 0
-#define OFF_OUT_PU 0
-#endif
-
-#define CORE_REVISION 0x0000
-#define CORE_HWINFO 0x0004
-#define CORE_SYSCONFIG 0x0010
-#define EMMC_CLK 0x0040
-#define EMMC_CMD 0x0042
-#define EMMC_DATA0 0x0044
-#define EMMC_DATA1 0x0046
-#define EMMC_DATA2 0x0048
-#define EMMC_DATA3 0x004a
-#define EMMC_DATA4 0x004c
-#define EMMC_DATA5 0x004e
-#define EMMC_DATA6 0x0050
-#define EMMC_DATA7 0x0052
-#define C2C_CLKOUT0 0x0054
-#define C2C_CLKOUT1 0x0056
-#define C2C_CLKIN0 0x0058
-#define C2C_CLKIN1 0x005a
-#define C2C_DATAIN0 0x005c
-#define C2C_DATAIN1 0x005e
-#define C2C_DATAIN2 0x0060
-#define C2C_DATAIN3 0x0062
-#define C2C_DATAIN4 0x0064
-#define C2C_DATAIN5 0x0066
-#define C2C_DATAIN6 0x0068
-#define C2C_DATAIN7 0x006a
-#define C2C_DATAOUT0 0x006c
-#define C2C_DATAOUT1 0x006e
-#define C2C_DATAOUT2 0x0070
-#define C2C_DATAOUT3 0x0072
-#define C2C_DATAOUT4 0x0074
-#define C2C_DATAOUT5 0x0076
-#define C2C_DATAOUT6 0x0078
-#define C2C_DATAOUT7 0x007a
-#define C2C_DATA8 0x007c
-#define C2C_DATA9 0x007e
-#define C2C_DATA10 0x0080
-#define C2C_DATA11 0x0082
-#define C2C_DATA12 0x0084
-#define C2C_DATA13 0x0086
-#define C2C_DATA14 0x0088
-#define C2C_DATA15 0x008a
-#define LLIA_WAKEREQOUT 0x008c
-#define LLIB_WAKEREQOUT 0x008e
-#define HSI1_ACREADY 0x0090
-#define HSI1_CAREADY 0x0092
-#define HSI1_ACWAKE 0x0094
-#define HSI1_CAWAKE 0x0096
-#define HSI1_ACFLAG 0x0098
-#define HSI1_ACDATA 0x009a
-#define HSI1_CAFLAG 0x009c
-#define HSI1_CADATA 0x009e
-#define UART1_TX 0x00a0
-#define UART1_CTS 0x00a2
-#define UART1_RX 0x00a4
-#define UART1_RTS 0x00a6
-#define HSI2_CAREADY 0x00a8
-#define HSI2_ACREADY 0x00aa
-#define HSI2_CAWAKE 0x00ac
-#define HSI2_ACWAKE 0x00ae
-#define HSI2_CAFLAG 0x00b0
-#define HSI2_CADATA 0x00b2
-#define HSI2_ACFLAG 0x00b4
-#define HSI2_ACDATA 0x00b6
-#define UART2_RTS 0x00b8
-#define UART2_CTS 0x00ba
-#define UART2_RX 0x00bc
-#define UART2_TX 0x00be
-#define USBB1_HSIC_STROBE 0x00c0
-#define USBB1_HSIC_DATA 0x00c2
-#define USBB2_HSIC_STROBE 0x00c4
-#define USBB2_HSIC_DATA 0x00c6
-#define TIMER10_PWM_EVT 0x00c8
-#define DSIPORTA_TE0 0x00ca
-#define DSIPORTA_LANE0X 0x00cc
-#define DSIPORTA_LANE0Y 0x00ce
-#define DSIPORTA_LANE1X 0x00d0
-#define DSIPORTA_LANE1Y 0x00d2
-#define DSIPORTA_LANE2X 0x00d4
-#define DSIPORTA_LANE2Y 0x00d6
-#define DSIPORTA_LANE3X 0x00d8
-#define DSIPORTA_LANE3Y 0x00da
-#define DSIPORTA_LANE4X 0x00dc
-#define DSIPORTA_LANE4Y 0x00de
-#define DSIPORTC_LANE0X 0x00e0
-#define DSIPORTC_LANE0Y 0x00e2
-#define DSIPORTC_LANE1X 0x00e4
-#define DSIPORTC_LANE1Y 0x00e6
-#define DSIPORTC_LANE2X 0x00e8
-#define DSIPORTC_LANE2Y 0x00ea
-#define DSIPORTC_LANE3X 0x00ec
-#define DSIPORTC_LANE3Y 0x00ee
-#define DSIPORTC_LANE4X 0x00f0
-#define DSIPORTC_LANE4Y 0x00f2
-#define DSIPORTC_TE0 0x00f4
-#define TIMER9_PWM_EVT 0x00f6
-#define I2C4_SCL 0x00f8
-#define I2C4_SDA 0x00fa
-#define MCSPI2_CLK 0x00fc
-#define MCSPI2_SIMO 0x00fe
-#define MCSPI2_SOMI 0x0100
-#define MCSPI2_CS0 0x0102
-#define RFBI_DATA15 0x0104
-#define RFBI_DATA14 0x0106
-#define RFBI_DATA13 0x0108
-#define RFBI_DATA12 0x010a
-#define RFBI_DATA11 0x010c
-#define RFBI_DATA10 0x010e
-#define RFBI_DATA9 0x0110
-#define RFBI_DATA8 0x0112
-#define RFBI_DATA7 0x0114
-#define RFBI_DATA6 0x0116
-#define RFBI_DATA5 0x0118
-#define RFBI_DATA4 0x011a
-#define RFBI_DATA3 0x011c
-#define RFBI_DATA2 0x011e
-#define RFBI_DATA1 0x0120
-#define RFBI_DATA0 0x0122
-#define RFBI_WE 0x0124
-#define RFBI_CS0 0x0126
-#define RFBI_A0 0x0128
-#define RFBI_RE 0x012a
-#define RFBI_HSYNC0 0x012c
-#define RFBI_TE_VSYNC0 0x012e
-#define GPIO6_182 0x0130
-#define GPIO6_183 0x0132
-#define GPIO6_184 0x0134
-#define GPIO6_185 0x0136
-#define GPIO6_186 0x0138
-#define GPIO6_187 0x013a
-#define HDMI_CEC 0x013c
-#define HDMI_HPD 0x013e
-#define HDMI_DDC_SCL 0x0140
-#define HDMI_DDC_SDA 0x0142
-#define CSIPORTC_LANE0X 0x0144
-#define CSIPORTC_LANE0Y 0x0146
-#define CSIPORTC_LANE1X 0x0148
-#define CSIPORTC_LANE1Y 0x014a
-#define CSIPORTB_LANE0X 0x014c
-#define CSIPORTB_LANE0Y 0x014e
-#define CSIPORTB_LANE1X 0x0150
-#define CSIPORTB_LANE1Y 0x0152
-#define CSIPORTB_LANE2X 0x0154
-#define CSIPORTB_LANE2Y 0x0156
-#define CSIPORTA_LANE0X 0x0158
-#define CSIPORTA_LANE0Y 0x015a
-#define CSIPORTA_LANE1X 0x015c
-#define CSIPORTA_LANE1Y 0x015e
-#define CSIPORTA_LANE2X 0x0160
-#define CSIPORTA_LANE2Y 0x0162
-#define CSIPORTA_LANE3X 0x0164
-#define CSIPORTA_LANE3Y 0x0166
-#define CSIPORTA_LANE4X 0x0168
-#define CSIPORTA_LANE4Y 0x016a
-#define CAM_SHUTTER 0x016c
-#define CAM_STROBE 0x016e
-#define CAM_GLOBALRESET 0x0170
-#define TIMER11_PWM_EVT 0x0172
-#define TIMER5_PWM_EVT 0x0174
-#define TIMER6_PWM_EVT 0x0176
-#define TIMER8_PWM_EVT 0x0178
-#define I2C3_SCL 0x017a
-#define I2C3_SDA 0x017c
-#define GPIO8_233 0x017e
-#define GPIO8_234 0x0180
-#define ABE_CLKS 0x0182
-#define ABEDMIC_DIN1 0x0184
-#define ABEDMIC_DIN2 0x0186
-#define ABEDMIC_DIN3 0x0188
-#define ABEDMIC_CLK1 0x018a
-#define ABEDMIC_CLK2 0x018c
-#define ABEDMIC_CLK3 0x018e
-#define ABESLIMBUS1_CLOCK 0x0190
-#define ABESLIMBUS1_DATA 0x0192
-#define ABEMCBSP2_DR 0x0194
-#define ABEMCBSP2_DX 0x0196
-#define ABEMCBSP2_FSX 0x0198
-#define ABEMCBSP2_CLKX 0x019a
-#define ABEMCPDM_UL_DATA 0x019c
-#define ABEMCPDM_DL_DATA 0x019e
-#define ABEMCPDM_FRAME 0x01a0
-#define ABEMCPDM_LB_CLK 0x01a2
-#define WLSDIO_CLK 0x01a4
-#define WLSDIO_CMD 0x01a6
-#define WLSDIO_DATA0 0x01a8
-#define WLSDIO_DATA1 0x01aa
-#define WLSDIO_DATA2 0x01ac
-#define WLSDIO_DATA3 0x01ae
-#define UART5_RX 0x01b0
-#define UART5_TX 0x01b2
-#define UART5_CTS 0x01b4
-#define UART5_RTS 0x01b6
-#define I2C2_SCL 0x01b8
-#define I2C2_SDA 0x01ba
-#define MCSPI1_CLK 0x01bc
-#define MCSPI1_SOMI 0x01be
-#define MCSPI1_SIMO 0x01c0
-#define MCSPI1_CS0 0x01c2
-#define MCSPI1_CS1 0x01c4
-#define I2C5_SCL 0x01c6
-#define I2C5_SDA 0x01c8
-#define PERSLIMBUS2_CLOCK 0x01ca
-#define PERSLIMBUS2_DATA 0x01cc
-#define UART6_TX 0x01ce
-#define UART6_RX 0x01d0
-#define UART6_CTS 0x01d2
-#define UART6_RTS 0x01d4
-#define UART3_CTS_RCTX 0x01d6
-#define UART3_RTS_IRSD 0x01d8
-#define UART3_TX_IRTX 0x01da
-#define UART3_RX_IRRX 0x01dc
-#define USBB3_HSIC_STROBE 0x01de
-#define USBB3_HSIC_DATA 0x01e0
-#define SDCARD_CLK 0x01e2
-#define SDCARD_CMD 0x01e4
-#define SDCARD_DATA2 0x01e6
-#define SDCARD_DATA3 0x01e8
-#define SDCARD_DATA0 0x01ea
-#define SDCARD_DATA1 0x01ec
-#define USBD0_HS_DP 0x01ee
-#define USBD0_HS_DM 0x01f0
-#define I2C1_PMIC_SCL 0x01f2
-#define I2C1_PMIC_SDA 0x01f4
-#define USBD0_SS_RX 0x01f6
-
-#define LLIA_WAKEREQIN 0x0040
-#define LLIB_WAKEREQIN 0x0042
-#define DRM_EMU0 0x0044
-#define DRM_EMU1 0x0046
-#define JTAG_NTRST 0x0048
-#define JTAG_TCK 0x004a
-#define JTAG_RTCK 0x004c
-#define JTAG_TMSC 0x004e
-#define JTAG_TDI 0x0050
-#define JTAG_TDO 0x0052
-#define SYS_32K 0x0054
-#define FREF_CLK_IOREQ 0x0056
-#define FREF_CLK0_OUT 0x0058
-#define FREF_CLK1_OUT 0x005a
-#define FREF_CLK2_OUT 0x005c
-#define FREF_CLK2_REQ 0x005e
-#define FREF_CLK1_REQ 0x0060
-#define SYS_NRESPWRON 0x0062
-#define SYS_NRESWARM 0x0064
-#define SYS_PWR_REQ 0x0066
-#define SYS_NIRQ1 0x0068
-#define SYS_NIRQ2 0x006a
-#define SR_PMIC_SCL 0x006c
-#define SR_PMIC_SDA 0x006e
-#define SYS_BOOT0 0x0070
-#define SYS_BOOT1 0x0072
-#define SYS_BOOT2 0x0074
-#define SYS_BOOT3 0x0076
-#define SYS_BOOT4 0x0078
-#define SYS_BOOT5 0x007a
-
-#endif /* _MUX_OMAP5_H_ */
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
deleted file mode 100644
index a9c0421..0000000
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- *
- * Authors:
- * Aneesh V <aneesh@ti.com>
- * Sricharan R <r.sricharan@ti.com>
- */
-
-#ifndef _OMAP5_H_
-#define _OMAP5_H_
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
-
-#include <linux/sizes.h>
-
-/*
- * L4 Peripherals - L4 Wakeup and L4 Core now
- */
-#define OMAP54XX_L4_CORE_BASE 0x4A000000
-#define OMAP54XX_L4_WKUP_BASE 0x4Ae00000
-#define OMAP54XX_L4_PER_BASE 0x48000000
-
-/* CONTROL ID CODE */
-#define CONTROL_CORE_ID_CODE 0x4A002204
-#define CONTROL_WKUP_ID_CODE 0x4AE0C204
-
-#if defined(CONFIG_DRA7XX)
-#define CONTROL_ID_CODE CONTROL_WKUP_ID_CODE
-#else
-#define CONTROL_ID_CODE CONTROL_CORE_ID_CODE
-#endif
-
-#if defined(CONFIG_DRA7XX)
-#define DRA7_USB_OTG_SS1_BASE 0x48890000
-#define DRA7_USB_OTG_SS1_GLUE_BASE 0x48880000
-#define DRA7_USB3_PHY1_PLL_CTRL 0x4A084C00
-#define DRA7_USB3_PHY1_POWER 0x4A002370
-#define DRA7_USB2_PHY1_POWER 0x4A002300
-
-#define DRA7_USB_OTG_SS2_BASE 0x488D0000
-#define DRA7_USB_OTG_SS2_GLUE_BASE 0x488C0000
-#define DRA7_USB2_PHY2_POWER 0x4A002E74
-#else
-#define OMAP5XX_USB_OTG_SS_BASE 0x4A030000
-#define OMAP5XX_USB_OTG_SS_GLUE_BASE 0x4A020000
-#define OMAP5XX_USB3_PHY_PLL_CTRL 0x4A084C00
-#define OMAP5XX_USB3_PHY_POWER 0x4A002370
-#define OMAP5XX_USB2_PHY_POWER 0x4A002300
-#endif
-
-/* To be verified */
-#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F
-#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F
-#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
-#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F
-#define DRA762_CONTROL_ID_CODE_ES1_0 0x0BB5002F
-#define DRA752_CONTROL_ID_CODE_ES1_0 0x0B99002F
-#define DRA752_CONTROL_ID_CODE_ES1_1 0x1B99002F
-#define DRA752_CONTROL_ID_CODE_ES2_0 0x2B99002F
-#define DRA722_CONTROL_ID_CODE_ES1_0 0x0B9BC02F
-#define DRA722_CONTROL_ID_CODE_ES2_0 0x1B9BC02F
-#define DRA722_CONTROL_ID_CODE_ES2_1 0x2B9BC02F
-
-#define DRA762_ABZ_PACKAGE 0x2
-#define DRA762_ACD_PACKAGE 0x3
-
-/* UART */
-#define UART1_BASE (OMAP54XX_L4_PER_BASE + 0x6a000)
-#define UART2_BASE (OMAP54XX_L4_PER_BASE + 0x6c000)
-#define UART3_BASE (OMAP54XX_L4_PER_BASE + 0x20000)
-#define UART4_BASE (OMAP54XX_L4_PER_BASE + 0x6e000)
-
-/* General Purpose Timers */
-#define GPT1_BASE (OMAP54XX_L4_WKUP_BASE + 0x18000)
-#define GPT2_BASE (OMAP54XX_L4_PER_BASE + 0x32000)
-#define GPT3_BASE (OMAP54XX_L4_PER_BASE + 0x34000)
-
-/* Watchdog Timer2 - MPU watchdog */
-#define WDT2_BASE (OMAP54XX_L4_WKUP_BASE + 0x14000)
-
-/* QSPI */
-#define QSPI_BASE 0x4B300000
-
-/* SATA */
-#define DWC_AHSATA_BASE 0x4A140000
-
-/*
- * Hardware Register Details
- */
-
-/* Watchdog Timer */
-#define WD_UNLOCK1 0xAAAA
-#define WD_UNLOCK2 0x5555
-
-/* GP Timer */
-#define TCLR_ST (0x1 << 0)
-#define TCLR_AR (0x1 << 1)
-#define TCLR_PRE (0x1 << 5)
-
-/* Control Module */
-#define LDOSRAM_ACTMODE_VSET_IN_MASK (0x1F << 5)
-#define LDOSRAM_VOLT_CTRL_OVERRIDE 0x0401040f
-#define CONTROL_EFUSE_1_OVERRIDE 0x1C4D0110
-#define CONTROL_EFUSE_2_OVERRIDE 0x00084000
-
-/* LPDDR2 IO regs */
-#define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN 0x1C1C1C1C
-#define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER 0x9E9E9E9E
-#define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN 0x7C7C7C7C
-#define LPDDR2IO_GR10_WD_MASK (3 << 17)
-#define CONTROL_LPDDR2IO_3_VAL 0xA0888C00
-
-/* CONTROL_EFUSE_2 */
-#define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1 0x00ffc000
-
-#define SDCARD_BIAS_PWRDNZ (1 << 27)
-#define SDCARD_PWRDNZ (1 << 26)
-#define SDCARD_BIAS_HIZ_MODE (1 << 25)
-#define SDCARD_PBIASLITE_VMODE (1 << 21)
-
-#ifndef __ASSEMBLY__
-
-struct s32ktimer {
- unsigned char res[0x10];
- unsigned int s32k_cr; /* 0x10 */
-};
-
-#define DEVICE_TYPE_SHIFT 0x6
-#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
-
-/* Output impedance control */
-#define ds_120_ohm 0x0
-#define ds_60_ohm 0x1
-#define ds_45_ohm 0x2
-#define ds_30_ohm 0x3
-#define ds_mask 0x3
-
-/* Slew rate control */
-#define sc_slow 0x0
-#define sc_medium 0x1
-#define sc_fast 0x2
-#define sc_na 0x3
-#define sc_mask 0x3
-
-/* Target capacitance control */
-#define lb_5_12_pf 0x0
-#define lb_12_25_pf 0x1
-#define lb_25_50_pf 0x2
-#define lb_50_80_pf 0x3
-#define lb_mask 0x3
-
-#define usb_i_mask 0x7
-
-#define DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN 0x80828082
-#define DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN 0x82828200
-#define DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL 0x8421
-#define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084
-#define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
-
-#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C
-#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464
-#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631
-#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC
-#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0
-
-#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C
-#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464
-#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631
-#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC
-#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000
-
-#define EFUSE_1 0x45145100
-#define EFUSE_2 0x45145100
-#define EFUSE_3 0x45145100
-#define EFUSE_4 0x45145100
-#endif /* __ASSEMBLY__ */
-
-/*
- * In all cases, the TRM defines the RAM Memory Map for the processor
- * and indicates the area for the downloaded image. We use all of that
- * space for download and once up and running may use other parts of the
- * map for our needs. We set a scratch space that is at the end of the
- * OMAP5 download area, but within the DRA7xx download area (as it is
- * much larger) and do not, at this time, make use of the additional
- * space.
- */
-#if defined(CONFIG_DRA7XX)
-#define NON_SECURE_SRAM_START 0x40300000
-#define NON_SECURE_SRAM_END 0x40380000 /* Not inclusive */
-#define NON_SECURE_SRAM_IMG_END 0x4037C000
-#else
-#define NON_SECURE_SRAM_START 0x40300000
-#define NON_SECURE_SRAM_END 0x40320000 /* Not inclusive */
-#define NON_SECURE_SRAM_IMG_END 0x4031E000
-#endif
-#define SRAM_SCRATCH_SPACE_ADDR (NON_SECURE_SRAM_IMG_END - SZ_1K)
-
-/* base address for indirect vectors (internal boot mode) */
-#define SRAM_ROM_VECT_BASE 0x4031F000
-
-/* CONTROL_SRCOMP_XXX_SIDE */
-#define OVERRIDE_XS_SHIFT 30
-#define OVERRIDE_XS_MASK (1 << 30)
-#define SRCODE_READ_XS_SHIFT 12
-#define SRCODE_READ_XS_MASK (0xff << 12)
-#define PWRDWN_XS_SHIFT 11
-#define PWRDWN_XS_MASK (1 << 11)
-#define DIVIDE_FACTOR_XS_SHIFT 4
-#define DIVIDE_FACTOR_XS_MASK (0x7f << 4)
-#define MULTIPLY_FACTOR_XS_SHIFT 1
-#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1)
-#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0
-#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0)
-
-/* ABB settings */
-#define OMAP_ABB_SETTLING_TIME 50
-#define OMAP_ABB_CLOCK_CYCLES 16
-
-/* ABB tranxdone mask */
-#define OMAP_ABB_MPU_TXDONE_MASK (0x1 << 7)
-#define OMAP_ABB_MM_TXDONE_MASK (0x1 << 31)
-#define OMAP_ABB_IVA_TXDONE_MASK (0x1 << 30)
-#define OMAP_ABB_EVE_TXDONE_MASK (0x1 << 29)
-#define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28)
-
-/* ABB efuse masks */
-#define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20)
-#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25)
-#define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20)
-#define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25)
-#define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10)
-#define OMAP5_ABB_LDOVBBMPU_VSET_OUT_MASK (0x1f << 0)
-
-#ifndef __ASSEMBLY__
-struct srcomp_params {
- s8 divide_factor;
- s8 multiply_factor;
-};
-
-struct ctrl_ioregs {
- u32 ctrl_ddrch;
- u32 ctrl_lpddr2ch;
- u32 ctrl_ddr3ch;
- u32 ctrl_ddrio_0;
- u32 ctrl_ddrio_1;
- u32 ctrl_ddrio_2;
- u32 ctrl_emif_sdram_config_ext;
- u32 ctrl_emif_sdram_config_ext_final;
- u32 ctrl_ddr_ctrl_ext_0;
-};
-
-void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits);
-
-#endif /* __ASSEMBLY__ */
-
-/* Boot parameters */
-#ifndef __ASSEMBLY__
-struct omap_boot_parameters {
- unsigned int boot_message;
- unsigned int boot_device_descriptor;
- unsigned char boot_device;
- unsigned char reset_reason;
- unsigned char ch_flags;
-};
-#endif
-
-#endif
diff --git a/arch/arm/include/asm/arch-omap5/sata.h b/arch/arm/include/asm/arch-omap5/sata.h
deleted file mode 100644
index 96c84fc..0000000
--- a/arch/arm/include/asm/arch-omap5/sata.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * SATA Wrapper Register map
- *
- * (C) Copyright 2013
- * Texas Instruments, <www.ti.com>
- */
-
-#ifndef _TI_SATA_H
-#define _TI_SATA_H
-
-/* SATA Wrapper module */
-#define TI_SATA_WRAPPER_BASE (OMAP54XX_L4_CORE_BASE + 0x141100)
-/* SATA PHY Module */
-#define TI_SATA_PLLCTRL_BASE (OMAP54XX_L4_CORE_BASE + 0x96800)
-
-/* SATA Wrapper register offsets */
-#define TI_SATA_SYSCONFIG 0x00
-#define TI_SATA_CDRLOCK 0x04
-
-/* Register Set */
-#define TI_SATA_SYSCONFIG_OVERRIDE0 (1 << 16)
-#define TI_SATA_SYSCONFIG_STANDBY_MASK (0x3 << 4)
-#define TI_SATA_SYSCONFIG_IDLE_MASK (0x3 << 2)
-
-/* Standby modes */
-#define TI_SATA_STANDBY_FORCE 0x0
-#define TI_SATA_STANDBY_NO (0x1 << 4)
-#define TI_SATA_STANDBY_SMART_WAKE (0x3 << 4)
-#define TI_SATA_STANDBY_SMART (0x2 << 4)
-
-/* Idle modes */
-#define TI_SATA_IDLE_FORCE 0x0
-#define TI_SATA_IDLE_NO (0x1 << 2)
-#define TI_SATA_IDLE_SMART_WAKE (0x3 << 2)
-#define TI_SATA_IDLE_SMART (0x2 << 2)
-
-#endif /* _TI_SATA_H */
diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h
deleted file mode 100644
index cda3b46..0000000
--- a/arch/arm/include/asm/arch-omap5/spl.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NONE 0x00
-#define BOOT_DEVICE_XIP 0x01
-#define BOOT_DEVICE_XIPWAIT 0x02
-#define BOOT_DEVICE_NAND 0x03
-#define BOOT_DEVICE_ONENAND 0x04
-#define BOOT_DEVICE_MMC1 0x05
-#define BOOT_DEVICE_MMC2 0x06
-#define BOOT_DEVICE_MMC2_2 0x07
-#define BOOT_DEVICE_SATA 0x09
-#define BOOT_DEVICE_SPI 0x0A
-#define BOOT_DEVICE_QSPI_1 0x0A
-#define BOOT_DEVICE_QSPI_4 0x0B
-#define BOOT_DEVICE_UART 0x43
-#define BOOT_DEVICE_DFU 0x45
-
-#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1
-#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2
-#endif
diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h
deleted file mode 100644
index 80b0c93..0000000
--- a/arch/arm/include/asm/arch-omap5/sys_proto.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Texas Instruments, <www.ti.com>
- */
-
-#ifndef _SYS_PROTO_H_
-#define _SYS_PROTO_H_
-
-#include <asm/arch/omap.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/omap_common.h>
-#include <linux/mtd/omap_gpmc.h>
-#include <asm/arch/clock.h>
-#include <asm/ti-common/sys_proto.h>
-
-/*
- * Structure for Iodelay configuration registers.
- * Theoretical max for g_delay is 21560 ps.
- * Theoretical max for a_delay is 1/3rd of g_delay max.
- * So using u16 for both a/g_delay.
- */
-struct iodelay_cfg_entry {
- u16 offset;
- u16 a_delay;
- u16 g_delay;
-};
-
-struct pad_conf_entry {
- u32 offset;
- u32 val;
-};
-
-struct mmc_platform_fixups {
- const char *hw_rev;
- u32 unsupported_caps;
- u32 max_freq;
-};
-
-struct omap_sysinfo {
- char *board_string;
-};
-extern const struct omap_sysinfo sysinfo;
-
-void gpmc_init(void);
-void watchdog_init(void);
-u32 get_device_type(void);
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
-void do_set_mux32(u32 base, struct pad_conf_entry const *array, int size);
-void set_muxconf_regs(void);
-u32 wait_on_value(u32, u32, void *, u32);
-void sdelay(unsigned long);
-void setup_early_clocks(void);
-void prcm_init(void);
-void do_board_detect(void);
-void vcores_init(void);
-void bypass_dpll(u32 const base);
-void freq_update_core(void);
-u32 get_sys_clk_freq(void);
-u32 omap5_ddr_clk(void);
-void cancel_out(u32 *num, u32 *den, u32 den_limit);
-void sdram_init(void);
-u32 omap_sdram_size(void);
-u32 cortex_rev(void);
-void save_omap_boot_params(void);
-void init_omap_revision(void);
-void init_package_revision(void);
-void do_io_settings(void);
-void sri2c_init(void);
-int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
-u32 warm_reset(void);
-void force_emif_self_refresh(void);
-void get_ioregs(const struct ctrl_ioregs **regs);
-void srcomp_enable(void);
-void setup_warmreset_time(void);
-const struct mmc_platform_fixups *platform_fixups_mmc(uint32_t addr);
-
-static inline u32 div_round_up(u32 num, u32 den)
-{
- return (num + den - 1)/den;
-}
-
-static inline u32 usec_to_32k(u32 usec)
-{
- return div_round_up(32768 * usec, 1000000);
-}
-
-#define OMAP5_SERVICE_L2ACTLR_SET 0x104
-#define OMAP5_SERVICE_ACR_SET 0x107
-
-#endif
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