diff options
Diffstat (limited to 'arch/arm/include/asm/arch-sunxi')
43 files changed, 0 insertions, 6653 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h b/arch/arm/include/asm/arch-sunxi/boot0.h deleted file mode 100644 index 54c144a..0000000 --- a/arch/arm/include/asm/arch-sunxi/boot0.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Allwinner A64 (sun50i) CPU - */ - -#if defined(CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER) && !defined(CONFIG_SPL_BUILD) -/* reserve space for BOOT0 header information */ - b reset - .space 1532 -#elif defined(CONFIG_ARM_BOOT_HOOK_RMR) -/* - * Switch into AArch64 if needed. - * Refer to arch/arm/mach-sunxi/rmr_switch.S for the original source. - */ - tst x0, x0 // this is "b #0x84" in ARM - b reset - .space 0x7c - .word 0xe59f1024 // ldr r1, [pc, #36] ; 0x170000a0 - .word 0xe59f0024 // ldr r0, [pc, #36] ; CONFIG_*_TEXT_BASE - .word 0xe5810000 // str r0, [r1] - .word 0xf57ff04f // dsb sy - .word 0xf57ff06f // isb sy - .word 0xee1c0f50 // mrc 15, 0, r0, cr12, cr0, {2} ; RMR - .word 0xe3800003 // orr r0, r0, #3 - .word 0xee0c0f50 // mcr 15, 0, r0, cr12, cr0, {2} ; RMR - .word 0xf57ff06f // isb sy - .word 0xe320f003 // wfi - .word 0xeafffffd // b @wfi -#ifndef CONFIG_MACH_SUN50I_H6 - .word 0x017000a0 // writeable RVBAR mapping address -#else - .word 0x09010040 // writeable RVBAR mapping address -#endif -#ifdef CONFIG_SPL_BUILD - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif -#else -/* normal execution */ - b reset -#endif diff --git a/arch/arm/include/asm/arch-sunxi/ccu.h b/arch/arm/include/asm/arch-sunxi/ccu.h deleted file mode 100644 index 5dd97ab..0000000 --- a/arch/arm/include/asm/arch-sunxi/ccu.h +++ /dev/null @@ -1,96 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2018 Amarula Solutions. - * Author: Jagan Teki <jagan@amarulasolutions.com> - */ - -#ifndef _ASM_ARCH_CCU_H -#define _ASM_ARCH_CCU_H - -/** - * enum ccu_flags - ccu clock/reset flags - * - * @CCU_CLK_F_IS_VALID: is given clock gate is valid? - * @CCU_RST_F_IS_VALID: is given reset control is valid? - */ -enum ccu_flags { - CCU_CLK_F_IS_VALID = BIT(0), - CCU_RST_F_IS_VALID = BIT(1), -}; - -/** - * struct ccu_clk_gate - ccu clock gate - * @off: gate offset - * @bit: gate bit - * @flags: ccu clock gate flags - */ -struct ccu_clk_gate { - u16 off; - u32 bit; - enum ccu_flags flags; -}; - -#define GATE(_off, _bit) { \ - .off = _off, \ - .bit = _bit, \ - .flags = CCU_CLK_F_IS_VALID, \ -} - -/** - * struct ccu_reset - ccu reset - * @off: reset offset - * @bit: reset bit - * @flags: ccu reset control flags - */ -struct ccu_reset { - u16 off; - u32 bit; - enum ccu_flags flags; -}; - -#define RESET(_off, _bit) { \ - .off = _off, \ - .bit = _bit, \ - .flags = CCU_RST_F_IS_VALID, \ -} - -/** - * struct ccu_desc - clock control unit descriptor - * - * @gates: clock gates - * @resets: reset unit - */ -struct ccu_desc { - const struct ccu_clk_gate *gates; - const struct ccu_reset *resets; -}; - -/** - * struct ccu_priv - sunxi clock control unit - * - * @base: base address - * @desc: ccu descriptor - */ -struct ccu_priv { - void *base; - const struct ccu_desc *desc; -}; - -/** - * sunxi_clk_probe - common sunxi clock probe - * @dev: clock device - */ -int sunxi_clk_probe(struct udevice *dev); - -extern struct clk_ops sunxi_clk_ops; - -/** - * sunxi_reset_bind() - reset binding - * - * @dev: reset device - * @count: reset count - * @return 0 success, or error value - */ -int sunxi_reset_bind(struct udevice *dev, ulong count); - -#endif /* _ASM_ARCH_CCU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h deleted file mode 100644 index 5994130..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_CLOCK_H -#define _SUNXI_CLOCK_H - -#include <linux/types.h> - -#define CLK_GATE_OPEN 0x1 -#define CLK_GATE_CLOSE 0x0 - -/* clock control module regs definition */ -#if defined(CONFIG_MACH_SUN8I_A83T) -#include <asm/arch/clock_sun8i_a83t.h> -#elif defined(CONFIG_MACH_SUN50I_H6) -#include <asm/arch/clock_sun50i_h6.h> -#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ - defined(CONFIG_MACH_SUN50I) -#include <asm/arch/clock_sun6i.h> -#elif defined(CONFIG_MACH_SUN9I) -#include <asm/arch/clock_sun9i.h> -#else -#include <asm/arch/clock_sun4i.h> -#endif - -#ifndef __ASSEMBLY__ -int clock_init(void); -int clock_twi_onoff(int port, int state); -void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz); -void clock_init_safe(void); -void clock_init_sec(void); -void clock_init_uart(void); -#endif - -#endif /* _SUNXI_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h b/arch/arm/include/asm/arch-sunxi/clock_sun4i.h deleted file mode 100644 index 2cec91c..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h +++ /dev/null @@ -1,362 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun4i, sun5i and sun7i clock register definitions - * - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_CLOCK_SUN4I_H -#define _SUNXI_CLOCK_SUN4I_H - -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x00 pll1 control */ - u32 pll1_tun; /* 0x04 pll1 tuning */ - u32 pll2_cfg; /* 0x08 pll2 control */ - u32 pll2_tun; /* 0x0c pll2 tuning */ - u32 pll3_cfg; /* 0x10 pll3 control */ - u8 res0[0x4]; - u32 pll4_cfg; /* 0x18 pll4 control */ - u8 res1[0x4]; - u32 pll5_cfg; /* 0x20 pll5 control */ - u32 pll5_tun; /* 0x24 pll5 tuning */ - u32 pll6_cfg; /* 0x28 pll6 control */ - u32 pll6_tun; /* 0x2c pll6 tuning */ - u32 pll7_cfg; /* 0x30 pll7 control */ - u32 pll1_tun2; /* 0x34 pll5 tuning2 */ - u8 res2[0x4]; - u32 pll5_tun2; /* 0x3c pll5 tuning2 */ - u8 res3[0xc]; - u32 pll_lock_dbg; /* 0x4c pll lock time debug */ - u32 osc24m_cfg; /* 0x50 osc24m control */ - u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ - u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ - u32 axi_gate; /* 0x5c axi module clock gating */ - u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ - u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ - u32 apb0_gate; /* 0x68 apb0 module clock gating */ - u32 apb1_gate; /* 0x6c apb1 module clock gating */ - u8 res4[0x10]; - u32 nand0_clk_cfg; /* 0x80 nand sub clock control */ - u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ - u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ - u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ - u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ - u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ - u32 ts_clk_cfg; /* 0x98 transport stream clock control */ - u32 ss_clk_cfg; /* 0x9c */ - u32 spi0_clk_cfg; /* 0xa0 */ - u32 spi1_clk_cfg; /* 0xa4 */ - u32 spi2_clk_cfg; /* 0xa8 */ - u32 pata_clk_cfg; /* 0xac */ - u32 ir0_clk_cfg; /* 0xb0 */ - u32 ir1_clk_cfg; /* 0xb4 */ - u32 iis_clk_cfg; /* 0xb8 */ - u32 ac97_clk_cfg; /* 0xbc */ - u32 spdif_clk_cfg; /* 0xc0 */ - u32 keypad_clk_cfg; /* 0xc4 */ - u32 sata_clk_cfg; /* 0xc8 */ - u32 usb_clk_cfg; /* 0xcc */ - u32 gps_clk_cfg; /* 0xd0 */ - u32 spi3_clk_cfg; /* 0xd4 */ - u8 res5[0x28]; - u32 dram_clk_gate; /* 0x100 */ - u32 be0_clk_cfg; /* 0x104 */ - u32 be1_clk_cfg; /* 0x108 */ - u32 fe0_clk_cfg; /* 0x10c */ - u32 fe1_clk_cfg; /* 0x110 */ - u32 mp_clk_cfg; /* 0x114 */ - u32 lcd0_ch0_clk_cfg; /* 0x118 */ - u32 lcd1_ch0_clk_cfg; /* 0x11c */ - u32 csi_isp_clk_cfg; /* 0x120 */ - u8 res6[0x4]; - u32 tvd_clk_reg; /* 0x128 */ - u32 lcd0_ch1_clk_cfg; /* 0x12c */ - u32 lcd1_ch1_clk_cfg; /* 0x130 */ - u32 csi0_clk_cfg; /* 0x134 */ - u32 csi1_clk_cfg; /* 0x138 */ - u32 ve_clk_cfg; /* 0x13c */ - u32 audio_codec_clk_cfg; /* 0x140 */ - u32 avs_clk_cfg; /* 0x144 */ - u32 ace_clk_cfg; /* 0x148 */ - u32 lvds_clk_cfg; /* 0x14c */ - u32 hdmi_clk_cfg; /* 0x150 */ - u32 mali_clk_cfg; /* 0x154 */ - u8 res7[0x4]; - u32 mbus_clk_cfg; /* 0x15c */ - u8 res8[0x4]; - u32 gmac_clk_cfg; /* 0x164 */ -}; - -/* apb1 bit field */ -#define APB1_CLK_SRC_OSC24M (0x0 << 24) -#define APB1_CLK_SRC_PLL6 (0x1 << 24) -#define APB1_CLK_SRC_LOSC (0x2 << 24) -#define APB1_CLK_SRC_MASK (0x3 << 24) -#define APB1_CLK_RATE_N_1 (0x0 << 16) -#define APB1_CLK_RATE_N_2 (0x1 << 16) -#define APB1_CLK_RATE_N_4 (0x2 << 16) -#define APB1_CLK_RATE_N_8 (0x3 << 16) -#define APB1_CLK_RATE_N_MASK (3 << 16) -#define APB1_CLK_RATE_M(m) (((m)-1) << 0) -#define APB1_CLK_RATE_M_MASK (0x1f << 0) - -/* apb1 gate field */ -#define APB1_GATE_UART_SHIFT (16) -#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) -#define APB1_GATE_TWI_SHIFT (0) -#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) - -/* clock divide */ -#define AXI_DIV_SHIFT (0) -#define AXI_DIV_1 0 -#define AXI_DIV_2 1 -#define AXI_DIV_3 2 -#define AXI_DIV_4 3 -#define AHB_DIV_SHIFT (4) -#define AHB_DIV_1 0 -#define AHB_DIV_2 1 -#define AHB_DIV_4 2 -#define AHB_DIV_8 3 -#define APB0_DIV_SHIFT (8) -#define APB0_DIV_1 0 -#define APB0_DIV_2 1 -#define APB0_DIV_4 2 -#define APB0_DIV_8 3 -#define CPU_CLK_SRC_SHIFT (16) -#define CPU_CLK_SRC_OSC24M 1 -#define CPU_CLK_SRC_PLL1 2 - -#define CCM_PLL1_CFG_ENABLE_SHIFT 31 -#define CCM_PLL1_CFG_VCO_RST_SHIFT 30 -#define CCM_PLL1_CFG_VCO_BIAS_SHIFT 26 -#define CCM_PLL1_CFG_PLL4_EXCH_SHIFT 25 -#define CCM_PLL1_CFG_BIAS_CUR_SHIFT 20 -#define CCM_PLL1_CFG_DIVP_SHIFT 16 -#define CCM_PLL1_CFG_LCK_TMR_SHIFT 13 -#define CCM_PLL1_CFG_FACTOR_N_SHIFT 8 -#define CCM_PLL1_CFG_FACTOR_K_SHIFT 4 -#define CCM_PLL1_CFG_SIG_DELT_PAT_IN_SHIFT 3 -#define CCM_PLL1_CFG_SIG_DELT_PAT_EN_SHIFT 2 -#define CCM_PLL1_CFG_FACTOR_M_SHIFT 0 - -#define PLL1_CFG_DEFAULT 0xa1005000 - -#if defined CONFIG_OLD_SUNXI_KERNEL_COMPAT && defined CONFIG_MACH_SUN5I -/* - * Older linux-sunxi-3.4 kernels override our PLL6 setting with 300 MHz, - * halving the mbus frequency, so set it to 300 MHz ourselves and base the - * mbus divider on that. - */ -#define PLL6_CFG_DEFAULT 0xa1009900 -#else -#define PLL6_CFG_DEFAULT 0xa1009911 -#endif - -/* nand clock */ -#define NAND_CLK_SRC_OSC24 0 -#define NAND_CLK_DIV_N 0 -#define NAND_CLK_DIV_M 0 - -/* gps clock */ -#define GPS_SCLK_GATING_OFF 0 -#define GPS_RESET 0 - -/* ahb clock gate bit offset */ -#define AHB_GATE_OFFSET_GPS 26 -#define AHB_GATE_OFFSET_SATA 25 -#define AHB_GATE_OFFSET_PATA 24 -#define AHB_GATE_OFFSET_SPI3 23 -#define AHB_GATE_OFFSET_SPI2 22 -#define AHB_GATE_OFFSET_SPI1 21 -#define AHB_GATE_OFFSET_SPI0 20 -#define AHB_GATE_OFFSET_TS0 18 -#define AHB_GATE_OFFSET_EMAC 17 -#define AHB_GATE_OFFSET_ACE 16 -#define AHB_GATE_OFFSET_DLL 15 -#define AHB_GATE_OFFSET_SDRAM 14 -#define AHB_GATE_OFFSET_NAND0 13 -#define AHB_GATE_OFFSET_MS 12 -#define AHB_GATE_OFFSET_MMC3 11 -#define AHB_GATE_OFFSET_MMC2 10 -#define AHB_GATE_OFFSET_MMC1 9 -#define AHB_GATE_OFFSET_MMC0 8 -#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) -#define AHB_GATE_OFFSET_BIST 7 -#define AHB_GATE_OFFSET_DMA 6 -#define AHB_GATE_OFFSET_SS 5 -#define AHB_GATE_OFFSET_USB_OHCI1 4 -#define AHB_GATE_OFFSET_USB_EHCI1 3 -#define AHB_GATE_OFFSET_USB_OHCI0 2 -#define AHB_GATE_OFFSET_USB_EHCI0 1 -#define AHB_GATE_OFFSET_USB0 0 - -/* ahb clock gate bit offset (second register) */ -#define AHB_GATE_OFFSET_GMAC 17 -#define AHB_GATE_OFFSET_DE_FE0 14 -#define AHB_GATE_OFFSET_DE_BE0 12 -#define AHB_GATE_OFFSET_HDMI 11 -#define AHB_GATE_OFFSET_LCD1 5 -#define AHB_GATE_OFFSET_LCD0 4 -#define AHB_GATE_OFFSET_TVE1 3 -#define AHB_GATE_OFFSET_TVE0 2 - -#define CCM_AHB_GATE_GPS (0x1 << 26) -#define CCM_AHB_GATE_SDRAM (0x1 << 14) -#define CCM_AHB_GATE_DLL (0x1 << 15) -#define CCM_AHB_GATE_ACE (0x1 << 16) - -#define CCM_PLL3_CTRL_M_SHIFT 0 -#define CCM_PLL3_CTRL_M_MASK (0x7f << CCM_PLL3_CTRL_M_SHIFT) -#define CCM_PLL3_CTRL_M(n) (((n) & 0x7f) << 0) -#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 15) -#define CCM_PLL3_CTRL_EN (0x1 << 31) - -#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) -#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3) -#define CCM_PLL5_CTRL_M_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2) -#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) -#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) -#define CCM_PLL5_CTRL_K_SHIFT 4 -#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) -#define CCM_PLL5_CTRL_K_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_LDO (0x1 << 7) -#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) -#define CCM_PLL5_CTRL_N_SHIFT 8 -#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) -#define CCM_PLL5_CTRL_N_X(n) (n) -#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) -#define CCM_PLL5_CTRL_P_SHIFT 16 -#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) -#define CCM_PLL5_CTRL_P_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_BW (0x1 << 18) -#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) -#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20) -#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f) -#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1) -#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25) -#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29) -#define CCM_PLL5_CTRL_BYPASS (0x1 << 30) -#define CCM_PLL5_CTRL_EN (0x1 << 31) - -#define CCM_PLL6_CTRL_EN 31 -#define CCM_PLL6_CTRL_BYPASS_EN 30 -#define CCM_PLL6_CTRL_SATA_EN_SHIFT 14 -#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_K_SHIFT 4 -#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) - -#define CCM_GPS_CTRL_RESET (0x1 << 0) -#define CCM_GPS_CTRL_GATE (0x1 << 1) - -#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15) - -#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) -#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) -#define CCM_MBUS_CTRL_M_X(n) ((n) - 1) -#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) -#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) -#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) -#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) -#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) -#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 -#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 -#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 -#define CCM_MBUS_CTRL_GATE (0x1 << 31) - -#define CCM_NAND_CTRL_M(x) ((x) - 1) -#define CCM_NAND_CTRL_N(x) ((x) << 16) -#define CCM_NAND_CTRL_OSCM24 (0x0 << 24) -#define CCM_NAND_CTRL_PLL6 (0x1 << 24) -#define CCM_NAND_CTRL_PLL5 (0x2 << 24) -#define CCM_NAND_CTRL_ENABLE (0x1 << 31) - -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) -#define CCM_MMC_CTRL_N(x) ((x) << 16) -#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) -#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) -#define CCM_MMC_CTRL_PLL6 (0x1 << 24) -#define CCM_MMC_CTRL_PLL5 (0x2 << 24) -#define CCM_MMC_CTRL_ENABLE (0x1 << 31) - -#define CCM_DRAM_GATE_OFFSET_DE_FE1 24 /* Note the order of FE1 and */ -#define CCM_DRAM_GATE_OFFSET_DE_FE0 25 /* FE0 is swapped ! */ -#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 -#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - -#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) -#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) -#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) -#define CCM_LCD_CH0_CTRL_MIPI_PLL 0 /* No mipi pll on sun4i/5i/7i */ -#ifdef CONFIG_MACH_SUN5I -#define CCM_LCD_CH0_CTRL_TVE_RST (0x1 << 29) -#else -#define CCM_LCD_CH0_CTRL_TVE_RST 0 /* No separate tve-rst on sun4i/7i */ -#endif -#define CCM_LCD_CH0_CTRL_RST (0x1 << 30) -#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) - -#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_LCD_CH1_CTRL_HALF_SCLK1 (1 << 11) -#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) -#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) -#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) -/* Enable / disable both ch1 sclk1 and sclk2 at the same time */ -#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31 | 0x1 << 15) - -#define CCM_LVDS_CTRL_RST (1 << 0) - -#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) -#define CCM_HDMI_CTRL_PLL3 (0 << 24) -#define CCM_HDMI_CTRL_PLL7 (1 << 24) -#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) -#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) -/* No separate ddc gate on sun4i, sun5i and sun7i */ -#define CCM_HDMI_CTRL_DDC_GATE 0 -#define CCM_HDMI_CTRL_GATE (0x1 << 31) - -#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 -#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 -#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 -#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) -#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) -#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) -#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) - -#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) -#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 6) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 7) -#define CCM_USB_CTRL_PHYGATE (0x1 << 8) -/* These 3 are sun6i only, define them as 0 on sun4i */ -#define CCM_USB_CTRL_PHY0_CLK 0 -#define CCM_USB_CTRL_PHY1_CLK 0 -#define CCM_USB_CTRL_PHY2_CLK 0 - -/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ -#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_DE_CTRL_PLL_MASK (3 << 24) -#define CCM_DE_CTRL_PLL3 (0 << 24) -#define CCM_DE_CTRL_PLL7 (1 << 24) -#define CCM_DE_CTRL_PLL5P (2 << 24) -#define CCM_DE_CTRL_RST (1 << 30) -#define CCM_DE_CTRL_GATE (1 << 31) - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int hz); -void clock_set_pll3(unsigned int hz); -unsigned int clock_get_pll3(void); -unsigned int clock_get_pll5p(void); -unsigned int clock_get_pll6(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h deleted file mode 100644 index e369370..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Allwinner H6 clock register definitions - * - * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SUNXI_CLOCK_SUN50I_H6_H -#define _SUNXI_CLOCK_SUN50I_H6_H - -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x000 pll1 (cpux) control */ - u8 reserved_0x004[12]; - u32 pll5_cfg; /* 0x010 pll5 (ddr) control */ - u8 reserved_0x014[12]; - u32 pll6_cfg; /* 0x020 pll6 (periph0) control */ - u8 reserved_0x020[4]; - u32 pll_periph1_cfg; /* 0x028 pll periph1 control */ - u8 reserved_0x028[4]; - u32 pll7_cfg; /* 0x030 pll7 (gpu) control */ - u8 reserved_0x034[12]; - u32 pll3_cfg; /* 0x040 pll3 (video0) control */ - u8 reserved_0x044[4]; - u32 pll_video1_cfg; /* 0x048 pll video1 control */ - u8 reserved_0x04c[12]; - u32 pll4_cfg; /* 0x058 pll4 (ve) control */ - u8 reserved_0x05c[4]; - u32 pll10_cfg; /* 0x060 pll10 (de) control */ - u8 reserved_0x064[12]; - u32 pll9_cfg; /* 0x070 pll9 (hsic) control */ - u8 reserved_0x074[4]; - u32 pll2_cfg; /* 0x078 pll2 (audio) control */ - u8 reserved_0x07c[148]; - u32 pll5_pat; /* 0x110 pll5 (ddr) pattern */ - u8 reserved_0x114[20]; - u32 pll_periph1_pat0; /* 0x128 pll periph1 pattern0 */ - u32 pll_periph1_pat1; /* 0x12c pll periph1 pattern1 */ - u32 pll7_pat0; /* 0x130 pll7 (gpu) pattern0 */ - u32 pll7_pat1; /* 0x134 pll7 (gpu) pattern1 */ - u8 reserved_0x138[8]; - u32 pll3_pat0; /* 0x140 pll3 (video0) pattern0 */ - u32 pll3_pat1; /* 0x144 pll3 (video0) pattern1 */ - u32 pll_video1_pat0; /* 0x148 pll video1 pattern0 */ - u32 pll_video1_pat1; /* 0x14c pll video1 pattern1 */ - u8 reserved_0x150[8]; - u32 pll4_pat0; /* 0x158 pll4 (ve) pattern0 */ - u32 pll4_pat1; /* 0x15c pll4 (ve) pattern1 */ - u32 pll10_pat0; /* 0x160 pll10 (de) pattern0 */ - u32 pll10_pat1; /* 0x164 pll10 (de) pattern1 */ - u8 reserved_0x168[8]; - u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */ - u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */ - u32 pll2_pat0; /* 0x178 pll2 (audio) pattern0 */ - u32 pll2_pat1; /* 0x17c pll2 (audio) pattern1 */ - u8 reserved_0x180[384]; - u32 pll1_bias; /* 0x300 pll1 (cpux) bias */ - u8 reserved_0x304[12]; - u32 pll5_bias; /* 0x310 pll5 (ddr) bias */ - u8 reserved_0x314[12]; - u32 pll6_bias; /* 0x320 pll6 (periph0) bias */ - u8 reserved_0x324[4]; - u32 pll_periph1_bias; /* 0x328 pll periph1 bias */ - u8 reserved_0x32c[4]; - u32 pll7_bias; /* 0x330 pll7 (gpu) bias */ - u8 reserved_0x334[12]; - u32 pll3_bias; /* 0x340 pll3 (video0) bias */ - u8 reserved_0x344[4]; - u32 pll_video1_bias; /* 0x348 pll video1 bias */ - u8 reserved_0x34c[12]; - u32 pll4_bias; /* 0x358 pll4 (ve) bias */ - u8 reserved_0x35c[4]; - u32 pll10_bias; /* 0x360 pll10 (de) bias */ - u8 reserved_0x364[12]; - u32 pll9_bias; /* 0x370 pll9 (hsic) bias */ - u8 reserved_0x374[4]; - u32 pll2_bias; /* 0x378 pll2 (audio) bias */ - u8 reserved_0x37c[132]; - u32 pll1_tun; /* 0x400 pll1 (cpux) tunning */ - u8 reserved_0x404[252]; - u32 cpu_axi_cfg; /* 0x500 CPUX/AXI clock control*/ - u8 reserved_0x504[12]; - u32 psi_ahb1_ahb2_cfg; /* 0x510 PSI/AHB1/AHB2 clock control */ - u8 reserved_0x514[8]; - u32 ahb3_cfg; /* 0x51c AHB3 clock control */ - u32 apb1_cfg; /* 0x520 APB1 clock control */ - u32 apb2_cfg; /* 0x524 APB2 clock control */ - u8 reserved_0x528[24]; - u32 mbus_cfg; /* 0x540 MBUS clock control */ - u8 reserved_0x544[188]; - u32 de_clk_cfg; /* 0x600 DE clock control */ - u8 reserved_0x604[8]; - u32 de_gate_reset; /* 0x60c DE gate/reset control */ - u8 reserved_0x610[16]; - u32 di_clk_cfg; /* 0x620 DI clock control */ - u8 reserved_0x024[8]; - u32 di_gate_reset; /* 0x62c DI gate/reset control */ - u8 reserved_0x630[64]; - u32 gpu_clk_cfg; /* 0x670 GPU clock control */ - u8 reserved_0x674[8]; - u32 gpu_gate_reset; /* 0x67c GPU gate/reset control */ - u32 ce_clk_cfg; /* 0x680 CE clock control */ - u8 reserved_0x684[8]; - u32 ce_gate_reset; /* 0x68c CE gate/reset control */ - u32 ve_clk_cfg; /* 0x690 VE clock control */ - u8 reserved_0x694[8]; - u32 ve_gate_reset; /* 0x69c VE gate/reset control */ - u8 reserved_0x6a0[16]; - u32 emce_clk_cfg; /* 0x6b0 EMCE clock control */ - u8 reserved_0x6b4[8]; - u32 emce_gate_reset; /* 0x6bc EMCE gate/reset control */ - u32 vp9_clk_cfg; /* 0x6c0 VP9 clock control */ - u8 reserved_0x6c4[8]; - u32 vp9_gate_reset; /* 0x6cc VP9 gate/reset control */ - u8 reserved_0x6d0[60]; - u32 dma_gate_reset; /* 0x70c DMA gate/reset control */ - u8 reserved_0x710[12]; - u32 msgbox_gate_reset; /* 0x71c Message Box gate/reset control */ - u8 reserved_0x720[12]; - u32 spinlock_gate_reset;/* 0x72c Spinlock gate/reset control */ - u8 reserved_0x730[12]; - u32 hstimer_gate_reset; /* 0x73c HS Timer gate/reset control */ - u32 avs_gate_reset; /* 0x740 AVS gate/reset control */ - u8 reserved_0x744[72]; - u32 dbgsys_gate_reset; /* 0x78c Debugging system gate/reset control */ - u8 reserved_0x790[12]; - u32 psi_gate_reset; /* 0x79c PSI gate/reset control */ - u8 reserved_0x7a0[12]; - u32 pwm_gate_reset; /* 0x7ac PWM gate/reset control */ - u8 reserved_0x7b0[12]; - u32 iommu_gate_reset; /* 0x7bc IOMMU gate/reset control */ - u8 reserved_0x7c0[64]; - u32 dram_clk_cfg; /* 0x800 DRAM clock control */ - u32 mbus_gate; /* 0x804 MBUS gate control */ - u8 reserved_0x808[4]; - u32 dram_gate_reset; /* 0x80c DRAM gate/reset control */ - u32 nand0_clk_cfg; /* 0x810 NAND0 clock control */ - u32 nand1_clk_cfg; /* 0x814 NAND1 clock control */ - u8 reserved_0x818[20]; - u32 nand_gate_reset; /* 0x82c NAND gate/reset control */ - u32 sd0_clk_cfg; /* 0x830 MMC0 clock control */ - u32 sd1_clk_cfg; /* 0x834 MMC1 clock control */ - u32 sd2_clk_cfg; /* 0x838 MMC2 clock control */ - u8 reserved_0x83c[16]; - u32 sd_gate_reset; /* 0x84c MMC gate/reset control */ - u8 reserved_0x850[188]; - u32 uart_gate_reset; /* 0x90c UART gate/reset control */ - u8 reserved_0x910[12]; - u32 twi_gate_reset; /* 0x91c I2C gate/reset control */ - u8 reserved_0x920[28]; - u32 scr_gate_reset; /* 0x93c SCR gate/reset control */ - u32 spi0_clk_cfg; /* 0x940 SPI0 clock control */ - u32 spi1_clk_cfg; /* 0x944 SPI1 clock control */ - u8 reserved_0x948[36]; - u32 spi_gate_reset; /* 0x96c SPI gate/reset control */ - u8 reserved_0x970[12]; - u32 emac_gate_reset; /* 0x97c EMAC gate/reset control */ - u8 reserved_0x980[48]; - u32 ts_clk_cfg; /* 0x9b0 TS clock control */ - u8 reserved_0x9b4[8]; - u32 ts_gate_reset; /* 0x9bc TS gate/reset control */ - u32 irtx_clk_cfg; /* 0x9c0 IR TX clock control */ - u8 reserved_0x9c4[8]; - u32 irtx_gate_reset; /* 0x9cc IR TX gate/reset control */ - u8 reserved_0x9d0[44]; - u32 ths_gate_reset; /* 0x9fc THS gate/reset control */ - u8 reserved_0xa00[12]; - u32 i2s3_clk_cfg; /* 0xa0c I2S3 clock control */ - u32 i2s0_clk_cfg; /* 0xa10 I2S0 clock control */ - u32 i2s1_clk_cfg; /* 0xa14 I2S1 clock control */ - u32 i2s2_clk_cfg; /* 0xa18 I2S2 clock control */ - u32 i2s_gate_reset; /* 0xa1c I2S gate/reset control */ - u32 spdif_clk_cfg; /* 0xa20 SPDIF clock control */ - u8 reserved_0xa24[8]; - u32 spdif_gate_reset; /* 0xa2c SPDIF gate/reset control */ - u8 reserved_0xa30[16]; - u32 dmic_clk_cfg; /* 0xa40 DMIC clock control */ - u8 reserved_0xa44[8]; - u32 dmic_gate_reset; /* 0xa4c DMIC gate/reset control */ - u8 reserved_0xa50[16]; - u32 ahub_clk_cfg; /* 0xa60 Audio HUB clock control */ - u8 reserved_0xa64[8]; - u32 ahub_gate_reset; /* 0xa6c Audio HUB gate/reset control */ - u32 usb0_clk_cfg; /* 0xa70 USB0(OTG) clock control */ - u32 usb1_clk_cfg; /* 0xa74 USB1(XHCI) clock control */ - u8 reserved_0xa78[4]; - u32 usb3_clk_cfg; /* 0xa78 USB3 clock control */ - u8 reserved_0xa80[12]; - u32 usb_gate_reset; /* 0xa8c USB gate/reset control */ - u8 reserved_0xa90[32]; - u32 pcie_ref_clk_cfg; /* 0xab0 PCIE REF clock control */ - u32 pcie_axi_clk_cfg; /* 0xab4 PCIE AXI clock control */ - u32 pcie_aux_clk_cfg; /* 0xab8 PCIE AUX clock control */ - u32 pcie_gate_reset; /* 0xabc PCIE gate/reset control */ - u8 reserved_0xac0[64]; - u32 hdmi_clk_cfg; /* 0xb00 HDMI clock control */ - u32 hdmi_slow_clk_cfg; /* 0xb04 HDMI slow clock control */ - u8 reserved_0xb08[8]; - u32 hdmi_cec_clk_cfg; /* 0xb10 HDMI CEC clock control */ - u8 reserved_0xb14[8]; - u32 hdmi_gate_reset; /* 0xb1c HDMI gate/reset control */ - u8 reserved_0xb20[60]; - u32 tcon_top_gate_reset;/* 0xb5c TCON TOP gate/reset control */ - u32 tcon_lcd0_clk_cfg; /* 0xb60 TCON LCD0 clock control */ - u8 reserved_0xb64[24]; - u32 tcon_lcd_gate_reset;/* 0xb7c TCON LCD gate/reset control */ - u32 tcon_tv0_clk_cfg; /* 0xb80 TCON TV0 clock control */ - u8 reserved_0xb84[24]; - u32 tcon_tv_gate_reset; /* 0xb9c TCON TV gate/reset control */ - u8 reserved_0xba0[96]; - u32 csi_misc_clk_cfg; /* 0xc00 CSI MISC clock control */ - u32 csi_top_clk_cfg; /* 0xc04 CSI TOP clock control */ - u32 csi_mclk_cfg; /* 0xc08 CSI Master clock control */ - u8 reserved_0xc0c[32]; - u32 csi_gate_reset; /* 0xc2c CSI gate/reset control */ - u8 reserved_0xc30[16]; - u32 hdcp_clk_cfg; /* 0xc40 HDCP clock control */ - u8 reserved_0xc44[8]; - u32 hdcp_gate_reset; /* 0xc4c HDCP gate/reset control */ - u8 reserved_0xc50[688]; - u32 ccu_sec_switch; /* 0xf00 CCU security switch */ - u32 pll_lock_dbg_ctrl; /* 0xf04 PLL lock debugging control */ -}; - -/* pll1 bit field */ -#define CCM_PLL1_CTRL_EN BIT(31) -#define CCM_PLL1_LOCK_EN BIT(29) -#define CCM_PLL1_LOCK BIT(28) -#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) -#define CCM_PLL1_CTRL_P(p) ((p) << 16) -#define CCM_PLL1_CTRL_N(n) ((n) << 8) - -/* pll5 bit field */ -#define CCM_PLL5_CTRL_EN BIT(31) -#define CCM_PLL5_LOCK_EN BIT(29) -#define CCM_PLL5_LOCK BIT(28) -#define CCM_PLL5_CTRL_N(n) ((n) << 8) -#define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) -#define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) - -/* pll6 bit field */ -#define CCM_PLL6_CTRL_EN BIT(31) -#define CCM_PLL6_LOCK_EN BIT(29) -#define CCM_PLL6_LOCK BIT(28) -#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_DIV1_SHIFT 0 -#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) -#define CCM_PLL6_CTRL_DIV2_SHIFT 1 -#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) -#define CCM_PLL6_DEFAULT 0xa0006300 - -/* cpu_axi bit field*/ -#define CCM_CPU_AXI_MUX_MASK (0x3 << 24) -#define CCM_CPU_AXI_MUX_OSC24M (0x0 << 24) -#define CCM_CPU_AXI_MUX_PLL_CPUX (0x3 << 24) -#define CCM_CPU_AXI_APB_MASK 0x300 -#define CCM_CPU_AXI_AXI_MASK 0x3 -#define CCM_CPU_AXI_DEFAULT_FACTORS 0x301 - -/* psi_ahb1_ahb2 bit field */ -#define CCM_PSI_AHB1_AHB2_DEFAULT 0x03000102 - -/* ahb3 bit field */ -#define CCM_AHB3_DEFAULT 0x03000002 - -/* apb1 bit field */ -#define CCM_APB1_DEFAULT 0x03000102 - -/* apb2 bit field */ -#define APB2_CLK_SRC_OSC24M (0x0 << 24) -#define APB2_CLK_SRC_OSC32K (0x1 << 24) -#define APB2_CLK_SRC_PSI (0x2 << 24) -#define APB2_CLK_SRC_PLL6 (0x3 << 24) -#define APB2_CLK_SRC_MASK (0x3 << 24) -#define APB2_CLK_RATE_N_1 (0x0 << 8) -#define APB2_CLK_RATE_N_2 (0x1 << 8) -#define APB2_CLK_RATE_N_4 (0x2 << 8) -#define APB2_CLK_RATE_N_8 (0x3 << 8) -#define APB2_CLK_RATE_N_MASK (3 << 8) -#define APB2_CLK_RATE_M(m) (((m)-1) << 0) -#define APB2_CLK_RATE_M_MASK (3 << 0) - -/* MBUS clock bit field */ -#define MBUS_ENABLE BIT(31) -#define MBUS_RESET BIT(30) -#define MBUS_CLK_SRC_MASK GENMASK(25, 24) -#define MBUS_CLK_SRC_OSCM24 (0 << 24) -#define MBUS_CLK_SRC_PLL6X2 (1 << 24) -#define MBUS_CLK_SRC_PLL5 (2 << 24) -#define MBUS_CLK_SRC_PLL6X4 (3 << 24) -#define MBUS_CLK_M(m) (((m)-1) << 0) - -/* Module gate/reset shift*/ -#define RESET_SHIFT (16) - -/* DRAM clock bit field */ -#define DRAM_MOD_RESET BIT(30) -#define DRAM_CLK_UPDATE BIT(27) -#define DRAM_CLK_SRC_MASK GENMASK(25, 24) -#define DRAM_CLK_SRC_PLL5 (0 << 24) -#define DRAM_CLK_M(m) (((m)-1) << 0) - -/* MMC clock bit field */ -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_N(x) ((x) << 8) -#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) -#define CCM_MMC_CTRL_PLL6X2 (0x1 << 24) -#define CCM_MMC_CTRL_PLL_PERIPH2X2 (0x2 << 24) -#define CCM_MMC_CTRL_ENABLE (0x1 << 31) -/* H6 doesn't have these delays */ -#define CCM_MMC_CTRL_OCLK_DLY(a) ((void) (a), 0) -#define CCM_MMC_CTRL_SCLK_DLY(a) ((void) (a), 0) - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int hz); -unsigned int clock_get_pll6(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN50I_H6_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h deleted file mode 100644 index ee38712..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h +++ /dev/null @@ -1,533 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun6i clock register definitions - * - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_CLOCK_SUN6I_H -#define _SUNXI_CLOCK_SUN6I_H - -struct sunxi_ccm_reg { - u32 pll1_cfg; /* 0x00 pll1 control */ - u32 reserved0; - u32 pll2_cfg; /* 0x08 pll2 control */ - u32 reserved1; - u32 pll3_cfg; /* 0x10 pll3 control */ - u32 reserved2; - u32 pll4_cfg; /* 0x18 pll4 control */ - u32 reserved3; - u32 pll5_cfg; /* 0x20 pll5 control */ - u32 reserved4; - u32 pll6_cfg; /* 0x28 pll6 control */ - u32 reserved5; - u32 pll7_cfg; /* 0x30 pll7 control */ - u32 sata_pll_cfg; /* 0x34 SATA pll control (R40 only) */ - u32 pll8_cfg; /* 0x38 pll8 control */ - u32 reserved7; - u32 mipi_pll_cfg; /* 0x40 MIPI pll control */ - u32 pll9_cfg; /* 0x44 pll9 control */ - u32 pll10_cfg; /* 0x48 pll10 control */ - u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */ - u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ - u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ - u32 apb2_div; /* 0x58 APB2 divide ratio */ - u32 axi_gate; /* 0x5c axi module clock gating */ - u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ - u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ - u32 apb1_gate; /* 0x68 apb1 module clock gating */ - u32 apb2_gate; /* 0x6c apb2 module clock gating */ - u32 bus_gate4; /* 0x70 gate 4 module clock gating */ - u8 res3[0xc]; - u32 nand0_clk_cfg; /* 0x80 nand0 clock control */ - u32 nand1_clk_cfg; /* 0x84 nand1 clock control */ - u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ - u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ - u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ - u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ - u32 ts_clk_cfg; /* 0x98 transport stream clock control */ - u32 ss_clk_cfg; /* 0x9c security system clock control */ - u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ - u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ - u32 spi2_clk_cfg; /* 0xa8 spi2 clock control */ - u32 spi3_clk_cfg; /* 0xac spi3 clock control */ - u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control*/ - u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ - u32 reserved10[2]; - u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ - u32 reserved11; - u32 sata_clk_cfg; /* 0xc8 SATA clock control (R40 only) */ - u32 usb_clk_cfg; /* 0xcc USB clock control */ -#ifdef CONFIG_MACH_SUN8I_R40 - u32 cir0_clk_cfg; /* 0xd0 CIR0 clock control (R40 only) */ -#else - u32 gmac_clk_cfg; /* 0xd0 GMAC clock control (not for R40) */ -#endif - u32 reserved12[7]; - u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */ - u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ - u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */ - u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */ - u32 dram_clk_gate; /* 0x100 DRAM module gating */ -#ifdef CONFIG_SUNXI_DE2 - u32 de_clk_cfg; /* 0x104 DE module clock */ -#else - u32 be0_clk_cfg; /* 0x104 BE0 module clock */ -#endif - u32 be1_clk_cfg; /* 0x108 BE1 module clock */ - u32 fe0_clk_cfg; /* 0x10c FE0 module clock */ - u32 fe1_clk_cfg; /* 0x110 FE1 module clock */ - u32 mp_clk_cfg; /* 0x114 MP module clock */ -#ifdef CONFIG_SUNXI_DE2 - u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */ - u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */ -#else - u32 lcd0_ch0_clk_cfg; /* 0x118 LCD0 CH0 module clock */ - u32 lcd1_ch0_clk_cfg; /* 0x11c LCD1 CH0 module clock */ -#endif - u32 tve_clk_cfg; /* 0x120 H3/H5 TVE module clock */ - u32 reserved14[2]; - u32 lcd0_ch1_clk_cfg; /* 0x12c LCD0 CH1 module clock */ - u32 lcd1_ch1_clk_cfg; /* 0x130 LCD1 CH1 module clock */ - u32 csi0_clk_cfg; /* 0x134 CSI0 module clock */ - u32 csi1_clk_cfg; /* 0x138 CSI1 module clock */ - u32 ve_clk_cfg; /* 0x13c VE module clock */ - u32 adda_clk_cfg; /* 0x140 ADDA module clock */ - u32 avs_clk_cfg; /* 0x144 AVS module clock */ - u32 dmic_clk_cfg; /* 0x148 Digital Mic module clock*/ - u32 reserved15; - u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ -#ifdef CONFIG_SUNXI_DE2 - u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ -#else - u32 ps_clk_cfg; /* 0x154 PS module clock */ -#endif - u32 mtc_clk_cfg; /* 0x158 MTC module clock */ - u32 mbus0_clk_cfg; /* 0x15c MBUS0 module clock */ - u32 mbus1_clk_cfg; /* 0x160 MBUS1 module clock */ -#ifdef CONFIG_MACH_SUN8I_R40 - u32 gmac_clk_cfg; /* 0x164 GMAC clock control (R40 only) */ -#else - u32 reserved16; -#endif - u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ - u32 mipi_csi_clk_cfg; /* 0x16c MIPI CSI clock control */ - u32 reserved17[4]; - u32 iep_drc0_clk_cfg; /* 0x180 IEP DRC0 module clock */ - u32 iep_drc1_clk_cfg; /* 0x184 IEP DRC1 module clock */ - u32 iep_deu0_clk_cfg; /* 0x188 IEP DEU0 module clock */ - u32 iep_deu1_clk_cfg; /* 0x18c IEP DEU1 module clock */ - u32 reserved18[4]; - u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ - u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ - u32 gpu_hyd_clk_cfg; /* 0x1a0 GPU HYD clock config */ - u32 reserved19[21]; - u32 pll_lock; /* 0x200 PLL Lock Time */ - u32 pll1_lock; /* 0x204 PLL1 Lock Time */ - u32 reserved20[6]; - u32 pll1_bias_cfg; /* 0x220 PLL1 Bias config */ - u32 pll2_bias_cfg; /* 0x224 PLL2 Bias config */ - u32 pll3_bias_cfg; /* 0x228 PLL3 Bias config */ - u32 pll4_bias_cfg; /* 0x22c PLL4 Bias config */ - u32 pll5_bias_cfg; /* 0x230 PLL5 Bias config */ - u32 pll6_bias_cfg; /* 0x234 PLL6 Bias config */ - u32 pll7_bias_cfg; /* 0x238 PLL7 Bias config */ - u32 pll8_bias_cfg; /* 0x23c PLL8 Bias config */ - u32 mipi_bias_cfg; /* 0x240 MIPI Bias config */ - u32 pll9_bias_cfg; /* 0x244 PLL9 Bias config */ - u32 pll10_bias_cfg; /* 0x248 PLL10 Bias config */ - u32 reserved21[5]; - u32 pll5_tuning_cfg; /* 0x260 PLL5 Tuning config */ - u32 reserved21_5[7]; - u32 pll1_pattern_cfg; /* 0x280 PLL1 Pattern config */ - u32 pll2_pattern_cfg; /* 0x284 PLL2 Pattern config */ - u32 pll3_pattern_cfg; /* 0x288 PLL3 Pattern config */ - u32 pll4_pattern_cfg; /* 0x28c PLL4 Pattern config */ - u32 pll5_pattern_cfg; /* 0x290 PLL5 Pattern config */ - u32 pll6_pattern_cfg; /* 0x294 PLL6 Pattern config */ - u32 pll7_pattern_cfg; /* 0x298 PLL7 Pattern config */ - u32 pll8_pattern_cfg; /* 0x29c PLL8 Pattern config */ - u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */ - u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */ - u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */ - u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */ - u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */ - u32 reserved22[3]; - u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ - u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ - u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ - u32 reserved23; - u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */ - u32 reserved24; - u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */ - u32 reserved25[5]; - u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */ - u32 reserved26[11]; - u32 pll_lock_ctrl; /* 0x320 PLL lock control, R40 only */ -}; - -/* apb2 bit field */ -#define APB2_CLK_SRC_LOSC (0x0 << 24) -#define APB2_CLK_SRC_OSC24M (0x1 << 24) -#define APB2_CLK_SRC_PLL6 (0x2 << 24) -#define APB2_CLK_SRC_MASK (0x3 << 24) -#define APB2_CLK_RATE_N_1 (0x0 << 16) -#define APB2_CLK_RATE_N_2 (0x1 << 16) -#define APB2_CLK_RATE_N_4 (0x2 << 16) -#define APB2_CLK_RATE_N_8 (0x3 << 16) -#define APB2_CLK_RATE_N_MASK (3 << 16) -#define APB2_CLK_RATE_M(m) (((m)-1) << 0) -#define APB2_CLK_RATE_M_MASK (0x1f << 0) - -/* apb2 gate field */ -#define APB2_GATE_UART_SHIFT (16) -#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) -#define APB2_GATE_TWI_SHIFT (0) -#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) - -/* cpu_axi_cfg bits */ -#define AXI_DIV_SHIFT 0 -#define ATB_DIV_SHIFT 8 -#define CPU_CLK_SRC_SHIFT 16 - -#define AXI_DIV_1 0 -#define AXI_DIV_2 1 -#define AXI_DIV_3 2 -#define AXI_DIV_4 3 -#define ATB_DIV_1 0 -#define ATB_DIV_2 1 -#define ATB_DIV_4 2 -#define AHB_DIV_1 0 -#define CPU_CLK_SRC_OSC24M 1 -#define CPU_CLK_SRC_PLL1 2 - -#define CCM_PLL1_CTRL_M(n) ((((n) - 1) & 0x3) << 0) -#define CCM_PLL1_CTRL_K(n) ((((n) - 1) & 0x3) << 4) -#define CCM_PLL1_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) -#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16) -#define CCM_PLL1_CTRL_EN (0x1 << 31) - -#define CCM_PLL3_CTRL_M_SHIFT 0 -#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT) -#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_PLL3_CTRL_N_SHIFT 8 -#define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT) -#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) -#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24) -#define CCM_PLL3_CTRL_LOCK (0x1 << 28) -#define CCM_PLL3_CTRL_EN (0x1 << 31) - -#define CCM_PLL5_CTRL_M(n) ((((n) - 1) & 0x3) << 0) -#define CCM_PLL5_CTRL_K(n) ((((n) - 1) & 0x3) << 4) -#define CCM_PLL5_CTRL_N(n) ((((n) - 1) & 0x1f) << 8) -#define CCM_PLL5_CTRL_UPD (0x1 << 20) -#define CCM_PLL5_CTRL_SIGMA_DELTA_EN (0x1 << 24) -#define CCM_PLL5_CTRL_EN (0x1 << 31) - -#define PLL6_CFG_DEFAULT 0x90041811 /* 600 MHz */ - -#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_K_SHIFT 4 -#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT) -#define CCM_PLL6_CTRL_LOCK (1 << 28) - -#define CCM_SATA_PLL_DEFAULT 0x90005811 /* 100 MHz */ - -#define CCM_MIPI_PLL_CTRL_M_SHIFT 0 -#define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT) -#define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_MIPI_PLL_CTRL_K_SHIFT 4 -#define CCM_MIPI_PLL_CTRL_K_MASK (0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT) -#define CCM_MIPI_PLL_CTRL_K(n) ((((n) - 1) & 0x3) << 4) -#define CCM_MIPI_PLL_CTRL_N_SHIFT 8 -#define CCM_MIPI_PLL_CTRL_N_MASK (0xf << CCM_MIPI_PLL_CTRL_N_SHIFT) -#define CCM_MIPI_PLL_CTRL_N(n) ((((n) - 1) & 0xf) << 8) -#define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22) -#define CCM_MIPI_PLL_CTRL_EN (0x1 << 31) - -#define CCM_PLL10_CTRL_M_SHIFT 0 -#define CCM_PLL10_CTRL_M_MASK (0xf << CCM_PLL10_CTRL_M_SHIFT) -#define CCM_PLL10_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_PLL10_CTRL_N_SHIFT 8 -#define CCM_PLL10_CTRL_N_MASK (0x7f << CCM_PLL10_CTRL_N_SHIFT) -#define CCM_PLL10_CTRL_N(n) ((((n) - 1) & 0x7f) << 8) -#define CCM_PLL10_CTRL_INTEGER_MODE (0x1 << 24) -#define CCM_PLL10_CTRL_LOCK (0x1 << 28) -#define CCM_PLL10_CTRL_EN (0x1 << 31) - -#define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8) -#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24) -#define CCM_PLL11_CTRL_UPD (0x1 << 30) -#define CCM_PLL11_CTRL_EN (0x1 << 31) - -#define CCM_PLL5_TUN_LOCK_TIME(x) (((x) & 0x7) << 24) -#define CCM_PLL5_TUN_LOCK_TIME_MASK CCM_PLL5_TUN_LOCK_TIME(0x7) -#define CCM_PLL5_TUN_INIT_FREQ(x) (((x) & 0x7f) << 16) -#define CCM_PLL5_TUN_INIT_FREQ_MASK CCM_PLL5_TUN_INIT_FREQ(0x7f) - -#if defined(CONFIG_MACH_SUN50I) -/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */ -#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */ -#else -#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */ -#endif - -#define AXI_GATE_OFFSET_DRAM 0 - -/* ahb_gate0 offsets */ -#ifdef CONFIG_MACH_SUNXI_H3_H5 -/* - * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call - * them 0 - 2 like they were called on older SoCs. - */ -#define AHB_GATE_OFFSET_USB_OHCI3 31 -#define AHB_GATE_OFFSET_USB_OHCI2 30 -#define AHB_GATE_OFFSET_USB_OHCI1 29 -#define AHB_GATE_OFFSET_USB_OHCI0 28 -#define AHB_GATE_OFFSET_USB_EHCI3 27 -#define AHB_GATE_OFFSET_USB_EHCI2 26 -#define AHB_GATE_OFFSET_USB_EHCI1 25 -#define AHB_GATE_OFFSET_USB_EHCI0 24 -#elif defined(CONFIG_MACH_SUN50I) -#define AHB_GATE_OFFSET_USB_OHCI0 28 -#define AHB_GATE_OFFSET_USB_OHCI1 29 -#define AHB_GATE_OFFSET_USB_EHCI0 24 -#define AHB_GATE_OFFSET_USB_EHCI1 25 -#else -#define AHB_GATE_OFFSET_USB_OHCI1 30 -#define AHB_GATE_OFFSET_USB_OHCI0 29 -#define AHB_GATE_OFFSET_USB_EHCI1 27 -#define AHB_GATE_OFFSET_USB_EHCI0 26 -#endif -#if defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNXI_H3_H5) -#define AHB_GATE_OFFSET_USB0 23 -#elif !defined(CONFIG_MACH_SUN8I_R40) -#define AHB_GATE_OFFSET_USB0 24 -#else -#define AHB_GATE_OFFSET_USB0 25 -#define AHB_GATE_OFFSET_SATA 24 -#endif -#define AHB_GATE_OFFSET_MCTL 14 -#define AHB_GATE_OFFSET_GMAC 17 -#define AHB_GATE_OFFSET_NAND0 13 -#define AHB_GATE_OFFSET_NAND1 12 -#define AHB_GATE_OFFSET_MMC3 11 -#define AHB_GATE_OFFSET_MMC2 10 -#define AHB_GATE_OFFSET_MMC1 9 -#define AHB_GATE_OFFSET_MMC0 8 -#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) -#define AHB_GATE_OFFSET_DMA 6 -#define AHB_GATE_OFFSET_SS 5 - -/* ahb_gate1 offsets */ -#define AHB_GATE_OFFSET_DRC0 25 -#define AHB_GATE_OFFSET_DE_FE0 14 -#define AHB_GATE_OFFSET_DE_BE0 12 -#define AHB_GATE_OFFSET_DE 12 -#define AHB_GATE_OFFSET_HDMI 11 -#define AHB_GATE_OFFSET_TVE 9 -#ifndef CONFIG_SUNXI_DE2 -#define AHB_GATE_OFFSET_LCD1 5 -#define AHB_GATE_OFFSET_LCD0 4 -#else -#define AHB_GATE_OFFSET_LCD1 4 -#define AHB_GATE_OFFSET_LCD0 3 -#endif - -#define CCM_NAND_CTRL_M(x) ((x) - 1) -#define CCM_NAND_CTRL_N(x) ((x) << 16) -#define CCM_NAND_CTRL_PLL6 (0x1 << 24) -#define CCM_NAND_CTRL_ENABLE (0x1 << 31) - -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) -#define CCM_MMC_CTRL_N(x) ((x) << 16) -#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) -#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) -#define CCM_MMC_CTRL_PLL6 (0x1 << 24) -#define CCM_MMC_CTRL_ENABLE (0x1 << 31) - -#define CCM_SATA_CTRL_ENABLE (0x1 << 31) -#define CCM_SATA_CTRL_USE_EXTCLK (0x1 << 24) - -#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) -#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -#define CCM_USB_CTRL_PHY2_RST (0x1 << 2) -#define CCM_USB_CTRL_PHY3_RST (0x1 << 3) -/* There is no global phy clk gate on sun6i, define as 0 */ -#define CCM_USB_CTRL_PHYGATE 0 -#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) -#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) -#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10) -#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11) -#ifdef CONFIG_MACH_SUNXI_H3_H5 -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) -#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 18) -#define CCM_USB_CTRL_OHCI3_CLK (0x1 << 19) -#else -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) -#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17) -#endif - -#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 -#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 -#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 -#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) -#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) -#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) -#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) - -#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ - -#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) -#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) -#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) -#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) -#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20) -#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20) -#define CCM_DRAMCLK_CFG_SRC_PLL11 (0x1 << 20) /* A64 only */ -#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20) -#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) -#define CCM_DRAMCLK_CFG_RST (0x1 << 31) - -#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ -#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ -#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) - -#define CCM_MBUS_RESET_RESET (0x1 << 31) - -#define CCM_DRAM_GATE_OFFSET_DE_FE0 24 -#define CCM_DRAM_GATE_OFFSET_DE_FE1 25 -#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 -#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - -#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24) -#define CCM_LCD_CH0_CTRL_PLL3_2X (2 << 24) -#define CCM_LCD_CH0_CTRL_PLL7_2X (3 << 24) -#define CCM_LCD_CH0_CTRL_MIPI_PLL (4 << 24) -/* No reset bit in ch0_clk_cfg (reset is controlled through ahb_reset1) */ -#define CCM_LCD_CH0_CTRL_RST 0 -#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31) - -#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_LCD_CH1_CTRL_HALF_SCLK1 0 /* no seperate sclk1 & 2 on sun6i */ -#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24) -#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24) -#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24) -#define CCM_LCD_CH1_CTRL_PLL7_2X (3 << 24) -#define CCM_LCD_CH1_CTRL_GATE (0x1 << 31) - -#define CCM_LCD0_CTRL_GATE (0x1 << 31) -#define CCM_LCD0_CTRL_M(n) ((((n) - 1) & 0xf) << 0) - -#define CCM_LCD1_CTRL_GATE (0x1 << 31) -#define CCM_LCD1_CTRL_M(n) ((((n) - 1) & 0xf) << 0) - -#define CCM_HDMI_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_HDMI_CTRL_PLL_MASK (3 << 24) -#define CCM_HDMI_CTRL_PLL3 (0 << 24) -#define CCM_HDMI_CTRL_PLL7 (1 << 24) -#define CCM_HDMI_CTRL_PLL3_2X (2 << 24) -#define CCM_HDMI_CTRL_PLL7_2X (3 << 24) -#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30) -#define CCM_HDMI_CTRL_GATE (0x1 << 31) - -#define CCM_HDMI_SLOW_CTRL_DDC_GATE (1 << 31) - -#define CCM_TVE_CTRL_GATE (0x1 << 31) -#define CCM_TVE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) - -#if defined(CONFIG_MACH_SUN50I) -#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */ -#elif defined(CONFIG_MACH_SUN8I) -#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */ -#else -#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */ -#endif -#define MBUS_CLK_GATE (0x1 << 31) - -#define CCM_PLL5_PATTERN 0xd1303333 -#define CCM_PLL11_PATTERN 0xf5860000 - -/* ahb_reset0 offsets */ -#ifdef CONFIG_MACH_SUN8I_R40 -#define AHB_RESET_OFFSET_SATA 24 -#endif -#define AHB_RESET_OFFSET_GMAC 17 -#define AHB_RESET_OFFSET_MCTL 14 -#define AHB_RESET_OFFSET_MMC3 11 -#define AHB_RESET_OFFSET_MMC2 10 -#define AHB_RESET_OFFSET_MMC1 9 -#define AHB_RESET_OFFSET_MMC0 8 -#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) -#define AHB_RESET_OFFSET_SS 5 - -/* ahb_reset1 offsets */ -#define AHB_RESET_OFFSET_SAT 26 -#define AHB_RESET_OFFSET_DRC0 25 -#define AHB_RESET_OFFSET_DE_FE0 14 -#define AHB_RESET_OFFSET_DE_BE0 12 -#define AHB_RESET_OFFSET_DE 12 -#define AHB_RESET_OFFSET_HDMI 11 -#define AHB_RESET_OFFSET_HDMI2 10 -#define AHB_RESET_OFFSET_TVE 9 -#ifndef CONFIG_SUNXI_DE2 -#define AHB_RESET_OFFSET_LCD1 5 -#define AHB_RESET_OFFSET_LCD0 4 -#else -#define AHB_RESET_OFFSET_LCD1 4 -#define AHB_RESET_OFFSET_LCD0 3 -#endif - -/* ahb_reset2 offsets */ -#define AHB_RESET_OFFSET_EPHY 2 -#define AHB_RESET_OFFSET_LVDS 0 - -/* apb2 reset */ -#define APB2_RESET_UART_SHIFT (16) -#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) -#define APB2_RESET_TWI_SHIFT (0) -#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) - -/* CCM bits common to all Display Engine (and IEP) clock ctrl regs */ -#define CCM_DE_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_DE_CTRL_PLL_MASK (0xf << 24) -#define CCM_DE_CTRL_PLL3 (0 << 24) -#define CCM_DE_CTRL_PLL7 (1 << 24) -#define CCM_DE_CTRL_PLL6_2X (2 << 24) -#define CCM_DE_CTRL_PLL8 (3 << 24) -#define CCM_DE_CTRL_PLL9 (4 << 24) -#define CCM_DE_CTRL_PLL10 (5 << 24) -#define CCM_DE_CTRL_GATE (1 << 31) - -/* CCM bits common to all Display Engine 2.0 clock ctrl regs */ -#define CCM_DE2_CTRL_M(n) ((((n) - 1) & 0xf) << 0) -#define CCM_DE2_CTRL_PLL_MASK (3 << 24) -#define CCM_DE2_CTRL_PLL6_2X (0 << 24) -#define CCM_DE2_CTRL_PLL10 (1 << 24) -#define CCM_DE2_CTRL_GATE (0x1 << 31) - -/* CCU security switch, H3 only */ -#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2) -#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1) -#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0) - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int hz); -void clock_set_pll3(unsigned int hz); -void clock_set_pll3_factors(int m, int n); -void clock_set_pll5(unsigned int clk, bool sigma_delta_enable); -void clock_set_pll10(unsigned int hz); -void clock_set_pll11(unsigned int clk, bool sigma_delta_enable); -void clock_set_mipi_pll(unsigned int hz); -unsigned int clock_get_pll3(void); -unsigned int clock_get_pll6(void); -unsigned int clock_get_mipi_pll(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h deleted file mode 100644 index 14df3cc..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun8i_a83t.h +++ /dev/null @@ -1,305 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun8i a83t clock register definitions - * - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> - * from sun6i.h - */ - -#ifndef _SUNXI_CLOCK_SUN8I_A83T_H -#define _SUNXI_CLOCK_SUN8I_A83T_H - -struct sunxi_ccm_reg { - u32 pll1_c0_cfg; /* 0x00 c1cpu# pll control */ - u32 pll1_c1_cfg; /* 0x04 c1cpu# pll control */ - u32 pll2_cfg; /* 0x08 pll2 audio control */ - u32 reserved1; - u32 pll3_cfg; /* 0x10 pll3 video0 control */ - u32 reserved2; - u32 pll4_cfg; /* 0x18 pll4 ve control */ - u32 reserved3; - u32 pll5_cfg; /* 0x20 pll5 ddr control */ - u32 reserved4; - u32 pll6_cfg; /* 0x28 pll6 peripheral control */ - u32 reserved5[3]; /* 0x2c */ - u32 pll7_cfg; /* 0x38 pll7 gpu control */ - u32 reserved6[2]; /* 0x3c */ - u32 pll8_cfg; /* 0x44 pll8 hsic control */ - u32 pll9_cfg; /* 0x48 pll9 de control */ - u32 pll10_cfg; /* 0x4c pll10 video1 control */ - u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */ - u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */ - u32 apb2_div; /* 0x58 APB2 divide ratio */ - u32 ahb2_div; /* 0x5c AHB2 divide ratio */ - u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ - u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ - u32 apb1_gate; /* 0x68 apb1 module clock gating 3 */ - u32 apb2_gate; /* 0x6c apb2 module clock gating 4 */ - u32 reserved7[2]; /* 0x70 */ - u32 cci400_cfg; /* 0x78 cci400 clock configuration A83T only */ - u32 reserved8; /* 0x7c */ - u32 nand0_clk_cfg; /* 0x80 nand clock control */ - u32 reserved9; /* 0x84 */ - u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ - u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ - u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ - u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ - u32 reserved10; /* 0x98 */ - u32 ss_clk_cfg; /* 0x9c security system clock control */ - u32 spi0_clk_cfg; /* 0xa0 spi0 clock control */ - u32 spi1_clk_cfg; /* 0xa4 spi1 clock control */ - u32 reserved11[2]; /* 0xa8 */ - u32 i2s0_clk_cfg; /* 0xb0 I2S0 clock control */ - u32 i2s1_clk_cfg; /* 0xb4 I2S1 clock control */ - u32 i2s2_clk_cfg; /* 0xb8 I2S2 clock control */ - u32 tdm_clk_cfg; /* 0xbc TDM clock control */ - u32 spdif_clk_cfg; /* 0xc0 SPDIF clock control */ - u32 reserved12[2]; /* 0xc4 */ - u32 usb_clk_cfg; /* 0xcc USB clock control */ - u32 reserved13[9]; /* 0xd0 */ - u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */ - u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register */ - u32 mbus_reset; /* 0xfc MBUS reset control */ - u32 dram_clk_gate; /* 0x100 DRAM module gating */ - u32 reserved14[5]; /* 0x104 BE0 */ - u32 lcd0_clk_cfg; /* 0x118 LCD0 module clock */ - u32 lcd1_clk_cfg; /* 0x11c LCD1 module clock */ - u32 reserved15[4]; /* 0x120 */ - u32 mipi_csi_clk_cfg; /* 0x130 MIPI CSI module clock */ - u32 csi_clk_cfg; /* 0x134 CSI module clock */ - u32 reserved16; /* 0x138 */ - u32 ve_clk_cfg; /* 0x13c VE module clock */ - u32 reserved17; /* 0x140 */ - u32 avs_clk_cfg; /* 0x144 AVS module clock */ - u32 reserved18[2]; /* 0x148 */ - u32 hdmi_clk_cfg; /* 0x150 HDMI module clock */ - u32 hdmi_slow_clk_cfg; /* 0x154 HDMI slow module clock */ - u32 reserved19; /* 0x158 */ - u32 mbus_clk_cfg; /* 0x15c MBUS module clock */ - u32 reserved20[2]; /* 0x160 */ - u32 mipi_dsi_clk_cfg; /* 0x168 MIPI DSI clock control */ - u32 reserved21[13]; /* 0x16c */ - u32 gpu_core_clk_cfg; /* 0x1a0 GPU core clock config */ - u32 gpu_mem_clk_cfg; /* 0x1a4 GPU memory clock config */ - u32 gpu_hyd_clk_cfg; /* 0x1a8 GPU HYD clock config */ - u32 reserved22[21]; /* 0x1ac */ - u32 pll_stable0; /* 0x200 PLL stable time 0 */ - u32 pll_stable1; /* 0x204 PLL stable time 1 */ - u32 reserved23; /* 0x208 */ - u32 pll_stable_status; /* 0x20c PLL stable status register */ - u32 reserved24[4]; /* 0x210 */ - u32 pll1_c0_bias_cfg; /* 0x220 PLL1 c0cpu# Bias config */ - u32 pll2_bias_cfg; /* 0x224 PLL2 audio Bias config */ - u32 pll3_bias_cfg; /* 0x228 PLL3 video Bias config */ - u32 pll4_bias_cfg; /* 0x22c PLL4 ve Bias config */ - u32 pll5_bias_cfg; /* 0x230 PLL5 ddr Bias config */ - u32 pll6_bias_cfg; /* 0x234 PLL6 periph Bias config */ - u32 pll1_c1_bias_cfg; /* 0x238 PLL1 c1cpu# Bias config */ - u32 pll8_bias_cfg; /* 0x23c PLL7 Bias config */ - u32 reserved25; /* 0x240 */ - u32 pll9_bias_cfg; /* 0x244 PLL9 hsic Bias config */ - u32 de_bias_cfg; /* 0x248 display engine Bias config */ - u32 video1_bias_cfg; /* 0x24c pll video1 bias register */ - u32 c0_tuning_cfg; /* 0x250 pll c0cpu# tuning register */ - u32 c1_tuning_cfg; /* 0x254 pll c1cpu# tuning register */ - u32 reserved26[11]; /* 0x258 */ - u32 pll2_pattern_cfg0; /* 0x284 PLL2 Pattern register 0 */ - u32 pll3_pattern_cfg0; /* 0x288 PLL3 Pattern register 0 */ - u32 reserved27; /* 0x28c */ - u32 pll5_pattern_cfg0; /* 0x290 PLL5 Pattern register 0*/ - u32 reserved28[4]; /* 0x294 */ - u32 pll2_pattern_cfg1; /* 0x2a4 PLL2 Pattern register 1 */ - u32 pll3_pattern_cfg1; /* 0x2a8 PLL3 Pattern register 1 */ - u32 reserved29; /* 0x2ac */ - u32 pll5_pattern_cfg1; /* 0x2b0 PLL5 Pattern register 1 */ - u32 reserved30[3]; /* 0x2b4 */ - u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */ - u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */ - u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */ - u32 reserved31; - u32 ahb_reset3_cfg; /* 0x2d0 AHB1 Reset 3 config */ - u32 reserved32; /* 0x2d4 */ - u32 apb2_reset_cfg; /* 0x2d8 BUS Reset 4 config */ -}; - -/* apb2 bit field */ -#define APB2_CLK_SRC_LOSC (0x0 << 24) -#define APB2_CLK_SRC_OSC24M (0x1 << 24) -#define APB2_CLK_SRC_PLL6 (0x2 << 24) -#define APB2_CLK_SRC_MASK (0x3 << 24) -#define APB2_CLK_RATE_N_1 (0x0 << 16) -#define APB2_CLK_RATE_N_2 (0x1 << 16) -#define APB2_CLK_RATE_N_4 (0x2 << 16) -#define APB2_CLK_RATE_N_8 (0x3 << 16) -#define APB2_CLK_RATE_N_MASK (3 << 16) -#define APB2_CLK_RATE_M(m) (((m)-1) << 0) -#define APB2_CLK_RATE_M_MASK (0x1f << 0) - -/* apb2 gate field */ -#define APB2_GATE_UART_SHIFT (16) -#define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) -#define APB2_GATE_TWI_SHIFT (0) -#define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) - -/* cpu_axi_cfg bits */ -#define AXI0_DIV_SHIFT 0 -#define AXI1_DIV_SHIFT 16 -#define C0_CPUX_CLK_SRC_SHIFT 12 -#define C1_CPUX_CLK_SRC_SHIFT 28 - -#define AXI_DIV_1 0 -#define AXI_DIV_2 1 -#define AXI_DIV_3 2 -#define AXI_DIV_4 3 -#define CPU_CLK_SRC_OSC24M 0 -#define CPU_CLK_SRC_PLL1 1 - -#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) -#define CCM_PLL1_CTRL_EN (0x1 << 31) -#define CMM_PLL1_CLOCK_TIME_2 (0x2 << 24) - -#define PLL8_CFG_DEFAULT 0x42800 -#define CCM_CCI400_CLK_SEL_HSIC (0x2<<24) - -#define CCM_PLL5_DIV1_SHIFT 16 -#define CCM_PLL5_DIV2_SHIFT 18 -#define CCM_PLL5_CTRL_N(n) (((n) - 1) << 8) -#define CCM_PLL5_CTRL_UPD (0x1 << 30) -#define CCM_PLL5_CTRL_EN (0x1 << 31) - -#define PLL6_CFG_DEFAULT 0x80001900 /* 600 MHz */ -#define CCM_PLL6_CTRL_N_SHIFT 8 -#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT) -#define CCM_PLL6_CTRL_DIV1_SHIFT 16 -#define CCM_PLL6_CTRL_DIV1_MASK (0x1 << CCM_PLL6_CTRL_DIV1_SHIFT) -#define CCM_PLL6_CTRL_DIV2_SHIFT 18 -#define CCM_PLL6_CTRL_DIV2_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT) - -#define AHB1_ABP1_DIV_DEFAULT 0x00002190 -#define AHB1_CLK_SRC_MASK (0x3<<12) -#define AHB1_CLK_SRC_INTOSC (0x0<<12) -#define AHB1_CLK_SRC_OSC24M (0x1<<12) -#define AHB1_CLK_SRC_PLL6 (0x2<<12) - -#define AXI_GATE_OFFSET_DRAM 0 - -/* ahb_gate0 offsets */ -#define AHB_GATE_OFFSET_USB_OHCI1 30 -#define AHB_GATE_OFFSET_USB_OHCI0 29 -#define AHB_GATE_OFFSET_USB_EHCI1 27 -#define AHB_GATE_OFFSET_USB_EHCI0 26 -#define AHB_GATE_OFFSET_USB0 24 -#define AHB_GATE_OFFSET_SPI1 21 -#define AHB_GATE_OFFSET_SPI0 20 -#define AHB_GATE_OFFSET_HSTIMER 19 -#define AHB_GATE_OFFSET_EMAC 17 -#define AHB_GATE_OFFSET_MCTL 14 -#define AHB_GATE_OFFSET_GMAC 17 -#define AHB_GATE_OFFSET_NAND0 13 -#define AHB_GATE_OFFSET_MMC0 8 -#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) -#define AHB_GATE_OFFSET_DMA 6 -#define AHB_GATE_OFFSET_SS 5 - -/* ahb_gate1 offsets */ -#define AHB_GATE_OFFSET_DRC0 25 -#define AHB_GATE_OFFSET_DE_FE0 14 -#define AHB_GATE_OFFSET_DE_BE0 12 -#define AHB_GATE_OFFSET_HDMI 11 -#define AHB_GATE_OFFSET_LCD1 5 -#define AHB_GATE_OFFSET_LCD0 4 - -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) -#define CCM_MMC_CTRL_N(x) ((x) << 16) -#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) -#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) -#define CCM_MMC_CTRL_PLL6 (0x1 << 24) -#define CCM_MMC_CTRL_MODE_SEL_NEW (0x1 << 30) -#define CCM_MMC_CTRL_ENABLE (0x1 << 31) - -#define CCM_USB_CTRL_PHY0_RST (0x1 << 0) -#define CCM_USB_CTRL_PHY1_RST (0x1 << 1) -#define CCM_USB_CTRL_HSIC_RST (0x1 << 2) -/* There is no global phy clk gate on sun6i, define as 0 */ -#define CCM_USB_CTRL_PHYGATE 0 -#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8) -#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9) -#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10) -#define CCM_USB_CTRL_12M_CLK (0x1 << 11) -#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16) - -#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 -#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 -#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 -#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) -#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) -#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5) -#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10) - -#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */ - -#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0) -#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0) -#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8) -#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8) -#define CCM_DRAMCLK_CFG_UPD (0x1 << 16) -#define CCM_DRAMCLK_CFG_RST (0x1 << 31) - -#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */ -#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */ -#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16) - -#define CCM_MBUS_RESET_RESET (0x1 << 31) - -#define CCM_DRAM_GATE_OFFSET_DE_FE0 24 -#define CCM_DRAM_GATE_OFFSET_DE_FE1 25 -#define CCM_DRAM_GATE_OFFSET_DE_BE0 26 -#define CCM_DRAM_GATE_OFFSET_DE_BE1 27 - - -#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6 / 2 */ - -#define MBUS_CLK_GATE (0x1 << 31) - -/* ahb_reset0 offsets */ -#define AHB_RESET_OFFSET_GMAC 17 -#define AHB_RESET_OFFSET_MCTL 14 -#define AHB_RESET_OFFSET_MMC3 11 -#define AHB_RESET_OFFSET_MMC2 10 -#define AHB_RESET_OFFSET_MMC1 9 -#define AHB_RESET_OFFSET_MMC0 8 -#define AHB_RESET_OFFSET_MMC(n) (AHB_RESET_OFFSET_MMC0 + (n)) -#define AHB_RESET_OFFSET_SS 5 - -/* ahb_reset1 offsets */ -#define AHB_RESET_OFFSET_SAT 26 -#define AHB_RESET_OFFSET_DRC0 25 -#define AHB_RESET_OFFSET_DE_FE0 14 -#define AHB_RESET_OFFSET_DE_BE0 12 -#define AHB_RESET_OFFSET_HDMI 11 -#define AHB_RESET_OFFSET_LCD1 5 -#define AHB_RESET_OFFSET_LCD0 4 - -/* ahb_reset2 offsets */ -#define AHB_RESET_OFFSET_LVDS 0 - -/* apb2 reset */ -#define APB2_RESET_UART_SHIFT (16) -#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) -#define APB2_RESET_TWI_SHIFT (0) -#define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) - - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int hz); -void clock_set_pll5(unsigned int clk); -unsigned int clock_get_pll6(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN8I_A83T_H */ diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h b/arch/arm/include/asm/arch-sunxi/clock_sun9i.h deleted file mode 100644 index 530e0dd..0000000 --- a/arch/arm/include/asm/arch-sunxi/clock_sun9i.h +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun9i clock register definitions - * - * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_CLOCK_SUN9I_H -#define _SUNXI_CLOCK_SUN9I_H - -struct sunxi_ccm_reg { - u32 pll1_c0_cfg; /* 0x00 c0cpu# pll configuration */ - u32 pll2_c1_cfg; /* 0x04 c1cpu# pll configuration */ - u32 pll3_audio_cfg; /* 0x08 audio pll configuration */ - u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */ - u32 pll5_ve_cfg; /* 0x10 videoengine pll configuration */ - u32 pll6_ddr_cfg; /* 0x14 ddr pll configuration */ - u32 pll7_video0_cfg; /* 0x18 video0 pll configuration */ - u32 pll8_video1_cfg; /* 0x1c video1 pll configuration */ - u32 pll9_gpu_cfg; /* 0x20 gpu pll configuration */ - u32 pll10_de_cfg; /* 0x24 displayengine pll configuration */ - u32 pll11_isp_cfg; /* 0x28 isp pll6 ontrol */ - u32 pll12_periph1_cfg; /* 0x2c peripheral1 pll configuration */ - u8 reserved1[0x20]; /* 0x30 */ - u32 cpu_clk_source; /* 0x50 cpu clk source configuration */ - u32 c0_cfg; /* 0x54 cpu cluster 0 clock configuration */ - u32 c1_cfg; /* 0x58 cpu cluster 1 clock configuration */ - u32 gtbus_cfg; /* 0x5c gtbus clock configuration */ - u32 ahb0_cfg; /* 0x60 ahb0 clock configuration */ - u32 ahb1_cfg; /* 0x64 ahb1 clock configuration */ - u32 ahb2_cfg; /* 0x68 ahb2 clock configuration */ - u8 reserved2[0x04]; /* 0x6c */ - u32 apb0_cfg; /* 0x70 apb0 clock configuration */ - u32 apb1_cfg; /* 0x74 apb1 clock configuration */ - u32 cci400_cfg; /* 0x78 cci400 clock configuration */ - u8 reserved3[0x04]; /* 0x7c */ - u32 ats_cfg; /* 0x80 ats clock configuration */ - u32 trace_cfg; /* 0x84 trace clock configuration */ - u8 reserved4[0x14]; /* 0x88 */ - u32 pll_stable_status; /* 0x9c */ - u8 reserved5[0xe0]; /* 0xa0 */ - u32 clk_output_a; /* 0x180 clk_output_a */ - u32 clk_output_b; /* 0x184 clk_output_a */ - u8 reserved6[0x278]; /* 0x188 */ - - u32 nand0_clk_cfg; /* 0x400 nand0 clock configuration0 */ - u32 nand0_clk_cfg1; /* 0x404 nand1 clock configuration */ - u8 reserved7[0x08]; /* 0x408 */ - u32 sd0_clk_cfg; /* 0x410 sd0 clock configuration */ - u32 sd1_clk_cfg; /* 0x414 sd1 clock configuration */ - u32 sd2_clk_cfg; /* 0x418 sd2 clock configuration */ - u32 sd3_clk_cfg; /* 0x41c sd3 clock configuration */ - u8 reserved8[0x08]; /* 0x420 */ - u32 ts_clk_cfg; /* 0x428 transport stream clock cfg */ - u32 ss_clk_cfg; /* 0x42c security system clock cfg */ - u32 spi0_clk_cfg; /* 0x430 spi0 clock configuration */ - u32 spi1_clk_cfg; /* 0x434 spi1 clock configuration */ - u32 spi2_clk_cfg; /* 0x438 spi2 clock configuration */ - u32 spi3_clk_cfg; /* 0x43c spi3 clock configuration */ - u8 reserved9[0x44]; /* 0x440 */ - u32 dram_clk_cfg; /* 0x484 DRAM (controller) clock config */ - u8 reserved10[0x8]; /* 0x488 */ - u32 de_clk_cfg; /* 0x490 display engine clock configuration */ - u8 reserved11[0x04]; /* 0x494 */ - u32 mp_clk_cfg; /* 0x498 mp clock configuration */ - u32 lcd0_clk_cfg; /* 0x49c LCD0 module clock */ - u32 lcd1_clk_cfg; /* 0x4a0 LCD1 module clock */ - u8 reserved12[0x1c]; /* 0x4a4 */ - u32 csi_isp_clk_cfg; /* 0x4c0 CSI ISP module clock */ - u32 csi0_clk_cfg; /* 0x4c4 CSI0 module clock */ - u32 csi1_clk_cfg; /* 0x4c8 CSI1 module clock */ - u32 fd_clk_cfg; /* 0x4cc FD module clock */ - u32 ve_clk_cfg; /* 0x4d0 VE module clock */ - u32 avs_clk_cfg; /* 0x4d4 AVS module clock */ - u8 reserved13[0x18]; /* 0x4d8 */ - u32 gpu_core_clk_cfg; /* 0x4f0 GPU core clock config */ - u32 gpu_mem_clk_cfg; /* 0x4f4 GPU memory clock config */ - u32 gpu_axi_clk_cfg; /* 0x4f8 GPU AXI clock config */ - u8 reserved14[0x10]; /* 0x4fc */ - u32 gp_adc_clk_cfg; /* 0x50c General Purpose ADC clk config */ - u8 reserved15[0x70]; /* 0x510 */ - - u32 ahb_gate0; /* 0x580 AHB0 Gating Register */ - u32 ahb_gate1; /* 0x584 AHB1 Gating Register */ - u32 ahb_gate2; /* 0x588 AHB2 Gating Register */ - u8 reserved16[0x04]; /* 0x58c */ - u32 apb0_gate; /* 0x590 APB0 Clock Gating Register */ - u32 apb1_gate; /* 0x594 APB1 Clock Gating Register */ - u8 reserved17[0x08]; /* 0x598 */ - u32 ahb_reset0_cfg; /* 0x5a0 AHB0 Software Reset Register */ - u32 ahb_reset1_cfg; /* 0x5a4 AHB1 Software Reset Register */ - u32 ahb_reset2_cfg; /* 0x5a8 AHB2 Software Reset Register */ - u8 reserved18[0x04]; /* 0x5ac */ - u32 apb0_reset_cfg; /* 0x5b0 Bus Software Reset Register 3 */ - u32 apb1_reset_cfg; /* 0x5b4 Bus Software Reset Register 4 */ -}; - -#define CCM_PLL4_CTRL_N_SHIFT 8 -#define CCM_PLL4_CTRL_N_MASK (0xff << CCM_PLL4_CTRL_N_SHIFT) -#define CCM_PLL4_CTRL_P_SHIFT 16 -#define CCM_PLL4_CTRL_P_MASK (0x1 << CCM_PLL4_CTRL_P_SHIFT) -#define CCM_PLL4_CTRL_M_SHIFT 18 -#define CCM_PLL4_CTRL_M_MASK (0x1 << CCM_PLL4_CTRL_M_SHIFT) - -/* pllx_cfg bits */ -#define CCM_PLL1_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL1_CTRL_P(n) (((n) & 0x1) << 16) -#define CCM_PLL1_CTRL_EN (1 << 31) -#define CCM_PLL1_CLOCK_TIME_2 (2 << 24) - -#define CCM_PLL2_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL2_CTRL_P(n) (((n) & 0x1) << 16) -#define CCM_PLL2_CTRL_EN (1 << 31) -#define CCM_PLL2_CLOCK_TIME_2 (2 << 24) - -#define CCM_PLL4_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL4_CTRL_EN (1 << 31) - -#define CCM_PLL6_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL6_CTRL_P(p) (((p) & 0x1) << 16) -#define CCM_PLL6_CTRL_EN (1 << 31) -#define CCM_PLL6_CFG_UPDATE (1 << 30) - -#define CCM_PLL12_CTRL_N(n) (((n) & 0xff) << 8) -#define CCM_PLL12_CTRL_EN (1 << 31) - -#define PLL_C0CPUX_STATUS (1 << 0) -#define PLL_C1CPUX_STATUS (1 << 1) -#define PLL_DDR_STATUS (1 << 5) -#define PLL_PERIPH1_STATUS (1 << 11) - -/* cpu_clk_source bits */ -#define C0_CPUX_CLK_SRC_SHIFT 0 -#define C1_CPUX_CLK_SRC_SHIFT 8 -#define C0_CPUX_CLK_SRC_MASK (1 << C0_CPUX_CLK_SRC_SHIFT) -#define C1_CPUX_CLK_SRC_MASK (1 << C1_CPUX_CLK_SRC_SHIFT) -#define C0_CPUX_CLK_SRC_OSC24M (0 << C0_CPUX_CLK_SRC_SHIFT) -#define C0_CPUX_CLK_SRC_PLL1 (1 << C0_CPUX_CLK_SRC_SHIFT) -#define C1_CPUX_CLK_SRC_OSC24M (0 << C1_CPUX_CLK_SRC_SHIFT) -#define C1_CPUX_CLK_SRC_PLL2 (1 << C1_CPUX_CLK_SRC_SHIFT) - -/* c0_cfg */ -#define C0_CFG_AXI0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) -#define C0_CFG_APB0_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 8) - -/* ahbx_cfg */ -#define AHBx_SRC_CLK_SELECT_SHIFT 24 -#define AHBx_SRC_MASK (0x3 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHB0_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHB1_SRC_GTBUS_CLK (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHB2_SRC_OSC24M (0x0 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHBx_SRC_PLL_PERIPH0 (0x1 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHBx_SRC_PLL_PERIPH1 (0x2 << AHBx_SRC_CLK_SELECT_SHIFT) -#define AHBx_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) - -/* apb0_cfg */ -#define APB0_SRC_CLK_SELECT_SHIFT 24 -#define APB0_SRC_MASK (0x1 << APB0_SRC_CLK_SELECT_SHIFT) -#define APB0_SRC_OSC24M (0x0 << APB0_SRC_CLK_SELECT_SHIFT) -#define APB0_SRC_PLL_PERIPH0 (0x1 << APB0_SRC_CLK_SELECT_SHIFT) -#define APB0_CLK_DIV_RATIO(n) (((ffs(n) - 1) & 0x3) << 0) - -/* gtbus_clk_cfg */ -#define GTBUS_SRC_CLK_SELECT_SHIFT 24 -#define GTBUS_SRC_MASK (0x3 << GTBUS_SRC_CLK_SELECT_SHIFT) -#define GTBUS_SRC_OSC24M (0x0 << GTBUS_SRC_CLK_SELECT_SHIFT) -#define GTBUS_SRC_PLL_PERIPH0 (0x1 << GTBUS_SRC_CLK_SELECT_SHIFT) -#define GTBUS_SRC_PLL_PERIPH1 (0x2 << GTBUS_SRC_CLK_SELECT_SHIFT) -#define GTBUS_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) - -/* cci400_clk_cfg */ -#define CCI400_SRC_CLK_SELECT_SHIFT 24 -#define CCI400_SRC_MASK (0x3 << CCI400_SRC_CLK_SELECT_SHIFT) -#define CCI400_SRC_OSC24M (0x0 << CCI400_SRC_CLK_SELECT_SHIFT) -#define CCI400_SRC_PLL_PERIPH0 (0x1 << CCI400_SRC_CLK_SELECT_SHIFT) -#define CCI400_SRC_PLL_PERIPH1 (0x2 << CCI400_SRC_CLK_SELECT_SHIFT) -#define CCI400_CLK_DIV_RATIO(n) (((n - 1) & 0x3) << 0) - -/* sd#_clk_cfg fields */ -#define CCM_MMC_CTRL_M(x) ((x) - 1) -#define CCM_MMC_CTRL_OCLK_DLY(x) ((x) << 8) -#define CCM_MMC_CTRL_N(x) ((x) << 16) -#define CCM_MMC_CTRL_SCLK_DLY(x) ((x) << 20) -#define CCM_MMC_CTRL_OSCM24 (0 << 24) -#define CCM_MMC_CTRL_PLL_PERIPH0 (1 << 24) -#define CCM_MMC_CTRL_ENABLE (1 << 31) - -/* ahb_gate0 fields */ -#define AHB_GATE_OFFSET_MCTL 14 - -/* On sun9i all sdc-s share their ahb gate, so ignore (x) */ -#define AHB_GATE_OFFSET_NAND0 13 -#define AHB_GATE_OFFSET_MMC(x) 8 - -/* ahb gate1 field */ -#define AHB_GATE_OFFSET_DMA 24 - -/* apb1_gate fields */ -#define APB1_GATE_UART_SHIFT 16 -#define APB1_GATE_UART_MASK (0xff << APB1_GATE_UART_SHIFT) -#define APB1_GATE_TWI_SHIFT 0 -#define APB1_GATE_TWI_MASK (0xf << APB1_GATE_TWI_SHIFT) - -/* ahb_reset0_cfg fields */ -#define AHB_RESET_OFFSET_MCTL 14 - -/* On sun9i all sdc-s share their ahb reset, so ignore (x) */ -#define AHB_RESET_OFFSET_MMC(x) 8 - -/* apb1_reset_cfg fields */ -#define APB1_RESET_UART_SHIFT 16 -#define APB1_RESET_UART_MASK (0xff << APB1_RESET_UART_SHIFT) -#define APB1_RESET_TWI_SHIFT 0 -#define APB1_RESET_TWI_MASK (0xf << APB1_RESET_TWI_SHIFT) - - -#ifndef __ASSEMBLY__ -void clock_set_pll1(unsigned int clk); -void clock_set_pll2(unsigned int clk); -void clock_set_pll4(unsigned int clk); -void clock_set_pll6(unsigned int clk); -void clock_set_pll12(unsigned int clk); -unsigned int clock_get_pll4_periph0(void); -#endif - -#endif /* _SUNXI_CLOCK_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h deleted file mode 100644 index 4c399b0..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_CPU_H -#define _SUNXI_CPU_H - -#if defined(CONFIG_MACH_SUN9I) -#include <asm/arch/cpu_sun9i.h> -#elif defined(CONFIG_MACH_SUN50I_H6) -#include <asm/arch/cpu_sun50i_h6.h> -#else -#include <asm/arch/cpu_sun4i.h> -#endif - -#define SOCID_A64 0x1689 -#define SOCID_H3 0x1680 -#define SOCID_H5 0x1718 -#define SOCID_R40 0x1701 - -#endif /* _SUNXI_CPU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h deleted file mode 100644 index 02ce739..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_CPU_SUN4I_H -#define _SUNXI_CPU_SUN4I_H - -#define SUNXI_SRAM_A1_BASE 0x00000000 -#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ - -#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ -#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ -#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ -#define SUNXI_SRAM_D_BASE 0x00010000 /* 4 kiB */ -#define SUNXI_SRAM_B_BASE 0x00020000 /* 64 kiB (secure) */ - -#define SUNXI_DE2_BASE 0x01000000 - -#ifdef CONFIG_MACH_SUN8I_A83T -#define SUNXI_CPUCFG_BASE 0x01700000 -#endif - -#define SUNXI_SRAMC_BASE 0x01c00000 -#define SUNXI_DRAMC_BASE 0x01c01000 -#define SUNXI_DMA_BASE 0x01c02000 -#define SUNXI_NFC_BASE 0x01c03000 -#define SUNXI_TS_BASE 0x01c04000 -#define SUNXI_SPI0_BASE 0x01c05000 -#define SUNXI_SPI1_BASE 0x01c06000 -#define SUNXI_MS_BASE 0x01c07000 -#define SUNXI_TVD_BASE 0x01c08000 -#define SUNXI_CSI0_BASE 0x01c09000 -#ifndef CONFIG_MACH_SUNXI_H3_H5 -#define SUNXI_TVE0_BASE 0x01c0a000 -#endif -#define SUNXI_EMAC_BASE 0x01c0b000 -#define SUNXI_LCD0_BASE 0x01c0C000 -#define SUNXI_LCD1_BASE 0x01c0d000 -#define SUNXI_VE_BASE 0x01c0e000 -#define SUNXI_MMC0_BASE 0x01c0f000 -#define SUNXI_MMC1_BASE 0x01c10000 -#define SUNXI_MMC2_BASE 0x01c11000 -#define SUNXI_MMC3_BASE 0x01c12000 -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define SUNXI_USB0_BASE 0x01c13000 -#define SUNXI_USB1_BASE 0x01c14000 -#endif -#define SUNXI_SS_BASE 0x01c15000 -#if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I) -#define SUNXI_HDMI_BASE 0x01c16000 -#endif -#define SUNXI_SPI2_BASE 0x01c17000 -#define SUNXI_SATA_BASE 0x01c18000 -#ifdef CONFIG_SUNXI_GEN_SUN4I -#define SUNXI_PATA_BASE 0x01c19000 -#define SUNXI_ACE_BASE 0x01c1a000 -#define SUNXI_TVE1_BASE 0x01c1b000 -#define SUNXI_USB2_BASE 0x01c1c000 -#endif -#ifdef CONFIG_SUNXI_GEN_SUN6I -#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) -#define SUNXI_USBPHY_BASE 0x01c19000 -#define SUNXI_USB0_BASE SUNXI_USBPHY_BASE -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 -#define SUNXI_USB3_BASE 0x01c1c000 -#define SUNXI_USB4_BASE 0x01c1d000 -#else -#define SUNXI_USB0_BASE 0x01c19000 -#define SUNXI_USB1_BASE 0x01c1a000 -#define SUNXI_USB2_BASE 0x01c1b000 -#endif -#endif -#define SUNXI_CSI1_BASE 0x01c1d000 -#define SUNXI_TZASC_BASE 0x01c1e000 -#define SUNXI_SPI3_BASE 0x01c1f000 - -#define SUNXI_CCM_BASE 0x01c20000 -#define SUNXI_INTC_BASE 0x01c20400 -#define SUNXI_PIO_BASE 0x01c20800 -#define SUNXI_TIMER_BASE 0x01c20c00 -#ifndef CONFIG_SUNXI_GEN_SUN6I -#define SUNXI_PWM_BASE 0x01c20e00 -#endif -#define SUNXI_SPDIF_BASE 0x01c21000 -#ifdef CONFIG_SUNXI_GEN_SUN6I -#define SUNXI_PWM_BASE 0x01c21400 -#else -#define SUNXI_AC97_BASE 0x01c21400 -#endif -#define SUNXI_IR0_BASE 0x01c21800 -#define SUNXI_IR1_BASE 0x01c21c00 - -#define SUNXI_IIS_BASE 0x01c22400 -#define SUNXI_LRADC_BASE 0x01c22800 -#define SUNXI_AD_DA_BASE 0x01c22c00 -#define SUNXI_KEYPAD_BASE 0x01c23000 -#define SUNXI_TZPC_BASE 0x01c23400 - -#if defined(CONFIG_MACH_SUN8I_A83T) || defined(CONFIG_MACH_SUNXI_H3_H5) || \ -defined(CONFIG_MACH_SUN50I) -/* SID address space starts at 0x01c1400, but e-fuse is at offset 0x200 */ -#define SUNXI_SIDC_BASE 0x01c14000 -#define SUNXI_SID_BASE 0x01c14200 -#else -#define SUNXI_SID_BASE 0x01c23800 -#endif - -#define SUNXI_SJTAG_BASE 0x01c23c00 - -#define SUNXI_TP_BASE 0x01c25000 -#define SUNXI_PMU_BASE 0x01c25400 - -#if defined CONFIG_MACH_SUN7I || defined CONFIG_MACH_SUN8I_R40 -#define SUNXI_CPUCFG_BASE 0x01c25c00 -#endif - -#define SUNXI_UART0_BASE 0x01c28000 -#define SUNXI_UART1_BASE 0x01c28400 -#define SUNXI_UART2_BASE 0x01c28800 -#define SUNXI_UART3_BASE 0x01c28c00 -#define SUNXI_UART4_BASE 0x01c29000 -#define SUNXI_UART5_BASE 0x01c29400 -#define SUNXI_UART6_BASE 0x01c29800 -#define SUNXI_UART7_BASE 0x01c29c00 -#define SUNXI_PS2_0_BASE 0x01c2a000 -#define SUNXI_PS2_1_BASE 0x01c2a400 - -#define SUNXI_TWI0_BASE 0x01c2ac00 -#define SUNXI_TWI1_BASE 0x01c2b000 -#define SUNXI_TWI2_BASE 0x01c2b400 -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_TWI3_BASE 0x01c0b800 -#endif -#ifdef CONFIG_MACH_SUN7I -#define SUNXI_TWI3_BASE 0x01c2b800 -#define SUNXI_TWI4_BASE 0x01c2c000 -#endif - -#define SUNXI_CAN_BASE 0x01c2bc00 - -#define SUNXI_SCR_BASE 0x01c2c400 - -#ifndef CONFIG_MACH_SUN6I -#define SUNXI_GPS_BASE 0x01c30000 -#define SUNXI_MALI400_BASE 0x01c40000 -#define SUNXI_GMAC_BASE 0x01c50000 -#else -#define SUNXI_GMAC_BASE 0x01c30000 -#endif - -#define SUNXI_DRAM_COM_BASE 0x01c62000 -#define SUNXI_DRAM_CTL0_BASE 0x01c63000 -#define SUNXI_DRAM_CTL1_BASE 0x01c64000 -#define SUNXI_DRAM_PHY0_BASE 0x01c65000 -#define SUNXI_DRAM_PHY1_BASE 0x01c66000 - -#define SUNXI_GIC400_BASE 0x01c80000 - -/* module sram */ -#define SUNXI_SRAM_C_BASE 0x01d00000 - -#ifndef CONFIG_MACH_SUN8I_H3 -#define SUNXI_DE_FE0_BASE 0x01e00000 -#else -#define SUNXI_TVE0_BASE 0x01e00000 -#endif -#define SUNXI_DE_FE1_BASE 0x01e20000 -#define SUNXI_DE_BE0_BASE 0x01e60000 -#ifndef CONFIG_MACH_SUN50I_H5 -#define SUNXI_DE_BE1_BASE 0x01e40000 -#else -#define SUNXI_TVE0_BASE 0x01e40000 -#endif -#define SUNXI_MP_BASE 0x01e80000 -#define SUNXI_AVG_BASE 0x01ea0000 - -#if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I) -#define SUNXI_HDMI_BASE 0x01ee0000 -#endif - -#define SUNXI_RTC_BASE 0x01f00000 -#define SUNXI_PRCM_BASE 0x01f01400 - -#if defined CONFIG_SUNXI_GEN_SUN6I && \ - !defined CONFIG_MACH_SUN8I_A83T && \ - !defined CONFIG_MACH_SUN8I_R40 -#define SUNXI_CPUCFG_BASE 0x01f01c00 -#endif - -#define SUNXI_R_TWI_BASE 0x01f02400 -#define SUNXI_R_UART_BASE 0x01f02800 -#define SUNXI_R_PIO_BASE 0x01f02c00 -#define SUN6I_P2WI_BASE 0x01f03400 -#define SUNXI_RSB_BASE 0x01f03400 - -/* CoreSight Debug Module */ -#define SUNXI_CSDM_BASE 0x3f500000 - -#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ - -#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ - -#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) - -/* SS bonding ids used for cpu identification */ -#define SUNXI_SS_BOND_ID_A31 4 -#define SUNXI_SS_BOND_ID_A31S 5 - -#ifndef __ASSEMBLY__ -void sunxi_board_init(void); -void sunxi_reset(void); -int sunxi_get_ss_bonding_id(void); -int sunxi_get_sid(unsigned int *sid); -#endif /* __ASSEMBLY__ */ - -#endif /* _SUNXI_CPU_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h deleted file mode 100644 index 6392cb0..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SUNXI_CPU_SUN50I_H6_H -#define _SUNXI_CPU_SUN50I_H6_H - -#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS -#define SUNXI_SRAM_C_BASE 0x00028000 -#define SUNXI_SRAM_A2_BASE 0x00100000 - -#define SUNXI_DE3_BASE 0x01000000 -#define SUNXI_SS_BASE 0x01904000 -#define SUNXI_EMCE_BASE 0x01905000 - -#define SUNXI_SRAMC_BASE 0x03000000 -#define SUNXI_CCM_BASE 0x03001000 -#define SUNXI_DMA_BASE 0x03002000 -/* SID address space starts at 0x03006000, but e-fuse is at offset 0x200 */ -#define SUNXI_SIDC_BASE 0x03006000 -#define SUNXI_SID_BASE 0x03006200 -#define SUNXI_TIMER_BASE 0x03009000 -#define SUNXI_PIO_BASE 0x0300B000 -#define SUNXI_PSI_BASE 0x0300C000 - -#define SUNXI_GIC400_BASE 0x03020000 -#define SUNXI_IOMMU_BASE 0x030F0000 - -#define SUNXI_DRAM_COM_BASE 0x04002000 -#define SUNXI_DRAM_CTL0_BASE 0x04003000 -#define SUNXI_DRAM_PHY0_BASE 0x04005000 -#define SUNXI_NFC_BASE 0x04011000 -#define SUNXI_MMC0_BASE 0x04020000 -#define SUNXI_MMC1_BASE 0x04021000 -#define SUNXI_MMC2_BASE 0x04022000 - -#define SUNXI_UART0_BASE 0x05000000 -#define SUNXI_UART1_BASE 0x05000400 -#define SUNXI_UART2_BASE 0x05000800 -#define SUNXI_UART3_BASE 0x05000C00 -#define SUNXI_TWI0_BASE 0x05002000 -#define SUNXI_TWI1_BASE 0x05002400 -#define SUNXI_TWI2_BASE 0x05002800 -#define SUNXI_TWI3_BASE 0x05002C00 -#define SUNXI_SPI0_BASE 0x05010000 -#define SUNXI_SPI1_BASE 0x05011000 -#define SUNXI_GMAC_BASE 0x05020000 -#define SUNXI_USB0_BASE 0x05100000 -#define SUNXI_XHCI_BASE 0x05200000 -#define SUNXI_USB3_BASE 0x05311000 -#define SUNXI_PCIE_BASE 0x05400000 - -#define SUNXI_HDMI_BASE 0x06000000 -#define SUNXI_TCON_TOP_BASE 0x06510000 -#define SUNXI_TCON_LCD0_BASE 0x06511000 -#define SUNXI_TCON_TV0_BASE 0x06515000 - -#define SUNXI_RTC_BASE 0x07000000 -#define SUNXI_R_CPUCFG_BASE 0x07000400 -#define SUNXI_PRCM_BASE 0x07010000 -#define SUNXI_R_WDOG_BASE 0x07020400 -#define SUNXI_R_PIO_BASE 0x07022000 -#define SUNXI_R_UART_BASE 0x07080000 -#define SUNXI_R_TWI_BASE 0x07081400 - -#ifndef __ASSEMBLY__ -void sunxi_board_init(void); -void sunxi_reset(void); -int sunxi_get_sid(unsigned int *sid); -#endif - -#endif /* _SUNXI_CPU_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h deleted file mode 100644 index 9c2d11b..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Jerry Wang <wangflord@allwinnertech.com> - */ - -#ifndef _SUNXI_CPU_SUN9I_H -#define _SUNXI_CPU_SUN9I_H - -#define REGS_AHB0_BASE 0x01C00000 -#define REGS_AHB1_BASE 0x00800000 -#define REGS_AHB2_BASE 0x03000000 -#define REGS_APB0_BASE 0x06000000 -#define REGS_APB1_BASE 0x07000000 -#define REGS_RCPUS_BASE 0x08000000 - -#define SUNXI_SRAM_D_BASE 0x08100000 - -/* AHB0 Module */ -#define SUNXI_NFC_BASE (REGS_AHB0_BASE + 0x3000) -#define SUNXI_TSC_BASE (REGS_AHB0_BASE + 0x4000) - -#define SUNXI_GTBUS_BASE (REGS_AHB0_BASE + 0x9000) -/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */ -#define SUNXI_SID_BASE (REGS_AHB0_BASE + 0xe200) - -#define SUNXI_MMC0_BASE (REGS_AHB0_BASE + 0x0f000) -#define SUNXI_MMC1_BASE (REGS_AHB0_BASE + 0x10000) -#define SUNXI_MMC2_BASE (REGS_AHB0_BASE + 0x11000) -#define SUNXI_MMC3_BASE (REGS_AHB0_BASE + 0x12000) -#define SUNXI_MMC_COMMON_BASE (REGS_AHB0_BASE + 0x13000) - -#define SUNXI_SPI0_BASE (REGS_AHB0_BASE + 0x1A000) -#define SUNXI_SPI1_BASE (REGS_AHB0_BASE + 0x1B000) -#define SUNXI_SPI2_BASE (REGS_AHB0_BASE + 0x1C000) -#define SUNXI_SPI3_BASE (REGS_AHB0_BASE + 0x1D000) - -#define SUNXI_GIC400_BASE (REGS_AHB0_BASE + 0x40000) -#define SUNXI_ARMA9_GIC_BASE (REGS_AHB0_BASE + 0x41000) -#define SUNXI_ARMA9_CPUIF_BASE (REGS_AHB0_BASE + 0x42000) - -#define SUNXI_DRAM_COM_BASE (REGS_AHB0_BASE + 0x62000) -#define SUNXI_DRAM_CTL0_BASE (REGS_AHB0_BASE + 0x63000) -#define SUNXI_DRAM_CTL1_BASE (REGS_AHB0_BASE + 0x64000) -#define SUNXI_DRAM_PHY0_BASE (REGS_AHB0_BASE + 0x65000) -#define SUNXI_DRAM_PHY1_BASE (REGS_AHB0_BASE + 0x66000) - -/* AHB1 Module */ -#define SUNXI_DMA_BASE (REGS_AHB1_BASE + 0x002000) -#define SUNXI_USBOTG_BASE (REGS_AHB1_BASE + 0x100000) -#define SUNXI_USBEHCI0_BASE (REGS_AHB1_BASE + 0x200000) -#define SUNXI_USBEHCI1_BASE (REGS_AHB1_BASE + 0x201000) -#define SUNXI_USBEHCI2_BASE (REGS_AHB1_BASE + 0x202000) - -/* AHB2 Module */ -#define SUNXI_DE_SYS_BASE (REGS_AHB2_BASE + 0x000000) -#define SUNXI_DISP_SYS_BASE (REGS_AHB2_BASE + 0x010000) -#define SUNXI_DE_FE0_BASE (REGS_AHB2_BASE + 0x100000) -#define SUNXI_DE_FE1_BASE (REGS_AHB2_BASE + 0x140000) -#define SUNXI_DE_FE2_BASE (REGS_AHB2_BASE + 0x180000) - -#define SUNXI_DE_BE0_BASE (REGS_AHB2_BASE + 0x200000) -#define SUNXI_DE_BE1_BASE (REGS_AHB2_BASE + 0x240000) -#define SUNXI_DE_BE2_BASE (REGS_AHB2_BASE + 0x280000) - -#define SUNXI_DE_DEU0_BASE (REGS_AHB2_BASE + 0x300000) -#define SUNXI_DE_DEU1_BASE (REGS_AHB2_BASE + 0x340000) -#define SUNXI_DE_DRC0_BASE (REGS_AHB2_BASE + 0x400000) -#define SUNXI_DE_DRC1_BASE (REGS_AHB2_BASE + 0x440000) - -#define SUNXI_LCD0_BASE (REGS_AHB2_BASE + 0xC00000) -#define SUNXI_LCD1_BASE (REGS_AHB2_BASE + 0xC10000) -#define SUNXI_LCD2_BASE (REGS_AHB2_BASE + 0xC20000) -#define SUNXI_MIPI_DSI0_BASE (REGS_AHB2_BASE + 0xC40000) -/* Also seen as SUNXI_MIPI_DSI0_DPHY_BASE 0x01ca1000 */ -#define SUNXI_MIPI_DSI0_DPHY_BASE (REGS_AHB2_BASE + 0xC40100) -#define SUNXI_HDMI_BASE (REGS_AHB2_BASE + 0xD00000) - -/* APB0 Module */ -#define SUNXI_CCM_BASE (REGS_APB0_BASE + 0x0000) -#define SUNXI_CCMMODULE_BASE (REGS_APB0_BASE + 0x0400) -#define SUNXI_PIO_BASE (REGS_APB0_BASE + 0x0800) -#define SUNXI_TIMER_BASE (REGS_APB0_BASE + 0x0C00) -#define SUNXI_PWM_BASE (REGS_APB0_BASE + 0x1400) -#define SUNXI_LRADC_BASE (REGS_APB0_BASE + 0x1800) - -/* APB1 Module */ -#define SUNXI_UART0_BASE (REGS_APB1_BASE + 0x0000) -#define SUNXI_UART1_BASE (REGS_APB1_BASE + 0x0400) -#define SUNXI_UART2_BASE (REGS_APB1_BASE + 0x0800) -#define SUNXI_UART3_BASE (REGS_APB1_BASE + 0x0C00) -#define SUNXI_UART4_BASE (REGS_APB1_BASE + 0x1000) -#define SUNXI_UART5_BASE (REGS_APB1_BASE + 0x1400) -#define SUNXI_TWI0_BASE (REGS_APB1_BASE + 0x2800) -#define SUNXI_TWI1_BASE (REGS_APB1_BASE + 0x2C00) -#define SUNXI_TWI2_BASE (REGS_APB1_BASE + 0x3000) -#define SUNXI_TWI3_BASE (REGS_APB1_BASE + 0x3400) -#define SUNXI_TWI4_BASE (REGS_APB1_BASE + 0x3800) - -/* RCPUS Module */ -#define SUNXI_PRCM_BASE (REGS_RCPUS_BASE + 0x1400) -#define SUNXI_R_UART_BASE (REGS_RCPUS_BASE + 0x2800) -#define SUNXI_R_PIO_BASE (REGS_RCPUS_BASE + 0x2c00) -#define SUNXI_RSB_BASE (REGS_RCPUS_BASE + 0x3400) - -/* Misc. */ -#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ -#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) - -#ifndef __ASSEMBLY__ -void sunxi_board_init(void); -void sunxi_reset(void); -int sunxi_get_sid(unsigned int *sid); -#endif - -#endif /* _SUNXI_CPU_SUN9I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpucfg.h b/arch/arm/include/asm/arch-sunxi/cpucfg.h deleted file mode 100644 index 4aaebe0..0000000 --- a/arch/arm/include/asm/arch-sunxi/cpucfg.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi A31 CPUCFG register definition. - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com - */ - -#ifndef _SUNXI_CPUCFG_H -#define _SUNXI_CPUCFG_H - -#include <linux/compiler.h> -#include <linux/types.h> - -#ifndef __ASSEMBLY__ - -struct __packed sunxi_cpucfg_cpu { - u32 rst; /* base + 0x0 */ - u32 ctrl; /* base + 0x4 */ - u32 status; /* base + 0x8 */ - u8 res[0x34]; /* base + 0xc */ -}; - -struct __packed sunxi_cpucfg_reg { - u8 res0[0x40]; /* 0x000 */ - struct sunxi_cpucfg_cpu cpu[4]; /* 0x040 */ - u8 res1[0x44]; /* 0x140 */ - u32 gen_ctrl; /* 0x184 */ - u32 l2_status; /* 0x188 */ - u8 res2[0x4]; /* 0x18c */ - u32 event_in; /* 0x190 */ - u8 res3[0xc]; /* 0x194 */ - u32 super_standy_flag; /* 0x1a0 */ - u32 priv0; /* 0x1a4 */ - u32 priv1; /* 0x1a8 */ - u8 res4[0x4]; /* 0x1ac */ - u32 cpu1_pwr_clamp; /* 0x1b0 sun7i only */ - u32 cpu1_pwroff; /* 0x1b4 sun7i only */ - u8 res5[0x2c]; /* 0x1b8 */ - u32 dbg_ctrl1; /* 0x1e4 */ - u8 res6[0x18]; /* 0x1e8 */ - u32 idle_cnt0_low; /* 0x200 */ - u32 idle_cnt0_high; /* 0x204 */ - u32 idle_cnt0_ctrl; /* 0x208 */ - u8 res8[0x4]; /* 0x20c */ - u32 idle_cnt1_low; /* 0x210 */ - u32 idle_cnt1_high; /* 0x214 */ - u32 idle_cnt1_ctrl; /* 0x218 */ - u8 res9[0x4]; /* 0x21c */ - u32 idle_cnt2_low; /* 0x220 */ - u32 idle_cnt2_high; /* 0x224 */ - u32 idle_cnt2_ctrl; /* 0x228 */ - u8 res10[0x4]; /* 0x22c */ - u32 idle_cnt3_low; /* 0x230 */ - u32 idle_cnt3_high; /* 0x234 */ - u32 idle_cnt3_ctrl; /* 0x238 */ - u8 res11[0x4]; /* 0x23c */ - u32 idle_cnt4_low; /* 0x240 */ - u32 idle_cnt4_high; /* 0x244 */ - u32 idle_cnt4_ctrl; /* 0x248 */ - u8 res12[0x34]; /* 0x24c */ - u32 cnt64_ctrl; /* 0x280 */ - u32 cnt64_low; /* 0x284 */ - u32 cnt64_high; /* 0x288 */ -}; - -#endif /* __ASSEMBLY__ */ -#endif /* _SUNXI_CPUCFG_H */ diff --git a/arch/arm/include/asm/arch-sunxi/display.h b/arch/arm/include/asm/arch-sunxi/display.h deleted file mode 100644 index 525f9cb..0000000 --- a/arch/arm/include/asm/arch-sunxi/display.h +++ /dev/null @@ -1,352 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi platform display controller register and constant defines - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DISPLAY_H -#define _SUNXI_DISPLAY_H - -struct sunxi_de_fe_reg { - u32 enable; /* 0x000 */ - u32 frame_ctrl; /* 0x004 */ - u32 bypass; /* 0x008 */ - u32 algorithm_sel; /* 0x00c */ - u32 line_int_ctrl; /* 0x010 */ - u8 res0[0x0c]; /* 0x014 */ - u32 ch0_addr; /* 0x020 */ - u32 ch1_addr; /* 0x024 */ - u32 ch2_addr; /* 0x028 */ - u32 field_sequence; /* 0x02c */ - u32 ch0_offset; /* 0x030 */ - u32 ch1_offset; /* 0x034 */ - u32 ch2_offset; /* 0x038 */ - u8 res1[0x04]; /* 0x03c */ - u32 ch0_stride; /* 0x040 */ - u32 ch1_stride; /* 0x044 */ - u32 ch2_stride; /* 0x048 */ - u32 input_fmt; /* 0x04c */ - u32 ch3_addr; /* 0x050 */ - u32 ch4_addr; /* 0x054 */ - u32 ch5_addr; /* 0x058 */ - u32 output_fmt; /* 0x05c */ - u32 int_enable; /* 0x060 */ - u32 int_status; /* 0x064 */ - u32 status; /* 0x068 */ - u8 res2[0x04]; /* 0x06c */ - u32 csc_coef00; /* 0x070 */ - u32 csc_coef01; /* 0x074 */ - u32 csc_coef02; /* 0x078 */ - u32 csc_coef03; /* 0x07c */ - u32 csc_coef10; /* 0x080 */ - u32 csc_coef11; /* 0x084 */ - u32 csc_coef12; /* 0x088 */ - u32 csc_coef13; /* 0x08c */ - u32 csc_coef20; /* 0x090 */ - u32 csc_coef21; /* 0x094 */ - u32 csc_coef22; /* 0x098 */ - u32 csc_coef23; /* 0x09c */ - u32 deinterlace_ctrl; /* 0x0a0 */ - u32 deinterlace_diag; /* 0x0a4 */ - u32 deinterlace_tempdiff; /* 0x0a8 */ - u32 deinterlace_sawtooth; /* 0x0ac */ - u32 deinterlace_spatcomp; /* 0x0b0 */ - u32 deinterlace_burstlen; /* 0x0b4 */ - u32 deinterlace_preluma; /* 0x0b8 */ - u32 deinterlace_tile_addr; /* 0x0bc */ - u32 deinterlace_tile_stride; /* 0x0c0 */ - u8 res3[0x0c]; /* 0x0c4 */ - u32 wb_stride_enable; /* 0x0d0 */ - u32 ch3_stride; /* 0x0d4 */ - u32 ch4_stride; /* 0x0d8 */ - u32 ch5_stride; /* 0x0dc */ - u32 fe_3d_ctrl; /* 0x0e0 */ - u32 fe_3d_ch0_addr; /* 0x0e4 */ - u32 fe_3d_ch1_addr; /* 0x0e8 */ - u32 fe_3d_ch2_addr; /* 0x0ec */ - u32 fe_3d_ch0_offset; /* 0x0f0 */ - u32 fe_3d_ch1_offset; /* 0x0f4 */ - u32 fe_3d_ch2_offset; /* 0x0f8 */ - u8 res4[0x04]; /* 0x0fc */ - u32 ch0_insize; /* 0x100 */ - u32 ch0_outsize; /* 0x104 */ - u32 ch0_horzfact; /* 0x108 */ - u32 ch0_vertfact; /* 0x10c */ - u32 ch0_horzphase; /* 0x110 */ - u32 ch0_vertphase0; /* 0x114 */ - u32 ch0_vertphase1; /* 0x118 */ - u8 res5[0x04]; /* 0x11c */ - u32 ch0_horztapoffset0; /* 0x120 */ - u32 ch0_horztapoffset1; /* 0x124 */ - u32 ch0_verttapoffset; /* 0x128 */ - u8 res6[0xd4]; /* 0x12c */ - u32 ch1_insize; /* 0x200 */ - u32 ch1_outsize; /* 0x204 */ - u32 ch1_horzfact; /* 0x208 */ - u32 ch1_vertfact; /* 0x20c */ - u32 ch1_horzphase; /* 0x210 */ - u32 ch1_vertphase0; /* 0x214 */ - u32 ch1_vertphase1; /* 0x218 */ - u8 res7[0x04]; /* 0x21c */ - u32 ch1_horztapoffset0; /* 0x220 */ - u32 ch1_horztapoffset1; /* 0x224 */ - u32 ch1_verttapoffset; /* 0x228 */ - u8 res8[0x1d4]; /* 0x22c */ - u32 ch0_horzcoef0[32]; /* 0x400 */ - u32 ch0_horzcoef1[32]; /* 0x480 */ - u32 ch0_vertcoef[32]; /* 0x500 */ - u8 res9[0x80]; /* 0x580 */ - u32 ch1_horzcoef0[32]; /* 0x600 */ - u32 ch1_horzcoef1[32]; /* 0x680 */ - u32 ch1_vertcoef[32]; /* 0x700 */ - u8 res10[0x280]; /* 0x780 */ - u32 vpp_enable; /* 0xa00 */ - u32 vpp_dcti; /* 0xa04 */ - u32 vpp_lp1; /* 0xa08 */ - u32 vpp_lp2; /* 0xa0c */ - u32 vpp_wle; /* 0xa10 */ - u32 vpp_ble; /* 0xa14 */ -}; - -struct sunxi_de_be_reg { - u8 res0[0x800]; /* 0x000 */ - u32 mode; /* 0x800 */ - u32 backcolor; /* 0x804 */ - u32 disp_size; /* 0x808 */ - u8 res1[0x4]; /* 0x80c */ - u32 layer0_size; /* 0x810 */ - u32 layer1_size; /* 0x814 */ - u32 layer2_size; /* 0x818 */ - u32 layer3_size; /* 0x81c */ - u32 layer0_pos; /* 0x820 */ - u32 layer1_pos; /* 0x824 */ - u32 layer2_pos; /* 0x828 */ - u32 layer3_pos; /* 0x82c */ - u8 res2[0x10]; /* 0x830 */ - u32 layer0_stride; /* 0x840 */ - u32 layer1_stride; /* 0x844 */ - u32 layer2_stride; /* 0x848 */ - u32 layer3_stride; /* 0x84c */ - u32 layer0_addr_low32b; /* 0x850 */ - u32 layer1_addr_low32b; /* 0x854 */ - u32 layer2_addr_low32b; /* 0x858 */ - u32 layer3_addr_low32b; /* 0x85c */ - u32 layer0_addr_high4b; /* 0x860 */ - u32 layer1_addr_high4b; /* 0x864 */ - u32 layer2_addr_high4b; /* 0x868 */ - u32 layer3_addr_high4b; /* 0x86c */ - u32 reg_ctrl; /* 0x870 */ - u8 res3[0xc]; /* 0x874 */ - u32 color_key_max; /* 0x880 */ - u32 color_key_min; /* 0x884 */ - u32 color_key_config; /* 0x888 */ - u8 res4[0x4]; /* 0x88c */ - u32 layer0_attr0_ctrl; /* 0x890 */ - u32 layer1_attr0_ctrl; /* 0x894 */ - u32 layer2_attr0_ctrl; /* 0x898 */ - u32 layer3_attr0_ctrl; /* 0x89c */ - u32 layer0_attr1_ctrl; /* 0x8a0 */ - u32 layer1_attr1_ctrl; /* 0x8a4 */ - u32 layer2_attr1_ctrl; /* 0x8a8 */ - u32 layer3_attr1_ctrl; /* 0x8ac */ - u8 res5[0x110]; /* 0x8b0 */ - u32 output_color_ctrl; /* 0x9c0 */ - u8 res6[0xc]; /* 0x9c4 */ - u32 output_color_coef[12]; /* 0x9d0 */ -}; - -struct sunxi_hdmi_reg { - u32 version_id; /* 0x000 */ - u32 ctrl; /* 0x004 */ - u32 irq; /* 0x008 */ - u32 hpd; /* 0x00c */ - u32 video_ctrl; /* 0x010 */ - u32 video_size; /* 0x014 */ - u32 video_bp; /* 0x018 */ - u32 video_fp; /* 0x01c */ - u32 video_spw; /* 0x020 */ - u32 video_polarity; /* 0x024 */ - u8 res0[0x58]; /* 0x028 */ - u8 avi_info_frame[0x14]; /* 0x080 */ - u8 res1[0x4c]; /* 0x094 */ - u32 qcp_packet0; /* 0x0e0 */ - u32 qcp_packet1; /* 0x0e4 */ - u8 res2[0x118]; /* 0x0e8 */ - u32 pad_ctrl0; /* 0x200 */ - u32 pad_ctrl1; /* 0x204 */ - u32 pll_ctrl; /* 0x208 */ - u32 pll_dbg0; /* 0x20c */ - u32 pll_dbg1; /* 0x210 */ - u32 hpd_cec; /* 0x214 */ - u8 res3[0x28]; /* 0x218 */ - u8 vendor_info_frame[0x14]; /* 0x240 */ - u8 res4[0x9c]; /* 0x254 */ - u32 pkt_ctrl0; /* 0x2f0 */ - u32 pkt_ctrl1; /* 0x2f4 */ - u8 res5[0x8]; /* 0x2f8 */ - u32 unknown; /* 0x300 */ - u8 res6[0xc]; /* 0x304 */ - u32 audio_sample_count; /* 0x310 */ - u8 res7[0xec]; /* 0x314 */ - u32 audio_tx_fifo; /* 0x400 */ - u8 res8[0xfc]; /* 0x404 */ -#ifndef CONFIG_MACH_SUN6I - u32 ddc_ctrl; /* 0x500 */ - u32 ddc_addr; /* 0x504 */ - u32 ddc_int_mask; /* 0x508 */ - u32 ddc_int_status; /* 0x50c */ - u32 ddc_fifo_ctrl; /* 0x510 */ - u32 ddc_fifo_status; /* 0x514 */ - u32 ddc_fifo_data; /* 0x518 */ - u32 ddc_byte_count; /* 0x51c */ - u32 ddc_cmnd; /* 0x520 */ - u32 ddc_exreg; /* 0x524 */ - u32 ddc_clock; /* 0x528 */ - u8 res9[0x14]; /* 0x52c */ - u32 ddc_line_ctrl; /* 0x540 */ -#else - u32 ddc_ctrl; /* 0x500 */ - u32 ddc_exreg; /* 0x504 */ - u32 ddc_cmnd; /* 0x508 */ - u32 ddc_addr; /* 0x50c */ - u32 ddc_int_mask; /* 0x510 */ - u32 ddc_int_status; /* 0x514 */ - u32 ddc_fifo_ctrl; /* 0x518 */ - u32 ddc_fifo_status; /* 0x51c */ - u32 ddc_clock; /* 0x520 */ - u32 ddc_timeout; /* 0x524 */ - u8 res9[0x18]; /* 0x528 */ - u32 ddc_dbg; /* 0x540 */ - u8 res10[0x3c]; /* 0x544 */ - u32 ddc_fifo_data; /* 0x580 */ -#endif -}; - -/* - * DE-FE register constants. - */ -#define SUNXI_DE_FE_WIDTH(x) (((x) - 1) << 0) -#define SUNXI_DE_FE_HEIGHT(y) (((y) - 1) << 16) -#define SUNXI_DE_FE_FACTOR_INT(n) ((n) << 16) -#define SUNXI_DE_FE_ENABLE_EN (1 << 0) -#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY (1 << 0) -#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY (1 << 1) -#define SUNXI_DE_FE_FRAME_CTRL_FRM_START (1 << 16) -#define SUNXI_DE_FE_BYPASS_CSC_BYPASS (1 << 1) -#define SUNXI_DE_FE_INPUT_FMT_ARGB8888 0x00000151 -#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888 0x00000002 - -/* - * DE-BE register constants. - */ -#define SUNXI_DE_BE_WIDTH(x) (((x) - 1) << 0) -#define SUNXI_DE_BE_HEIGHT(y) (((y) - 1) << 16) -#define SUNXI_DE_BE_MODE_ENABLE (1 << 0) -#define SUNXI_DE_BE_MODE_START (1 << 1) -#define SUNXI_DE_BE_MODE_DEFLICKER_ENABLE (1 << 4) -#define SUNXI_DE_BE_MODE_LAYER0_ENABLE (1 << 8) -#define SUNXI_DE_BE_MODE_INTERLACE_ENABLE (1 << 28) -#define SUNXI_DE_BE_LAYER_STRIDE(x) ((x) << 5) -#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS (1 << 0) -#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0 0x00000002 -#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888 (0x09 << 8) -#define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE 1 - -/* - * HDMI register constants. - */ -#define SUNXI_HDMI_X(x) (((x) - 1) << 0) -#define SUNXI_HDMI_Y(y) (((y) - 1) << 16) -#define SUNXI_HDMI_CTRL_ENABLE (1 << 31) -#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF (1 << 0) -#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF (1 << 1) -#define SUNXI_HDMI_IRQ_STATUS_BITS 0x73 -#define SUNXI_HDMI_HPD_DETECT (1 << 0) -#define SUNXI_HDMI_VIDEO_CTRL_ENABLE (1 << 31) -#define SUNXI_HDMI_VIDEO_CTRL_HDMI (1 << 30) -#define SUNXI_HDMI_VIDEO_POL_HOR (1 << 0) -#define SUNXI_HDMI_VIDEO_POL_VER (1 << 1) -#define SUNXI_HDMI_VIDEO_POL_TX_CLK (0x3e0 << 16) -#define SUNXI_HDMI_QCP_PACKET0 3 -#define SUNXI_HDMI_QCP_PACKET1 0 - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_PAD_CTRL0_HDP 0x7e80000f -#define SUNXI_HDMI_PAD_CTRL0_RUN 0x7e8000ff -#else -#define SUNXI_HDMI_PAD_CTRL0_HDP 0xfe800000 -#define SUNXI_HDMI_PAD_CTRL0_RUN 0xfe800000 -#endif - -#ifdef CONFIG_MACH_SUN4I -#define SUNXI_HDMI_PAD_CTRL1 0x00d8c820 -#elif defined CONFIG_MACH_SUN6I -#define SUNXI_HDMI_PAD_CTRL1 0x01ded030 -#else -#define SUNXI_HDMI_PAD_CTRL1 0x00d8c830 -#endif -#define SUNXI_HDMI_PAD_CTRL1_HALVE (1 << 6) - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_PLL_CTRL 0xba48a308 -#define SUNXI_HDMI_PLL_CTRL_DIV(n) (((n) - 1) << 4) -#else -#define SUNXI_HDMI_PLL_CTRL 0xfa4ef708 -#define SUNXI_HDMI_PLL_CTRL_DIV(n) ((n) << 4) -#endif -#define SUNXI_HDMI_PLL_CTRL_DIV_MASK (0xf << 4) - -#define SUNXI_HDMI_PLL_DBG0_PLL3 (0 << 21) -#define SUNXI_HDMI_PLL_DBG0_PLL7 (1 << 21) - -#define SUNXI_HDMI_PKT_CTRL0 0x00000f21 -#define SUNXI_HDMI_PKT_CTRL1 0x0000000f -#define SUNXI_HDMI_UNKNOWN_INPUT_SYNC 0x08000000 - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 0) -#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE (1 << 4) -#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE (1 << 6) -#define SUNXI_HMDI_DDC_CTRL_START (1 << 27) -#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 31) -#else -#define SUNXI_HMDI_DDC_CTRL_RESET (1 << 0) -/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */ -#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE 0 -#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE 0 -#define SUNXI_HMDI_DDC_CTRL_START (1 << 30) -#define SUNXI_HMDI_DDC_CTRL_ENABLE (1 << 31) -#endif - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0xa0 << 0) -#else -#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR (0x50 << 0) -#endif -#define SUNXI_HMDI_DDC_ADDR_OFFSET(n) (((n) & 0xff) << 8) -#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR (0x60 << 16) -#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n) ((n) << 24) - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 15) -#else -#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR (1 << 31) -#endif - -#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ 6 -#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ 7 - -#ifdef CONFIG_MACH_SUN6I -#define SUNXI_HDMI_DDC_CLOCK 0x61 -#else -/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */ -#define SUNXI_HDMI_DDC_CLOCK 0x0d -#endif - -#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE (1 << 8) -#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE (1 << 9) - -int sunxi_simplefb_setup(void *blob); - -#endif /* _SUNXI_DISPLAY_H */ diff --git a/arch/arm/include/asm/arch-sunxi/display2.h b/arch/arm/include/asm/arch-sunxi/display2.h deleted file mode 100644 index 7202d27..0000000 --- a/arch/arm/include/asm/arch-sunxi/display2.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi platform display controller register and constant defines - * - * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> - * - * Based on out of tree Linux DRM driver defines: - * Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr> - * Copyright (c) 2016 Allwinnertech Co., Ltd. - */ - -#ifndef _SUNXI_DISPLAY2_H -#define _SUNXI_DISPLAY2_H - -/* internal clock settings */ -struct de_clk { - u32 gate_cfg; - u32 bus_cfg; - u32 rst_cfg; - u32 div_cfg; - u32 sel_cfg; -}; - -/* global control */ -struct de_glb { - u32 ctl; - u32 status; - u32 dbuff; - u32 size; -}; - -/* alpha blending */ -struct de_bld { - u32 fcolor_ctl; - struct { - u32 fcolor; - u32 insize; - u32 offset; - u32 dum; - } attr[4]; - u32 dum0[15]; - u32 route; - u32 premultiply; - u32 bkcolor; - u32 output_size; - u32 bld_mode[4]; - u32 dum1[4]; - u32 ck_ctl; - u32 ck_cfg; - u32 dum2[2]; - u32 ck_max[4]; - u32 dum3[4]; - u32 ck_min[4]; - u32 dum4[3]; - u32 out_ctl; -}; - -/* VI channel */ -struct de_vi { - struct { - u32 attr; - u32 size; - u32 coord; - u32 pitch[3]; - u32 top_laddr[3]; - u32 bot_laddr[3]; - } cfg[4]; - u32 fcolor[4]; - u32 top_haddr[3]; - u32 bot_haddr[3]; - u32 ovl_size[2]; - u32 hori[2]; - u32 vert[2]; -}; - -struct de_ui { - struct { - u32 attr; - u32 size; - u32 coord; - u32 pitch; - u32 top_laddr; - u32 bot_laddr; - u32 fcolor; - u32 dum; - } cfg[4]; - u32 top_haddr; - u32 bot_haddr; - u32 ovl_size; -}; - -struct de_csc { - u32 csc_ctl; - u8 res[0xc]; - u32 coef11; - u32 coef12; - u32 coef13; - u32 coef14; - u32 coef21; - u32 coef22; - u32 coef23; - u32 coef24; - u32 coef31; - u32 coef32; - u32 coef33; - u32 coef34; -}; - -/* - * DE register constants. - */ -#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000) -#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000) - -#define SUNXI_DE2_MUX_GLB_REGS 0x00000 -#define SUNXI_DE2_MUX_BLD_REGS 0x01000 -#define SUNXI_DE2_MUX_CHAN_REGS 0x02000 -#define SUNXI_DE2_MUX_CHAN_SZ 0x1000 -#define SUNXI_DE2_MUX_VSU_REGS 0x20000 -#define SUNXI_DE2_MUX_GSU1_REGS 0x30000 -#define SUNXI_DE2_MUX_GSU2_REGS 0x40000 -#define SUNXI_DE2_MUX_GSU3_REGS 0x50000 -#define SUNXI_DE2_MUX_FCE_REGS 0xa0000 -#define SUNXI_DE2_MUX_BWS_REGS 0xa2000 -#define SUNXI_DE2_MUX_LTI_REGS 0xa4000 -#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000 -#define SUNXI_DE2_MUX_ASE_REGS 0xa8000 -#define SUNXI_DE2_MUX_FCC_REGS 0xaa000 -#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000 - -#define SUNXI_DE2_FORMAT_XRGB_8888 4 -#define SUNXI_DE2_FORMAT_RGB_565 10 - -#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0) -#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0) -#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8) - -#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1)) - -#endif /* _SUNXI_DISPLAY2_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dma.h b/arch/arm/include/asm/arch-sunxi/dma.h deleted file mode 100644 index bd4c84f..0000000 --- a/arch/arm/include/asm/arch-sunxi/dma.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> - */ - -#ifndef _SUNXI_DMA_H -#define _SUNXI_DMA_H - -#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN5I) || defined(CONFIG_MACH_SUN7I) -#include <asm/arch/dma_sun4i.h> -#else -#error "DMA definition not available for this architecture" -#endif - -#endif /* _SUNXI_DMA_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dma_sun4i.h b/arch/arm/include/asm/arch-sunxi/dma_sun4i.h deleted file mode 100644 index 309dc4f..0000000 --- a/arch/arm/include/asm/arch-sunxi/dma_sun4i.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Roy Spliet <rspliet@ultimaker.com> - */ - -#ifndef _SUNXI_DMA_SUN4I_H -#define _SUNXI_DMA_SUN4I_H - -struct sunxi_dma_cfg -{ - u32 ctl; /* 0x00 Control */ - u32 src_addr; /* 0x04 Source address */ - u32 dst_addr; /* 0x08 Destination address */ - u32 bc; /* 0x0C Byte counter */ - u32 res0[2]; - u32 ddma_para; /* 0x18 extra parameter (dedicated DMA only) */ - u32 res1; -}; - -struct sunxi_dma -{ - u32 irq_en; /* 0x000 IRQ enable */ - u32 irq_pend; /* 0x004 IRQ pending */ - u32 auto_gate; /* 0x008 auto gating */ - u32 res0[61]; - struct sunxi_dma_cfg ndma[8]; /* 0x100 Normal DMA */ - u32 res1[64]; - struct sunxi_dma_cfg ddma[8]; /* 0x300 Dedicated DMA */ -}; - -enum ddma_drq_type { - DDMA_DST_DRQ_SRAM = 0, - DDMA_SRC_DRQ_SRAM = 0, - DDMA_DST_DRQ_SDRAM = 1, - DDMA_SRC_DRQ_SDRAM = 1, - DDMA_DST_DRQ_PATA = 2, - DDMA_SRC_DRQ_PATA = 2, - DDMA_DST_DRQ_NAND = 3, - DDMA_SRC_DRQ_NAND = 3, - DDMA_DST_DRQ_USB0 = 4, - DDMA_SRC_DRQ_USB0 = 4, - DDMA_DST_DRQ_ETHERNET_MAC_TX = 6, - DDMA_SRC_DRQ_ETHERNET_MAC_RX = 7, - DDMA_DST_DRQ_SPI1_TX = 8, - DDMA_SRC_DRQ_SPI1_RX = 9, - DDMA_DST_DRQ_SECURITY_SYS_TX = 10, - DDMA_SRC_DRQ_SECURITY_SYS_RX = 11, - DDMA_DST_DRQ_TCON0 = 14, - DDMA_DST_DRQ_TCON1 = 15, - DDMA_DST_DRQ_MSC = 23, - DDMA_SRC_DRQ_MSC = 23, - DDMA_DST_DRQ_SPI0_TX = 26, - DDMA_SRC_DRQ_SPI0_RX = 27, - DDMA_DST_DRQ_SPI2_TX = 28, - DDMA_SRC_DRQ_SPI2_RX = 29, - DDMA_DST_DRQ_SPI3_TX = 30, - DDMA_SRC_DRQ_SPI3_RX = 31, -}; - -#define SUNXI_DMA_CTL_SRC_DRQ(a) ((a) & 0x1f) -#define SUNXI_DMA_CTL_MODE_IO (1 << 5) -#define SUNXI_DMA_CTL_SRC_DATA_WIDTH_32 (2 << 9) -#define SUNXI_DMA_CTL_DST_DRQ(a) (((a) & 0x1f) << 16) -#define SUNXI_DMA_CTL_DST_DATA_WIDTH_32 (2 << 25) -#define SUNXI_DMA_CTL_TRIGGER (1 << 31) - -#endif /* _SUNXI_DMA_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h deleted file mode 100644 index 8002b7e..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * Sunxi platform dram register definition. - */ - -#ifndef _SUNXI_DRAM_H -#define _SUNXI_DRAM_H - -#include <asm/io.h> -#include <linux/types.h> - -/* dram regs definition */ -#if defined(CONFIG_MACH_SUN6I) -#include <asm/arch/dram_sun6i.h> -#elif defined(CONFIG_MACH_SUN8I_A23) -#include <asm/arch/dram_sun8i_a23.h> -#elif defined(CONFIG_MACH_SUN8I_A33) -#include <asm/arch/dram_sun8i_a33.h> -#elif defined(CONFIG_MACH_SUN8I_A83T) -#include <asm/arch/dram_sun8i_a83t.h> -#elif defined(CONFIG_SUNXI_DRAM_DW) -#include <asm/arch/dram_sunxi_dw.h> -#elif defined(CONFIG_MACH_SUN9I) -#include <asm/arch/dram_sun9i.h> -#elif defined(CONFIG_MACH_SUN50I_H6) -#include <asm/arch/dram_sun50i_h6.h> -#else -#include <asm/arch/dram_sun4i.h> -#endif - -unsigned long sunxi_dram_init(void); -void mctl_await_completion(u32 *reg, u32 mask, u32 val); -bool mctl_mem_matches(u32 offset); - -#endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h b/arch/arm/include/asm/arch-sunxi/dram_sun4i.h deleted file mode 100644 index 69c6600..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun4i.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * Sunxi platform dram register definition. - */ - -#ifndef _SUNXI_DRAM_SUN4I_H -#define _SUNXI_DRAM_SUN4I_H - -struct sunxi_dram_reg { - u32 ccr; /* 0x00 controller configuration register */ - u32 dcr; /* 0x04 dram configuration register */ - u32 iocr; /* 0x08 i/o configuration register */ - u32 csr; /* 0x0c controller status register */ - u32 drr; /* 0x10 dram refresh register */ - u32 tpr0; /* 0x14 dram timing parameters register 0 */ - u32 tpr1; /* 0x18 dram timing parameters register 1 */ - u32 tpr2; /* 0x1c dram timing parameters register 2 */ - u32 gdllcr; /* 0x20 global dll control register */ - u8 res0[0x28]; - u32 rslr0; /* 0x4c rank system latency register */ - u32 rslr1; /* 0x50 rank system latency register */ - u8 res1[0x8]; - u32 rdgr0; /* 0x5c rank dqs gating register */ - u32 rdgr1; /* 0x60 rank dqs gating register */ - u8 res2[0x34]; - u32 odtcr; /* 0x98 odt configuration register */ - u32 dtr0; /* 0x9c data training register 0 */ - u32 dtr1; /* 0xa0 data training register 1 */ - u32 dtar; /* 0xa4 data training address register */ - u32 zqcr0; /* 0xa8 zq control register 0 */ - u32 zqcr1; /* 0xac zq control register 1 */ - u32 zqsr; /* 0xb0 zq status register */ - u32 idcr; /* 0xb4 initializaton delay configure reg */ - u8 res3[0x138]; - u32 mr; /* 0x1f0 mode register */ - u32 emr; /* 0x1f4 extended mode register */ - u32 emr2; /* 0x1f8 extended mode register */ - u32 emr3; /* 0x1fc extended mode register */ - u32 dllctr; /* 0x200 dll control register */ - u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ - /* 0x208 dll control register 1(byte 1) */ - /* 0x20c dll control register 2(byte 2) */ - /* 0x210 dll control register 3(byte 3) */ - /* 0x214 dll control register 4(byte 4) */ - u32 dqtr0; /* 0x218 dq timing register */ - u32 dqtr1; /* 0x21c dq timing register */ - u32 dqtr2; /* 0x220 dq timing register */ - u32 dqtr3; /* 0x224 dq timing register */ - u32 dqstr; /* 0x228 dqs timing register */ - u32 dqsbtr; /* 0x22c dqsb timing register */ - u32 mcr; /* 0x230 mode configure register */ - u8 res[0x8]; - u32 ppwrsctl; /* 0x23c pad power save control */ - u32 apr; /* 0x240 arbiter period register */ - u32 pldtr; /* 0x244 priority level data threshold reg */ - u8 res5[0x8]; - u32 hpcr[32]; /* 0x250 host port configure register */ - u8 res6[0x10]; - u32 csel; /* 0x2e0 controller select register */ -}; - -struct dram_para { - u32 clock; - u32 mbus_clock; - u32 type; - u32 rank_num; - u32 density; - u32 io_width; - u32 bus_width; - u32 cas; - u32 zq; - u32 odt_en; - u32 size; /* For compat with dram.c files from u-boot-sunxi, unused */ - u32 tpr0; - u32 tpr1; - u32 tpr2; - u32 tpr3; - u32 tpr4; - u32 tpr5; - u32 emr1; - u32 emr2; - u32 emr3; - u32 dqs_gating_delay; - u32 active_windowing; -}; - -#define DRAM_CCR_COMMAND_RATE_1T (0x1 << 5) -#define DRAM_CCR_DQS_GATE (0x1 << 14) -#define DRAM_CCR_DQS_DRIFT_COMP (0x1 << 17) -#define DRAM_CCR_ITM_OFF (0x1 << 28) -#define DRAM_CCR_DATA_TRAINING (0x1 << 30) -#define DRAM_CCR_INIT (0x1 << 31) - -#define DRAM_MEMORY_TYPE_DDR1 1 -#define DRAM_MEMORY_TYPE_DDR2 2 -#define DRAM_MEMORY_TYPE_DDR3 3 -#define DRAM_MEMORY_TYPE_LPDDR2 4 -#define DRAM_MEMORY_TYPE_LPDDR 5 -#define DRAM_DCR_TYPE (0x1 << 0) -#define DRAM_DCR_TYPE_DDR2 0x0 -#define DRAM_DCR_TYPE_DDR3 0x1 -#define DRAM_DCR_IO_WIDTH(n) (((n) & 0x3) << 1) -#define DRAM_DCR_IO_WIDTH_MASK DRAM_DCR_IO_WIDTH(0x3) -#define DRAM_DCR_IO_WIDTH_8BIT 0x0 -#define DRAM_DCR_IO_WIDTH_16BIT 0x1 -#define DRAM_DCR_CHIP_DENSITY(n) (((n) & 0x7) << 3) -#define DRAM_DCR_CHIP_DENSITY_MASK DRAM_DCR_CHIP_DENSITY(0x7) -#define DRAM_DCR_CHIP_DENSITY_256M 0x0 -#define DRAM_DCR_CHIP_DENSITY_512M 0x1 -#define DRAM_DCR_CHIP_DENSITY_1024M 0x2 -#define DRAM_DCR_CHIP_DENSITY_2048M 0x3 -#define DRAM_DCR_CHIP_DENSITY_4096M 0x4 -#define DRAM_DCR_CHIP_DENSITY_8192M 0x5 -#define DRAM_DCR_BUS_WIDTH(n) (((n) & 0x7) << 6) -#define DRAM_DCR_BUS_WIDTH_MASK DRAM_DCR_BUS_WIDTH(0x7) -#define DRAM_DCR_BUS_WIDTH_32BIT 0x3 -#define DRAM_DCR_BUS_WIDTH_16BIT 0x1 -#define DRAM_DCR_BUS_WIDTH_8BIT 0x0 -#define DRAM_DCR_RANK_SEL(n) (((n) & 0x3) << 10) -#define DRAM_DCR_RANK_SEL_MASK DRAM_DCR_CMD_RANK(0x3) -#define DRAM_DCR_CMD_RANK_ALL (0x1 << 12) -#define DRAM_DCR_MODE(n) (((n) & 0x3) << 13) -#define DRAM_DCR_MODE_MASK DRAM_DCR_MODE(0x3) -#define DRAM_DCR_MODE_SEQ 0x0 -#define DRAM_DCR_MODE_INTERLEAVE 0x1 - -#define DRAM_CSR_DTERR (0x1 << 20) -#define DRAM_CSR_DTIERR (0x1 << 21) -#define DRAM_CSR_FAILED (DRAM_CSR_DTERR | DRAM_CSR_DTIERR) - -#define DRAM_DRR_TRFC(n) ((n) & 0xff) -#define DRAM_DRR_TREFI(n) (((n) & 0xffff) << 8) -#define DRAM_DRR_BURST(n) ((((n) - 1) & 0xf) << 24) - -#define DRAM_MCR_MODE_NORM(n) (((n) & 0x3) << 0) -#define DRAM_MCR_MODE_NORM_MASK DRAM_MCR_MOD_NORM(0x3) -#define DRAM_MCR_MODE_DQ_OUT(n) (((n) & 0x3) << 2) -#define DRAM_MCR_MODE_DQ_OUT_MASK DRAM_MCR_MODE_DQ_OUT(0x3) -#define DRAM_MCR_MODE_ADDR_OUT(n) (((n) & 0x3) << 4) -#define DRAM_MCR_MODE_ADDR_OUT_MASK DRAM_MCR_MODE_ADDR_OUT(0x3) -#define DRAM_MCR_MODE_DQ_IN_OUT(n) (((n) & 0x3) << 6) -#define DRAM_MCR_MODE_DQ_IN_OUT_MASK DRAM_MCR_MODE_DQ_IN_OUT(0x3) -#define DRAM_MCR_MODE_DQ_TURNON_DELAY(n) (((n) & 0x7) << 8) -#define DRAM_MCR_MODE_DQ_TURNON_DELAY_MASK DRAM_MCR_MODE_DQ_TURNON_DELAY(0x7) -#define DRAM_MCR_MODE_ADDR_IN (0x1 << 11) -#define DRAM_MCR_RESET (0x1 << 12) -#define DRAM_MCR_MODE_EN(n) (((n) & 0x3) << 13) -#define DRAM_MCR_MODE_EN_MASK DRAM_MCR_MOD_EN(0x3) -#define DRAM_MCR_DCLK_OUT (0x1 << 16) - -#define DRAM_DLLCR_NRESET (0x1 << 30) -#define DRAM_DLLCR_DISABLE (0x1 << 31) - -#define DRAM_ZQCR0_IMP_DIV(n) (((n) & 0xff) << 20) -#define DRAM_ZQCR0_IMP_DIV_MASK DRAM_ZQCR0_IMP_DIV(0xff) -#define DRAM_ZQCR0_ZCAL (1 << 31) /* Starts ZQ calibration when set to 1 */ -#define DRAM_ZQCR0_ZDEN (1 << 28) /* Uses ZDATA instead of doing calibration */ - -#define DRAM_ZQSR_ZDONE (1 << 31) /* ZQ calibration completion flag */ - -#define DRAM_IOCR_ODT_EN ((3 << 30) | (3 << 0)) - -#define DRAM_MR_BURST_LENGTH(n) (((n) & 0x7) << 0) -#define DRAM_MR_BURST_LENGTH_MASK DRAM_MR_BURST_LENGTH(0x7) -#define DRAM_MR_CAS_LAT(n) (((n) & 0x7) << 4) -#define DRAM_MR_CAS_LAT_MASK DRAM_MR_CAS_LAT(0x7) -#define DRAM_MR_WRITE_RECOVERY(n) (((n) & 0x7) << 9) -#define DRAM_MR_WRITE_RECOVERY_MASK DRAM_MR_WRITE_RECOVERY(0x7) -#define DRAM_MR_POWER_DOWN (0x1 << 12) - -#define DRAM_CSEL_MAGIC 0x16237495 - -unsigned long dramc_init(struct dram_para *para); - -#endif /* _SUNXI_DRAM_SUN4I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h deleted file mode 100644 index 0a1da02..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * H6 dram controller register and constant defines - * - * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef _SUNXI_DRAM_SUN50I_H6_H -#define _SUNXI_DRAM_SUN50I_H6_H - -#include <stdbool.h> - -enum sunxi_dram_type { - SUNXI_DRAM_TYPE_DDR3 = 3, - SUNXI_DRAM_TYPE_DDR4, - SUNXI_DRAM_TYPE_LPDDR2 = 6, - SUNXI_DRAM_TYPE_LPDDR3, -}; - -static inline bool sunxi_dram_is_lpddr(int type) -{ - return type >= SUNXI_DRAM_TYPE_LPDDR2; -} - -/* - * The following information is mainly retrieved by disassembly and some FPGA - * test code of sun50iw3 platform. - */ -struct sunxi_mctl_com_reg { - u32 cr; /* 0x000 control register */ - u8 reserved_0x004[4]; /* 0x004 */ - u32 unk_0x008; /* 0x008 */ - u32 tmr; /* 0x00c timer register */ - u8 reserved_0x010[4]; /* 0x010 */ - u32 unk_0x014; /* 0x014 */ - u8 reserved_0x018[8]; /* 0x018 */ - u32 maer0; /* 0x020 master enable register 0 */ - u32 maer1; /* 0x024 master enable register 1 */ - u32 maer2; /* 0x028 master enable register 2 */ - u8 reserved_0x02c[468]; /* 0x02c */ - u32 bwcr; /* 0x200 bandwidth control register */ - u8 reserved_0x204[12]; /* 0x204 */ - /* - * The last master configured by BSP libdram is at 0x49x, so the - * size of this struct array is set to 41 (0x29) now. - */ - struct { - u32 cfg0; /* 0x0 */ - u32 cfg1; /* 0x4 */ - u8 reserved_0x8[8]; /* 0x8 */ - } master[41]; /* 0x210 + index * 0x10 */ -}; -check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498); - -/* - * The following register information are retrieved from some similar DRAM - * controllers, including the DRAM controllers in Allwinner A23/A80 SoCs, - * Rockchip RK3328 SoC, NXP i.MX7 SoCs and Xilinx Zynq UltraScale+ SoCs. - * - * The DRAM controller in Allwinner A23/A80 SoCs and NXP i.MX7 SoCs seems - * to be older than the one in Allwinner H6, as the DRAMTMG9 register - * is missing in these SoCs. (From the product specifications of these - * SoCs they're not capable of DDR4) - * - * Information sources: - * - dram_sun9i.h and dram_sun8i_a23.h in the same directory. - * - sdram_rk3328.h from the RK3328 TPL DRAM patchset - * - i.MX 7Solo Applications Processor Reference Manual (IMX7SRM) - * - Zynq UltraScale+ MPSoC Register Reference (UG1087) - */ -struct sunxi_mctl_ctl_reg { - u32 mstr; /* 0x000 */ - u32 statr; /* 0x004 unused */ - u32 mstr1; /* 0x008 unused */ - u32 unk_0x00c; /* 0x00c */ - u32 mrctrl0; /* 0x010 unused */ - u32 mrctrl1; /* 0x014 unused */ - u32 mrstatr; /* 0x018 unused */ - u32 mrctrl2; /* 0x01c unused */ - u32 derateen; /* 0x020 unused */ - u32 derateint; /* 0x024 unused */ - u8 reserved_0x028[8]; /* 0x028 */ - u32 pwrctl; /* 0x030 unused */ - u32 pwrtmg; /* 0x034 unused */ - u32 hwlpctl; /* 0x038 unused */ - u8 reserved_0x03c[20]; /* 0x03c */ - u32 rfshctl0; /* 0x050 unused */ - u32 rfshctl1; /* 0x054 unused */ - u8 reserved_0x058[8]; /* 0x05c */ - u32 rfshctl3; /* 0x060 */ - u32 rfshtmg; /* 0x064 */ - u8 reserved_0x068[104]; /* 0x068 reserved for ECC&CRC (from ZynqMP) */ - u32 init[8]; /* 0x0d0 */ - u32 dimmctl; /* 0x0f0 unused */ - u32 rankctl; /* 0x0f4 */ - u8 reserved_0x0f8[8]; /* 0x0f8 */ - u32 dramtmg[17]; /* 0x100 */ - u8 reserved_0x144[60]; /* 0x144 */ - u32 zqctl[3]; /* 0x180 */ - u32 zqstat; /* 0x18c unused */ - u32 dfitmg0; /* 0x190 */ - u32 dfitmg1; /* 0x194 */ - u32 dfilpcfg[2]; /* 0x198 unused */ - u32 dfiupd[3]; /* 0x1a0 */ - u32 reserved_0x1ac; /* 0x1ac */ - u32 dfimisc; /* 0x1b0 */ - u32 dfitmg2; /* 0x1b4 unused, may not exist */ - u8 reserved_0x1b8[8]; /* 0x1b8 */ - u32 dbictl; /* 0x1c0 */ - u8 reserved_0x1c4[60]; /* 0x1c4 */ - u32 addrmap[12]; /* 0x200 */ - u8 reserved_0x230[16]; /* 0x230 */ - u32 odtcfg; /* 0x240 */ - u32 odtmap; /* 0x244 */ - u8 reserved_0x248[8]; /* 0x248 */ - u32 sched[2]; /* 0x250 */ - u8 reserved_0x258[180]; /* 0x258 */ - u32 dbgcmd; /* 0x30c unused */ - u32 dbgstat; /* 0x310 unused */ - u8 reserved_0x314[12]; /* 0x314 */ - u32 swctl; /* 0x320 */ - u32 swstat; /* 0x324 */ -}; -check_member(sunxi_mctl_ctl_reg, swstat, 0x324); - -#define MSTR_DEVICETYPE_DDR3 BIT(0) -#define MSTR_DEVICETYPE_LPDDR2 BIT(2) -#define MSTR_DEVICETYPE_LPDDR3 BIT(3) -#define MSTR_DEVICETYPE_DDR4 BIT(4) -#define MSTR_DEVICETYPE_MASK GENMASK(5, 0) -#define MSTR_2TMODE BIT(10) -#define MSTR_BUSWIDTH_FULL (0 << 12) -#define MSTR_BUSWIDTH_HALF (1 << 12) -#define MSTR_ACTIVE_RANKS(x) (((x == 2) ? 3 : 1) << 24) -#define MSTR_BURST_LENGTH(x) (((x) >> 1) << 16) - -/* - * The following register information is based on Zynq UltraScale+ - * MPSoC Register Reference, as it's the currently only known - * DDR PHY similar to the one used in H6; however although the - * map is similar, the bit fields definitions are different. - * - * Other DesignWare DDR PHY's have similar register names, but the - * offset and definitions are both different. - */ -struct sunxi_mctl_phy_reg { - u32 ver; /* 0x000 guess based on similar PHYs */ - u32 pir; /* 0x004 */ - u8 reserved_0x008[8]; /* 0x008 */ - /* - * The ZynqMP manual didn't document PGCR1, however this register - * exists on H6 and referenced by libdram. - */ - u32 pgcr[8]; /* 0x010 */ - /* - * By comparing the hardware and the ZynqMP manual, the PGSR seems - * to start at 0x34 on H6. - */ - u8 reserved_0x030[4]; /* 0x030 */ - u32 pgsr[3]; /* 0x034 */ - u32 ptr[7]; /* 0x040 */ - /* - * According to ZynqMP reference there's PLLCR0~6 in this area, - * but they're tagged "Type B PLL Only" and H6 seems to have - * no them. - * 0x080 is not present in ZynqMP reference but it seems to be - * present on H6. - */ - u8 reserved_0x05c[36]; /* 0x05c */ - u32 unk_0x080; /* 0x080 */ - u8 reserved_0x084[4]; /* 0x084 */ - u32 dxccr; /* 0x088 */ - u8 reserved_0x08c[4]; /* 0x08c */ - u32 dsgcr; /* 0x090 */ - u8 reserved_0x094[4]; /* 0x094 */ - u32 odtcr; /* 0x098 */ - u8 reserved_0x09c[4]; /* 0x09c */ - u32 aacr; /* 0x0a0 */ - u8 reserved_0x0a4[32]; /* 0x0a4 */ - u32 gpr1; /* 0x0c4 */ - u8 reserved_0x0c8[56]; /* 0x0c8 */ - u32 dcr; /* 0x100 */ - u8 reserved_0x104[12]; /* 0x104 */ - u32 dtpr[7]; /* 0x110 */ - u8 reserved_0x12c[20]; /* 0x12c */ - u32 rdimmgcr[3]; /* 0x140 */ - u8 reserved_0x14c[4]; /* 0x14c */ - u32 rdimmcr[5]; /* 0x150 */ - u8 reserved_0x164[4]; /* 0x164 */ - u32 schcr[2]; /* 0x168 */ - u8 reserved_0x170[16]; /* 0x170 */ - /* - * The ZynqMP manual documents MR0~7, 11~14 and 22. - */ - u32 mr[23]; /* 0x180 */ - u8 reserved_0x1dc[36]; /* 0x1dc */ - u32 dtcr[2]; /* 0x200 */ - u32 dtar[3]; /* 0x208 */ - u8 reserved_0x214[4]; /* 0x214 */ - u32 dtdr[2]; /* 0x218 */ - u8 reserved_0x220[16]; /* 0x220 */ - u32 dtedr0; /* 0x230 */ - u32 dtedr1; /* 0x234 */ - u32 dtedr2; /* 0x238 */ - u32 vtdr; /* 0x23c */ - u32 catr[2]; /* 0x240 */ - u8 reserved_0x248[8]; - u32 dqsdr[3]; /* 0x250 */ - u32 dtedr3; /* 0x25c */ - u8 reserved_0x260[160]; /* 0x260 */ - u32 dcuar; /* 0x300 */ - u32 dcudr; /* 0x304 */ - u32 dcurr; /* 0x308 */ - u32 dculr; /* 0x30c */ - u32 dcugcr; /* 0x310 */ - u32 dcutpr; /* 0x314 */ - u32 dcusr[2]; /* 0x318 */ - u8 reserved_0x320[444]; /* 0x320 */ - u32 rankidr; /* 0x4dc */ - u32 riocr[6]; /* 0x4e0 */ - u8 reserved_0x4f8[8]; /* 0x4f8 */ - u32 aciocr[6]; /* 0x500 */ - u8 reserved_0x518[8]; /* 0x518 */ - u32 iovcr[2]; /* 0x520 */ - u32 vtcr[2]; /* 0x528 */ - u8 reserved_0x530[16]; /* 0x530 */ - u32 acbdlr[17]; /* 0x540 */ - u32 aclcdlr; /* 0x584 */ - u8 reserved_0x588[24]; /* 0x588 */ - u32 acmdlr[2]; /* 0x5a0 */ - u8 reserved_0x5a8[216]; /* 0x5a8 */ - struct { - u32 zqcr; /* 0x00 only the first one valid */ - u32 zqpr[2]; /* 0x04 */ - u32 zqdr[2]; /* 0x0c */ - u32 zqor[2]; /* 0x14 */ - u32 zqsr; /* 0x1c */ - } zq[2]; /* 0x680, 0x6a0 */ - u8 reserved_0x6c0[64]; /* 0x6c0 */ - struct { - u32 gcr[7]; /* 0x00 */ - u8 reserved_0x1c[36]; /* 0x1c */ - u32 bdlr0; /* 0x40 */ - u32 bdlr1; /* 0x44 */ - u32 bdlr2; /* 0x48 */ - u8 reserved_0x4c[4]; /* 0x4c */ - u32 bdlr3; /* 0x50 */ - u32 bdlr4; /* 0x54 */ - u32 bdlr5; /* 0x58 */ - u8 reserved_0x5c[4]; /* 0x5c */ - u32 bdlr6; /* 0x60 */ - u8 reserved_0x64[28]; /* 0x64 */ - u32 lcdlr[6]; /* 0x80 */ - u8 reserved_0x98[8]; /* 0x98 */ - u32 mdlr[2]; /* 0xa0 */ - u8 reserved_0xa8[24]; /* 0xa8 */ - u32 gtr0; /* 0xc0 */ - u8 reserved_0xc4[12]; /* 0xc4 */ - /* - * DXnRSR0 is not documented in ZynqMP manual but - * it's used in libdram. - */ - u32 rsr[4]; /* 0xd0 */ - u32 gsr[4]; /* 0xe0 */ - u8 reserved_0xf0[16]; /* 0xf0 */ - } dx[4]; /* 0x700, 0x800, 0x900, 0xa00 */ -}; -check_member(sunxi_mctl_phy_reg, dx[3].reserved_0xf0, 0xaf0); - -#define PIR_INIT BIT(0) -#define PIR_ZCAL BIT(1) -#define PIR_CA BIT(2) -#define PIR_PLLINIT BIT(4) -#define PIR_DCAL BIT(5) -#define PIR_PHYRST BIT(6) -#define PIR_DRAMRST BIT(7) -#define PIR_DRAMINIT BIT(8) -#define PIR_WL BIT(9) -#define PIR_QSGATE BIT(10) -#define PIR_WLADJ BIT(11) -#define PIR_RDDSKW BIT(12) -#define PIR_WRDSKW BIT(13) -#define PIR_RDEYE BIT(14) -#define PIR_WREYE BIT(15) -#define PIR_VREF BIT(17) -#define PIR_CTLDINIT BIT(18) -#define PIR_DQS2DQ BIT(20) -#define PIR_DCALPSE BIT(29) -#define PIR_ZCALBYP BIT(30) - -#define DCR_LPDDR3 (1 << 0) -#define DCR_DDR3 (3 << 0) -#define DCR_DDR4 (4 << 0) -#define DCR_DDR8BANK BIT(3) -#define DCR_DDR2T BIT(28) - -/* - * The delay parameters allow to allegedly specify delay times of some - * unknown unit for each individual bit trace in each of the four data bytes - * the 32-bit wide access consists of. Also three control signals can be - * adjusted individually. - */ -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable and DQSN */ -#define WR_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 4) -/* - * The eight data lines (DQn) plus DM, DQS, DQS/DM/DQ Output Enable, DQSN, - * Termination and Power down - */ -#define RD_LINES_PER_BYTE_LANE (BITS_PER_BYTE + 6) -struct dram_para { - u32 clk; - enum sunxi_dram_type type; - u8 cols; - u8 rows; - u8 ranks; - const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE]; -}; - - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; - - return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); -} - -void mctl_set_timing_params(struct dram_para *para); - -#endif /* _SUNXI_DRAM_SUN50I_H6_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h b/arch/arm/include/asm/arch-sunxi/dram_sun6i.h deleted file mode 100644 index 929450f..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun6i.h +++ /dev/null @@ -1,358 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun6i platform dram controller register and constant defines - * - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DRAM_SUN6I_H -#define _SUNXI_DRAM_SUN6I_H - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u32 dbgcr1; /* 0x0c */ - u32 rmcr[8]; /* 0x10 */ - u32 mmcr[16]; /* 0x30 */ - u32 mbagcr[6]; /* 0x70 */ - u32 maer; /* 0x88 */ - u8 res0[0x14]; /* 0x8c */ - u32 mdfscr; /* 0x100 */ - u32 mdfsmer; /* 0x104 */ - u32 mdfsmrmr; /* 0x108 */ - u32 mdfstr0; /* 0x10c */ - u32 mdfstr1; /* 0x110 */ - u32 mdfstr2; /* 0x114 */ - u32 mdfstr3; /* 0x118 */ - u32 mdfsgcr; /* 0x11c */ - u8 res1[0x1c]; /* 0x120 */ - u32 mdfsivr; /* 0x13c */ - u8 res2[0x0c]; /* 0x140 */ - u32 mdfstcr; /* 0x14c */ -}; - -struct sunxi_mctl_ctl_reg { - u8 res0[0x04]; /* 0x00 */ - u32 sctl; /* 0x04 */ - u32 sstat; /* 0x08 */ - u8 res1[0x34]; /* 0x0c */ - u32 mcmd; /* 0x40 */ - u8 res2[0x08]; /* 0x44 */ - u32 cmdstat; /* 0x4c */ - u32 cmdstaten; /* 0x50 */ - u8 res3[0x0c]; /* 0x54 */ - u32 mrrcfg0; /* 0x60 */ - u32 mrrstat0; /* 0x64 */ - u32 mrrstat1; /* 0x68 */ - u8 res4[0x10]; /* 0x6c */ - u32 mcfg1; /* 0x7c */ - u32 mcfg; /* 0x80 */ - u32 ppcfg; /* 0x84 */ - u32 mstat; /* 0x88 */ - u32 lp2zqcfg; /* 0x8c */ - u8 res5[0x04]; /* 0x90 */ - u32 dtustat; /* 0x94 */ - u32 dtuna; /* 0x98 */ - u32 dtune; /* 0x9c */ - u32 dtuprd0; /* 0xa0 */ - u32 dtuprd1; /* 0xa4 */ - u32 dtuprd2; /* 0xa8 */ - u32 dtuprd3; /* 0xac */ - u32 dtuawdt; /* 0xb0 */ - u8 res6[0x0c]; /* 0xb4 */ - u32 togcnt1u; /* 0xc0 */ - u8 res7[0x08]; /* 0xc4 */ - u32 togcnt100n; /* 0xcc */ - u32 trefi; /* 0xd0 */ - u32 tmrd; /* 0xd4 */ - u32 trfc; /* 0xd8 */ - u32 trp; /* 0xdc */ - u32 trtw; /* 0xe0 */ - u32 tal; /* 0xe4 */ - u32 tcl; /* 0xe8 */ - u32 tcwl; /* 0xec */ - u32 tras; /* 0xf0 */ - u32 trc; /* 0xf4 */ - u32 trcd; /* 0xf8 */ - u32 trrd; /* 0xfc */ - u32 trtp; /* 0x100 */ - u32 twr; /* 0x104 */ - u32 twtr; /* 0x108 */ - u32 texsr; /* 0x10c */ - u32 txp; /* 0x110 */ - u32 txpdll; /* 0x114 */ - u32 tzqcs; /* 0x118 */ - u32 tzqcsi; /* 0x11c */ - u32 tdqs; /* 0x120 */ - u32 tcksre; /* 0x124 */ - u32 tcksrx; /* 0x128 */ - u32 tcke; /* 0x12c */ - u32 tmod; /* 0x130 */ - u32 trstl; /* 0x134 */ - u32 tzqcl; /* 0x138 */ - u32 tmrr; /* 0x13c */ - u32 tckesr; /* 0x140 */ - u32 tdpd; /* 0x144 */ - u8 res8[0xb8]; /* 0x148 */ - u32 dtuwactl; /* 0x200 */ - u32 dturactl; /* 0x204 */ - u32 dtucfg; /* 0x208 */ - u32 dtuectl; /* 0x20c */ - u32 dtuwd0; /* 0x210 */ - u32 dtuwd1; /* 0x214 */ - u32 dtuwd2; /* 0x218 */ - u32 dtuwd3; /* 0x21c */ - u32 dtuwdm; /* 0x220 */ - u32 dturd0; /* 0x224 */ - u32 dturd1; /* 0x228 */ - u32 dturd2; /* 0x22c */ - u32 dturd3; /* 0x230 */ - u32 dtulfsrwd; /* 0x234 */ - u32 dtulfsrrd; /* 0x238 */ - u32 dtueaf; /* 0x23c */ - u32 dfitctldly; /* 0x240 */ - u32 dfiodtcfg; /* 0x244 */ - u32 dfiodtcfg1; /* 0x248 */ - u32 dfiodtrmap; /* 0x24c */ - u32 dfitphywrd; /* 0x250 */ - u32 dfitphywrl; /* 0x254 */ - u8 res9[0x08]; /* 0x258 */ - u32 dfitrdden; /* 0x260 */ - u32 dfitphyrdl; /* 0x264 */ - u8 res10[0x08]; /* 0x268 */ - u32 dfitphyupdtype0; /* 0x270 */ - u32 dfitphyupdtype1; /* 0x274 */ - u32 dfitphyupdtype2; /* 0x278 */ - u32 dfitphyupdtype3; /* 0x27c */ - u32 dfitctrlupdmin; /* 0x280 */ - u32 dfitctrlupdmax; /* 0x284 */ - u32 dfitctrlupddly; /* 0x288 */ - u8 res11[4]; /* 0x28c */ - u32 dfiupdcfg; /* 0x290 */ - u32 dfitrefmski; /* 0x294 */ - u32 dfitcrlupdi; /* 0x298 */ - u8 res12[0x10]; /* 0x29c */ - u32 dfitrcfg0; /* 0x2ac */ - u32 dfitrstat0; /* 0x2b0 */ - u32 dfitrwrlvlen; /* 0x2b4 */ - u32 dfitrrdlvlen; /* 0x2b8 */ - u32 dfitrrdlvlgateen; /* 0x2bc */ - u8 res13[0x04]; /* 0x2c0 */ - u32 dfistcfg0; /* 0x2c4 */ - u32 dfistcfg1; /* 0x2c8 */ - u8 res14[0x04]; /* 0x2cc */ - u32 dfitdramclken; /* 0x2d0 */ - u32 dfitdramclkdis; /* 0x2d4 */ - u8 res15[0x18]; /* 0x2d8 */ - u32 dfilpcfg0; /* 0x2f0 */ -}; - -struct sunxi_mctl_phy_reg { - u8 res0[0x04]; /* 0x00 */ - u32 pir; /* 0x04 */ - u32 pgcr; /* 0x08 phy general configuration register */ - u32 pgsr; /* 0x0c */ - u32 dllgcr; /* 0x10 */ - u32 acdllcr; /* 0x14 */ - u32 ptr0; /* 0x18 */ - u32 ptr1; /* 0x1c */ - u32 ptr2; /* 0x20 */ - u32 aciocr; /* 0x24 */ - u32 dxccr; /* 0x28 DATX8 common configuration register */ - u32 dsgcr; /* 0x2c dram system general config register */ - u32 dcr; /* 0x30 */ - u32 dtpr0; /* 0x34 dram timing parameters register 0 */ - u32 dtpr1; /* 0x38 dram timing parameters register 1 */ - u32 dtpr2; /* 0x3c dram timing parameters register 2 */ - u32 mr0; /* 0x40 mode register 0 */ - u32 mr1; /* 0x44 mode register 1 */ - u32 mr2; /* 0x48 mode register 2 */ - u32 mr3; /* 0x4c mode register 3 */ - u32 odtcr; /* 0x50 */ - u32 dtar; /* 0x54 data training address register */ - u32 dtd0; /* 0x58 */ - u32 dtd1; /* 0x5c */ - u8 res1[0x60]; /* 0x60 */ - u32 dcuar; /* 0xc0 */ - u32 dcudr; /* 0xc4 */ - u32 dcurr; /* 0xc8 */ - u32 dculr; /* 0xcc */ - u32 dcugcr; /* 0xd0 */ - u32 dcutpr; /* 0xd4 */ - u32 dcusr0; /* 0xd8 */ - u32 dcusr1; /* 0xdc */ - u8 res2[0x20]; /* 0xe0 */ - u32 bistrr; /* 0x100 */ - u32 bistmskr0; /* 0x104 */ - u32 bistmskr1; /* 0x108 */ - u32 bistwcr; /* 0x10c */ - u32 bistlsr; /* 0x110 */ - u32 bistar0; /* 0x114 */ - u32 bistar1; /* 0x118 */ - u32 bistar2; /* 0x11c */ - u32 bistupdr; /* 0x120 */ - u32 bistgsr; /* 0x124 */ - u32 bistwer; /* 0x128 */ - u32 bistber0; /* 0x12c */ - u32 bistber1; /* 0x130 */ - u32 bistber2; /* 0x134 */ - u32 bistwcsr; /* 0x138 */ - u32 bistfwr0; /* 0x13c */ - u32 bistfwr1; /* 0x140 */ - u8 res3[0x3c]; /* 0x144 */ - u32 zq0cr0; /* 0x180 zq 0 control register 0 */ - u32 zq0cr1; /* 0x184 zq 0 control register 1 */ - u32 zq0sr0; /* 0x188 zq 0 status register 0 */ - u32 zq0sr1; /* 0x18c zq 0 status register 1 */ - u8 res4[0x30]; /* 0x190 */ - u32 dx0gcr; /* 0x1c0 */ - u32 dx0gsr0; /* 0x1c4 */ - u32 dx0gsr1; /* 0x1c8 */ - u32 dx0dllcr; /* 0x1cc */ - u32 dx0dqtr; /* 0x1d0 */ - u32 dx0dqstr; /* 0x1d4 */ - u8 res5[0x28]; /* 0x1d8 */ - u32 dx1gcr; /* 0x200 */ - u32 dx1gsr0; /* 0x204 */ - u32 dx1gsr1; /* 0x208 */ - u32 dx1dllcr; /* 0x20c */ - u32 dx1dqtr; /* 0x210 */ - u32 dx1dqstr; /* 0x214 */ - u8 res6[0x28]; /* 0x218 */ - u32 dx2gcr; /* 0x240 */ - u32 dx2gsr0; /* 0x244 */ - u32 dx2gsr1; /* 0x248 */ - u32 dx2dllcr; /* 0x24c */ - u32 dx2dqtr; /* 0x250 */ - u32 dx2dqstr; /* 0x254 */ - u8 res7[0x28]; /* 0x258 */ - u32 dx3gcr; /* 0x280 */ - u32 dx3gsr0; /* 0x284 */ - u32 dx3gsr1; /* 0x288 */ - u32 dx3dllcr; /* 0x28c */ - u32 dx3dqtr; /* 0x290 */ - u32 dx3dqstr; /* 0x294 */ -}; - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_RANK_MASK (3 << 0) -#define MCTL_CR_RANK(x) (((x) - 1) << 0) -#define MCTL_CR_BANK_MASK (3 << 2) -#define MCTL_CR_BANK(x) ((x) << 2) -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_BUSW_MASK (3 << 12) -#define MCTL_CR_BUSW16 (1 << 12) -#define MCTL_CR_BUSW32 (3 << 12) -#define MCTL_CR_SEQUENCE (1 << 15) -#define MCTL_CR_DDR3 (3 << 16) -#define MCTL_CR_CHANNEL_MASK (1 << 19) -#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) -#define MCTL_CR_UNKNOWN ((1 << 22) | (1 << 20)) -#define MCTL_CCR_CH0_CLK_EN (1 << 0) -#define MCTL_CCR_CH1_CLK_EN (1 << 1) -#define MCTL_CCR_MASTER_CLK_EN (1 << 2) - -/* - * DRAM control (sunxi_mctl_ctl_reg) register constants. - * Note that we use constant values for a lot of the timings, this is what - * the original boot0 bootloader does. - */ -#define MCTL_SCTL_CONFIG 1 -#define MCTL_SCTL_ACCESS 2 -#define MCTL_MCMD_NOP 0x88000000 -#define MCTL_MCMD_BUSY 0x80000000 -#define MCTL_MCFG_DDR3 0x70061 -#define MCTL_TREFI 78 -#define MCTL_TMRD 4 -#define MCTL_TRFC 115 -#define MCTL_TRP 9 -#define MCTL_TPREA 0 -#define MCTL_TRTW 2 -#define MCTL_TAL 0 -#define MCTL_TCL 9 -#define MCTL_TCWL 8 -#define MCTL_TRAS 18 -#define MCTL_TRC 23 -#define MCTL_TRCD 9 -#define MCTL_TRRD 4 -#define MCTL_TRTP 4 -#define MCTL_TWR 8 -#define MCTL_TWTR 4 -#define MCTL_TEXSR 512 -#define MCTL_TXP 4 -#define MCTL_TXPDLL 14 -#define MCTL_TZQCS 64 -#define MCTL_TZQCSI 0 -#define MCTL_TDQS 1 -#define MCTL_TCKSRE 5 -#define MCTL_TCKSRX 5 -#define MCTL_TCKE 4 -#define MCTL_TMOD 12 -#define MCTL_TRSTL 80 -#define MCTL_TZQCL 512 -#define MCTL_TMRR 2 -#define MCTL_TCKESR 5 -#define MCTL_TDPD 0 -#define MCTL_DFITPHYRDL 15 -#define MCTL_DFIUPDCFG_UPD (1 << 1) -#define MCTL_DFISTCFG0 5 - -/* - * DRAM phy (sunxi_mctl_phy_reg) register values / constants. - */ -#define MCTL_PIR_CLEAR_STATUS (1 << 28) -#define MCTL_PIR_STEP1 0xe9 -#define MCTL_PIR_STEP2 0x81 -#define MCTL_PGCR_RANK (1 << 19) -#define MCTL_PGCR 0x018c0202 -#define MCTL_PGSR_TRAIN_ERR_MASK (3 << 5) -/* constants for both acdllcr as well as dx#dllcr */ -#define MCTL_DLLCR_NRESET (1 << 30) -#define MCTL_DLLCR_DISABLE (1 << 31) -/* ptr constants these are or-ed together to get the final ptr# values */ -#define MCTL_TITMSRST 10 -#define MCTL_TDLLLOCK 2250 -#define MCTL_TDLLSRST 23 -#define MCTL_TDINIT0 217000 -#define MCTL_TDINIT1 160 -#define MCTL_TDINIT2 87000 -#define MCTL_TDINIT3 433 -/* end ptr constants */ -#define MCTL_ACIOCR_DISABLE ((3 << 18) | (1 << 8) | (1 << 3)) -#define MCTL_DXCCR_DISABLE ((1 << 3) | (1 << 2)) -#define MCTL_DXCCR 0x800 -#define MCTL_DSGCR_ENABLE (1 << 28) -#define MCTL_DSGCR 0xf200001b -#define MCTL_DCR_DDR3 0x0b -/* dtpr constants these are or-ed together to get the final dtpr# values */ -#define MCTL_TCCD 0 -#define MCTL_TDQSCKMAX 1 -#define MCTL_TDQSCK 1 -#define MCTL_TRTODT 0 -#define MCTL_TFAW 20 -#define MCTL_TAOND 0 -#define MCTL_TDLLK 512 -/* end dtpr constants */ -#define MCTL_MR0 0x1a50 -#define MCTL_MR1 0x4 -#define MCTL_MR2 ((MCTL_TCWL - 5) << 3) -#define MCTL_MR3 0x0 -#define MCTL_DX_GCR_EN (1 << 0) -#define MCTL_DX_GCR 0x880 -#define MCTL_DX_GSR0_RANK0_TRAIN_DONE (1 << 0) -#define MCTL_DX_GSR0_RANK1_TRAIN_DONE (1 << 1) -#define MCTL_DX_GSR0_RANK0_TRAIN_ERR (1 << 4) -#define MCTL_DX_GSR0_RANK1_TRAIN_ERR (1 << 5) - -#endif /* _SUNXI_DRAM_SUN6I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h deleted file mode 100644 index ca98597..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a23.h +++ /dev/null @@ -1,266 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * CPL <cplanxy@allwinnertech.com> - * Jerry Wang <wangflord@allwinnertech.com> - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DRAM_SUN8I_H -#define _SUNXI_DRAM_SUN8I_H - -struct dram_para { - u32 clock; - u32 type; - u32 zq; - u32 odt_en; - s32 odt_correction; - u32 para1; - u32 para2; - u32 mr0; - u32 mr1; - u32 mr2; - u32 mr3; - u32 tpr0; - u32 tpr1; - u32 tpr2; - u32 tpr3; - u32 tpr4; - u32 tpr5; - u32 tpr6; - u32 tpr7; - u32 tpr8; - u32 tpr9; - u32 tpr10; - u32 tpr11; - u32 tpr12; - u32 tpr13; -}; - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u8 res0[0x4]; /* 0x0c */ - u32 mcr0_0; /* 0x10 */ - u32 mcr1_0; /* 0x14 */ - u32 mcr0_1; /* 0x18 */ - u32 mcr1_1; /* 0x1c */ - u32 mcr0_2; /* 0x20 */ - u32 mcr1_2; /* 0x24 */ - u32 mcr0_3; /* 0x28 */ - u32 mcr1_3; /* 0x2c */ - u32 mcr0_4; /* 0x30 */ - u32 mcr1_4; /* 0x34 */ - u32 mcr0_5; /* 0x38 */ - u32 mcr1_5; /* 0x3c */ - u32 mcr0_6; /* 0x40 */ - u32 mcr1_6; /* 0x44 */ - u32 mcr0_7; /* 0x48 */ - u32 mcr1_7; /* 0x4c */ - u32 mcr0_8; /* 0x50 */ - u32 mcr1_8; /* 0x54 */ - u32 mcr0_9; /* 0x58 */ - u32 mcr1_9; /* 0x5c */ - u32 mcr0_10; /* 0x60 */ - u32 mcr1_10; /* 0x64 */ - u32 mcr0_11; /* 0x68 */ - u32 mcr1_11; /* 0x6c */ - u32 mcr0_12; /* 0x70 */ - u32 mcr1_12; /* 0x74 */ - u32 mcr0_13; /* 0x78 */ - u32 mcr1_13; /* 0x7c */ - u32 mcr0_14; /* 0x80 */ - u32 mcr1_14; /* 0x84 */ - u32 mcr0_15; /* 0x88 */ - u32 mcr1_15; /* 0x8c */ - u32 bwcr; /* 0x90 */ - u32 maer; /* 0x94 */ - u8 res1[0x4]; /* 0x98 */ - u32 mcgcr; /* 0x9c */ - u32 bwctr; /* 0xa0 */ - u8 res2[0x4]; /* 0xa4 */ - u32 swonr; /* 0xa8 */ - u32 swoffr; /* 0xac */ -}; - -struct sunxi_mctl_ctl_reg { - u32 mstr; /* 0x00 */ - u32 statr; /* 0x04 */ - u8 res0[0x08]; /* 0x08 */ - u32 mrctrl0; /* 0x10 */ - u32 mrctrl1; /* 0x14 */ - u32 mrstatr; /* 0x18 */ - u8 res1[0x04]; /* 0x1c */ - u32 derateen; /* 0x20 */ - u32 deratenint; /* 0x24 */ - u8 res2[0x08]; /* 0x28 */ - u32 pwrctl; /* 0x30 */ - u32 pwrtmg; /* 0x34 */ - u8 res3[0x18]; /* 0x38 */ - u32 rfshctl0; /* 0x50 */ - u32 rfshctl1; /* 0x54 */ - u8 res4[0x8]; /* 0x58 */ - u32 rfshctl3; /* 0x60 */ - u32 rfshtmg; /* 0x64 */ - u8 res6[0x68]; /* 0x68 */ - u32 init0; /* 0xd0 */ - u32 init1; /* 0xd4 */ - u32 init2; /* 0xd8 */ - u32 init3; /* 0xdc */ - u32 init4; /* 0xe0 */ - u32 init5; /* 0xe4 */ - u8 res7[0x0c]; /* 0xe8 */ - u32 rankctl; /* 0xf4 */ - u8 res8[0x08]; /* 0xf8 */ - u32 dramtmg0; /* 0x100 */ - u32 dramtmg1; /* 0x104 */ - u32 dramtmg2; /* 0x108 */ - u32 dramtmg3; /* 0x10c */ - u32 dramtmg4; /* 0x110 */ - u32 dramtmg5; /* 0x114 */ - u32 dramtmg6; /* 0x118 */ - u32 dramtmg7; /* 0x11c */ - u32 dramtmg8; /* 0x120 */ - u8 res9[0x5c]; /* 0x124 */ - u32 zqctl0; /* 0x180 */ - u32 zqctl1; /* 0x184 */ - u32 zqctl2; /* 0x188 */ - u32 zqstat; /* 0x18c */ - u32 pitmg0; /* 0x190 */ - u32 pitmg1; /* 0x194 */ - u32 plpcfg0; /* 0x198 */ - u8 res10[0x04]; /* 0x19c */ - u32 upd0; /* 0x1a0 */ - u32 upd1; /* 0x1a4 */ - u32 upd2; /* 0x1a8 */ - u32 upd3; /* 0x1ac */ - u32 pimisc; /* 0x1b0 */ - u8 res11[0x1c]; /* 0x1b4 */ - u32 trainctl0; /* 0x1d0 */ - u32 trainctl1; /* 0x1d4 */ - u32 trainctl2; /* 0x1d8 */ - u32 trainstat; /* 0x1dc */ - u8 res12[0x60]; /* 0x1e0 */ - u32 odtcfg; /* 0x240 */ - u32 odtmap; /* 0x244 */ - u8 res13[0x08]; /* 0x248 */ - u32 sched; /* 0x250 */ - u8 res14[0x04]; /* 0x254 */ - u32 perfshpr0; /* 0x258 */ - u32 perfshpr1; /* 0x25c */ - u32 perflpr0; /* 0x260 */ - u32 perflpr1; /* 0x264 */ - u32 perfwr0; /* 0x268 */ - u32 perfwr1; /* 0x26c */ -}; - -struct sunxi_mctl_phy_reg { - u8 res0[0x04]; /* 0x00 */ - u32 pir; /* 0x04 */ - u32 pgcr0; /* 0x08 phy general configuration register */ - u32 pgcr1; /* 0x0c phy general configuration register */ - u32 pgsr0; /* 0x10 */ - u32 pgsr1; /* 0x14 */ - u32 dllgcr; /* 0x18 */ - u32 ptr0; /* 0x1c */ - u32 ptr1; /* 0x20 */ - u32 ptr2; /* 0x24 */ - u32 ptr3; /* 0x28 */ - u32 ptr4; /* 0x2c */ - u32 acmdlr; /* 0x30 */ - u32 acbdlr; /* 0x34 */ - u32 aciocr; /* 0x38 */ - u32 dxccr; /* 0x3c DATX8 common configuration register */ - u32 dsgcr; /* 0x40 dram system general config register */ - u32 dcr; /* 0x44 */ - u32 dtpr0; /* 0x48 dram timing parameters register 0 */ - u32 dtpr1; /* 0x4c dram timing parameters register 1 */ - u32 dtpr2; /* 0x50 dram timing parameters register 2 */ - u32 mr0; /* 0x54 mode register 0 */ - u32 mr1; /* 0x58 mode register 1 */ - u32 mr2; /* 0x5c mode register 2 */ - u32 mr3; /* 0x60 mode register 3 */ - u32 odtcr; /* 0x64 */ - u32 dtcr; /* 0x68 */ - u32 dtar0; /* 0x6c data training address register 0 */ - u32 dtar1; /* 0x70 data training address register 1 */ - u32 dtar2; /* 0x74 data training address register 2 */ - u32 dtar3; /* 0x78 data training address register 3 */ - u32 dtdr0; /* 0x7c */ - u32 dtdr1; /* 0x80 */ - u32 dtedr0; /* 0x84 */ - u32 dtedr1; /* 0x88 */ - u32 pgcr2; /* 0x8c */ - u8 res1[0x70]; /* 0x90 */ - u32 bistrr; /* 0x100 */ - u32 bistwcr; /* 0x104 */ - u32 bistmskr0; /* 0x108 */ - u32 bistmskr1; /* 0x10c */ - u32 bistmskr2; /* 0x110 */ - u32 bistlsr; /* 0x114 */ - u32 bistar0; /* 0x118 */ - u32 bistar1; /* 0x11c */ - u32 bistar2; /* 0x120 */ - u32 bistupdr; /* 0x124 */ - u32 bistgsr; /* 0x128 */ - u32 bistwer; /* 0x12c */ - u32 bistber0; /* 0x130 */ - u32 bistber1; /* 0x134 */ - u32 bistber2; /* 0x138 */ - u32 bistber3; /* 0x13c */ - u32 bistwcsr; /* 0x140 */ - u32 bistfwr0; /* 0x144 */ - u32 bistfwr1; /* 0x148 */ - u32 bistfwr2; /* 0x14c */ - u8 res2[0x30]; /* 0x150 */ - u32 zqcr0; /* 0x180 zq control register 0 */ - u32 zqcr1; /* 0x184 zq control register 1 */ - u32 zqsr0; /* 0x188 zq status register 0 */ - u32 zqsr1; /* 0x18c zq status register 1 */ - u32 zqcr2; /* 0x190 zq control register 2 */ - u8 res3[0x2c]; /* 0x194 */ - u32 dx0gcr; /* 0x1c0 */ - u32 dx0gsr0; /* 0x1c4 */ - u32 dx0gsr1; /* 0x1c8 */ - u32 dx0bdlr0; /* 0x1cc */ - u32 dx0bdlr1; /* 0x1d0 */ - u32 dx0bdlr2; /* 0x1d4 */ - u32 dx0bdlr3; /* 0x1d8 */ - u32 dx0bdlr4; /* 0x1dc */ - u32 dx0lcdlr0; /* 0x1e0 */ - u32 dx0lcdlr1; /* 0x1e4 */ - u32 dx0lcdlr2; /* 0x1e8 */ - u32 dx0mdlr; /* 0x1ec */ - u32 dx0gtr; /* 0x1f0 */ - u32 dx0gsr2; /* 0x1f4 */ - u8 res4[0x08]; /* 0x1f8 */ - u32 dx1gcr; /* 0x200 */ - u32 dx1gsr0; /* 0x204 */ - u32 dx1gsr1; /* 0x208 */ - u32 dx1bdlr0; /* 0x20c */ - u32 dx1bdlr1; /* 0x210 */ - u32 dx1bdlr2; /* 0x214 */ - u32 dx1bdlr3; /* 0x218 */ - u32 dx1bdlr4; /* 0x21c */ - u32 dx1lcdlr0; /* 0x220 */ - u32 dx1lcdlr1; /* 0x224 */ - u32 dx1lcdlr2; /* 0x228 */ - u32 dx1mdlr; /* 0x22c */ - u32 dx1gtr; /* 0x230 */ - u32 dx1gsr2; /* 0x234 */ -}; - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((x) << 8) - -#endif /* _SUNXI_DRAM_SUN8I_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h deleted file mode 100644 index 49a6108..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a33.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang <wangflord@allwinnertech.com> - * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> - * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DRAM_SUN8I_A33_H -#define _SUNXI_DRAM_SUN8I_A33_H - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u8 res0[0x4]; /* 0x0c */ - u32 mcr0_0; /* 0x10 */ - u32 mcr1_0; /* 0x14 */ - u32 mcr0_1; /* 0x18 */ - u32 mcr1_1; /* 0x1c */ - u32 mcr0_2; /* 0x20 */ - u32 mcr1_2; /* 0x24 */ - u32 mcr0_3; /* 0x28 */ - u32 mcr1_3; /* 0x2c */ - u32 mcr0_4; /* 0x30 */ - u32 mcr1_4; /* 0x34 */ - u32 mcr0_5; /* 0x38 */ - u32 mcr1_5; /* 0x3c */ - u32 mcr0_6; /* 0x40 */ - u32 mcr1_6; /* 0x44 */ - u32 mcr0_7; /* 0x48 */ - u32 mcr1_7; /* 0x4c */ - u32 mcr0_8; /* 0x50 */ - u32 mcr1_8; /* 0x54 */ - u32 mcr0_9; /* 0x58 */ - u32 mcr1_9; /* 0x5c */ - u32 mcr0_10; /* 0x60 */ - u32 mcr1_10; /* 0x64 */ - u32 mcr0_11; /* 0x68 */ - u32 mcr1_11; /* 0x6c */ - u32 mcr0_12; /* 0x70 */ - u32 mcr1_12; /* 0x74 */ - u32 mcr0_13; /* 0x78 */ - u32 mcr1_13; /* 0x7c */ - u32 mcr0_14; /* 0x80 */ - u32 mcr1_14; /* 0x84 */ - u32 mcr0_15; /* 0x88 */ - u32 mcr1_15; /* 0x8c */ - u32 bwcr; /* 0x90 */ - u32 maer; /* 0x94 */ - u32 mapr; /* 0x98 */ - u32 mcgcr; /* 0x9c */ - u32 bwctr; /* 0xa0 */ - u8 res2[0x8]; /* 0xa4 */ - u32 swoffr; /* 0xac */ - u8 res3[0x10]; /* 0xb0 */ - u32 swonr; /* 0xc0 */ - u8 res4[0x3c]; /* 0xc4 */ - u32 mdfscr; /* 0x100 */ - u32 mdfsmer; /* 0x104 */ -}; - -struct sunxi_mctl_ctl_reg { - u32 pir; /* 0x00 */ - u32 pwrctl; /* 0x04 */ - u32 mrctrl0; /* 0x08 */ - u32 clken; /* 0x0c */ - u32 pgsr0; /* 0x10 */ - u32 pgsr1; /* 0x14 */ - u32 statr; /* 0x18 */ - u8 res1[0x14]; /* 0x1c */ - u32 mr0; /* 0x30 */ - u32 mr1; /* 0x34 */ - u32 mr2; /* 0x38 */ - u32 mr3; /* 0x3c */ - u32 pllgcr; /* 0x40 */ - u32 ptr0; /* 0x44 */ - u32 ptr1; /* 0x48 */ - u32 ptr2; /* 0x4c */ - u32 ptr3; /* 0x50 */ - u32 ptr4; /* 0x54 */ - u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ - u32 dramtmg1; /* 0x5c dram timing parameters register 1 */ - u32 dramtmg2; /* 0x60 dram timing parameters register 2 */ - u32 dramtmg3; /* 0x64 dram timing parameters register 3 */ - u32 dramtmg4; /* 0x68 dram timing parameters register 4 */ - u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ - u32 dramtmg6; /* 0x70 dram timing parameters register 6 */ - u32 dramtmg7; /* 0x74 dram timing parameters register 7 */ - u32 dramtmg8; /* 0x78 dram timing parameters register 8 */ - u32 odtcfg; /* 0x7c */ - u32 pitmg0; /* 0x80 */ - u32 pitmg1; /* 0x84 */ - u8 res2[0x4]; /* 0x88 */ - u32 rfshctl0; /* 0x8c */ - u32 rfshtmg; /* 0x90 */ - u32 rfshctl1; /* 0x94 */ - u32 pwrtmg; /* 0x98 */ - u8 res3[0x20]; /* 0x9c */ - u32 dqsgmr; /* 0xbc */ - u32 dtcr; /* 0xc0 */ - u32 dtar0; /* 0xc4 */ - u32 dtar1; /* 0xc8 */ - u32 dtar2; /* 0xcc */ - u32 dtar3; /* 0xd0 */ - u32 dtdr0; /* 0xd4 */ - u32 dtdr1; /* 0xd8 */ - u32 dtmr0; /* 0xdc */ - u32 dtmr1; /* 0xe0 */ - u32 dtbmr; /* 0xe4 */ - u32 catr0; /* 0xe8 */ - u32 catr1; /* 0xec */ - u32 dtedr0; /* 0xf0 */ - u32 dtedr1; /* 0xf4 */ - u8 res4[0x8]; /* 0xf8 */ - u32 pgcr0; /* 0x100 */ - u32 pgcr1; /* 0x104 */ - u32 pgcr2; /* 0x108 */ - u8 res5[0x4]; /* 0x10c */ - u32 iovcr0; /* 0x110 */ - u32 iovcr1; /* 0x114 */ - u32 dqsdr; /* 0x118 */ - u32 dxccr; /* 0x11c */ - u32 odtmap; /* 0x120 */ - u32 zqctl0; /* 0x124 */ - u32 zqctl1; /* 0x128 */ - u8 res6[0x14]; /* 0x12c */ - u32 zqcr0; /* 0x140 zq control register 0 */ - u32 zqcr1; /* 0x144 zq control register 1 */ - u32 zqcr2; /* 0x148 zq control register 2 */ - u32 zqsr0; /* 0x14c zq status register 0 */ - u32 zqsr1; /* 0x150 zq status register 1 */ - u8 res7[0x6c]; /* 0x154 */ - u32 sched; /* 0x1c0 */ - u32 perfhpr0; /* 0x1c4 */ - u32 perfhpr1; /* 0x1c8 */ - u32 perflpr0; /* 0x1cc */ - u32 perflpr1; /* 0x1d0 */ - u32 perfwr0; /* 0x1d4 */ - u32 perfwr1; /* 0x1d8 */ -}; - -#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x) -#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) -#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) -#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x) -#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x) - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_RANK_MASK (3 << 0) -#define MCTL_CR_RANK(x) (((x) - 1) << 0) -#define MCTL_CR_BANK_MASK (3 << 2) -#define MCTL_CR_BANK(x) ((x) << 2) -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_BUSW_MASK (7 << 12) -#define MCTL_CR_BUSW8 (0 << 12) -#define MCTL_CR_BUSW16 (1 << 12) -#define MCTL_CR_SEQUENCE (1 << 15) -#define MCTL_CR_DDR3 (3 << 16) -#define MCTL_CR_CHANNEL_MASK (1 << 19) -#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) -#define MCTL_CR_UNKNOWN (0x4 << 20) -#define MCTL_CR_CS1_CONTROL(x) ((x) << 24) - -/* DRAM control (sunxi_mctl_ctl_reg) register constants */ -#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ -#define MCTL_MR1 0x40 -#define MCTL_MR2 0x18 /* CWL=8 */ -#define MCTL_MR3 0x0 - -#endif /* _SUNXI_DRAM_SUN8I_A33_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h b/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h deleted file mode 100644 index d4634e5..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun8i_a83t.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang <wangflord@allwinnertech.com> - * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> - * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_DRAM_SUN8I_A83T_H -#define _SUNXI_DRAM_SUN8I_A83T_H - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u8 res0[0x4]; /* 0x0c */ - u32 mcr0_0; /* 0x10 */ - u32 mcr1_0; /* 0x14 */ - u32 mcr0_1; /* 0x18 */ - u32 mcr1_1; /* 0x1c */ - u32 mcr0_2; /* 0x20 */ - u32 mcr1_2; /* 0x24 */ - u32 mcr0_3; /* 0x28 */ - u32 mcr1_3; /* 0x2c */ - u32 mcr0_4; /* 0x30 */ - u32 mcr1_4; /* 0x34 */ - u32 mcr0_5; /* 0x38 */ - u32 mcr1_5; /* 0x3c */ - u32 mcr0_6; /* 0x40 */ - u32 mcr1_6; /* 0x44 */ - u32 mcr0_7; /* 0x48 */ - u32 mcr1_7; /* 0x4c */ - u32 mcr0_8; /* 0x50 */ - u32 mcr1_8; /* 0x54 */ - u32 mcr0_9; /* 0x58 */ - u32 mcr1_9; /* 0x5c */ - u32 mcr0_10; /* 0x60 */ - u32 mcr1_10; /* 0x64 */ - u32 mcr0_11; /* 0x68 */ - u32 mcr1_11; /* 0x6c */ - u32 mcr0_12; /* 0x70 */ - u32 mcr1_12; /* 0x74 */ - u32 mcr0_13; /* 0x78 */ - u32 mcr1_13; /* 0x7c */ - u32 mcr0_14; /* 0x80 */ - u32 mcr1_14; /* 0x84 */ - u32 mcr0_15; /* 0x88 */ - u32 mcr1_15; /* 0x8c */ - u32 bwcr; /* 0x90 */ - u32 maer; /* 0x94 */ - u32 mapr; /* 0x98 */ - u32 mcgcr; /* 0x9c */ - u32 bwctr; /* 0xa0 */ - u8 res2[0x8]; /* 0xa4 */ - u32 swoffr; /* 0xac */ - u8 res3[0x10]; /* 0xb0 */ - u32 swonr; /* 0xc0 */ - u8 res4[0x3c]; /* 0xc4 */ - u32 mdfscr; /* 0x100 */ - u32 mdfsmer; /* 0x104 */ -}; - -struct sunxi_mctl_ctl_reg { - u32 pir; /* 0x00 */ - u32 pwrctl; /* 0x04 */ - u32 mrctrl0; /* 0x08 */ - u32 clken; /* 0x0c */ - u32 pgsr0; /* 0x10 */ - u32 pgsr1; /* 0x14 */ - u32 statr; /* 0x18 */ - u8 res1[0x14]; /* 0x1c */ - u32 mr0; /* 0x30 */ - u32 mr1; /* 0x34 */ - u32 mr2; /* 0x38 */ - u32 mr3; /* 0x3c */ - u32 pllgcr; /* 0x40 */ - u32 ptr0; /* 0x44 */ - u32 ptr1; /* 0x48 */ - u32 ptr2; /* 0x4c */ - u32 ptr3; /* 0x50 */ - u32 ptr4; /* 0x54 */ - u32 dramtmg0; /* 0x58 dram timing parameters register 0 */ - u32 dramtmg1; /* 0x5c dram timing parameters register 1 */ - u32 dramtmg2; /* 0x60 dram timing parameters register 2 */ - u32 dramtmg3; /* 0x64 dram timing parameters register 3 */ - u32 dramtmg4; /* 0x68 dram timing parameters register 4 */ - u32 dramtmg5; /* 0x6c dram timing parameters register 5 */ - u32 dramtmg6; /* 0x70 dram timing parameters register 6 */ - u32 dramtmg7; /* 0x74 dram timing parameters register 7 */ - u32 dramtmg8; /* 0x78 dram timing parameters register 8 */ - u32 odtcfg; /* 0x7c */ - u32 pitmg0; /* 0x80 */ - u32 pitmg1; /* 0x84 */ - u8 res2[0x4]; /* 0x88 */ - u32 rfshctl0; /* 0x8c */ - u32 rfshtmg; /* 0x90 */ - u32 rfshctl1; /* 0x94 */ - u32 pwrtmg; /* 0x98 */ - u8 res3[0x20]; /* 0x9c */ - u32 dqsgmr; /* 0xbc */ - u32 dtcr; /* 0xc0 */ - u32 dtar0; /* 0xc4 */ - u32 dtar1; /* 0xc8 */ - u32 dtar2; /* 0xcc */ - u32 dtar3; /* 0xd0 */ - u32 dtdr0; /* 0xd4 */ - u32 dtdr1; /* 0xd8 */ - u32 dtmr0; /* 0xdc */ - u32 dtmr1; /* 0xe0 */ - u32 dtbmr; /* 0xe4 */ - u32 catr0; /* 0xe8 */ - u32 catr1; /* 0xec */ - u32 dtedr0; /* 0xf0 */ - u32 dtedr1; /* 0xf4 */ - u8 res4[0x8]; /* 0xf8 */ - u32 pgcr0; /* 0x100 */ - u32 pgcr1; /* 0x104 */ - u32 pgcr2; /* 0x108 */ - u32 pgcr3; /* 0x10c */ - u32 iovcr0; /* 0x110 */ - u32 iovcr1; /* 0x114 */ - u32 dqsdr; /* 0x118 */ - u32 dxccr; /* 0x11c */ - u32 odtmap; /* 0x120 */ - u32 zqctl0; /* 0x124 */ - u32 zqctl1; /* 0x128 */ - u8 res6[0x14]; /* 0x12c */ - u32 zqncr; /* 0x140 zq control register 0 */ - u32 zqnpr; /* 0x144 zq control register 1 */ - u32 zqndr; /* 0x148 zq control register 2 */ - u32 zqnsr; /* 0x14c zq status register 0 */ - u32 res7; /* 0x150 zq status register 1 */ - u8 res8[0x6c]; /* 0x154 */ - u32 sched; /* 0x1c0 */ - u32 perfhpr0; /* 0x1c4 */ - u32 perfhpr1; /* 0x1c8 */ - u32 perflpr0; /* 0x1cc */ - u32 perflpr1; /* 0x1d0 */ - u32 perfwr0; /* 0x1d4 */ - u32 perfwr1; /* 0x1d8 */ -}; - - -#define ZQnPR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000144 + 0x10 * x) -#define ZQnDR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000148 + 0x10 * x) -#define ZQnSR(x) (SUNXI_DRAM_CTL0_BASE + 0x0000014c + 0x10 * x) - -#define DXnGTR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000340 + 0x80 * x) -#define DXnGCR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000344 + 0x80 * x) -#define DXnGSR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000348 + 0x80 * x) -#define DXnGSR1(x) (SUNXI_DRAM_CTL0_BASE + 0x0000034c + 0x80 * x) -#define DXnGSR2(x) (SUNXI_DRAM_CTL0_BASE + 0x00000350 + 0x80 * x) - -#define CAIOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000210 + 0x4 * (x)) -#define DXnMDLR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000300 + 0x80 * x) -#define DXMDLR0 (SUNXI_DRAM_CTL0_BASE + 0x00000300) -#define DXnLCDLR0(x) (SUNXI_DRAM_CTL0_BASE + 0x00000304 + 0x80 * x) -#define DXnLCDLR1(x) (SUNXI_DRAM_CTL0_BASE + 0x00000308 + 0x80 * x) -#define DXnLCDLR2(x) (SUNXI_DRAM_CTL0_BASE + 0x0000030c + 0x80 * x) -#define DATX0IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000310 + 0x4 * x) -#define DATX1IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000390 + 0x4 * x) -#define DATX2IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000410 + 0x4 * x) -#define DATX3IOCR(x) (SUNXI_DRAM_CTL0_BASE + 0x00000490 + 0x4 * x) -#define MX_UPD0 (SUNXI_DRAM_CTL0_BASE + 0x00000880) -#define MX_UPD2 (SUNXI_DRAM_CTL0_BASE + 0x00000888) - -#define MCTL_PROTECT (SUNXI_DRAM_COM_BASE + 0x800) -#define MCTL_MASTER_CFG0(x) (SUNXI_DRAM_COM_BASE + 0x10 + 0x8 * x) -#define MCTL_MASTER_CFG1(x) (SUNXI_DRAM_COM_BASE + 0x14 + 0x8 * x) - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_RANK_MASK (3 << 0) -#define MCTL_CR_RANK(x) (((x) - 1) << 0) -#define MCTL_CR_BANK_MASK (3 << 2) -#define MCTL_CR_BANK(x) ((x) << 2) -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_BUSW_MASK (7 << 12) -#define MCTL_CR_BUSW8 (0 << 12) -#define MCTL_CR_BUSW16 (1 << 12) -#define MCTL_CR_SEQUENCE (1 << 15) -#define MCTL_CR_DRAM_TYPE(x) ((x) << 16) -#define MCTL_CR_CHANNEL_MASK (1 << 19) -#define MCTL_CR_CHANNEL(x) (((x) - 1) << 19) -#define MCTL_CR_UNKNOWN (0x4 << 20) -#define MCTL_CR_CS1_CONTROL(x) ((x) << 24) - -/* DRAM control (sunxi_mctl_ctl_reg) register constants */ -#define MCTL_MR0 0x1c70 /* CL=11, WR=12 */ -#define MCTL_MR1 0x40 -#define MCTL_MR2 0x18 /* CWL=8 */ -#define MCTL_MR3 0x0 - -#define MCTL_LPDDR3_MR0 0x0 -#define MCTL_LPDDR3_MR1 0xc3 /* twr=8, bl=8 */ -#define MCTL_LPDDR3_MR2 0xa /* RL=12, CWL=6 */ -#define MCTL_LPDDR3_MR3 0x0 - -#define DRAM_TYPE_DDR3 3 -#define DRAM_TYPE_LPDDR3 7 -#endif /* _SUNXI_DRAM_SUN8I_A83T_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h b/arch/arm/include/asm/arch-sunxi/dram_sun9i.h deleted file mode 100644 index 603850b..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sun9i.h +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sun8i platform dram controller register and constant defines - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang <wangflord@allwinnertech.com> - * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH - * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> - */ - -#ifndef _SUNXI_DRAM_SUN9I_H -#define _SUNXI_DRAM_SUN9I_H - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 */ - u32 ccr; /* 0x04 controller configuration register */ - u32 dbgcr; /* 0x08 */ - u32 dbgcr1; /* 0x0c */ - u32 rmcr; /* 0x10 */ - u8 res1[0x1c]; /* 0x14 */ - u32 mmcr; /* 0x30 */ - u8 res2[0x3c]; /* 0x34 */ - u32 mbagcr; /* 0x70 */ - u32 mbacr; /* 0x74 */ - u8 res3[0x10]; /* 0x78 */ - u32 maer; /* 0x88 */ - u8 res4[0x74]; /* 0x8c */ - u32 mdfscr; /* 0x100 */ - u32 mdfsmer; /* 0x104 */ - u32 mdfsmrmr; /* 0x108 */ - u32 mdfstr[4]; /* 0x10c */ - u32 mdfsgcr; /* 0x11c */ - u8 res5[0x1c]; /* 0x120 */ - u32 mdfsivr; /* 0x13c */ - u8 res6[0xc]; /* 0x140 */ - u32 mdfstcr; /* 0x14c */ -}; - - -struct sunxi_mctl_ctl_reg { - u32 mstr; /* 0x00 master register */ - u32 stat; /* 0x04 operating mode status register */ - u8 res1[0x8]; /* 0x08 */ - u32 mrctrl[2]; /* 0x10 mode register read/write control reg */ - u32 mstat; /* 0x18 mode register read/write status reg */ - u8 res2[0x4]; /* 0x1c */ - u32 derateen; /* 0x20 temperature derate enable register */ - u32 derateint; /* 0x24 temperature derate interval register */ - u8 res3[0x8]; /* 0x28 */ - u32 pwrctl; /* 0x30 low power control register */ - u32 pwrtmg; /* 0x34 low power timing register */ - u8 res4[0x18]; /* 0x38 */ - u32 rfshctl0; /* 0x50 refresh control register 0 */ - u32 rfshctl1; /* 0x54 refresh control register 1 */ - u8 res5[0x8]; /* 0x58 */ - u32 rfshctl3; /* 0x60 refresh control register 3 */ - u32 rfshtmg; /* 0x64 refresh timing register */ - u8 res6[0x68]; /* 0x68 */ - u32 init[6]; /* 0xd0 SDRAM initialisation register */ - u8 res7[0xc]; /* 0xe8 */ - u32 rankctl; /* 0xf4 rank control register */ - u8 res8[0x8]; /* 0xf8 */ - u32 dramtmg[9]; /* 0x100 DRAM timing register */ - u8 res9[0x5c]; /* 0x124 */ - u32 zqctrl[3]; /* 0x180 ZQ control register */ - u32 zqstat; /* 0x18c ZQ status register */ - u32 dfitmg[2]; /* 0x190 DFI timing register */ - u32 dfilpcfg; /* 0x198 DFI low power configuration register */ - u8 res10[0x4]; /* 0x19c */ - u32 dfiupd[4]; /* 0x1a0 DFI update register */ - u32 dfimisc; /* 0x1b0 DFI miscellaneous control register */ - u8 res11[0x1c]; /* 0x1b4 */ - u32 trainctl[3]; /* 0x1d0 */ - u32 trainstat; /* 0x1dc */ - u8 res12[0x20]; /* 0x1e0 */ - u32 addrmap[7]; /* 0x200 address map register */ - u8 res13[0x24]; /* 0x21c */ - u32 odtcfg; /* 0x240 ODT configuration register */ - u32 odtmap; /* 0x244 ODT/rank map register */ - u8 res14[0x8]; /* 0x248 */ - u32 sched; /* 0x250 scheduler control register */ - u8 res15[0x4]; /* 0x254 */ - u32 perfhpr0; /* 0x258 high priority read CAM register 0 */ - u32 perfhpr1; /* 0x25c high priority read CAM register 1 */ - u32 perflpr0; /* 0x260 low priority read CAM register 0 */ - u32 perflpr1; /* 0x264 low priority read CAM register 1 */ - u32 perfwr0; /* 0x268 write CAM register 0 */ - u32 perfwr1; /* 0x26c write CAM register 1 */ -}; - - -struct sunxi_mctl_phy_reg { - u8 res0[0x04]; /* 0x00 revision id ??? */ - u32 pir; /* 0x04 PHY initialisation register */ - u32 pgcr[4]; /* 0x08 PHY general configuration register */ - u32 pgsr[2]; /* 0x18 PHY general status register */ - u32 pllcr; /* 0x20 PLL control register */ - u32 ptr[5]; /* 0x24 PHY timing register */ - u32 acmdlr; /* 0x38 AC master delay line register */ - u32 aclcdlr; /* 0x3c AC local calibrated delay line reg */ - u32 acbdlr[10]; /* 0x40 AC bit delay line register */ - u32 aciocr[6]; /* 0x68 AC IO configuration register */ - u32 dxccr; /* 0x80 DATX8 common configuration register */ - u32 dsgcr; /* 0x84 DRAM system general config register */ - u32 dcr; /* 0x88 DRAM configuration register */ - u32 dtpr[4]; /* 0x8c DRAM timing parameters register */ - u32 mr0; /* 0x9c mode register 0 */ - u32 mr1; /* 0xa0 mode register 1 */ - u32 mr2; /* 0xa4 mode register 2 */ - u32 mr3; /* 0xa8 mode register 3 */ - u32 odtcr; /* 0xac ODT configuration register */ - u32 dtcr; /* 0xb0 data training configuration register */ - u32 dtar[4]; /* 0xb4 data training address register */ - u32 dtdr[2]; /* 0xc4 data training data register */ - u32 dtedr[2]; /* 0xcc data training eye data register */ - u32 rdimmgcr[2]; /* 0xd4 RDIMM general configuration register */ - u32 rdimmcr[2]; /* 0xdc RDIMM control register */ - u32 gpr[2]; /* 0xe4 general purpose register */ - u32 catr[2]; /* 0xec CA training register */ - u32 dqdsr; /* 0xf4 DQS drift register */ - u8 res1[0xc8]; /* 0xf8 */ - u32 bistrr; /* 0x1c0 BIST run register */ - u32 bistwcr; /* 0x1c4 BIST word count register */ - u32 bistmskr[3]; /* 0x1c8 BIST mask register */ - u32 bistlsr; /* 0x1d4 BIST LFSR seed register */ - u32 bistar[3]; /* 0x1d8 BIST address register */ - u32 bistupdr; /* 0x1e4 BIST user pattern data register */ - u32 bistgsr; /* 0x1e8 BIST general status register */ - u32 bistwer; /* 0x1dc BIST word error register */ - u32 bistber[4]; /* 0x1f0 BIST bit error register */ - u32 bistwcsr; /* 0x200 BIST word count status register */ - u32 bistfwr[3]; /* 0x204 BIST fail word register */ - u8 res2[0x28]; /* 0x210 */ - u32 iovcr[2]; /* 0x238 IO VREF control register */ - struct ddrphy_zq { - u32 cr; /* impedance control register */ - u32 pr; /* impedance control data register */ - u32 dr; /* impedance control data register */ - u32 sr; /* impedance control status register */ - } zq[4]; /* 0x240, 0x250, 0x260, 0x270 */ - struct ddrphy_dx { - u32 gcr[4]; /* DATX8 general configuration register */ - u32 gsr[3]; /* DATX8 general status register */ - u32 bdlr[7]; /* DATX8 bit delay line register */ - u32 lcdlr[3]; /* DATX8 local calibrated delay line reg */ - u32 mdlr; /* DATX8 master delay line register */ - u32 gtr; /* DATX8 general timing register */ - u8 res[0x34]; - } dx[4]; /* 0x280, 0x300, 0x380, 0x400 */ -}; - -/* - * DRAM common (sunxi_mctl_com_reg) register constants. - */ -#define MCTL_CR_RANK_MASK (3 << 0) -#define MCTL_CR_RANK(x) (((x) - 1) << 0) -#define MCTL_CR_BANK_MASK (3 << 2) -#define MCTL_CR_BANK(x) ((x) << 2) -#define MCTL_CR_ROW_MASK (0xf << 4) -#define MCTL_CR_ROW(x) (((x) - 1) << 4) -#define MCTL_CR_PAGE_SIZE_MASK (0xf << 8) -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_BUSW_MASK (3 << 12) -#define MCTL_CR_BUSW16 (1 << 12) -#define MCTL_CR_BUSW32 (3 << 12) -#define MCTL_CR_DRAMTYPE_MASK (7 << 16) -#define MCTL_CR_DRAMTYPE_DDR2 (2 << 16) -#define MCTL_CR_DRAMTYPE_DDR3 (3 << 16) -#define MCTL_CR_DRAMTYPE_LPDDR2 (6 << 16) - -#define MCTL_CR_CHANNEL_MASK ((1 << 22) | (1 << 20) | (1 << 19)) -#define MCTL_CR_CHANNEL_SINGLE (1 << 22) -#define MCTL_CR_CHANNEL_DUAL ((1 << 22) | (1 << 20) | (1 << 19)) - -#define MCTL_CCR_CH0_CLK_EN (1 << 15) -#define MCTL_CCR_CH1_CLK_EN (1 << 31) - -/* - * post_cke_x1024 [bits 16..25]: Cycles to wait after driving CKE high - * to start the SDRAM initialization sequence (in 1024s of cycles). - */ -#define MCTL_INIT0_POST_CKE_x1024(n) ((n & 0x0fff) << 16) -/* - * pre_cke_x1024 [bits 0..11] Cycles to wait after reset before driving - * CKE high to start the SDRAM initialization (in 1024s of cycles) - */ -#define MCTL_INIT0_PRE_CKE_x1024(n) ((n & 0x0fff) << 0) -#define MCTL_INIT1_DRAM_RSTN_x1024(n) ((n & 0xff) << 16) -#define MCTL_INIT1_FINAL_WAIT_x32(n) ((n & 0x3f) << 8) -#define MCTL_INIT1_PRE_OCD_x32(n) ((n & 0x0f) << 0) -#define MCTL_INIT2_IDLE_AFTER_RESET_x32(n) ((n & 0xff) << 8) -#define MCTL_INIT2_MIN_STABLE_CLOCK_x1(n) ((n & 0x0f) << 0) -#define MCTL_INIT3_MR(n) ((n & 0xffff) << 16) -#define MCTL_INIT3_EMR(n) ((n & 0xffff) << 0) -#define MCTL_INIT4_EMR2(n) ((n & 0xffff) << 16) -#define MCTL_INIT4_EMR3(n) ((n & 0xffff) << 0) -#define MCTL_INIT5_DEV_ZQINIT_x32(n) ((n & 0x00ff) << 16) -#define MCTL_INIT5_MAX_AUTO_INIT_x1024(n) ((n & 0x03ff) << 0); - -#define MCTL_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) -#define MCTL_DFIUPD0_DIS_AUTO_CTRLUPD (1 << 31) - -#define MCTL_MSTR_DEVICETYPE_DDR3 1 -#define MCTL_MSTR_DEVICETYPE_LPDDR2 4 -#define MCTL_MSTR_DEVICETYPE_LPDDR3 8 -#define MCTL_MSTR_DEVICETYPE(type) \ - ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_DEVICETYPE_DDR3 : \ - ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_DEVICETYPE_LPDDR2 : \ - MCTL_MSTR_DEVICETYPE_LPDDR3)) -#define MCTL_MSTR_BURSTLENGTH4 (2 << 16) -#define MCTL_MSTR_BURSTLENGTH8 (4 << 16) -#define MCTL_MSTR_BURSTLENGTH16 (8 << 16) -#define MCTL_MSTR_BURSTLENGTH(type) \ - ((type == DRAM_TYPE_DDR3) ? MCTL_MSTR_BURSTLENGTH8 : \ - ((type == DRAM_TYPE_LPDDR2) ? MCTL_MSTR_BURSTLENGTH4 : \ - MCTL_MSTR_BURSTLENGTH8)) -#define MCTL_MSTR_ACTIVERANKS(x) (((x == 2) ? 3 : 1) << 24) -#define MCTL_MSTR_BUSWIDTH8 (2 << 12) -#define MCTL_MSTR_BUSWIDTH16 (1 << 12) -#define MCTL_MSTR_BUSWIDTH32 (0 << 12) -#define MCTL_MSTR_2TMODE (1 << 10) - -#define MCTL_RFSHCTL3_DIS_AUTO_REFRESH (1 << 0) - -#define MCTL_ZQCTRL0_TZQCS(x) (x << 0) -#define MCTL_ZQCTRL0_TZQCL(x) (x << 16) -#define MCTL_ZQCTRL0_ZQCL_DIS (1 << 30) -#define MCTL_ZQCTRL0_ZQCS_DIS (1 << 31) -#define MCTL_ZQCTRL1_TZQRESET(x) (x << 20) -#define MCTL_ZQCTRL1_TZQSI_x1024(x) (x << 0) -#define MCTL_ZQCTRL2_TZRESET_TRIGGER (1 << 0) - -#define MCTL_PHY_DCR_BYTEMASK (1 << 10) -#define MCTL_PHY_DCR_2TMODE (1 << 28) -#define MCTL_PHY_DCR_DDR8BNK (1 << 3) -#define MCTL_PHY_DRAMMODE_DDR3 3 -#define MCTL_PHY_DRAMMODE_LPDDR2 0 -#define MCTL_PHY_DRAMMODE_LPDDR3 1 - -#define MCTL_DTCR_DEFAULT 0x00003007 -#define MCTL_DTCR_RANKEN(n) (((n == 2) ? 3 : 1) << 24) - -#define MCTL_PGCR1_ZCKSEL_MASK (3 << 23) -#define MCTL_PGCR1_IODDRM_MASK (3 << 7) -#define MCTL_PGCR1_IODDRM_DDR3 (1 << 7) -#define MCTL_PGCR1_IODDRM_DDR3L (2 << 7) -#define MCTL_PGCR1_INHVT_EN (1 << 26) - -#define MCTL_PLLGCR_PLL_BYPASS (1 << 31) -#define MCTL_PLLGCR_PLL_POWERDOWN (1 << 29) - -#define MCTL_PIR_PLL_BYPASS (1 << 17) -#define MCTL_PIR_MASK (~(1 << 17)) -#define MCTL_PIR_INIT (1 << 0) - -#define MCTL_PGSR0_ERRORS (0x1ff << 20) - -/* Constants for assembling MR0 */ -#define DDR3_MR0_PPD_FAST_EXIT (1 << 12) -#define DDR3_MR0_WR(n) \ - ((n <= 8) ? ((n - 4) << 9) : (((n >> 1) & 0x7) << 9)) -#define DDR3_MR0_CL(n) \ - ((((n - 4) & 0x7) << 4) | (((n - 4) & 0x8) >> 2)) -#define DDR3_MR0_BL8 (0 << 0) - -#define DDR3_MR1_RTT120OHM ((0 << 9) | (1 << 6) | (0 << 2)) - -#define DDR3_MR2_TWL(n) \ - (((n - 5) & 0x7) << 3) - -#define MCTL_NS2CYCLES_CEIL(ns) ((ns * (CONFIG_DRAM_CLK / 2) + 999) / 1000) - -#define DRAM_TYPE_DDR3 3 -#define DRAM_TYPE_LPDDR2 6 -#define DRAM_TYPE_LPDDR3 7 - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h deleted file mode 100644 index a5a7ebd..0000000 --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h +++ /dev/null @@ -1,238 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * sun8i H3 platform dram controller register and constant defines - * - * (C) Copyright 2007-2015 Allwinner Technology Co. - * Jerry Wang <wangflord@allwinnertech.com> - * (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com> - * (C) Copyright 2014-2015 Hans de Goede <hdegoede@redhat.com> - * (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com> - */ - -#ifndef _SUNXI_DRAM_SUN8I_H3_H -#define _SUNXI_DRAM_SUN8I_H3_H - -#include <linux/bitops.h> - -struct sunxi_mctl_com_reg { - u32 cr; /* 0x00 control register */ - u32 cr_r1; /* 0x04 rank 1 control register (R40 only) */ - u8 res0[0x4]; /* 0x08 */ - u32 tmr; /* 0x0c (unused on H3) */ - u32 mcr[16][2]; /* 0x10 */ - u32 bwcr; /* 0x90 bandwidth control register */ - u32 maer; /* 0x94 master enable register */ - u32 mapr; /* 0x98 master priority register */ - u32 mcgcr; /* 0x9c */ - u32 cpu_bwcr; /* 0xa0 */ - u32 gpu_bwcr; /* 0xa4 */ - u32 ve_bwcr; /* 0xa8 */ - u32 disp_bwcr; /* 0xac */ - u32 other_bwcr; /* 0xb0 */ - u32 total_bwcr; /* 0xb4 */ - u8 res1[0x8]; /* 0xb8 */ - u32 swonr; /* 0xc0 */ - u32 swoffr; /* 0xc4 */ - u8 res2[0x8]; /* 0xc8 */ - u32 cccr; /* 0xd0 */ - u8 res3[0x54]; /* 0xd4 */ - u32 mdfs_bwlr[3]; /* 0x128 (unused on H3) */ - u8 res4[0x6cc]; /* 0x134 */ - u32 protect; /* 0x800 */ -}; - -#define MCTL_CR_BL8 (0x4 << 20) - -#define MCTL_CR_1T (0x1 << 19) -#define MCTL_CR_2T (0x0 << 19) - -#define MCTL_CR_LPDDR3 (0x7 << 16) -#define MCTL_CR_LPDDR2 (0x6 << 16) -#define MCTL_CR_DDR3 (0x3 << 16) -#define MCTL_CR_DDR2 (0x2 << 16) - -#define MCTL_CR_SEQUENTIAL (0x1 << 15) -#define MCTL_CR_INTERLEAVED (0x0 << 15) - -#define MCTL_CR_FULL_WIDTH (0x1 << 12) -#define MCTL_CR_HALF_WIDTH (0x0 << 12) -#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12) - -#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8) -#define MCTL_CR_ROW_BITS(x) (((x) - 1) << 4) -#define MCTL_CR_EIGHT_BANKS (0x1 << 2) -#define MCTL_CR_FOUR_BANKS (0x0 << 2) -#define MCTL_CR_DUAL_RANK (0x1 << 0) -#define MCTL_CR_SINGLE_RANK (0x0 << 0) - -/* - * CR_R1 is a register found in the R40's DRAM controller. It sets various - * parameters for rank 1. Bits [11:0] have the same meaning as the bits in - * MCTL_CR, but they apply to rank 1 only. This implies we can have - * different chips for rank 1 than rank 0. - * - * As address line A15 and CS1 chip select for rank 1 are muxed on the same - * pin, if single rank is used, A15 must be muxed in. - */ -#define MCTL_CR_R1_MUX_A15 (0x1 << 21) - -#define PROTECT_MAGIC (0x94be6fa3) - -struct sunxi_mctl_ctl_reg { - u32 pir; /* 0x00 PHY initialization register */ - u32 pwrctl; /* 0x04 */ - u32 mrctrl; /* 0x08 */ - u32 clken; /* 0x0c */ - u32 pgsr[2]; /* 0x10 PHY general status registers */ - u32 statr; /* 0x18 */ - u8 res1[0x10]; /* 0x1c */ - u32 lp3mr11; /* 0x2c */ - u32 mr[4]; /* 0x30 mode registers */ - u32 pllgcr; /* 0x40 */ - u32 ptr[5]; /* 0x44 PHY timing registers */ - u32 dramtmg[9]; /* 0x58 DRAM timing registers */ - u32 odtcfg; /* 0x7c */ - u32 pitmg[2]; /* 0x80 PHY interface timing registers */ - u8 res2[0x4]; /* 0x88 */ - u32 rfshctl0; /* 0x8c */ - u32 rfshtmg; /* 0x90 refresh timing */ - u32 rfshctl1; /* 0x94 */ - u32 pwrtmg; /* 0x98 */ - u8 res3[0x1c]; /* 0x9c */ - u32 vtfcr; /* 0xb8 (unused on H3) */ - u32 dqsgmr; /* 0xbc */ - u32 dtcr; /* 0xc0 */ - u32 dtar[4]; /* 0xc4 */ - u32 dtdr[2]; /* 0xd4 */ - u32 dtmr[2]; /* 0xdc */ - u32 dtbmr; /* 0xe4 */ - u32 catr[2]; /* 0xe8 */ - u32 dtedr[2]; /* 0xf0 */ - u8 res4[0x8]; /* 0xf8 */ - u32 pgcr[4]; /* 0x100 PHY general configuration registers */ - u32 iovcr[2]; /* 0x110 */ - u32 dqsdr; /* 0x118 */ - u32 dxccr; /* 0x11c */ - u32 odtmap; /* 0x120 */ - u32 zqctl[2]; /* 0x124 */ - u8 res6[0x14]; /* 0x12c */ - u32 zqcr; /* 0x140 ZQ control register */ - u32 zqsr; /* 0x144 ZQ status register */ - u32 zqdr[3]; /* 0x148 ZQ data registers */ - u8 res7[0x6c]; /* 0x154 */ - u32 sched; /* 0x1c0 */ - u32 perfhpr[2]; /* 0x1c4 */ - u32 perflpr[2]; /* 0x1cc */ - u32 perfwr[2]; /* 0x1d4 */ - u8 res8[0x24]; /* 0x1dc */ - u32 acmdlr; /* 0x200 AC master delay line register */ - u32 aclcdlr; /* 0x204 AC local calibrated delay line register */ - u32 aciocr; /* 0x208 AC I/O configuration register */ - u8 res9[0x4]; /* 0x20c */ - u32 acbdlr[31]; /* 0x210 AC bit delay line registers */ - u8 res10[0x74]; /* 0x28c */ - struct { /* 0x300 DATX8 modules*/ - u32 mdlr; /* 0x00 master delay line register */ - u32 lcdlr[3]; /* 0x04 local calibrated delay line registers */ - u32 bdlr[11]; /* 0x10 bit delay line registers */ - u32 sdlr; /* 0x3c output enable bit delay registers */ - u32 gtr; /* 0x40 general timing register */ - u32 gcr; /* 0x44 general configuration register */ - u32 gsr[3]; /* 0x48 general status registers */ - u8 res0[0x2c]; /* 0x54 */ - } dx[4]; - u8 res11[0x388]; /* 0x500 */ - u32 upd2; /* 0x888 */ -}; - -#define PTR3_TDINIT1(x) ((x) << 20) -#define PTR3_TDINIT0(x) ((x) << 0) - -#define PTR4_TDINIT3(x) ((x) << 20) -#define PTR4_TDINIT2(x) ((x) << 0) - -#define DRAMTMG0_TWTP(x) ((x) << 24) -#define DRAMTMG0_TFAW(x) ((x) << 16) -#define DRAMTMG0_TRAS_MAX(x) ((x) << 8) -#define DRAMTMG0_TRAS(x) ((x) << 0) - -#define DRAMTMG1_TXP(x) ((x) << 16) -#define DRAMTMG1_TRTP(x) ((x) << 8) -#define DRAMTMG1_TRC(x) ((x) << 0) - -#define DRAMTMG2_TCWL(x) ((x) << 24) -#define DRAMTMG2_TCL(x) ((x) << 16) -#define DRAMTMG2_TRD2WR(x) ((x) << 8) -#define DRAMTMG2_TWR2RD(x) ((x) << 0) - -#define DRAMTMG3_TMRW(x) ((x) << 16) -#define DRAMTMG3_TMRD(x) ((x) << 12) -#define DRAMTMG3_TMOD(x) ((x) << 0) - -#define DRAMTMG4_TRCD(x) ((x) << 24) -#define DRAMTMG4_TCCD(x) ((x) << 16) -#define DRAMTMG4_TRRD(x) ((x) << 8) -#define DRAMTMG4_TRP(x) ((x) << 0) - -#define DRAMTMG5_TCKSRX(x) ((x) << 24) -#define DRAMTMG5_TCKSRE(x) ((x) << 16) -#define DRAMTMG5_TCKESR(x) ((x) << 8) -#define DRAMTMG5_TCKE(x) ((x) << 0) - -#define RFSHTMG_TREFI(x) ((x) << 16) -#define RFSHTMG_TRFC(x) ((x) << 0) - -#define PIR_CLRSR (0x1 << 27) /* clear status registers */ -#define PIR_QSGATE (0x1 << 10) /* Read DQS gate training */ -#define PIR_DRAMINIT (0x1 << 8) /* DRAM initialization */ -#define PIR_DRAMRST (0x1 << 7) /* DRAM reset */ -#define PIR_PHYRST (0x1 << 6) /* PHY reset */ -#define PIR_DCAL (0x1 << 5) /* DDL calibration */ -#define PIR_PLLINIT (0x1 << 4) /* PLL initialization */ -#define PIR_ZCAL (0x1 << 1) /* ZQ calibration */ -#define PIR_INIT (0x1 << 0) /* PHY initialization trigger */ - -#define PGSR_INIT_DONE (0x1 << 0) /* PHY init done */ - -#define ZQCR_PWRDOWN (1U << 31) /* ZQ power down */ - -#define ACBDLR_WRITE_DELAY(x) ((x) << 8) - -#define DXBDLR_DQ(x) (x) /* DQ0-7 BDLR index */ -#define DXBDLR_DM 8 /* DM BDLR index */ -#define DXBDLR_DQS 9 /* DQS BDLR index */ -#define DXBDLR_DQSN 10 /* DQSN BDLR index */ - -#define DXBDLR_WRITE_DELAY(x) ((x) << 8) -#define DXBDLR_READ_DELAY(x) ((x) << 0) - -/* - * The delay parameters below allow to allegedly specify delay times of some - * unknown unit for each individual bit trace in each of the four data bytes - * the 32-bit wide access consists of. Also three control signals can be - * adjusted individually. - */ -#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE) -/* The eight data lines (DQn) plus DM, DQS and DQSN */ -#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3) -struct dram_para { - u16 page_size; - u8 bus_full_width; - u8 dual_rank; - u8 row_bits; - u8 bank_bits; - const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE]; - const u8 ac_delays[31]; -}; - -static inline int ns_to_t(int nanoseconds) -{ - const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2; - - return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000); -} - -void mctl_set_timing_params(uint16_t socid, struct dram_para *para); - -#endif /* _SUNXI_DRAM_SUN8I_H3_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h deleted file mode 100644 index 40a3f84..0000000 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ /dev/null @@ -1,248 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_GPIO_H -#define _SUNXI_GPIO_H - -#include <linux/types.h> -#include <asm/arch/cpu.h> - -/* - * sunxi has 9 banks of gpio, they are: - * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 - * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 - * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 - */ - -#define SUNXI_GPIO_A 0 -#define SUNXI_GPIO_B 1 -#define SUNXI_GPIO_C 2 -#define SUNXI_GPIO_D 3 -#define SUNXI_GPIO_E 4 -#define SUNXI_GPIO_F 5 -#define SUNXI_GPIO_G 6 -#define SUNXI_GPIO_H 7 -#define SUNXI_GPIO_I 8 - -/* - * This defines the number of GPIO banks for the _main_ GPIO controller. - * You should fix up the padding in struct sunxi_gpio_reg below if you - * change this. - */ -#define SUNXI_GPIO_BANKS 9 - -/* - * sun6i/sun8i and later SoCs have an additional GPIO controller (R_PIO) - * at a different register offset. - * - * sun6i has 2 banks: - * PL0 - PL8 | PM0 - PM7 - * - * sun8i has 1 bank: - * PL0 - PL11 - * - * sun9i has 3 banks: - * PL0 - PL9 | PM0 - PM15 | PN0 - PN1 - */ -#define SUNXI_GPIO_L 11 -#define SUNXI_GPIO_M 12 -#define SUNXI_GPIO_N 13 - -struct sunxi_gpio { - u32 cfg[4]; - u32 dat; - u32 drv[2]; - u32 pull[2]; -}; - -/* gpio interrupt control */ -struct sunxi_gpio_int { - u32 cfg[3]; - u32 ctl; - u32 sta; - u32 deb; /* interrupt debounce */ -}; - -struct sunxi_gpio_reg { - struct sunxi_gpio gpio_bank[SUNXI_GPIO_BANKS]; - u8 res[0xbc]; - struct sunxi_gpio_int gpio_int; -}; - -#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \ - &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \ - &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L]) - -#define GPIO_BANK(pin) ((pin) >> 5) -#define GPIO_NUM(pin) ((pin) & 0x1f) - -#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3) -#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2) - -#define GPIO_DRV_INDEX(pin) (((pin) & 0x1f) >> 4) -#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) - -#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4) -#define GPIO_PULL_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1) - -/* GPIO bank sizes */ -#define SUNXI_GPIO_A_NR 32 -#define SUNXI_GPIO_B_NR 32 -#define SUNXI_GPIO_C_NR 32 -#define SUNXI_GPIO_D_NR 32 -#define SUNXI_GPIO_E_NR 32 -#define SUNXI_GPIO_F_NR 32 -#define SUNXI_GPIO_G_NR 32 -#define SUNXI_GPIO_H_NR 32 -#define SUNXI_GPIO_I_NR 32 -#define SUNXI_GPIO_L_NR 32 -#define SUNXI_GPIO_M_NR 32 - -#define SUNXI_GPIO_NEXT(__gpio) \ - ((__gpio##_START) + (__gpio##_NR) + 0) - -enum sunxi_gpio_number { - SUNXI_GPIO_A_START = 0, - SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), - SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), - SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), - SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), - SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), - SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), - SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), - SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), - SUNXI_GPIO_L_START = 352, - SUNXI_GPIO_M_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_L), - SUNXI_GPIO_N_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_M), - SUNXI_GPIO_AXP0_START = 1024, -}; - -/* SUNXI GPIO number definitions */ -#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) -#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) -#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) -#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) -#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) -#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) -#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) -#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) -#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) -#define SUNXI_GPL(_nr) (SUNXI_GPIO_L_START + (_nr)) -#define SUNXI_GPM(_nr) (SUNXI_GPIO_M_START + (_nr)) -#define SUNXI_GPN(_nr) (SUNXI_GPIO_N_START + (_nr)) - -#define SUNXI_GPAXP0(_nr) (SUNXI_GPIO_AXP0_START + (_nr)) - -/* GPIO pin function config */ -#define SUNXI_GPIO_INPUT 0 -#define SUNXI_GPIO_OUTPUT 1 -#define SUNXI_GPIO_DISABLE 7 - -#define SUNXI_GPA_EMAC 2 -#define SUN6I_GPA_GMAC 2 -#define SUN7I_GPA_GMAC 5 -#define SUN6I_GPA_SDC2 5 -#define SUN6I_GPA_SDC3 4 -#define SUN8I_H3_GPA_UART0 2 - -#define SUN4I_GPB_PWM 2 -#define SUN4I_GPB_TWI0 2 -#define SUN4I_GPB_TWI1 2 -#define SUN5I_GPB_TWI1 2 -#define SUN4I_GPB_TWI2 2 -#define SUN5I_GPB_TWI2 2 -#define SUN4I_GPB_UART0 2 -#define SUN5I_GPB_UART0 2 -#define SUN8I_GPB_UART2 2 -#define SUN8I_A33_GPB_UART0 3 -#define SUN8I_A83T_GPB_UART0 2 -#define SUN8I_V3S_GPB_UART0 3 -#define SUN50I_GPB_UART0 4 - -#define SUNXI_GPC_NAND 2 -#define SUNXI_GPC_SPI0 3 -#define SUNXI_GPC_SDC2 3 -#define SUN6I_GPC_SDC3 4 -#define SUN50I_GPC_SPI0 4 - -#define SUN8I_GPD_SDC1 3 -#define SUNXI_GPD_LCD0 2 -#define SUNXI_GPD_LVDS0 3 -#define SUNXI_GPD_PWM 2 - -#define SUN5I_GPE_SDC2 3 -#define SUN8I_GPE_TWI2 3 -#define SUN50I_GPE_TWI2 3 - -#define SUNXI_GPF_SDC0 2 -#define SUNXI_GPF_UART0 4 -#define SUN8I_GPF_UART0 3 - -#define SUN4I_GPG_SDC1 4 -#define SUN5I_GPG_SDC1 2 -#define SUN6I_GPG_SDC1 2 -#define SUN8I_GPG_SDC1 2 -#define SUN6I_GPG_TWI3 2 -#define SUN5I_GPG_UART1 4 - -#define SUN6I_GPH_PWM 2 -#define SUN8I_GPH_PWM 2 -#define SUN4I_GPH_SDC1 5 -#define SUN6I_GPH_TWI0 2 -#define SUN8I_GPH_TWI0 2 -#define SUN50I_GPH_TWI0 2 -#define SUN6I_GPH_TWI1 2 -#define SUN8I_GPH_TWI1 2 -#define SUN50I_GPH_TWI1 2 -#define SUN6I_GPH_TWI2 2 -#define SUN6I_GPH_UART0 2 -#define SUN9I_GPH_UART0 2 -#define SUN50I_H6_GPH_UART0 2 - -#define SUNXI_GPI_SDC3 2 -#define SUN7I_GPI_TWI3 3 -#define SUN7I_GPI_TWI4 3 - -#define SUN6I_GPL0_R_P2WI_SCK 3 -#define SUN6I_GPL1_R_P2WI_SDA 3 - -#define SUN8I_GPL_R_RSB 2 -#define SUN8I_H3_GPL_R_TWI 2 -#define SUN8I_A23_GPL_R_TWI 3 -#define SUN8I_GPL_R_UART 2 -#define SUN50I_GPL_R_TWI 2 - -#define SUN9I_GPN_R_RSB 3 - -/* GPIO pin pull-up/down config */ -#define SUNXI_GPIO_PULL_DISABLE 0 -#define SUNXI_GPIO_PULL_UP 1 -#define SUNXI_GPIO_PULL_DOWN 2 - -/* Virtual AXP0 GPIOs */ -#define SUNXI_GPIO_AXP0_PREFIX "AXP0-" -#define SUNXI_GPIO_AXP0_VBUS_DETECT 4 -#define SUNXI_GPIO_AXP0_VBUS_ENABLE 5 -#define SUNXI_GPIO_AXP0_GPIO_COUNT 6 - -void sunxi_gpio_set_cfgbank(struct sunxi_gpio *pio, int bank_offset, u32 val); -void sunxi_gpio_set_cfgpin(u32 pin, u32 val); -int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); -int sunxi_gpio_get_cfgpin(u32 pin); -int sunxi_gpio_set_drv(u32 pin, u32 val); -int sunxi_gpio_set_pull(u32 pin, u32 val); -int sunxi_name_to_gpio_bank(const char *name); -int sunxi_name_to_gpio(const char *name); -#define name_to_gpio(name) sunxi_name_to_gpio(name) - -#if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO -int axp_gpio_init(void); -#else -static inline int axp_gpio_init(void) { return 0; } -#endif - -#endif /* _SUNXI_GPIO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gtbus.h b/arch/arm/include/asm/arch-sunxi/gtbus.h deleted file mode 100644 index a89102e..0000000 --- a/arch/arm/include/asm/arch-sunxi/gtbus.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * GTBUS initialisation - * - * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH - * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> - */ - -#ifndef _SUNXI_GTBUS_H -#define _SUNXI_GTBUS_H - -#if defined(CONFIG_MACH_SUN9I) -#include <asm/arch/gtbus_sun9i.h> -#endif - -#ifndef __ASSEMBLY__ -void gtbus_init(void); -#endif - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h b/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h deleted file mode 100644 index f962992..0000000 --- a/arch/arm/include/asm/arch-sunxi/gtbus_sun9i.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * GTBUS initialisation for sun9i - * - * (C) Copyright 2016 Theobroma Systems Design und Consulting GmbH - * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> - */ - -#ifndef _SUNXI_GTBUS_SUN9I_H -#define _SUNXI_GTBUS_SUN9I_H - -#include <linux/types.h> - -struct sunxi_gtbus_reg { - u32 mst_cfg[36]; /* 0x000 */ - u8 reserved1[0x70]; /* 0x090 */ - u32 bw_wdw_cfg; /* 0x100 */ - u32 mst_read_prio_cfg[2]; /* 0x104 */ - u32 lvl2_mst_cfg; /* 0x10c */ - u32 sw_clk_on; /* 0x110 */ - u32 sw_clk_off; /* 0x114 */ - u32 pmu_mst_en; /* 0x118 */ - u32 pmu_cfg; /* 0x11c */ - u32 pmu_cnt[19]; /* 0x120 */ - u32 reserved2[0x94]; /* 0x16c */ - u32 cci400_config[3]; /* 0x200 */ - u32 cci400_status[2]; /* 0x20c */ -}; - -/* for register GT_MST_CFG_REG(n) */ -#define GT_ENABLE_REQ (1<<31) /* clock on */ -#define GT_DISABLE_REQ (1<<30) /* clock off */ -#define GT_QOS_SHIFT 28 -#define GT_THD1_SHIFT 16 -#define GT_REQN_MAX 0xf /* max no master requests in one cycle */ -#define GT_REQN_SHIFT 12 -#define GT_THD0_SHIFT 0 - -#define GT_QOS_MAX 0x3 -#define GT_THD_MAX 0xfff -#define GT_BW_WDW_MAX 0xffff - -/* mst_read_prio_cfg */ -#define GT_PRIO_LOW 0 -#define GT_PRIO_HIGH 1 - -/* GTBUS port ids */ -#define GT_PORT_CPUM1 0 -#define GT_PORT_CPUM2 1 -#define GT_PORT_SATA 2 -#define GT_PORT_USB3 3 -#define GT_PORT_FE0 4 -#define GT_PORT_BE1 5 -#define GT_PORT_BE2 6 -#define GT_PORT_IEP0 7 -#define GT_PORT_FE1 8 -#define GT_PORT_BE0 9 -#define GT_PORT_FE2 10 -#define GT_PORT_IEP1 11 -#define GT_PORT_VED 12 -#define GT_PORT_VEE 13 -#define GT_PORT_FD 14 -#define GT_PORT_CSI 15 -#define GT_PORT_MP 16 -#define GT_PORT_HSI 17 -#define GT_PORT_SS 18 -#define GT_PORT_TS 19 -#define GT_PORT_DMA 20 -#define GT_PORT_NDFC0 21 -#define GT_PORT_NDFC1 22 -#define GT_PORT_CPUS 23 -#define GT_PORT_TH 24 -#define GT_PORT_GMAC 25 -#define GT_PORT_USB0 26 -#define GT_PORT_MSTG0 27 -#define GT_PORT_MSTG1 28 -#define GT_PORT_MSTG2 29 -#define GT_PORT_MSTG3 30 -#define GT_PORT_USB1 31 -#define GT_PORT_GPU0 32 -#define GT_PORT_GPU1 33 -#define GT_PORT_USB2 34 -#define GT_PORT_CPUM0 35 - -#define GP_MST_CFG_DEFAULT \ - ((GT_QOS_MAX << GT_QOS_SHIFT) | \ - (GT_THD_MAX << GT_THD1_SHIFT) | \ - (GT_REQN_MAX << GT_REQN_SHIFT) | \ - (GT_THD_MAX << GT_THD0_SHIFT)) - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h deleted file mode 100644 index 1cb2ba6..0000000 --- a/arch/arm/include/asm/arch-sunxi/i2c.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 - Hans de Goede <hdegoede@redhat.com> - */ -#ifndef _SUNXI_I2C_H_ -#define _SUNXI_I2C_H_ - -#include <asm/arch/cpu.h> - -#ifdef CONFIG_I2C0_ENABLE -#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE -#endif -#ifdef CONFIG_I2C1_ENABLE -#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE -#endif -#ifdef CONFIG_I2C2_ENABLE -#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE -#endif -#ifdef CONFIG_I2C3_ENABLE -#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE -#endif -#ifdef CONFIG_I2C4_ENABLE -#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE -#endif -#ifdef CONFIG_R_I2C_ENABLE -#define CONFIG_I2C_MVTWSI_BASE5 SUNXI_R_TWI_BASE -#endif - -/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */ -#define CONFIG_SYS_TCLK 24000000 - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/lcdc.h b/arch/arm/include/asm/arch-sunxi/lcdc.h deleted file mode 100644 index 90216bc..0000000 --- a/arch/arm/include/asm/arch-sunxi/lcdc.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi platform timing controller register and constant defines - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> - */ - -#ifndef _LCDC_H -#define _LCDC_H - -#include <fdtdec.h> - -struct sunxi_lcdc_reg { - u32 ctrl; /* 0x00 */ - u32 int0; /* 0x04 */ - u32 int1; /* 0x08 */ - u8 res0[0x04]; /* 0x0c */ - u32 tcon0_frm_ctrl; /* 0x10 */ - u32 tcon0_frm_seed[6]; /* 0x14 */ - u32 tcon0_frm_table[4]; /* 0x2c */ - u8 res1[4]; /* 0x3c */ - u32 tcon0_ctrl; /* 0x40 */ - u32 tcon0_dclk; /* 0x44 */ - u32 tcon0_timing_active; /* 0x48 */ - u32 tcon0_timing_h; /* 0x4c */ - u32 tcon0_timing_v; /* 0x50 */ - u32 tcon0_timing_sync; /* 0x54 */ - u32 tcon0_hv_intf; /* 0x58 */ - u8 res2[0x04]; /* 0x5c */ - u32 tcon0_cpu_intf; /* 0x60 */ - u32 tcon0_cpu_wr_dat; /* 0x64 */ - u32 tcon0_cpu_rd_dat0; /* 0x68 */ - u32 tcon0_cpu_rd_dat1; /* 0x6c */ - u32 tcon0_ttl_timing0; /* 0x70 */ - u32 tcon0_ttl_timing1; /* 0x74 */ - u32 tcon0_ttl_timing2; /* 0x78 */ - u32 tcon0_ttl_timing3; /* 0x7c */ - u32 tcon0_ttl_timing4; /* 0x80 */ - u32 tcon0_lvds_intf; /* 0x84 */ - u32 tcon0_io_polarity; /* 0x88 */ - u32 tcon0_io_tristate; /* 0x8c */ - u32 tcon1_ctrl; /* 0x90 */ - u32 tcon1_timing_source; /* 0x94 */ - u32 tcon1_timing_scale; /* 0x98 */ - u32 tcon1_timing_out; /* 0x9c */ - u32 tcon1_timing_h; /* 0xa0 */ - u32 tcon1_timing_v; /* 0xa4 */ - u32 tcon1_timing_sync; /* 0xa8 */ - u8 res3[0x44]; /* 0xac */ - u32 tcon1_io_polarity; /* 0xf0 */ - u32 tcon1_io_tristate; /* 0xf4 */ - u8 res4[0x108]; /* 0xf8 */ - u32 mux_ctrl; /* 0x200 */ - u8 res5[0x1c]; /* 0x204 */ - u32 lvds_ana0; /* 0x220 */ - u32 lvds_ana1; /* 0x224 */ -}; - -/* - * LCDC register constants. - */ -#define SUNXI_LCDC_X(x) (((x) - 1) << 16) -#define SUNXI_LCDC_Y(y) (((y) - 1) << 0) -#define SUNXI_LCDC_TCON_VSYNC_MASK (1 << 24) -#define SUNXI_LCDC_TCON_HSYNC_MASK (1 << 25) -#define SUNXI_LCDC_CTRL_IO_MAP_MASK (1 << 0) -#define SUNXI_LCDC_CTRL_IO_MAP_TCON0 (0 << 0) -#define SUNXI_LCDC_CTRL_IO_MAP_TCON1 (1 << 0) -#define SUNXI_LCDC_CTRL_TCON_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB666 ((1 << 31) | (0 << 4)) -#define SUNXI_LCDC_TCON0_FRM_CTRL_RGB565 ((1 << 31) | (5 << 4)) -#define SUNXI_LCDC_TCON0_FRM_SEED 0x11111111 -#define SUNXI_LCDC_TCON0_FRM_TAB0 0x01010000 -#define SUNXI_LCDC_TCON0_FRM_TAB1 0x15151111 -#define SUNXI_LCDC_TCON0_FRM_TAB2 0x57575555 -#define SUNXI_LCDC_TCON0_FRM_TAB3 0x7f7f7777 -#define SUNXI_LCDC_TCON0_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) -#define SUNXI_LCDC_TCON0_CTRL_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_DCLK_DIV(n) ((n) << 0) -#define SUNXI_LCDC_TCON0_DCLK_ENABLE (0xf << 28) -#define SUNXI_LCDC_TCON0_TIMING_H_BP(n) (((n) - 1) << 0) -#define SUNXI_LCDC_TCON0_TIMING_H_TOTAL(n) (((n) - 1) << 16) -#define SUNXI_LCDC_TCON0_TIMING_V_BP(n) (((n) - 1) << 0) -#define SUNXI_LCDC_TCON0_TIMING_V_TOTAL(n) (((n) * 2) << 16) -#ifdef CONFIG_SUNXI_GEN_SUN6I -#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 (1 << 20) -#else -#define SUNXI_LCDC_TCON0_LVDS_CLK_SEL_TCON0 0 /* NA */ -#endif -#define SUNXI_LCDC_TCON0_LVDS_INTF_BITWIDTH(n) ((n) << 26) -#define SUNXI_LCDC_TCON0_LVDS_INTF_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON0_IO_POL_DCLK_PHASE(x) ((x) << 28) -#define SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(n) (((n) & 0x1f) << 4) -#define SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE (1 << 20) -#define SUNXI_LCDC_TCON1_CTRL_ENABLE (1 << 31) -#define SUNXI_LCDC_TCON1_TIMING_H_BP(n) (((n) - 1) << 0) -#define SUNXI_LCDC_TCON1_TIMING_H_TOTAL(n) (((n) - 1) << 16) -#define SUNXI_LCDC_TCON1_TIMING_V_BP(n) (((n) - 1) << 0) -#define SUNXI_LCDC_TCON1_TIMING_V_TOTAL(n) ((n) << 16) -#define SUNXI_LCDC_MUX_CTRL_SRC0_MASK (0xf << 0) -#define SUNXI_LCDC_MUX_CTRL_SRC0(x) ((x) << 0) -#define SUNXI_LCDC_MUX_CTRL_SRC1_MASK (0xf << 4) -#define SUNXI_LCDC_MUX_CTRL_SRC1(x) ((x) << 4) -#ifdef CONFIG_SUNXI_GEN_SUN6I -#define SUNXI_LCDC_LVDS_ANA0 0x40040320 -#define SUNXI_LCDC_LVDS_ANA0_EN_MB (1 << 31) -#define SUNXI_LCDC_LVDS_ANA0_DRVC (1 << 24) -#define SUNXI_LCDC_LVDS_ANA0_DRVD(x) ((x) << 20) -#else -#define SUNXI_LCDC_LVDS_ANA0 0x3f310000 -#define SUNXI_LCDC_LVDS_ANA0_UPDATE (1 << 22) -#endif -#define SUNXI_LCDC_LVDS_ANA1_INIT1 (0x1f << 26 | 0x1f << 10) -#define SUNXI_LCDC_LVDS_ANA1_INIT2 (0x1f << 16 | 0x1f << 00) - -void lcdc_init(struct sunxi_lcdc_reg * const lcdc); -void lcdc_enable(struct sunxi_lcdc_reg * const lcdc, int depth); -void lcdc_tcon0_mode_set(struct sunxi_lcdc_reg * const lcdc, - const struct display_timing *mode, - int clk_div, bool for_ext_vga_dac, - int depth, int dclk_phase); -void lcdc_tcon1_mode_set(struct sunxi_lcdc_reg * const lcdc, - const struct display_timing *mode, - bool ext_hvsync, bool is_composite); -void lcdc_pll_set(struct sunxi_ccm_reg * const ccm, int tcon, - int dotclock, int *clk_div, int *clk_double, - bool is_composite); - -#endif /* _LCDC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h deleted file mode 100644 index f2deafd..0000000 --- a/arch/arm/include/asm/arch-sunxi/mmc.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Aaron <leafy.myeh@allwinnertech.com> - * - * MMC register definition for allwinner sunxi platform. - */ - -#ifndef _SUNXI_MMC_H -#define _SUNXI_MMC_H - -#include <linux/types.h> - -struct sunxi_mmc { - u32 gctrl; /* 0x00 global control */ - u32 clkcr; /* 0x04 clock control */ - u32 timeout; /* 0x08 time out */ - u32 width; /* 0x0c bus width */ - u32 blksz; /* 0x10 block size */ - u32 bytecnt; /* 0x14 byte count */ - u32 cmd; /* 0x18 command */ - u32 arg; /* 0x1c argument */ - u32 resp0; /* 0x20 response 0 */ - u32 resp1; /* 0x24 response 1 */ - u32 resp2; /* 0x28 response 2 */ - u32 resp3; /* 0x2c response 3 */ - u32 imask; /* 0x30 interrupt mask */ - u32 mint; /* 0x34 masked interrupt status */ - u32 rint; /* 0x38 raw interrupt status */ - u32 status; /* 0x3c status */ - u32 ftrglevel; /* 0x40 FIFO threshold watermark*/ - u32 funcsel; /* 0x44 function select */ - u32 cbcr; /* 0x48 CIU byte count */ - u32 bbcr; /* 0x4c BIU byte count */ - u32 dbgc; /* 0x50 debug enable */ - u32 res0; /* 0x54 reserved */ - u32 a12a; /* 0x58 Auto command 12 argument */ - u32 ntsr; /* 0x5c New timing set register */ - u32 res1[8]; - u32 dmac; /* 0x80 internal DMA control */ - u32 dlba; /* 0x84 internal DMA descr list base address */ - u32 idst; /* 0x88 internal DMA status */ - u32 idie; /* 0x8c internal DMA interrupt enable */ - u32 chda; /* 0x90 */ - u32 cbda; /* 0x94 */ - u32 res2[26]; -#if defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) - u32 res3[17]; - u32 samp_dl; - u32 res4[46]; -#endif - u32 fifo; /* 0x100 / 0x200 FIFO access address */ -}; - -#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) -#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) -#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) - -#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) -#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) -#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) -#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ - SUNXI_MMC_GCTRL_FIFO_RESET|\ - SUNXI_MMC_GCTRL_DMA_RESET) -#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) -#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) - -#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) -#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) -#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) -#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) -#define SUNXI_MMC_CMD_WRITE (0x1 << 10) -#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) -#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) -#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) -#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) -#define SUNXI_MMC_CMD_START (0x1 << 31) - -#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) -#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) -#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) -#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) -#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) -#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) -#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) -#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) -#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) -#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) -#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) -#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) -#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) -#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) -#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) -#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) -#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) -#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) -#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ - (SUNXI_MMC_RINT_RESP_ERROR | \ - SUNXI_MMC_RINT_RESP_CRC_ERROR | \ - SUNXI_MMC_RINT_DATA_CRC_ERROR | \ - SUNXI_MMC_RINT_RESP_TIMEOUT | \ - SUNXI_MMC_RINT_DATA_TIMEOUT | \ - SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ - SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ - SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ - SUNXI_MMC_RINT_START_BIT_ERROR | \ - SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ -#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ - (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ - SUNXI_MMC_RINT_DATA_OVER | \ - SUNXI_MMC_RINT_COMMAND_DONE | \ - SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) - -#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) -#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) -#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) -#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) -#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) -#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) -#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) - -#define SUNXI_MMC_NTSR_MODE_SEL_NEW (0x1 << 31) - -#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) -#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) -#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) - -#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) -#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) - -#define SUNXI_MMC_COMMON_CLK_GATE (1 << 16) -#define SUNXI_MMC_COMMON_RESET (1 << 18) - -#define SUNXI_MMC_CAL_DL_SW_EN (0x1 << 7) - -struct mmc *sunxi_mmc_init(int sdc_no); -#endif /* _SUNXI_MMC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/p2wi.h b/arch/arm/include/asm/arch-sunxi/p2wi.h deleted file mode 100644 index 5f2a898..0000000 --- a/arch/arm/include/asm/arch-sunxi/p2wi.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi platform Push-Push i2c register definition. - * - * (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> - * http://linux-sunxi.org - * - * (c)Copyright 2006-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_P2WI_H -#define _SUNXI_P2WI_H - -#include <linux/types.h> - -#define P2WI_CTRL_RESET (0x1 << 0) -#define P2WI_CTRL_IRQ_EN (0x1 << 1) -#define P2WI_CTRL_TRANS_ABORT (0x1 << 6) -#define P2WI_CTRL_TRANS_START (0x1 << 7) - -#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0) -#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff) -#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1) -#define P2WI_CC_CLK_DIV(n) \ - __P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n)) -#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8) -#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7) - -#define P2WI_IRQ_TRANS_DONE (0x1 << 0) -#define P2WI_IRQ_TRANS_ERR (0x1 << 1) -#define P2WI_IRQ_LOAD_BUSY (0x1 << 2) - -#define P2WI_STAT_TRANS_DONE (0x1 << 0) -#define P2WI_STAT_TRANS_ERR (0x1 << 1) -#define P2WI_STAT_LOAD_BUSY (0x1 << 2) -#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8) -#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff) -#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01 -#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02 -#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04 -#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08 -#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10 -#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20 -#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40 -#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80 -#define P2WI_STAT_TRANS_ERR_BYTE_1 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1) -#define P2WI_STAT_TRANS_ERR_BYTE_2 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2) -#define P2WI_STAT_TRANS_ERR_BYTE_3 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3) -#define P2WI_STAT_TRANS_ERR_BYTE_4 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4) -#define P2WI_STAT_TRANS_ERR_BYTE_5 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5) -#define P2WI_STAT_TRANS_ERR_BYTE_6 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6) -#define P2WI_STAT_TRANS_ERR_BYTE_7 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7) -#define P2WI_STAT_TRANS_ERR_BYTE_8 \ - __P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8) - -#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0) -#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff) -#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8) -#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff) -#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16) -#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff) -#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24) -#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff) -#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0) -#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff) -#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8) -#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff) -#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16) -#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff) -#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24) -#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff) - -#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0) -#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7) -#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1) -#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4) - -#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0) -#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff) -#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8) -#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff) -#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16) -#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff) -#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24) -#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff) -#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0) -#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff) -#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8) -#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff) -#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16) -#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff) -#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24) -#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff) - -#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0) -#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1) -#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2) -#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3) -#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4) -#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5) - -#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0) -#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff) -#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8) -#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff) -#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16) -#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff) -#define P2WI_PM_INIT_SEND (0x1 << 31) - -struct sunxi_p2wi_reg { - u32 ctrl; /* 0x00 control */ - u32 cc; /* 0x04 clock control */ - u32 irq; /* 0x08 interrupt */ - u32 status; /* 0x0c status */ - u32 dataddr0; /* 0x10 data address 0 */ - u32 dataddr1; /* 0x14 data address 1 */ - u32 numbytes; /* 0x18 num bytes */ - u32 data0; /* 0x1c data buffer 0 */ - u32 data1; /* 0x20 data buffer 1 */ - u32 linectrl; /* 0x24 line control */ - u32 pm; /* 0x28 power management */ -}; - -void p2wi_init(void); -int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data); -int p2wi_read(const u8 addr, u8 *data); -int p2wi_write(const u8 addr, u8 data); - -#endif /* _SUNXI_P2WI_H */ diff --git a/arch/arm/include/asm/arch-sunxi/pmic_bus.h b/arch/arm/include/asm/arch-sunxi/pmic_bus.h deleted file mode 100644 index 3ccfe13..0000000 --- a/arch/arm/include/asm/arch-sunxi/pmic_bus.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com> - * - * Sunxi PMIC bus access helpers header - */ - -#ifndef _SUNXI_PMIC_BUS_H -#define _SUNXI_PMIS_BUS_H - -int pmic_bus_init(void); -int pmic_bus_read(u8 reg, u8 *data); -int pmic_bus_write(u8 reg, u8 data); -int pmic_bus_setbits(u8 reg, u8 bits); -int pmic_bus_clrbits(u8 reg, u8 bits); - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/prcm.h b/arch/arm/include/asm/arch-sunxi/prcm.h deleted file mode 100644 index 58a3689..0000000 --- a/arch/arm/include/asm/arch-sunxi/prcm.h +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi A31 Power Management Unit register definition. - * - * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl> - * http://linux-sunxi.org - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Berg Xing <bergxing@allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SUNXI_PRCM_H -#define _SUNXI_PRCM_H - -#define __PRCM_CPUS_CFG_PRE(n) (((n) & 0x3) << 4) -#define PRCM_CPUS_CFG_PRE_MASK __PRCM_CPUS_CFG_PRE(0x3) -#define __PRCM_CPUS_CFG_PRE_DIV(n) (((n) >> 1) - 1) -#define PRCM_CPUS_CFG_PRE_DIV(n) \ - __PRCM_CPUS_CFG_PRE(__PRCM_CPUS_CFG_CLK_PRE(n)) -#define __PRCM_CPUS_CFG_POST(n) (((n) & 0x1f) << 8) -#define PRCM_CPUS_CFG_POST_MASK __PRCM_CPUS_CFG_POST(0x1f) -#define __PRCM_CPUS_CFG_POST_DIV(n) ((n) - 1) -#define PRCM_CPUS_CFG_POST_DIV(n) \ - __PRCM_CPUS_CFG_POST_DIV(__PRCM_CPUS_CFG_POST_DIV(n)) -#define __PRCM_CPUS_CFG_CLK_SRC(n) (((n) & 0x3) << 16) -#define PRCM_CPUS_CFG_CLK_SRC_MASK __PRCM_CPUS_CFG_CLK_SRC(0x3) -#define __PRCM_CPUS_CFG_CLK_SRC_LOSC 0x0 -#define __PRCM_CPUS_CFG_CLK_SRC_HOSC 0x1 -#define __PRCM_CPUS_CFG_CLK_SRC_PLL6 0x2 -#define __PRCM_CPUS_CFG_CLK_SRC_PDIV 0x3 -#define PRCM_CPUS_CFG_CLK_SRC_LOSC \ - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_LOSC) -#define PRCM_CPUS_CFG_CLK_SRC_HOSC \ - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_HOSC) -#define PRCM_CPUS_CFG_CLK_SRC_PLL6 \ - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PLL6) -#define PRCM_CPUS_CFG_CLK_SRC_PDIV \ - __PRCM_CPUS_CFG_CLK_SRC(__PRCM_CPUS_CFG_CLK_SRC_PDIV) - -#define __PRCM_APB0_RATIO(n) (((n) & 0x3) << 0) -#define PRCM_APB0_RATIO_DIV_MASK __PRCM_APB0_RATIO_DIV(0x3) -#define __PRCM_APB0_RATIO_DIV(n) (((n) >> 1) - 1) -#define PRCM_APB0_RATIO_DIV(n) \ - __PRCM_APB0_RATIO(__PRCM_APB0_RATIO_DIV(n)) - -#define PRCM_CPU_CFG_NEON_CLK_EN (0x1 << 0) -#define PRCM_CPU_CFG_CPU_CLK_EN (0x1 << 1) - -#define PRCM_APB0_GATE_PIO (0x1 << 0) -#define PRCM_APB0_GATE_IR (0x1 << 1) -#define PRCM_APB0_GATE_TIMER01 (0x1 << 2) -#define PRCM_APB0_GATE_P2WI (0x1 << 3) /* sun6i */ -#define PRCM_APB0_GATE_RSB (0x1 << 3) /* sun8i */ -#define PRCM_APB0_GATE_UART (0x1 << 4) -#define PRCM_APB0_GATE_1WIRE (0x1 << 5) -#define PRCM_APB0_GATE_I2C (0x1 << 6) - -#define PRCM_APB0_RESET_PIO (0x1 << 0) -#define PRCM_APB0_RESET_IR (0x1 << 1) -#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) -#define PRCM_APB0_RESET_P2WI (0x1 << 3) -#define PRCM_APB0_RESET_UART (0x1 << 4) -#define PRCM_APB0_RESET_1WIRE (0x1 << 5) -#define PRCM_APB0_RESET_I2C (0x1 << 6) - -#define PRCM_PLL_CTRL_PLL_BIAS (0x1 << 0) -#define PRCM_PLL_CTRL_HOSC_GAIN_ENH (0x1 << 1) -#define __PRCM_PLL_CTRL_USB_CLK_SRC(n) (((n) & 0x3) << 4) -#define PRCM_PLL_CTRL_USB_CLK_SRC_MASK \ - __PRCM_PLL_CTRL_USB_CLK_SRC(0x3) -#define __PRCM_PLL_CTRL_USB_CLK_0 0x0 -#define __PRCM_PLL_CTRL_USB_CLK_1 0x1 -#define __PRCM_PLL_CTRL_USB_CLK_2 0x2 -#define __PRCM_PLL_CTRL_USB_CLK_3 0x3 -#define PRCM_PLL_CTRL_USB_CLK_0 \ - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_0) -#define PRCM_PLL_CTRL_USB_CLK_1 \ - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_1) -#define PRCM_PLL_CTRL_USB_CLK_2 \ - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_2) -#define PRCM_PLL_CTRL_USB_CLK_3 \ - __PRCM_PLL_CTRL_USB_CLK_SRC(__PRCM_PLL_CTRL_USB_CLK_3) -#define __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) (((n) & 0x3) << 12) -#define PRCM_PLL_CTRL_INT_PLL_IN_SEL_MASK \ - __PRCM_PLL_CTRL_INT_PLL_IN_SEL(0x3) -#define PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) \ - __PRCM_PLL_CTRL_INT_PLL_IN_SEL(n) -#define __PRCM_PLL_CTRL_HOSC_CLK_SEL(n) (((n) & 0x3) << 20) -#define PRCM_PLL_CTRL_HOSC_CLK_SEL_MASK \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(0x3) -#define __PRCM_PLL_CTRL_HOSC_CLK_0 0x0 -#define __PRCM_PLL_CTRL_HOSC_CLK_1 0x1 -#define __PRCM_PLL_CTRL_HOSC_CLK_2 0x2 -#define __PRCM_PLL_CTRL_HOSC_CLK_3 0x3 -#define PRCM_PLL_CTRL_HOSC_CLK_0 \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_0) -#define PRCM_PLL_CTRL_HOSC_CLK_1 \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_1) -#define PRCM_PLL_CTRL_HOSC_CLK_2 \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_2) -#define PRCM_PLL_CTRL_HOSC_CLK_3 \ - __PRCM_PLL_CTRL_HOSC_CLK_SEL(__PRCM_PLL_CTRL_HOSC_CLK_3) -#define PRCM_PLL_CTRL_PLL_TST_SRC_EXT (0x1 << 24) -#define PRCM_PLL_CTRL_LDO_DIGITAL_EN (0x1 << 0) -#define PRCM_PLL_CTRL_LDO_ANALOG_EN (0x1 << 1) -#define PRCM_PLL_CTRL_EXT_OSC_EN (0x1 << 2) -#define PRCM_PLL_CTRL_CLK_TST_EN (0x1 << 3) -#define PRCM_PLL_CTRL_IN_PWR_HIGH (0x1 << 15) /* 3.3 for hi 2.5 for lo */ -#define __PRCM_PLL_CTRL_VDD_LDO_OUT(n) (((n) & 0x7) << 16) -#define PRCM_PLL_CTRL_LDO_OUT_MASK \ - __PRCM_PLL_CTRL_LDO_OUT(0x7) -/* When using the low voltage 20 mV steps, and high voltage 30 mV steps */ -#define PRCM_PLL_CTRL_LDO_OUT_L(n) \ - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1000) / 20) & 0x7) -#define PRCM_PLL_CTRL_LDO_OUT_H(n) \ - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) - 1160) / 30) & 0x7) -#define PRCM_PLL_CTRL_LDO_OUT_LV(n) \ - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 20) + 1000) -#define PRCM_PLL_CTRL_LDO_OUT_HV(n) \ - __PRCM_PLL_CTRL_VDD_LDO_OUT((((n) & 0x7) * 30) + 1160) -#define PRCM_PLL_CTRL_LDO_KEY (0xa7 << 24) -#define PRCM_PLL_CTRL_LDO_KEY_MASK (0xff << 24) - -#define PRCM_CLK_1WIRE_GATE (0x1 << 31) - -#define __PRCM_CLK_MOD0_M(n) (((n) & 0xf) << 0) -#define PRCM_CLK_MOD0_M_MASK __PRCM_CLK_MOD0_M(0xf) -#define __PRCM_CLK_MOD0_M_X(n) (n - 1) -#define PRCM_CLK_MOD0_M(n) __PRCM_CLK_MOD0_M(__PRCM_CLK_MOD0_M_X(n)) -#define PRCM_CLK_MOD0_OUT_PHASE(n) (((n) & 0x7) << 8) -#define PRCM_CLK_MOD0_OUT_PHASE_MASK(n) PRCM_CLK_MOD0_OUT_PHASE(0x7) -#define _PRCM_CLK_MOD0_N(n) (((n) & 0x3) << 16) -#define PRCM_CLK_MOD0_N_MASK __PRCM_CLK_MOD_N(0x3) -#define __PRCM_CLK_MOD0_N_X(n) (((n) >> 1) - 1) -#define PRCM_CLK_MOD0_N(n) __PRCM_CLK_MOD0_N(__PRCM_CLK_MOD0_N_X(n)) -#define PRCM_CLK_MOD0_SMPL_PHASE(n) (((n) & 0x7) << 20) -#define PRCM_CLK_MOD0_SMPL_PHASE_MASK PRCM_CLK_MOD0_SMPL_PHASE(0x7) -#define PRCM_CLK_MOD0_SRC_SEL(n) (((n) & 0x7) << 24) -#define PRCM_CLK_MOD0_SRC_SEL_MASK PRCM_CLK_MOD0_SRC_SEL(0x7) -#define PRCM_CLK_MOD0_GATE_EN (0x1 << 31) - -#define PRCM_APB0_RESET_PIO (0x1 << 0) -#define PRCM_APB0_RESET_IR (0x1 << 1) -#define PRCM_APB0_RESET_TIMER01 (0x1 << 2) -#define PRCM_APB0_RESET_P2WI (0x1 << 3) -#define PRCM_APB0_RESET_UART (0x1 << 4) -#define PRCM_APB0_RESET_1WIRE (0x1 << 5) -#define PRCM_APB0_RESET_I2C (0x1 << 6) - -#define __PRCM_CLK_OUTD_M(n) (((n) & 0x7) << 8) -#define PRCM_CLK_OUTD_M_MASK __PRCM_CLK_OUTD_M(0x7) -#define __PRCM_CLK_OUTD_M_X() ((n) - 1) -#define PRCM_CLK_OUTD_M(n) __PRCM_CLK_OUTD_M(__PRCM_CLK_OUTD_M_X(n)) -#define __PRCM_CLK_OUTD_N(n) (((n) & 0x7) << 20) -#define PRCM_CLK_OUTD_N_MASK __PRCM_CLK_OUTD_N(0x7) -#define __PRCM_CLK_OUTD_N_X(n) (((n) >> 1) - 1) -#define PRCM_CLK_OUTD_N(n) __PRCM_CLK_OUTD_N(__PRCM_CLK_OUTD_N_X(n) -#define __PRCM_CLK_OUTD_SRC_SEL(n) (((n) & 0x3) << 24) -#define PRCM_CLK_OUTD_SRC_SEL_MASK __PRCM_CLK_OUTD_SRC_SEL(0x3) -#define __PRCM_CLK_OUTD_SRC_LOSC2 0x0 -#define __PRCM_CLK_OUTD_SRC_LOSC 0x1 -#define __PRCM_CLK_OUTD_SRC_HOSC 0x2 -#define __PRCM_CLK_OUTD_SRC_ERR 0x3 -#define PRCM_CLK_OUTD_SRC_LOSC2 \ -#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC2) -#define PRCM_CLK_OUTD_SRC_LOSC \ -#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_LOSC) -#define PRCM_CLK_OUTD_SRC_HOSC \ -#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_HOSC) -#define PRCM_CLK_OUTD_SRC_ERR \ -#deifne __PRCM_CLK_OUTD_SRC_SEL(__PRCM_CLK_OUTD_SRC_ERR) -#define PRCM_CLK_OUTD_EN (0x1 << 31) - -#define PRCM_CPU0_PWROFF (0x1 << 0) -#define PRCM_CPU1_PWROFF (0x1 << 1) -#define PRCM_CPU2_PWROFF (0x1 << 2) -#define PRCM_CPU3_PWROFF (0x1 << 3) -#define PRCM_CPU_ALL_PWROFF (0xf << 0) - -#define PRCM_VDD_SYS_DRAM_CH0_PAD_HOLD_PWROFF (0x1 << 0) -#define PRCM_VDD_SYS_DRAM_CH1_PAD_HOLD_PWROFF (0x1 << 1) -#define PRCM_VDD_SYS_AVCC_A_PWROFF (0x1 << 2) -#define PRCM_VDD_SYS_CPU0_VDD_PWROFF (0x1 << 3) - -#define PRCM_VDD_GPU_PWROFF (0x1 << 0) - -#define PRCM_VDD_SYS_RESET (0x1 << 0) - -#define PRCM_CPU1_PWR_CLAMP(n) (((n) & 0xff) << 0) -#define PRCM_CPU1_PWR_CLAMP_MASK PRCM_CPU1_PWR_CLAMP(0xff) - -#define PRCM_CPU2_PWR_CLAMP(n) (((n) & 0xff) << 0) -#define PRCM_CPU2_PWR_CLAMP_MASK PRCM_CPU2_PWR_CLAMP(0xff) - -#define PRCM_CPU3_PWR_CLAMP(n) (((n) & 0xff) << 0) -#define PRCM_CPU3_PWR_CLAMP_MASK PRCM_CPU3_PWR_CLAMP(0xff) - -#define PRCM_SEC_SWITCH_APB0_CLK_NONSEC (0x1 << 0) -#define PRCM_SEC_SWITCH_PLL_CFG_NONSEC (0x1 << 1) -#define PRCM_SEC_SWITCH_PWR_GATE_NONSEC (0x1 << 2) - -#ifndef __ASSEMBLY__ -#include <linux/compiler.h> - -struct __packed sunxi_prcm_reg { - u32 cpus_cfg; /* 0x000 */ - u8 res0[0x8]; /* 0x004 */ - u32 apb0_ratio; /* 0x00c */ - u32 cpu0_cfg; /* 0x010 */ - u32 cpu1_cfg; /* 0x014 */ - u32 cpu2_cfg; /* 0x018 */ - u32 cpu3_cfg; /* 0x01c */ - u8 res1[0x8]; /* 0x020 */ - u32 apb0_gate; /* 0x028 */ - u8 res2[0x14]; /* 0x02c */ - u32 pll_ctrl0; /* 0x040 */ - u32 pll_ctrl1; /* 0x044 */ - u8 res3[0x8]; /* 0x048 */ - u32 clk_1wire; /* 0x050 */ - u32 clk_ir; /* 0x054 */ - u8 res4[0x58]; /* 0x058 */ - u32 apb0_reset; /* 0x0b0 */ - u8 res5[0x3c]; /* 0x0b4 */ - u32 clk_outd; /* 0x0f0 */ - u8 res6[0xc]; /* 0x0f4 */ - u32 cpu_pwroff; /* 0x100 */ - u8 res7[0xc]; /* 0x104 */ - u32 vdd_sys_pwroff; /* 0x110 */ - u8 res8[0x4]; /* 0x114 */ - u32 gpu_pwroff; /* 0x118 */ - u8 res9[0x4]; /* 0x11c */ - u32 vdd_pwr_reset; /* 0x120 */ - u8 res10[0x1c]; /* 0x124 */ - u32 cpu_pwr_clamp[4]; /* 0x140 but first one is actually unused */ - u8 res11[0x30]; /* 0x150 */ - u32 dram_pwr; /* 0x180 */ - u8 res12[0xc]; /* 0x184 */ - u32 dram_tst; /* 0x190 */ - u8 res13[0x3c]; /* 0x194 */ - u32 prcm_sec_switch; /* 0x1d0 */ -}; - -void prcm_apb0_enable(u32 flags); -void prcm_apb0_disable(u32 flags); - -#endif /* __ASSEMBLY__ */ -#endif /* _PRCM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/pwm.h b/arch/arm/include/asm/arch-sunxi/pwm.h deleted file mode 100644 index dca283c..0000000 --- a/arch/arm/include/asm/arch-sunxi/pwm.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Hans de Goede <hdegoede@redhat.com> - */ - -#ifndef _SUNXI_PWM_H -#define _SUNXI_PWM_H - -#define SUNXI_PWM_CTRL_REG (SUNXI_PWM_BASE + 0) -#define SUNXI_PWM_CH0_PERIOD (SUNXI_PWM_BASE + 4) - -#define SUNXI_PWM_CTRL_PRESCALE0(x) ((x) & 0xf) -#define SUNXI_PWM_CTRL_PRESCALE0_MASK 0xf -#define SUNXI_PWM_CTRL_ENABLE0 (0x5 << 4) -#define SUNXI_PWM_CTRL_POLARITY0(x) ((x) << 5) -#define SUNXI_PWM_CTRL_CH0_ACT_STA BIT(5) -#define SUNXI_PWM_CTRL_CLK_GATE BIT(6) - -#define SUNXI_PWM_CH0_PERIOD_MAX (0xffff) -#define SUNXI_PWM_CH0_PERIOD_PRD(x) ((x & 0xffff) << 16) -#define SUNXI_PWM_CH0_PERIOD_DUTY(x) ((x) & 0xffff) - -#define SUNXI_PWM_PERIOD_80PCT 0x04af03c0 - -#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN5I -#define SUNXI_PWM_PIN0 SUNXI_GPB(2) -#define SUNXI_PWM_MUX SUN4I_GPB_PWM -#endif - -#if defined CONFIG_MACH_SUN6I -#define SUNXI_PWM_PIN0 SUNXI_GPH(13) -#define SUNXI_PWM_MUX SUN6I_GPH_PWM -#endif - -#if defined CONFIG_MACH_SUN8I_A23 || defined CONFIG_MACH_SUN8I_A33 -#define SUNXI_PWM_PIN0 SUNXI_GPH(0) -#define SUNXI_PWM_MUX SUN8I_GPH_PWM -#endif - -struct sunxi_pwm { - u32 ctrl; - u32 ch0_period; -}; - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/rsb.h b/arch/arm/include/asm/arch-sunxi/rsb.h deleted file mode 100644 index 616b6e2..0000000 --- a/arch/arm/include/asm/arch-sunxi/rsb.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * - * Based on allwinner u-boot sources rsb code which is: - * (C) Copyright 2007-2013 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * lixiang <lixiang@allwinnertech.com> - */ - -#ifndef __SUNXI_RSB_H -#define __SUNXI_RSB_H - -#include <common.h> -#include <asm/io.h> - -struct sunxi_rsb_reg { - u32 ctrl; /* 0x00 */ - u32 ccr; /* 0x04 */ - u32 inte; /* 0x08 */ - u32 stat; /* 0x0c */ - u32 addr; /* 0x10 */ - u8 res0[8]; /* 0x14 */ - u32 data; /* 0x1c */ - u8 res1[4]; /* 0x20 */ - u32 lcr; /* 0x24 */ - u32 dmcr; /* 0x28 */ - u32 cmd; /* 0x2c */ - u32 devaddr; /* 0x30 */ -}; - -#define RSB_CTRL_SOFT_RST (1 << 0) -#define RSB_CTRL_START_TRANS (1 << 7) - -#define RSB_STAT_TOVER_INT (1 << 0) -#define RSB_STAT_TERR_INT (1 << 1) -#define RSB_STAT_LBSY_INT (1 << 2) - -#define RSB_DMCR_DEVICE_MODE_DATA 0x7c3e00 -#define RSB_DMCR_DEVICE_MODE_START (1 << 31) - -#define RSB_CMD_BYTE_WRITE 0x4e -#define RSB_CMD_BYTE_READ 0x8b -#define RSB_CMD_SET_RTSADDR 0xe8 - -#define RSB_DEVADDR_RUNTIME_ADDR(x) ((x) << 16) -#define RSB_DEVADDR_DEVICE_ADDR(x) ((x) << 0) - -int rsb_init(void); -int rsb_set_device_address(u16 device_addr, u16 runtime_addr); -int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data); -int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data); - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h deleted file mode 100644 index 8c916e8..0000000 --- a/arch/arm/include/asm/arch-sunxi/spl.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ -#ifndef _ASM_ARCH_SPL_H_ -#define _ASM_ARCH_SPL_H_ - -#define BOOT0_MAGIC "eGON.BT0" -#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */ -#define SPL_MAJOR_BITS 3 -#define SPL_MINOR_BITS 5 -#define SPL_VERSION(maj, min) \ - ((((maj) & ((1U << SPL_MAJOR_BITS) - 1)) << SPL_MINOR_BITS) | \ - ((min) & ((1U << SPL_MINOR_BITS) - 1))) - -#define SPL_HEADER_VERSION SPL_VERSION(0, 2) - -#define SPL_ENV_HEADER_VERSION SPL_VERSION(0, 1) -#define SPL_DT_HEADER_VERSION SPL_VERSION(0, 2) -#define SPL_DRAM_HEADER_VERSION SPL_VERSION(0, 3) - -#define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS - -/* The low 8-bits of the 'boot_media' field in the SPL header */ -#define SUNXI_BOOTED_FROM_MMC0 0 -#define SUNXI_BOOTED_FROM_NAND 1 -#define SUNXI_BOOTED_FROM_MMC2 2 -#define SUNXI_BOOTED_FROM_SPI 3 -#define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10 -#define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12 - -/* boot head definition from sun4i boot code */ -struct boot_file_head { - uint32_t b_instruction; /* one intruction jumping to real code */ - uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ - uint32_t check_sum; /* generated by PC */ - uint32_t length; /* generated by PC */ - /* - * We use a simplified header, only filling in what is needed - * by the boot ROM. To be compatible with Allwinner tools we - * would need to implement the proper fields here instead of - * padding. - * - * Actually we want the ability to recognize our "sunxi" variant - * of the SPL. To do so, let's place a special signature into the - * "pub_head_size" field. We can reasonably expect Allwinner's - * boot0 to always have the upper 16 bits of this set to 0 (after - * all the value shouldn't be larger than the limit imposed by - * SRAM size). - * If the signature is present (at 0x14), then we know it's safe - * to use the remaining 8 bytes (at 0x18) for our own purposes. - * (E.g. sunxi-tools "fel" utility can pass information there.) - */ - union { - uint32_t pub_head_size; - uint8_t spl_signature[4]; - }; - uint32_t fel_script_address; /* since v0.1, set by sunxi-fel */ - /* - * If the fel_uEnv_length member below is set to a non-zero value, - * it specifies the size (byte count) of data at fel_script_address. - * At the same time this indicates that the data is in uEnv.txt - * compatible format, ready to be imported via "env import -t". - */ - uint32_t fel_uEnv_length; /* since v0.1, set by sunxi-fel */ - /* - * Offset of an ASCIIZ string (relative to the SPL header), which - * contains the default device tree name (CONFIG_DEFAULT_DEVICE_TREE). - * This is optional and may be set to NULL. Is intended to be used - * by flash programming tools for providing nice informative messages - * to the users. - */ - uint32_t dt_name_offset; /* since v0.2, set by mksunxiboot */ - uint32_t dram_size; /* in MiB, since v0.3, set by SPL */ - uint32_t boot_media; /* written here by the boot ROM */ - /* A padding area (may be used for storing text strings) */ - uint32_t string_pool[13]; /* since v0.2, filled by mksunxiboot */ - /* The header must be a multiple of 32 bytes (for VBAR alignment) */ -}; - -/* Compile time check to assure proper alignment of structure */ -typedef char boot_file_head_not_multiple_of_32[1 - 2*(sizeof(struct boot_file_head) % 32)]; - -#define is_boot0_magic(addr) (memcmp((void *)addr, BOOT0_MAGIC, 8) == 0) - -uint32_t sunxi_get_boot_device(void); - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h deleted file mode 100644 index 0646022..0000000 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2012 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - */ - -#ifndef _SYS_PROTO_H_ -#define _SYS_PROTO_H_ - -#include <linux/types.h> - -void sdelay(unsigned long); - -/* return_to_fel() - Return to BROM from SPL - * - * This returns back into the BROM after U-Boot SPL has performed its initial - * init. It uses the provided lr and sp to do so. - * - * @lr: BROM link register value (return address) - * @sp: BROM stack pointer - */ -void return_to_fel(uint32_t lr, uint32_t sp); - -/* Board / SoC level designware gmac init */ -#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I_GMAC -void eth_init_board(void); -#else -static inline void eth_init_board(void) {} -#endif - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h deleted file mode 100644 index 6f138d0..0000000 --- a/arch/arm/include/asm/arch-sunxi/timer.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. <www.allwinnertech.com> - * Tom Cubie <tangliang@allwinnertech.com> - * - * Configuration settings for the Allwinner A10-evb board. - */ - -#ifndef _SUNXI_TIMER_H_ -#define _SUNXI_TIMER_H_ - -#ifndef __ASSEMBLY__ - -#include <linux/types.h> -#include <asm/arch/watchdog.h> - -/* General purpose timer */ -struct sunxi_timer { - u32 ctl; - u32 inter; - u32 val; - u8 res[4]; -}; - -/* Audio video sync*/ -struct sunxi_avs { - u32 ctl; /* 0x80 */ - u32 cnt0; /* 0x84 */ - u32 cnt1; /* 0x88 */ - u32 div; /* 0x8c */ -}; - -/* 64 bit counter */ -struct sunxi_64cnt { - u32 ctl; /* 0xa0 */ - u32 lo; /* 0xa4 */ - u32 hi; /* 0xa8 */ -}; - -/* Rtc */ -struct sunxi_rtc { - u32 ctl; /* 0x100 */ - u32 yymmdd; /* 0x104 */ - u32 hhmmss; /* 0x108 */ -}; - -/* Alarm */ -struct sunxi_alarm { - u32 ddhhmmss; /* 0x10c */ - u32 hhmmss; /* 0x110 */ - u32 en; /* 0x114 */ - u32 irqen; /* 0x118 */ - u32 irqsta; /* 0x11c */ -}; - -/* Timer general purpose register */ -struct sunxi_tgp { - u32 tgpd; -}; - -struct sunxi_timer_reg { - u32 tirqen; /* 0x00 */ - u32 tirqsta; /* 0x04 */ - u8 res1[8]; - struct sunxi_timer timer[6]; /* We have 6 timers */ - u8 res2[16]; - struct sunxi_avs avs; -#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40) - struct sunxi_wdog wdog; /* 0x90 */ - /* XXX the following is not accurate for sun5i/sun7i */ - struct sunxi_64cnt cnt64; /* 0xa0 */ - u8 res4[0x58]; - struct sunxi_rtc rtc; - struct sunxi_alarm alarm; - struct sunxi_tgp tgp[4]; - u8 res5[8]; - u32 cpu_cfg; -#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) - u8 res3[16]; - struct sunxi_wdog wdog[5]; /* We have 5 watchdogs */ -#endif -}; - -#endif /* __ASSEMBLY__ */ - -#endif diff --git a/arch/arm/include/asm/arch-sunxi/tve.h b/arch/arm/include/asm/arch-sunxi/tve.h deleted file mode 100644 index 46cd87e..0000000 --- a/arch/arm/include/asm/arch-sunxi/tve.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sunxi TV encoder register and constant defines - * - * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com> - * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net> - */ - -#ifndef _TVE_H -#define _TVE_H - -enum tve_mode { - tve_mode_vga, - tve_mode_composite_pal, - tve_mode_composite_ntsc, - tve_mode_composite_pal_m, - tve_mode_composite_pal_nc, -}; - -/* - * This is based on the A10s User Manual, and the A10s only supports - * composite video and not vga like the A10 / A20 does, still other - * than the removed vga out capability the tvencoder seems to be the same. - * "unknown#" registers are registers which are used in the A10 kernel code, - * but not documented in the A10s User Manual. - */ -struct sunxi_tve_reg { - u32 gctrl; /* 0x000 */ - u32 cfg0; /* 0x004 */ - u32 dac_cfg0; /* 0x008 */ - u32 filter; /* 0x00c */ - u32 chroma_freq; /* 0x010 */ - u32 porch_num; /* 0x014 */ - u32 unknown0; /* 0x018 */ - u32 line_num; /* 0x01c */ - u32 blank_black_level; /* 0x020 */ - u32 unknown1; /* 0x024, seems to be 1 byte per dac */ - u8 res0[0x08]; /* 0x028 */ - u32 auto_detect_en; /* 0x030 */ - u32 auto_detect_int_status; /* 0x034 */ - u32 auto_detect_status; /* 0x038 */ - u32 auto_detect_debounce; /* 0x03c */ - u32 csc_reg0; /* 0x040 */ - u32 csc_reg1; /* 0x044 */ - u32 csc_reg2; /* 0x048 */ - u32 csc_reg3; /* 0x04c */ - u8 res1[0xb0]; /* 0x050 */ - u32 color_burst; /* 0x100 */ - u32 vsync_num; /* 0x104 */ - u32 notch_freq; /* 0x108 */ - u32 cbr_level; /* 0x10c */ - u32 burst_phase; /* 0x110 */ - u32 burst_width; /* 0x114 */ - u32 unknown2; /* 0x118 */ - u32 sync_vbi_level; /* 0x11c */ - u32 white_level; /* 0x120 */ - u32 active_num; /* 0x124 */ - u32 chroma_bw_gain; /* 0x128 */ - u32 notch_width; /* 0x12c */ - u32 resync_num; /* 0x130 */ - u32 slave_para; /* 0x134 */ - u32 cfg1; /* 0x138 */ - u32 cfg2; /* 0x13c */ -}; - -/* - * TVE register constants. - */ -#define SUNXI_TVE_GCTRL_ENABLE (1 << 0) -/* - * Select input 0 to disable dac, 1 - 4 to feed dac from tve0, 5 - 8 to feed - * dac from tve1. When using tve1 the mux value must be written to both tve0's - * and tve1's gctrl reg. - */ -#define SUNXI_TVE_GCTRL_DAC_INPUT_MASK(dac) (0xf << (((dac) + 1) * 4)) -#define SUNXI_TVE_GCTRL_DAC_INPUT(dac, sel) ((sel) << (((dac) + 1) * 4)) -#define SUNXI_TVE_CFG0_VGA 0x20000000 -#define SUNXI_TVE_CFG0_PAL 0x07030001 -#define SUNXI_TVE_CFG0_NTSC 0x07030000 -#define SUNXI_TVE_DAC_CFG0_VGA 0x403e1ac7 -#ifdef CONFIG_MACH_SUN5I -#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x433f0009 -#else -#define SUNXI_TVE_DAC_CFG0_COMPOSITE 0x403f0008 -#endif -#define SUNXI_TVE_FILTER_COMPOSITE 0x00000120 -#define SUNXI_TVE_CHROMA_FREQ_PAL_M 0x21e6efe3 -#define SUNXI_TVE_CHROMA_FREQ_PAL_NC 0x21f69446 -#define SUNXI_TVE_PORCH_NUM_PAL 0x008a0018 -#define SUNXI_TVE_PORCH_NUM_NTSC 0x00760020 -#define SUNXI_TVE_LINE_NUM_PAL 0x00160271 -#define SUNXI_TVE_LINE_NUM_NTSC 0x0016020d -#define SUNXI_TVE_BLANK_BLACK_LEVEL_PAL 0x00fc00fc -#define SUNXI_TVE_BLANK_BLACK_LEVEL_NTSC 0x00f0011a -#define SUNXI_TVE_UNKNOWN1_VGA 0x00000000 -#define SUNXI_TVE_UNKNOWN1_COMPOSITE 0x18181818 -#define SUNXI_TVE_AUTO_DETECT_EN_DET_EN(dac) (1 << ((dac) + 0)) -#define SUNXI_TVE_AUTO_DETECT_EN_INT_EN(dac) (1 << ((dac) + 16)) -#define SUNXI_TVE_AUTO_DETECT_INT_STATUS(dac) (1 << ((dac) + 0)) -#define SUNXI_TVE_AUTO_DETECT_STATUS_SHIFT(dac) ((dac) * 8) -#define SUNXI_TVE_AUTO_DETECT_STATUS_MASK(dac) (3 << ((dac) * 8)) -#define SUNXI_TVE_AUTO_DETECT_STATUS_NONE 0 -#define SUNXI_TVE_AUTO_DETECT_STATUS_CONNECTED 1 -#define SUNXI_TVE_AUTO_DETECT_STATUS_SHORT_GND 3 -#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_SHIFT(d) ((d) * 8) -#define SUNXI_TVE_AUTO_DETECT_DEBOUNCE_MASK(d) (0xf << ((d) * 8)) -#define SUNXI_TVE_CSC_REG0_ENABLE (1 << 31) -#define SUNXI_TVE_CSC_REG0 0x08440832 -#define SUNXI_TVE_CSC_REG1 0x3b6dace1 -#define SUNXI_TVE_CSC_REG2 0x0e1d13dc -#define SUNXI_TVE_CSC_REG3 0x00108080 -#define SUNXI_TVE_COLOR_BURST_PAL_M 0x00000000 -#define SUNXI_TVE_CBR_LEVEL_PAL 0x00002828 -#define SUNXI_TVE_CBR_LEVEL_NTSC 0x0000004f -#define SUNXI_TVE_BURST_PHASE_NTSC 0x00000000 -#define SUNXI_TVE_BURST_WIDTH_COMPOSITE 0x0016447e -#define SUNXI_TVE_UNKNOWN2_PAL 0x0000e0e0 -#define SUNXI_TVE_UNKNOWN2_NTSC 0x0000a0a0 -#define SUNXI_TVE_SYNC_VBI_LEVEL_NTSC 0x001000f0 -#define SUNXI_TVE_ACTIVE_NUM_COMPOSITE 0x000005a0 -#define SUNXI_TVE_CHROMA_BW_GAIN_COMP 0x00000002 -#define SUNXI_TVE_NOTCH_WIDTH_COMPOSITE 0x00000101 -#define SUNXI_TVE_RESYNC_NUM_PAL 0x800d000c -#define SUNXI_TVE_RESYNC_NUM_NTSC 0x000e000c -#define SUNXI_TVE_SLAVE_PARA_COMPOSITE 0x00000000 - -void tvencoder_mode_set(struct sunxi_tve_reg * const tve, enum tve_mode mode); -void tvencoder_enable(struct sunxi_tve_reg * const tve); - -#endif /* _TVE_H */ diff --git a/arch/arm/include/asm/arch-sunxi/tzpc.h b/arch/arm/include/asm/arch-sunxi/tzpc.h deleted file mode 100644 index 7a6fcae..0000000 --- a/arch/arm/include/asm/arch-sunxi/tzpc.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Chen-Yu Tsai <wens@csie.org> - */ - -#ifndef _SUNXI_TZPC_H -#define _SUNXI_TZPC_H - -#ifndef __ASSEMBLY__ -struct sunxi_tzpc { - u32 r0size; /* 0x00 Size of secure RAM region */ - u32 decport0_status; /* 0x04 Status of decode protection port 0 */ - u32 decport0_set; /* 0x08 Set decode protection port 0 */ - u32 decport0_clear; /* 0x0c Clear decode protection port 0 */ - /* For A80 and later SoCs */ - u32 decport1_status; /* 0x10 Status of decode protection port 1 */ - u32 decport1_set; /* 0x14 Set decode protection port 1 */ - u32 decport1_clear; /* 0x18 Clear decode protection port 1 */ - u32 decport2_status; /* 0x1c Status of decode protection port 2 */ - u32 decport2_set; /* 0x20 Set decode protection port 2 */ - u32 decport2_clear; /* 0x24 Clear decode protection port 2 */ -}; -#endif - -#define SUN6I_TZPC_DECPORT0_RTC (1 << 1) - -#define SUN8I_H3_TZPC_DECPORT0_ALL 0xbe -#define SUN8I_H3_TZPC_DECPORT1_ALL 0xff -#define SUN8I_H3_TZPC_DECPORT2_ALL 0x7f - -void tzpc_init(void); - -#endif /* _SUNXI_TZPC_H */ diff --git a/arch/arm/include/asm/arch-sunxi/watchdog.h b/arch/arm/include/asm/arch-sunxi/watchdog.h deleted file mode 100644 index 38e2ef2..0000000 --- a/arch/arm/include/asm/arch-sunxi/watchdog.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Chen-Yu Tsai <wens@csie.org> - * - * Watchdog register definitions - */ - -#ifndef _SUNXI_WATCHDOG_H_ -#define _SUNXI_WATCHDOG_H_ - -#define WDT_CTRL_RESTART (0x1 << 0) -#define WDT_CTRL_KEY (0x0a57 << 1) - -#if defined(CONFIG_MACH_SUN4I) || \ - defined(CONFIG_MACH_SUN5I) || \ - defined(CONFIG_MACH_SUN7I) || \ - defined(CONFIG_MACH_SUN8I_R40) - -#define WDT_MODE_EN (0x1 << 0) -#define WDT_MODE_RESET_EN (0x1 << 1) - -struct sunxi_wdog { - u32 ctl; /* 0x00 */ - u32 mode; /* 0x04 */ - u32 res[2]; -}; - -#else - -#define WDT_CFG_RESET (0x1) -#define WDT_MODE_EN (0x1) - -struct sunxi_wdog { - u32 irq_en; /* 0x00 */ - u32 irq_sta; /* 0x04 */ - u32 res1[2]; - u32 ctl; /* 0x10 */ - u32 cfg; /* 0x14 */ - u32 mode; /* 0x18 */ - u32 res2; -}; - -#endif - -#endif /* _SUNXI_WATCHDOG_H_ */ |