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-rw-r--r--arch/arm/include/asm/arch-tegra210/ahb.h90
-rw-r--r--arch/arm/include/asm/arch-tegra210/clock-tables.h567
-rw-r--r--arch/arm/include/asm/arch-tegra210/clock.h26
-rw-r--r--arch/arm/include/asm/arch-tegra210/flow.h44
-rw-r--r--arch/arm/include/asm/arch-tegra210/funcmux.h22
-rw-r--r--arch/arm/include/asm/arch-tegra210/gp_padctrl.h73
-rw-r--r--arch/arm/include/asm/arch-tegra210/gpio.h43
-rw-r--r--arch/arm/include/asm/arch-tegra210/mc.h71
-rw-r--r--arch/arm/include/asm/arch-tegra210/pinmux.h415
-rw-r--r--arch/arm/include/asm/arch-tegra210/powergate.h11
-rw-r--r--arch/arm/include/asm/arch-tegra210/sysctr.h25
-rw-r--r--arch/arm/include/asm/arch-tegra210/tegra.h31
12 files changed, 0 insertions, 1418 deletions
diff --git a/arch/arm/include/asm/arch-tegra210/ahb.h b/arch/arm/include/asm/arch-tegra210/ahb.h
deleted file mode 100644
index 8ecd6d9..0000000
--- a/arch/arm/include/asm/arch-tegra210/ahb.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA210_AHB_H_
-#define _TEGRA210_AHB_H_
-
-struct ahb_ctlr {
- u32 reserved0; /* 00h */
- u32 arbitration_disable; /* _ARBITRATION_DISABLE_0, 04h */
- u32 arbitration_priority_ctrl; /* _ARBITRATION_PRIORITY_CTRL_0,08h */
- u32 arbitration_usr_protect; /* _ARBITRATION_USR_PROTECT_0, 0ch */
- u32 gizmo_ahb_mem; /* _GIZMO_AHB_MEM_0, 10h */
- u32 gizmo_apb_dma; /* _GIZMO_APB_DMA_0, 14h */
- u32 reserved6[2]; /* 18h, 1ch */
- u32 gizmo_usb; /* _GIZMO_USB_0, 20h */
- u32 gizmo_ahb_xbar_bridge; /* _GIZMO_AHB_XBAR_BRIDGE_0, 24h */
- u32 gizmo_cpu_ahb_bridge; /* _GIZMO_CPU_AHB_BRIDGE_0, 28h */
- u32 gizmo_cop_ahb_bridge; /* _GIZMO_COP_AHB_BRIDGE_0, 2ch */
- u32 gizmo_xbar_apb_ctlr; /* _GIZMO_XBAR_APB_CTLR_0, 30h */
- u32 gizmo_vcp_ahb_bridge; /* _GIZMO_VCP_AHB_BRIDGE_0, 34h */
- u32 reserved13[2]; /* 38h, 3ch */
- u32 gizmo_nand; /* _GIZMO_NAND_0, 40h */
- u32 reserved15; /* 44h */
- u32 gizmo_sdmmc4; /* _GIZMO_SDMMC4_0, 48h */
- u32 reserved17; /* 4ch */
- u32 gizmo_se; /* _GIZMO_SE_0, 50h */
- u32 gizmo_tzram; /* _GIZMO_TZRAM_0, 54h */
- u32 reserved20[3]; /* 58h, 5ch, 60h */
- u32 gizmo_bsev; /* _GIZMO_BSEV_0, 64h */
- u32 reserved22[3]; /* 68h, 6ch, 70h */
- u32 gizmo_bsea; /* _GIZMO_BSEA_0, 74h */
- u32 gizmo_nor; /* _GIZMO_NOR_0, 78h */
- u32 gizmo_usb2; /* _GIZMO_USB2_0, 7ch */
- u32 gizmo_usb3; /* _GIZMO_USB3_0, 80h */
- u32 gizmo_sdmmc1; /* _GIZMO_SDMMC1_0, 84h */
- u32 gizmo_sdmmc2; /* _GIZMO_SDMMC2_0, 88h */
- u32 gizmo_sdmmc3; /* _GIZMO_SDMMC3_0, 8ch */
- u32 reserved30[13]; /* 90h ~ c0h */
- u32 ahb_wrq_empty; /* _AHB_WRQ_EMPTY_0, c4h */
- u32 reserved32[5]; /* c8h ~ d8h */
- u32 ahb_mem_prefetch_cfg_x; /* _AHB_MEM_PREFETCH_CFG_X_0, dch */
- u32 arbitration_xbar_ctrl; /* _ARBITRATION_XBAR_CTRL_0, e0h */
- u32 ahb_mem_prefetch_cfg3; /* _AHB_MEM_PREFETCH_CFG3_0, e4h */
- u32 ahb_mem_prefetch_cfg4; /* _AHB_MEM_PREFETCH_CFG3_0, e8h */
- u32 avp_ppcs_rd_coh_status; /* _AVP_PPCS_RD_COH_STATUS_0, ech */
- u32 ahb_mem_prefetch_cfg1; /* _AHB_MEM_PREFETCH_CFG1_0, f0h */
- u32 ahb_mem_prefetch_cfg2; /* _AHB_MEM_PREFETCH_CFG2_0, f4h */
- u32 ahbslvmem_status; /* _AHBSLVMEM_STATUS_0, f8h */
- /* _ARBITRATION_AHB_MEM_WRQUE_MST_ID_0, fch */
- u32 arbitration_ahb_mem_wrque_mst_id;
- u32 arbitration_cpu_abort_addr; /* _ARBITRATION_CPU_ABORT_ADDR_0,100h */
- u32 arbitration_cpu_abort_info; /* _ARBITRATION_CPU_ABORT_INFO_0,104h */
- u32 arbitration_cop_abort_addr; /* _ARBITRATION_COP_ABORT_ADDR_0,108h */
- u32 arbitration_cop_abort_info; /* _ARBITRATION_COP_ABORT_INFO_0,10ch */
- u32 reserved46[4]; /* 110h ~ 11ch */
- u32 avpc_mccif_fifoctrl; /* _AVPC_MCCIF_FIFOCTRL_0, 120h */
- u32 timeout_wcoal_avpc; /* _TIMEOUT_WCOAL_AVPC_0, 124h */
- u32 mpcorelp_mccif_fifoctrl; /* _MPCORELP_MCCIF_FIFOCTRL_0, 128h */
- u32 mpcore_mccif_fifoctrl; /* _MPCORE_MCCIF_FIFOCTRL_0, 12ch */
- u32 axicif_fastsync_ctrl; /* AXICIF_FASTSYNC_CTRL_0, 130h */
- u32 axicif_fastsync_statistics; /* _AXICIF_FASTSYNC_STATISTICS_0,134h */
- /* _AXICIF_FASTSYNC0_CPUCLK_TO_MCCLK_0, 138h */
- u32 axicif_fastsync0_cpuclk_to_mcclk;
- /* _AXICIF_FASTSYNC1_CPUCLK_TO_MCCLK_0, 13ch */
- u32 axicif_fastsync1_cpuclk_to_mcclk;
- /* _AXICIF_FASTSYNC2_CPUCLK_TO_MCCLK_0, 140h */
- u32 axicif_fastsync2_cpuclk_to_mcclk;
- /* _AXICIF_FASTSYNC0_MCCLK_TO_CPUCLK_0, 144h */
- u32 axicif_fastsync0_mcclk_to_cpuclk;
- /* _AXICIF_FASTSYNC1_MCCLK_TO_CPUCLK_0, 148h */
- u32 axicif_fastsync1_mcclk_to_cpuclk;
- /* _AXICIF_FASTSYNC2_MCCLK_TO_CPUCLK_0, 14ch */
- u32 axicif_fastsync2_mcclk_to_cpuclk;
-};
-
-#define PPSB_STOPCLK_ENABLE (1 << 2)
-
-#define GIZ_ENABLE_SPLIT (1 << 0)
-#define GIZ_ENB_FAST_REARB (1 << 2)
-#define GIZ_DONT_SPLIT_AHB_WR (1 << 7)
-
-#define GIZ_USB_IMMEDIATE (1 << 18)
-
-/* AHB_ARBITRATION_XBAR_CTRL_0 0xe0 */
-#define ARBITRATION_XBAR_CTRL_PPSB_ENABLE (1 << 2)
-
-#endif /* _TEGRA210_AHB_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/clock-tables.h b/arch/arm/include/asm/arch-tegra210/clock-tables.h
deleted file mode 100644
index c6d7487..0000000
--- a/arch/arm/include/asm/arch-tegra210/clock-tables.h
+++ /dev/null
@@ -1,567 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-/* Tegra210 clock PLL tables */
-
-#ifndef _TEGRA210_CLOCK_TABLES_H_
-#define _TEGRA210_CLOCK_TABLES_H_
-
-/* The PLLs supported by the hardware */
-enum clock_id {
- CLOCK_ID_FIRST,
- CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
- CLOCK_ID_MEMORY,
- CLOCK_ID_PERIPH,
- CLOCK_ID_AUDIO,
- CLOCK_ID_USB,
- CLOCK_ID_DISPLAY,
-
- /* now the simple ones */
- CLOCK_ID_FIRST_SIMPLE,
- CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
- CLOCK_ID_EPCI,
- CLOCK_ID_SFROM32KHZ,
- CLOCK_ID_DP,
-
- /* These are the base clocks (inputs to the Tegra SoC) */
- CLOCK_ID_32KHZ,
- CLOCK_ID_OSC,
- CLOCK_ID_CLK_M,
-
- CLOCK_ID_COUNT, /* number of PLLs */
-
- /*
- * These are clock IDs that are used in table clock_source[][]
- * but will not be assigned as a clock source for any peripheral.
- */
- CLOCK_ID_DISPLAY2,
- CLOCK_ID_CGENERAL_0,
- CLOCK_ID_CGENERAL_1,
- CLOCK_ID_CGENERAL2,
- CLOCK_ID_CGENERAL3,
- CLOCK_ID_CGENERAL4_0,
- CLOCK_ID_CGENERAL4_1,
- CLOCK_ID_CGENERAL4_2,
- CLOCK_ID_MEMORY2,
- CLOCK_ID_SRC2,
-
- CLOCK_ID_NONE = -1,
-};
-
-/* The clocks supported by the hardware */
-enum periph_id {
- PERIPH_ID_FIRST,
-
- /* Low word: 31:0 (DEVICES_L) */
- PERIPH_ID_CPU = PERIPH_ID_FIRST,
- PERIPH_ID_COP,
- PERIPH_ID_TRIGSYS,
- PERIPH_ID_ISPB,
- PERIPH_ID_RESERVED4,
- PERIPH_ID_TMR,
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
-
- /* 8 */
- PERIPH_ID_GPIO,
- PERIPH_ID_SDMMC2,
- PERIPH_ID_SPDIF,
- PERIPH_ID_I2S2,
- PERIPH_ID_I2C1,
- PERIPH_ID_RESERVED13,
- PERIPH_ID_SDMMC1,
- PERIPH_ID_SDMMC4,
-
- /* 16 */
- PERIPH_ID_TCW,
- PERIPH_ID_PWM,
- PERIPH_ID_I2S3,
- PERIPH_ID_RESERVED19,
- PERIPH_ID_VI,
- PERIPH_ID_RESERVED21,
- PERIPH_ID_USBD,
- PERIPH_ID_ISP,
-
- /* 24 */
- PERIPH_ID_RESERVED24,
- PERIPH_ID_RESERVED25,
- PERIPH_ID_DISP2,
- PERIPH_ID_DISP1,
- PERIPH_ID_HOST1X,
- PERIPH_ID_VCP,
- PERIPH_ID_I2S1,
- PERIPH_ID_CACHE2,
-
- /* Middle word: 63:32 (DEVICES_H) */
- PERIPH_ID_MEM,
- PERIPH_ID_AHBDMA,
- PERIPH_ID_APBDMA,
- PERIPH_ID_RESERVED35,
- PERIPH_ID_RESERVED36,
- PERIPH_ID_STAT_MON,
- PERIPH_ID_RESERVED38,
- PERIPH_ID_FUSE,
-
- /* 40 */
- PERIPH_ID_KFUSE,
- PERIPH_ID_SBC1,
- PERIPH_ID_SNOR,
- PERIPH_ID_RESERVED43,
- PERIPH_ID_SBC2,
- PERIPH_ID_XIO,
- PERIPH_ID_SBC3,
- PERIPH_ID_I2C5,
-
- /* 48 */
- PERIPH_ID_DSI,
- PERIPH_ID_RESERVED49,
- PERIPH_ID_HSI,
- PERIPH_ID_HDMI,
- PERIPH_ID_CSI,
- PERIPH_ID_RESERVED53,
- PERIPH_ID_I2C2,
- PERIPH_ID_UART3,
-
- /* 56 */
- PERIPH_ID_MIPI_CAL,
- PERIPH_ID_EMC,
- PERIPH_ID_USB2,
- PERIPH_ID_USB3,
- PERIPH_ID_RESERVED60,
- PERIPH_ID_VDE,
- PERIPH_ID_BSEA,
- PERIPH_ID_BSEV,
-
- /* Upper word 95:64 (DEVICES_U) */
- PERIPH_ID_RESERVED64,
- PERIPH_ID_UART4,
- PERIPH_ID_UART5,
- PERIPH_ID_I2C3,
- PERIPH_ID_SBC4,
- PERIPH_ID_SDMMC3,
- PERIPH_ID_PCIE,
- PERIPH_ID_OWR,
-
- /* 72 */
- PERIPH_ID_AFI,
- PERIPH_ID_CORESIGHT,
- PERIPH_ID_PCIEXCLK,
- PERIPH_ID_AVPUCQ,
- PERIPH_ID_LA,
- PERIPH_ID_TRACECLKIN,
- PERIPH_ID_SOC_THERM,
- PERIPH_ID_DTV,
-
- /* 80 */
- PERIPH_ID_RESERVED80,
- PERIPH_ID_I2CSLOW,
- PERIPH_ID_DSIB,
- PERIPH_ID_TSEC,
- PERIPH_ID_RESERVED84,
- PERIPH_ID_RESERVED85,
- PERIPH_ID_RESERVED86,
- PERIPH_ID_EMUCIF,
-
- /* 88 */
- PERIPH_ID_RESERVED88,
- PERIPH_ID_XUSB_HOST,
- PERIPH_ID_RESERVED90,
- PERIPH_ID_MSENC,
- PERIPH_ID_RESERVED92,
- PERIPH_ID_RESERVED93,
- PERIPH_ID_RESERVED94,
- PERIPH_ID_XUSB_DEV,
-
- PERIPH_ID_VW_FIRST,
- /* V word: 31:0 */
- PERIPH_ID_CPUG = PERIPH_ID_VW_FIRST,
- PERIPH_ID_CPULP,
- PERIPH_ID_V_RESERVED2,
- PERIPH_ID_MSELECT,
- PERIPH_ID_V_RESERVED4,
- PERIPH_ID_I2S4,
- PERIPH_ID_I2S5,
- PERIPH_ID_I2C4,
-
- /* 104 */
- PERIPH_ID_SBC5,
- PERIPH_ID_SBC6,
- PERIPH_ID_AHUB,
- PERIPH_ID_APB2APE,
- PERIPH_ID_V_RESERVED12,
- PERIPH_ID_V_RESERVED13,
- PERIPH_ID_V_RESERVED14,
- PERIPH_ID_HDA2CODEC2X,
-
- /* 112 */
- PERIPH_ID_ATOMICS,
- PERIPH_ID_V_RESERVED17,
- PERIPH_ID_V_RESERVED18,
- PERIPH_ID_V_RESERVED19,
- PERIPH_ID_V_RESERVED20,
- PERIPH_ID_V_RESERVED21,
- PERIPH_ID_V_RESERVED22,
- PERIPH_ID_ACTMON,
-
- /* 120 */
- PERIPH_ID_EXTPERIPH1,
- PERIPH_ID_EXTPERIPH2,
- PERIPH_ID_EXTPERIPH3,
- PERIPH_ID_OOB,
- PERIPH_ID_SATA,
- PERIPH_ID_HDA,
- PERIPH_ID_V_RESERVED30,
- PERIPH_ID_V_RESERVED31,
-
- /* W word: 31:0 */
- PERIPH_ID_HDA2HDMICODEC,
- PERIPH_ID_SATACOLD,
- PERIPH_ID_W_RESERVED2,
- PERIPH_ID_W_RESERVED3,
- PERIPH_ID_W_RESERVED4,
- PERIPH_ID_W_RESERVED5,
- PERIPH_ID_W_RESERVED6,
- PERIPH_ID_W_RESERVED7,
-
- /* 136 */
- PERIPH_ID_CEC,
- PERIPH_ID_W_RESERVED9,
- PERIPH_ID_W_RESERVED10,
- PERIPH_ID_W_RESERVED11,
- PERIPH_ID_W_RESERVED12,
- PERIPH_ID_W_RESERVED13,
- PERIPH_ID_XUSB_PADCTL,
- PERIPH_ID_W_RESERVED15,
-
- /* 144 */
- PERIPH_ID_W_RESERVED16,
- PERIPH_ID_W_RESERVED17,
- PERIPH_ID_W_RESERVED18,
- PERIPH_ID_W_RESERVED19,
- PERIPH_ID_W_RESERVED20,
- PERIPH_ID_ENTROPY,
- PERIPH_ID_DDS,
- PERIPH_ID_W_RESERVED23,
-
- /* 152 */
- PERIPH_ID_W_RESERVED24,
- PERIPH_ID_W_RESERVED25,
- PERIPH_ID_W_RESERVED26,
- PERIPH_ID_DVFS,
- PERIPH_ID_XUSB_SS,
- PERIPH_ID_W_RESERVED29,
- PERIPH_ID_W_RESERVED30,
- PERIPH_ID_W_RESERVED31,
-
- PERIPH_ID_X_FIRST,
- /* X word: 31:0 */
- PERIPH_ID_SPARE = PERIPH_ID_X_FIRST,
- PERIPH_ID_X_RESERVED1,
- PERIPH_ID_X_RESERVED2,
- PERIPH_ID_X_RESERVED3,
- PERIPH_ID_CAM_MCLK,
- PERIPH_ID_CAM_MCLK2,
- PERIPH_ID_I2C6,
- PERIPH_ID_X_RESERVED7,
-
- /* 168 */
- PERIPH_ID_X_RESERVED8,
- PERIPH_ID_X_RESERVED9,
- PERIPH_ID_X_RESERVED10,
- PERIPH_ID_VIM2_CLK,
- PERIPH_ID_X_RESERVED12,
- PERIPH_ID_X_RESERVED13,
- PERIPH_ID_EMC_DLL,
- PERIPH_ID_X_RESERVED15,
-
- /* 176 */
- PERIPH_ID_HDMI_AUDIO,
- PERIPH_ID_CLK72MHZ,
- PERIPH_ID_VIC,
- PERIPH_ID_X_RESERVED19,
- PERIPH_ID_X_RESERVED20,
- PERIPH_ID_DPAUX,
- PERIPH_ID_SOR0,
- PERIPH_ID_X_RESERVED23,
-
- /* 184 */
- PERIPH_ID_GPU,
- PERIPH_ID_X_RESERVED25,
- PERIPH_ID_X_RESERVED26,
- PERIPH_ID_X_RESERVED27,
- PERIPH_ID_X_RESERVED28,
- PERIPH_ID_X_RESERVED29,
- PERIPH_ID_X_RESERVED30,
- PERIPH_ID_X_RESERVED31,
-
- PERIPH_ID_Y_FIRST,
- /* Y word: 31:0 (192:223) */
- PERIPH_ID_SPARE1 = PERIPH_ID_Y_FIRST,
- PERIPH_ID_Y_RESERVED1,
- PERIPH_ID_Y_RESERVED2,
- PERIPH_ID_Y_RESERVED3,
- PERIPH_ID_Y_RESERVED4,
- PERIPH_ID_Y_RESERVED5,
- PERIPH_ID_APE,
- PERIPH_ID_Y_RESERVED7,
-
- /* 200 */
- PERIPH_ID_MC_CDPA,
- PERIPH_ID_Y_RESERVED9,
- PERIPH_ID_Y_RESERVED10,
- PERIPH_ID_Y_RESERVED11,
- PERIPH_ID_Y_RESERVED12,
- PERIPH_ID_PEX_USB_UPHY,
- PERIPH_ID_Y_RESERVED14,
- PERIPH_ID_Y_RESERVED15,
-
- /* 208 */
- PERIPH_ID_VI_I2C,
- PERIPH_ID_Y_RESERVED17,
- PERIPH_ID_Y_RESERVED18,
- PERIPH_ID_QSPI,
- PERIPH_ID_Y_RESERVED20,
- PERIPH_ID_Y_RESERVED21,
- PERIPH_ID_Y_RESERVED22,
- PERIPH_ID_Y_RESERVED23,
-
- /* 216 */
- PERIPH_ID_Y_RESERVED24,
- PERIPH_ID_Y_RESERVED25,
- PERIPH_ID_Y_RESERVED26,
- PERIPH_ID_Y_RESERVED27,
- PERIPH_ID_Y_RESERVED28,
- PERIPH_ID_Y_RESERVED29,
- PERIPH_ID_Y_RESERVED30,
- PERIPH_ID_Y_RESERVED31,
-
- PERIPH_ID_COUNT,
- PERIPH_ID_NONE = -1,
-};
-
-enum pll_out_id {
- PLL_OUT1,
- PLL_OUT2,
- PLL_OUT3,
- PLL_OUT4
-};
-
-/*
- * Clock peripheral IDs which sadly don't match up with PERIPH_ID. we want
- * callers to use the PERIPH_ID for all access to peripheral clocks to avoid
- * confusion bewteen PERIPH_ID_... and PERIPHC_...
- *
- * We don't call this CLOCK_PERIPH_ID or PERIPH_CLOCK_ID as it would just be
- * confusing.
- */
-enum periphc_internal_id {
- /* 0x00 */
- PERIPHC_I2S2,
- PERIPHC_I2S3,
- PERIPHC_SPDIF_OUT,
- PERIPHC_SPDIF_IN,
- PERIPHC_PWM,
- PERIPHC_05h,
- PERIPHC_SBC2,
- PERIPHC_SBC3,
-
- /* 0x08 */
- PERIPHC_08h,
- PERIPHC_I2C1,
- PERIPHC_I2C5,
- PERIPHC_0bh,
- PERIPHC_0ch,
- PERIPHC_SBC1,
- PERIPHC_DISP1,
- PERIPHC_DISP2,
-
- /* 0x10 */
- PERIPHC_10h,
- PERIPHC_11h,
- PERIPHC_VI,
- PERIPHC_13h,
- PERIPHC_SDMMC1,
- PERIPHC_SDMMC2,
- PERIPHC_G3D,
- PERIPHC_G2D,
-
- /* 0x18 */
- PERIPHC_18h,
- PERIPHC_SDMMC4,
- PERIPHC_VFIR,
- PERIPHC_1Bh,
- PERIPHC_1Ch,
- PERIPHC_HSI,
- PERIPHC_UART1,
- PERIPHC_UART2,
-
- /* 0x20 */
- PERIPHC_HOST1X,
- PERIPHC_21h,
- PERIPHC_22h,
- PERIPHC_HDMI,
- PERIPHC_24h,
- PERIPHC_25h,
- PERIPHC_I2C2,
- PERIPHC_EMC,
-
- /* 0x28 */
- PERIPHC_UART3,
- PERIPHC_29h,
- PERIPHC_VI_SENSOR,
- PERIPHC_2bh,
- PERIPHC_2ch,
- PERIPHC_SBC4,
- PERIPHC_I2C3,
- PERIPHC_SDMMC3,
-
- /* 0x30 */
- PERIPHC_UART4,
- PERIPHC_UART5,
- PERIPHC_VDE,
- PERIPHC_OWR,
- PERIPHC_NOR,
- PERIPHC_CSITE,
- PERIPHC_I2S1,
- PERIPHC_DTV,
-
- /* 0x38 */
- PERIPHC_38h,
- PERIPHC_39h,
- PERIPHC_3ah,
- PERIPHC_3bh,
- PERIPHC_MSENC,
- PERIPHC_TSEC,
- PERIPHC_3eh,
- PERIPHC_OSC,
-
- PERIPHC_VW_FIRST,
- /* 0x40 */
- PERIPHC_40h = PERIPHC_VW_FIRST,
- PERIPHC_MSELECT,
- PERIPHC_TSENSOR,
- PERIPHC_I2S4,
- PERIPHC_I2S5,
- PERIPHC_I2C4,
- PERIPHC_SBC5,
- PERIPHC_SBC6,
-
- /* 0x48 */
- PERIPHC_AUDIO,
- PERIPHC_49h,
- PERIPHC_4ah,
- PERIPHC_4bh,
- PERIPHC_4ch,
- PERIPHC_HDA2CODEC2X,
- PERIPHC_ACTMON,
- PERIPHC_EXTPERIPH1,
-
- /* 0x50 */
- PERIPHC_EXTPERIPH2,
- PERIPHC_EXTPERIPH3,
- PERIPHC_52h,
- PERIPHC_I2CSLOW,
- PERIPHC_SYS,
- PERIPHC_55h,
- PERIPHC_56h,
- PERIPHC_57h,
-
- /* 0x58 */
- PERIPHC_58h,
- PERIPHC_59h,
- PERIPHC_5ah,
- PERIPHC_5bh,
- PERIPHC_SATAOOB,
- PERIPHC_SATA,
- PERIPHC_HDA, /* 0x428 */
- PERIPHC_5fh,
-
- PERIPHC_X_FIRST,
- /* 0x60 */
- PERIPHC_XUSB_CORE_HOST = PERIPHC_X_FIRST, /* 0x600 */
- PERIPHC_XUSB_FALCON,
- PERIPHC_XUSB_FS,
- PERIPHC_XUSB_CORE_DEV,
- PERIPHC_XUSB_SS,
- PERIPHC_CILAB,
- PERIPHC_CILCD,
- PERIPHC_CILE,
-
- /* 0x68 */
- PERIPHC_DSIA_LP,
- PERIPHC_DSIB_LP,
- PERIPHC_ENTROPY,
- PERIPHC_DVFS_REF,
- PERIPHC_DVFS_SOC,
- PERIPHC_TRACECLKIN,
- PERIPHC_6Eh,
- PERIPHC_6Fh,
-
- /* 0x70 */
- PERIPHC_EMC_LATENCY,
- PERIPHC_SOC_THERM,
- PERIPHC_72h,
- PERIPHC_73h,
- PERIPHC_74h,
- PERIPHC_75h,
- PERIPHC_VI_SENSOR2,
- PERIPHC_I2C6,
-
- /* 0x78 */
- PERIPHC_78h,
- PERIPHC_EMC_DLL,
- PERIPHC_7ah,
- PERIPHC_CLK72MHZ,
- PERIPHC_7ch,
- PERIPHC_7dh,
- PERIPHC_VIC,
- PERIPHC_7fh,
-
- PERIPHC_Y_FIRST,
- /* 0x80 */
- PERIPHC_SDMMC_LEGACY_TM = PERIPHC_Y_FIRST, /* 0x694 */
- PERIPHC_NVDEC, /* 0x698 */
- PERIPHC_NVJPG, /* 0x69c */
- PERIPHC_NVENC, /* 0x6a0 */
- PERIPHC_84h,
- PERIPHC_85h,
- PERIPHC_86h,
- PERIPHC_87h,
-
- /* 0x88 */
- PERIPHC_88h,
- PERIPHC_89h,
- PERIPHC_DMIC3, /* 0x6bc: */
- PERIPHC_APE, /* 0x6c0: */
- PERIPHC_QSPI, /* 0x6c4: */
- PERIPHC_VI_I2C, /* 0x6c8: */
- PERIPHC_USB2_HSIC_TRK, /* 0x6cc: */
- PERIPHC_PEX_SATA_USB_RX_BYP, /* 0x6d0: */
-
- /* 0x90 */
- PERIPHC_MAUD, /* 0x6d4: */
- PERIPHC_TSECB, /* 0x6d8: */
-
- PERIPHC_COUNT,
- PERIPHC_NONE = -1,
-};
-
-/* Converts a clock number to a clock register: 0=L, 1=H, 2=U, 0=V, 1=W */
-#define PERIPH_REG(id) \
- (id < PERIPH_ID_VW_FIRST) ? \
- ((id) >> 5) : ((id - PERIPH_ID_VW_FIRST) >> 5)
-
-/* Mask value for a clock (within PERIPH_REG(id)) */
-#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
-
-/* return 1 if a PLL ID is in range */
-#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && (id) < CLOCK_ID_COUNT)
-
-/* return 1 if a peripheral ID is in range */
-#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
- (id) < PERIPH_ID_COUNT)
-
-#endif /* _TEGRA210_CLOCK_TABLES_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/clock.h b/arch/arm/include/asm/arch-tegra210/clock.h
deleted file mode 100644
index 438a6f4..0000000
--- a/arch/arm/include/asm/arch-tegra210/clock.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-/* Tegra210 clock control definitions */
-
-#ifndef _TEGRA210_CLOCK_H_
-#define _TEGRA210_CLOCK_H_
-
-#include <asm/arch-tegra/clock.h>
-
-/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
-#define OSC_FREQ_SHIFT 28
-#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
-
-/* PLL bits that differ from generic clk_rst.h */
-#define PLLC_RESET 30
-#define PLLC_IDDQ 27
-#define PLLD_ENABLE_CLK 21
-#define PLLD_EN_LCKDET 28
-
-int tegra_plle_enable(void);
-
-#endif /* _TEGRA210_CLOCK_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/flow.h b/arch/arm/include/asm/arch-tegra210/flow.h
deleted file mode 100644
index ef0be19..0000000
--- a/arch/arm/include/asm/arch-tegra210/flow.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA210_FLOW_H_
-#define _TEGRA210_FLOW_H_
-
-struct flow_ctlr {
- u32 halt_cpu_events; /* offset 0x00 */
- u32 halt_cop_events; /* offset 0x04 */
- u32 cpu_csr; /* offset 0x08 */
- u32 cop_csr; /* offset 0x0c */
- u32 xrq_events; /* offset 0x10 */
- u32 halt_cpu1_events; /* offset 0x14 */
- u32 cpu1_csr; /* offset 0x18 */
- u32 halt_cpu2_events; /* offset 0x1c */
- u32 cpu2_csr; /* offset 0x20 */
- u32 halt_cpu3_events; /* offset 0x24 */
- u32 cpu3_csr; /* offset 0x28 */
- u32 cluster_control; /* offset 0x2c */
- u32 halt_cop1_events; /* offset 0x30 */
- u32 halt_cop1_csr; /* offset 0x34 */
- u32 cpu_pwr_csr; /* offset 0x38 */
- u32 mpid; /* offset 0x3c */
- u32 ram_repair; /* offset 0x40 */
-};
-
-/* HALT_COP_EVENTS_0, 0x04 */
-#define EVENT_MSEC (1 << 24)
-#define EVENT_USEC (1 << 25)
-#define EVENT_JTAG (1 << 28)
-#define EVENT_MODE_STOP (2 << 29)
-
-/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */
-#define ACTIVE_LP (1 << 0)
-
-/* CPUn_CSR_0 */
-#define CSR_ENABLE (1 << 0)
-#define CSR_IMMEDIATE_WAKE (1 << 3)
-#define CSR_WAIT_WFI_SHIFT 8
-
-#endif /* _TEGRA210_FLOW_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/funcmux.h b/arch/arm/include/asm/arch-tegra210/funcmux.h
deleted file mode 100644
index f6270e5..0000000
--- a/arch/arm/include/asm/arch-tegra210/funcmux.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-/* Tegra210 high-level function multiplexing */
-
-#ifndef _TEGRA210_FUNCMUX_H_
-#define _TEGRA210_FUNCMUX_H_
-
-#include <asm/arch-tegra/funcmux.h>
-
-/* Configs supported by the func mux */
-enum {
- FUNCMUX_DEFAULT = 0, /* default config */
-
- /* UART configs */
- FUNCMUX_UART1_UART1 = 0,
- FUNCMUX_UART4_UART4 = 0,
-};
-#endif /* _TEGRA210_FUNCMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h b/arch/arm/include/asm/arch-tegra210/gp_padctrl.h
deleted file mode 100644
index e9ff903..0000000
--- a/arch/arm/include/asm/arch-tegra210/gp_padctrl.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA210_GP_PADCTRL_H_
-#define _TEGRA210_GP_PADCTRL_H_
-
-#include <asm/arch-tegra/gp_padctrl.h>
-
-/* APB_MISC_GP and padctrl registers */
-struct apb_misc_gp_ctlr {
- u32 modereg; /* 0x00: APB_MISC_GP_MODEREG */
- u32 hidrev; /* 0x04: APB_MISC_GP_HIDREV */
- u32 reserved0[22]; /* 0x08 - 0x5C: */
- u32 emu_revid; /* 0x60: APB_MISC_GP_EMU_REVID */
- u32 xactor_scratch; /* 0x64: APB_MISC_GP_XACTOR_SCRATCH */
- u32 aocfg1; /* 0x68: APB_MISC_GP_AOCFG1PADCTRL */
- u32 aocfg2; /* 0x6C: APB_MISC_GP_AOCFG2PADCTRL */
- u32 atcfg1; /* 0x70: APB_MISC_GP_ATCFG1PADCTRL */
- u32 atcfg2; /* 0x74: APB_MISC_GP_ATCFG2PADCTRL */
- u32 atcfg3; /* 0x78: APB_MISC_GP_ATCFG3PADCTRL */
- u32 atcfg4; /* 0x7C: APB_MISC_GP_ATCFG4PADCTRL */
- u32 atcfg5; /* 0x80: APB_MISC_GP_ATCFG5PADCTRL */
- u32 cdev1cfg; /* 0x84: APB_MISC_GP_CDEV1CFGPADCTRL */
- u32 cdev2cfg; /* 0x88: APB_MISC_GP_CDEV2CFGPADCTRL */
- u32 reserved1; /* 0x8C: */
- u32 dap1cfg; /* 0x90: APB_MISC_GP_DAP1CFGPADCTRL */
- u32 dap2cfg; /* 0x94: APB_MISC_GP_DAP2CFGPADCTRL */
- u32 dap3cfg; /* 0x98: APB_MISC_GP_DAP3CFGPADCTRL */
- u32 dap4cfg; /* 0x9C: APB_MISC_GP_DAP4CFGPADCTRL */
- u32 dbgcfg; /* 0xA0: APB_MISC_GP_DBGCFGPADCTRL */
- u32 reserved2[3]; /* 0xA4 - 0xAC: */
- u32 sdio3cfg; /* 0xB0: APB_MISC_GP_SDIO3CFGPADCTRL */
- u32 spicfg; /* 0xB4: APB_MISC_GP_SPICFGPADCTRL */
- u32 uaacfg; /* 0xB8: APB_MISC_GP_UAACFGPADCTRL */
- u32 uabcfg; /* 0xBC: APB_MISC_GP_UABCFGPADCTRL */
- u32 uart2cfg; /* 0xC0: APB_MISC_GP_UART2CFGPADCTRL */
- u32 uart3cfg; /* 0xC4: APB_MISC_GP_UART3CFGPADCTRL */
- u32 reserved3[9]; /* 0xC8-0xE8: */
- u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
- u32 reserved4[3]; /* 0xF0-0xF8: */
- u32 ddccfg; /* 0xFC: APB_MISC_GP_DDCCFGPADCTRL */
- u32 gmacfg; /* 0x100: APB_MISC_GP_GMACFGPADCTRL */
- u32 reserved5[3]; /* 0x104-0x10C: */
- u32 gmecfg; /* 0x110: APB_MISC_GP_GMECFGPADCTRL */
- u32 gmfcfg; /* 0x114: APB_MISC_GP_GMFCFGPADCTRL */
- u32 gmgcfg; /* 0x118: APB_MISC_GP_GMGCFGPADCTRL */
- u32 gmhcfg; /* 0x11C: APB_MISC_GP_GMHCFGPADCTRL */
- u32 owrcfg; /* 0x120: APB_MISC_GP_OWRCFGPADCTRL */
- u32 uadcfg; /* 0x124: APB_MISC_GP_UADCFGPADCTRL */
- u32 reserved6; /* 0x128: */
- u32 dev3cfg; /* 0x12C: APB_MISC_GP_DEV3CFGPADCTRL */
- u32 reserved7[2]; /* 0x130 - 0x134: */
- u32 ceccfg; /* 0x138: APB_MISC_GP_CECCFGPADCTRL */
- u32 reserved8[22]; /* 0x13C - 0x190: */
- u32 atcfg6; /* 0x194: APB_MISC_GP_ATCFG6PADCTRL */
- u32 dap5cfg; /* 0x198: APB_MISC_GP_DAP5CFGPADCTRL */
- u32 vbuscfg; /* 0x19C: APB_MISC_GP_USBVBUSENCFGPADCTRL */
- u32 aocfg3; /* 0x1A0: APB_MISC_GP_AOCFG3PADCTRL */
- u32 hvccfg0; /* 0x1A4: APB_MISC_GP_HVCCFG0PADCTRL */
- u32 sdio4cfg; /* 0x1A8: APB_MISC_GP_SDIO4CFGPADCTRL */
- u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
-};
-
-/* SDMMC1/3 settings from section 27.5 of T114 TRM */
-#define SDIOCFG_DRVUP_SLWF 0
-#define SDIOCFG_DRVDN_SLWR 0
-#define SDIOCFG_DRVUP 0x24
-#define SDIOCFG_DRVDN 0x14
-
-#endif /* _TEGRA210_GP_PADCTRL_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/gpio.h b/arch/arm/include/asm/arch-tegra210/gpio.h
deleted file mode 100644
index cb91b10..0000000
--- a/arch/arm/include/asm/arch-tegra210/gpio.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA210_GPIO_H_
-#define _TEGRA210_GPIO_H_
-
-/*
- * The Tegra210 GPIO controller has 256 GPIOS in 8 banks of 4 ports,
- * each with 8 GPIOs.
- */
-#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
-#define TEGRA_GPIO_BANKS 8 /* number of banks */
-
-#include <asm/arch-tegra/gpio.h>
-
-/* GPIO Controller registers for a single bank */
-struct gpio_ctlr_bank {
- uint gpio_config[TEGRA_GPIO_PORTS];
- uint gpio_dir_out[TEGRA_GPIO_PORTS];
- uint gpio_out[TEGRA_GPIO_PORTS];
- uint gpio_in[TEGRA_GPIO_PORTS];
- uint gpio_int_status[TEGRA_GPIO_PORTS];
- uint gpio_int_enable[TEGRA_GPIO_PORTS];
- uint gpio_int_level[TEGRA_GPIO_PORTS];
- uint gpio_int_clear[TEGRA_GPIO_PORTS];
- uint gpio_masked_config[TEGRA_GPIO_PORTS];
- uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
- uint gpio_masked_out[TEGRA_GPIO_PORTS];
- uint gpio_masked_in[TEGRA_GPIO_PORTS];
- uint gpio_masked_int_status[TEGRA_GPIO_PORTS];
- uint gpio_masked_int_enable[TEGRA_GPIO_PORTS];
- uint gpio_masked_int_level[TEGRA_GPIO_PORTS];
- uint gpio_masked_int_clear[TEGRA_GPIO_PORTS];
-};
-
-struct gpio_ctlr {
- struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
-};
-
-#endif /* _TEGRA210_GPIO_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/mc.h b/arch/arm/include/asm/arch-tegra210/mc.h
deleted file mode 100644
index 5a2a568..0000000
--- a/arch/arm/include/asm/arch-tegra210/mc.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA210_MC_H_
-#define _TEGRA210_MC_H_
-
-/**
- * Defines the memory controller registers we need/care about
- */
-struct mc_ctlr {
- u32 reserved0[4]; /* offset 0x00 - 0x0C */
- u32 mc_smmu_config; /* offset 0x10 */
- u32 mc_smmu_tlb_config; /* offset 0x14 */
- u32 mc_smmu_ptc_config; /* offset 0x18 */
- u32 mc_smmu_ptb_asid; /* offset 0x1C */
- u32 mc_smmu_ptb_data; /* offset 0x20 */
- u32 reserved1[3]; /* offset 0x24 - 0x2C */
- u32 mc_smmu_tlb_flush; /* offset 0x30 */
- u32 mc_smmu_ptc_flush; /* offset 0x34 */
- u32 reserved2[6]; /* offset 0x38 - 0x4C */
- u32 mc_emem_cfg; /* offset 0x50 */
- u32 mc_emem_adr_cfg; /* offset 0x54 */
- u32 mc_emem_adr_cfg_dev0; /* offset 0x58 */
- u32 mc_emem_adr_cfg_dev1; /* offset 0x5C */
- u32 reserved3[4]; /* offset 0x60 - 0x6C */
- u32 mc_security_cfg0; /* offset 0x70 */
- u32 mc_security_cfg1; /* offset 0x74 */
- u32 reserved4[6]; /* offset 0x7C - 0x8C */
- u32 mc_emem_arb_reserved[28]; /* offset 0x90 - 0xFC */
- u32 reserved5[74]; /* offset 0x100 - 0x224 */
- u32 mc_smmu_translation_enable_0; /* offset 0x228 */
- u32 mc_smmu_translation_enable_1; /* offset 0x22C */
- u32 mc_smmu_translation_enable_2; /* offset 0x230 */
- u32 mc_smmu_translation_enable_3; /* offset 0x234 */
- u32 mc_smmu_afi_asid; /* offset 0x238 */
- u32 mc_smmu_avpc_asid; /* offset 0x23C */
- u32 mc_smmu_dc_asid; /* offset 0x240 */
- u32 mc_smmu_dcb_asid; /* offset 0x244 */
- u32 reserved6[2]; /* offset 0x248 - 0x24C */
- u32 mc_smmu_hc_asid; /* offset 0x250 */
- u32 mc_smmu_hda_asid; /* offset 0x254 */
- u32 mc_smmu_isp2_asid; /* offset 0x258 */
- u32 reserved7[2]; /* offset 0x25C - 0x260 */
- u32 mc_smmu_msenc_asid; /* offset 0x264 */
- u32 mc_smmu_nv_asid; /* offset 0x268 */
- u32 mc_smmu_nv2_asid; /* offset 0x26C */
- u32 mc_smmu_ppcs_asid; /* offset 0x270 */
- u32 mc_smmu_sata_asid; /* offset 0x274 */
- u32 reserved8[1]; /* offset 0x278 */
- u32 mc_smmu_vde_asid; /* offset 0x27C */
- u32 mc_smmu_vi_asid; /* offset 0x280 */
- u32 mc_smmu_vic_asid; /* offset 0x284 */
- u32 mc_smmu_xusb_host_asid; /* offset 0x288 */
- u32 mc_smmu_xusb_dev_asid; /* offset 0x28C */
- u32 reserved9[1]; /* offset 0x290 */
- u32 mc_smmu_tsec_asid; /* offset 0x294 */
- u32 mc_smmu_ppcs1_asid; /* offset 0x298 */
- u32 reserved10[235]; /* offset 0x29C - 0x644 */
- u32 mc_video_protect_bom; /* offset 0x648 */
- u32 mc_video_protect_size_mb; /* offset 0x64c */
- u32 mc_video_protect_reg_ctrl; /* offset 0x650 */
-};
-
-#define TEGRA_MC_SMMU_CONFIG_ENABLE (1 << 0)
-
-#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_ENABLED (0 << 0)
-#define TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED (1 << 0)
-
-#endif /* _TEGRA210_MC_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/pinmux.h b/arch/arm/include/asm/arch-tegra210/pinmux.h
deleted file mode 100644
index 9e94074..0000000
--- a/arch/arm/include/asm/arch-tegra210/pinmux.h
+++ /dev/null
@@ -1,415 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA210_PINMUX_H_
-#define _TEGRA210_PINMUX_H_
-
-enum pmux_pingrp {
- PMUX_PINGRP_SDMMC1_CLK_PM0,
- PMUX_PINGRP_SDMMC1_CMD_PM1,
- PMUX_PINGRP_SDMMC1_DAT3_PM2,
- PMUX_PINGRP_SDMMC1_DAT2_PM3,
- PMUX_PINGRP_SDMMC1_DAT1_PM4,
- PMUX_PINGRP_SDMMC1_DAT0_PM5,
- PMUX_PINGRP_SDMMC3_CLK_PP0 = (0x1c / 4),
- PMUX_PINGRP_SDMMC3_CMD_PP1,
- PMUX_PINGRP_SDMMC3_DAT0_PP5,
- PMUX_PINGRP_SDMMC3_DAT1_PP4,
- PMUX_PINGRP_SDMMC3_DAT2_PP3,
- PMUX_PINGRP_SDMMC3_DAT3_PP2,
- PMUX_PINGRP_PEX_L0_RST_N_PA0 = (0x38 / 4),
- PMUX_PINGRP_PEX_L0_CLKREQ_N_PA1,
- PMUX_PINGRP_PEX_WAKE_N_PA2,
- PMUX_PINGRP_PEX_L1_RST_N_PA3,
- PMUX_PINGRP_PEX_L1_CLKREQ_N_PA4,
- PMUX_PINGRP_SATA_LED_ACTIVE_PA5,
- PMUX_PINGRP_SPI1_MOSI_PC0,
- PMUX_PINGRP_SPI1_MISO_PC1,
- PMUX_PINGRP_SPI1_SCK_PC2,
- PMUX_PINGRP_SPI1_CS0_PC3,
- PMUX_PINGRP_SPI1_CS1_PC4,
- PMUX_PINGRP_SPI2_MOSI_PB4,
- PMUX_PINGRP_SPI2_MISO_PB5,
- PMUX_PINGRP_SPI2_SCK_PB6,
- PMUX_PINGRP_SPI2_CS0_PB7,
- PMUX_PINGRP_SPI2_CS1_PDD0,
- PMUX_PINGRP_SPI4_MOSI_PC7,
- PMUX_PINGRP_SPI4_MISO_PD0,
- PMUX_PINGRP_SPI4_SCK_PC5,
- PMUX_PINGRP_SPI4_CS0_PC6,
- PMUX_PINGRP_QSPI_SCK_PEE0,
- PMUX_PINGRP_QSPI_CS_N_PEE1,
- PMUX_PINGRP_QSPI_IO0_PEE2,
- PMUX_PINGRP_QSPI_IO1_PEE3,
- PMUX_PINGRP_QSPI_IO2_PEE4,
- PMUX_PINGRP_QSPI_IO3_PEE5,
- PMUX_PINGRP_DMIC1_CLK_PE0 = (0xa4 / 4),
- PMUX_PINGRP_DMIC1_DAT_PE1,
- PMUX_PINGRP_DMIC2_CLK_PE2,
- PMUX_PINGRP_DMIC2_DAT_PE3,
- PMUX_PINGRP_DMIC3_CLK_PE4,
- PMUX_PINGRP_DMIC3_DAT_PE5,
- PMUX_PINGRP_GEN1_I2C_SCL_PJ1,
- PMUX_PINGRP_GEN1_I2C_SDA_PJ0,
- PMUX_PINGRP_GEN2_I2C_SCL_PJ2,
- PMUX_PINGRP_GEN2_I2C_SDA_PJ3,
- PMUX_PINGRP_GEN3_I2C_SCL_PF0,
- PMUX_PINGRP_GEN3_I2C_SDA_PF1,
- PMUX_PINGRP_CAM_I2C_SCL_PS2,
- PMUX_PINGRP_CAM_I2C_SDA_PS3,
- PMUX_PINGRP_PWR_I2C_SCL_PY3,
- PMUX_PINGRP_PWR_I2C_SDA_PY4,
- PMUX_PINGRP_UART1_TX_PU0,
- PMUX_PINGRP_UART1_RX_PU1,
- PMUX_PINGRP_UART1_RTS_PU2,
- PMUX_PINGRP_UART1_CTS_PU3,
- PMUX_PINGRP_UART2_TX_PG0,
- PMUX_PINGRP_UART2_RX_PG1,
- PMUX_PINGRP_UART2_RTS_PG2,
- PMUX_PINGRP_UART2_CTS_PG3,
- PMUX_PINGRP_UART3_TX_PD1,
- PMUX_PINGRP_UART3_RX_PD2,
- PMUX_PINGRP_UART3_RTS_PD3,
- PMUX_PINGRP_UART3_CTS_PD4,
- PMUX_PINGRP_UART4_TX_PI4,
- PMUX_PINGRP_UART4_RX_PI5,
- PMUX_PINGRP_UART4_RTS_PI6,
- PMUX_PINGRP_UART4_CTS_PI7,
- PMUX_PINGRP_DAP1_FS_PB0,
- PMUX_PINGRP_DAP1_DIN_PB1,
- PMUX_PINGRP_DAP1_DOUT_PB2,
- PMUX_PINGRP_DAP1_SCLK_PB3,
- PMUX_PINGRP_DAP2_FS_PAA0,
- PMUX_PINGRP_DAP2_DIN_PAA2,
- PMUX_PINGRP_DAP2_DOUT_PAA3,
- PMUX_PINGRP_DAP2_SCLK_PAA1,
- PMUX_PINGRP_DAP4_FS_PJ4,
- PMUX_PINGRP_DAP4_DIN_PJ5,
- PMUX_PINGRP_DAP4_DOUT_PJ6,
- PMUX_PINGRP_DAP4_SCLK_PJ7,
- PMUX_PINGRP_CAM1_MCLK_PS0,
- PMUX_PINGRP_CAM2_MCLK_PS1,
- PMUX_PINGRP_JTAG_RTCK,
- PMUX_PINGRP_CLK_32K_IN,
- PMUX_PINGRP_CLK_32K_OUT_PY5,
- PMUX_PINGRP_BATT_BCL,
- PMUX_PINGRP_CLK_REQ,
- PMUX_PINGRP_CPU_PWR_REQ,
- PMUX_PINGRP_PWR_INT_N,
- PMUX_PINGRP_SHUTDOWN,
- PMUX_PINGRP_CORE_PWR_REQ,
- PMUX_PINGRP_AUD_MCLK_PBB0,
- PMUX_PINGRP_DVFS_PWM_PBB1,
- PMUX_PINGRP_DVFS_CLK_PBB2,
- PMUX_PINGRP_GPIO_X1_AUD_PBB3,
- PMUX_PINGRP_GPIO_X3_AUD_PBB4,
- PMUX_PINGRP_PCC7,
- PMUX_PINGRP_HDMI_CEC_PCC0,
- PMUX_PINGRP_HDMI_INT_DP_HPD_PCC1,
- PMUX_PINGRP_SPDIF_OUT_PCC2,
- PMUX_PINGRP_SPDIF_IN_PCC3,
- PMUX_PINGRP_USB_VBUS_EN0_PCC4,
- PMUX_PINGRP_USB_VBUS_EN1_PCC5,
- PMUX_PINGRP_DP_HPD0_PCC6,
- PMUX_PINGRP_WIFI_EN_PH0,
- PMUX_PINGRP_WIFI_RST_PH1,
- PMUX_PINGRP_WIFI_WAKE_AP_PH2,
- PMUX_PINGRP_AP_WAKE_BT_PH3,
- PMUX_PINGRP_BT_RST_PH4,
- PMUX_PINGRP_BT_WAKE_AP_PH5,
- PMUX_PINGRP_AP_WAKE_NFC_PH7,
- PMUX_PINGRP_NFC_EN_PI0,
- PMUX_PINGRP_NFC_INT_PI1,
- PMUX_PINGRP_GPS_EN_PI2,
- PMUX_PINGRP_GPS_RST_PI3,
- PMUX_PINGRP_CAM_RST_PS4,
- PMUX_PINGRP_CAM_AF_EN_PS5,
- PMUX_PINGRP_CAM_FLASH_EN_PS6,
- PMUX_PINGRP_CAM1_PWDN_PS7,
- PMUX_PINGRP_CAM2_PWDN_PT0,
- PMUX_PINGRP_CAM1_STROBE_PT1,
- PMUX_PINGRP_LCD_TE_PY2,
- PMUX_PINGRP_LCD_BL_PWM_PV0,
- PMUX_PINGRP_LCD_BL_EN_PV1,
- PMUX_PINGRP_LCD_RST_PV2,
- PMUX_PINGRP_LCD_GPIO1_PV3,
- PMUX_PINGRP_LCD_GPIO2_PV4,
- PMUX_PINGRP_AP_READY_PV5,
- PMUX_PINGRP_TOUCH_RST_PV6,
- PMUX_PINGRP_TOUCH_CLK_PV7,
- PMUX_PINGRP_MODEM_WAKE_AP_PX0,
- PMUX_PINGRP_TOUCH_INT_PX1,
- PMUX_PINGRP_MOTION_INT_PX2,
- PMUX_PINGRP_ALS_PROX_INT_PX3,
- PMUX_PINGRP_TEMP_ALERT_PX4,
- PMUX_PINGRP_BUTTON_POWER_ON_PX5,
- PMUX_PINGRP_BUTTON_VOL_UP_PX6,
- PMUX_PINGRP_BUTTON_VOL_DOWN_PX7,
- PMUX_PINGRP_BUTTON_SLIDE_SW_PY0,
- PMUX_PINGRP_BUTTON_HOME_PY1,
- PMUX_PINGRP_PA6,
- PMUX_PINGRP_PE6,
- PMUX_PINGRP_PE7,
- PMUX_PINGRP_PH6,
- PMUX_PINGRP_PK0,
- PMUX_PINGRP_PK1,
- PMUX_PINGRP_PK2,
- PMUX_PINGRP_PK3,
- PMUX_PINGRP_PK4,
- PMUX_PINGRP_PK5,
- PMUX_PINGRP_PK6,
- PMUX_PINGRP_PK7,
- PMUX_PINGRP_PL0,
- PMUX_PINGRP_PL1,
- PMUX_PINGRP_PZ0,
- PMUX_PINGRP_PZ1,
- PMUX_PINGRP_PZ2,
- PMUX_PINGRP_PZ3,
- PMUX_PINGRP_PZ4,
- PMUX_PINGRP_PZ5,
- PMUX_PINGRP_COUNT,
-};
-
-enum pmux_drvgrp {
- PMUX_DRVGRP_ALS_PROX_INT = (0x10 / 4),
- PMUX_DRVGRP_AP_READY,
- PMUX_DRVGRP_AP_WAKE_BT,
- PMUX_DRVGRP_AP_WAKE_NFC,
- PMUX_DRVGRP_AUD_MCLK,
- PMUX_DRVGRP_BATT_BCL,
- PMUX_DRVGRP_BT_RST,
- PMUX_DRVGRP_BT_WAKE_AP,
- PMUX_DRVGRP_BUTTON_HOME,
- PMUX_DRVGRP_BUTTON_POWER_ON,
- PMUX_DRVGRP_BUTTON_SLIDE_SW,
- PMUX_DRVGRP_BUTTON_VOL_DOWN,
- PMUX_DRVGRP_BUTTON_VOL_UP,
- PMUX_DRVGRP_CAM1_MCLK,
- PMUX_DRVGRP_CAM1_PWDN,
- PMUX_DRVGRP_CAM1_STROBE,
- PMUX_DRVGRP_CAM2_MCLK,
- PMUX_DRVGRP_CAM2_PWDN,
- PMUX_DRVGRP_CAM_AF_EN,
- PMUX_DRVGRP_CAM_FLASH_EN,
- PMUX_DRVGRP_CAM_I2C_SCL,
- PMUX_DRVGRP_CAM_I2C_SDA,
- PMUX_DRVGRP_CAM_RST,
- PMUX_DRVGRP_CLK_32K_IN,
- PMUX_DRVGRP_CLK_32K_OUT,
- PMUX_DRVGRP_CLK_REQ,
- PMUX_DRVGRP_CORE_PWR_REQ,
- PMUX_DRVGRP_CPU_PWR_REQ,
- PMUX_DRVGRP_DAP1_DIN,
- PMUX_DRVGRP_DAP1_DOUT,
- PMUX_DRVGRP_DAP1_FS,
- PMUX_DRVGRP_DAP1_SCLK,
- PMUX_DRVGRP_DAP2_DIN,
- PMUX_DRVGRP_DAP2_DOUT,
- PMUX_DRVGRP_DAP2_FS,
- PMUX_DRVGRP_DAP2_SCLK,
- PMUX_DRVGRP_DAP4_DIN,
- PMUX_DRVGRP_DAP4_DOUT,
- PMUX_DRVGRP_DAP4_FS,
- PMUX_DRVGRP_DAP4_SCLK,
- PMUX_DRVGRP_DMIC1_CLK,
- PMUX_DRVGRP_DMIC1_DAT,
- PMUX_DRVGRP_DMIC2_CLK,
- PMUX_DRVGRP_DMIC2_DAT,
- PMUX_DRVGRP_DMIC3_CLK,
- PMUX_DRVGRP_DMIC3_DAT,
- PMUX_DRVGRP_DP_HPD0,
- PMUX_DRVGRP_DVFS_CLK,
- PMUX_DRVGRP_DVFS_PWM,
- PMUX_DRVGRP_GEN1_I2C_SCL,
- PMUX_DRVGRP_GEN1_I2C_SDA,
- PMUX_DRVGRP_GEN2_I2C_SCL,
- PMUX_DRVGRP_GEN2_I2C_SDA,
- PMUX_DRVGRP_GEN3_I2C_SCL,
- PMUX_DRVGRP_GEN3_I2C_SDA,
- PMUX_DRVGRP_PA6,
- PMUX_DRVGRP_PCC7,
- PMUX_DRVGRP_PE6,
- PMUX_DRVGRP_PE7,
- PMUX_DRVGRP_PH6,
- PMUX_DRVGRP_PK0,
- PMUX_DRVGRP_PK1,
- PMUX_DRVGRP_PK2,
- PMUX_DRVGRP_PK3,
- PMUX_DRVGRP_PK4,
- PMUX_DRVGRP_PK5,
- PMUX_DRVGRP_PK6,
- PMUX_DRVGRP_PK7,
- PMUX_DRVGRP_PL0,
- PMUX_DRVGRP_PL1,
- PMUX_DRVGRP_PZ0,
- PMUX_DRVGRP_PZ1,
- PMUX_DRVGRP_PZ2,
- PMUX_DRVGRP_PZ3,
- PMUX_DRVGRP_PZ4,
- PMUX_DRVGRP_PZ5,
- PMUX_DRVGRP_GPIO_X1_AUD,
- PMUX_DRVGRP_GPIO_X3_AUD,
- PMUX_DRVGRP_GPS_EN,
- PMUX_DRVGRP_GPS_RST,
- PMUX_DRVGRP_HDMI_CEC,
- PMUX_DRVGRP_HDMI_INT_DP_HPD,
- PMUX_DRVGRP_JTAG_RTCK,
- PMUX_DRVGRP_LCD_BL_EN,
- PMUX_DRVGRP_LCD_BL_PWM,
- PMUX_DRVGRP_LCD_GPIO1,
- PMUX_DRVGRP_LCD_GPIO2,
- PMUX_DRVGRP_LCD_RST,
- PMUX_DRVGRP_LCD_TE,
- PMUX_DRVGRP_MODEM_WAKE_AP,
- PMUX_DRVGRP_MOTION_INT,
- PMUX_DRVGRP_NFC_EN,
- PMUX_DRVGRP_NFC_INT,
- PMUX_DRVGRP_PEX_L0_CLKREQ_N,
- PMUX_DRVGRP_PEX_L0_RST_N,
- PMUX_DRVGRP_PEX_L1_CLKREQ_N,
- PMUX_DRVGRP_PEX_L1_RST_N,
- PMUX_DRVGRP_PEX_WAKE_N,
- PMUX_DRVGRP_PWR_I2C_SCL,
- PMUX_DRVGRP_PWR_I2C_SDA,
- PMUX_DRVGRP_PWR_INT_N,
- PMUX_DRVGRP_QSPI_SCK = (0x1bc / 4),
- PMUX_DRVGRP_SATA_LED_ACTIVE,
- PMUX_DRVGRP_SDMMC1,
- PMUX_DRVGRP_SDMMC2,
- PMUX_DRVGRP_SDMMC3 = (0x1dc / 4),
- PMUX_DRVGRP_SDMMC4,
- PMUX_DRVGRP_SHUTDOWN = (0x1f4 / 4),
- PMUX_DRVGRP_SPDIF_IN,
- PMUX_DRVGRP_SPDIF_OUT,
- PMUX_DRVGRP_SPI1_CS0,
- PMUX_DRVGRP_SPI1_CS1,
- PMUX_DRVGRP_SPI1_MISO,
- PMUX_DRVGRP_SPI1_MOSI,
- PMUX_DRVGRP_SPI1_SCK,
- PMUX_DRVGRP_SPI2_CS0,
- PMUX_DRVGRP_SPI2_CS1,
- PMUX_DRVGRP_SPI2_MISO,
- PMUX_DRVGRP_SPI2_MOSI,
- PMUX_DRVGRP_SPI2_SCK,
- PMUX_DRVGRP_SPI4_CS0,
- PMUX_DRVGRP_SPI4_MISO,
- PMUX_DRVGRP_SPI4_MOSI,
- PMUX_DRVGRP_SPI4_SCK,
- PMUX_DRVGRP_TEMP_ALERT,
- PMUX_DRVGRP_TOUCH_CLK,
- PMUX_DRVGRP_TOUCH_INT,
- PMUX_DRVGRP_TOUCH_RST,
- PMUX_DRVGRP_UART1_CTS,
- PMUX_DRVGRP_UART1_RTS,
- PMUX_DRVGRP_UART1_RX,
- PMUX_DRVGRP_UART1_TX,
- PMUX_DRVGRP_UART2_CTS,
- PMUX_DRVGRP_UART2_RTS,
- PMUX_DRVGRP_UART2_RX,
- PMUX_DRVGRP_UART2_TX,
- PMUX_DRVGRP_UART3_CTS,
- PMUX_DRVGRP_UART3_RTS,
- PMUX_DRVGRP_UART3_RX,
- PMUX_DRVGRP_UART3_TX,
- PMUX_DRVGRP_UART4_CTS,
- PMUX_DRVGRP_UART4_RTS,
- PMUX_DRVGRP_UART4_RX,
- PMUX_DRVGRP_UART4_TX,
- PMUX_DRVGRP_USB_VBUS_EN0,
- PMUX_DRVGRP_USB_VBUS_EN1,
- PMUX_DRVGRP_WIFI_EN,
- PMUX_DRVGRP_WIFI_RST,
- PMUX_DRVGRP_WIFI_WAKE_AP,
- PMUX_DRVGRP_COUNT,
-};
-
-enum pmux_func {
- PMUX_FUNC_DEFAULT,
- PMUX_FUNC_AUD,
- PMUX_FUNC_BCL,
- PMUX_FUNC_BLINK,
- PMUX_FUNC_CCLA,
- PMUX_FUNC_CEC,
- PMUX_FUNC_CLDVFS,
- PMUX_FUNC_CLK,
- PMUX_FUNC_CORE,
- PMUX_FUNC_CPU,
- PMUX_FUNC_DISPLAYA,
- PMUX_FUNC_DISPLAYB,
- PMUX_FUNC_DMIC1,
- PMUX_FUNC_DMIC2,
- PMUX_FUNC_DMIC3,
- PMUX_FUNC_DP,
- PMUX_FUNC_DTV,
- PMUX_FUNC_EXTPERIPH3,
- PMUX_FUNC_I2C1,
- PMUX_FUNC_I2C2,
- PMUX_FUNC_I2C3,
- PMUX_FUNC_I2CPMU,
- PMUX_FUNC_I2CVI,
- PMUX_FUNC_I2S1,
- PMUX_FUNC_I2S2,
- PMUX_FUNC_I2S3,
- PMUX_FUNC_I2S4A,
- PMUX_FUNC_I2S4B,
- PMUX_FUNC_I2S5A,
- PMUX_FUNC_I2S5B,
- PMUX_FUNC_IQC0,
- PMUX_FUNC_IQC1,
- PMUX_FUNC_JTAG,
- PMUX_FUNC_PE,
- PMUX_FUNC_PE0,
- PMUX_FUNC_PE1,
- PMUX_FUNC_PMI,
- PMUX_FUNC_PWM0,
- PMUX_FUNC_PWM1,
- PMUX_FUNC_PWM2,
- PMUX_FUNC_PWM3,
- PMUX_FUNC_QSPI,
- PMUX_FUNC_SATA,
- PMUX_FUNC_SDMMC1,
- PMUX_FUNC_SDMMC3,
- PMUX_FUNC_SHUTDOWN,
- PMUX_FUNC_SOC,
- PMUX_FUNC_SOR0,
- PMUX_FUNC_SOR1,
- PMUX_FUNC_SPDIF,
- PMUX_FUNC_SPI1,
- PMUX_FUNC_SPI2,
- PMUX_FUNC_SPI3,
- PMUX_FUNC_SPI4,
- PMUX_FUNC_SYS,
- PMUX_FUNC_TOUCH,
- PMUX_FUNC_UART,
- PMUX_FUNC_UARTA,
- PMUX_FUNC_UARTB,
- PMUX_FUNC_UARTC,
- PMUX_FUNC_UARTD,
- PMUX_FUNC_USB,
- PMUX_FUNC_VGP1,
- PMUX_FUNC_VGP2,
- PMUX_FUNC_VGP3,
- PMUX_FUNC_VGP4,
- PMUX_FUNC_VGP5,
- PMUX_FUNC_VGP6,
- PMUX_FUNC_VIMCLK,
- PMUX_FUNC_VIMCLK2,
- PMUX_FUNC_RSVD0,
- PMUX_FUNC_RSVD1,
- PMUX_FUNC_RSVD2,
- PMUX_FUNC_RSVD3,
- PMUX_FUNC_COUNT,
-};
-
-#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
-#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
-#define TEGRA_PMX_SOC_HAS_DRVGRPS
-#define TEGRA_PMX_PINS_HAVE_E_INPUT
-#define TEGRA_PMX_PINS_HAVE_LOCK
-#define TEGRA_PMX_PINS_HAVE_OD
-#define TEGRA_PMX_PINS_HAVE_E_IO_HV
-#include <asm/arch-tegra/pinmux.h>
-
-#endif /* _TEGRA210_PINMUX_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/powergate.h b/arch/arm/include/asm/arch-tegra210/powergate.h
deleted file mode 100644
index ec8f518..0000000
--- a/arch/arm/include/asm/arch-tegra210/powergate.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (c) 2014-2015 NVIDIA CORPORATION. All rights reserved.
- */
-
-#ifndef _TEGRA210_POWERGATE_H_
-#define _TEGRA210_POWERGATE_H_
-
-#include <asm/arch-tegra/powergate.h>
-
-#endif /* _TEGRA210_POWERGATE_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/sysctr.h b/arch/arm/include/asm/arch-tegra210/sysctr.h
deleted file mode 100644
index cb1c499..0000000
--- a/arch/arm/include/asm/arch-tegra210/sysctr.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA210_SYSCTR_H_
-#define _TEGRA210_SYSCTR_H_
-
-struct sysctr_ctlr {
- u32 cntcr; /* 0x00: SYSCTR0_CNTCR Counter Control */
- u32 cntsr; /* 0x04: SYSCTR0_CNTSR Counter Status */
- u32 cntcv0; /* 0x08: SYSCTR0_CNTCV0 Counter Count 31:00 */
- u32 cntcv1; /* 0x0C: SYSCTR0_CNTCV1 Counter Count 63:32 */
- u32 reserved1[4]; /* 0x10 - 0x1C */
- u32 cntfid0; /* 0x20: SYSCTR0_CNTFID0 Freq Table Entry */
- u32 cntfid1; /* 0x24: SYSCTR0_CNTFID1 Freq Table End */
- u32 reserved2[1002]; /* 0x28 - 0xFCC */
- u32 counterid[12]; /* 0xFD0 - 0xFxx CounterID regs, RO */
-};
-
-#define TSC_CNTCR_ENABLE (1 << 0) /* Enable */
-#define TSC_CNTCR_HDBG (1 << 1) /* Halt on debug */
-
-#endif /* _TEGRA210_SYSCTR_H_ */
diff --git a/arch/arm/include/asm/arch-tegra210/tegra.h b/arch/arm/include/asm/arch-tegra210/tegra.h
deleted file mode 100644
index 1c6fba6..0000000
--- a/arch/arm/include/asm/arch-tegra210/tegra.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013-2015
- * NVIDIA Corporation <www.nvidia.com>
- */
-
-#ifndef _TEGRA210_TEGRA_H_
-#define _TEGRA210_TEGRA_H_
-
-#define GICD_BASE 0x50041000 /* Generic Int Cntrlr Distrib */
-#define GICC_BASE 0x50042000 /* Generic Int Cntrlr CPU I/F */
-#define NV_PA_AHB_BASE 0x6000C000 /* System regs (AHB, etc.) */
-#define NV_PA_TSC_BASE 0x700F0000 /* System Counter TSC regs */
-#define NV_PA_MC_BASE 0x70019000 /* Mem Ctlr regs (MCB, etc.) */
-#define NV_PA_SDRAM_BASE 0x80000000
-
-#include <asm/arch-tegra/tegra.h>
-
-#define BCT_ODMDATA_OFFSET 1288 /* offset to ODMDATA word */
-
-#undef NVBOOTINFOTABLE_BCTSIZE
-#undef NVBOOTINFOTABLE_BCTPTR
-#define NVBOOTINFOTABLE_BCTSIZE 0x48 /* BCT size in BIT in IRAM */
-#define NVBOOTINFOTABLE_BCTPTR 0x4C /* BCT pointer in BIT in IRAM */
-
-#define MAX_NUM_CPU 4
-#define MCB_EMEM_ARB_OVERRIDE (NV_PA_MC_BASE + 0xE8)
-
-#define TEGRA_USB1_BASE 0x7D000000
-
-#endif /* _TEGRA210_TEGRA_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-07 12:29:34 +0000