From 1a691f101632955a994a0198fc5498b108e97fbc Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Wed, 30 Oct 2019 15:42:15 +0800 Subject: rm include/configs --- include/configs/10m50_devboard.h | 80 -- include/configs/3c120_devboard.h | 80 -- include/configs/B4860QDS.h | 781 ------------------- include/configs/BSC9131RDB.h | 348 --------- include/configs/BSC9132QDS.h | 565 -------------- include/configs/C29XPCIE.h | 456 ----------- include/configs/M5208EVBE.h | 181 ----- include/configs/M52277EVB.h | 253 ------ include/configs/M5235EVB.h | 213 ------ include/configs/M5249EVB.h | 162 ---- include/configs/M5253DEMO.h | 213 ------ include/configs/M5272C3.h | 200 ----- include/configs/M5275EVB.h | 196 ----- include/configs/M5282EVB.h | 204 ----- include/configs/M53017EVB.h | 207 ----- include/configs/M5329EVB.h | 217 ------ include/configs/M5373EVB.h | 217 ------ include/configs/M54418TWR.h | 309 -------- include/configs/M54451EVB.h | 260 ------- include/configs/M54455EVB.h | 376 --------- include/configs/M5475EVB.h | 256 ------- include/configs/M5485EVB.h | 243 ------ include/configs/MCR3000.h | 110 --- include/configs/MPC8308RDB.h | 341 --------- include/configs/MPC8313ERDB_NAND.h | 404 ---------- include/configs/MPC8313ERDB_NOR.h | 377 --------- include/configs/MPC8315ERDB.h | 390 ---------- include/configs/MPC8323ERDB.h | 324 -------- include/configs/MPC832XEMDS.h | 322 -------- include/configs/MPC8349EMDS.h | 394 ---------- include/configs/MPC8349EMDS_SDRAM.h | 451 ----------- include/configs/MPC8349ITX.h | 454 ----------- include/configs/MPC837XEMDS.h | 390 ---------- include/configs/MPC837XERDB.h | 428 ----------- include/configs/MPC8536DS.h | 654 ---------------- include/configs/MPC8540ADS.h | 375 --------- include/configs/MPC8541CDS.h | 397 ---------- include/configs/MPC8544DS.h | 422 ---------- include/configs/MPC8548CDS.h | 530 ------------- include/configs/MPC8555CDS.h | 393 ---------- include/configs/MPC8560ADS.h | 405 ---------- include/configs/MPC8568MDS.h | 411 ---------- include/configs/MPC8569MDS.h | 503 ------------ include/configs/MPC8572DS.h | 624 --------------- include/configs/MPC8610HPCD.h | 575 -------------- include/configs/MPC8641HPCN.h | 649 ---------------- include/configs/MigoR.h | 92 --- include/configs/P1010RDB.h | 767 ------------------- include/configs/P1022DS.h | 607 --------------- include/configs/P1023RDB.h | 348 --------- include/configs/P2041RDB.h | 603 --------------- include/configs/P3041DS.h | 24 - include/configs/P4080DS.h | 23 - include/configs/P5020DS.h | 25 - include/configs/P5040DS.h | 19 - include/configs/SBx81LIFKW.h | 104 --- include/configs/SBx81LIFXCAT.h | 104 --- include/configs/T102xQDS.h | 772 ------------------- include/configs/T102xRDB.h | 744 ------------------ include/configs/T1040QDS.h | 681 ----------------- include/configs/T104xRDB.h | 824 -------------------- include/configs/T208xQDS.h | 787 ------------------- include/configs/T208xRDB.h | 736 ------------------ include/configs/T4240QDS.h | 560 -------------- include/configs/T4240RDB.h | 696 ----------------- include/configs/TQM834x.h | 288 ------- include/configs/UCP1020.h | 883 --------------------- include/configs/adp-ae3xx.h | 223 ------ include/configs/adp-ag101p.h | 338 -------- include/configs/advantech_dms-ba16.h | 242 ------ include/configs/alt.h | 53 -- include/configs/am335x_evm.h | 332 -------- include/configs/am335x_guardian.h | 112 --- include/configs/am335x_igep003x.h | 129 ---- include/configs/am335x_shc.h | 261 ------- include/configs/am335x_sl50.h | 89 --- include/configs/am3517_crane.h | 247 ------ include/configs/am3517_evm.h | 190 ----- include/configs/am43xx_evm.h | 278 ------- include/configs/am57xx_evm.h | 94 --- include/configs/am65x_evm.h | 132 ---- include/configs/amcore.h | 110 --- include/configs/ap121.h | 45 -- include/configs/ap143.h | 49 -- include/configs/ap152.h | 50 -- include/configs/apalis-imx8.h | 125 --- include/configs/apalis-tk1.h | 148 ---- include/configs/apalis_imx6.h | 240 ------ include/configs/apalis_t30.h | 48 -- include/configs/apf27.h | 274 ------- include/configs/apx4devkit.h | 93 --- include/configs/aristainetos-common.h | 201 ----- include/configs/aristainetos.h | 43 -- include/configs/aristainetos2.h | 50 -- include/configs/aristainetos2b.h | 50 -- include/configs/armadillo-800eva.h | 94 --- include/configs/arndale.h | 38 - include/configs/aspeed-common.h | 56 -- include/configs/aspenite.h | 40 - include/configs/astro_mcf5373l.h | 297 -------- include/configs/at91-sama5_common.h | 74 -- include/configs/at91rm9200ek.h | 174 ----- include/configs/at91sam9260ek.h | 157 ---- include/configs/at91sam9261ek.h | 135 ---- include/configs/at91sam9263ek.h | 241 ------ include/configs/at91sam9m10g45ek.h | 141 ---- include/configs/at91sam9n12ek.h | 166 ---- include/configs/at91sam9rlek.h | 106 --- include/configs/at91sam9x5ek.h | 128 ---- include/configs/ax25-ae350.h | 149 ---- include/configs/axs10x.h | 72 -- include/configs/baltos.h | 258 ------- include/configs/bav335x.h | 491 ------------ include/configs/bayleybay.h | 25 - include/configs/bcm23550_w1d.h | 103 --- include/configs/bcm28155_ap.h | 100 --- include/configs/bcm7260.h | 39 - include/configs/bcm7445.h | 38 - include/configs/bcm_ep_board.h | 56 -- include/configs/bcm_northstar2.h | 45 -- include/configs/bcmstb.h | 174 ----- include/configs/beaver.h | 37 - include/configs/bg0900.h | 43 -- include/configs/bitmain_antminer_s9.h | 27 - include/configs/bk4r1.h | 270 ------- include/configs/blanche.h | 65 -- include/configs/bmips_bcm3380.h | 25 - include/configs/bmips_bcm6318.h | 32 - include/configs/bmips_bcm63268.h | 32 - include/configs/bmips_bcm6328.h | 32 - include/configs/bmips_bcm6338.h | 29 - include/configs/bmips_bcm6348.h | 34 - include/configs/bmips_bcm6358.h | 36 - include/configs/bmips_bcm6362.h | 32 - include/configs/bmips_bcm6368.h | 36 - include/configs/bmips_bcm6838.h | 25 - include/configs/bmips_common.h | 28 - include/configs/boston.h | 66 -- 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include/configs/cm_t54.h | 126 --- include/configs/cobra5272.h | 336 -------- include/configs/colibri-imx6ull.h | 166 ---- include/configs/colibri-imx8x.h | 160 ---- include/configs/colibri_imx6.h | 221 ------ include/configs/colibri_imx7.h | 260 ------- include/configs/colibri_pxa270.h | 184 ----- include/configs/colibri_t20.h | 53 -- include/configs/colibri_t30.h | 47 -- include/configs/colibri_vf.h | 171 ----- include/configs/comtrend_ar5315u.h | 11 - include/configs/comtrend_ar5387un.h | 11 - include/configs/comtrend_ct5361.h | 11 - include/configs/comtrend_vr3032u.h | 17 - include/configs/comtrend_wap5813n.h | 11 - include/configs/condor.h | 41 - include/configs/conga-qeval20-qa3-e3845.h | 40 - include/configs/controlcenterd.h | 369 --------- include/configs/controlcenterdc.h | 187 ----- include/configs/coreboot.h | 32 - include/configs/corenet_ds.h | 616 --------------- include/configs/corvus.h | 143 ---- include/configs/cougarcanyon2.h | 23 - include/configs/crownbay.h | 27 - include/configs/crs305-1g-4s.h | 38 - include/configs/cyrus.h | 468 ------------ include/configs/da850evm.h | 282 ------- include/configs/dalmore.h | 33 - include/configs/dart_6ul.h | 130 ---- include/configs/db-88f6281-bp.h | 96 --- include/configs/db-88f6720.h | 78 -- include/configs/db-88f6820-amc.h | 82 -- include/configs/db-88f6820-gp.h | 106 --- include/configs/db-mv784mp-gp.h | 91 --- include/configs/db-xc3-24g4xg.h | 40 - include/configs/devkit3250.h | 190 ----- include/configs/devkit8000.h | 181 ----- include/configs/dfi-bt700.h | 45 -- include/configs/dh_imx6.h | 152 ---- include/configs/display5.h | 363 --------- include/configs/dns325.h | 118 --- include/configs/dockstar.h | 72 -- include/configs/dra7xx_evm.h | 152 ---- include/configs/draak.h | 34 - include/configs/draco.h | 83 -- include/configs/dragonboard410c.h | 94 --- include/configs/dragonboard820c.h | 62 -- include/configs/dreamplug.h | 76 -- include/configs/ds109.h | 79 -- include/configs/ds414.h | 102 --- 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-- include/configs/minnowmax.h | 28 - include/configs/miqi_rk3288.h | 18 - include/configs/mpc8308_p1m.h | 319 -------- include/configs/mt7623.h | 63 -- include/configs/mt7629.h | 60 -- include/configs/mv-common.h | 78 -- include/configs/mv-plug-common.h | 22 - include/configs/mvebu_armada-37xx.h | 108 --- include/configs/mvebu_armada-8k.h | 110 --- include/configs/mx23_olinuxino.h | 128 ---- include/configs/mx23evk.h | 112 --- include/configs/mx25pdk.h | 186 ----- include/configs/mx28evk.h | 251 ------ include/configs/mx31pdk.h | 146 ---- include/configs/mx35pdk.h | 225 ------ include/configs/mx51evk.h | 189 ----- include/configs/mx53ard.h | 180 ----- include/configs/mx53cx9020.h | 164 ---- include/configs/mx53evk.h | 126 --- include/configs/mx53loco.h | 194 ----- include/configs/mx53ppd.h | 214 ------ include/configs/mx53smd.h | 121 --- include/configs/mx6_common.h | 63 -- include/configs/mx6cuboxi.h | 137 ---- include/configs/mx6memcal.h | 57 -- include/configs/mx6qarm2.h | 133 ---- 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CONFIG_SYS_NS16550_MEM32 - -/* - * Flash - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -/* - * NET options - */ -#define CONFIG_SYS_RX_ETH_BUFFER 0 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * FDT options - */ -#define CONFIG_LMB - -/* - * MEMORY ORGANIZATION - * -Monitor at top of sdram. - * -The heap is placed below the monitor - * -The stack is placed below the heap (&grows down). - */ -#define CONFIG_SYS_SDRAM_BASE 0xc8000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN 0x20000 - -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ - -#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (0xf4000000 + CONFIG_SYS_MONITOR_LEN) - -/* - * MISC - */ -#define CONFIG_SYS_LOAD_ADDR 0xcc000000 /* Half of RAM */ -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ - CONFIG_ENV_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - 0x10000) - -#endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h deleted file mode 100644 index f6ce430..0000000 --- a/include/configs/3c120_devboard.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2005, Psyent Corporation - * Scott McNutt - * (C) Copyright 2010, Thomas Chou - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * BOARD/CPU - */ - -/* - * SERIAL - */ - -/* - * CFI Flash - */ -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * NET options - */ -#define CONFIG_SYS_RX_ETH_BUFFER 0 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * FDT options - */ -#define CONFIG_LMB - -/* - * MEMORY ORGANIZATION - * -Monitor at top of sdram. - * -The heap is placed below the monitor - * -The stack is placed below the heap (&grows down). - */ -#define CONFIG_SYS_SDRAM_BASE 0xD0000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 -#define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_MALLOC_LEN 0x20000 - -/* - * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above - * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the - * reset address, no? This will keep the environment in user region - * of flash. NOTE: the monitor length must be multiple of sector size - * (which is common practice). - */ - -#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ -#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ -#define CONFIG_ENV_ADDR (0xe2800000 + CONFIG_SYS_MONITOR_LEN) - -/* - * MISC - */ -#define CONFIG_SYS_LOAD_ADDR 0xd4000000 /* Half of RAM */ -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MONITOR_BASE - \ - CONFIG_ENV_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - 0x10000) - -#endif /* __CONFIG_H */ diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h deleted file mode 100644 index 3ccd092..0000000 --- a/include/configs/B4860QDS.h +++ /dev/null @@ -1,781 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * B4860 QDS board configuration file - */ -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg -#ifndef CONFIG_NAND -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif -#endif -#endif - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#ifndef CONFIG_ARCH_B4420 -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#endif - -/* I2C bus multiplexer */ -#define I2C_MUX_PCA_ADDR 0x77 - -/* VSC Crossbar switches */ -#define CONFIG_VSC_CROSSBAR -#define I2C_CH_DEFAULT 0x8 -#define I2C_CH_VSC3316 0xc -#define I2C_CH_VSC3308 0xd - -#define VSC3316_TX_ADDRESS 0x70 -#define VSC3316_RX_ADDRESS 0x71 -#define VSC3308_TX_ADDRESS 0x02 -#define VSC3308_RX_ADDRESS 0x03 - -/* IDT clock synthesizers */ -#define CONFIG_IDT8T49N222A -#define I2C_CH_IDT 0x9 - -#define IDT_SERDES1_ADDRESS 0x6E -#define IDT_SERDES2_ADDRESS 0x6C - -/* Voltage monitor on channel 2*/ -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -#define CONFIG_ZM7300 -#define I2C_MUX_CH_DPM 0xa -#define I2C_DPM_ADDR 0x28 - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1097) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#if 0 -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#endif -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#ifdef CONFIG_NAND -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_DDR_RAW_TIMING - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x53 - -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) | \ - FTIM0_NOR_TEADC(0x04) | \ - FTIM0_NOR_TEAHC(0x20)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x01) | \ - FTIM2_NOR_TCH(0x0E) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define CONFIG_FSL_QIXIS_V2 -#define QIXIS_BASE 0xffdf0000 -#ifdef CONFIG_PHYS_64BIT -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#else -#define QIXIS_BASE_PHYS QIXIS_BASE -#endif -#define QIXIS_LBMAP_SWITCH 0x01 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x02 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x119000 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * RapidIO - */ -#ifdef CONFIG_SYS_SRIO -#ifdef CONFIG_SRIO1 -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#endif - -#ifdef CONFIG_SRIO2 -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 -#endif -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ -#endif -#endif - -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif - -/* - * eSPI - Enhanced SPI - */ - -/* - * MAPLE - */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull -#else -#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000 -#endif - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 25 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 25 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN - -#define CONFIG_SYS_DPAA_RMAN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 545KB (1089 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_TERANETICS -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x10 -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x11 -#endif - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10 -#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11 - -/*B4860 QDS AMC2PEX-2S default PHY_ADDR */ -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/ -#define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6 /*SLOT 2*/ - -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f - -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE ulpi - -#ifdef CONFIG_ARCH_B4860 -#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ - "bank_intlv=cs0_cs1;" \ - "en_cpc:cpc2;" -#else -#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - HWCONFIG \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=b4860qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=b4860qds/b4860qds.dtb\0" \ - "bdev=sda3\0" - -/* For emulation this causes u-boot to jump to the start of the proof point - app code automatically */ -#define CONFIG_PROOF_POINTS \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x29000000 - - -;" \ - "cpu 2 release 0x29000000 - - -;" \ - "cpu 3 release 0x29000000 - - -;" \ - "cpu 4 release 0x29000000 - - -;" \ - "cpu 5 release 0x29000000 - - -;" \ - "cpu 6 release 0x29000000 - - -;" \ - "cpu 7 release 0x29000000 - - -;" \ - "go 0x29000000" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x01e00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h deleted file mode 100644 index b5d759c..0000000 --- a/include/configs/BSC9131RDB.h +++ /dev/null @@ -1,348 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -/* - * BSC9131 RDB board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_NAND_FSL_IFC - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_NAND -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ -#if defined(CONFIG_SYS_CLK_100) -#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */ -#else -#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ -#endif - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* enable branch predition */ - -#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01ffffff - -/* DDR Setup */ -#undef CONFIG_SYS_DDR_RAW_TIMING -#undef CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#ifndef __ASSEMBLY__ -extern unsigned long get_sdram_size(void); -#endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -/* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ - /* CONFIG_SYS_IMMR */ -/* DSP CCSRBAR */ -#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT -#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - -/* - * Memory map - * - * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable - * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M - * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M - * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M - * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K - * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K - * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K - * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M - * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M - * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M - * - */ - -/* - * IFC Definitions - */ - -/* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -/* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ - | FTIM0_NAND_TWP(0x05) \ - | FTIM0_NAND_TWCHT(0x02) \ - | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \ - | FTIM1_NAND_TWBE(0x1E) \ - | FTIM1_NAND_TRR(0x07) \ - | FTIM1_NAND_TRP(0x05)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ - | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x11)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* Set up IFC registers for boot location NAND */ -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -/* I2C EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* eSPI - Enhanced SPI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 - -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#elif defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "BSC9131rdb" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=bsc9131rdb.dtb\0" \ - "bdev=sda1\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ - "bootm_size=0x37000000\0" \ - "othbootargs=ramdisk_size=600000 " \ - "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/BSC9132QDS.h b/include/configs/BSC9132QDS.h deleted file mode 100644 index 1c615ac..0000000 --- a/include/configs/BSC9132QDS.h +++ /dev/null @@ -1,565 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * BSC9132 QDS board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif -#ifdef CONFIG_NAND_SECBOOT -#define CONFIG_RAMBOOT_NAND -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_NAND -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0x8ffffffc -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -/* - * PCI Windows - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "PCIe Slot" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xC0010000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_PHYS 0xC0010000 - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SYS_CLK_100_DDR_100) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#elif defined(CONFIG_SYS_CLK_100_DDR_133) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133000000 -#endif - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* enable branch predition */ - -#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x01ffffff - -/* DDR Setup */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x54 /* I2C access */ -#define SPD_EEPROM_ADDRESS2 0x56 /* I2C access */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_SDRAM_SIZE (1024) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* DDR3 Controller Settings */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG_1333 0x80004302 -#define CONFIG_SYS_DDR_CS0_CONFIG_800 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR1_CS0_BNDS 0x0040007F - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL_800 0x470C0000 -#define CONFIG_SYS_DDR_CONTROL_2_800 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4_800 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5_800 0x03402400 - -#define CONFIG_SYS_DDR_CONTROL_1333 0x470C0008 -#define CONFIG_SYS_DDR_CONTROL_2_1333 0x24401010 -#define CONFIG_SYS_DDR_TIMING_4_1333 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5_1333 0x03401400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x40461520 -#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300000 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 - -#define CONFIG_SYS_DDR_TIMING_3_1333 0x01061000 -#define CONFIG_SYS_DDR_TIMING_0_1333 0x00440104 -#define CONFIG_SYS_DDR_TIMING_1_1333 0x98913A45 -#define CONFIG_SYS_DDR_TIMING_2_1333 0x0FB8B114 -#define CONFIG_SYS_DDR_CLK_CTRL_1333 0x02800000 -#define CONFIG_SYS_DDR_MODE_1_1333 0x00061A50 -#define CONFIG_SYS_DDR_MODE_2_1333 0x00100000 -#define CONFIG_SYS_DDR_INTERVAL_1333 0x144E0513 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_1333 0x8655F607 - -/*FIXME: the following params are constant w.r.t diff freq -combinations. this should be removed later -*/ -#if CONFIG_DDR_CLK_FREQ == 100000000 -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 -#elif CONFIG_DDR_CLK_FREQ == 133000000 -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_1333 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_1333 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333 -#else -#define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800 -#define CONFIG_SYS_DDR_CONTROL CONFIG_SYS_DDR_CONTROL_800 -#define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800 -#define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800 -#define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800 -#endif - -/* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT - -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - -/* DSP CCSRBAR */ -#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT -#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT - -/* - * IFC Definitions - */ -/* NOR Flash on IFC */ - -#define CONFIG_SYS_FLASH_BASE 0x88000000 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* Max number of sector: 32M */ - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_NOR_CSPR 0x88000101 -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(5) -/* NOR Flash Timing Params */ - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x01) \ - | FTIM0_NOR_TEADC(0x03) \ - | FTIM0_NOR_TAVDS(0x00) \ - | FTIM0_NOR_TEAHC(0x0f)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1d) \ - | FTIM1_NOR_TRAD_NOR(0x09) \ - | FTIM1_NOR_TSEQRAD_NOR(0x09)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) \ - | FTIM2_NOR_TCH(0x4) \ - | FTIM2_NOR_TWPH(0x7) \ - | FTIM2_NOR_TWP(0x1e)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -/* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \ - | FTIM0_NAND_TWP(0x05) \ - | FTIM0_NAND_TWCHT(0x02) \ - | FTIM0_NAND_TWH(0x04)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1c) \ - | FTIM1_NAND_TWBE(0x1e) \ - | FTIM1_NAND_TRR(0x07) \ - | FTIM1_NAND_TRP(0x05)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ - | FTIM2_NAND_TREH(0x04) \ - | FTIM2_NAND_TWHRE(0x11)) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* NAND */ -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_FSL_QIXIS -#endif -#ifdef CONFIG_FSL_QIXIS -#define CONFIG_SYS_FPGA_BASE 0xffb00000 -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_BASE CONFIG_SYS_FPGA_BASE -#define QIXIS_LBMAP_SWITCH 9 -#define QIXIS_LBMAP_MASK 0x07 -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 - -#define CONFIG_SYS_FPGA_BASE_PHYS CONFIG_SYS_FPGA_BASE - -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 -/* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 -#endif - -/* Set up IFC registers for boot location NOR/NAND */ -#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400800 /* I2C speed and slave address*/ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400800 /* I2C speed and slave address*/ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C EEPROM */ -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_BUS_NUM 0 - -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* I2C FPGA */ -#define CONFIG_I2C_FPGA -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 - -#define CONFIG_RTC_DS3231 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * SPI interface will not be available in case of NAND boot SPI CS0 will be - * used for SLIC - */ -/* eSPI - Enhanced SPI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - -#endif /* CONFIG_TSEC_ENET */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * Environment - */ -#if defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) -#elif defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_HOSTNAME "BSC9132qds" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" - -#ifdef CONFIG_SDCARD -#define CONFIG_DEF_HWCONFIG "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" -#else -#define CONFIG_DEF_HWCONFIG "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "loadaddr=1000000\0" \ - "bootfile=uImage\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=bsc9132qds.dtb\0" \ - "bdev=sda1\0" \ - CONFIG_DEF_HWCONFIG\ - "othbootargs=mem=880M ramdisk_size=600000 " \ - "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \ - "isolcpus=0\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "debug_halt_off=mw ff7e0e30 0xf0000000;" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h deleted file mode 100644 index 5a1a29b..0000000 --- a/include/configs/C29XPCIE.h +++ /dev/null @@ -1,456 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -/* - * C29XPCIE board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifdef CONFIG_NAND -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_TPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_NAND_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ - -#ifdef CONFIG_PCI -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -/* - * PCI Windows - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "Slot 1" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DDR_CLK_FREQ 100000000 -#define CONFIG_SYS_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* DDR Setup */ -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SYS_DDR_RAW_TIMING - -/* DDR ECC Setup*/ -#define CONFIG_DDR_ECC -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER - -#define CONFIG_SYS_SDRAM_SIZE 512 -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* Platform SRAM setting */ -#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 -#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ - (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) -#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) - -/* - * IFC Definitions - */ -/* NOR Flash on IFC */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ - -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ - -/* 16Bit NOR Flash - S29GL512S10TFI01 */ -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -/* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024) - -/* 8Bit NAND Flash - K9F1G08U0B */ -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */ -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ - | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ - | CSOR_NAND_PB(128)) /*128 Pages Per Block*/ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ - FTIM0_NAND_TWP(0x0c) | \ - FTIM0_NAND_TWCHT(0x08) | \ - FTIM0_NAND_TWH(0x06)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ - FTIM1_NAND_TWBE(0x1d) | \ - FTIM1_NAND_TRR(0x08) | \ - FTIM1_NAND_TRP(0x0c)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x18)) -#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* Set up IFC registers for boot location NOR/NAND */ -#ifdef CONFIG_NAND -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -/* CPLD on IFC, selected by CS2 */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ - | CONFIG_SYS_CPLD_BASE) - -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 -/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 - -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -/* - * Config the L2 Cache as L2 SRAM - */ -#if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#elif defined(CONFIG_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) -#else -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) -#endif -#endif -#endif - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C EEPROM */ -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* eSPI - Enhanced SPI */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -/* Default mode is RGMII mode */ -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 2 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define CONFIG_ETHPRIME "eTSEC1" -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#if defined(CONFIG_SYS_RAMBOOT) -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#endif -#elif defined(CONFIG_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#else -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE -#endif -#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif - -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=name/of/device-tree.dtb\0" \ - "othbootargs=ramdisk_size=600000\0" \ - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h deleted file mode 100644 index 0a356f4..0000000 --- a/include/configs/M5208EVBE.h +++ /dev/null @@ -1,181 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF5208EVBe. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -#ifndef _M5208EVBE_H -#define _M5208EVBE_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 5000 - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_HAS_ETH1 - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -#define CONFIG_UDP_CHECKSUM - -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5208EVBe" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off 0 3ffff;" \ - "era 0 3ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" - -#define CONFIG_PRAM 512 /* 512 KB */ - -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - -#define CONFIG_SYS_CLK 166666666 /* CPU Core Clock */ -#define CONFIG_SYS_PLL_ODR 0x36 -#define CONFIG_SYS_PLL_FDR 0x7D - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1002000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/* FLASH organization */ -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of sectors on one chip */ -#endif - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -/* - * Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#define CONFIG_ENV_OFFSET 0x2000 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x2000 - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*); - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/* Chipselect bank definitions */ -/* - * CS0 - NOR Flash - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007F0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 - -#endif /* _M5208EVBE_H */ diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h deleted file mode 100644 index a9c260d..0000000 --- a/include/configs/M52277EVB.h +++ /dev/null @@ -1,253 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF52277 EVB board. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M52277EVB_H -#define _M52277EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_HOSTNAME "M52277EVB" -#define CONFIG_SYS_UBOOT_END 0x3FFFF -#define CONFIG_SYS_LOAD_ADDR2 0x40010007 -#ifdef CONFIG_SYS_STMICRO_BOOT -/* ST Micro serial flash */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "uboot=u-boot.bin\0" \ - "load=loadb ${loadaddr} ${baudrate};" \ - "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:2 10000 1;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 30000;" \ - "save\0" \ - "" -#endif -#ifdef CONFIG_SYS_SPANSION_BOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "uboot=u-boot.bin\0" \ - "load=loadb ${loadaddr} ${baudrate}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ - " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ - __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize}; save\0" \ - "updsbf=run loadsbf; run progsbf\0" \ - "loadsbf=loadb ${loadaddr} ${baudrate};" \ - "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ - "progsbf=sf probe 0:2 10000 1;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 30000;" \ - "" -#endif - -/* LCD */ -#ifdef CONFIG_CMD_BMP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_LCD_LOGO -#define CONFIG_SHARP_LQ035Q7DH06 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 -#define CONFIG_SYS_USB_EHCI_CPU_INIT -#endif - -/* Realtime clock */ -#define CONFIG_MCFRTC -#undef RTC_DEBUG -#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SYS_SBFHDR_SIZE 0x7 - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_SYS_INPUT_CLKSRC 16000000 - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x81810000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 -#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#ifdef CONFIG_CF_SBF -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/* - * Configuration for environment - * Environment is not embedded in u-boot. First time runing may have env - * crc error warning if there is no correct environment on the flash. - */ -#define CONFIG_ENV_OVERWRITE 1 - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_ENV_OFFSET 0x30000 -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_SECT_SIZE 0x10000 -#endif -#ifdef CONFIG_SYS_SPANSION_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_SECT_SIZE 0x8000 -#endif - -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_FLASH_SPANSION_S29WS_N 1 -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } -#endif - -#define LDS_BOARD_TEXT \ - arch/m68k/cpu/mcf5227x/built-in.o (.text*) \ - arch/m68k/lib/built-in.o (.text*) - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ - -#ifdef CONFIG_CF_SBF -#define CONFIG_SYS_CS0_BASE 0x04000000 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 -#else -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 -#endif - -#endif /* _M52277EVB_H */ diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h deleted file mode 100644 index a197c3a..0000000 --- a/include/configs/M5235EVB.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF5329 FireEngine board. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5235EVB_H -#define _M5235EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_i2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) -#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) -#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA) - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#define CONFIG_BOOTFILE "u-boot.bin" -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M5235EVB" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b ${loadaddr} ffe00000 ${filesize};"\ - "save\0" \ - "" - -#define CONFIG_PRAM 512 /* 512 KB */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) - -#define CONFIG_SYS_CLK 75000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 - -#define CONFIG_SYS_MBAR 0x40000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -#ifdef NORFLASH_PS32BIT -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#else -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#endif -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -#endif - -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text); - -#ifdef NORFLASH_PS32BIT -# define CONFIG_ENV_OFFSET (0x8000) -# define CONFIG_ENV_SIZE 0x4000 -# define CONFIG_ENV_SECT_SIZE 0x4000 -#else -# define CONFIG_ENV_OFFSET (0x4000) -# define CONFIG_ENV_SIZE 0x2000 -# define CONFIG_ENV_SECT_SIZE 0x2000 -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Chipselect bank definitions - */ -/* - * CS0 - NOR Flash 1, 2, 4, or 8MB - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - * CS6 - Available - * CS7 - Available - */ -#ifdef NORFLASH_PS32BIT -# define CONFIG_SYS_CS0_BASE 0xFFC00000 -# define CONFIG_SYS_CS0_MASK 0x003f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D00 -#else -# define CONFIG_SYS_CS0_BASE 0xFFE00000 -# define CONFIG_SYS_CS0_MASK 0x001f0001 -# define CONFIG_SYS_CS0_CTRL 0x00001D80 -#endif - -#endif /* _M5329EVB_H */ diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h deleted file mode 100644 index f214dc9..0000000 --- a/include/configs/M5249EVB.h +++ /dev/null @@ -1,162 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the esd TASREG board. - * - * (C) Copyright 2004 - * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5249EVB_H -#define _M5249EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG - -#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */ - -/* - * BOOTP options - */ -#undef CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ - -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -/* - * Clock configuration: enable only one of the following options - */ - -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK 1 /* MCF5249 can run at 140MHz */ -#define CONFIG_SYS_CLK 132025600 /* MCF5249 can run at 140MHz */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text); - -#define CONFIG_ENV_OFFSET 0x4000 /* Address of Environment Sector*/ -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ -#define CONFIG_ENV_SECT_SIZE 0x2000 /* see README - env sector total size */ - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) - -#if 0 /* test-only */ -#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ -#endif - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */ -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI - -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ - CF_ADDRMASK(2) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ - CF_CACR_DBWE) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ - -/* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 /* WS=0110, AA=1, PS=10 */ -/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/ -#define CONFIG_SYS_CS0_MASK 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */ - -/* CS1 - FPGA, address 0xe0000000 */ -#define CONFIG_SYS_CS1_BASE 0xe0000000 -#define CONFIG_SYS_CS1_CTRL 0x00000d80 /* WS=0011, AA=1, PS=10 */ -#define CONFIG_SYS_CS1_MASK 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/ - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ - -#endif /* M5249 */ diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h deleted file mode 100644 index 1199fa3..0000000 --- a/include/configs/M5253DEMO.h +++ /dev/null @@ -1,213 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * Hayden Fraser (Hayden.Fraser@freescale.com) - */ - -#ifndef _M5253DEMO_H -#define _M5253DEMO_H - -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG /* disable watchdog */ - - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifdef CONFIG_MONITOR_IS_IN_RAM -# define CONFIG_ENV_OFFSET 0x4000 -# define CONFIG_ENV_SECT_SIZE 0x1000 -#else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000) -# define CONFIG_ENV_SECT_SIZE 0x1000 -#endif - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*); - -/* - * Command line configuration. - */ - -#ifdef CONFIG_IDE -/* ATA */ -# define CONFIG_IDE_RESET 1 -# define CONFIG_IDE_PREINIT 1 -# define CONFIG_ATAPI -# undef CONFIG_LBA48 - -# define CONFIG_SYS_IDE_MAXBUS 1 -# define CONFIG_SYS_IDE_MAXDEVICE 2 - -# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800) -# define CONFIG_SYS_ATA_IDE0_OFFSET 0 - -# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ -# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ -# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ -# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ -#endif - -#define CONFIG_DRIVER_DM9000 -#ifdef CONFIG_DRIVER_DM9000 -# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE | 0x300) -# define DM9000_IO CONFIG_DM9000_BASE -# define DM9000_DATA (CONFIG_DM9000_BASE + 4) -# undef CONFIG_DM9000_DEBUG -# define CONFIG_DM9000_BYTE_SWAPPED - -# define CONFIG_OVERWRITE_ETHADDR_ONCE - -# define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off 0xff800000 0xff82ffff;" \ - "era 0xff800000 0xff82ffff;" \ - "cp.b ${loadaddr} 0xff800000 ${filesize};" \ - "save\0" \ - "" -#endif - -#define CONFIG_HOSTNAME "M5253DEMO" - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_SYS_I2C_PINMUX_REG (*(u32 *) (CONFIG_SYS_MBAR+0x19C)) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF) -#define CONFIG_SYS_I2C_PINMUX_SET (0) - -#define CONFIG_SYS_LOAD_ADDR 0x00100000 - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */ -#define CONFIG_SYS_FAST_CLK -#ifdef CONFIG_SYS_FAST_CLK -# define CONFIG_SYS_PLLCR 0x1243E054 -# define CONFIG_SYS_CLK 140000000 -#else -# define CONFIG_SYS_PLLCR 0x135a4140 -# define CONFIG_SYS_CLK 70000000 -#endif - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */ - -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ - -#ifdef CONFIG_MONITOR_IS_IN_RAM -# define CONFIG_SYS_MONITOR_BASE 0x20000 -#else -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x40000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define FLASH_SST6401B 0x200 -#define SST_ID_xF6401B 0x236D236D - -#ifdef CONFIG_SYS_FLASH_CFI -/* - * Unable to use CFI driver, due to incompatible sector erase command by SST. - * Amd/Atmel use 0x30 for sector erase, SST use 0x50. - * 0x30 is block erase in SST - */ -# define CONFIG_SYS_FLASH_SIZE 0x800000 -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_FLASH_CFI_LEGACY -#else -# define CONFIG_SYS_SST_SECT 2048 -# define CONFIG_SYS_SST_SECTSZ 0x1000 -# define CONFIG_SYS_FLASH_WRITE_TOUT 500 -#endif - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \ - CF_ADDRMASK(8) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \ - CF_CACR_DBWE) - -/* Port configuration */ -#define CONFIG_SYS_FECI2C 0xF0 - -#define CONFIG_SYS_CS0_BASE 0xFF800000 -#define CONFIG_SYS_CS0_MASK 0x007F0021 -#define CONFIG_SYS_CS0_CTRL 0x00001D80 - -#define CONFIG_SYS_CS1_BASE 0xE0000000 -#define CONFIG_SYS_CS1_MASK 0x00000001 -#define CONFIG_SYS_CS1_CTRL 0x00003DD8 - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */ -#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */ -#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */ -#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */ -#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */ - -#endif /* _M5253DEMO_H */ diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h deleted file mode 100644 index 9d3bf42..0000000 --- a/include/configs/M5272C3.h +++ /dev/null @@ -1,200 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Motorola MC5272C3 board. - * - * (C) Copyright 2003 Josef Baumgartner - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5272C3_H -#define _M5272C3_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ - -#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR 0xffe04000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text); - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5272C3" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b ${loadaddr} ffe00000 ${filesize};"\ - "save\0" \ - "" - -#define CONFIG_SYS_LOAD_ADDR 0x20000 -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 -#define CONFIG_SYS_CLK 66000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE 0xffe00000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -#define CONFIG_SYS_BR0_PRELIM 0xFFE00201 -#define CONFIG_SYS_OR0_PRELIM 0xFFE00014 -#define CONFIG_SYS_BR1_PRELIM 0 -#define CONFIG_SYS_OR1_PRELIM 0 -#define CONFIG_SYS_BR2_PRELIM 0x30000001 -#define CONFIG_SYS_OR2_PRELIM 0xFFF80000 -#define CONFIG_SYS_BR3_PRELIM 0 -#define CONFIG_SYS_OR3_PRELIM 0 -#define CONFIG_SYS_BR4_PRELIM 0 -#define CONFIG_SYS_OR4_PRELIM 0 -#define CONFIG_SYS_BR5_PRELIM 0 -#define CONFIG_SYS_OR5_PRELIM 0 -#define CONFIG_SYS_BR6_PRELIM 0 -#define CONFIG_SYS_OR6_PRELIM 0 -#define CONFIG_SYS_BR7_PRELIM 0x00000701 -#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CONFIG_SYS_PACNT 0x00000000 -#define CONFIG_SYS_PADDR 0x0000 -#define CONFIG_SYS_PADAT 0x0000 -#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */ -#define CONFIG_SYS_PBDDR 0x0000 -#define CONFIG_SYS_PBDAT 0x0000 -#define CONFIG_SYS_PDCNT 0x00000000 -#endif /* _M5272C3_H */ diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h deleted file mode 100644 index 682e2e3..0000000 --- a/include/configs/M5275EVB.h +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Motorola MC5275EVB board. - * - * By Arthur Shipkowski - * Copyright (C) 2005 Videon Central, Inc. - * - * Based off of M5272C3 board code by Josef Baumgartner - * - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5275EVB_H -#define _M5275EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR 0xffe04000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text); - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Available command configuration */ - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -#define CONFIG_MII_INIT 1 -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_SYS_FEC0_PINMUX 0 -#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -#define CONFIG_SYS_FEC1_PINMUX 0 -#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE -#define MCFFEC_TOUT_LOOP 50000 -#define CONFIG_HAS_ETH1 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#else -#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#endif -#endif -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR -#define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) -#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) -#define CONFIG_SYS_I2C_PINMUX_SET (0x000F) - -#define CONFIG_SYS_LOAD_ADDR 0x800000 - -#define CONFIG_BOOTCOMMAND "bootm ffe40000" -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#ifdef CONFIG_MCFFEC -# define CONFIG_NET_RETRY_COUNT 5 -# define CONFIG_OVERWRITE_ETHADDR_ONCE -#endif /* FEC_ENET */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${uboot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b ${loadaddr} ffe00000 ${filesize};"\ - "save\0" \ - "" - -#define CONFIG_SYS_CLK 150000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -#define CONFIG_SYS_MBAR 0x40000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define CONFIG_SYS_FLASH_SIZE 0x200000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -#define CONFIG_SYS_CS0_BASE 0xffe00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 - -#define CONFIG_SYS_CS1_BASE 0x30000000 -#define CONFIG_SYS_CS1_CTRL 0x00001900 -#define CONFIG_SYS_CS1_MASK 0x00070001 - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CONFIG_SYS_FECI2C 0x0FA0 - -#endif /* _M5275EVB_H */ diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h deleted file mode 100644 index a068726..0000000 --- a/include/configs/M5282EVB.h +++ /dev/null @@ -1,204 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Motorola MC5282EVB board. - * - * (C) Copyright 2003 Josef Baumgartner - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _CONFIG_M5282EVB_H -#define _CONFIG_M5282EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_MCFTMR - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#define CONFIG_ENV_ADDR 0xffe04000 -#define CONFIG_ENV_SIZE 0x2000 - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*); - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* CONFIG_MCFFEC */ - -#define CONFIG_HOSTNAME "M5282EVB" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off ffe00000 ffe3ffff;" \ - "era ffe00000 ffe3ffff;" \ - "cp.b ${loadaddr} ffe00000 ${filesize};"\ - "save\0" \ - "" - -#define CONFIG_SYS_LOAD_ADDR 0x20000 - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -#define CONFIG_SYS_CLK 64000000 - -/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ - -#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -#define CONFIG_SYS_MBAR 0x40000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 - -/* If M5282 port is fully implemented the monitor base will be behind - * the vector table. */ -#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI - -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ - CF_CACR_CEIB | CF_CACR_DBWE | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -#define CONFIG_SYS_CS0_BASE 0xFFE00000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x001F0001 - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 - -#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 - -#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - -#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF - -#endif /* _CONFIG_M5282EVB_H */ diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h deleted file mode 100644 index 39e2748..0000000 --- a/include/configs/M53017EVB.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF53017EVB. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M53017EVB_H -#define _M53017EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 5000 - -#define CONFIG_SYS_UNIFY_CACHE - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_TX_ETH_BUFFER 8 -# define CONFIG_SYS_FEC_BUF_USE_SRAM -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_HAS_ETH1 - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define CONFIG_SYS_FEC1_PINMUX 0 -# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE -# define MCFFEC_TOUT_LOOP 50000 - -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_MCFRTC -#undef RTC_DEBUG -#define CONFIG_SYS_RTC_CNT (0x8000) -#define CONFIG_SYS_RTC_SETUP (RTC_OCEN_OSCBYP | RTC_OCEN_CLKEN) - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -#define CONFIG_UDP_CHECKSUM - -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M53017" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off 0 3ffff;" \ - "era 0 3ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" - -#define CONFIG_PRAM 512 /* 512 KB */ - -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/* - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x20000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x43711630 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x80010000 -#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_FLASH_SPANSION_S29WS_N 1 -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -#endif - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#define CONFIG_ENV_OFFSET (CONFIG_SYS_FLASH_BASE + 0x40000) -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x8000 - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*) - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ - CF_CACR_DCM_P) - -/*----------------------------------------------------------------------- - * Chipselect bank definitions - */ -/* - * CS0 - NOR Flash - * CS1 - Ext SRAM - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00001FA0 - -#define CONFIG_SYS_CS1_BASE 0xC0000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001FA0 - -#endif /* _M53017EVB_H */ diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h deleted file mode 100644 index 7a96dd1..0000000 --- a/include/configs/M5329EVB.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF5329 FireEngine board. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5329EVB_H -#define _M5329EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ - -#define CONFIG_SYS_UNIFY_CACHE - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_MCFRTC -#undef RTC_DEBUG - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -#define CONFIG_UDP_CHECKSUM - -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M5329EVB" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off 0 3ffff;" \ - "era 0 3ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" - -#define CONFIG_PRAM 512 /* 512 KB */ - -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 - -#define CONFIG_SYS_MBAR 0xFC000000 - -#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -#endif - -#ifdef CONFIG_NANDFLASH_SIZE -# define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_SIZE 1 -# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -# define NAND_ALLOW_ERASE_ALL 1 -# define CONFIG_JFFS2_NAND 1 -# define CONFIG_JFFS2_DEV "nand0" -# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) -# define CONFIG_JFFS2_PART_OFFSET 0x00000000 -#endif - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x2000 - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*); - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ - CF_CACR_DCM_P) - -/*----------------------------------------------------------------------- - * Chipselect bank definitions - */ -/* - * CS0 - NOR Flash 1, 2, 4, or 8MB - * CS1 - CompactFlash and registers - * CS2 - NAND Flash 16, 32, or 64MB - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 - -#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 - -#ifdef CONFIG_NANDFLASH_SIZE -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 -#endif - -#endif /* _M5329EVB_H */ diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h deleted file mode 100644 index f62fb5a..0000000 --- a/include/configs/M5373EVB.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF5373 FireEngine board. - * - * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5373EVB_H -#define _M5373EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */ - -#define CONFIG_SYS_UNIFY_CACHE - -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_MCFRTC -#undef RTC_DEBUG - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -#define CONFIG_UDP_CHECKSUM - -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M5373EVB" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off 0 3ffff;" \ - "era 0 3ffff;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" - -#define CONFIG_PRAM 512 /* 512 KB */ - -#define CONFIG_SYS_LOAD_ADDR 0x40010000 - -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 - -#define CONFIG_SYS_MBAR 0xFC000000 - -#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x53722730 -#define CONFIG_SYS_SDRAM_CFG2 0x56670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) -#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -#endif - -#ifdef CONFIG_NANDFLASH_SIZE -# define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE -# define CONFIG_SYS_NAND_SIZE 1 -# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -# define NAND_ALLOW_ERASE_ALL 1 -# define CONFIG_JFFS2_NAND 1 -# define CONFIG_JFFS2_DEV "nand0" -# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) -# define CONFIG_JFFS2_PART_OFFSET 0x00000000 -#endif - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x2000 - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*); - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ - CF_CACR_DCM_P) - -/*----------------------------------------------------------------------- - * Chipselect bank definitions - */ -/* - * CS0 - NOR Flash 1, 2, 4, or 8MB - * CS1 - CompactFlash and registers - * CS2 - NAND Flash 16, 32, or 64MB - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x007f0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fa0 - -#define CONFIG_SYS_CS1_BASE 0x10000000 -#define CONFIG_SYS_CS1_MASK 0x001f0001 -#define CONFIG_SYS_CS1_CTRL 0x002A3780 - -#ifdef CONFIG_NANDFLASH_SIZE -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) -#define CONFIG_SYS_CS2_CTRL 0x00001f60 -#endif - -#endif /* _M5373EVB_H */ diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h deleted file mode 100644 index e07684d..0000000 --- a/include/configs/M54418TWR.h +++ /dev/null @@ -1,309 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF54418 TWR board. - * - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M54418TWR_H -#define _M54418TWR_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -#define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * NAND FLASH - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_JFFS2_NAND -#define CONFIG_NAND_FSL_NFC -#define CONFIG_SYS_NAND_BASE 0xFC0FC000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE -#define CONFIG_SYS_NAND_SELECT_DEVICE -#endif - -/* Network configuration */ -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -#define CONFIG_MII_INIT 1 -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_SYS_RX_ETH_BUFFER 2 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_SYS_TX_ETH_BUFFER 2 -#define CONFIG_HAS_ETH1 - -#define CONFIG_SYS_FEC0_PINMUX 0 -#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -#define CONFIG_SYS_FEC1_PINMUX 0 -#define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE -#define MCFFEC_TOUT_LOOP 50000 -#define CONFIG_SYS_FEC0_PHYADDR 0 -#define CONFIG_SYS_FEC1_PHYADDR 1 - -#define CONFIG_ETHPRIME "FEC0" -#define CONFIG_IPADDR 192.168.1.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 - -#define CONFIG_SYS_FEC_BUF_USE_SRAM -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -#ifndef CONFIG_SYS_DISCOVER_PHY -#define FECDUPLEX FULL -#define FECSPEED _100BASET -#define LINKSTATUS 1 -#else -#define LINKSTATUS 0 -#ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -#endif -#endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_HOSTNAME "M54418TWR" - -#if defined(CONFIG_CF_SBF) -/* ST Micro serial flash */ -#define CONFIG_SYS_LOAD_ADDR2 0x40010007 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "sbfhdr=sbfhdr.bin\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${sbfhdr};" \ - "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:1 1000000 3;" \ - "sf erase 0 40000;" \ - "sf write ${loadaddr} 0 40000;" \ - "save\0" \ - "" -#elif defined(CONFIG_SYS_NAND_BOOT) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot};\0" \ - "upd=run load; run prog\0" \ - "prog=nand device 0;" \ - "nand erase 0 40000;" \ - "nb_update ${loadaddr} ${filesize};" \ - "save\0" \ - "" -#else -#define CONFIG_SYS_UBOOT_END 0x3FFFF -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off mram" " ;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" -#endif - -/* Realtime clock */ -#undef CONFIG_MCFRTC -#define CONFIG_RTC_MCFRRTC -#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2c */ -#undef CONFIG_SYS_FSL_I2C -#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -/* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SERIAL_FLASH -#define CONFIG_SYS_SBFHDR_SIZE 0x7 - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -/* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) -#define CONFIG_SYS_DRAM_TEST - -#if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) -#define CONFIG_SERIAL_BOOT -#endif - -#if defined(CONFIG_SERIAL_BOOT) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) -/* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ -#if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ -#define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ -#define CONFIG_ENV_SIZE 0x1000 -#endif - -#if defined(CONFIG_CF_SBF) -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#endif -#if defined(CONFIG_SYS_NAND_BOOT) -#define CONFIG_ENV_OFFSET 0x80000 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif -#undef CONFIG_ENV_OVERWRITE - -/* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -#ifdef CONFIG_SYS_FLASH_CFI - -/* Max size that the board might have */ -#define CONFIG_SYS_FLASH_SIZE 0x1000000 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -/* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 270 -/* "Real" (hardware) sectors protection */ -#define CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } -#else -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 270 -/* max number of sectors on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 0 -#endif - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_DEV "nand0" -#define CONFIG_JFFS2_PART_OFFSET (0x800000) - -#endif - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ - CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 12) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash 16MB - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ - - /* Flash */ -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x000F0101 -#define CONFIG_SYS_CS0_CTRL 0x00001D60 - -#endif /* _M54418TWR_H */ diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h deleted file mode 100644 index 2bd0e62..0000000 --- a/include/configs/M54451EVB.h +++ /dev/null @@ -1,260 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF54451 EVB board. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M54451EVB_H -#define _M54451EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_M54451EVB /* M54451EVB board */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#define LDS_BOARD_TEXT board/freescale/m54451evb/sbf_dram_init.o (.text*) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Network configuration */ -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 - -# define CONFIG_ETHPRIME "FEC0" -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 - -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_HOSTNAME "M54451EVB" -#ifdef CONFIG_SYS_STMICRO_BOOT -/* ST Micro serial flash */ -#define CONFIG_SYS_LOAD_ADDR2 0x40010007 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "sbfhdr=sbfhdr.bin\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${sbfhdr};" \ - "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:1 1000000 3;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 30000;" \ - "save\0" \ - "" -#else -#define CONFIG_SYS_UBOOT_END 0x3FFFF -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=40010000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \ - "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \ - "cp.b ${loadaddr} 0 ${filesize};" \ - "save\0" \ - "" -#endif - -/* Realtime clock */ -#define CONFIG_MCFRTC -#undef RTC_DEBUG -#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SERIAL_FLASH -#define CONFIG_SYS_SBFHDR_SIZE 0x7 - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x33633F30 -#define CONFIG_SYS_SDRAM_CFG2 0x57670000 -#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00 -#define CONFIG_SYS_SDRAM_EMOD 0x80810000 -#define CONFIG_SYS_SDRAM_MODE 0x008D0000 -#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#ifdef CONFIG_CF_SBF -# define CONFIG_SERIAL_BOOT -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* Configuration for environment - * Environment is not embedded in u-boot. First time runing may have env - * crc error warning if there is no correct environment on the flash. - */ -#if defined(CONFIG_SYS_STMICRO_BOOT) -# define CONFIG_ENV_OFFSET 0x20000 -# define CONFIG_ENV_SIZE 0x2000 -# define CONFIG_ENV_SECT_SIZE 0x10000 -#else -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -# define CONFIG_ENV_SIZE 0x2000 -# define CONFIG_ENV_SECT_SIZE 0x20000 -#endif -#undef CONFIG_ENV_OVERWRITE - -/* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE - -#ifdef CONFIG_SYS_FLASH_CFI - -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } - -#endif - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) -#endif - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ - CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash 16MB - * CS1 - Available - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ - - /* Flash */ -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00004D80 - -#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE - -#endif /* _M54451EVB_H */ diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h deleted file mode 100644 index d73101f..0000000 --- a/include/configs/M54455EVB.h +++ /dev/null @@ -1,376 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF54455 EVB board. - * - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M54455EVB_H -#define _M54455EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_M54455EVB /* M54455EVB board */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*) - -#undef CONFIG_WATCHDOG - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Network configuration */ -#define CONFIG_MCFFEC -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC1_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -# define CONFIG_HAS_ETH1 - -# define CONFIG_ETHPRIME "FEC0" -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 - -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -#define CONFIG_HOSTNAME "M54455EVB" -#ifdef CONFIG_SYS_STMICRO_BOOT -/* ST Micro serial flash */ -#define CONFIG_SYS_LOAD_ADDR2 0x40010013 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "sbfhdr=sbfhdr.bin\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${sbfhdr};" \ - "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ - "upd=run load; run prog\0" \ - "prog=sf probe 0:1 1000000 3;" \ - "sf erase 0 30000;" \ - "sf write ${loadaddr} 0 0x30000;" \ - "save\0" \ - "" -#else -/* Atmel and Intel */ -#ifdef CONFIG_SYS_ATMEL_BOOT -# define CONFIG_SYS_UBOOT_END 0x0403FFFF -#elif defined(CONFIG_SYS_INTEL_BOOT) -# define CONFIG_SYS_UBOOT_END 0x3FFFF -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ - "loadaddr=0x40010000\0" \ - "uboot=u-boot.bin\0" \ - "load=tftp ${loadaddr} ${uboot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ - " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ - __stringify(CONFIG_SYS_UBOOT_END) ";" \ - "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize}; save\0" \ - "" -#endif - -/* ATA configuration */ -#define CONFIG_IDE_RESET 1 -#define CONFIG_IDE_PREINIT 1 -#define CONFIG_ATAPI -#undef CONFIG_LBA48 - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 2 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ -#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ -#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ - -/* Realtime clock */ -#define CONFIG_MCFRTC -#undef RTC_DEBUG -#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2c */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SYS_SBFHDR_SIZE 0x13 - -/* PCI */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4 - -#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_SYS_PCI_IO_BUS 0xB1000000 -#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000 -#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS -#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 -#endif - -/* FPGA - Spartan 2 */ -/* experiment -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_CHECK_CTRLC -*/ - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_PRAM 2048 /* 2048 KB */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) - -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_BASE1 0x48000000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */ -#define CONFIG_SYS_SDRAM_CFG1 0x65311610 -#define CONFIG_SYS_SDRAM_CFG2 0x59670000 -#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x00010033 -#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#ifdef CONFIG_CF_SBF -# define CONFIG_SERIAL_BOOT -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* - * Configuration for environment - * Environment is not embedded in u-boot. First time runing may have env - * crc error warning if there is no correct environment on the flash. - */ -#undef CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_STMICRO_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE -# define CONFIG_ENV_OFFSET 0x30000 -# define CONFIG_ENV_SIZE 0x2000 -# define CONFIG_ENV_SECT_SIZE 0x10000 -#endif -#ifdef CONFIG_SYS_ATMEL_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -# define CONFIG_ENV_SIZE 0x2000 -# define CONFIG_ENV_SECT_SIZE 0x10000 -#endif -#ifdef CONFIG_SYS_INTEL_BOOT -# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE -# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE -# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) -# define CONFIG_ENV_SIZE 0x2000 -# define CONFIG_ENV_SECT_SIZE 0x20000 -#endif - -#ifdef CONFIG_SYS_FLASH_CFI - -# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -# define CONFIG_SYS_FLASH_CHECKSUM -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } -# define CONFIG_FLASH_CFI_LEGACY - -#ifdef CONFIG_FLASH_CFI_LEGACY -# define CONFIG_SYS_ATMEL_REGION 4 -# define CONFIG_SYS_ATMEL_TOTALSECT 11 -# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7} -# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} -#endif -#endif - -/* - * This is setting for JFFS2 support in u-boot. - * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. - */ -#ifdef CONFIG_CMD_JFFS2 -#ifdef CF_STMICRO_BOOT -# define CONFIG_JFFS2_DEV "nor1" -# define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000) -#endif -#ifdef CONFIG_SYS_ATMEL_BOOT -# define CONFIG_JFFS2_DEV "nor1" -# define CONFIG_JFFS2_PART_SIZE 0x01000000 -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000) -#endif -#ifdef CONFIG_SYS_INTEL_BOOT -# define CONFIG_JFFS2_DEV "nor0" -# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) -# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000) -#endif -#endif - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ - CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ -/* - * CS0 - NOR Flash 1, 2, 4, or 8MB - * CS1 - CompactFlash and registers - * CS2 - CPLD - * CS3 - FPGA - * CS4 - Available - * CS5 - Available - */ - -#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT) - /* Atmel Flash */ -#define CONFIG_SYS_CS0_BASE 0x04000000 -#define CONFIG_SYS_CS0_MASK 0x00070001 -#define CONFIG_SYS_CS0_CTRL 0x00001140 -/* Intel Flash */ -#define CONFIG_SYS_CS1_BASE 0x00000000 -#define CONFIG_SYS_CS1_MASK 0x01FF0001 -#define CONFIG_SYS_CS1_CTRL 0x00000D60 - -#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE -#else -/* Intel Flash */ -#define CONFIG_SYS_CS0_BASE 0x00000000 -#define CONFIG_SYS_CS0_MASK 0x01FF0001 -#define CONFIG_SYS_CS0_CTRL 0x00000D60 - /* Atmel Flash */ -#define CONFIG_SYS_CS1_BASE 0x04000000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x00001140 - -#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE -#endif - -/* CPLD */ -#define CONFIG_SYS_CS2_BASE 0x08000000 -#define CONFIG_SYS_CS2_MASK 0x00070001 -#define CONFIG_SYS_CS2_CTRL 0x003f1140 - -/* FPGA */ -#define CONFIG_SYS_CS3_BASE 0x09000000 -#define CONFIG_SYS_CS3_MASK 0x00070001 -#define CONFIG_SYS_CS3_CTRL 0x00000020 - -#endif /* _M54455EVB_H */ diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h deleted file mode 100644 index 7cc09ab..0000000 --- a/include/configs/M5475EVB.h +++ /dev/null @@ -1,256 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF5475 board. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5475EVB_H -#define _M5475EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_HW_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ - -#define CONFIG_SLTTMR - -#define CONFIG_FSLDMAFEC -#ifdef CONFIG_FSLDMAFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_HAS_ETH1 - -# define CONFIG_SYS_DMA_USE_INTSRAM 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 32 -# define CONFIG_SYS_TX_ETH_BUFFER 48 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define CONFIG_SYS_FEC1_PINMUX 0 -# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE - -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ - -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 - -#endif - -#ifdef CONFIG_CMD_USB -# define CONFIG_USB_OHCI_NEW - -# define CONFIG_PCI_OHCI - -# undef CONFIG_SYS_USB_OHCI_BOARD_INIT -# undef CONFIG_SYS_USB_OHCI_CPU_INIT -# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" -# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* PCI */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 - -#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_SYS_PCI_IO_BUS 0x71000000 -#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 -#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS -#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 -#endif - -#define CONFIG_UDP_CHECKSUM - -#ifdef CONFIG_MCFFEC -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 -#endif /* FEC_ENET */ - -#define CONFIG_HOSTNAME "M547xEVB" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off bank 1;" \ - "era ff800000 ff83ffff;" \ - "cp.b ${loadaddr} ff800000 ${filesize};"\ - "save\0" \ - "" - -#define CONFIG_PRAM 512 /* 512 KB */ - -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 - -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) -#define CONFIG_SYS_INTSRAMSZ 0x8000 - -/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 -#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) -#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_CFG1 0x73711630 -#define CONFIG_SYS_SDRAM_CFG2 0x46770000 -#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 -#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA -#ifdef CONFIG_SYS_DRAMSZ1 -# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) -#else -# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ -#endif - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -#ifdef CONFIG_SYS_NOR1SZ -# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } -#else -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) -#endif -#endif - -/* Configuration for environment - * Environment is not embedded in u-boot but at offset 0x40000 on the flash. - * First time runing may have env crc error warning if there is - * no correct environment on the flash. - */ -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ - CF_CACR_IDCM) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ - CF_CACR_IEC | CF_CACR_ICINVA) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -/*----------------------------------------------------------------------- - * Chipselect bank definitions - */ -/* - * CS0 - NOR Flash 1, 2, 4, or 8MB - * CS1 - NOR Flash - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ -#define CONFIG_SYS_CS0_BASE 0xFF800000 -#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) -#define CONFIG_SYS_CS0_CTRL 0x00101980 - -#ifdef CONFIG_SYS_NOR1SZ -#define CONFIG_SYS_CS1_BASE 0xE0000000 -#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) -#define CONFIG_SYS_CS1_CTRL 0x00101D80 -#endif - -#endif /* _M5475EVB_H */ diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h deleted file mode 100644 index 3f5ced2..0000000 --- a/include/configs/M5485EVB.h +++ /dev/null @@ -1,243 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Freescale MCF5485 FireEngine board. - * - * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. - * TsiChung Liew (Tsi-Chung.Liew@freescale.com) - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef _M5485EVB_H -#define _M5485EVB_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_HW_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ - -#define CONFIG_SLTTMR - -#define CONFIG_FSLDMAFEC -#ifdef CONFIG_FSLDMAFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_HAS_ETH1 - -# define CONFIG_SYS_DMA_USE_INTSRAM 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 32 -# define CONFIG_SYS_TX_ETH_BUFFER 48 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define CONFIG_SYS_FEC1_PINMUX 0 -# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE - -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ - -# define CONFIG_IPADDR 192.162.1.2 -# define CONFIG_NETMASK 255.255.255.0 -# define CONFIG_SERVERIP 192.162.1.1 -# define CONFIG_GATEWAYIP 192.162.1.1 - -#endif - -#ifdef CONFIG_CMD_USB -# define CONFIG_USB_OHCI_NEW -/*# define CONFIG_PCI_OHCI*/ -# define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80041000 -# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" -# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* PCI */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 - -#define CONFIG_SYS_PCI_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_SYS_PCI_IO_BUS 0x71000000 -#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS -#define CONFIG_SYS_PCI_IO_SIZE 0x01000000 - -#define CONFIG_SYS_PCI_CFG_BUS 0x70000000 -#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS -#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 -#endif - -#define CONFIG_UDP_CHECKSUM - -#define CONFIG_HOSTNAME "M548xEVB" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "loadaddr=10000\0" \ - "u-boot=u-boot.bin\0" \ - "load=tftp ${loadaddr) ${u-boot}\0" \ - "upd=run load; run prog\0" \ - "prog=prot off bank 1;" \ - "era ff800000 ff83ffff;" \ - "cp.b ${loadaddr} ff800000 ${filesize};"\ - "save\0" \ - "" - -#define CONFIG_PRAM 512 /* 512 KB */ - -#define CONFIG_SYS_LOAD_ADDR 0x00010000 - -#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK -#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 - -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) -#define CONFIG_SYS_INTSRAMSZ 0x8000 - -/*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_CTRL 0x21 -#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) -#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM1_CTRL 0x21 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_CFG1 0x73711630 -#define CONFIG_SYS_SDRAM_CFG2 0x46770000 -#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 -#define CONFIG_SYS_SDRAM_EMOD 0x40010000 -#define CONFIG_SYS_SDRAM_MODE 0x018D0000 -#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA -#ifdef CONFIG_SYS_DRAMSZ1 -# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) -#else -# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ -#endif - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) - -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#ifdef CONFIG_SYS_FLASH_CFI -# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ -#ifdef CONFIG_SYS_NOR1SZ -# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } -#else -# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) -#endif -#endif - -/* Configuration for environment - * Environment is not embedded in u-boot. First time runing may have env - * crc error warning if there is no correct environment on the flash. - */ -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ - CF_CACR_IDCM) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ - CF_CACR_IEC | CF_CACR_ICINVA) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -/*----------------------------------------------------------------------- - * Chipselect bank definitions - */ -/* - * CS0 - NOR Flash 1, 2, 4, or 8MB - * CS1 - NOR Flash - * CS2 - Available - * CS3 - Available - * CS4 - Available - * CS5 - Available - */ -#define CONFIG_SYS_CS0_BASE 0xFF800000 -#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) -#define CONFIG_SYS_CS0_CTRL 0x00101980 - -#ifdef CONFIG_SYS_NOR1SZ -#define CONFIG_SYS_CS1_BASE 0xE0000000 -#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) -#define CONFIG_SYS_CS1_CTRL 0x00101D80 -#endif - -#endif /* _M5485EVB_H */ diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h deleted file mode 100644 index 3c46ae0..0000000 --- a/include/configs/MCR3000.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2017 CS Systemes d'Information - * Christophe Leroy - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "sdram_type=SDRAM\0" \ - "flash_type=AM29LV160DB\0" \ - "loadaddr=0x400000\0" \ - "filename=uImage.lzma\0" \ - "nfsroot=/opt/ofs\0" \ - "dhcp_ip=ip=:::::eth0:dhcp\0" \ - "console_args=console=ttyCPM0,115200N8\0" \ - "flashboot=setenv bootargs " \ - "${console_args} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "mcr3k:eth0:off;" \ - "${ofl_args}; " \ - "bootm 0x04060000 - 0x04050000\0" \ - "tftpboot=setenv bootargs " \ - "${console_args} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "mcr3k:eth0:off " \ - "${ofl_args}; " \ - "tftp ${loadaddr} ${filename};" \ - "tftp 0xf00000 mcr3000.dtb;" \ - "bootm ${loadaddr} - 0xf00000\0" \ - "netboot=dhcp ${loadaddr} ${filename};" \ - "tftp 0xf00000 mcr3000.dtb;" \ - "setenv bootargs " \ - "root=/dev/nfs rw " \ - "${console_args} " \ - "${dhcp_ip};" \ - "bootm ${loadaddr} - 0xf00000\0" \ - "nfsboot=setenv bootargs " \ - "root=/dev/nfs rw nfsroot=${serverip}:${nfsroot} " \ - "${console_args} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "mcr3k:eth0:off;" \ - "bootm 0x04060000 - 0x04050000\0" \ - "dhcpboot=dhcp ${loadaddr} ${filename};" \ - "tftp 0xf00000 mcr3000.dtb;" \ - "setenv bootargs " \ - "${console_args} " \ - "${dhcp_ip} " \ - "${ofl_args}; " \ - "bootm ${loadaddr} - 0xf00000\0" - -#define CONFIG_IPADDR 192.168.0.3 -#define CONFIG_SERVERIP 192.168.0.1 -#define CONFIG_NETMASK 255.0.0.0 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x00002000 -#define CONFIG_SYS_MEMTEST_END 0x00800000 - -#define CONFIG_SYS_LOAD_ADDR 0x200000 - -#define CONFIG_SYS_HZ 1000 - -/* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) -#define CONFIG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) - -/* RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* FLASH organization */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 35 -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) -#define CONFIG_SYS_MONITOR_LEN (320 << 10) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (4096 << 10) - -/* Environment Configuration */ - -/* environment is in FLASH */ -#define CONFIG_ENV_SECT_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_OVERWRITE 1 - -/* Ethernet configuration part */ -#define CONFIG_SYS_DISCOVER_PHY 1 -#define CONFIG_MII_INIT 1 - -/* NAND configuration part */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE 0x0C000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h deleted file mode 100644 index 85d7ff6..0000000 --- a/include/configs/MPC8308RDB.h +++ /dev/null @@ -1,341 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_USE_PIO -#endif - -/* - * On-board devices - * - * TSEC1 is SoC TSEC - * TSEC2 is VSC switch - */ -#define CONFIG_TSEC1 -#define CONFIG_VSC7385_ENET - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of two chips HY5PS12621BFP-C4 from HYNIX - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (6 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x27256222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x121048c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03600100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -/* 127 64KB sectors and 8 8KB top sectors per device */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ - /* 0xFFFF8396 */ - -#ifdef CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 - /* VSC7385 Base address on CS2 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 -#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ - /* 0xFFFE09FF */ -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFE7FE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 -#endif -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * SPI on header J8 - * - * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) - * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. - */ -#ifdef CONFIG_MPC8XXX_SPI -#define CONFIG_USE_SPIFLASH -#endif - -/* - * Board info - revision and where boot from - */ -#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=${consoledev},${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "kernel_addr=FE080000\0" \ - "fdt_addr=FE280000\0" \ - "ramdisk_addr=FE290000\0" \ - "u-boot=mpc8308rdb/u-boot.bin\0" \ - "kernel_addr_r=1000000\0" \ - "fdt_addr_r=C00000\0" \ - "hostname=mpc8308rdb\0" \ - "bootfile=mpc8308rdb/uImage\0" \ - "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ - "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "bootcmd=run flash_self\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8313ERDB_NAND.h b/include/configs/MPC8313ERDB_NAND.h deleted file mode 100644 index 4153d60..0000000 --- a/include/configs/MPC8313ERDB_NAND.h +++ /dev/null @@ -1,404 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. - */ -/* - * mpc8313epb board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 - -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MPC83XX_WAIT_FOR_NAND - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 -#define CONFIG_SPL_MAX_SIZE (4 * 1024) -#define CONFIG_SPL_PAD_TO 0x4000 - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_ELBC 1 - -/* - * On-board devices - * - * TSEC1 is VSC switch - * TSEC2 is SoC TSEC - */ -#define CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 - -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - -/* Early revs of this board will lock up hard when attempting - * to access the PMC registers, unless a JTAG debugger is - * connected, or some resistor modifications are made. - */ -#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 - -/* - * Device configurations - */ - -/* Vitesse 7385 */ - -#ifdef CONFIG_VSC7385_ENET - -#define CONFIG_TSEC1 - -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFE7FE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 - -#endif - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ - -/* - * Manually set up DDR parameters, as this board does not - * seem to have the SPD connected to I2C. - */ -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (10 << TIMING_CFG1_REFREC_SHIFT) \ - | (3 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3835a322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (5 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x129048c6 */ /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x05100500 */ -#if defined(CONFIG_DDR_2T_TIMING) -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32 \ - | SDRAM_CFG_2T_EN) - /* 0x43088000 */ -#else -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ -#endif -#define CONFIG_SYS_SDRAM_CFG2 0x00401000 -/* set burst length to 8 for 32-bit data path */ -#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0632 << SDRAM_MODE_SD_SHIFT)) - /* 0x44480632 */ -#define CONFIG_SYS_DDR_MODE_2 0x8000C000 - -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - /*0x02000000*/ -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_NOMZ \ - | DDRCDR_NZ_NOMZ \ - | DDRCDR_M_ODR) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ - !defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* drivers/mtd/nand/raw/nand.c */ -#if defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_NAND_BASE 0xFFF00000 -#else -#define CONFIG_SYS_NAND_BASE 0xE2800000 -#endif - -#define CONFIG_MTD_PARTITION - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) - -/* Still needed for spl_minimal.c */ -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM - -/* local bus write LED / read status buffer (BCSR) mapping */ -#define CONFIG_SYS_BCSR_ADDR 0xFA000000 -#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ - /* map at 0xFA000000 on LCS3 */ - -/* Vitesse 7385 */ - -#ifdef CONFIG_VSC7385_ENET - - /* VSC7385 Base address on LCS2 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 -#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ - - -#endif - -#define CONFIG_MPC83XX_GPIO 1 - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -/* - * TSEC - */ - -#define CONFIG_GMII /* MII PHY management */ - -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1c -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define TSEC2_PHY_ADDR 4 -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC2_PHYIDX 0 -#endif - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC1" - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Environment - */ -#define CONFIG_ENV_OFFSET (512 * 1024) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4) -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) - -/* System IO Config */ -#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ - /* Enable Internal USB Phy and GPIO on LCD Connector */ -#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NETDEV "eth1" - -#define CONFIG_HOSTNAME "mpc8313erdb" -#define CONFIG_ROOTPATH "/nfs/root/path" -#define CONFIG_BOOTFILE "uImage" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" -#define CONFIG_FDTFILE "mpc8313erdb.dtb" - - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 800000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" CONFIG_NETDEV "\0" \ - "ethprime=TSEC1\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" \ - "console=ttyS0\0" \ - "setbootargs=setenv bootargs " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ - "$netdev:off " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv rootdev /dev/nfs;" \ - "run setbootargs;" \ - "run setipargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv rootdev /dev/ram;" \ - "run setbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8313ERDB_NOR.h b/include/configs/MPC8313ERDB_NOR.h deleted file mode 100644 index ff8dedf..0000000 --- a/include/configs/MPC8313ERDB_NOR.h +++ /dev/null @@ -1,377 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. - */ -/* - * mpc8313epb board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_FSL_ELBC 1 - -/* - * On-board devices - * - * TSEC1 is VSC switch - * TSEC2 is SoC TSEC - */ -#define CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 - -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - -/* Early revs of this board will lock up hard when attempting - * to access the PMC registers, unless a JTAG debugger is - * connected, or some resistor modifications are made. - */ -#define CONFIG_SYS_8313ERDB_BROKEN_PMC 1 - -/* - * Device configurations - */ - -/* Vitesse 7385 */ - -#ifdef CONFIG_VSC7385_ENET - -#define CONFIG_TSEC1 - -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFE7FE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 - -#endif - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ - -/* - * Manually set up DDR parameters, as this board does not - * seem to have the SPD connected to I2C. - */ -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (8 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (10 << TIMING_CFG1_REFREC_SHIFT) \ - | (3 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3835a322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (5 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x129048c6 */ /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_INTERVAL ((1296 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x05100500 */ -#if defined(CONFIG_DDR_2T_TIMING) -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32 \ - | SDRAM_CFG_2T_EN) - /* 0x43088000 */ -#else -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ -#endif -#define CONFIG_SYS_SDRAM_CFG2 0x00401000 -/* set burst length to 8 for 32-bit data path */ -#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0632 << SDRAM_MODE_SD_SHIFT)) - /* 0x44480632 */ -#define CONFIG_SYS_DDR_MODE_2 0x8000C000 - -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - /*0x02000000*/ -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_NOMZ \ - | DDRCDR_NZ_NOMZ \ - | DDRCDR_M_ODR) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) && \ - !defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* drivers/mtd/nand/nand.c */ -#define CONFIG_SYS_NAND_BASE 0xE2800000 - -#define CONFIG_MTD_PARTITION - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) - -/* Still needed for spl_minimal.c */ -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM - -/* local bus write LED / read status buffer (BCSR) mapping */ -#define CONFIG_SYS_BCSR_ADDR 0xFA000000 -#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ - /* map at 0xFA000000 on LCS3 */ -/* Vitesse 7385 */ - -#ifdef CONFIG_VSC7385_ENET - - /* VSC7385 Base address on LCS2 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 -#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ - - -#endif - -#define CONFIG_MPC83XX_GPIO 1 - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -/* - * TSEC - */ - -#define CONFIG_GMII /* MII PHY management */ - -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1c -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define TSEC2_PHY_ADDR 4 -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC2_PHYIDX 0 -#endif - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC1" - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * Environment - */ -#if !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) - -/* System IO Config */ -#define CONFIG_SYS_SICRH (SICRH_TSOBI1 | SICRH_TSOBI2) /* RGMII */ - /* Enable Internal USB Phy and GPIO on LCD Connector */ -#define CONFIG_SYS_SICRL (SICRL_USBDR_10 | SICRL_LBC) - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NETDEV "eth1" - -#define CONFIG_HOSTNAME "mpc8313erdb" -#define CONFIG_ROOTPATH "/nfs/root/path" -#define CONFIG_BOOTFILE "uImage" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" -#define CONFIG_FDTFILE "mpc8313erdb.dtb" - - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 800000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" CONFIG_NETDEV "\0" \ - "ethprime=TSEC1\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" \ - "console=ttyS0\0" \ - "setbootargs=setenv bootargs " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ - "$netdev:off " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv rootdev /dev/nfs;" \ - "run setbootargs;" \ - "run setipargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv rootdev /dev/ram;" \ - "run setbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h deleted file mode 100644 index 521c5ca..0000000 --- a/include/configs/MPC8315ERDB.h +++ /dev/null @@ -1,390 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. - * - * Dave Liu - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */ - -#define CONFIG_HWCONFIG - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of two chips HY5PS12621BFP-C4 from HYNIX - */ -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (6 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x27256222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x121048c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03600100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00140000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_FSL_ELBC - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -/* 127 64KB sectors and 8 8KB top sectors per device */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ - -#ifdef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xFFF00000 -#else -#define CONFIG_SYS_NAND_BASE 0xE0600000 -#endif - -#define CONFIG_MTD_PARTITION - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 -#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 - - - -/* Still needed for spl_minimal.c */ -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM - -#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \ - !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Board info - revision and where boot from - */ -#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_SYS_SCCR_USBDRCM 3 - -#define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_PHY_TYPE "utmi" -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC1" - -/* - * SATA - */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* - * Environment - */ -#if !defined(CONFIG_SYS_RAMBOOT) - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * MMU Setup - */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc8315erdb.dtb\0" \ - "usb_phy_type=utmi\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h deleted file mode 100644 index 94c2a61..0000000 --- a/include/configs/MPC8323ERDB.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published - * by the Free Software Foundation. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ - -#undef CONFIG_SPD_EEPROM -#if defined(CONFIG_SPD_EEPROM) -/* Determine DDR configuration from I2C interface - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ -#else -/* Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 64 /* MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_9) - /* 0x80010101 */ -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (3 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26253222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (31 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x1f9048c7 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - /* 0x02000000 */ -#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* 0x44480232 */ -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03200064 */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE) - /* 0x43080000 */ -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#endif - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x03f00000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ - - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Config on-board EEPROM - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_SKIP_HOST_BRIDGE - -#undef CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* ETH3 */ - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 4 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -#define CONFIG_UEC_ETH2 /* ETH4 */ - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x20000 - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if (CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ -#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ - -/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM - * (see CONFIG_SYS_I2C_EEPROM) */ - /* MAC address offset in I2C EEPROM */ -#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 - -#define CONFIG_NETDEV "eth1" - -#define CONFIG_HOSTNAME "mpc8323erdb" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "uImage" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" -#define CONFIG_FDTFILE "mpc832x_rdb.dtb" -#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" - - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 800000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" CONFIG_NETDEV "\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "tftpflash=tftp $loadaddr $uboot;" \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ - "console=ttyS0\0" \ - "setbootargs=setenv bootargs " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\ - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ - "$netdev:off "\ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv rootdev /dev/nfs;" \ - "run setbootargs;" \ - "run setipargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv rootdev /dev/ram;" \ - "run setbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h deleted file mode 100644 index 26a4407..0000000 --- a/include/configs/MPC832XEMDS.h +++ /dev/null @@ -1,322 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ - -#undef CONFIG_SPD_EEPROM -#if defined(CONFIG_SPD_EEPROM) -/* Determine DDR configuration from I2C interface - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ -#else -/* Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_AP \ - | CSCONFIG_ODT_WR_CFG \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - /* 0x80840102 */ -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (13 << TIMING_CFG1_REFREC_SHIFT) \ - | (3 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3935D322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (31 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x0F9048CA */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - /* 0x02000000 */ -#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* 0x44400232 */ -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03200064 */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE) - /* 0x43080000 */ -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#endif - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM - -/* - * BCSR on the Local Bus - */ -#define CONFIG_SYS_BCSR 0xF8000000 - /* Access window base at BCSR base */ - - -/* - * Windows to access PIB via local bus - */ - /* PIB window base 0xF8008000 */ -#define CONFIG_SYS_PIB_BASE 0xF8008000 -#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) - -/* - * CS2 on Local Bus, to PIB - */ - - -/* - * CS3 on Local Bus, to PIB - */ - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_83XX_PCI_STREAMING - -#undef CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" - -#define CONFIG_UEC_ETH1 /* ETH3 */ - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 3 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 -#endif - -#define CONFIG_UEC_ETH2 /* ETH4 */ - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7 -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 4 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 -#endif - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x20000 - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ #define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc832x_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h deleted file mode 100644 index 7352e34..0000000 --- a/include/configs/MPC8349EMDS.h +++ /dev/null @@ -1,394 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * mpc8349emds board configuration file - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * DDR Setup - */ -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver - * unselect it to use old spd_sdram.c - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x52 -#define SPD_EEPROM_ADDRESS2 0x51 -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#undef CONFIG_DDR_2T_TIMING - -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 - -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x47d00432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#else -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ - -#if defined(CONFIG_DDR_32BIT) -/* set burst length to 8 for 32-bit data path */ - /* DLL,normal,seq,4/2.5, 8 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000023 -#else -/* the default burst length is 4 - for 64-bit data path */ - /* DLL,normal,seq,4/2.5, 4 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000022 -#endif -#endif -#endif - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for MDS config reg - */ -#define CONFIG_SYS_BCSR 0xE2400000 - /* Access window base at BCSR base */ - - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* SPI */ -#undef CONFIG_SOFT_SPI /* SPI bit-banged */ - -/* GPIOs. Used as SPI chip selects */ -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ -#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* USB */ -#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_83XX_PCI_STREAMING - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* - * System performance - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "mpc8349emds" -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=mpc8349emds\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ - "update=protect off fe000000 fe03ffff; " \ - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc834x_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h deleted file mode 100644 index 2ae1069..0000000 --- a/include/configs/MPC8349EMDS_SDRAM.h +++ /dev/null @@ -1,451 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * mpc8349emds board configuration file - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * DDR Setup - */ -#define CONFIG_DDR_ECC /* support DDR ECC function */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ - -/* - * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver - * unselect it to use old spd_sdram.c - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x52 -#define SPD_EEPROM_ADDRESS2 0x51 -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#undef CONFIG_DDR_2T_TIMING - -/* - * DDRCDR - DDR Control Driver Register - */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 - -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ -#else -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#if defined(CONFIG_DDR_II) -#define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x47d00432 -#define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#else -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ - -#if defined(CONFIG_DDR_32BIT) -/* set burst length to 8 for 32-bit data path */ - /* DLL,normal,seq,4/2.5, 8 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000023 -#else -/* the default burst length is 4 - for 64-bit data path */ - /* DLL,normal,seq,4/2.5, 4 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000022 -#endif -#endif -#endif - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* - * BCSR register on local bus 32KB, 8-bit wide for MDS config reg - */ -#define CONFIG_SYS_BCSR 0xE2400000 - /* Access window base at BCSR base */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. - */ - -/* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 - */ - - - /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_LSRT 0x32000000 - /* LB refresh timer prescal, 266MHz/32 */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 - -#define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ - | LSDMR_BSMA1516 \ - | LSDMR_RFCR8 \ - | LSDMR_PRETOACT6 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC3 \ - | LSDMR_CL3) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* SPI */ -#undef CONFIG_SOFT_SPI /* SPI bit-banged */ - -/* GPIOs. Used as SPI chip selects */ -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ -#define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* USB */ -#define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_83XX_PCI_STREAMING - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Configure on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* - * System performance - */ -#define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ -#define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_HOSTNAME "mpc8349emds" -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=mpc8349emds\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ - "update=protect off fe000000 fe03ffff; " \ - "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc834x_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h deleted file mode 100644 index c395d62..0000000 --- a/include/configs/MPC8349ITX.h +++ /dev/null @@ -1,454 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - */ - -/* - MPC8349E-mITX and MPC8349E-mITX-GP board configuration file - - Memory map: - - 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) - 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) - 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) - 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) - 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) - 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) - 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) - 0xF001_0000-0xF001_FFFF Local bus expansion slot - 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) - 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory - 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) - - I2C address list: - Align. Board - Bus Addr Part No. Description Length Location - ---------------------------------------------------------------- - I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 - - I2C1 0x20 PCF8574 I2C Expander 0 U8 - I2C1 0x21 PCF8574 I2C Expander 0 U10 - I2C1 0x38 PCF8574A I2C Expander 0 U8 - I2C1 0x39 PCF8574A I2C Expander 0 U10 - I2C1 0x51 (DDR) DDR EEPROM 1 U1 - I2C1 0x68 DS1339 RTC 1 U68 - - Note that a given board has *either* a pair of 8574s or a pair of 8574As. -*/ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MISC_INIT_F - -/* - * On-board devices - */ - -#ifdef CONFIG_TARGET_MPC8349ITX -/* The CF card interface on the back of the board */ -#define CONFIG_COMPACT_FLASH -#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ -#define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ -#endif - -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_I2C - -/* - * Device configurations - */ - -/* I2C */ -#ifdef CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -#define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ -#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ - -#define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ -#define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ -#define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ -#define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ -#define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ - -/* Don't probe these addresses: */ -#define CONFIG_SYS_I2C_NOPROBES { {1, CONFIG_SYS_I2C_8574_ADDR1}, \ - {1, CONFIG_SYS_I2C_8574_ADDR2}, \ - {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ - {1, CONFIG_SYS_I2C_8574A_ADDR2} } -/* Bit definitions for the 8574[A] I2C expander */ - /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ -#define I2C_8574_REVISION 0x03 -#define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ -#define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ -#define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ -#define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ - -#endif - -/* Compact Flash */ -#ifdef CONFIG_COMPACT_FLASH - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE -#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 -#define CONFIG_SYS_ATA_STRIDE 2 - -/* If a CF card is not inserted, time out quickly */ -#define ATA_RESET_TIME 1 - -#endif - -/* - * SATA - */ -#ifdef CONFIG_SATA_SIL3114 - -#define CONFIG_SYS_SATA_MAX_DEVICE 4 -#define CONFIG_LBA48 - -#endif - -#ifdef CONFIG_SYS_USB_HOST -/* - * Support USB - */ -#define CONFIG_USB_EHCI_FSL - -/* Current USB implementation supports the only USB controller, - * so we have to choose between the MPH or the DR ones */ -#if 1 -#define CONFIG_HAS_FSL_MPH_USB -#else -#define CONFIG_HAS_FSL_DR_USB -#endif - -#endif - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_83XX_DDR_USES_CS0 -#define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x2000 - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) - -#ifdef CONFIG_SYS_I2C -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ -#endif - -/* No SPD? Then manually set up DDR parameters */ -#ifndef CONFIG_SPD_EEPROM - #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ - #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - - #define CONFIG_SYS_DDR_TIMING_1 0x26242321 - #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ -#endif - -/* - *Flash on the Local Bus - */ - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -/* 127 64KB sectors + 8 8KB sectors per device */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -/* The ITX has two flash chips, but the ITX-GP has only one. To support both -boards, we say we have two, but don't display a message if we find only one. */ -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ - -/* Vitesse 7385 */ - -#ifdef CONFIG_VSC7385_ENET - -#define CONFIG_TSEC2 - -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFEFFE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 - -#endif - -/* - * BRx, ORx, LBLAWBARx, and LBLAWARx - */ - - -/* Vitesse 7385 */ - -#define CONFIG_SYS_VSC7385_BASE 0xF8000000 - -#define CONFIG_SYS_LED_BASE 0xF9000000 - - -/* Compact Flash */ - -#ifdef CONFIG_COMPACT_FLASH - -#define CONFIG_SYS_CF_BASE 0xF0000000 - - -#endif - -/* - * U-Boot memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONSOLE ttyS0 - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* - * PCI - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_MPC83XX_PCI2 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE \ - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE \ - (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE \ - (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS \ - (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ -#endif - -#ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR 0x00000000 - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE - #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif - -/* TSEC */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_TSEC1 - -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 - -#define TSEC2_PHY_ADDR 4 -#define TSEC2_PHYIDX 0 -#define TSEC2_FLAGS TSEC_GIGABIT -#endif - -#define CONFIG_ETHPRIME "Freescale TSEC" - -#endif - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Watchdog */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * System performance - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ -#define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ - -/* - * System IO Config - */ -/* Needed for gigabit to work on TSEC 1 */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 - /* USB DR as device + USB MPH as host */ -#define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_NETDEV "eth0" - -/* Default path and filenames */ -#define CONFIG_ROOTPATH "/nfsroot/rootfs" -#define CONFIG_BOOTFILE "uImage" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" - -#ifdef CONFIG_TARGET_MPC8349ITX -#define CONFIG_FDTFILE "mpc8349emitx.dtb" -#else -#define CONFIG_FDTFILE "mpc8349emitxgp.dtb" -#endif - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=" __stringify(CONSOLE) "\0" \ - "netdev=" CONFIG_NETDEV "\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ - " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\ - " console=$console,$baudrate $othbootargs; " \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw" \ - " console=$console,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h deleted file mode 100644 index 724f8af..0000000 --- a/include/configs/MPC837XEMDS.h +++ /dev/null @@ -1,390 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * Dave Liu - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * IP blocks clock configuration - */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * Output Buffer Impedance - */ -#define CONFIG_SYS_OBIR 0x31100000 - -#define CONFIG_HWCONFIG - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_83XX_DDR_USES_CS0 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x80080001 */ /* ODT 150ohm on SoC */ - -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ - -#if defined(CONFIG_SPD_EEPROM) -#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ -#else -/* - * Manually set up DDR parameters - * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM - * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 - */ -#define CONFIG_SYS_DDR_SIZE 512 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ - | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ - | CSCONFIG_ROW_BIT_14 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010202 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00620802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (13 << TIMING_CFG1_REFREC_SHIFT) \ - | (3 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3935d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (6 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x131088c8 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03E00100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x1432 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 -#endif - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00140000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_FSL_ELBC 1 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * BCSR on the Local Bus - */ -#define CONFIG_SYS_BCSR 0xF8000000 - /* Access window base at BCSR base */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 - -#define CONFIG_SYS_NAND_BASE 0xE0600000 - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#ifndef __ASSEMBLY__ -extern int board_pci_host_broken(void); -#endif -#define CONFIG_PCIE -#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ - -#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */ -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#undef CONFIG_EEPRO100 -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#endif /* CONFIG_PCI */ - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 -#define TSEC1_PHY_ADDR_SGMII 8 -#define TSEC2_PHY_ADDR_SGMII 4 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC1" - -/* SERDES */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 - -/* - * SATA - */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_PIN_MUX -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=780000\0" \ - "fdtfile=mpc8379_mds.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h deleted file mode 100644 index 37f51ba..0000000 --- a/include/configs/MPC837XERDB.h +++ /dev/null @@ -1,428 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007 Freescale Semiconductor, Inc. - * Kevin Lam - * Joe D'Abbraccio - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#define CONFIG_HWCONFIG - -/* - * On-board devices - */ -#define CONFIG_VSC7385_ENET - -/* System performance - define the value i.e. CONFIG_SYS_XXX -*/ - -/* System Clock Configuration Register */ -#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ -#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */ - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRH 0x08200000 -#define CONFIG_SYS_SICRL 0x00000000 - -/* - * Output Buffer Impedance - */ -#define CONFIG_SYS_OBIR 0x30100000 - -/* - * Device configurations - */ - -/* Vitesse 7385 */ - -#ifdef CONFIG_VSC7385_ENET - -#define CONFIG_TSEC2 - -/* The flash address and size of the VSC7385 firmware image */ -#define CONFIG_VSC7385_IMAGE 0xFE7FE000 -#define CONFIG_VSC7385_IMAGE_SIZE 8192 - -#endif - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 -#define CONFIG_SYS_83XX_DDR_USES_CS0 - -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) - -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - -#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ - -/* - * Manually set up DDR parameters - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00260802 */ /* DDR400 */ -#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (7 << TIMING_CFG1_CASLAT_SHIFT) \ - | (13 << TIMING_CFG1_REFREC_SHIFT) \ - | (3 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3937d322 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (5 << TIMING_CFG2_CPO_SHIFT) \ - | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x02984cc8 */ - -#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x06090100 */ - -#if defined(CONFIG_DDR_2T_TIMING) -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE \ - | SDRAM_CFG_2T_EN) - /* 0x43088000 */ -#else -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2) - /* 0x43000000 */ -#endif -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0442 << SDRAM_MODE_SD_SHIFT)) - /* 0x04400442 */ /* DDR400 */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x0ef70010 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_FSL_ELBC 1 - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* - * NAND Flash on the Local Bus - */ -#define CONFIG_SYS_NAND_BASE 0xE0600000 - - -/* Vitesse 7385 */ - -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* SERDES */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 -#define CONFIG_FSL_SERDES2 0xe3100 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } - -/* - * Config on-board RTC - */ -#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE -#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE -#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000 -#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 -#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000 - -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#endif /* CONFIG_PCI */ - -/* - * TSEC - */ -#ifdef CONFIG_TSEC_ENET - -#define CONFIG_GMII /* MII PHY management */ - -#define CONFIG_TSEC1 - -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 2 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define TSEC2_PHY_ADDR 0x1c -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_PHYIDX 0 -#endif - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif - -/* - * SATA - */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET) -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET) -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#ifdef CONFIG_FSL_SATA -#define CONFIG_LBA48 -#endif - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ - #define CONFIG_ENV_SIZE 0x4000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_PIN_MUX -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_NETDEV "eth1" - -#define CONFIG_HOSTNAME "mpc837x_rdb" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" -#define CONFIG_BOOTFILE "uImage" - /* U-Boot image on TFTP server */ -#define CONFIG_UBOOTPATH "u-boot.bin" -#define CONFIG_FDTFILE "mpc8379_rdb.dtb" - - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 800000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" CONFIG_NETDEV "\0" \ - "uboot=" CONFIG_UBOOTPATH "\0" \ - "tftpflash=tftp $loadaddr $uboot;" \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "fdtaddr=780000\0" \ - "fdtfile=" CONFIG_FDTFILE "\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ - "console=ttyS0\0" \ - "setbootargs=setenv bootargs " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ - "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "root=$rootdev rw console=$console,$baudrate $othbootargs\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv rootdev /dev/nfs;" \ - "run setbootargs;" \ - "run setipargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv rootdev /dev/ram;" \ - "run setbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h deleted file mode 100644 index 7697e8d..0000000 --- a/include/configs/MPC8536DS.h +++ /dev/null @@ -1,654 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc. - */ - -/* - * mpc8536ds board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD 1 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH 1 -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_PCI1 1 /* Enable PCI controller 1 */ -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ -#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ - -/* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -#if defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ -#define CONFIG_SYS_SPD_BUS_NUM 1 - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 -#define CONFIG_SYS_DDR_MODE_1 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x06180100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x04400010 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Memory map -- xxx -this is wrong, needs updating - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_BR1_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ - CONFIG_SYS_FLASH_BASE_PHYS } -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 - -#define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ -#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ -#ifdef CONFIG_PHYS_64BIT -#define PIXIS_BASE_PHYS 0xfffdf0000ull -#else -#define PIXIS_BASE_PHYS PIXIS_BASE -#endif - -#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ - -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_PWR 0x5 /* PIXIS Power status register */ -#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VSTAT 0x11 /* VELA Status Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ -#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ -#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ -#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ -#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ -#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ -#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ -#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ -#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ -#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ -#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ -#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ -#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ -#define PIXIS_VWATCH 0x24 /* Watchdog Register */ -#define PIXIS_LED 0x25 /* LED Register */ - -#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ - -/* old pixis referenced names */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#else -#define CONFIG_SYS_NAND_BASE 0xfff00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#endif -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ - CONFIG_SYS_NAND_BASE + 0x40000, \ - CONFIG_SYS_NAND_BASE + 0x80000, \ - CONFIG_SYS_NAND_BASE + 0xC0000} -#define CONFIG_SYS_MAX_NAND_DEVICE 4 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START \ - (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< PHY1 */ -#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ - -#if defined(CONFIG_SYS_RAMBOOT) -#if defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0xF0000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_MPH_USB -#ifdef CONFIG_HAS_FSL_MPH_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.254 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=8536ds/ramdisk.uboot\0" \ -"fdtaddr=1e00000\0" \ -"fdtfile=8536ds/mpc8536ds.dtb\0" \ -"bdev=sda3\0" \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h deleted file mode 100644 index 13ca2c3..0000000 --- a/include/configs/MPC8540ADS.h +++ /dev/null @@ -1,375 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - */ - -/* - * mpc8540ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * default CCARBAR is at 0xff700000 - * assume U-Boot is less than 0.5MB - */ - -#ifndef CONFIG_HAS_FEC -#define CONFIG_HAS_FEC 1 /* 8540 has FEC */ -#endif - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_ENV_OVERWRITE - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - * - * XXX -- Can't we run at 66 MHz, anyway? PCI should drop to - * 33MHz to accommodate, based on a PCI pin. - * Note that PCI-X won't work at 33MHz. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ - | LSDMR_RFCR5 \ - | LSDMR_PRETOACT3 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC2 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CONFIG_SYS_BR4_PRELIM 0xf8000801 -#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 -#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -#if CONFIG_HAS_FEC -#define CONFIG_MPC85XX_FEC 1 -#define CONFIG_MPC85XX_FEC_NAME "FEC" -#define FEC_PHY_ADDR 3 -#define FEC_PHYIDX 0 -#define FEC_FLAGS 0 -#endif - -/* Options are: TSEC[0-1], FEC */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h deleted file mode 100644 index e00a56e..0000000 --- a/include/configs/MPC8541CDS.h +++ /dev/null @@ -1,397 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - */ - -/* - * mpc8541cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_CPM2 1 /* has CPM2 */ - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_VIA - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CONFIG_SYS_BR0_PRELIM 0xff801001 -#define CONFIG_SYS_BR1_PRELIM 0xff001001 - -#define CONFIG_SYS_OR0_PRELIM 0xff806e65 -#define CONFIG_SYS_OR1_PRELIM 0xff806e65 - -#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ - | LSDMR_PRETOACT7 \ - | LSDMR_ACTTORW7 \ - | LSDMR_BL8 \ - | LSDMR_WRC4 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CONFIG_FSL_CADMUS - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CONFIG_SYS_BR3_PRELIM 0xf8000801 -#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_CCID -#define CONFIG_SYS_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x100000 /* 1M */ - -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - -#if defined(CONFIG_PCI) - -#define CONFIG_MPC85XX_PCI2 - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h deleted file mode 100644 index 2cbe855..0000000 --- a/include/configs/MPC8544DS.h +++ /dev/null @@ -1,422 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc. - */ - -/* - * mpc8544ds board configuration file - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_PCI1 1 /* PCI controller 1 */ -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * - * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * - * Localbus cacheable - * - * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable - * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 - * - * Localbus non-cacheable - * - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable - * - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */ - -#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */ - -#define CONFIG_SYS_BR0_PRELIM 0xff801001 -#define CONFIG_SYS_BR1_PRELIM 0xfe801001 - -#define CONFIG_SYS_OR0_PRELIM 0xff806e65 -#define CONFIG_SYS_OR1_PRELIM 0xff806e65 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 - -#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */ -#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ - -#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ - -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ -#define PIXIS_BASE 0xf8100000 /* PIXIS registers */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch - * register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ -#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ -#define PIXIS_VSPEED2_TSEC1SER 0x2 -#define PIXIS_VSPEED2_TSEC3SER 0x1 -#define PIXIS_VCFGEN1_TSEC1SER 0x20 -#define PIXIS_VCFGEN1_TSEC3SER 0x40 -#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER) -#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER) - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */ -#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ -#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */ -#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ - -#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 1, tgtid 1, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "Slot 1" -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, Slot 2,tgtid 2, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "Slot 2" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, direct to uli, tgtid 3, Base address b000 */ -#define CONFIG_SYS_PCIE3_NAME "ULI" -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */ -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */ -#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000 -#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000 -#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000 -#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */ - -#if defined(CONFIG_PCI) - -/*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT - -/*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ - -/* video */ - -#if defined(CONFIG_VIDEO) -#define CONFIG_BIOSEMU -#define CONFIG_ATI_RADEON_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET -#endif - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#ifndef CONFIG_PCI_PNP - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS - #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_SATA_ULI5288 -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) -#endif /* CONFIG_SCSI_AHCI */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define CONFIG_PIXIS_SGMII_CMD -#define CONFIG_FSL_SGMII_RISER 1 -#define SGMII_RISER_PHY_OFFSET 0x1c - -#define TSEC1_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ -#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * USB - */ - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_PCI_EHCI_DEVICE 0 -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_IPADDR 192.168.1.251 - -#define CONFIG_HOSTNAME "8544ds_unknown" -#define CONFIG_ROOTPATH "/nfs/mpc85xx" -#define CONFIG_BOOTFILE "8544ds/uImage.uboot" -#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.0.0 - -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=8544ds/ramdisk.uboot\0" \ -"fdtaddr=1e00000\0" \ -"fdtfile=8544ds/mpc8544ds.dtb\0" \ -"bdev=sda3\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h deleted file mode 100644 index 3a8c074..0000000 --- a/include/configs/MPC8548CDS.h +++ /dev/null @@ -1,530 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. - */ - -/* - * mpc8548cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCI1 /* PCI controller 1 */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#undef CONFIG_PCI2 -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - -#define CONFIG_FSL_VIA - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD - -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ -/* - * Physical Address Map - * - * 32bit: - * 0x0000_0000 0x7fff_ffff DDR 2G cacheable - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable - * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable - * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable - * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable - * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable - * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable - * 0xf000_0000 0xf3ff_ffff SDRAM 64M cacheable - * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS 1M non-cacheable - * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable - * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable - * - * 36bit: - * 0x00000_0000 0x07fff_ffff DDR 2G cacheable - * 0xc0000_0000 0xc1fff_ffff PCI1 MEM 512M cacheable - * 0xc2000_0000 0xc3fff_ffff PCIe MEM 512M cacheable - * 0xc4000_0000 0xc5fff_ffff RapidIO 512M cacheable - * 0xfe000_0000 0xfe00f_ffff CCSR 1M non-cacheable - * 0xfe200_0000 0xfe20f_ffff PCI1 IO 1M non-cacheable - * 0xfe300_0000 0xfe30f_ffff PCIe IO 1M non-cacheable - * 0xff000_0000 0xff3ff_ffff SDRAM 64M cacheable - * 0xff800_0000 0xff80f_ffff NVRAM/CADMUS 1M non-cacheable - * 0xfff00_0000 0xfff7f_ffff FLASH (2nd bank) 8M non-cacheable - * 0xfff80_0000 0xfffff_ffff FLASH (boot bank) 8M non-cacheable - * - */ - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_BR0_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V) -#define CONFIG_SYS_BR1_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) - -#define CONFIG_SYS_OR0_PRELIM 0xff806e65 -#define CONFIG_SYS_OR1_PRELIM 0xff806e65 - -#define CONFIG_SYS_FLASH_BANKS_LIST \ - {CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_HWCONFIG /* enable hwconfig */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS 0xff0000000ull -#else -#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS CONFIG_SYS_LBC_SDRAM_BASE -#endif -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \ - | BR_PS_32 | (3< 0xfff80000 -#define CONFIG_ENV_ADDR 0xfff80000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "8548cds/uImage.uboot" -#define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ecc=off\0" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=mpc8548cds.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h deleted file mode 100644 index 5b39334..0000000 --- a/include/configs/MPC8555CDS.h +++ /dev/null @@ -1,393 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - */ - -/* - * mpc8555cds board configuration file - * - * Please refer to doc/README.mpc85xxcds for more info. - * - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_CPM2 1 /* has CPM2 */ - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_FSL_VIA - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */ - -#define CONFIG_SYS_BR0_PRELIM 0xff801001 -#define CONFIG_SYS_BR1_PRELIM 0xff001001 - -#define CONFIG_SYS_OR0_PRELIM 0xff806e65 -#define CONFIG_SYS_OR1_PRELIM 0xff806e65 - -#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ - | LSDMR_PRETOACT7 \ - | LSDMR_ACTTORW7 \ - | LSDMR_BL8 \ - | LSDMR_WRC4 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * The CADMUS registers are connected to CS3 on CDS. - * The new memory map places CADMUS at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ - -#define CONFIG_FSL_CADMUS - -#define CADMUS_BASE_ADDR 0xf8000000 -#define CONFIG_SYS_BR3_PRELIM 0xf8000801 -#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_CCID -#define CONFIG_SYS_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000 -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - -#if defined(CONFIG_PCI) - -#define CONFIG_MPC85XX_PCI2 - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h deleted file mode 100644 index 5ba2b6d..0000000 --- a/include/configs/MPC8560ADS.h +++ /dev/null @@ -1,405 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004, 2011 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - */ - -/* - * mpc8560ads board configuration file - * - * Please refer to doc/README.mpc85xx for more info. - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc. in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_CPM2 1 /* has CPM2 */ - -/* - * default CCARBAR is at 0xff700000 - * assume U-Boot is less than 0.5MB - */ - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 33000000 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002 -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */ - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ -#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ - -#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ - -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \ - | LSDMR_RFCR5 \ - | LSDMR_PRETOACT3 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BL8 \ - | LSDMR_WRC2 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * SDRAM Controller configuration sequence. - */ -#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) - -/* - * 32KB, 8-bit wide for ADS config reg - */ -#define CONFIG_SYS_BR4_PRELIM 0xf8000801 -#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1 -#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000) - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */ -#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ - -#if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_TSEC_ENET - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -#ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */ - -#undef CONFIG_ETHER_NONE /* define if ether on something else */ -#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ - -#if (CONFIG_ETHER_INDEX == 2) - /* - * - Rx-CLK is CLK13 - * - Tx-CLK is CLK14 - * - Select bus for bd/buffers - * - Full duplex - */ - #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) - #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) - #define CONFIG_SYS_CPMFCR_RAMTYPE 0 - #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) - #define FETH2_RST 0x01 -#elif (CONFIG_ETHER_INDEX == 3) - /* need more definitions here for FE3 */ - #define FETH3_RST 0x80 -#endif /* CONFIG_ETHER_INDEX */ - -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ - -/* - * GPIO pins used for bit-banged MII communications - */ -#define MDIO_PORT 2 /* Port C */ -#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ - (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) -#define MDC_DECLARE MDIO_DECLARE - -#define MDIO_ACTIVE (iop->pdir |= 0x00400000) -#define MDIO_TRISTATE (iop->pdir &= ~0x00400000) -#define MDIO_READ ((iop->pdat & 0x00400000) != 0) - -#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ - else iop->pdat &= ~0x00400000 - -#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ - else iop->pdat &= ~0x00200000 - -#define MIIDELAY udelay(1) - -#endif - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) - #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyCPM\0" \ - "ramdiskaddr=1000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8560ads.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h deleted file mode 100644 index 01ee69c..0000000 --- a/include/configs/MPC8568MDS.h +++ /dev/null @@ -1,411 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2004-2007, 2010-2011 Freescale Semiconductor. - */ - -/* - * mpc8568mds board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCI1 1 /* PCI controller */ -#define CONFIG_PCIE1 1 /* PCIE controller */ -#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_ENV_OVERWRITE - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif /*Replace a call to get_clock_freq (after it is implemented)*/ -#define CONFIG_SYS_CLK_FREQ 66000000 /*TODO: restore if wanting to read from BCSR: get_clock_freq()*/ /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* Make sure required options are set */ -#ifndef CONFIG_SPD_EEPROM -#error ("CONFIG_SPD_EEPROM is required") -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -/* - * FLASH on the Local Bus - * Two banks, 8M each, using the CFI driver. - * Boot from BR0/OR0 bank at 0xff00_0000 - * Alternate BR1/OR1 bank at 0xff80_0000 - * - * BR0, BR1: - * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0 - * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0 - * Port Size = 16 bits = BRx[19:20] = 10 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0 - * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1 - * - * OR0, OR1: - * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0 - * Reserved ORx[17:18] = 11, confusion here? - * CSNT = ORx[20] = 1 - * ACS = half cycle delay = ORx[21:22] = 11 - * SCY = 6 = ORx[24:27] = 0110 - * TRLX = use relaxed timing = ORx[29] = 1 - * EAD = use external address latch delay = OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx - */ -#define CONFIG_SYS_BCSR_BASE 0xf8000000 - -#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ - -/*Chip select 0 - Flash*/ -#define CONFIG_SYS_BR0_PRELIM 0xfe001001 -#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 - -/*Chip slelect 1 - BCSR*/ -#define CONFIG_SYS_BR1_PRELIM 0xf8000801 -#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 - -/*#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE} */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* - * SDRAM on the LocalBus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/*Chip select 2 - SDRAM*/ -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * Common settings for all Local Bus SDRAM commands. - * At run time, either BSMA1516 (for CPU 1.1) - * or BSMA1617 (for CPU 1.0) (old) - * is OR'ed in too. - */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ - | LSDMR_PRETOACT7 \ - | LSDMR_ACTTORW7 \ - | LSDMR_BL8 \ - | LSDMR_WRC4 \ - | LSDMR_CL3 \ - | LSDMR_RFEN \ - ) - -/* - * The bcsr registers are connected to CS3 on MDS. - * The new memory map places bcsr at 0xf8000000. - * - * For BR3, need: - * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0 - * port-size = 8-bits = BR[19:20] = 01 - * no parity checking = BR[21:22] = 00 - * GPMC for MSEL = BR[24:26] = 000 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801 - * - * For OR3, need: - * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0 - * disable buffer ctrl OR[19] = 0 - * CSNT OR[20] = 1 - * ACS OR[21:22] = 11 - * XACS OR[23] = 1 - * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe - * SETA OR[28] = 0 - * TRLX OR[29] = 1 - * EHTR OR[30] = 1 - * EAD extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7 - */ -#define CONFIG_SYS_BCSR (0xf8000000) - -/*Chip slelect 4 - PIB*/ -#define CONFIG_SYS_BR4_PRELIM 0xf8008801 -#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 - -/*Chip select 5 - PIB*/ -#define CONFIG_SYS_BR5_PRELIM 0xf8010801 -#define CONFIG_SYS_OR5_PRELIM 0xffff69f7 - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 - -/* - * General PCI - * Memory Addresses are mapped 1-1. I/O is mapped from 0 - */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ - -#define CONFIG_SYS_PCIE1_NAME "Slot" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ - -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ - -#ifdef CONFIG_QE -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#ifndef CONFIG_TSEC_ENET -#define CONFIG_ETHPRIME "UEC0" -#endif -#define CONFIG_PHY_MODE_NEED_CHANGE -#define CONFIG_eTSEC_MDIO_BUS - -#ifdef CONFIG_eTSEC_MDIO_BUS -#define CONFIG_MIIM_ADDRESS 0xE0024520 -#endif - -#define CONFIG_UEC_ETH1 /* GETH1 */ - -#ifdef CONFIG_UEC_ETH1 -#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 -#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 -#endif - -#define CONFIG_UEC_ETH2 /* GETH2 */ - -#ifdef CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 -#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 -#endif -#endif /* CONFIG_QE */ - -#if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" - -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 3 - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -/* The mac addresses for all ethernet interface */ -#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.253 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/nfsroot" -#define CONFIG_BOOTFILE "your.uImage" - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "run nfsargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "run ramargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h deleted file mode 100644 index de187bf..0000000 --- a/include/configs/MPC8569MDS.h +++ /dev/null @@ -1,503 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * mpc8569mds board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCIE1 1 /* PCIE controller */ -#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_ENV_OVERWRITE - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -/* Replace a call to get_clock_freq (after it is implemented)*/ -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#ifdef CONFIG_ATM -#define CONFIG_PQ_MDS_PIB -#define CONFIG_PQ_MDS_PIB_ATM -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -#if defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 - /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 -#define CONFIG_SYS_DDR_TIMING_2 0x002888D0 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 -#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 -#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 -#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 -#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 -#define CONFIG_SYS_DDR_CDR_1 0x80040000 -#define CONFIG_SYS_DDR_CDR_2 0x00000000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL2 0x24400000 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_BCSR_BASE 0xf8000000 -#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE - -/*Chip select 0 - Flash*/ -#define CONFIG_FLASH_BR_PRELIM 0xfe000801 -#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 - -/*Chip select 1 - BCSR*/ -#define CONFIG_SYS_BR1_PRELIM 0xf8000801 -#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 - -/*Chip select 4 - PIB*/ -#define CONFIG_SYS_BR4_PRELIM 0xf8008801 -#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 - -/*Chip select 5 - PIB*/ -#define CONFIG_SYS_BR5_PRELIM 0xf8010801 -#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#undef CONFIG_SYS_RAMBOOT - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Chip select 3 - NAND */ -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xFC000000 -#else -#define CONFIG_SYS_NAND_BASE 0xFFF00000 -#endif - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START \ - (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) - -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ - | (2< 0xfff80000 - #define CONFIG_ENV_ADDR 0xfff80000 - #else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) - #endif - #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * USB - */ - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_PCI_EHCI_DEVICE 0 -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_HAS_ETH3 -#endif - -#define CONFIG_IPADDR 192.168.1.254 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=8572ds/ramdisk.uboot\0" \ -"fdtaddr=1e00000\0" \ -"fdtfile=8572ds/mpc8572ds.dtb\0" \ -"bdev=sda3\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h deleted file mode 100644 index 04f55e3..0000000 --- a/include/configs/MPC8610HPCD.h +++ /dev/null @@ -1,575 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2007-2011 Freescale Semiconductor, Inc. - */ - -/* - * MPC8610HPCD board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ - -/* video */ -#define CONFIG_FSL_DIU_FB - -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#endif - -#ifdef RUN_DIAG -#define CONFIG_SYS_DIAG_ADDR 0xff800000 -#endif - -/* - * virtual address to be used for temporary mappings. There - * should be 128k free at this VA. - */ -#define CONFIG_SYS_SCRATCH_VA 0xc0000000 - -#define CONFIG_PCI1 1 /* PCI controller 1 */ -#define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ -#define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - -#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_ALTIVEC 1 - -/* - * L2CR setup -- make sure this is right for your board! - */ -#define CONFIG_SYS_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2CR_L2E |0x00100000 ) - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD for DDR */ -#define CONFIG_DDR_SPD - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ - -#if 0 /* TODO */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 -#define CONFIG_SYS_DDR_MODE_1 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x06180100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x04400010 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x000f0000 - -#endif - -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ -#define CONFIG_SYS_FLASH_BASE2 0xf8000000 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} - -#define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ -#define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ - -#define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ -#define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ -#if 0 /* TODO */ -#define CONFIG_SYS_BR2_PRELIM 0xf0000000 -#define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ -#endif -#define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ - -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ -#define PIXIS_BASE 0xe8000000 /* PIXIS registers */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_SPD_EEPROM -#define CONFIG_SYS_SDRAM_SIZE 256 -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#ifndef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* maximum size of the flat tree (8K) */ -#define OF_FLAT_TREE_MAX_SIZE 8192 - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BUS 0x0000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 -#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -/* controller 1, Base address 0xa000 */ -#define CONFIG_SYS_PCIE1_NAME "ULI" -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ - -/* controller 2, Base Address 0x9000 */ -#define CONFIG_SYS_PCIE2_NAME "Slot 1" -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ -#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#define CONFIG_ULI526X - -/************************************************************ - * USB support - ************************************************************/ -#define CONFIG_PCI_OHCI 1 -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 - -#if !defined(CONFIG_PCI_PNP) -#define PCI_ENET0_IOADDR 0xe0000000 -#define PCI_ENET0_MEMADDR 0xe0000000 -#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_SATA_ULI5288 -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) -#endif - -#endif /* CONFIG_PCI */ - -/* - * BAT0 2G Cacheable, non-guarded - * 0x0000_0000 2G DDR - */ -#define CONFIG_SYS_DBAT0L (BATL_PP_RW) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW) - -/* - * BAT1 1G Cache-inhibited, guarded - * 0x8000_0000 256M PCI-1 Memory - * 0xa000_0000 256M PCI-Express 1 Memory - * 0x9000_0000 256M PCI-Express 2 Memory - */ - -#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U - -/* - * BAT2 16M Cache-inhibited, guarded - * 0xe100_0000 1M PCI-1 I/O - */ - -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U - -/* - * BAT3 4M Cache-inhibited, guarded - * 0xe000_0000 4M CCSR - */ - -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) -#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU -#endif - -/* - * BAT4 32M Cache-inhibited, guarded - * 0xe200_0000 1M PCI-Express 2 I/O - * 0xe300_0000 1M PCI-Express 1 I/O - */ - -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U - -/* - * BAT5 128K Cacheable, non-guarded - * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L -#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U - -/* - * BAT6 256M Cache-inhibited, guarded - * 0xf000_0000 256M FLASH - */ -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U - -/* Map the last 1M of flash where we're running from reset */ -#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY - -/* - * BAT7 4M Cache-inhibited, guarded - * 0xe800_0000 4M PIXIS - */ -#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#define CONFIG_WATCHDOG /* watchdog enabled */ -#define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_IPADDR 192.168.1.100 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x10000000 - -#if defined(CONFIG_PCI1) -#define PCI_ENV \ - "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ - "echo e;md ${a}e00 9\0" \ - "pci1regs=setenv a e0008; run pcireg\0" \ - "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ - "pci d.w $b.0 56 1\0" \ - "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ - "pci w.w $b.0 56 ffff\0" \ - "pci1err=setenv a e0008; run pcierr\0" \ - "pci1errc=setenv a e0008; run pcierrc\0" -#else -#define PCI_ENV "" -#endif - -#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) -#define PCIE_ENV \ - "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ - "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ - "pcie1regs=setenv a e000a; run pciereg\0" \ - "pcie2regs=setenv a e0009; run pciereg\0" \ - "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ - "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ - "pci d $b.0 130 1\0" \ - "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ - "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ - "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ - "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ - "pcie1err=setenv a e000a; run pcieerr\0" \ - "pcie2err=setenv a e0009; run pcieerr\0" \ - "pcie1errc=setenv a e000a; run pcieerrc\0" \ - "pcie2errc=setenv a e0009; run pcieerrc\0" -#else -#define PCIE_ENV "" -#endif - -#define DMA_ENV \ - "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ - "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ - "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ - "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ - "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ - "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ - "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ - "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" - -#ifdef ENV_DEBUG -#define CONFIG_EXTRA_ENV_SETTINGS \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=0x18000000\0" \ -"ramdiskfile=8610hpcd/ramdisk.uboot\0" \ -"fdtaddr=0x17c00000\0" \ -"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ -"bdev=sda3\0" \ -"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ -"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ -"maxcpus=1" \ -"eoi=mw e00400b0 0\0" \ -"iack=md e00400a0 1\0" \ -"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ - "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ - "md ${a}f00 5\0" \ -"ddr1regs=setenv a e0002; run ddrreg\0" \ -"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ - "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ - "md ${a}e60 1; md ${a}ef0 1d\0" \ -"guregs=setenv a e00e0; run gureg\0" \ -"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ -"mcmregs=setenv a e0001; run mcmreg\0" \ -"diuregs=md e002c000 1d\0" \ -"dium=mw e002c01c\0" \ -"diuerr=md e002c014 1\0" \ -"pmregs=md e00e1000 2b\0" \ -"lawregs=md e0000c08 4b\0" \ -"lbcregs=md e0005000 36\0" \ -"dma0regs=md e0021100 12\0" \ -"dma1regs=md e0021180 12\0" \ -"dma2regs=md e0021200 12\0" \ -"dma3regs=md e0021280 12\0" \ - PCI_ENV \ - PCIE_ENV \ - DMA_ENV -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=0x18000000\0" \ - "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ - "fdtaddr=0x17c00000\0" \ - "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ - "bdev=sda3\0" -#endif - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#endif /* __CONFIG_H */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h deleted file mode 100644 index 8c01891..0000000 --- a/include/configs/MPC8641HPCN.h +++ /dev/null @@ -1,649 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2006, 2010-2011 Freescale Semiconductor. - * - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - */ - -/* - * MPC8641HPCN board configuration file - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc. in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#define CONFIG_ADDR_MAP 1 /* Use addr map */ - -/* - * default CCSRBAR is at 0xff700000 - * assume U-Boot is less than 0.5MB - */ - -#ifdef RUN_DIAG -#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE -#endif - -/* - * virtual address to be used for temporary mappings. There - * should be 128k free at this VA. - */ -#define CONFIG_SYS_SCRATCH_VA 0xe0000000 - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCIE1 1 /* PCIE controller 1 (ULI bridge) */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ - -#define CONFIG_ALTIVEC 1 - -/* - * L2CR setup -- make sure this is right for your board! - */ -#define CONFIG_SYS_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2CR_L2E) - -#ifndef CONFIG_SYS_CLK_FREQ -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * With the exception of PCI Memory and Rapid IO, most devices will simply - * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA - * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. - */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f -#else -#define CONFIG_SYS_PHYS_ADDR_HIGH 0x00000000 -#endif - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - -/* Physical addresses */ -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH CONFIG_SYS_PHYS_ADDR_HIGH -#define CONFIG_SYS_CCSRBAR_PHYS \ - PAIRED_PHYS_TO_PHYS(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH) - -#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ - -/* - * DDR Setup - */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* - * I2C addresses of SPD EEPROMs - */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ -#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ -#define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ -#define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ - -/* - * These are used when DDR doesn't use SPD. - */ -#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x39357322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 -#define CONFIG_SYS_DDR_MODE_1 0x00480432 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x06090100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ -#define CONFIG_SYS_DDR_CONTROL2 0x04400000 - -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -#define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ -#define CONFIG_SYS_FLASH_BASE_PHYS_LOW CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS \ - PAIRED_PHYS_TO_PHYS(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | 0x00001001) /* port size 16bit */ -#define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ - -#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ - | 0x00001001) /* port size 16bit */ -#define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ - -#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ - | 0x00000801) /* port size 8bit */ -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ - -/* - * The LBC_BASE is the base of the region that contains the PIXIS and the CF. - * The PIXIS and CF by themselves aren't large enough to take up the 128k - * required for the smallest BAT mapping, so there's a 64k hole. - */ -#define CONFIG_SYS_LBC_BASE 0xffde0000 -#define CONFIG_SYS_LBC_BASE_PHYS_LOW CONFIG_SYS_LBC_BASE - -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ -#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) -#define PIXIS_BASE_PHYS_LOW (CONFIG_SYS_LBC_BASE_PHYS_LOW + 0x00010000) -#define PIXIS_BASE_PHYS PAIRED_PHYS_TO_PHYS(PIXIS_BASE_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) -#define PIXIS_SIZE 0x00008000 /* 32k */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ -#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ - -/* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ -#define CF_BASE (PIXIS_BASE + PIXIS_SIZE) -#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#if defined(CONFIG_SYS_RAMBOOT) -#undef CONFIG_SPD_EEPROM -#define CONFIG_SYS_SDRAM_SIZE 256 -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#ifndef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* - * RapidIO MMU - */ -#define CONFIG_SYS_SRIO1_MEM_BASE 0x80000000 /* base address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW 0x00000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x0000000c -#else -#define CONFIG_SYS_SRIO1_MEM_PHYS_LOW CONFIG_SYS_SRIO1_MEM_BASE -#define CONFIG_SYS_SRIO1_MEM_PHYS_HIGH 0x00000000 -#endif -#define CONFIG_SYS_SRIO1_MEM_PHYS \ - PAIRED_PHYS_TO_PHYS(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ - CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ - -#define CONFIG_SYS_PCIE1_NAME "ULI" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW 0x00000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x0000000c -#else -#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT -#define CONFIG_SYS_PCIE1_MEM_PHYS_LOW CONFIG_SYS_PCIE1_MEM_VIRT -#define CONFIG_SYS_PCIE1_MEM_PHYS_HIGH 0x00000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_PHYS \ - PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ - CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_PHYS_LOW CONFIG_SYS_PCIE1_IO_VIRT -#define CONFIG_SYS_PCIE1_IO_PHYS \ - PAIRED_PHYS_TO_PHYS(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ - -#ifdef CONFIG_PHYS_64BIT -/* - * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. - * This will increase the amount of PCI address space available for - * for mapping RAM. - */ -#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS -#else -#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ - + CONFIG_SYS_PCIE1_MEM_SIZE) -#endif -#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ - + CONFIG_SYS_PCIE1_MEM_SIZE) -#define CONFIG_SYS_PCIE2_MEM_PHYS_LOW (CONFIG_SYS_PCIE1_MEM_PHYS_LOW \ - + CONFIG_SYS_PCIE1_MEM_SIZE) -#define CONFIG_SYS_PCIE2_MEM_PHYS_HIGH CONFIG_SYS_PCIE1_MEM_PHYS_HIGH -#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ - + CONFIG_SYS_PCIE1_MEM_SIZE) -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ - + CONFIG_SYS_PCIE1_IO_SIZE) -#define CONFIG_SYS_PCIE2_IO_PHYS_LOW (CONFIG_SYS_PCIE1_IO_PHYS_LOW \ - + CONFIG_SYS_PCIE1_IO_SIZE) -#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ - + CONFIG_SYS_PCIE1_IO_SIZE) -#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -/************************************************************ - * USB support - ************************************************************/ -#define CONFIG_PCI_OHCI 1 -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 - -/*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT - -/*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ - -/* video */ - -#if defined(CONFIG_VIDEO) -#define CONFIG_BIOSEMU -#define CONFIG_ATI_RADEON_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_SATA_ULI5288 -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) -#endif - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "eTSEC4" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 -#define TSEC3_PHY_ADDR 2 -#define TSEC4_PHY_ADDR 3 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -#ifdef CONFIG_PHYS_64BIT -#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) -#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) - -/* Put physical address into the BAT format */ -#define BAT_PHYS_ADDR(low, high) \ - (low | PHYS_HIGH_TO_BXPN(high) | PHYS_HIGH_TO_BX(high)) -/* Convert high/low pairs to actual 64-bit value */ -#define PAIRED_PHYS_TO_PHYS(low, high) (low | ((u64)high << 32)) -#else -/* 32-bit systems just ignore the "high" bits */ -#define BAT_PHYS_ADDR(low, high) (low) -#define PAIRED_PHYS_TO_PHYS(low, high) (low) -#endif - -/* - * BAT0 DDR - */ -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) - -/* - * BAT1 LBC (PIXIS/CF) - */ -#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ - | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) \ - | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U - -/* if CONFIG_PCI: - * BAT2 PCIE1 and PCIE1 MEM - * if CONFIG_RIO - * BAT2 Rapidio Memory - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ - CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ - | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS_LOW, \ - CONFIG_SYS_PCIE1_MEM_PHYS_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#else /* CONFIG_RIO */ -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ - CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT | \ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M \ - | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_SRIO1_MEM_PHYS_LOW, \ - CONFIG_SYS_SRIO1_MEM_PHYS_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U -#endif - -/* - * BAT3 CCSR Space - */ -#define CONFIG_SYS_DBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT3L (BAT_PHYS_ADDR(CONFIG_SYS_CCSRBAR_PHYS_LOW, \ - CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) -#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU -#endif - -/* - * BAT4 PCIE1_IO and PCIE2_IO - */ -#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ - | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U - -/* - * BAT5 Init RAM for stack in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L -#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U - -/* - * BAT6 FLASH - */ -#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) \ - | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_LOW, \ - CONFIG_SYS_PHYS_ADDR_HIGH) \ - | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U - -/* Map the last 1M of flash where we're running from reset */ -#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY - -/* - * BAT7 FREE - used later for tmp mappings - */ -#define CONFIG_SYS_DBAT7L 0x00000000 -#define CONFIG_SYS_DBAT7U 0x00000000 -#define CONFIG_SYS_IBAT7L 0x00000000 -#define CONFIG_SYS_IBAT7U 0x00000000 - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#endif -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) - #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_HAS_ETH0 1 -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 -#define CONFIG_HAS_ETH3 1 - -#define CONFIG_IPADDR 192.168.1.100 - -#define CONFIG_HOSTNAME "unknown" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 0x10000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ - " $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=0x18000000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=0x17c00000\0" \ - "fdtfile=mpc8641_hpcn.dtb\0" \ - "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ - "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ - "maxcpus=2" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h deleted file mode 100644 index 64172f3..0000000 --- a/include/configs/MigoR.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas Solutions Migo-R board - * - * Copyright (C) 2007 Nobuhiro Iwamatsu - */ - -#ifndef __MIGO_R_H -#define __MIGO_R_H - -#define CONFIG_CPU_SH7722 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* SMC9111 */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (0xB0000000) - -/* MEMORY */ -#define MIGO_R_SDRAM_BASE (0x8C000000) -#define MIGO_R_FLASH_BASE_1 (0xA0000000) -#define MIGO_R_FLASH_BANK_SIZE (64 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */ - -/* SCIF */ -#define CONFIG_CONS_SCIF0 1 - -#define CONFIG_SYS_MEMTEST_START (MIGO_R_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) - -/* Enable alternate, more extensive, memory test */ -/* Scratch address used by the alternate memory test */ -#undef CONFIG_SYS_MEMTEST_SCRATCH - -/* Enable temporary baudrate change while serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (MIGO_R_SDRAM_BASE) -/* maybe more, but if so u-boot doesn't know about it... */ -#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) -/* default load address for scripts ?!? */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) - -/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ -#define CONFIG_SYS_MONITOR_BASE (MIGO_R_FLASH_BASE_1) -/* Monitor size */ -#define CONFIG_SYS_MONITOR_LEN (128 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* FLASH */ -#undef CONFIG_SYS_FLASH_QUIET_TEST -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -/* Physical start address of Flash memory */ -#define CONFIG_SYS_FLASH_BASE (MIGO_R_FLASH_BASE_1) -/* Max number of sectors on each Flash chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* if you use all NOR Flash , you change dip-switch. Please see MIGO_R01 Manual. */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MIGO_R_FLASH_BANK_SIZE) } - -/* Timeout for Flash erase operations (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -/* Timeout for Flash write operations (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -/* Timeout for Flash set sector lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -/* Timeout for Flash clear lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) - -/* Use hardware flash sectors protection instead of U-Boot software protection */ -#undef CONFIG_SYS_DIRECT_FLASH_TFTP - -/* ENV setting */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 33333333 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#endif /* __MIGO_R_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h deleted file mode 100644 index 1152bca..0000000 --- a/include/configs/P1010RDB.h +++ /dev/null @@ -1,767 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -/* - * P010 RDB board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#define CONFIG_NAND_FSL_IFC - -#ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#else -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x18000 -#define CONFIG_SPL_MAX_SIZE (96 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif -#endif - -#ifdef CONFIG_NAND -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 -#define CONFIG_SPL_RELOC_STACK 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 -#else -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xD0001000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_NAND_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 8192 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif -#endif - -#ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ -#define CONFIG_RAMBOOT_NAND -#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ - -#if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -/* - * PCI Windows - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* controller 1, Slot 1, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_SYS_PCIE2_NAME "PCIe Slot" -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" -#endif -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ -#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff - -/* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS 0x52 - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#ifndef __ASSEMBLY__ -extern unsigned long get_sdram_size(void); -#endif -#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -/* DDR3 Controller Settings */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 - -/* settings for DDR3 at 667MT/s */ -#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 -#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 -#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_667 0x00441210 -#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* Don't relocate CCSRBAR while in NAND_SPL */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * - * Localbus non-cacheable - * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable - * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * IFC Definitions - */ -/* NOR Flash on IFC */ - -#define CONFIG_SYS_FLASH_BASE 0xee000000 -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5) -#define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ - FTIM1_NOR_TRAD_NOR(0x0f) -#define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWP(0x1c) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -/* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* NAND Flash on IFC */ -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_MTD_PARTITION - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ - | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ - | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ - | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) - -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ - | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) -#endif - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#if defined(CONFIG_TARGET_P1010RDB_PA) -/* NAND Flash Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ - FTIM0_NAND_TWP(0x0C) | \ - FTIM0_NAND_TWCHT(0x04) | \ - FTIM0_NAND_TWH(0x05) -#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ - FTIM1_NAND_TWBE(0x1d) | \ - FTIM1_NAND_TRR(0x07) | \ - FTIM1_NAND_TRP(0x0c) -#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ - FTIM2_NAND_TREH(0x05) | \ - FTIM2_NAND_TWHRE(0x0f) -#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) - -#elif defined(CONFIG_TARGET_P1010RDB_PB) -/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 -#endif - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -/* Set up IFC registers for boot location NOR/NAND */ -#if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffb00000 - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull -#else -#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE -#endif - -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 0x0 -/* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ - defined(CONFIG_RAMBOOT_NAND) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 -#if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_A003399_NOR_WORKAROUND -#endif -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ - -/* - * Config the L2 Cache as L2 SRAM - */ -#if defined(CONFIG_SPL_BUILD) -#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) -#elif defined(CONFIG_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 -#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) -#else -#define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) -#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) -#endif -#endif -#endif - -/* Serial Port */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define I2C_PCA9557_ADDR1 0x18 -#define I2C_PCA9557_ADDR2 0x19 -#define I2C_PCA9557_BUS_NUM 0 - -/* I2C EEPROM */ -#if defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ID_EEPROM -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ -#endif -/* enable read and write access to EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* RTC */ -#define CONFIG_RTC_PT7C4338 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * SPI interface will not be available in case of NAND boot SPI CS0 will be - * used for SLIC - */ -#if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) -/* eSPI - Enhanced SPI */ -#endif - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 2 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -/* TBI PHY configuration for SGMII mode */ -#define CONFIG_TSEC_TBICR_SETTINGS ( \ - TBICR_PHY_RESET \ - | TBICR_ANEG_ENABLE \ - | TBICR_FULL_DUPLEX \ - | TBICR_SPEED1_SET \ - ) - -#endif /* CONFIG_TSEC_ENET */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif /* #ifdef CONFIG_FSL_SATA */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -/* - * Environment - */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_NAND) -#ifdef CONFIG_TPL_BUILD -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) -#else -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ -#endif -#endif -#define CONFIG_ENV_OFFSET (1024 * 1024) -#elif defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ - || defined(CONFIG_FSL_SATA) -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=p1010rdb.dtb\0" \ - "bdev=sda1\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ - "othbootargs=ramdisk_size=600000\0" \ - "usbfatboot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "fatload usb 0:2 $loadaddr $bootfile;" \ - "fatload usb 0:2 $fdtaddr $fdtfile;" \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - "usbext2boot=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ - CONFIG_BOOTMODE - -#if defined(CONFIG_TARGET_P1010RDB_PA) -#define CONFIG_BOOTMODE \ - "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ - "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ - "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ - "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ - "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ - "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" - -#elif defined(CONFIG_TARGET_P1010RDB_PB) -#define CONFIG_BOOTMODE \ - "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ - "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ - "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ - "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ - "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ - "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ - "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ - "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ - "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ - "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" -#endif - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs; " \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h deleted file mode 100644 index 4b2eb65..0000000 --- a/include/configs/P1022DS.h +++ /dev/null @@ -1,607 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2012 Freescale Semiconductor, Inc. - * Authors: Srikanth Srinivasan - * Timur Tabi - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#define CONFIG_SYS_NAND_MAX_OOBFREE 5 - -#ifdef CONFIG_NAND -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif - -/* High Level Configuration Options */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x7fffffff - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_DDR_SPD -#define CONFIG_VERY_BIG_RAM - -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 2048 -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0 0x40110104 -#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746 -#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca -#define CONFIG_SYS_DDR_MODE_1 0x00441221 -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL 0x0a280100 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000 -#define CONFIG_SYS_DDR_CONTROL 0xc7000008 -#define CONFIG_SYS_DDR_CONTROL_2 0x24401041 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x02401400 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608 - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable - * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable - * - * Localbus cacheable (TBD) - * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable - * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable - * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable - * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7) - -#ifdef CONFIG_NAND -#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#else -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#endif - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -#ifndef CONFIG_SYS_MONITOR_BASE -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif -#endif - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Nand Flash */ -#if defined(CONFIG_NAND_FSL_ELBC) -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) -#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< - * Chunhe Lan - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* High Level Configuration Options */ - -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif - -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_HWCONFIG - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x02000000 - -/* Implement conversion of addresses in the LBC */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 - -/* DDR Setup */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x50 -#define CONFIG_SYS_DDR_RAW_TIMING - -/* - * Memory map - * - * 0x0000_0000 0x1fff_ffff DDR 512M cacheable - * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable - * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable - * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable - * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable - * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0 - * - * Localbus non-cacheable - * - * 0xec00_0000 0xefff_ffff NOR flash 64M non-cacheable - * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 /* start of FLASH 64M */ -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) -#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ - -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2<> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_BMAN_MEM_BASE 0xff200000 -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 - -/* For FM */ -#define CONFIG_SYS_DPAA_FMAN - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_ATHEROS -#endif - -/* Default address of microcode for the Linux Fman driver */ -/* QE microcode/firmware address */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 - -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "loadaddr=1000000\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off $ubootaddr +$filesize; " \ - "erase $ubootaddr +$filesize; " \ - "cp.b $loadaddr $ubootaddr $filesize; " \ - "protect on $ubootaddr +$filesize; " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=p1023rdb.dtb\0" \ - "othbootargs=ramdisk_size=600000\0" \ - "bdev=sda1\0" \ - "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h deleted file mode 100644 index f8cfef7..0000000 --- a/include/configs/P2041RDB.h +++ /dev/null @@ -1,603 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -/* - * P2041 RDB board configuration file - * Also supports P2040 RDB - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg -#endif - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_SYS_DPAA_RMAN /* RMan */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SPIFLASH) - #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ - #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ - #define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) - #define CONFIG_FSL_FIXED_MMC_LOCATION - #define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_OFFSET (512 * 1658) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ - - CONFIG_ENV_SECT_SIZE) - #define CONFIG_ENV_SIZE 0x2000 - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ - CONFIG_RAMBOOT_TEXT_BASE) -#else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR -#endif -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x52 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * Local Bus Definitions - */ - -/* Set the local bus clock 1/8 of platform clock */ -#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 - -/* - * This board doesn't have a promjet connector. - * However, it uses commone corenet board LAW and TLB. - * It is necessary to use the same start address with proper offset. - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ - BR_PS_16 | BR_V) -#define CONFIG_SYS_FLASH_OR_PRELIM \ - ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ - | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) - -#define CONFIG_FSL_CPLD -#define CPLD_BASE 0xffdf0000 /* CPLD registers */ -#ifdef CONFIG_PHYS_64BIT -#define CPLD_BASE_PHYS 0xfffdf0000ull -#else -#define CPLD_BASE_PHYS CPLD_BASE -#endif - -#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ - -#define PIXIS_LBMAP_SWITCH 7 -#define PIXIS_LBMAP_MASK 0xf0 -#define PIXIS_LBMAP_SHIFT 4 -#define PIXIS_LBMAP_ALTBANK 0x40 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_NAND_FSL_ELBC -/* Nand Flash */ -#ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2<> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_TERANETICS -#endif - -#ifdef CONFIG_PCI -#if !defined(CONFIG_DM_PCI) -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 -#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 - -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f - -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 - -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Command line configuration. - */ - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1\0" \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "usb_dr_mode=host\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=p2041rdb/p2041rdb.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h deleted file mode 100644 index 2f6cc5d..0000000 --- a/include/configs/P3041DS.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -/* - * P3041 DS board configuration file - * - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 -#define CONFIG_SYS_DPAA_RMAN - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h deleted file mode 100644 index ed88b41..0000000 --- a/include/configs/P4080DS.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P4080 DS board configuration file - * Also supports P4040 DS - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_PCIE3 - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h deleted file mode 100644 index 873d39a..0000000 --- a/include/configs/P5020DS.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P5020 DS board configuration file - * Also supports P5010 DS - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 -#define CONFIG_SYS_FSL_RAID_ENGINE -#define CONFIG_SYS_DPAA_RMAN - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h deleted file mode 100644 index 12666d6..0000000 --- a/include/configs/P5040DS.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * P5040 DS board configuration file - * - */ -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ - -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_PCIE3 -#define CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_FSL_RAID_ENGINE - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#include "corenet_ds.h" diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h deleted file mode 100644 index f24cd23..0000000 --- a/include/configs/SBx81LIFKW.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Allied Telesis - */ - -#ifndef _CONFIG_SBX81LIFKW_H -#define _CONFIG_SBX81LIFKW_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_GPIO 1 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" -#define MTDPARTS_MTDOOPS "errlog" -#define CONFIG_DOS_PARTITION - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ -#define CONFIG_ENV_SIZE 0x02000 -#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */ - -/* - * U-Boot bootcode configuration - */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/* size in bytes reserved for initial data */ - -#include -/* There is no PHY directly connected so don't ask it for link status */ -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ -#define CONFIG_PHY_BASE_ADR 0x01 -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#endif /* CONFIG_CMD_NET */ - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ - -#endif /* _CONFIG_SBX81LIFKW_H */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h deleted file mode 100644 index b602323..0000000 --- a/include/configs/SBx81LIFXCAT.h +++ /dev/null @@ -1,104 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Allied Telesis - */ - -#ifndef _CONFIG_SBX81LIFXCAT_H -#define _CONFIG_SBX81LIFXCAT_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */ -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_GPIO 1 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define MTDPARTS_DEFAULT "mtdparts=spi0.0:768K(boot)ro,256K(boot-env),14M(user),1M(errlog)" -#define MTDPARTS_MTDOOPS "errlog" -#define CONFIG_DOS_PARTITION - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ -#define CONFIG_ENV_SIZE 0x02000 -#define CONFIG_ENV_OFFSET 0xc0000 /* env starts here - 768K */ - -/* - * U-Boot bootcode configuration - */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/* size in bytes reserved for initial data */ - -#include -/* There is no PHY directly connected so don't ask it for link status */ -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_NET_MULTI /* specify more that one ports available */ -#define CONFIG_MVGBE /* Enable kirkwood Gbe Controller Driver */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable a single port */ -#define CONFIG_PHY_BASE_ADR 0x01 -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#endif /* CONFIG_CMD_NET */ - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ - -#endif /* _CONFIG_SBX81LIFXCAT_H */ diff --git a/include/configs/T102xQDS.h b/include/configs/T102xQDS.h deleted file mode 100644 index fe9a909..0000000 --- a/include/configs/T102xQDS.h +++ /dev/null @@ -1,772 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -/* - * T1024/T1023 QDS board configuration file - */ - -#ifndef __T1024QDS_H -#define __T1024QDS_H - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_DEEP_SLEEP - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_nand_rcw.cfg -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_spi_rcw.cfg -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_sd_rcw.cfg -#endif - -#endif /* CONFIG_RAMBOOT_PBL */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* PCIe Boot - Master */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -#else -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 -#endif -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#else -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 -#endif -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* PCIe Boot - Slave */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -/* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 0x800) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (256 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#ifdef CONFIG_PHYS_64BIT -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#else -#define QIXIS_BASE_PHYS QIXIS_BASE -#endif -#define QIXIS_LBMAP_SWITCH 0x06 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* Video */ -#ifdef CONFIG_ARCH_T1024 /* no DIU on T1023 */ -#define CONFIG_FSL_DIU_FB -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 - -#define I2C_MUX_PCA_ADDR 0x77 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_DIU 0xC -#define I2C_MUX_CH5 0xD -#define I2C_MUX_CH7 0xF - -/* LDI/DVI Encoder for display */ -#define CONFIG_SYS_I2C_LDI_ADDR 0x38 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCIe - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* - *SATA - */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - -/* - * SDHC - */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN - -/* Default address of microcode for the Linux FMan driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#define CONFIG_SYS_QE_FW_ADDR 0x130000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHY_TERANETICS -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 -#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3 -#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4 -#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ -#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ - "ramdiskfile=t1024qds/ramdisk.uboot\0" \ - "fdtfile=t1024qds/t1024qds.dtb\0" \ - "netdev=eth0\0" \ - "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "fdtaddr=d00000\0" \ - "bdev=sda3\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __T1024QDS_H */ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h deleted file mode 100644 index 8c1434f..0000000 --- a/include/configs/T102xRDB.h +++ /dev/null @@ -1,744 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -/* - * T1024/T1023 RDB board configuration file - */ - -#ifndef __T1024RDB_H -#define __T1024RDB_H - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS - -#define CONFIG_ENV_OVERWRITE - -/* support deep sleep */ -#ifdef CONFIG_ARCH_T1024 -#define CONFIG_DEEP_SLEEP -#endif - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_nand_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_nand_rcw.cfg -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_spi_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_spi_rcw.cfg -#endif -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_sd_rcw.cfg -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_sd_rcw.cfg -#endif -#endif - -#endif /* CONFIG_RAMBOOT_PBL */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* PCIe Boot - Master */ -#define CONFIG_SRIO_PCIE_BOOT_MASTER -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -#else -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000 -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000 -#endif -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#else -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000 -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000 -#endif -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* PCIe Boot - Slave */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -/* Set 1M boot space for PCIe boot */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#endif -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 0x800) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE 0x2000 -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) -#endif -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (256 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_SYS_SDRAM_SIZE 2048 -#endif - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -/* NOR Flash Timing Params */ -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(0) | \ - CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN) -#endif -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} - -#ifdef CONFIG_TARGET_T1024RDB -/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 - -/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 -#endif - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#endif - -#define CONFIG_SYS_NAND_ONFI_DETECTION -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* Video */ -#undef CONFIG_FSL_DIU_FB /* RDB doesn't support DIU */ -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 - -#define I2C_PCA6408_BUS_NUM 1 -#define I2C_PCA6408_ADDR 0x20 - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCIe - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#endif - -#if !defined(CONFIG_DM_PCI) -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - -/* - * SDHC - */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN - -/* Default address of microcode for the Linux FMan driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#define CONFIG_SYS_QE_FW_ADDR 0x130000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) -#elif defined(CONFIG_NAND) -#if defined(CONFIG_TARGET_T1024RDB) -#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_TARGET_T1023RDB) -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE) -#endif -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_REALTEK -#if defined(CONFIG_TARGET_T1024RDB) -#define RGMII_PHY1_ADDR 0x2 -#define RGMII_PHY2_ADDR 0x6 -#define SGMII_AQR_PHY_ADDR 0x2 -#define FM1_10GEC1_PHY_ADDR 0x1 -#elif defined(CONFIG_TARGET_T1023RDB) -#define RGMII_PHY1_ADDR 0x1 -#define SGMII_RTK_PHY_ADDR 0x3 -#define SGMII_AQR_PHY_ADDR 0x2 -#endif -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ -#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */ -#define __USB_PHY_TYPE utmi - -#ifdef CONFIG_ARCH_T1024 -#define CONFIG_BOARDNAME t1024rdb -#define BANK_INTLV cs0_cs1 -#else -#define CONFIG_BOARDNAME t1023rdb -#define BANK_INTLV null -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=" __stringify(BANK_INTLV) "\0" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \ - "fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \ - __stringify(CONFIG_BOARDNAME) ".dtb\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \ - "netdev=eth0\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "fdtaddr=1e00000\0" \ - "bdev=sda3\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __T1024RDB_H */ diff --git a/include/configs/T1040QDS.h b/include/configs/T1040QDS.h deleted file mode 100644 index d8b65e6..0000000 --- a/include/configs/T1040QDS.h +++ /dev/null @@ -1,681 +0,0 @@ -/* - * Copyright 2013-2014 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * T1040 QDS board configuration file - */ - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -/* support deep sleep */ -#define CONFIG_DEEP_SLEEP - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ - -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_MTD_NOR_FLASH -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif -#else /* CONFIG_MTD_NOR_FLASH */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -/* - * TDM Definition - */ -#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) -#define QIXIS_LBMAP_SWITCH 0x06 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* Video */ -#define CONFIG_FSL_DIU_FB -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -/* - * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so - * disable empty flash sector detection, which is I/O-intensive. - */ -#undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SPEED 50000 -#define CONFIG_SYS_FSL_I2C3_SPEED 50000 -#define CONFIG_SYS_FSL_I2C4_SPEED 50000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 - -#define I2C_MUX_PCA_ADDR 0x77 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_DIU 0xC - -/* LDI/DVI Encoder for display */ -#define CONFIG_SYS_I2C_LDI_ADDR 0x38 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#endif - -/* controller 4, Base address 203000 */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_FSL_ESDHC_ADAPTER_IDENT -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHY_TERANETICS -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x10 -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x11 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01 -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02 - -#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f - -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* Enable VSC9953 L2 Switch driver */ -#define CONFIG_VSC9953 -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18 - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t1040qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t1040qds/t1040qds.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h deleted file mode 100644 index 53ee148..0000000 --- a/include/configs/T104xRDB.h +++ /dev/null @@ -1,824 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * T104x RDB board configuration file - */ -#include - -#ifdef CONFIG_RAMBOOT_PBL - -#ifndef CONFIG_SECURE_BOOT -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg -#else -#define CONFIG_SYS_FSL_PBL_PBI \ - $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg -#endif - -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 - -#ifdef CONFIG_NAND -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. - */ -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \ - CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#endif -#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg -#endif -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB_PI -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1040D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg -#endif -#ifdef CONFIG_TARGET_T1042D4RDB -#define CONFIG_SYS_FSL_PBL_RCW \ -$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg -#endif -#endif - -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -/* support deep sleep */ -#define CONFIG_DEEP_SLEEP - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ - -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 0x800) -#elif defined(CONFIG_NAND) -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_RAMBOOT_NAND -#define CONFIG_BOOTSCRIPT_COPY_RAM -#endif -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 66666666 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -/* - * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence - * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address - * (CONFIG_SYS_INIT_L3_VADDR) will be different. - */ -#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE 256 << 10 -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024) -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x51 - -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#define CONFIG_SYS_NOR_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -/* - * TDM Definition - */ -#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000 - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} - -/* CPLD on IFC */ -#define CPLD_LBMAP_MASK 0x3F -#define CPLD_BANK_SEL_MASK 0x07 -#define CPLD_BANK_OVERRIDE 0x40 -#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */ -#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */ -#define CPLD_LBMAP_RESET 0xFF -#define CPLD_LBMAP_SHIFT 0x03 - -#if defined(CONFIG_TARGET_T1042RDB_PI) -#define CPLD_DIU_SEL_DFP 0x80 -#elif defined(CONFIG_TARGET_T1042D4RDB) -#define CPLD_DIU_SEL_DFP 0xc0 -#endif - -#if defined(CONFIG_TARGET_T1040D4RDB) -#define CPLD_INT_MASK_ALL 0xFF -#define CPLD_INT_MASK_THERM 0x80 -#define CPLD_INT_MASK_DVI_DFP 0x40 -#define CPLD_INT_MASK_QSGMII1 0x20 -#define CPLD_INT_MASK_QSGMII2 0x10 -#define CPLD_INT_MASK_SGMI1 0x08 -#define CPLD_INT_MASK_SGMI2 0x04 -#define CPLD_INT_MASK_TDMR1 0x02 -#define CPLD_INT_MASK_TDMR2 0x01 -#endif - -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 -/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SYS_FSL_ERRATUM_A008044 -#if defined(CONFIG_NAND) -#define CONFIG_A008044_WORKAROUND -#endif -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -#if defined(CONFIG_TARGET_T1042RDB_PI) || defined(CONFIG_TARGET_T1042D4RDB) -/* Video */ -#define CONFIG_FSL_DIU_FB - -#ifdef CONFIG_FSL_DIU_FB -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000) -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#endif -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */ -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */ -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C3_SPEED 400000 -#define CONFIG_SYS_FSL_I2C4_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 - -/* I2C bus multiplexer */ -#define I2C_MUX_PCA_ADDR 0x70 -#define I2C_MUX_CH_DEFAULT 0x8 - -#if defined(CONFIG_TARGET_T1042RDB_PI) || \ - defined(CONFIG_TARGET_T1040D4RDB) || \ - defined(CONFIG_TARGET_T1042D4RDB) -/* LDI/DVI Encoder for display */ -#define CONFIG_SYS_I2C_LDI_ADDR 0x38 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS1337 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/*DVI encoder*/ -#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75 -#endif - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -#ifdef CONFIG_PCI -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#endif - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#ifdef CONFIG_PCIE2 -#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#endif - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#ifdef CONFIG_PCIE3 -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#endif - -/* controller 4, Base address 203000 */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#endif - -#if !defined(CONFIG_DM_PCI) -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_HAS_FSL_DR_USB -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME - -#define CONFIG_U_QE - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_SYS_QE_FW_ADDR 0x130000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000 -#endif - -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#endif - -#ifdef CONFIG_FMAN_ENET -#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1042RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03 -#elif defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01 -#elif defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02 -#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03 -#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01 -#endif - -#if defined(CONFIG_TARGET_T1040D4RDB) || defined(CONFIG_TARGET_T1042D4RDB) -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05 -#else -#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01 -#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02 -#endif - -/* Enable VSC9953 L2 Switch driver on T1040 SoC */ -#if defined(CONFIG_TARGET_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB) -#define CONFIG_VSC9953 -#ifdef CONFIG_TARGET_T1040RDB -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08 -#else -#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08 -#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c -#endif -#endif - -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE utmi -#define RAMDISKFILE "t104xrdb/ramdisk.uboot" - -#ifdef CONFIG_TARGET_T1040RDB -#define FDTFILE "t1040rdb/t1040rdb.dtb" -#elif defined(CONFIG_TARGET_T1042RDB_PI) -#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb" -#elif defined(CONFIG_TARGET_T1042RDB) -#define FDTFILE "t1042rdb/t1042rdb.dtb" -#elif defined(CONFIG_TARGET_T1040D4RDB) -#define FDTFILE "t1042rdb/t1040d4rdb.dtb" -#elif defined(CONFIG_TARGET_T1042D4RDB) -#define FDTFILE "t1042rdb/t1042d4rdb.dtb" -#endif - -#ifdef CONFIG_FSL_DIU_FB -#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi" -#else -#define DIU_ENVIRONMENT -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ - "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=" __stringify(FDTFILE) "\0" \ - "bdev=sda3\0" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h deleted file mode 100644 index 54ec1ab..0000000 --- a/include/configs/T208xQDS.h +++ /dev/null @@ -1,787 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2013 Freescale Semiconductor, Inc. - */ - -/* - * T2080/T2081 QDS board configuration file - */ - -#ifndef __T208xQDS_H -#define __T208xQDS_H - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SRIO /* Enable Serial RapidIO Support */ -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ -#elif defined(CONFIG_ARCH_T2081) -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xqds/t208x_pbi.cfg - -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_nand_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_nand_rcw.cfg -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_spi_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_spi_rcw.cfg -#endif -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#if defined(CONFIG_ARCH_T2080) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2080_sd_rcw.cfg -#elif defined(CONFIG_ARCH_T2081) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xqds/t2081_sd_rcw.cfg -#endif -#endif - -#endif /* CONFIG_RAMBOOT_PBL */ - -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 0x800) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CTRL_INTLV_PREFERED cacheline - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_LBMAP_NAND 0x09 -#define QIXIS_LBMAP_SD 0x00 -#define QIXIS_RCW_SRC_NAND 0x104 -#define QIXIS_RCW_SRC_SD 0x040 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RST_FORCE_MEM 0x1 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */\ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C3_SPEED 100000 -#define CONFIG_SYS_FSL_I2C4_SPEED 100000 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ -#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ -#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ -#define I2C_MUX_CH_DEFAULT 0x8 - -#define I2C_MUX_CH_VOL_MONITOR 0xa - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -#define CONFIG_VID_FLS_ENV "t208xqds_vdd_mv" -#ifndef CONFIG_SPL_BUILD -#define CONFIG_VID -#endif -#define CONFIG_VOL_MONITOR_IR36021_SET -#define CONFIG_VOL_MONITOR_IR36021_READ -/* The lowest and highest voltage allowed for T208xQDS */ -#define VDD_MV_MIN 819 -#define VDD_MV_MAX 1212 - -/* - * RapidIO - */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull - -/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull - -#ifdef CONFIG_PCI -#if !defined(CONFIG_DM_PCI) -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ -#define CONFIG_SYS_INTERLAKEN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHY_TERANETICS -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 -#define FM1_10GEC1_PHY_ADDR 0x3 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC3" -#endif - -/* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* - * USB - */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * SDHC - */ -#ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#define CONFIG_FSL_ESDHC_ADAPTER_IDENT -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t2080qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t2080qds/t2080qds.dtb\0" \ - "bdev=sda3\0" - -/* - * For emulation this causes u-boot to jump to the start of the - * proof point app code automatically - */ -#define CONFIG_PROOF_POINTS \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x29000000 - - -;" \ - "cpu 2 release 0x29000000 - - -;" \ - "cpu 3 release 0x29000000 - - -;" \ - "cpu 4 release 0x29000000 - - -;" \ - "cpu 5 release 0x29000000 - - -;" \ - "cpu 6 release 0x29000000 - - -;" \ - "cpu 7 release 0x29000000 - - -;" \ - "go 0x29000000" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __T208xQDS_H */ diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h deleted file mode 100644 index 3d95c4a..0000000 --- a/include/configs/T208xRDB.h +++ /dev/null @@ -1,736 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -/* - * T2080 RDB/PCIe board configuration file - */ - -#ifndef __T2080RDB_H -#define __T2080RDB_H - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ -#define CONFIG_FSL_SATA_V2 - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg - -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg -#endif - -#endif /* CONFIG_RAMBOOT_PBL */ - -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 0x800) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ 66660000 -#define CONFIG_DDR_CLK_FREQ 133330000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */ -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CTRL_INTLV_PREFERED cacheline - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe8000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS } - -/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR2_EXT (0xf) -#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR2 0x0 - -/* CPLD Timing parameters for IFC CS2 */ -#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS2_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */\ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C3_SPEED 100000 -#define CONFIG_SYS_FSL_I2C4_SPEED 100000 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ -#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */ -#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */ -#define I2C_MUX_CH_DEFAULT 0x8 - -#define I2C_MUX_CH_VOL_MONITOR 0xa - -#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv" -#ifndef CONFIG_SPL_BUILD -#define CONFIG_VID -#endif -#define CONFIG_VOL_MONITOR_IR36021_SET -#define CONFIG_VOL_MONITOR_IR36021_READ -/* The lowest and highest voltage allowed for T208xRDB */ -#define VDD_MV_MIN 819 -#define VDD_MV_MAX 1212 - -/* - * RapidIO - */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull - -/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull - -#ifdef CONFIG_PCI -#if !defined(CONFIG_DM_PCI) -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 18 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 18 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN /* RMan */ -#define CONFIG_SYS_INTERLAKEN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#define CONFIG_CORTINA_FW_ADDR 0x120000 - -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_CORTINA_FW_IN_MMC -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0) - -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_CORTINA_FW_IN_NAND -#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE) -#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_CORTINA_FW_IN_REMOTE -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#define CONFIG_CORTINA_FW_ADDR 0xFFE10000 -#else -#define CONFIG_SYS_CORTINA_FW_IN_NOR -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#define CONFIG_CORTINA_FW_ADDR 0xEFE00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_CORTINA -#define CONFIG_PHY_REALTEK -#define CONFIG_CORTINA_FW_LENGTH 0x40000 -#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */ -#define RGMII_PHY2_ADDR 0x02 -#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */ -#define CORTINA_PHY_ADDR2 0x0d -#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */ -#define FM1_10GEC4_PHY_ADDR 0x01 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC3" -#endif - -/* - * SATA - */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_LBA48 -#endif - -/* - * USB - */ -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB -#endif - -/* - * SDHC - */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -/* - * Dynamic MTD Partition support with mtdparts - */ - -/* - * Environment - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t2080rdb/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t2080rdb/t2080rdb.dtb\0" \ - "bdev=sda3\0" - -/* - * For emulation this causes u-boot to jump to the start of the - * proof point app code automatically - */ -#define CONFIG_PROOF_POINTS \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x29000000 - - -;" \ - "cpu 2 release 0x29000000 - - -;" \ - "cpu 3 release 0x29000000 - - -;" \ - "cpu 4 release 0x29000000 - - -;" \ - "cpu 5 release 0x29000000 - - -;" \ - "cpu 6 release 0x29000000 - - -;" \ - "cpu 7 release 0x29000000 - - -;" \ - "go 0x29000000" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __T2080RDB_H */ diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h deleted file mode 100644 index f176253..0000000 --- a/include/configs/T4240QDS.h +++ /dev/null @@ -1,560 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -/* - * T4240 QDS board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE4 - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t4qds/t4_pbi.cfg -#if !defined(CONFIG_NAND) && !defined(CONFIG_SDCARD) -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 - -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_nand_rcw.cfg -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t4qds/t4_sd_rcw.cfg -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#endif -#endif /* CONFIG_RAMBOOT_PBL */ - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -#define CONFIG_SRIO_PCIE_BOOT_MASTER -#define CONFIG_DDR_ECC - -#include "t4qds.h" - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 0x800) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 -#define SPD_EEPROM_ADDRESS5 0x55 -#define SPD_EEPROM_ADDRESS6 0x56 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_BASE 0xffdf0000 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_RST_CTL_RESET 0x83 -#define QIXIS_RST_FORCE_MEM 0x1 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_BRDCFG5 0x55 -#define QIXIS_MUX_SDHC 2 -#define QIXIS_MUX_SDHC_WIDTH8 1 -#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) - -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -/* I2C */ -#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ - -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_MUX_CH_VSC3316_FS 0xc -#define I2C_MUX_CH_VSC3316_BS 0xd - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -/* VSC Crossbar switches */ -#define CONFIG_VSC_CROSSBAR -#define VSC3316_FSM_TX_ADDR 0x70 -#define VSC3316_FSM_RX_ADDR 0x71 - -/* - * RapidIO - */ - -/* - * for slave u-boot IMAGE instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ -#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull -/* - * for slave UCODE and ENV instored in master memory space, - * PHYS must be aligned based on the SIZE - */ -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull -#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ - -/* slave core release by master*/ -#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 -#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ - -/* - * SRIO_PCIE_BOOT - SLAVE - */ -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 -#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) -#endif -/* - * eSPI - Enhanced SPI - */ - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN -#define CONFIG_SYS_INTERLAKEN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_TERANETICS -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -#define FM1_10GEC1_PHY_ADDR 0x0 -#define FM1_10GEC2_PHY_ADDR 0x1 -#define FM2_10GEC1_PHY_ADDR 0x2 -#define FM2_10GEC2_PHY_ADDR 0x3 -#endif - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* -* USB -*/ -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#define CONFIG_ESDHC_DETECT_QUIRK \ - (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ - IS_SVR_REV(get_svr(), 1, 0)) -#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \ - (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8)) -#endif - - -#define __USB_PHY_TYPE utmi - -/* - * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be - * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way - * interleaving. It can be cacheline, page, bank, superbank. - * See doc/README.fsl-ddr for details. - */ -#ifdef CONFIG_ARCH_T4240 -#define CTRL_INTLV_PREFERED 3way_4KB -#else -#define CTRL_INTLV_PREFERED cacheline -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t4240qds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t4240qds/t4240qds.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_ALU \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "cpu 1 release 0x01000000 - - -;" \ - "cpu 2 release 0x01000000 - - -;" \ - "cpu 3 release 0x01000000 - - -;" \ - "cpu 4 release 0x01000000 - - -;" \ - "cpu 5 release 0x01000000 - - -;" \ - "cpu 6 release 0x01000000 - - -;" \ - "cpu 7 release 0x01000000 - - -;" \ - "go 0x01000000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h deleted file mode 100644 index 57d8d17..0000000 --- a/include/configs/T4240RDB.h +++ /dev/null @@ -1,696 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -/* - * T4240 RDB board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE4 - -#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg -#ifndef CONFIG_SDCARD -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#else -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_PAD_TO 0x40000 -#define CONFIG_SPL_MAX_SIZE 0x28000 -#define RESET_VECTOR_OFFSET 0x27FFC -#define BOOT_PAGE_OFFSET 0x27000 - -#ifdef CONFIG_SDCARD -#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_START 0x00200000 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#endif -#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_sd_rcw.cfg -#endif - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_SKIP_RELOCATE -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -#endif -#endif /* CONFIG_RAMBOOT_PBL */ - -#define CONFIG_DDR_ECC - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BTB /* toggle branch predition */ -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_DDR_SPD - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull - -/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull - -#ifdef CONFIG_PCI -#if !defined(CONFIG_DM_PCI) -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 0x800) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ 133333333 - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -/* - * DDR Setup - */ -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS1 0x52 -#define SPD_EEPROM_ADDRESS2 0x54 -#define SPD_EEPROM_ADDRESS3 0x56 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * IFC Definitions - */ -#define CONFIG_SYS_NOR0_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0xf) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80 - -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} - -/* NAND Flash on IFC */ -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_BASE 0xff800000 -#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE) - -#define CONFIG_SYS_NAND_CSPR_EXT (0xf) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ - | CSOR_NAND_PB(128)) /*Page Per Block = 128*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_DDR_LAW 11 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 - -/* CPLD on IFC */ -#define CONFIG_SYS_CPLD_BASE 0xffdf0000 -#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE) -#define CONFIG_SYS_CSPR3_EXT (0xf) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) - -#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CSOR3 0x0 - -/* CPLD Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0x1f)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -/* I2C */ -#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */ -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */ -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */ - -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_MUX_CH_VSC3316_FS 0xc -#define I2C_MUX_CH_VSC3316_BS 0xd - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -#define CONFIG_VID_FLS_ENV "t4240rdb_vdd_mv" -#ifndef CONFIG_SPL_BUILD -#define CONFIG_VID -#endif -#define CONFIG_VOL_MONITOR_IR36021_SET -#define CONFIG_VOL_MONITOR_IR36021_READ -/* The lowest and highest voltage allowed for T4240RDB */ -#define VDD_MV_MIN 819 -#define VDD_MV_MAX 1212 - -/* - * eSPI - Enhanced SPI - */ - -/* Qman/Bman */ -#ifndef CONFIG_NOBQFMAN -#define CONFIG_SYS_BMAN_NUM_PORTALS 50 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 50 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_PMAN -#define CONFIG_SYS_DPAA_DCE -#define CONFIG_SYS_DPAA_RMAN -#define CONFIG_SYS_INTERLAKEN - -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif /* CONFIG_NOBQFMAN */ - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_CORTINA -#define CONFIG_SYS_CORTINA_FW_IN_NOR -#define CONFIG_CORTINA_FW_ADDR 0xefe00000 -#define CONFIG_CORTINA_FW_LENGTH 0x40000 -#define CONFIG_PHY_TERANETICS -#define SGMII_PHY_ADDR1 0x0 -#define SGMII_PHY_ADDR2 0x1 -#define SGMII_PHY_ADDR3 0x2 -#define SGMII_PHY_ADDR4 0x3 -#define SGMII_PHY_ADDR5 0x4 -#define SGMII_PHY_ADDR6 0x5 -#define SGMII_PHY_ADDR7 0x6 -#define SGMII_PHY_ADDR8 0x7 -#define FM1_10GEC1_PHY_ADDR 0x10 -#define FM1_10GEC2_PHY_ADDR 0x11 -#define FM2_10GEC1_PHY_ADDR 0x12 -#define FM2_10GEC2_PHY_ADDR 0x13 -#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR -#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR -#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR -#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR -#endif - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* -* USB -*/ -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_HAS_FSL_DR_USB - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - - -#define __USB_PHY_TYPE utmi - -/* - * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be - * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way - * interleaving. It can be cacheline, page, bank, superbank. - * See doc/README.fsl-ddr for details. - */ -#ifdef CONFIG_ARCH_T4240 -#define CTRL_INTLV_PREFERED 3way_4KB -#else -#define CTRL_INTLV_PREFERED cacheline -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:" \ - "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \ - "bank_intlv=auto;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=t4240rdb/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=t4240rdb/t4240rdb.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#define CONFIG_LINUX \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "setenv ramdiskaddr 0x02000000;" \ - "setenv fdtaddr 0x00c00000;" \ - "setenv loadaddr 0x1000000;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_LINUX - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h deleted file mode 100644 index 9bf5d9d..0000000 --- a/include/configs/TQM834x.h +++ /dev/null @@ -1,288 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2005 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * TQM8349 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -/* board pre init: do not call, nothing to do */ - -/* detect the number of flash banks */ - -/* - * DDR Setup - */ - /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define DDR_CASLAT_25 /* CASLAT set to 2.5 */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_SPD_EEPROM /* do not use SPD EEPROM for DDR setup */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * FLASH on the Local Bus - */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_BASE 0x80000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size in MB */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sectors */ - -/* - * FLASH bank number detection - */ - -/* - * When CONFIG_SYS_MAX_FLASH_BANKS_DETECT is defined, the actual number of - * Flash banks has to be determined at runtime and stored in a gloabl variable - * tqm834x_num_flash_banks. The value of CONFIG_SYS_MAX_FLASH_BANKS_DETECT is - * only used instead of CONFIG_SYS_MAX_FLASH_BANKS to allocate the array - * flash_info, and should be made sufficiently large to accomodate the number - * of banks that might actually be detected. Since most (all?) Flash related - * functions use CONFIG_SYS_MAX_FLASH_BANKS as the number of actual banks on - * the board, it is defined as tqm834x_num_flash_banks. - */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 - -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ - - -/* disable remaining mappings */ -#define CONFIG_SYS_BR1_PRELIM 0x00000000 -#define CONFIG_SYS_OR1_PRELIM 0x00000000 - -#define CONFIG_SYS_BR2_PRELIM 0x00000000 -#define CONFIG_SYS_OR2_PRELIM 0x00000000 - -#define CONFIG_SYS_BR3_PRELIM 0x00000000 -#define CONFIG_SYS_OR3_PRELIM 0x00000000 - -/* - * Monitor config - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT -#else -# undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - - /* Reserve 384 kB = 3 sect. for Mon */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) - /* Reserve 512 kB for malloc */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -/* I2C EEPROM, configuration for onboard EEPROMs 24C256 and 24C32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* 16 bit */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 32 bytes/write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 12 /* 10ms +/- 20% */ - -/* I2C RTC */ -#define CONFIG_RTC_DS1337 /* use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - -/* - * TSEC - */ - -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 2 -#define TSEC2_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -/* PCI1 host bridge */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE \ - (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x1000000 /* 16M */ - -#undef CONFIG_EEPRO100 -#define CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BASE - #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_MEM_BASE - #define PCI_IDSEL_NUMBER 0x1c /* slot0 (IDSEL) = 28 */ -#endif - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * Environment - */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ -#define CONFIG_ENV_SIZE 0x8000 /* 32K max size */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 400000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=tqm834x\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcons=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ - "flash_nfs_old=run nfsargs addip addcons;" \ - "bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addcons;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "flash_self_old=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_self=run ramargs addip addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs_old=tftp 400000 ${bootfile};" \ - "run nfsargs addip addcons;bootm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons; " \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "bootfile=tqm834x/uImage\0" \ - "fdtfile=tqm834x/tqm834x.dtb\0" \ - "kernel_addr_r=400000\0" \ - "fdt_addr_r=600000\0" \ - "ramdisk_addr_r=800000\0" \ - "kernel_addr=800C0000\0" \ - "fdt_addr=800A0000\0" \ - "ramdisk_addr=80300000\0" \ - "u-boot=tqm834x/u-boot.bin\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "update=protect off 80000000 +${filesize};" \ - "era 80000000 +${filesize};" \ - "cp.b 200000 80000000 ${filesize}\0" \ - "upd=run load update\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -/* - * JFFS2 partitions - */ -/* mtdparts command line support */ - -/* default mtd partition table */ -#endif /* __CONFIG_H */ diff --git a/include/configs/UCP1020.h b/include/configs/UCP1020.h deleted file mode 100644 index 6a01a90..0000000 --- a/include/configs/UCP1020.h +++ /dev/null @@ -1,883 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2019 Arcturus Networks, Inc. - * https://www.arcturusnetworks.com/products/ucp1020/ - * based on include/configs/p1_p2_rdb_pc.h - * original copyright follows: - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * QorIQ uCP1020-xx boards configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/*** Arcturus FirmWare Environment */ - -#define MAX_SERIAL_SIZE 15 -#define MAX_HWADDR_SIZE 17 - -#define MAX_FWENV_ADDR 4 - -#define FWENV_MMC 1 -#define FWENV_SPI_FLASH 2 -#define FWENV_NOR_FLASH 3 -/* - #define FWENV_TYPE FWENV_MMC - #define FWENV_TYPE FWENV_SPI_FLASH -*/ -#define FWENV_TYPE FWENV_NOR_FLASH - -#if (FWENV_TYPE == FWENV_MMC) -#ifndef CONFIG_SYS_MMC_ENV_DEV -#define CONFIG_SYS_MMC_ENV_DEV 1 -#endif -#define FWENV_ADDR1 -1 -#define FWENV_ADDR2 -1 -#define FWENV_ADDR3 -1 -#define FWENV_ADDR4 -1 -#define EMPY_CHAR 0 -#endif - -#if (FWENV_TYPE == FWENV_SPI_FLASH) -#ifndef CONFIG_SF_DEFAULT_SPEED -#define CONFIG_SF_DEFAULT_SPEED 1000000 -#endif -#ifndef CONFIG_SF_DEFAULT_MODE -#define CONFIG_SF_DEFAULT_MODE SPI_MODE0 -#endif -#ifndef CONFIG_SF_DEFAULT_CS -#define CONFIG_SF_DEFAULT_CS 0 -#endif -#ifndef CONFIG_SF_DEFAULT_BUS -#define CONFIG_SF_DEFAULT_BUS 0 -#endif -#define FWENV_ADDR1 (0x200 - sizeof(smac)) -#define FWENV_ADDR2 (0x400 - sizeof(smac)) -#define FWENV_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac)) -#define FWENV_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac)) -#define EMPY_CHAR 0xff -#endif - -#if (FWENV_TYPE == FWENV_NOR_FLASH) -#define FWENV_ADDR1 0xEC080000 -#define FWENV_ADDR2 -1 -#define FWENV_ADDR3 -1 -#define FWENV_ADDR4 -1 -#define EMPY_CHAR 0xff -#endif -/***********************************/ - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#if defined(CONFIG_TARTGET_UCP1020T1) - -#define CONFIG_UCP1020_REV_1_3 - -#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1" - -#define CONFIG_TSEC1 -#define CONFIG_TSEC3 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF -#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE -#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD -#define CONFIG_IPADDR 10.80.41.229 -#define CONFIG_SERVERIP 10.80.41.227 -#define CONFIG_NETMASK 255.255.252.0 -#define CONFIG_ETHPRIME "eTSEC3" - -#define CONFIG_SYS_L2_SIZE (256 << 10) - -#endif - -#if defined(CONFIG_TARGET_UCP1020) - -#define CONFIG_UCP1020 -#define CONFIG_UCP1020_REV_1_3 - -#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR" - -#define CONFIG_TSEC1 -#define CONFIG_TSEC3 -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF -#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE -#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD -#define CONFIG_IPADDR 192.168.1.81 -#define CONFIG_IPADDR1 192.168.1.82 -#define CONFIG_IPADDR2 192.168.1.83 -#define CONFIG_SERVERIP 192.168.1.80 -#define CONFIG_GATEWAYIP 102.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_ETHPRIME "eTSEC1" - -#undef CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#define CONFIG_SYS_L2_SIZE (256 << 10) - -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#endif - -#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000 - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_DDR_ECC_ENABLE -#ifndef CONFIG_DDR_ECC_ENABLE -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD -#endif -#define CONFIG_SYS_SPD_BUS_NUM 1 - -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* Default settings for DDR3 */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#ifdef CONFIG_DDR_ECC_ENABLE -#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */ -#else -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#endif -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x40461520 -#define CONFIG_SYS_DDR_MODE_2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2) - * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 - * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable - * (early boot only) - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 - -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) - -#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ -/* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -/* Size of used area in RAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */ - -#define CONFIG_SYS_PMC_BASE 0xff980000 -#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE -#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ - BR_PS_8 | BR_V) -#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) - -#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ -#ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ -#endif - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) -#define CONFIG_NS16550_MIN_FUNCTIONS -#endif - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } -#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */ - -#define CONFIG_RTC_DS1337 -#define CONFIG_RTC_DS1337_NOOSC -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18 -#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C -#define CONFIG_SYS_I2C_IDT6V49205B 0x69 - -#if defined(CONFIG_PCI) -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9" -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10" -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* - * Environment - */ -#ifdef CONFIG_ENV_FIT_UCBOOT - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ - -#else - - -#ifdef CONFIG_RAMBOOT_SPIFLASH - -#define CONFIG_ENV_SIZE 0x3000 /* 12KB */ -#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */ -#define CONFIG_ENV_SECT_SIZE 0x1000 - -#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#endif - -#elif defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#elif defined(CONFIG_SYS_RAMBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 - -#else -#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000) -#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT) -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#endif - -#endif - -#endif /* CONFIG_ENV_FIT_UCBOOT */ - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_FSL -#endif -#endif - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#endif - -/* Misc Extra Settings */ -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ -#endif - -/* - * Environment Configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#if defined(CONFIG_UCP1020_REV_1_2) || defined(CONFIG_UCP1020_REV_1_3) -#else -#error "UCP1020 module revision is not defined !!!" -#endif - -#define CONFIG_BOOTP_SERVERIP - -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 4 -#define TSEC2_PHY_ADDR 0 -#define TSEC2_PHY_ADDR_SGMII 0x00 -#define TSEC3_PHY_ADDR 6 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#endif - -#define CONFIG_HOSTNAME "UCP1020" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#if defined(CONFIG_DONGLE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run prog_spi_mbrbootcramfs\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"cramfsfile=image.cramfs\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ - "protect off $nor_recoveryaddr +$filesize; " \ - "erase $nor_recoveryaddr +$filesize; " \ - "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ - "protect on $nor_recoveryaddr +$filesize\0 " \ -"flashuboot=tftp $ubootaddr $ubootfile; " \ - "protect off $nor_ubootaddr +$filesize; " \ - "erase $nor_ubootaddr +$filesize; " \ - "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ - "protect on $nor_ubootaddr +$filesize\0 " \ -"flashworking=tftp $workingaddr $cramfsfile; " \ - "protect off $nor_workingaddr +$filesize; " \ - "erase $nor_workingaddr +$filesize; " \ - "cp.b $workingaddr $nor_workingaddr $filesize; " \ - "protect on $nor_workingaddr +$filesize\0 " \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020d.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"mmbr=uCP1020Quiet.mbr\0" \ -"mmcpart=0:2\0" \ -"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ - "mmc erase 1 1; " \ - "mmc write $loadaddr 1 1\0" \ -"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \ - "mmc erase 0x40 0x400; " \ - "mmc write $loadaddr 0x40 0x400\0" \ -"netdev=eth0\0" \ -"nor_recoveryaddr=0xEC0A0000\0" \ -"nor_ubootaddr=0xEFF80000\0" \ -"nor_workingaddr=0xECFA0000\0" \ -"norbootrecovery=setenv bootargs $recoverybootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadrecovery; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norbootworking=setenv bootargs $workingbootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadworking; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_recoveryaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_workingaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"prog_spi_mbr=run spi__mbr\0" \ -"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \ -"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \ - "run spi__cramfs\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"recoveryaddr=0x02F00000\0" \ -"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeC000000 +$filesize; " \ - "erase 0xEC000000 +$filesize; " \ - "cp.b $loadaddr 0xEC000000 $filesize; " \ - "cmp.b $loadaddr 0xEC000000 $filesize; " \ - "protect on 0xeC000000 +$filesize\0" \ -"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeFF80000 +$filesize; " \ - "erase 0xEFF80000 +$filesize; " \ - "cp.b $loadaddr 0xEFF80000 $filesize; " \ - "cmp.b $loadaddr 0xEFF80000 $filesize; " \ - "protect on 0xeFF80000 +$filesize\0" \ -"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \ - "sf probe 0; sf erase 0x8000 +$filesize; " \ - "sf write $loadaddr 0x8000 $filesize\0" \ -"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \ - "protect off 0xec0a0000 +$filesize; " \ - "erase 0xeC0A0000 +$filesize; " \ - "cp.b $loadaddr 0xeC0A0000 $filesize; " \ - "protect on 0xec0a0000 +$filesize\0" \ -"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ - "sf probe 1; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \ - "sf probe 0; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=0x01000000\0" \ -"ubootfile=u-boot.bin\0" \ -"ubootd=u-boot4dongle.bin\0" \ -"upgrade=run flashworking\0" \ -"usb_phy_type=ulpi\0 " \ -"workingaddr=0x02F00000\0" \ -"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" - -#else - -#if defined(CONFIG_UCP1020T1) - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"cramfsfile=image.cramfs\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashrecovery=tftp $recoveryaddr $cramfsfile; " \ - "protect off $nor_recoveryaddr +$filesize; " \ - "erase $nor_recoveryaddr +$filesize; " \ - "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \ - "protect on $nor_recoveryaddr +$filesize\0 " \ -"flashuboot=tftp $ubootaddr $ubootfile; " \ - "protect off $nor_ubootaddr +$filesize; " \ - "erase $nor_ubootaddr +$filesize; " \ - "cp.b $ubootaddr $nor_ubootaddr $filesize; " \ - "protect on $nor_ubootaddr +$filesize\0 " \ -"flashworking=tftp $workingaddr $cramfsfile; " \ - "protect off $nor_workingaddr +$filesize; " \ - "erase $nor_workingaddr +$filesize; " \ - "cp.b $workingaddr $nor_workingaddr $filesize; " \ - "protect on $nor_workingaddr +$filesize\0 " \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"netdev=eth0\0" \ -"nor_recoveryaddr=0xEC0A0000\0" \ -"nor_ubootaddr=0xEFF80000\0" \ -"nor_workingaddr=0xECFA0000\0" \ -"norbootrecovery=setenv bootargs $recoverybootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadrecovery; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norbootworking=setenv bootargs $workingbootargs" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "run norloadworking; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_recoveryaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $nor_workingaddr; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"othbootargs=quiet\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"recoveryaddr=0x02F00000\0" \ -"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"silent=1\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=0x01000000\0" \ -"ubootfile=u-boot.bin\0" \ -"upgrade=run flashworking\0" \ -"workingaddr=0x02F00000\0" \ -"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" - -#else /* For Arcturus Modules */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"bootcmd=run norkernel\0" \ -"bootfile=uImage\0" \ -"consoledev=ttyS0\0" \ -"dtbaddr=0x00c00000\0" \ -"dtbfile=image.dtb\0" \ -"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ -"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \ -"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \ -"fileaddr=0x01000000\0" \ -"filesize=0x00080000\0" \ -"flashmbr=sf probe 0; " \ - "tftp $loadaddr $mbr; " \ - "sf erase $mbr_offset +$filesize; " \ - "sf write $loadaddr $mbr_offset $filesize\0" \ -"flashuboot=tftp $loadaddr $ubootfile; " \ - "protect off $nor_ubootaddr0 +$filesize; " \ - "erase $nor_ubootaddr0 +$filesize; " \ - "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \ - "protect on $nor_ubootaddr0 +$filesize; " \ - "protect off $nor_ubootaddr1 +$filesize; " \ - "erase $nor_ubootaddr1 +$filesize; " \ - "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \ - "protect on $nor_ubootaddr1 +$filesize\0 " \ -"format0=protect off $part0base +$part0size; " \ - "erase $part0base +$part0size\0" \ -"format1=protect off $part1base +$part1size; " \ - "erase $part1base +$part1size\0" \ -"format2=protect off $part2base +$part2size; " \ - "erase $part2base +$part2size\0" \ -"format3=protect off $part3base +$part3size; " \ - "erase $part3base +$part3size\0" \ -"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \ -"kerneladdr=0x01100000\0" \ -"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \ -"kernelfile=uImage\0" \ -"loadaddr=0x01000000\0" \ -"mbr=uCP1020.mbr\0" \ -"mbr_offset=0x00000000\0" \ -"netdev=eth0\0" \ -"nor_ubootaddr0=0xEC000000\0" \ -"nor_ubootaddr1=0xEFF80000\0" \ -"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \ - "run norkernelload; " \ - "bootm $kerneladdr - $dtbaddr\0" \ -"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \ - "setenv cramfsaddr $part0base; " \ - "cramfsload $dtbaddr $dtbfile; " \ - "cramfsload $kerneladdr $kernelfile\0" \ -"part0base=0xEC100000\0" \ -"part0size=0x00700000\0" \ -"part1base=0xEC800000\0" \ -"part1size=0x02000000\0" \ -"part2base=0xEE800000\0" \ -"part2size=0x00800000\0" \ -"part3base=0xEF000000\0" \ -"part3size=0x00F80000\0" \ -"partENVbase=0xEC080000\0" \ -"partENVsize=0x00080000\0" \ -"program0=tftp part0-000000.bin; " \ - "protect off $part0base +$filesize; " \ - "erase $part0base +$filesize; " \ - "cp.b $loadaddr $part0base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part0base $filesize\0" \ -"program1=tftp part1-000000.bin; " \ - "protect off $part1base +$filesize; " \ - "erase $part1base +$filesize; " \ - "cp.b $loadaddr $part1base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part1base $filesize\0" \ -"program2=tftp part2-000000.bin; " \ - "protect off $part2base +$filesize; " \ - "erase $part2base +$filesize; " \ - "cp.b $loadaddr $part2base $filesize; " \ - "echo Verifying...; " \ - "cmp.b $loadaddr $part2base $filesize\0" \ -"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \ - " console=$consoledev,$baudrate $othbootargs; " \ - "tftp $rootfsaddr $rootfsfile; " \ - "tftp $loadaddr $kernelfile; " \ - "tftp $dtbaddr $dtbfile; " \ - "bootm $loadaddr $rootfsaddr $dtbaddr\0" \ -"ramdisk_size=120000\0" \ -"ramdiskfile=rootfs.ext2.gz.uboot\0" \ -"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \ - "mw.l 0xffe0f008 0x00400000\0" \ -"rootfsaddr=0x02F00000\0" \ -"rootfsfile=rootfs.ext2.gz.uboot\0" \ -"rootpath=/opt/nfsroot\0" \ -"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \ - "sf probe 0; sf erase 0 +$filesize; " \ - "sf write $loadaddr 0 $filesize\0" \ -"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \ - "protect off 0xeC000000 +$filesize; " \ - "erase 0xEC000000 +$filesize; " \ - "cp.b $loadaddr 0xEC000000 $filesize; " \ - "cmp.b $loadaddr 0xEC000000 $filesize; " \ - "protect on 0xeC000000 +$filesize\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\ -"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootfile=u-boot.bin\0" \ -"upgrade=run flashuboot\0" \ -"usb_phy_type=ulpi\0 " \ -"boot_nfs= " \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr\0" \ -"boot_hd = " \ - "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "usb start;" \ - "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \ - "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \ - "bootm $loadaddr - $fdtaddr\0" \ -"boot_usb_fat = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "usb start;" \ - "fatload usb 0:2 $loadaddr $bootfile;" \ - "fatload usb 0:2 $fdtaddr $fdtfile;" \ - "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ -"boot_usb_ext2 = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "usb start;" \ - "ext2load usb 0:4 $loadaddr $bootfile;" \ - "ext2load usb 0:4 $fdtaddr $fdtfile;" \ - "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \ -"boot_nor = " \ - "setenv bootargs root=/dev/$jffs2nor rw " \ - "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \ - "bootm $norbootaddr - $norfdtaddr\0 " \ -"boot_ram = " \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs " \ - "ramdisk_size=$ramdisk_size;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr\0" - -#endif -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/adp-ae3xx.h b/include/configs/adp-ae3xx.h deleted file mode 100644 index 1fe3391..0000000 --- a/include/configs/adp-ae3xx.h +++ /dev/null @@ -1,223 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * CPU and Board Configuration Options - */ -#define CONFIG_USE_INTERRUPT - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_SKIP_TRUNOFF_WATCHDOG - -#define CONFIG_ARCH_MAP_SYSMEM - -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SERVERIP - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#ifdef CONFIG_OF_CONTROL -#undef CONFIG_OF_SEPARATE -#define CONFIG_OF_EMBED -#endif -#endif - -/* - * Timer - */ -#define CONFIG_SYS_CLK_FREQ 39062500 -#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ - -/* - * Use Externel CLOCK or PCLK - */ -#undef CONFIG_FTRTC010_EXTCLK - -#ifndef CONFIG_FTRTC010_EXTCLK -#define CONFIG_FTRTC010_PCLK -#endif - -#ifdef CONFIG_FTRTC010_EXTCLK -#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ -#else -#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ -#endif - -#define TIMER_LOAD_VAL 0xffffffff - -/* - * Real Time Clock - */ -#define CONFIG_RTC_FTRTC010 - -/* - * Real Time Clock Divider - * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) - */ -#define OSC_5MHZ (5*1000000) -#define OSC_CLK (4*OSC_5MHZ) -#define RTC_DIV_COUNT (0.5) /* Why?? */ - -/* - * Serial console configuration - */ - -/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif -#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ - -/* - * Miscellaneous configurable options - */ - -/* - * Size of malloc() pool - */ -/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ - -#define PHYS_SDRAM_1 \ - (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ - -#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Load address and memory test area should agree with - * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x300000 - -/* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) - -/* - * Static memory controller configuration - */ -#define CONFIG_FTSMC020 - -#ifdef CONFIG_FTSMC020 -#include - -#define CONFIG_SYS_FTSMC020_CONFIGS { \ - { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ - { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ -} - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ -#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ - FTSMC020_TPR_AST(1) | \ - FTSMC020_TPR_CTW(1) | \ - FTSMC020_TPR_ATI(1) | \ - FTSMC020_TPR_AT2(1) | \ - FTSMC020_TPR_WTC(1) | \ - FTSMC020_TPR_AHT(1) | \ - FTSMC020_TPR_TRNA(1)) -#endif - -/* - * FLASH on ADP_AG101P is connected to BANK0 - * Just disalbe the other BANK to avoid detection error. - */ -#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ - FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ - FTSMC020_TPR_CTW(3) | \ - FTSMC020_TPR_ATI(0xf) | \ - FTSMC020_TPR_AT2(3) | \ - FTSMC020_TPR_WTC(3) | \ - FTSMC020_TPR_AHT(3) | \ - FTSMC020_TPR_TRNA(0xf)) - -#define FTSMC020_BANK1_CONFIG (0x00) -#define FTSMC020_BANK1_TIMING (0x00) -#endif /* CONFIG_FTSMC020 */ - -/* - * FLASH and environment organization - */ -/* use CFI framework */ - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL - -/* support JEDEC */ -#ifdef CONFIG_CFI_FLASH -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#endif - -/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ -#define PHYS_FLASH_1 0x88000000 /* BANK 0 */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ - -/* max number of memory banks */ -/* - * There are 4 banks supported for this Controller, - * but we have only 1 bank connected to flash on board - */ -#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#endif -#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} - -/* max number of sectors on one chip */ -#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* environments */ -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x140000 -#define CONFIG_ENV_SIZE 8192 -#define CONFIG_ENV_OVERWRITE - - -/* SPI FLASH */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - -/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) -/* Increase max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -#endif /* __CONFIG_H */ diff --git a/include/configs/adp-ag101p.h b/include/configs/adp-ag101p.h deleted file mode 100644 index 6cf494e..0000000 --- a/include/configs/adp-ag101p.h +++ /dev/null @@ -1,338 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Shawn Lin, Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * CPU and Board Configuration Options - */ -#define CONFIG_USE_INTERRUPT - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_ARCH_MAP_SYSMEM - -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SERVERIP - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_MEM_REMAP -#endif - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#ifdef CONFIG_OF_CONTROL -#undef CONFIG_OF_SEPARATE -#define CONFIG_OF_EMBED -#endif -#endif - -/* - * Timer - */ -#define CONFIG_SYS_CLK_FREQ 39062500 -#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ - -/* - * Use Externel CLOCK or PCLK - */ -#undef CONFIG_FTRTC010_EXTCLK - -#ifndef CONFIG_FTRTC010_EXTCLK -#define CONFIG_FTRTC010_PCLK -#endif - -#ifdef CONFIG_FTRTC010_EXTCLK -#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ -#else -#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ -#endif - -#define TIMER_LOAD_VAL 0xffffffff - -/* - * Real Time Clock - */ -#define CONFIG_RTC_FTRTC010 - -/* - * Real Time Clock Divider - * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) - */ -#define OSC_5MHZ (5*1000000) -#define OSC_CLK (4*OSC_5MHZ) -#define RTC_DIV_COUNT (0.5) /* Why?? */ - -/* - * Serial console configuration - */ - -/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif -#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ - -/* - * Miscellaneous configurable options - */ - -/* - * Size of malloc() pool - */ -/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - -/* - * AHB Controller configuration - */ -#define CONFIG_FTAHBC020S - -#ifdef CONFIG_FTAHBC020S -#include - -/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ -#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 - -/* - * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, - * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote - * in C language. - */ -#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ - (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ - FTAHBC020S_SLAVE_BSR_SIZE(0xb)) -#endif - -/* - * Watchdog - */ -#define CONFIG_FTWDT010_WATCHDOG - -/* - * PMU Power controller configuration - */ -#define CONFIG_PMU -#define CONFIG_FTPMU010_POWER - -#ifdef CONFIG_FTPMU010_POWER -#include -#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E -#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ - FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ - FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ - FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ - FTPMU010_SDRAMHTC_CKE_DCSR | \ - FTPMU010_SDRAMHTC_DQM_DCSR | \ - FTPMU010_SDRAMHTC_SDCLK_DCSR) -#endif - -/* - * SDRAM controller configuration - */ -#define CONFIG_FTSDMC021 - -#ifdef CONFIG_FTSDMC021 -#include - -#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ - FTSDMC021_TP1_TRP(1) | \ - FTSDMC021_TP1_TRCD(1) | \ - FTSDMC021_TP1_TRF(3) | \ - FTSDMC021_TP1_TWR(1) | \ - FTSDMC021_TP1_TCL(2)) - -#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ - FTSDMC021_TP2_INI_REFT(8) | \ - FTSDMC021_TP2_REF_INTV(0x180)) - -/* - * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, - * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in - * C language. - */ -#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ - FTSDMC021_CR1_DSZ(3) | \ - FTSDMC021_CR1_MBW(2) | \ - FTSDMC021_CR1_BNKSIZE(6)) - -#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ - FTSDMC021_CR2_IREF | \ - FTSDMC021_CR2_ISMR) - -#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE -#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ - CONFIG_SYS_FTSDMC021_BANK0_BASE) - -#define CONFIG_SYS_FTSDMC021_BANK1_BASE \ - (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) -#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ - CONFIG_SYS_FTSDMC021_BANK1_BASE) -#endif - -/* - * Physical Memory Map - */ -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ -#else -#ifdef CONFIG_MEM_REMAP -#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ -#else -#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ -#endif -#endif - -#define PHYS_SDRAM_1 \ - (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ - -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#else -#ifdef CONFIG_MEM_REMAP -#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#else -#define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#endif -#endif - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 - -#ifdef CONFIG_MEM_REMAP -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ - GENERATED_GBL_DATA_SIZE) -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) -#endif /* CONFIG_MEM_REMAP */ - -/* - * Load address and memory test area should agree with - * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x300000 - -/* memtest works on 63 MB in DRAM */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) - -/* - * Static memory controller configuration - */ -#define CONFIG_FTSMC020 - -#ifdef CONFIG_FTSMC020 -#include - -#define CONFIG_SYS_FTSMC020_CONFIGS { \ - { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ - { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ -} - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ -#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ - FTSMC020_TPR_AST(1) | \ - FTSMC020_TPR_CTW(1) | \ - FTSMC020_TPR_ATI(1) | \ - FTSMC020_TPR_AT2(1) | \ - FTSMC020_TPR_WTC(1) | \ - FTSMC020_TPR_AHT(1) | \ - FTSMC020_TPR_TRNA(1)) -#endif - -/* - * FLASH on ADP_AG101P is connected to BANK0 - * Just disalbe the other BANK to avoid detection error. - */ -#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ - FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ - FTSMC020_BANK_SIZE_32M | \ - FTSMC020_BANK_MBW_32) - -#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ - FTSMC020_TPR_CTW(3) | \ - FTSMC020_TPR_ATI(0xf) | \ - FTSMC020_TPR_AT2(3) | \ - FTSMC020_TPR_WTC(3) | \ - FTSMC020_TPR_AHT(3) | \ - FTSMC020_TPR_TRNA(0xf)) - -#define FTSMC020_BANK1_CONFIG (0x00) -#define FTSMC020_BANK1_TIMING (0x00) -#endif /* CONFIG_FTSMC020 */ - -/* - * FLASH and environment organization - */ -/* use CFI framework */ - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL - -/* support JEDEC */ - -/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ -#ifdef CONFIG_SKIP_LOWLEVEL_INIT -#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ -#else -#ifdef CONFIG_MEM_REMAP -#define PHYS_FLASH_1 0x80000000 /* BANK 0 */ -#else -#define PHYS_FLASH_1 0x00000000 /* BANK 0 */ -#endif -#endif /* CONFIG_MEM_REMAP */ - -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ - -/* max number of memory banks */ -/* - * There are 4 banks supported for this Controller, - * but we have only 1 bank connected to flash on board - */ -#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#endif -#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} - -/* max number of sectors on one chip */ -#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) -#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* environments */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) -#define CONFIG_ENV_SIZE 8192 -#define CONFIG_ENV_OVERWRITE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - -/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) -/* Increase max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -#endif /* __CONFIG_H */ diff --git a/include/configs/advantech_dms-ba16.h b/include/configs/advantech_dms-ba16.h deleted file mode 100644 index 1298859..0000000 --- a/include/configs/advantech_dms-ba16.h +++ /dev/null @@ -1,242 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Timesys Corporation - * Copyright (C) 2016 Advantech Corporation - * Copyright (C) 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __ADVANTECH_DMSBA16_CONFIG_H -#define __ADVANTECH_DMSBA16_CONFIG_H - -#include -#include - -#define CONFIG_BOARD_NAME "Advantech DMS-BA16" - -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" -#define CONFIG_EXTRA_BOOTARGS "panic=10" - -#define CONFIG_BOOT_DIR "" -#define CONFIG_LOADCMD "fatload" -#define CONFIG_RFSPART "2" - -#include "mx6_common.h" -#include - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART - -/* SATA Configs */ -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_USBD_HS - -/* Networking Configs */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 -#define CONFIG_PHY_ATHEROS - -/* Serial Flash */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_LOADADDR 0x12000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=" CONFIG_BOOT_DIR "/uImage\0" \ - "uboot=u-boot.imx\0" \ - "fdt_file=" CONFIG_BOOT_DIR "/" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=yes\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "sddev=0\0" \ - "emmcdev=1\0" \ - "partnum=1\0" \ - "loadcmd=" CONFIG_LOADCMD "\0" \ - "rfspart=" CONFIG_RFSPART "\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "update_sf_uboot=" \ - "if tftp $loadaddr $uboot; then " \ - "sf probe; " \ - "sf erase 0 0xC0000; " \ - "sf write $loadaddr 0x400 $filesize; " \ - "echo 'U-Boot upgraded. Please reset'; " \ - "fi\0" \ - "setargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${rootdev} rw rootwait " CONFIG_EXTRA_BOOTARGS "\0" \ - "loadbootscript=" \ - "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from ${dev}:${devnum}:${partnum};" \ - " source\0" \ - "loadimage=" \ - "${loadcmd} ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ - "loadfdt=${loadcmd} ${dev} ${devnum}:${partnum} ${fdt_addr} ${fdt_file}\0" \ - "tryboot=" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run doboot; " \ - "fi; " \ - "fi;\0" \ - "doboot=echo Booting from ${dev}:${devnum}:${partnum} ...; " \ - "run setargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "usb start; " \ - "setenv dev usb; " \ - "setenv devnum 0; " \ - "setenv rootdev sda${rfspart}; " \ - "run tryboot; " \ - \ - "setenv dev mmc; " \ - "setenv rootdev mmcblk0p${rfspart}; " \ - \ - "setenv devnum ${sddev}; " \ - "if mmc dev ${devnum}; then " \ - "run tryboot; " \ - "fi; " \ - \ - "setenv devnum ${emmcdev}; " \ - "setenv rootdev mmcblk${emmcdev}p${rfspart}; " \ - "if mmc dev ${devnum}; then " \ - "run tryboot; " \ - "fi; " \ - \ - "bmode usb; " \ - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ - -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) - -#define CONFIG_SYS_FSL_USDHC_NUM 3 - -/* Framebuffer */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP -#endif - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 - -#endif /* __ADVANTECH_DMSBA16_CONFIG_H */ diff --git a/include/configs/alt.h b/include/configs/alt.h deleted file mode 100644 index bb52675..0000000 --- a/include/configs/alt.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/alt.h - * This file is alt board configuration. - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -#ifndef __ALT_H -#define __ALT_H - -#include "rcar-gen2-common.h" - -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 -#define STACK_AREA_SIZE 0x00100000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) -#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "usb_pgood_delay=2000\0" - -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_CONS_SCIF2 -#define CONFIG_SH_SCIF_CLK_FREQ 65000000 -#endif - -#endif /* __ALT_H */ diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h deleted file mode 100644 index be57106..0000000 --- a/include/configs/am335x_evm.h +++ /dev/null @@ -1,332 +0,0 @@ -/* - * am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_AM335X_EVM_H -#define __CONFIG_AM335X_EVM_H - -#include -#include - -#ifndef CONFIG_SPL_BUILD -# define CONFIG_TIMESTAMP -#endif - -#define CONFIG_SYS_BOOTM_LEN SZ_16M - -#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#ifdef CONFIG_NAND -#define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ - "nand read ${loadaddr} NAND.kernel; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" -#else -#define NANDARGS "" -#endif - -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance"; "\ - "setenv bootpart " #instance":2 ; "\ - "run mmcboot\0" - -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel "=" \ - "run nandboot\0" - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#if CONFIG_IS_ENABLED(CMD_PXE) -# define BOOT_TARGET_PXE(func) func(PXE, pxe, na) -#else -# define BOOT_TARGET_PXE(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_DHCP) -# define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) -#else -# define BOOT_TARGET_DHCP(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ - func(MMC, mmc, 1) \ - func(LEGACY_MMC, legacy_mmc, 1) \ - func(NAND, nand, 0) \ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) - -#include - -#ifndef CONFIG_SPL_BUILD -#include -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - DEFAULT_FIT_TI_ARGS \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "fdtfile=undefined\0" \ - "console=ttyO0,115200n8\0" \ - "partitions=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=bootloader,start=384K,size=1792K," \ - "uuid=${uuid_gpt_bootloader};" \ - "name=rootfs,start=2688K,size=-,uuid=${uuid_gpt_rootfs}\0" \ - "optargs=\0" \ - "ramroot=/dev/ram0 rw\0" \ - "ramrootfstype=ext2\0" \ - "spiroot=/dev/mtdblock4 rw\0" \ - "spirootfstype=jffs2\0" \ - "spisrcaddr=0xe0000\0" \ - "spiimgsize=0x362000\0" \ - "spibusno=0\0" \ - "spiargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${spiroot} " \ - "rootfstype=${spirootfstype}\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "spiboot=echo Booting from spi ...; " \ - "run spiargs; " \ - "sf probe ${spibusno}:0; " \ - "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ - "bootz ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ - "findfdt="\ - "if test $board_name = A335BONE; then " \ - "setenv fdtfile am335x-bone.dtb; fi; " \ - "if test $board_name = A335BNLT; then " \ - "setenv fdtfile am335x-boneblack.dtb; fi; " \ - "if test $board_name = A335PBGL; then " \ - "setenv fdtfile am335x-pocketbeagle.dtb; fi; " \ - "if test $board_name = BBBW; then " \ - "setenv fdtfile am335x-boneblack-wireless.dtb; fi; " \ - "if test $board_name = BBG1; then " \ - "setenv fdtfile am335x-bonegreen.dtb; fi; " \ - "if test $board_name = BBGW; then " \ - "setenv fdtfile am335x-bonegreen-wireless.dtb; fi; " \ - "if test $board_name = BBBL; then " \ - "setenv fdtfile am335x-boneblue.dtb; fi; " \ - "if test $board_name = BBEN; then " \ - "setenv fdtfile am335x-sancloud-bbe.dtb; fi; " \ - "if test $board_name = A33515BB; then " \ - "setenv fdtfile am335x-evm.dtb; fi; " \ - "if test $board_name = A335X_SK; then " \ - "setenv fdtfile am335x-evmsk.dtb; fi; " \ - "if test $board_name = A335_ICE; then " \ - "setenv fdtfile am335x-icev2.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ - "init_console=" \ - "if test $board_name = A335_ICE; then "\ - "setenv console ttyO3,115200n8;" \ - "else " \ - "setenv console ttyO0,115200n8;" \ - "fi;\0" \ - NANDARGS \ - NETARGS \ - DFUARGS \ - BOOTENV -#endif - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* PMIC support */ -#define CONFIG_POWER_TPS65217 -#define CONFIG_POWER_TPS65910 - -/* SPL */ -#ifndef CONFIG_NOR_BOOT -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - -/* USB gadget RNDIS */ -#endif - -#ifdef CONFIG_NAND -/* NAND: device related configs */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -/* NAND: driver related configs */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 -/* NAND: SPL related configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif -#endif /* !CONFIG_NAND */ - -/* - * For NOR boot, we must set this to the start of where NOR is mapped - * in memory. - */ - -/* - * USB configuration. We enable MUSB support, both for host and for - * gadget. We set USB0 as peripheral and USB1 as host, based on the - * board schematic and physical port wired to each. Then for host we - * add mass storage support and for gadget we add both RNDIS ethernet - * and DFU. - */ -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -/* - * Disable MMC DM for SPL build and can be re-enabled after adding - * DM support in SPL - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_MMC -#undef CONFIG_TIMER -#endif - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) -/* Remove other SPL modes. */ -/* disable host part of MUSB in SPL */ -/* disable EFI partitions and partition UUID support */ -#endif - -/* USB Device Firmware Update support */ -#ifndef CONFIG_SPL_BUILD -#define DFUARGS \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_NAND -#endif - -/* - * Default to using SPI for environment, etc. - * 0x000000 - 0x020000 : SPL (128KiB) - * 0x020000 - 0x0A0000 : U-Boot (512KiB) - * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) - * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) - * 0x0E0000 - 0x442000 : Linux Kernel - * 0x442000 - 0x800000 : Userland - */ -#if defined(CONFIG_SPI_BOOT) -/* SPL related */ - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ -#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ -#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ -#elif defined(CONFIG_EMMC_BOOT) -#define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_ENV_OFFSET 0x260000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_SYS_MMC_MAX_DEVICE 2 -#elif defined(CONFIG_NOR_BOOT) -#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ -#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ -#elif defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_OFFSET 0x001c0000 -#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#endif - -/* SPI flash. */ - -/* Network. */ -#define CONFIG_PHY_SMSC -/* Enable Atheros phy driver */ -#define CONFIG_PHY_ATHEROS - -/* - * NOR Size = 16 MiB - * Number of Sectors/Blocks = 128 - * Sector Size = 128 KiB - * Word length = 16 bits - * Default layout: - * 0x000000 - 0x07FFFF : U-Boot (512 KiB) - * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB) - * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB) - * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB) - * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) - */ -#if defined(CONFIG_NOR) -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#endif /* NOR support */ - -#ifdef CONFIG_DRIVER_TI_CPSW -#define CONFIG_CLOCK_SYNTHESIZER -#define CLK_SYNTHESIZER_I2C_ADDR 0x65 -#endif - -#endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/am335x_guardian.h b/include/configs/am335x_guardian.h deleted file mode 100644 index b45b8d2..0000000 --- a/include/configs/am335x_guardian.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am335x_guardian_.h - * - * Copyright (C) 2018 Robert Bosch Power Tools GmbH - * Copyright (C) 2018 sjoerd Simons - * - */ - -#ifndef __CONFIG_AM335X_GUARDIAN_H -#define __CONFIG_AM335X_GUARDIAN_H - -#include - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_TIMESTAMP -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#ifndef CONFIG_SPL_BUILD - -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x80000000\0" \ - "pxefile_addr_r=0x80100000\0" \ - "kernel_addr_r=0x82000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "ramdisk_addr_r=0x88080000\0" \ - -#define BOOT_TARGET_DEVICES(func) \ - func(UBIFS, ubifs, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - AM335XX_BOARD_FDTFILE \ - MEM_LAYOUT_ENV_SETTINGS \ - BOOTENV \ - "bootlimit=3\0" \ - "bootubivol=rootfs\0" \ - "altbootcmd=" \ - "setenv boot_config \"extlinux-rollback.conf\"; " \ - "run distro_bootcmd\0" - -#endif /* ! CONFIG_SPL_BUILD */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* PMIC support */ -#define CONFIG_POWER_TPS65217 - -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_LE - -#ifdef CONFIG_NAND - -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 4096 -#define CONFIG_SYS_NAND_OOBSIZE 256 -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) - -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ - 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ - 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ - 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ - 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ - 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ - 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ - 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ - 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ - 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ - 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ - 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ - 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ - 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ - 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ - 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ - 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ - 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ - } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW -#define MTDIDS_DEFAULT "nand0=nand.0" - -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS - -#endif /* CONFIG_NAND */ - -#endif /* ! __CONFIG_AM335X_GUARDIAN_H */ diff --git a/include/configs/am335x_igep003x.h b/include/configs/am335x_igep003x.h deleted file mode 100644 index 5b5e160..0000000 --- a/include/configs/am335x_igep003x.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (C) 2013, ISEE 2007 SL - http://www.isee.biz/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_IGEP003X_H -#define __CONFIG_IGEP003X_H - -#include - -/* Clock defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "console=ttyO0,115200n8\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ - "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run mmcload; then " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr};" \ - "fi;" \ - "fi;\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=1\0" \ - "nandrootfstype=ubifs rootwait\0" \ - "nandload=ubi part UBI; " \ - "ubi read ${loadaddr} kernel; " \ - "ubi read ${fdtaddr} dtb \0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} \0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "run nandload; " \ - "bootz ${loadaddr} - ${fdtaddr} \0" \ - "netload=tftpboot ${loadaddr} ${bootfile}; " \ - "tftpboot ${fdtaddr} ${fdtfile} \0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "ip=${ipaddr} nfsroot=${serverip}:${rootnfs},v3,tcp \0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "run netload; " \ - "bootz ${loadaddr} - ${fdtaddr} \0" \ - "findfdt="\ - "if test ${board_name} = igep0033; then " \ - "setenv fdtfile am335x-igep-base0033.dtb; fi; " \ - "if test ${board_name} = igep0034; then " \ - "setenv fdtfile am335x-igep-base0040.dtb; fi; " \ - "if test ${board_name} = igep0034-lite; then " \ - "setenv fdtfile am335x-igep-base0040-lite.dtb; fi; " \ - "if test ${fdtfile} = ''; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" -#endif - -#define CONFIG_BOOTCOMMAND \ - "run findfdt;" \ - "run mmcboot;" \ - "run nandboot;" \ - "run netboot;" - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ - -/* Ethernet support */ -#define CONFIG_PHY_SMSC - -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION 1 - -/* NAND config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW - -#endif /* ! __CONFIG_IGEP003X_H */ diff --git a/include/configs/am335x_shc.h b/include/configs/am335x_shc.h deleted file mode 100644 index f4a000f..0000000 --- a/include/configs/am335x_shc.h +++ /dev/null @@ -1,261 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_AM335X_SHC_H -#define __CONFIG_AM335X_SHC_H - -#include - -/* settings we don;t want on this board */ -#undef CONFIG_CMD_SPI - -#define CONFIG_CMD_CACHE - -#ifndef CONFIG_SPL_BUILD -# define CONFIG_TIMESTAMP -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* - * in case of SD Card or Network boot we want to have a possibility to - * debrick the shc, therefore do not read environment from eMMC - */ -#if defined(CONFIG_SHC_SDBOOT) || defined(CONFIG_SHC_NETBOOT) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#else -#define CONFIG_SYS_MMC_ENV_DEV 1 -#endif - -/* - * Info when using boot partitions: As environment resides within first - * 128 kB, MLO must start at 128 kB == 0x20000 - * ENV at MMC Boot0 Partition - 0/Undefined=user, 1=boot0, 2=boot1, - * 4..7=general0..3 - */ -#define CONFIG_ENV_SIZE 0x1000 /* 4 KB */ -#define CONFIG_ENV_OFFSET 0x7000 /* 28 kB */ - -#define CONFIG_HSMMC2_8BIT - -#define CONFIG_ENV_OFFSET_REDUND 0x9000 /* 36 kB */ -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#ifndef CONFIG_SHC_ICT -/* - * In builds other than ICT, reset to retry after timeout - * Define a timeout after which a stopped bootloader continues autoboot - * (only works with CONFIG_RESET_TO_RETRY) - */ -# define CONFIG_BOOT_RETRY_TIME 30 -# define CONFIG_RESET_TO_RETRY -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "kloadaddr=0x84000000\0" \ - "fdtaddr=0x85000000\0" \ - "fdt_high=0xffffffff\0" \ - "rdaddr=0x81000000\0" \ - "bootfile=uImage\0" \ - "fdtfile=am335x-shc.dtb\0" \ - "verify=no\0" \ - "serverip=10.55.152.184\0" \ - "rootpath=/srv/nfs/shc-rootfs\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=quiet\0" \ - "mmcdev=1\0" \ - "harakiri=0\0" \ - "mmcpart=2\0" \ - "active_root=root1\0" \ - "inactive_root=root2\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nfsopts=nolock\0" \ - "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ - "::off\0" \ - "ip_method=none\0" \ - "bootargs_defaults=setenv bootargs " \ - "console=${console} " \ - "${optargs}\0" \ - "mmcargs=run bootargs_defaults;" \ - "setenv bootargs ${bootargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} ip=${ip_method}\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=if fatload mmc ${mmcdev} ${loadaddr} ${bootenv}; then " \ - "echo Loaded environment from ${bootenv}; " \ - "run importbootenv; " \ - "fi;\0" \ - "importbootenv=echo Importing environment variables from uEnv.txt ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${kloadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:${mmcpart} ${kloadaddr} /boot/${bootfile}\0" \ - "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdtaddr} /boot/${fdtfile}\0" \ - "netloaduimage=tftp ${loadaddr} ${bootfile}\0" \ - "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \ - "mmcboot=echo Booting Linux from ${mmcdevice} ...; " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "echo device tree detected; " \ - "bootm ${kloadaddr} - ${fdtaddr}; " \ - "else " \ - "bootm ${kloadaddr}; " \ - "fi; \0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "run netloaduimage; " \ - "run netargs; " \ - "echo NFS path: ${serverip}:${rootpath};" \ - "if run netloadfdt; then " \ - "echo device tree detected; " \ - "bootm ${loadaddr} - ${fdtaddr}; " \ - "else " \ - "bootm ${loadaddr}; " \ - "fi; \0" \ - "emmc_erase=if test ${harakiri} = 1 ; then echo erase emmc ...; setenv mmcdev 1; mmc erase 0 200; reset; fi; \0" \ - "mmcpart_gp=mmcpart gp 1 40; \0" \ - "mmcpart_enhance=mmcpart enhance 0 64; \0" \ - "mmcpart_rel_write=mmcpart rel_write 1f; \0" \ - "mmcpart_commit=mmcpart commit 1; \0" \ - "mmc_hw_part=run mmcpart_gp; run mmcpart_enhance; run mmcpart_rel_write; run mmcpart_commit; \0" \ - "led_success=gpio set 22; \0" \ - "fusecmd=mmc dev 1; if mmcpart iscommitted; then echo HW Partitioning already committed; mmcpart list; else run mmc_hw_part; fi; run led_success; \0" \ - "uenv_exec=if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi;\0" \ - "sd_setup=echo SD/MMC-Card detected on device 0; " \ - "setenv mmcdevice SD; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" \ - "emmc_setup=echo eMMC detected on device 1; " \ - "setenv mmcdevice eMMC; " \ - "setenv mmcdev 1; " \ - "run emmc_erase; " \ - "if test ${active_root} = root2; then " \ - "echo Active root is partition 6 (root2); " \ - "setenv mmcpart 6; " \ - "else " \ - "echo Active root is partition 5 (root1); " \ - "setenv mmcpart 5; " \ - "fi; " \ - "setenv mmcroot /dev/mmcblk${mmcdev}p${mmcpart};\0" -#endif /* #ifndef CONFIG_SPL_BUILD */ - -#if defined CONFIG_SHC_NETBOOT -/* Network Boot */ -# define CONFIG_BOOTCOMMAND \ - "run fusecmd; " \ - "if run netboot; then " \ - "echo Booting from network; " \ - "else " \ - "echo ERROR: Cannot boot from network!; " \ - "panic; " \ - "fi; " - -#elif defined CONFIG_SHC_SDBOOT /* !defined CONFIG_SHC_NETBOOT */ -/* SD-Card Boot */ -# define CONFIG_BOOTCOMMAND \ - "if mmc dev 0; mmc rescan; then " \ - "run sd_setup; " \ - "else " \ - "echo ERROR: SD/MMC-Card not detected!; " \ - "panic; " \ - "fi; " \ - "if run loaduimage; then " \ - "echo Bootable SD/MMC-Card inserted, booting from it!; " \ - "run mmcboot; " \ - "else " \ - "echo ERROR: Unable to load uImage from SD/MMC-Card!; " \ - "panic; " \ - "fi; " - -#elif defined CONFIG_SHC_ICT -/* ICT adapter boots only u-boot and does HW partitioning */ -# define CONFIG_BOOTCOMMAND \ - "if mmc dev 0; mmc rescan; then " \ - "run sd_setup; " \ - "else " \ - "echo ERROR: SD/MMC-Card not detected!; " \ - "panic; " \ - "fi; " \ - "run fusecmd; " - -#else /* !defined CONFIG_SHC_NETBOOT, !defined CONFIG_SHC_SDBOOT */ -/* Regular Boot from internal eMMC */ -# define CONFIG_BOOTCOMMAND \ - "if mmc dev 1; mmc rescan; then " \ - "run emmc_setup; " \ - "else " \ - "echo ERROR: eMMC device not detected!; " \ - "panic; " \ - "fi; " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else " \ - "echo ERROR Unable to load uImage from eMMC!; " \ - "echo Performing Rollback!; " \ - "setenv _active_ ${active_root}; " \ - "setenv _inactive_ ${inactive_root}; " \ - "setenv active_root ${_inactive_}; " \ - "setenv inactive_root ${_active_}; " \ - "saveenv; " \ - "reset; " \ - "fi; " - -#endif /* Regular Boot */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* PMIC support */ -#define CONFIG_POWER_TPS65217 - -/* SPL */ - -/* - * Disable MMC DM for SPL build and can be re-enabled after adding - * DM support in SPL - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_MMC -#undef CONFIG_TIMER -#endif - -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_PHY_SMSC - -/* I2C configuration */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 1 -#endif /* ! __CONFIG_AM335X_SHC_H */ diff --git a/include/configs/am335x_sl50.h b/include/configs/am335x_sl50.h deleted file mode 100644 index a08e6bf..0000000 --- a/include/configs/am335x_sl50.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am335x_sl50.h - * - * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ - */ - -#ifndef __CONFIG_AM335X_EVM_H -#define __CONFIG_AM335X_EVM_H - -#include - -#ifndef CONFIG_SPL_BUILD -# define CONFIG_TIMESTAMP -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/*#define CONFIG_MACH_TYPE 3589 Until the next sync */ - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#ifndef CONFIG_SPL_BUILD - -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x80000000\0" \ - "pxefile_addr_r=0x80100000\0" \ - "kernel_addr_r=0x82000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "ramdisk_addr_r=0x88080000\0" \ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) - -#define AM335XX_BOARD_FDTFILE \ - "fdtfile=am335x-sl50.dtb\0" \ - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - AM335XX_BOARD_FDTFILE \ - MEM_LAYOUT_ENV_SETTINGS \ - BOOTENV - -#endif - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* PMIC support */ -#define CONFIG_POWER_TPS65217 -#define CONFIG_POWER_TPS65910 - -/* SPL */ - -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) -/* Remove other SPL modes. */ -/* disable host part of MUSB in SPL */ -#undef CONFIG_MUSB_HOST -/* disable EFI partitions and partition UUID support */ -#endif - -#if defined(CONFIG_EMMC_BOOT) -#define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET 0x0 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#endif - -/* Network. */ -#define CONFIG_PHY_SMSC - -#endif /* ! __CONFIG_AM335X_SL50_H */ diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h deleted file mode 100644 index 5fa393d..0000000 --- a/include/configs/am3517_crane.h +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am3517_crane.h - Default configuration for AM3517 CraneBoard. - * - * Author: Srinath.R - * - * Based on include/configs/am3517evm.h - * - * Copyright (C) 2011 Mistral Solutions pvt Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#include /* get chip and board defs */ -#include - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - /* initial data */ -/* - * DDR related - */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * USB configuration - * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard - * Enable CONFIG_USB_MUSB_UDC for Device functionalities. - */ - -#ifdef CONFIG_USB_AM35X -#ifdef CONFIG_USB_MUSB_UDC -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" -#endif /* CONFIG_USB_MUSB_UDC */ - -#endif /* CONFIG_USB_AM35X */ - -#define CONFIG_SYS_I2C - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access */ - /* nand at CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ - -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ - -/* Environment information */ - -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ - "mmcdev=0\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "nandargs=setenv bootargs console=${console} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command */ - /* args */ -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ - /* address */ - -/* - * AM3517 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ - /* on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_FLASH_BASE NAND_BASE - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ -#define CONFIG_ENV_ADDR 0x260000 - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h deleted file mode 100644 index 3e5f0b1..0000000 --- a/include/configs/am3517_evm.h +++ /dev/null @@ -1,190 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am3517_evm.h - Default configuration for AM3517 EVM board. - * - * Author: Vaibhav Hiremath - * - * Based on omap3_evm_config.h - * - * Copyright (C) 2010 Texas Instruments Incorporated - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_REVISION_TAG - -/* Hardware drivers */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * USB configuration - * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard - * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_USB_EHCI_OMAP -#else -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 57 -#endif - -/* I2C */ - -/* Ethernet */ -#define CONFIG_DRIVER_TI_EMAC_USE_RMII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* Board NAND Info. */ -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \ - 11, 12, 13, 14, 16, 17, 18, 19, 20, \ - 21, 22, 23, 24, 25, 26, 27, 28, 30, \ - 31, 32, 33, 34, 35, 36, 37, 38, 39, \ - 40, 41, 42, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56 } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 -/* NAND block size is 128 KiB. Synchronize these values with - * corresponding Device Tree entries in Linux: - * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000 - * U-Boot 15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000 - * U-Boot environment 2 * NAND_BLOCK_SIZE = 256 KiB @ 0x260000 - * Kernel 64 * NAND_BLOCK_SIZE = 8 MiB @ 0x2A0000 - * DTB 4 * NAND_BLOCK_SIZE = 512 KiB @ 0xAA0000 - * RootFS Remaining Flash Space @ 0xB20000 - */ -#endif /* CONFIG_NAND */ - -/* Environment information */ - -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ - "fdtfile=am3517-evm.dtb\0" \ - "fdtaddr=0x82C00000\0" \ - "vram=16M\0" \ - "bootenv=uEnv.txt\0" \ - "cmdline=\0" \ - "optargs=\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait fixrtc\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} " \ - "${cmdline}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${optargs} " \ - "root=ubi0:rootfs rw ubi.mtd=rootfs " \ - "rootfstype=ubifs rootwait " \ - "${cmdline}\0" \ - "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 2a0000 800000; " \ - "nand read ${fdtaddr} aa0000 80000; " \ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device $mmcdev; " \ - "if run loadbootenv; then " \ - "run importbootenv; " \ - "fi; " \ - "echo Checking if uenvcmd is set ...; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "echo Running default loadimage ...; " \ - "setenv bootfile zImage; " \ - "if run loadimage; then " \ - "run loadfdt; " \ - "run mmcboot; " \ - "fi; " \ - "else run nandboot; fi" - -/* Miscellaneous configurable options */ - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ - + sizeof(CONFIG_SYS_PROMPT) + 16) -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -/* Physical Memory Map */ -#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) - -/* FLASH and environment organization */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ - /* on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_ADDR 0x260000 - -/* Defines for SPL */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC - -#endif /* __CONFIG_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h deleted file mode 100644 index d355b80..0000000 --- a/include/configs/am43xx_evm.h +++ /dev/null @@ -1,278 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * am43xx_evm.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_AM43XX_EVM_H -#define __CONFIG_AM43XX_EVM_H - -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 21) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ - -#include - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_SERIAL -#endif - -/* I2C Configuration */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* Power */ -#ifndef CONFIG_DM_I2C -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#endif -#define CONFIG_POWER_TPS65218 -#define CONFIG_POWER_TPS62362 - -/* SPL defines. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) - -/* Enabling L2 Cache */ -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE 0x48242000 - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_QSPI_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * When building U-Boot such that there is no previous loader - * we need to call board_early_init_f. This is taken care of in - * s_init when we have SPL used. - */ - -/* Now bring in the rest of the common code. */ -#include - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ - -/* SPL USB Support */ - -#if defined(CONFIG_SPL_USB_HOST_SUPPORT) || !defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_USB_FAT_BOOT_PARTITION 1 -#define CONFIG_USB_XHCI_OMAP - -#define CONFIG_AM437X_USB2PHY2_HOST -#endif - -#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_USB_ETHER) -#undef CONFIG_USB_DWC3_PHY_OMAP -#undef CONFIG_USB_DWC3_OMAP -#undef CONFIG_USB_DWC3 -#undef CONFIG_USB_DWC3_GADGET - -#undef CONFIG_USB_GADGET_DOWNLOAD -#undef CONFIG_USB_GADGET_VBUS_DRAW -#undef CONFIG_USB_GADGET_MANUFACTURER -#undef CONFIG_USB_GADGET_VENDOR_NUM -#undef CONFIG_USB_GADGET_PRODUCT_NUM -#undef CONFIG_USB_GADGET_DUALSPEED -#endif - -/* - * Disable MMC DM for SPL build and can be re-enabled after adding - * DM support in SPL - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_TIMER -#endif - -#ifndef CONFIG_SPL_BUILD -/* USB Device Firmware Update support */ -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_QSPI_XIP -#else -#define DFUARGS -#endif - -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND 0x120000 -#endif - -#ifndef CONFIG_SPL_BUILD -#include -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - DEFAULT_FIT_TI_ARGS \ - "fdtfile=undefined\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "console=ttyO0,115200n8\0" \ - "partitions=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ - "optargs=\0" \ - "usbroot=/dev/sda2 rw\0" \ - "usbrootfstype=ext4 rootwait\0" \ - "usbdev=0\0" \ - "ramroot=/dev/ram0 rw\0" \ - "ramrootfstype=ext2\0" \ - "usbargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${usbroot} " \ - "rootfstype=${usbrootfstype}\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=load ${devtype} ${devnum} ${rdaddr} ramdisk.gz\0" \ - "usbboot=" \ - "setenv devnum ${usbdev}; " \ - "setenv devtype usb; " \ - "usb start ${usbdev}; " \ - "if usb dev ${usbdev}; then " \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadimage; then " \ - "run loadfdt; " \ - "echo Booting from usb ${usbdev}...; " \ - "run usbargs;" \ - "bootz ${loadaddr} - ${fdtaddr}; " \ - "fi;" \ - "fi\0" \ - "fi;" \ - "usb stop ${usbdev};\0" \ - "findfdt="\ - "if test $board_name = AM43EPOS; then " \ - "setenv fdtfile am43x-epos-evm.dtb; fi; " \ - "if test $board_name = AM43__GP; then " \ - "setenv fdtfile am437x-gp-evm.dtb; fi; " \ - "if test $board_name = AM43XXHS; then " \ - "setenv fdtfile am437x-gp-evm.dtb; fi; " \ - "if test $board_name = AM43__SK; then " \ - "setenv fdtfile am437x-sk-evm.dtb; fi; " \ - "if test $board_name = AM43_IDK; then " \ - "setenv fdtfile am437x-idk-evm.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree; fi; \0" \ - NANDARGS \ - NETARGS \ - DFUARGS \ - -#define CONFIG_BOOTCOMMAND \ - "if test ${boot_fit} -eq 1; then " \ - "run update_to_fit;" \ - "fi;" \ - "run findfdt; " \ - "run envboot;" \ - "run mmcboot;" \ - "run usbboot;" \ - NANDBOOT \ - -#endif - -#ifndef CONFIG_SPL_BUILD -/* CPSW Ethernet */ -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ - -#define CONFIG_SYS_RX_ETH_BUFFER 64 - -/* NAND support */ -#ifdef CONFIG_NAND -/* NAND: device related configs */ -#define CONFIG_SYS_NAND_PAGE_SIZE 4096 -#define CONFIG_SYS_NAND_OOBSIZE 224 -#define CONFIG_SYS_NAND_BLOCK_SIZE (256*1024) -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -/* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ - 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ - 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ - 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ - 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ - 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ - 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ - 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ - 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ - 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ - 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ - 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ - 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ - 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ - 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ - 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ - 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ - 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ - } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000 -/* NAND: SPL related configs */ -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */ -#endif -#define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,4096\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${fdtaddr} NAND.u-boot-spl-os; " \ - "nand read ${loadaddr} NAND.kernel; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" -#define NANDBOOT "run nandboot; " -#else /* !CONFIG_NAND */ -#define NANDARGS -#define NANDBOOT -#endif /* CONFIG_NAND */ - -#if defined(CONFIG_TI_SECURE_DEVICE) -/* Avoid relocating onto firewalled area at end of DRAM */ -#define CONFIG_PRAM (64 * 1024) -#endif /* CONFIG_TI_SECURE_DEVICE */ - -#endif /* __CONFIG_AM43XX_EVM_H */ diff --git a/include/configs/am57xx_evm.h b/include/configs/am57xx_evm.h deleted file mode 100644 index 531f79e..0000000 --- a/include/configs/am57xx_evm.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Texas Instruments Incorporated. - * Felipe Balbi - * - * Configuration settings for the TI Beagle x15 board. - * See ti_omap5_common.h for omap5 common settings. - */ - -#ifndef __CONFIG_AM57XX_EVM_H -#define __CONFIG_AM57XX_EVM_H - -#include -#include - -#define CONFIG_IODELAY_RECALIBRATION - -/* MMC ENV related defines */ -#define CONFIG_SYS_MMC_ENV_DEV 1 /* eMMC */ -#define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -#define CONSOLEDEV "ttyS2" -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ - -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -#define CONFIG_SYS_OMAP_ABE_SYSCK - -#ifdef CONFIG_SPL_DFU -#ifndef CONFIG_SPL_BUILD -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_QSPI -#else -#undef CONFIG_CMD_BOOTD -#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_RAM -#endif -#endif - -#include - -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - -/* CPSW Ethernet */ -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs longer aneg time at 1G */ - -/* USB xHCI HOST */ -#define CONFIG_USB_XHCI_OMAP - -#define CONFIG_OMAP_USB3PHY1_HOST - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -/* - * Default to using SPI for environment, etc. - * 0x000000 - 0x040000 : QSPI.SPL (256KiB) - * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) - * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) - * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) - * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) - * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) - * 0x9E0000 - 0x2000000 : USERLAND - */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 - -/* SPI SPL */ - -#endif /* __CONFIG_AM57XX_EVM_H */ diff --git a/include/configs/am65x_evm.h b/include/configs/am65x_evm.h deleted file mode 100644 index 1149d55..0000000 --- a/include/configs/am65x_evm.h +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration header file for K3 AM654 EVM - * - * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/ - * Lokesh Vutla - */ - -#ifndef __CONFIG_AM654_EVM_H -#define __CONFIG_AM654_EVM_H - -#include -#include -#include -#include - -#define CONFIG_ENV_SIZE (128 << 10) - -/* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 - -/* SPL Loader Configuration */ -#ifdef CONFIG_TARGET_AM654_A53_EVM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ - CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) -#else -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x5000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#endif - -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" -#endif - -#ifndef CONFIG_CPU_V7R -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -#define PARTS_DEFAULT \ - /* Linux partitions */ \ - "name=rootfs,start=0,size=-,uuid=${uuid_gpt_rootfs}\0" - -/* U-Boot general configuration */ -#define EXTRA_ENV_AM65X_BOARD_SETTINGS \ - "findfdt=" \ - "setenv name_fdt k3-am654-base-board.dtb;" \ - "setenv fdtfile ${name_fdt}\0" \ - "loadaddr=0x80080000\0" \ - "fdtaddr=0x82000000\0" \ - "overlayaddr=0x83000000\0" \ - "name_kern=Image\0" \ - "console=ttyS2,115200n8\0" \ - "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \ - "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" \ - -/* U-Boot MMC-specific configuration */ -#define EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ - "boot=mmc\0" \ - "mmcdev=1\0" \ - "bootpart=1:2\0" \ - "bootdir=/boot\0" \ - "rd_spec=-\0" \ - "init_mmc=run args_all args_mmc\0" \ - "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0" \ - "get_overlay_mmc=" \ - "fdt address ${fdtaddr};" \ - "fdt resize 0x100000;" \ - "for overlay in $name_overlays;" \ - "do;" \ - "load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay};" \ - "fdt apply ${overlayaddr};" \ - "done;\0" \ - "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ - "${bootdir}/${name_kern}\0" \ - "get_fit_mmc=load mmc ${bootpart} ${addr_fit} " \ - "${bootdir}/${name_fit}\0" \ - "partitions=" PARTS_DEFAULT - -#ifdef DEFAULT_RPROCS -#undef DEFAULT_RPROCS -#endif -#define DEFAULT_RPROCS "" \ - "0 /lib/firmware/am65x-mcu-r5f0_0-fw " \ - "1 /lib/firmware/am65x-mcu-r5f0_1-fw " - -/* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_MMC_TI_ARGS \ - DEFAULT_FIT_TI_ARGS \ - EXTRA_ENV_AM65X_BOARD_SETTINGS \ - EXTRA_ENV_AM65X_BOARD_SETTINGS_MMC \ - EXTRA_ENV_RPROC_SETTINGS - -/* MMC ENV related defines */ -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_ENV_OFFSET 0x680000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#endif - -#define CONFIG_SUPPORT_EMMC_BOOT - -/* Now for the remaining common defines */ -#include - -#endif /* __CONFIG_AM654_EVM_H */ diff --git a/include/configs/amcore.h b/include/configs/amcore.h deleted file mode 100644 index 26d6fef..0000000 --- a/include/configs/amcore.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sysam AMCORE board configuration - * - * (C) Copyright 2016 Angelo Dureghello - */ - -#ifndef __AMCORE_CONFIG_H -#define __AMCORE_CONFIG_H - -#define CONFIG_HOSTNAME "AMCORE" - -#define CONFIG_MCFTMR -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT 0 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_BOOTCOMMAND "bootm ffc20000" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "upgrade_uboot=loady; " \ - "protect off 0xffc00000 0xffc1ffff; " \ - "erase 0xffc00000 0xffc1ffff; " \ - "cp.b 0x20000 0xffc00000 ${filesize}\0" \ - "upgrade_kernel=loady; " \ - "erase 0xffc20000 0xffefffff; " \ - "cp.b 0x20000 0xffc20000 ${filesize}\0" \ - "upgrade_jffs2=loady; " \ - "erase 0xfff00000 0xffffffff; " \ - "cp.b 0x20000 0xfff00000 ${filesize}\0" - -/* undef to save memory */ - -#define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ - -#define CONFIG_SYS_MEMTEST_START 0x0 -#define CONFIG_SYS_MEMTEST_END 0x1000000 - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_CLK 45000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) -/* Register Base Addrs */ -#define CONFIG_SYS_MBAR 0x10000000 -/* Definitions for initial stack pointer and data area (in DPRAM) */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -/* size of internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_FLASH_BASE 0xffc00000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -/* amcore design has flash data bytes wired swapped */ -#define CONFIG_SYS_WRITE_SWAPPED_DATA -/* reserve 128-4KB */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x1000 - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*); - -/* memory map space for linux boot data */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Cache Configuration - * - * Special 8K version 3 core cache. - * This is a single unified instruction/data cache. - * sdram - single region - no masks - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ - CF_ACR_EN) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ - CF_CACR_EC) - -/* CS0 - AMD Flash, address 0xffc00000 */ -#define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) -/* 4MB, AA=0,V=1 C/I BIT for errata */ -#define CONFIG_SYS_CS0_MASK 0x003f0001 -/* WS=10, AA=1, PS=16bit (10) */ -#define CONFIG_SYS_CS0_CTRL 0x1980 -/* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ -#define CONFIG_SYS_CS1_BASE 0x3000 -#define CONFIG_SYS_CS1_MASK 0x00070001 -#define CONFIG_SYS_CS1_CTRL 0x0100 - -#endif /* __AMCORE_CONFIG_H */ - diff --git a/include/configs/ap121.h b/include/configs/ap121.h deleted file mode 100644 index 0e8c3f7..0000000 --- a/include/configs/ap121.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2016 Wills Wang - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_MHZ 200 -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MALLOC_LEN 0x40000 -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 - -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {9600, 19200, 38400, 57600, 115200} - -#define CONFIG_BOOTCOMMAND "sf probe;" \ - "mtdparts default;" \ - "bootm 0x9f650000" - -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x10000 - -/* Miscellaneous configurable options */ - -/* - * Diagnostics - */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x83f00000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ap143.h b/include/configs/ap143.h deleted file mode 100644 index fa69210..0000000 --- a/include/configs/ap143.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2016 Wills Wang - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_MHZ 325 -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MALLOC_LEN 0x40000 -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 - -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {9600, 19200, 38400, 57600, 115200} - -#define CONFIG_BOOTCOMMAND "sf probe;" \ - "mtdparts default;" \ - "bootm 0x9f680000" - -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x10000 - -/* Miscellaneous configurable options */ - -/* - * Diagnostics - */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x83f00000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/ap152.h b/include/configs/ap152.h deleted file mode 100644 index c948a44..0000000 --- a/include/configs/ap152.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Rosy Song - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_MHZ 375 -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MALLOC_LEN 0x40000 -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 - -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {9600, 19200, 38400, 57600, 115200} - -#define CONFIG_BOOTCOMMAND "sf probe;" \ - "mtdparts default;" \ - "bootm 0x9f060000" - -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x10000 - -/* Miscellaneous configurable options */ - -/* - * Diagnostics - */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x83f00000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h deleted file mode 100644 index 3a8d2d4..0000000 --- a/include/configs/apalis-imx8.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Toradex - */ - -#ifndef __APALIS_IMX8_H -#define __APALIS_IMX8_H - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_DISPLAY_BOARDINFO_LATE - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5b010000 -#define USDHC2_BASE_ADDR 0x5b020000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -/* Networking */ -#define FEC_QUIRK_ENET_MAC - -#define CONFIG_TFTP_TSIZE - -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - -#define MEM_LAYOUT_ENV_SETTINGS \ - "fdt_addr_r=0x84000000\0" \ - "kernel_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x94400000\0" \ - "scriptaddr=0x87000000\0" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) -#include -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - MEM_LAYOUT_ENV_SETTINGS \ - "console=ttyLP1 earlycon\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_file=fsl-imx8qm-apalis-eval.dtb\0" \ - "fdtfile=fsl-imx8qm-apalis-eval.dtb\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "image=Image\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait " \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp" \ - "\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ - "apalis-imx8/${fdt_file}; booti ${loadaddr} - ${fdt_addr}\0" \ - "panel=NULL\0" \ - "script=boot.scr\0" \ - "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ - "if test \"$confirm\" = \"y\"; then " \ - "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ - "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ - "${blkcnt}; fi\0" - -/* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - -#define CONFIG_SYS_MEMTEST_START 0x88000000 -#define CONFIG_SYS_MEMTEST_END 0x89000000 - -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ -#define CONFIG_SYS_MMC_ENV_PART 1 - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 - -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_2 0x880000000 -#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ -#define PHYS_SDRAM_2_SIZE SZ_2G /* 2 GB */ - -/* Serial */ -#define CONFIG_BAUDRATE 115200 - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 8000000 /* 8MHz */ - -#endif /* __APALIS_IMX8_H */ diff --git a/include/configs/apalis-tk1.h b/include/configs/apalis-tk1.h deleted file mode 100644 index fe45917..0000000 --- a/include/configs/apalis-tk1.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Toradex, Inc. - * - * Configuration settings for the Toradex Apalis TK1 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" - -#define CONFIG_ARCH_MISC_INIT - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define FDT_MODULE "apalis-v1.2" -#define FDT_MODULE_V1_0 "apalis" - -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 - -/* PCI host support */ -#undef CONFIG_PCI_SCAN_SHOW - -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - -/* General networking support */ -#define CONFIG_TFTP_TSIZE - -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - -#define DFU_ALT_EMMC_INFO "apalis-tk1.img raw 0x0 0x500 mmcpart 1; " \ - "boot part 0 1 mmcpart 0; " \ - "rootfs part 0 2 mmcpart 0; " \ - "zImage fat 0 1 mmcpart 0; " \ - "tegra124-apalis-eval.dtb fat 0 1 mmcpart 0" - -#define EMMC_BOOTCMD \ - "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \ - "ro rootfstype=ext4 rootwait\0" \ - "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ - "setenv bootargs ${defargs} ${emmcargs} " \ - "${setupargs} ${vidargs}; echo Booting from internal eMMC; " \ - "run emmcdtbload; " \ - "load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} - ${dtbparam}\0" \ - "emmcbootpart=1\0" \ - "emmcdev=0\0" \ - "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \ - "${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb && " \ - "setenv dtbparam ${fdt_addr_r}\0" \ - "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \ - "emmcrootpart=2\0" - -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ - "nfsboot=pci enum; run setup; setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} - ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} " \ - "${soc}-${fdt_module}-${fdt_board}.dtb " \ - "&& setenv dtbparam ${fdt_addr_r}\0" - -#define SD_BOOTCMD \ - "set_sdargs=setenv sdargs ip=off root=PARTUUID=${uuid} ro " \ - "rootfstype=ext4 rootwait\0" \ - "sdboot=run setup; run sdfinduuid; run set_sdargs; " \ - "setenv bootargs ${defargs} ${sdargs} ${setupargs} " \ - "${vidargs}; echo Booting from SD card in 8bit slot...; " \ - "run sddtbload; load mmc ${sddev}:${sdbootpart} " \ - "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} - ${dtbparam}\0" \ - "sdbootpart=1\0" \ - "sddev=1\0" \ - "sddtbload=setenv dtbparam; load mmc ${sddev}:${sdbootpart} " \ - "${fdt_addr_r} ${soc}-${fdt_module}-${fdt_board}.dtb " \ - "&& setenv dtbparam ${fdt_addr_r}\0" \ - "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \ - "sdrootpart=2\0" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "boot_file=zImage\0" \ - "console=ttyS0\0" \ - "defargs=lp0_vec=2064@0xf46ff000 core_edp_mv=1150 core_edp_ma=4000 " \ - "usb_port_owner_info=2 lane_owner_info=6 emc_max_dvfs=0 " \ - "user_debug=30 pcie_aspm=off\0" \ - "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ - EMMC_BOOTCMD \ - "fdt_board=eval\0" \ - "fdt_fixup=;\0" \ - "fdt_module=" FDT_MODULE "\0" \ - NFS_BOOTCMD \ - SD_BOOTCMD \ - "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ - "00:14:2d:00:00:00; fi; pci enum && tftpboot ${loadaddr} " \ - "flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ - "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \ - "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1 " \ - "${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "setup=setenv setupargs igb_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8 debug_uartport=lsport,0 " \ - "${memargs}\0" \ - "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ - "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ - "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "vidargs=fbcon=map:1\0" - -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - -#define CONFIG_CMD_TIME - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -/* Reserve top 1M for secure RAM */ -#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 -#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h deleted file mode 100644 index a5f9a96..0000000 --- a/include/configs/apalis_imx6.h +++ /dev/null @@ -1,240 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2019 Toradex, Inc. - * - * Configuration settings for the Toradex Apalis iMX6 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#undef CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_MACH_TYPE 4886 - -#include -#include - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 3 - -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_LBA48 -#endif - -/* Network */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ -#define CONFIG_FEC_MXC_PHYADDR 6 -#define CONFIG_TFTP_TSIZE - -/* USB Configs */ -/* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -/* Client */ -#define CONFIG_USBD_HS - -/* Framebuffer and LCD */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_MUX -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FLASH - -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - -#define CONFIG_LOADADDR 0x12000000 - -#ifndef CONFIG_SPL_BUILD -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif /* CONFIG_SPL_BUILD */ - -#define DFU_ALT_EMMC_INFO \ - "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "zImage fat 0 1;" \ - "imx6q-apalis-eval.dtb fat 0 1;" \ - "imx6q-apalis-cam-eval.dtb fat 0 1" - -#define EMMC_BOOTCMD \ - "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} " \ - "ro,noatime rootfstype=ext4 rootwait\0" \ - "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ - "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ - "${vidargs}; echo Booting from internal eMMC chip...; " \ - "run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \ - "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "emmcbootpart=1\0" \ - "emmcdev=0\0" \ - "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \ - "${fdt_addr_r} ${fdt_file} && " \ - "setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \ - "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \ - "emmcrootpart=2\0" - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x20000000\0" \ - "fdt_addr_r=0x12100000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x11000000\0" \ - "pxefile_addr_r=0x17100000\0" \ - "ramdisk_addr_r=0x12200000\0" \ - "scriptaddr=0x17000000\0" - -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs ro\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ - "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ - "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" - -#ifndef CONFIG_TDX_APALIS_IMX6_V1_0 -#define FDT_FILE "imx6q-apalis-eval.dtb" -#define FDT_FILE_V1_0 "imx6q-apalis_v1_0-eval.dtb" -#else -#define FDT_FILE "imx6q-apalis_v1_0-eval.dtb" -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - "bootcmd=setenv fdtfile ${fdt_file}; run distro_bootcmd ; " \ - "usb start ; " \ - "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ - "boot_file=zImage\0" \ - "console=ttymxc0\0" \ - "defargs=enable_wait_mode=off vmalloc=400M\0" \ - "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ - EMMC_BOOTCMD \ - "fdt_file=" FDT_FILE "\0" \ - "fdt_fixup=;\0" \ - MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ - "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ - "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ - "flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; " \ - "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img " \ - "|| setenv drive 2; mmc rescan; load ${interface} ${drive}:1" \ - " ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "setup=setenv setupargs fec_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8\0 " \ - "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ - "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ - "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "vidargs=mxc_hdmi.only_cea=1 " \ - "video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24 " \ - "video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off " \ - "fbmem=32M\0 " - -/* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 48 - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_MMC) -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 -#endif - -#define CONFIG_CMD_TIME - -#endif /* __CONFIG_H */ diff --git a/include/configs/apalis_t30.h b/include/configs/apalis_t30.h deleted file mode 100644 index f6adfeb..0000000 --- a/include/configs/apalis_t30.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2014-2016 Marcel Ziswiler - * - * Configuration settings for the Toradex Apalis T30 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_APALIS_T30 - -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 - -/* PCI networking support */ -#define CONFIG_E1000_NO_NVM - -/* General networking support */ -#define CONFIG_TFTP_TSIZE - -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/apf27.h b/include/configs/apf27.h deleted file mode 100644 index 044ce44..0000000 --- a/include/configs/apf27.h +++ /dev/null @@ -1,274 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Configuration settings for the Armadeus Project motherboard APF27 - * - * Copyright (C) 2008-2013 Eric Jarrige - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ENV_VERSION 10 -#define CONFIG_BOARD_NAME apf27 - -/* - * SoC configurations - */ -#define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ -#define CONFIG_MACH_TYPE 1698 /* APF27 */ - -/* - * Enable the call to miscellaneous platform dependent initialization. - */ - -/* - * SPL - */ -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_SIZE 2048 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 - -#define CONFIG_HOSTNAME "apf27" -#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" - -/* - * Memory configurations - */ -#define CONFIG_NR_DRAM_POPULATED 1 - -#define ACFG_SDRAM_MBYTE_SYZE 64 - -#define PHYS_SDRAM_1 0xA0000000 -#define PHYS_SDRAM_2 0xB0000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) -#define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ -#define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ - + PHYS_SDRAM_1_SIZE - 0x0100000) - -/* - * FLASH organization - */ -#define ACFG_MONITOR_OFFSET 0x00000000 -#define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ -#define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ -#define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ -#define CONFIG_FIRMWARE_OFFSET 0x00200000 -#define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ -#define CONFIG_KERNEL_OFFSET 0x00300000 -#define CONFIG_ROOTFS_OFFSET 0x00800000 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ -#define CONFIG_INITRD_TAG /* send initrd params */ - -#define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" - -#define ACFG_CONSOLE_DEV ttySMX0 -#define CONFIG_BOOTCOMMAND "run ubifsboot" -#define CONFIG_SYS_AUTOLOAD "no" -/* - * Default load address for user programs and kernel - */ -#define CONFIG_LOADADDR 0xA0000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Extra Environments - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ - "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "partition=nand0,6\0" \ - "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ - "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ - "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ - "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ - "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ - "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ - "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ - "kernel_addr_r=A0000000\0" \ - "check_env=if test -n ${flash_env_version}; " \ - "then env default env_version; " \ - "else env set flash_env_version ${env_version}; env save; "\ - "fi; " \ - "if itest ${flash_env_version} < ${env_version}; then " \ - "echo \"*** Warning - Environment version" \ - " change suggests: run flash_reset_env; reset\"; "\ - "env default flash_reset_env; "\ - "fi; \0" \ - "check_flash=nand lock; nand unlock ${env_addr}; \0" \ - "flash_reset_env=env default -f -a; saveenv; run update_env;" \ - "echo Flash environment variables erased!\0" \ - "download_uboot=tftpboot ${loadaddr} ${board_name}" \ - "-u-boot-with-spl.bin\0" \ - "flash_uboot=nand unlock ${u-boot_addr} ;" \ - "nand erase.part u-boot;" \ - "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ - "then nand lock; nand unlock ${env_addr};" \ - "echo Flashing of uboot succeed;" \ - "else echo Flashing of uboot failed;" \ - "fi; \0" \ - "update_uboot=run download_uboot flash_uboot\0" \ - "download_env=tftpboot ${loadaddr} ${board_name}" \ - "-u-boot-env.txt\0" \ - "flash_env=env import -t ${loadaddr}; env save; \0" \ - "update_env=run download_env flash_env\0" \ - "update_all=run update_env update_uboot\0" \ - "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ - -/* - * Serial Driver - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * NOR - */ - -/* - * NAND - */ - -#define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 -#define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 -#define NAND_MAX_CHIPS 1 - -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_NAND_QUIET 1 - -/* - * Partitions & Filsystems - */ - -/* - * Ethernet (on SOC imx FEC) - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* - * FPGA - */ -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_CHECK_CTRLC -#define CONFIG_SYS_FPGA_CHECK_ERROR - -/* - * Fuses - IIM - */ -#ifdef CONFIG_CMD_IMX_FUSE -#define IIM_MAC_BANK 0 -#define IIM_MAC_ROW 5 -#define IIM0_SCC_KEY 11 -#define IIM1_SUID 1 -#endif - -/* - * I2C - */ - -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F -#define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES { } - -#ifdef CONFIG_CMD_EEPROM -# define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ -# define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ -#endif /* CONFIG_CMD_EEPROM */ -#endif /* CONFIG_CMD_I2C */ - -/* - * SD/MMC - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MXC_MCI_REGS_BASE 0x10014000 -#endif - -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1374 -#define CONFIG_SYS_RTC_BUS_NUM 0 -#endif /* CONFIG_CMD_DATE */ - -/* - * PLL - * - * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 - * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| - */ -#define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ - -#if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ -/* micron 64MB */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ -#define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 128) -/* micron 128MB */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#endif - -#if (ACFG_SDRAM_MBYTE_SYZE == 256) -/* micron 256MB */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ -#define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h deleted file mode 100644 index 09de1c0..0000000 --- a/include/configs/apx4devkit.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Bluegiga Technologies Oy - * - * Authors: - * Veli-Pekka Peltola - * Lauri Hintsala - * - * Based on m28evk.h: - * Copyright (C) 2011 Marek Vasut - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_APX4DEVKIT_H__ -#define __CONFIGS_APX4DEVKIT_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_APX4DEVKIT - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* Max 512 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_OVERWRITE - -/* Environment is in MMC */ -#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_RANGE (384 * 1024) -#define CONFIG_ENV_OFFSET 0x120000 -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) -#endif - -/* UBI and NAND partitioning */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 -#define IMX_FEC_BASE MXS_ENET0_BASE -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "run bootcmd_nand" -#define CONFIG_LOADADDR 0x41000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG - -/* Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "verify=no\0" \ - "bootcmd=run bootcmd_nand\0" \ - "kernelargs=console=tty0 console=ttyAMA0,115200 consoleblank=0\0" \ - "bootargs_nand=" \ - "setenv bootargs ${kernelargs} ubi.mtd=3,2048 " \ - "root=ubi0:rootfs rootfstype=ubifs ${mtdparts} rw\0" \ - "bootcmd_nand=" \ - "run bootargs_nand && ubi part root 2048 && " \ - "ubifsmount ubi:rootfs && ubifsload 41000000 boot/uImage && " \ - "bootm 41000000\0" \ - "bootargs_mmc=" \ - "setenv bootargs ${kernelargs} " \ - "root=/dev/mmcblk0p2 rootwait ${mtdparts} rw\0" \ - "bootcmd_mmc=" \ - "run bootargs_mmc && mmc rescan && " \ - "ext2load mmc 0:2 41000000 boot/uImage && bootm 41000000\0" \ -"" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_APX4DEVKIT_H__ */ diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h deleted file mode 100644 index e998d9b..0000000 --- a/include/configs/aristainetos-common.h +++ /dev/null @@ -1,201 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * (C) Copyright 2014 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q SabreSD board. - */ -#ifndef __ARISTAINETOS_COMMON_CONFIG_H -#define __ARISTAINETOS_COMMON_CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_MACH_TYPE 4501 -#define CONFIG_MMCROOT "/dev/mmcblk0p1" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) - -#define CONFIG_MXC_UART - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_SPI_FLASH_MTD -#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=u-boot.scr\0" \ - "fit_file=/boot/system.itb\0" \ - "loadaddr=0x12000000\0" \ - "fit_addr_r=0x14000000\0" \ - "uboot=/boot/u-boot.imx\0" \ - "uboot_sz=d0000\0" \ - "rescue_sys_addr=f0000\0" \ - "rescue_sys_length=f10000\0" \ - "panel=lb07wv8\0" \ - "splashpos=m,m\0" \ - "console=" CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ - "default ${board_type}\0" \ - "get_env=mw ${loadaddr} 0 0x20000;" \ - "mmc rescan;" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ - "env import -t ${loadaddr}\0" \ - "default_env=mw ${loadaddr} 0 0x20000;" \ - "env export -t ${loadaddr} serial# ethaddr eth1addr " \ - "board_type panel;" \ - "env default -a;" \ - "env import -t ${loadaddr}\0" \ - "loadbootscript=" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "mmcpart=1\0" \ - "mmcdev=0\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addmtd addmisc set_fit_default;" \ - "bootm ${fit_addr_r}\0" \ - "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${uboot}\0" \ - "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ - "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ - "setexpr uboot_maxsize ${uboot_sz} - 400;" \ - "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ - "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ - "sf write ${loadaddr} 400 ${filesize};" \ - "sf read ${cmp_buf} 400 ${uboot_sz};" \ - "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ - "ubiboot=echo Booting from ubi ...; " \ - "run ubiargs addmtd addmisc set_fit_default;" \ - "bootm ${fit_addr_r}\0" \ - "rescueargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/ram rw\0 " \ - "rescueboot=echo Booting rescue system from NOR ...; " \ - "run rescueargs addmtd addmisc set_fit_default;" \ - "bootm ${fit_addr_r}\0" \ - "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ - "${rescue_sys_length}; imi ${fit_addr_r}\0" \ - CONFIG_EXTRA_ENV_BOARD_SETTINGS - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run mmc_load_fit; then " \ - "run mmcboot; " \ - "else " \ - "if run ubifs_load_fit; then " \ - "run ubiboot; " \ - "else " \ - "if run rescue_load_fit; then " \ - "run rescueboot; " \ - "else " \ - "echo RESCUE SYSTEM BOOT " \ - "FAILURE;" \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "else " \ - "if run ubifs_load_fit; then " \ - "run ubiboot; " \ - "else " \ - "if run rescue_load_fit; then " \ - "run rescueboot; " \ - "else " \ - "echo RESCUE SYSTEM BOOT FAILURE;" \ - "fi; " \ - "fi; " \ - "fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (12 * 1024) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SECT_SIZE (0x010000) -#define CONFIG_ENV_OFFSET (0x0d0000) -#define CONFIG_ENV_OFFSET_REDUND (0x0e0000) - -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7f -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_RTC_M41T11 - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* UBI support */ - -/* Framebuffer */ -/* check this console not needed, after test remove it */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_VIDEO_SKIP - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - -#endif /* __ARISTAINETOS_COMMON_CONFIG_H */ diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h deleted file mode 100644 index 03e2a2b..0000000 --- a/include/configs/aristainetos.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * (C) Copyright 2014 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q SabreSD board. - */ -#ifndef __ARISTAINETOS_CONFIG_H -#define __ARISTAINETOS_CONFIG_H - -#define CONFIG_SYS_BOARD_VERSION 1 -#define CONFIG_HOSTNAME "aristainetos" -#define CONFIG_BOARDNAME "aristainetos" - -#define CONFIG_MXC_UART_BASE UART5_BASE -#define CONSOLE_DEV "ttymxc4" - -#define CONFIG_FEC_XCV_TYPE RMII - -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "board_type=aristainetos7@1\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi3.0\0" \ - "mtdparts=mtdparts=spi3.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(rescue-system);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \ - "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " - -#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) -#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31) -#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) - -#include "aristainetos-common.h" - -#endif /* __ARISTAINETOS_CONFIG_H */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h deleted file mode 100644 index 361e6ac..0000000 --- a/include/configs/aristainetos2.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6DL aristainetos2 board. - */ -#ifndef __ARISTAINETOS2_CONFIG_H -#define __ARISTAINETOS2_CONFIG_H - -#define CONFIG_SYS_BOARD_VERSION 2 -#define CONFIG_HOSTNAME "aristainetos2" -#define CONFIG_BOARDNAME "aristainetos2" - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" - -#define CONFIG_FEC_XCV_TYPE RGMII - -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "board_type=aristainetos2_7@1\0" \ - "nor_bootdelay=-2\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ - "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ - "-(rescue-system);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ - "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " - -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ - -#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) -#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) -#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) - -/* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 33246000 -#define CONFIG_LG4573 -#define CONFIG_LG4573_BUS 0 -#define CONFIG_LG4573_CS 0 - -#include "aristainetos-common.h" - -#endif /* __ARISTAINETOS2_CONFIG_H */ diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h deleted file mode 100644 index cdeb7a3..0000000 --- a/include/configs/aristainetos2b.h +++ /dev/null @@ -1,50 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6DL aristainetos2 board. - */ -#ifndef __ARISTAINETOS2B_CONFIG_H -#define __ARISTAINETOS2B_CONFIG_H - -#define CONFIG_SYS_BOARD_VERSION 3 -#define CONFIG_HOSTNAME "aristainetos2" -#define CONFIG_BOARDNAME "aristainetos2-revB" - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" - -#define CONFIG_FEC_XCV_TYPE RGMII - -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "board_type=aristainetos2_7@1\0" \ - "nor_bootdelay=-2\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(rescue-system);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ - "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " \ - -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ - -#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) -#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) -#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) - -/* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 33246000 -#define CONFIG_LG4573 -#define CONFIG_LG4573_BUS 0 -#define CONFIG_LG4573_CS 1 - -#include "aristainetos-common.h" - -#endif /* __ARISTAINETOS2B_CONFIG_H */ diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h deleted file mode 100644 index c3cccee..0000000 --- a/include/configs/armadillo-800eva.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the bonito board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __ARMADILLO_800EVA_H -#define __ARMADILLO_800EVA_H - -#define CONFIG_SH_GPIO_PFC - -#include - -#define BOARD_LATE_INIT - -#define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 4) - -/* STACK */ -#define CONFIG_SYS_INIT_SP_ADDR 0xE8083000 -#define STACK_AREA_SIZE 0xC000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define ARMADILLO_800EVA_SDRAM_BASE 0x40000000 -#define ARMADILLO_800EVA_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF1 -#define SCIF0_BASE 0xe6c40000 -#define SCIF1_BASE 0xe6c50000 -#define SCIF2_BASE 0xe6c60000 -#define SCIF4_BASE 0xe6c80000 -#define CONFIG_SCIF_A - -#define CONFIG_SYS_MEMTEST_START (ARMADILLO_800EVA_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 504 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (ARMADILLO_800EVA_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (ARMADILLO_800EVA_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - 64 * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* FLASH */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } - -#define CONFIG_SYS_FLASH_ERASE_TOUT 3000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 3000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 - -/* ENV setting */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x0 -#define CONFIG_SH_ETHER_BASE_ADDR 0xe9a00000 -#define CONFIG_SH_ETHER_SH7734_MII (0x01) -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CONFIG_PHY_SMSC -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 50000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#endif /* __ARMADILLO_800EVA_H */ diff --git a/include/configs/arndale.h b/include/configs/arndale.h deleted file mode 100644 index 8aa6e1d..0000000 --- a/include/configs/arndale.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG Arndale board. - */ - -#ifndef __CONFIG_ARNDALE_H -#define __CONFIG_ARNDALE_H - -#define EXYNOS_FDTFILE_SETTING \ - "fdtfile=exynos5250-arndale.dtb\0" - -#include "exynos5250-common.h" -#include - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* MMC SPL */ -#define CONFIG_EXYNOS_SPL - -/* Miscellaneous configurable options */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - -#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) - -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK - -#define CONFIG_S5P_PA_SYSRAM 0x02020000 -#define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM - -/* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */ -#define CONFIG_ARM_GIC_BASE_ADDRESS 0x10480000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h deleted file mode 100644 index 6815c5f..0000000 --- a/include/configs/aspeed-common.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012-2020 ASPEED Technology Inc. - * Ryan Chen - * - * Copyright 2016 IBM Corporation - * (C) Copyright 2016 Google, Inc - */ - -#ifndef __AST_COMMON_CONFIG_H -#define __AST_COMMON_CONFIG_H - -/* Misc CPU related */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#ifdef CONFIG_PRE_CON_BUF_SZ -#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000 + CONFIG_PRE_CON_BUF_SZ) -#define CONFIG_SYS_INIT_RAM_SIZE (36*1024 - CONFIG_PRE_CON_BUF_SZ) -#else -#define CONFIG_SYS_INIT_RAM_ADDR (0x1e720000) -#define CONFIG_SYS_INIT_RAM_SIZE (36*1024) -#endif - -#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \ - + CONFIG_SYS_INIT_RAM_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (SYS_INIT_RAM_END \ - - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (32 << 20) - -/* - * NS16550 Configuration - */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_BOOTCOMMAND "bootm 20080000 20300000" -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=yes\0" \ - "spi_dma=yes\0" \ - "" - -#endif /* __AST_COMMON_CONFIG_H */ diff --git a/include/configs/aspenite.h b/include/configs/aspenite.h deleted file mode 100644 index 79bf8f2..0000000 --- a/include/configs/aspenite.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * Contributor: Mahavir Jain - */ - -#ifndef __CONFIG_ASPENITE_H -#define __CONFIG_ASPENITE_H - -/* - * High Level Configuration Options - */ -#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_ARMADA100 1 /* SOC Family Name */ -#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * There is no internal RAM in ARMADA100, using DRAM - * TBD: dcache to be used for this - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) - -/* - * Commands configuration - */ -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_SIZE 0x20000 /* 64k */ - -#endif /* __CONFIG_ASPENITE_H */ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h deleted file mode 100644 index 2e7fbfb..0000000 --- a/include/configs/astro_mcf5373l.h +++ /dev/null @@ -1,297 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Sentec Cobra Board. - * - * (C) Copyright 2003 Josef Baumgartner - */ - -/* - * configuration for ASTRO "Urmel" board. - * Originating from Cobra5272 configuration, messed up by - * Wolfgang Wegner - * Please do not bother the original author with bug reports - * concerning this file. - */ - -#ifndef _CONFIG_ASTRO_MCF5373L_H -#define _CONFIG_ASTRO_MCF5373L_H - -#include - -/* - * set the card type to actually compile for; either of - * the possibilities listed below has to be used! - */ -#define CONFIG_ASTRO_V532 1 - -#if CONFIG_ASTRO_V532 -#define ASTRO_ID 0xF8 -#elif CONFIG_ASTRO_V512 -#define ASTRO_ID 0xFA -#elif CONFIG_ASTRO_TWIN7S2 -#define ASTRO_ID 0xF9 -#elif CONFIG_ASTRO_V912 -#define ASTRO_ID 0xFC -#elif CONFIG_ASTRO_COFDMDUOS2 -#define ASTRO_ID 0xFB -#else -#error No card type defined! -#endif - -/* Command line configuration */ -/* - * CONFIG_RAM defines if u-boot is loaded via BDM (or started from - * a different bootloader that has already performed RAM setup) or - * started directly from flash, which is the regular case for production - * boards. - */ -#ifdef CONFIG_RAM -#define CONFIG_MONITOR_IS_IN_RAM -#define ENABLE_JFFS 0 -#else -#define ENABLE_JFFS 1 -#endif - -#define CONFIG_MCFRTC -#undef RTC_DEBUG - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 80000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -/* - * Defines processor clock - important for correct timings concerning serial - * interface etc. - */ - -#define CONFIG_SYS_CLK 80000000 -#define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 3) -#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ - -#define CONFIG_SYS_CORE_SRAM_SIZE 0x8000 -#define CONFIG_SYS_CORE_SRAM 0x80000000 - -#define CONFIG_SYS_UNIFY_CACHE - -/* - * Define baudrate for UART1 (console output, tftp, ...) - * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected - * in u-boot command interface - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (2) -#define CONFIG_SYS_UART2_ALT3_GPIO - -/* - * Watchdog configuration; Watchdog is disabled for running from RAM - * and set to highest possible value else. Beware there is no check - * in the watchdog code to validate the timeout value set here! - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 3355 /* timeout in milliseconds */ -#endif - -/* - * Configuration for environment - * Environment is located in the last sector of the flash - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_OFFSET 0x1FF8000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#else -/* - * environment in RAM - This is used to use a single PC-based application - * to load an image, load U-Boot, load an environment and then start U-Boot - * to execute the commands from the environment. Feedback is done via setting - * and reading memory locations. - */ -#define CONFIG_ENV_ADDR 0x40060000 -#define CONFIG_ENV_SECT_SIZE 0x8000 -#endif - -/* here we put our FPGA configuration... */ - -/* Define user parameters that have to be customized most likely */ - -/* AUTOBOOT settings - booting images automatically by u-boot after power on */ - -/* - * The following settings will be contained in the environment block ; if you - * want to use a neutral environment all those settings can be manually set in - * u-boot: 'set' command - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loaderversion=11\0" \ - "card_id="__stringify(ASTRO_ID)"\0" \ - "alterafile=0\0" \ - "xilinxfile=0\0" \ - "xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\ - "fpga load 0 0x41000000 $filesize\0" \ - "alteraload=imxtract 0x6c0000 $alterafile 0x41000000&&"\ - "fpga load 1 0x41000000 $filesize\0" \ - "env_default=1\0" \ - "env_check=if test $env_default -eq 1;"\ - " then setenv env_default 0;saveenv;fi\0" - -/* - * "update" is a non-standard command that has to be supplied - * by external update.c; This is not included in mainline because - * it needs non-blocking CFI routines. - */ -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_BOOTCOMMAND "" /* no autoboot in this case */ -#else -#if CONFIG_ASTRO_V532 -#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ - "run xilinxload&&run alteraload&&bootm 0x80000;"\ - "update;reset" -#else -#define CONFIG_BOOTCOMMAND "protect off 0x80000 0x1ffffff;run env_check;"\ - "run xilinxload&&bootm 0x80000;update;reset" -#endif -#endif - -/* default RAM address for user programs */ -#define CONFIG_SYS_LOAD_ADDR 0x20000 - -#define CONFIG_FPGA_COUNT 1 -#define CONFIG_SYS_FPGA_PROG_FEEDBACK -#define CONFIG_SYS_FPGA_WAIT 1000 - -/* End of user parameters to be customized */ - -/* Defines memory range for test */ - -#define CONFIG_SYS_MEMTEST_START 0x40020000 -#define CONFIG_SYS_MEMTEST_END 0x41ffffff - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ - -/* Base register address */ - -#define CONFIG_SYS_MBAR 0xFC000000 /* Register Base Addrs */ - -/* System Conf. Reg. & System Protection Reg. */ - -#define CONFIG_SYS_SCR 0x0003; -#define CONFIG_SYS_SPR 0xffff; - -/* - * Definitions for initial stack pointer and data area (in internal SRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * for MCF5373, the allowable range is 0x40000000 to 0x7FF00000 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 - -/* - * Chipselect bank definitions - * - * CS0 - Flash 32MB (first 16MB) - * CS1 - Flash 32MB (second half) - * CS2 - FPGA - * CS3 - FPGA - * CS4 - unused - * CS5 - unused - */ -#define CONFIG_SYS_CS0_BASE 0 -#define CONFIG_SYS_CS0_MASK 0x00ff0001 -#define CONFIG_SYS_CS0_CTRL 0x00001fc0 - -#define CONFIG_SYS_CS1_BASE 0x01000000 -#define CONFIG_SYS_CS1_MASK 0x00ff0001 -#define CONFIG_SYS_CS1_CTRL 0x00001fc0 - -#define CONFIG_SYS_CS2_BASE 0x20000000 -#define CONFIG_SYS_CS2_MASK 0x00ff0001 -#define CONFIG_SYS_CS2_CTRL 0x0000fec0 - -#define CONFIG_SYS_CS3_BASE 0x21000000 -#define CONFIG_SYS_CS3_MASK 0x00ff0001 -#define CONFIG_SYS_CS3_CTRL 0x0000fec0 - -#define CONFIG_SYS_FLASH_BASE 0x00000000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#else -/* This is mainly used during relocation in start.S */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif -/* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) -/* Reserve 128 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 259 -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 - -#define CONFIG_SYS_FLASH_SIZE 0x2000000 -#define CONFIG_SYS_FLASH_CFI_NONBLOCK 1 - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text*) - -#if ENABLE_JFFS -/* JFFS Partition offset set */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 -#endif - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ - CF_CACR_DCM_P) - -#endif /* _CONFIG_ASTRO_MCF5373L_H */ diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h deleted file mode 100644 index 6131277..0000000 --- a/include/configs/at91-sama5_common.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common part of configuration settings for the AT91 SAMA5 board. - * - * Copyright (C) 2015 Atmel Corporation - * Josh Wu - */ - -#ifndef __AT91_SAMA5_COMMON_H -#define __AT91_SAMA5_COMMON_H - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* general purpose I/O */ -#ifndef CONFIG_DM_GPIO -#define CONFIG_AT91_GPIO -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#ifdef CONFIG_SD_BOOT - -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#define CONFIG_BOOTCOMMAND "if test ! -n ${dtb_name}; then " \ - "setenv dtb_name at91-${board_name}.dtb; " \ - "fi; " \ - "fatload mmc 0:1 0x21000000 ${dtb_name}; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" - -#else - -#ifdef CONFIG_NAND_BOOT -/* u-boot env in nand flash */ -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \ - "nand read 0x22000000 0x200000 0x600000;" \ - "bootz 0x22000000 - 0x21000000" -#elif CONFIG_SPI_BOOT -/* u-boot env in serial flash, by default is bus 0 and cs 0 */ -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x21000000 0x60000 0xc000; " \ - "sf read 0x22000000 0x6c000 0x394000; " \ - "bootz 0x22000000 - 0x21000000" -#elif CONFIG_QSPI_BOOT -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x21000000 0x180000 0x80000; " \ - "sf read 0x22000000 0x200000 0x600000; " \ - "bootz 0x22000000 - 0x21000000" -#endif - -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -#endif diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h deleted file mode 100644 index 8bfba35..0000000 --- a/include/configs/at91rm9200ek.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Andreas Bießmann - * - * based on previous work by - * - * Ulf Samuelsson - * Rick Bronson - * - * Configuration settings for the AT91RM9200EK board. - */ - -#ifndef __AT91RM9200EK_CONFIG_H__ -#define __AT91RM9200EK_CONFIG_H__ - -#include - -/* - * set some initial configurations depending on configure target - * - * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0 - * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel - * initialisation was done by some preloader - */ -#ifdef CONFIG_RAMBOOT -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz - * AT91C_MAIN_CLOCK is the frequency of PLLA output - * AT91C_MASTER_CLOCK is the peripherial clock - * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely - * set in arch/arm/cpu/arm920t/at91/timer.c) - * CONFIG_SYS_HZ is the tick rate for timer tc0 - */ -#define AT91C_XTAL_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39) -#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 ) -#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2) - -/* CPU configuration */ -#define CONFIG_AT91RM9200 -#define CONFIG_AT91RM9200EK -#define USE_920T_MMU - -#include /* needed for port definitions */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Memory Configuration - */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_32M - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K) - -/* - * LowLevel Init - */ -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_USE_MAIN_OSCILLATOR -/* flash */ -#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000 -#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */ - -/* clocks */ -#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */ -#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */ -/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */ -#define CONFIG_SYS_MCKR_VAL 0x00000202 - -/* sdram */ -#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */ -#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000 -#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000 -#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */ -#define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80) -#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */ -#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */ -#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */ -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */ -#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */ -#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */ -#endif /* CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - * Hardware drivers - */ -/* - * Choose a USART for serial console - * CONFIG_DBGU is DBGU unit on J10 - * CONFIG_USART1 is USART1 on J14 - */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0/* ignored in arm */ - -/* - * Command line configuration. - */ - -/* - * Network Driver Setting - */ -#define CONFIG_DRIVER_AT91EMAC -#define CONFIG_SYS_RX_ETH_BUFFER 16 -#define CONFIG_RMII - -/* - * NOR Flash - */ -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE -#define PHYS_FLASH_SIZE SZ_8M -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -/* - * USB Config - */ -#define CONFIG_USB_ATMEL 1 -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 - -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * Environment Settings - */ - -/* - * after u-boot.bin - */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) - -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN SZ_256K - -/* - * Boot option - */ - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M -#define CONFIG_ENV_OVERWRITE - -/* - * Shell Settings - */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \ - SZ_4K) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - - GENERATED_GBL_DATA_SIZE) - -#endif /* __AT91RM9200EK_CONFIG_H__ */ diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h deleted file mode 100644 index b283c9d..0000000 --- a/include/configs/at91sam9260ek.h +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires - * adapting the initial boot program. - * Since the linker has to swallow that define, we must use a pure - * hex number here! - */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ - -/* Define actual evaluation board type from used processor type */ -#ifdef CONFIG_AT91SAM9G20 -# define CONFIG_AT91SAM9G20EK /* It's an Atmel AT91SAM9G20 EK */ -#else -# define CONFIG_AT91SAM9260EK /* It's an Atmel AT91SAM9260 EK */ -#endif - -/* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 - -/* - * SDRAM: 1 bank, min 32, max 128 MB - * Initialized before u-boot gets started. - */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#ifdef CONFIG_AT91SAM9XE -# define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#else -# define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -/* - * The (arm)linux board id set by generic code depending on configured board - * (see boards.cfg for different boards) - */ -#ifdef CONFIG_AT91SAM9G20 - /* the sam9g20 variants have two different board ids */ -# ifdef CONFIG_AT91SAM9G20EK_2MMC - /* we may be setup for the 2MMC variant of at91sam9g20ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK_2MMC -# else - /* or the normal at91sam9g20ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9G20EK -# endif -#else - /* otherwise default to good old at91sam9260ek */ -# define CONFIG_MACH_TYPE MACH_TYPE_AT91SAM9260EK -#endif - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 -#endif - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 -#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ - "sf read 0x22000000 0x84000 0x294000; " \ - "bootm 0x22000000" - -#elif CONFIG_SYS_USE_DATAFLASH_CS1 - -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 -#define CONFIG_BOOTCOMMAND "sf probe 0:1; " \ - "sf read 0x22000000 0x84000 0x294000; " \ - "bootm 0x22000000" - -#elif defined(CONFIG_SYS_USE_NANDFLASH) - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET 0x140000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" - -#else /* CONFIG_SYS_USE_MMC */ -/* bootstrap + u-boot + env + linux in mmc */ -/* For FAT system, most cases it should be in the reserved sector */ -#define CONFIG_ENV_OFFSET 0x2000 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_BOOTCOMMAND \ - "fatload mmc 0:1 0x22000000 uImage; bootm" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#endif diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h deleted file mode 100644 index 599e262..0000000 --- a/include/configs/at91sam9261ek.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Configuation settings for the AT91SAM9261EK board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ - -#ifdef CONFIG_AT91SAM9G10 -#define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/ -#else -#define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/ -#endif - -#include - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_ATMEL_LEGACY - -/* - * Hardware drivers - */ - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD -#ifdef CONFIG_AT91SAM9261EK -#define CONFIG_ATMEL_LCD_BGR555 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 -/* our ALE is AD22 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) -/* our CLE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 - -#endif - -/* Ethernet */ -#define CONFIG_DRIVER_DM9000 -#define CONFIG_DM9000_BASE 0x30000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_DM9000_USE_16BIT -#define CONFIG_DM9000_NO_SROM -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ -#ifdef CONFIG_AT91SAM9G10EK -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" -#else -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" -#endif -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x22000000 0x84000 0x294000; " \ - "bootm 0x22000000" - -#elif CONFIG_SYS_USE_DATAFLASH_CS3 - -/* bootstrap + u-boot + env + linux in dataflash on CS3 */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 -#define CONFIG_BOOTCOMMAND "sf probe 0:3; " \ - "sf read 0x22000000 0x84000 0x294000; " \ - "bootm 0x22000000" - -#else /* CONFIG_SYS_USE_NANDFLASH */ - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET 0x140000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#endif diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h deleted file mode 100644 index 3e7adf6..0000000 --- a/include/configs/at91sam9263ek.h +++ /dev/null @@ -1,241 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Configuation settings for the AT91SAM9263EK board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#ifndef CONFIG_SYS_USE_BOOT_NORFLASH -#define CONFIG_SKIP_LOWLEVEL_INIT -#else -#define CONFIG_SYS_USE_NORFLASH -#endif - -/* - * Hardware drivers - */ -#define CONFIG_ATMEL_LEGACY - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_BGR555 1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NOR flash, if populated */ -#ifdef CONFIG_SYS_USE_NORFLASH -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_MONITOR_SEC 1:0-3 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_SIZE 0x10000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=" \ - "protect off ${monitor_base} +${filesize};" \ - "erase ${monitor_base} +${filesize};" \ - "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ - "protect on ${monitor_base} +${filesize}\0" - -#ifndef CONFIG_SKIP_LOWLEVEL_INIT -#define MASTER_PLL_MUL 171 -#define MASTER_PLL_DIV 14 -#define MASTER_PLL_OUT 3 - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLAR_29 | \ - AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ - AT91_PMC_PLLXR_PLLCOUNT(63) | \ - AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ - AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ - AT91_MATRIX_CSA_EBI_CS1A) - -/* SDRAM */ -/* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (1 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (2 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (1 << 28)) /* Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ - AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ - AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_MR_URSTEN | \ - AT91_RSTC_MR_ERSTL(15)) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ - AT91_WDT_MR_WDV(0xfff) | \ - AT91_WDT_MR_WDDIS | \ - AT91_WDT_MR_WDD(0xfff)) - -#endif -#endif - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 -#endif - -/* Ethernet */ -#define CONFIG_RESET_PHY_R 1 -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#ifdef CONFIG_SYS_USE_DATAFLASH - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x22000000 0x84000 0x294000; " \ - "bootm 0x22000000" - -#elif CONFIG_SYS_USE_NANDFLASH - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET 0x140000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#endif diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h deleted file mode 100644 index 044c428..0000000 --- a/include/configs/at91sam9m10g45ek.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES). - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_AT91SAM9M10G45EK - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD -#define CONFIG_ATMEL_LCD_RGB565 -/* board specific(not enough SRAM) */ -#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 - -#endif - -/* Ethernet */ -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#ifdef CONFIG_NAND_BOOT -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_ENV_OFFSET 0x140000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 - -#define CONFIG_BOOTCOMMAND \ - "nand read 0x70000000 0x200000 0x300000;" \ - "bootm 0x70000000" -#elif CONFIG_SD_BOOT -/* bootstrap + u-boot + env + linux in mmc */ -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ - "fatload mmc 0:1 0x72000000 zImage; " \ - "bootz 0x72000000 - 0x71000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 - -#define CONFIG_SYS_MONITOR_LEN 0x80000 - -#ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_BSS_START_ADDR 0x70000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_SOFTECC -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } -#endif - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#endif diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h deleted file mode 100644 index bc79e17..0000000 --- a/include/configs/at91sam9n12ek.h +++ /dev/null @@ -1,166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Atmel Corporation. - * Josh Wu - * - * Configuation settings for the AT91SAM9N12-EK boards. - */ - -#ifndef __AT91SAM9N12_CONFIG_H_ -#define __AT91SAM9N12_CONFIG_H_ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ - -/* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* LCD */ -#define LCD_BPP LCD_COLOR16 -#define LCD_OUTPUT_BPP 24 -#define CONFIG_LCD_LOGO -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_HLCD -#define CONFIG_ATMEL_LCD_RGB565 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 - -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -# define CONFIG_SYS_INIT_SP_ADDR \ - (0x00300000 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* DataFlash */ - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ - "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ - "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" - -/* Ethernet */ -#define CONFIG_KS8851_MLL -#define CONFIG_KS8851_MLL_BASEADDR 0x30000000 /* use NCS2 */ - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x26e00000 - -/* USB host */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - -#ifdef CONFIG_SPI_BOOT - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x5000 -#define CONFIG_ENV_SIZE 0x3000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \ - "sf probe 0; sf read 0x22000000 0x100000 0x300000; " \ - "bootm 0x22000000" - -#elif defined(CONFIG_NAND_BOOT) - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET 0x140000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_nand};" \ - "nand read 0x21000000 0x180000 0x080000;" \ - "nand read 0x22000000 0x200000 0x400000;" \ - "bootm 0x22000000 - 0x21000000" - -#else /* CONFIG_SD_BOOT */ - -/* bootstrap + u-boot + env + linux in mmc */ - -#ifdef CONFIG_ENV_IS_IN_MMC -/* Use raw reserved sectors to save environment */ -#define CONFIG_ENV_OFFSET 0x2000 -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#else -/* Use file in FAT file to save environment */ -#define CONFIG_ENV_SIZE 0x4000 -#endif - -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_mmc};" \ - "fatload mmc 0:1 0x21000000 dtb;" \ - "fatload mmc 0:1 0x22000000 uImage;" \ - "bootm 0x22000000 - 0x21000000" - -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20953f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#endif -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h deleted file mode 100644 index 1c67be5..0000000 --- a/include/configs/at91sam9rlek.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Configuation settings for the AT91SAM9RLEK board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */ - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#define CONFIG_ATMEL_LEGACY - -/* - * Hardware drivers - */ - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_RGB565 1 -/* Let board_init_f handle the framebuffer allocation */ -#undef CONFIG_FB_ADDR - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17 - -#endif - -/* Ethernet - not present */ - -/* USB - not supported */ - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#ifdef CONFIG_SYS_USE_DATAFLASH - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x22000000 0x84000 0x294000; " \ - "bootm 0x22000000" - -#elif CONFIG_SYS_USE_NANDFLASH - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET 0x140000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x600000; " \ - "nand read 0x21000000 0x180000 0x80000; " \ - "bootz 0x22000000 - 0x21000000" - -#else /* CONFIG_SYS_USE_MMC */ - -/* bootstrap + u-boot + env + linux in mmc */ -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91sam9rlek.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#endif diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h deleted file mode 100644 index f9a100b..0000000 --- a/include/configs/at91sam9x5ek.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Atmel Corporation - * - * Configuation settings for the AT91SAM9X5EK board. - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) - * NB: in this case, USB 1.1 devices won't be recognized. - */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* DataFlash */ - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#ifndef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#endif -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x26e00000 - -#ifdef CONFIG_NAND_BOOT -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_BOOTCOMMAND "nand read " \ - "0x22000000 0x200000 0x600000; " \ - "nand read 0x21000000 0x180000 0x20000; " \ - "bootz 0x22000000 - 0x21000000" -#elif defined(CONFIG_SPI_BOOT) -/* bootstrap + u-boot + env + linux in spi flash */ -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x22000000 0x100000 0x300000; " \ - "bootm 0x22000000" -#elif defined(CONFIG_SYS_USE_DATAFLASH) -/* bootstrap + u-boot + env + linux in data flash */ -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x22000000 0x84000 0x294000; " \ - "bootm 0x22000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#endif -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/ax25-ae350.h b/include/configs/ax25-ae350.h deleted file mode 100644 index a4037f3..0000000 --- a/include/configs/ax25-ae350.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Andes Technology Corporation - * Rick Chen, Andes Technology Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * CPU and Board Configuration Options - */ -#define CONFIG_BOOTP_SEND_HOSTNAME - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* - * Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * max number of command args - */ -#define CONFIG_SYS_MAXARGS 16 - -/* - * Boot Argument Buffer Size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Size of malloc() pool - * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough - */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - -/* DT blob (fdt) address */ -#define CONFIG_SYS_FDT_BASE 0x800f0000 - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1 \ - (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ -#define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 - -/* - * Serial console configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif -#define CONFIG_SYS_NS16550_CLK 19660800 - -/* Init Stack Pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000000 - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Load address and memory test area should agree with - * arch/riscv/config.mk. Be careful not to overwrite U-Boot itself. - */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* SDRAM */ - -/* - * memtest works on 512 MB in DRAM - */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) - -/* - * FLASH and environment organization - */ - -/* use CFI framework */ - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL - -/* support JEDEC */ -#ifdef CONFIG_CFI_FLASH -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#endif/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ -#define PHYS_FLASH_1 0x88000000 /* BANK 0 */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } -#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ - -/* max number of memory banks */ -/* - * There are 4 banks supported for this Controller, - * but we have only 1 bank connected to flash on board -*/ -#ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#endif -#define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} - -/* max number of sectors on one chip */ -#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* environments */ -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OVERWRITE - -/* SPI FLASH */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - -/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) -/* Increase max gunzip size */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -/* When we use RAM as ENV */ -#define CONFIG_ENV_SIZE 0x2000 - -/* Enable distro boot */ -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00080000\0" \ - "pxefile_addr_r=0x01f00000\0" \ - "scriptaddr=0x01f00000\0" \ - "fdt_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x02800000\0" \ - BOOTENV - -#endif /* __CONFIG_H */ diff --git a/include/configs/axs10x.h b/include/configs/axs10x.h deleted file mode 100644 index 0c5a3af..0000000 --- a/include/configs/axs10x.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. - */ - -#ifndef _CONFIG_AXS10X_H_ -#define _CONFIG_AXS10X_H_ - -#include -/* - * CPU configuration - */ -#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000 -#define ARC_APB_PERIPHERAL_BASE 0xF0000000 -#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000) -#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000) - -/* - * Memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_512M - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN SZ_2M -#define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -/* - * UART configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 33333333 -#define CONFIG_SYS_NS16550_MEM32 - -/* - * Ethernet PHY configuration - */ - -/* - * USB 1.1 configuration - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -/* - * Environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "upgrade=if mmc rescan && " \ - "fatload mmc 0:1 ${loadaddr} u-boot-update.img && " \ - "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ - "\"Fail to upgrade.\n" \ - "Do you have u-boot-update.img and u-boot.head on first (FAT) SD card partition?\"" \ - "; fi\0" - -/* - * Environment configuration - */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -/* - * Console configuration - */ - -#endif /* _CONFIG_AXS10X_H_ */ diff --git a/include/configs/baltos.h b/include/configs/baltos.h deleted file mode 100644 index a9b14c5..0000000 --- a/include/configs/baltos.h +++ /dev/null @@ -1,258 +0,0 @@ -/* - * am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_BALTOS_H -#define __CONFIG_BALTOS_H - -#include -#include - -#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* FIT support */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -#ifdef CONFIG_NAND - -#define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "${mtdparts} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=5\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "setenv loadaddr 0x84000000; " \ - "ubi part UBI; " \ - "ubifsmount ubi0:kernel; " \ - "ubifsload $loadaddr kernel-fit.itb;" \ - "ubifsumount; " \ - "bootm ${loadaddr}#conf${board_name}; " \ - "if test $? -ne 0; then echo Using default FIT config; " \ - "bootm ${loadaddr}; fi;\0" -#else -#define NANDARGS "" -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "boot_fdt=try\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "fdtfile=undefined\0" \ - "console=ttyO0,115200n8\0" \ - "partitions=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "usbroot=/dev/sda2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "usbrootfstype=ext4 rootwait\0" \ - "rootpath=/export/rootfs\0" \ - "nfsopts=nolock\0" \ - "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ - "::off\0" \ - "ramroot=/dev/ram0 rw\0" \ - "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "${mtdparts} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "usbargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "${mtdparts} " \ - "root=${usbroot} " \ - "rootfstype=${usbrootfstype}\0" \ - "spiroot=/dev/mtdblock4 rw\0" \ - "spirootfstype=jffs2\0" \ - "spisrcaddr=0xe0000\0" \ - "spiimgsize=0x362000\0" \ - "spibusno=0\0" \ - "spiargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${spiroot} " \ - "rootfstype=${spirootfstype}\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "usbloadbootenv=load usb 0:1 ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "usbimportbootenv=echo Importing environment from USB ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "usbloadimage=load usb 0:1 ${loadaddr} kernel-fit.itb\0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "usbloados=run usbargs; " \ - "bootm ${loadaddr}#conf${board_name}; " \ - "if test $? -ne 0; then " \ - "echo Using default FIT configuration; " \ - "bootm ${loadaddr}; " \ - "fi;\0" \ - "mmcloados=run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdtaddr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "usbboot=usb reset; " \ - "if usb storage; then " \ - "echo USB drive found;" \ - "if run usbloadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run usbimportbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run usbloadimage; then " \ - "run usbloados;" \ - "fi;" \ - "fi;\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadimage; then " \ - "run mmcloados;" \ - "fi;" \ - "fi;\0" \ - "spiboot=echo Booting from spi ...; " \ - "run spiargs; " \ - "sf probe ${spibusno}:0; " \ - "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ - "bootz ${loadaddr}\0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "tftp ${loadaddr} ${bootfile}; " \ - "tftp ${fdtaddr} ${fdtfile}; " \ - "run netargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ - "findfdt=setenv fdtfile am335x-baltos.dtb\0" \ - NANDARGS - /*DFUARGS*/ -#endif - -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "run usbboot;" \ - "run mmcboot;" \ - "setenv mmcdev 1; " \ - "setenv bootpart 1:2; " \ - "run mmcboot;" \ - "run nandboot;" - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* PMIC support */ -#define CONFIG_POWER_TPS65910 - -/* SPL */ -#ifndef CONFIG_NOR_BOOT - -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#endif -#endif - -/* - * USB configuration. We enable MUSB support, both for host and for - * gadget. We set USB0 as peripheral and USB1 as host, based on the - * board schematic and physical port wired to each. Then for host we - * add mass storage support and for gadget we add both RNDIS ethernet - * and DFU. - */ -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_HOST -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_OTG - -/* NAND support */ -#ifdef CONFIG_NAND -#define GPMC_NAND_ECC_LP_x8_LAYOUT 1 -#endif - -#endif /* ! __CONFIG_BALTOS_H */ diff --git a/include/configs/bav335x.h b/include/configs/bav335x.h deleted file mode 100644 index db21a47..0000000 --- a/include/configs/bav335x.h +++ /dev/null @@ -1,491 +0,0 @@ -/* - * bav335x.h - * - * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_BAV335X_H -#define __CONFIG_BAV335X_H - -#include - -#ifndef CONFIG_SPL_BUILD -# define CONFIG_TIMESTAMP -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -#define CONFIG_MACH_TYPE MACH_TYPE_AM335XEVM - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#ifdef CONFIG_NAND -#define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=9,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${fdtaddr} u-boot-spl-os; " \ - "nand read ${loadaddr} kernel; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" -#else -#define NANDARGS "" -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ -DEFAULT_LINUX_BOOT_ENV \ -"boot_fdt=try\0" \ -"bootpart=0:2\0" \ -"bootdir=\0" \ -"fdtdir=/dtbs\0" \ -"bootfile=zImage\0" \ -"fdtfile=undefined\0" \ -"console=ttyO0,115200n8\0" \ -"loadaddr=0x82000000\0" \ -"fdtaddr=0x88000000\0" \ -"rdaddr=0x88080000\0" \ -"initrd_high=0xffffffff\0" \ -"fdt_high=0xffffffff\0" \ -"partitions=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ -"optargs=\0" \ -"cmdline=\0" \ -"mmcdev=0\0" \ -"mmcpart=1\0" \ -"mmcroot=/dev/mmcblk0p2 ro\0" \ -"mmcrootfstype=ext4 rootwait fixrtc\0" \ -"rootpath=/export/rootfs\0" \ -"nfsopts=nolock\0" \ -"static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off\0" \ -"ramroot=/dev/ram0 rw\0" \ -"ramrootfstype=ext2\0" \ -"mmcargs=setenv bootargs console=${console} ${optargs} " \ - "root=${mmcroot} rootfstype=${mmcrootfstype} ${cmdline}\0" \ -"server_ip=192.168.1.100\0" \ -"gw_ip=192.168.1.1\0" \ -"netmask=255.255.255.0\0" \ -"hostname=\0" \ -"device=eth0\0" \ -"autoconf=off\0" \ -"root_dir=/home/userid/targetNFS\0" \ -"nfs_options=,vers=3\0" \ -"nfsrootfstype=ext4 rootwait fixrtc\0" \ -"nfsargs=setenv bootargs console=${console} ${optargs} " \ - "root=/dev/nfs rw rootfstype=${nfsrootfstype} " \ - "nfsroot=${nfsroot} ip=${ip} ${cmdline}\0" \ -"netargs=setenv bootargs console=${console} " \ - "${optargs} root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw ip=dhcp\0" \ -"bootenv=uEnv.txt\0" \ -"script=boot.scr\0" \ -"scriptfile=${script}\0" \ -"loadbootscript=load mmc ${bootpart} ${loadaddr} ${scriptfile};\0" \ -"bootscript=echo Running bootscript from mmc${bootpart} ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \ -"importbootenv=echo Importing environment from mmc ...; " \ - "env import -t -r $loadaddr $filesize\0" \ -"ramargs=setenv bootargs console=${console} " \ - "${optargs} root=${ramroot} rootfstype=${ramrootfstype}\0" \ -"loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ -"loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadrd=load mmc ${bootpart} ${rdaddr} " \ - "${bootdir}/${rdfile}; setenv rdsize ${filesize}\0" \ -"loadfdt=echo loading ${fdtdir}/${fdtfile} ...; " \ - "load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \ -"mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "gpio set 54;" \ - "setenv bootpart ${mmcdev}:1; " \ - "if test -e mmc ${bootpart} /etc/fstab; then " \ - "setenv mmcpart 1;" \ - "fi; " \ - "echo Checking for: /uEnv.txt ...;" \ - "if test -e mmc ${bootpart} /uEnv.txt; then " \ - "if run loadbootenv; then " \ - "gpio set 55;" \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "echo Checking if uenvcmd is set ...;" \ - "if test -n ${uenvcmd}; then " \ - "gpio set 56; " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "echo Checking if client_ip is set ...;" \ - "if test -n ${client_ip}; then " \ - "if test -n ${dtb}; then " \ - "setenv fdtfile ${dtb};" \ - "echo using ${fdtfile} ...;" \ - "fi;" \ - "gpio set 56; " \ - "if test -n ${uname_r}; then " \ - "echo Running nfsboot_uname_r ...;" \ - "run nfsboot_uname_r;" \ - "fi;" \ - "echo Running nfsboot ...;" \ - "run nfsboot;" \ - "fi;" \ - "fi; " \ - "echo Checking for: /${script} ...;" \ - "if test -e mmc ${bootpart} /${script}; then " \ - "gpio set 55;" \ - "setenv scriptfile ${script};" \ - "run loadbootscript;" \ - "echo Loaded script from ${scriptfile};" \ - "gpio set 56; " \ - "run bootscript;" \ - "fi; " \ - "echo Checking for: /boot/${script} ...;" \ - "if test -e mmc ${bootpart} /boot/${script}; then " \ - "gpio set 55;" \ - "setenv scriptfile /boot/${script};" \ - "run loadbootscript;" \ - "echo Loaded script from ${scriptfile};" \ - "gpio set 56; " \ - "run bootscript;" \ - "fi; " \ - "echo Checking for: /boot/uEnv.txt ...;" \ - "for i in 1 2 3 4 5 6 7 ; do " \ - "setenv mmcpart ${i};" \ - "setenv bootpart ${mmcdev}:${mmcpart};" \ - "if test -e mmc ${bootpart} /boot/uEnv.txt; then " \ - "gpio set 55;" \ - "load mmc ${bootpart} ${loadaddr} " \ - "/boot/uEnv.txt;" \ - "env import -t ${loadaddr} ${filesize};" \ - "echo Loaded environment from /boot/uEnv.txt;" \ - "if test -n ${dtb}; then " \ - "setenv fdtfile ${dtb};" \ - "echo Using: dtb=${fdtfile} ...;" \ - "fi;" \ - "echo Checking if uname_r is set in " \ - "/boot/uEnv.txt...;" \ - "if test -n ${uname_r}; then " \ - "gpio set 56; " \ - "echo Running uname_boot ...;" \ - "setenv mmcroot /dev/mmcblk${mmcdev}" \ - "p${mmcpart} ro;" \ - "run uname_boot;" \ - "fi;" \ - "fi;" \ - "done;" \ - "fi;\0" \ -"netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "tftp ${loadaddr} ${bootfile}; " \ - "tftp ${fdtaddr} ${fdtfile}; " \ - "run netargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ -"nfsboot=echo Booting from ${server_ip} ...; " \ - "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \ - "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \ - ":${device}:${autoconf}; " \ - "setenv autoload no; " \ - "setenv serverip ${server_ip}; " \ - "setenv ipaddr ${client_ip}; " \ - "tftp ${loadaddr} ${bootfile}; " \ - "tftp ${fdtaddr} dtbs/${fdtfile}; " \ - "run nfsargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ -"nfsboot_uname_r=echo Booting from ${server_ip} ...; " \ - "setenv nfsroot ${server_ip}:${root_dir}${nfs_options}; " \ - "setenv ip ${client_ip}:${server_ip}:${gw_ip}:${netmask}:${hostname}" \ - ":${device}:${autoconf}; " \ - "setenv autoload no; " \ - "setenv serverip ${server_ip}; " \ - "setenv ipaddr ${client_ip}; " \ - "tftp ${loadaddr} vmlinuz-${uname_r}; " \ - "tftp ${fdtaddr} dtbs/${uname_r}/${fdtfile}; " \ - "run nfsargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ -"ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ -"findfdt="\ - "if test $board_rev = B; then " \ - "setenv fdtfile birdland_bav335b.dtb; " \ - "setenv fdtbase am335x-boneblack; fi; " \ - "if test $board_rev = A; then " \ - "setenv fdtfile birdland_bav335a.dtb; " \ - "setenv fdtbase am335x-boneblack; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ -"uname_boot="\ - "setenv bootdir /boot; " \ - "setenv bootfile vmlinuz-${uname_r}; " \ - "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \ - "echo loading ${bootdir}/${bootfile} ...; "\ - "run loadimage;" \ - "setenv fdtdir /boot/dtbs/${uname_r}; " \ - "if test -e mmc ${bootpart} ${fdtdir}/${fdtfile}; then " \ - "run loadfdt;" \ - "else " \ - "setenv fdtdir /lib/firmware/${uname_r}/device-tree; " \ - "if test -e mmc ${bootpart} ${fdtdir}/" \ - "${fdtfile}; then " \ - "run loadfdt;" \ - "else " \ - "setenv fdtdir /boot/dtb-${uname_r}; " \ - "if test -e mmc ${bootpart} ${fdtdir}" \ - "/${fdtfile}; then " \ - "run loadfdt;" \ - "else " \ - "setenv fdtdir /boot/dtbs; " \ - "if test -e mmc ${bootpart} ${fdtdir}" \ - "/${fdtfile}; then " \ - "run loadfdt;" \ - "else " \ - "echo; echo unable to find " \ - "[${fdtfile}] " \ - "did you name it correctly?" \ - "echo booting fallback " \ - "[/boot/dtbs/" \ - "${uname_r}" \ - "/${fdtbase}.dtb]...;" \ - "setenv fdtdir /boot/dtbs/" \ - "${uname_r}; " \ - "setenv fdtfile " \ - "${fdtbase}.dtb; " \ - "run loadfdt;" \ - "fi;" \ - "fi;" \ - "fi;" \ - "fi;" \ - "fi; " \ - "setenv rdfile initrd.img-${uname_r}; " \ - "if test -e mmc ${bootpart} ${bootdir}/${rdfile}; then " \ - "echo loading ${bootdir}/${rdfile} ...; "\ - "run loadrd;" \ - "if test -n ${uuid}; then " \ - "setenv mmcroot UUID=${uuid} ro;" \ - "fi;" \ - "run mmcargs;" \ - "echo debug: [${bootargs}] ... ;" \ - "echo debug: [bootz ${loadaddr} ${rdaddr}:${rdsize} " \ - "${fdtaddr}] ... ;" \ - "bootz ${loadaddr} ${rdaddr}:${rdsize} ${fdtaddr}; " \ - "else " \ - "run mmcargs;" \ - "echo debug: [${bootargs}] ... ;" \ - "echo debug: [bootz ${loadaddr} - ${fdtaddr}] ... ;" \ - "bootz ${loadaddr} - ${fdtaddr}; " \ - "fi;" \ -"fi;\0" \ - NANDARGS \ - DFUARGS -#endif - -#define CONFIG_BOOTCOMMAND \ - "gpio set 53; " \ - "i2c mw 0x24 1 0x3e; " \ - "run findfdt; " \ - "setenv mmcdev 0; " \ - "setenv bootpart 0:1; " \ - "run mmcboot;" \ - "gpio clear 56; " \ - "gpio clear 55; " \ - "gpio clear 54; " \ - "setenv mmcdev 1; " \ - "setenv bootpart 1:1; " \ - "run mmcboot;" - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* PMIC support */ -#define CONFIG_POWER_TPS65217 -#define CONFIG_POWER_TPS65910 - -/* SPL */ -#ifndef CONFIG_NOR_BOOT -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - -/* USB gadget RNDIS */ -#endif - -#ifdef CONFIG_NAND -/* NAND: device related configs */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -/* NAND: driver related configs */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { \ - 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 -#define CONFIG_ENV_OFFSET 0x001c0000 -#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -/* NAND: SPL related configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif -#endif /* !CONFIG_NAND */ - -/* - * For NOR boot, we must set this to the start of where NOR is mapped - * in memory. - */ - -/* - * USB configuration. We enable MUSB support, both for host and for - * gadget. We set USB0 as peripheral and USB1 as host, based on the - * board schematic and physical port wired to each. Then for host we - * add mass storage support and for gadget we add both RNDIS ethernet - * and DFU. - */ -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USB_ETHER) -/* disable host part of MUSB in SPL */ -/* disable EFI partitions and partition UUID support */ -#endif - -/* USB Device Firmware Update support */ -#ifndef CONFIG_SPL_BUILD -#define DFU_ALT_INFO_MMC \ - "dfu_alt_info_mmc=" \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "MLO fat 0 1;" \ - "MLO.raw raw 0x100 0x100;" \ - "u-boot.img.raw raw 0x300 0x400;" \ - "spl-os-args.raw raw 0x80 0x80;" \ - "spl-os-image.raw raw 0x900 0x2000;" \ - "spl-os-args fat 0 1;" \ - "spl-os-image fat 0 1;" \ - "u-boot.img fat 0 1;" \ - "uEnv.txt fat 0 1\0" -#ifdef CONFIG_NAND -#define DFU_ALT_INFO_NAND \ - "dfu_alt_info_nand=" \ - "SPL part 0 1;" \ - "SPL.backup1 part 0 2;" \ - "SPL.backup2 part 0 3;" \ - "SPL.backup3 part 0 4;" \ - "u-boot part 0 5;" \ - "u-boot-spl-os part 0 6;" \ - "kernel part 0 8;" \ - "rootfs part 0 9\0" -#else -#define DFU_ALT_INFO_NAND "" -#endif -#define DFU_ALT_INFO_RAM \ - "dfu_alt_info_ram=" \ - "kernel ram 0x80200000 0xD80000;" \ - "fdt ram 0x80F80000 0x80000;" \ - "ramdisk ram 0x81000000 0x4000000\0" -#define DFUARGS \ - "dfu_alt_info_emmc=rawemmc raw 0 3751936\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_NAND -#endif - -/* - * Default to using SPI for environment, etc. - * 0x000000 - 0x020000 : SPL (128KiB) - * 0x020000 - 0x0A0000 : U-Boot (512KiB) - * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) - * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) - * 0x0E0000 - 0x442000 : Linux Kernel - * 0x442000 - 0x800000 : Userland - */ -#if defined(CONFIG_SPI_BOOT) -/* SPL related */ - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ -#define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ -#define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ -#elif defined(CONFIG_EMMC_BOOT) -#define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET 0x0 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#endif - -/* SPI flash. */ - -/* Network. */ -#define CONFIG_PHY_SMSC - -/* - * NOR Size = 16 MiB - * Number of Sectors/Blocks = 128 - * Sector Size = 128 KiB - * Word length = 16 bits - * Default layout: - * 0x000000 - 0x07FFFF : U-Boot (512 KiB) - * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB) - * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB) - * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB) - * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) - */ -#if defined(CONFIG_NOR) -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_SIZE 0x01000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -/* Reduce SPL size by removing unlikey targets */ -#ifdef CONFIG_NOR_BOOT -#define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ -#define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ -#endif -#endif /* NOR support */ - -#endif /* ! __CONFIG_AM335X_EVM_H */ diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h deleted file mode 100644 index 288bb8e..0000000 --- a/include/configs/bayleybay.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -/* Environment configuration */ -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x006ff000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/bcm23550_w1d.h b/include/configs/bcm23550_w1d.h deleted file mode 100644 index f59cd75..0000000 --- a/include/configs/bcm23550_w1d.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __BCM23550_W1D_H -#define __BCM23550_W1D_H - -#include -#include - -/* CPU, chip, mach, etc */ -#define CONFIG_KONA -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_KONA_RESET_S - -/* - * Memory configuration - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ - -/* GPIO Driver */ -#define CONFIG_KONA_GPIO - -/* MMC/SD Driver */ -#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR -#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO0 "sdio1" -#define CONFIG_SYS_SDIO1 "sdio2" -#define CONFIG_SYS_SDIO2 "sdio3" -#define CONFIG_SYS_SDIO3 "sdio4" - -/* I2C Driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_KONA -#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ -#define CONFIG_SYS_MAX_I2C_BUS 4 -#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR -#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR -#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR -#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR - -/* Timer Driver */ -#define CONFIG_SYS_TIMER_RATE 32000 -#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ - -/* Init functions */ - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* No mtest functions as recommended */ - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 13000000 -#define CONFIG_SYS_NS16550_COM1 0x3e000000 - -/* must fit into GPT:u-boot-env partition */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET (0x00011a00 * 512) -#define CONFIG_ENV_SIZE (8 * 512) - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * One partition type must be defined for part.c - * This is necessary for the fatls command to work on an SD card - * for example. - */ - -/* version string, parser, etc */ - -/* Initial upstream - boot to cmd prompt only */ -#define CONFIG_BOOTCOMMAND "" - -#define CONFIG_USBID_ADDR 0x34052c46 - -#define CONFIG_SYS_L2CACHE_OFF - -#endif /* __BCM23550_W1D_H */ diff --git a/include/configs/bcm28155_ap.h b/include/configs/bcm28155_ap.h deleted file mode 100644 index 111858f..0000000 --- a/include/configs/bcm28155_ap.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __BCM28155_AP_H -#define __BCM28155_AP_H - -#include -#include - -/* CPU, chip, mach, etc */ -#define CONFIG_KONA -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory configuration - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 - -#define CONFIG_SYS_MALLOC_LEN SZ_4M /* see armv7/start.S. */ - -/* GPIO Driver */ -#define CONFIG_KONA_GPIO - -/* MMC/SD Driver */ -#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR -#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR -#define CONFIG_SYS_SDIO0_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO1_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO2_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO3_MAX_CLK 48000000 -#define CONFIG_SYS_SDIO0 "sdio1" -#define CONFIG_SYS_SDIO1 "sdio2" -#define CONFIG_SYS_SDIO2 "sdio3" -#define CONFIG_SYS_SDIO3 "sdio4" - -/* I2C Driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_KONA -#define CONFIG_SYS_SPD_BUS_NUM 3 /* Start with PMU bus */ -#define CONFIG_SYS_MAX_I2C_BUS 4 -#define CONFIG_SYS_I2C_BASE0 BSC1_BASE_ADDR -#define CONFIG_SYS_I2C_BASE1 BSC2_BASE_ADDR -#define CONFIG_SYS_I2C_BASE2 BSC3_BASE_ADDR -#define CONFIG_SYS_I2C_BASE3 PMU_BSC_BASE_ADDR - -/* Timer Driver */ -#define CONFIG_SYS_TIMER_RATE 32000 -#define CONFIG_SYS_TIMER_COUNTER (TIMER_BASE_ADDR + 4) /* STCLO offset */ - -/* Init functions */ - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* No mtest functions as recommended */ - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL -/* Post pad 3 bytes after each reg addr */ -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 13000000 -#define CONFIG_SYS_NS16550_COM1 0x3e000000 - -/* must fit into GPT:u-boot-env partition */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET (0x00011a00 * 512) -#define CONFIG_ENV_SIZE (8 * 512) - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * One partition type must be defined for part.c - * This is necessary for the fatls command to work on an SD card - * for example. - */ - -/* version string, parser, etc */ - -/* Initial upstream - boot to cmd prompt only */ -#define CONFIG_BOOTCOMMAND "" - -#define CONFIG_USBID_ADDR 0x34052c46 - -#endif /* __BCM28155_AP_H */ diff --git a/include/configs/bcm7260.h b/include/configs/bcm7260.h deleted file mode 100644 index 967bde5..0000000 --- a/include/configs/bcm7260.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2018 Cisco Systems, Inc. - * - * Author: Thomas Fitzsimmons - * - * Configuration settings for the Broadcom BCM7260 SoC family. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_NS16550_COM1 0xf040c000 - -#define CONFIG_SYS_TEXT_BASE 0x10100000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x10200000 - -#define CONFIG_SYS_MALLOC_LEN ((40 * 1024) << 10) /* 40 MiB */ - -#include "bcmstb.h" - -#define BCMSTB_TIMER_LOW 0xf0412008 -#define BCMSTB_TIMER_HIGH 0xf041200c -#define BCMSTB_TIMER_FREQUENCY 0xf0412020 -#define BCMSTB_HIF_MSPI_BASE 0xf0203c00 -#define BCMSTB_BSPI_BASE 0xf0203a00 -#define BCMSTB_HIF_SPI_INTR2 0xf0201a00 -#define BCMSTB_CS_REG 0xf0200920 - -/* - * Environment configuration for eMMC. - */ -#define CONFIG_ENV_OFFSET (0x000040a4 * 512) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 - -#define CONFIG_CMD_GPT - -#endif /* __CONFIG_H */ diff --git a/include/configs/bcm7445.h b/include/configs/bcm7445.h deleted file mode 100644 index 3ff4677..0000000 --- a/include/configs/bcm7445.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2018 Cisco Systems, Inc. - * - * Author: Thomas Fitzsimmons - * - * Configuration settings for the Broadcom BCM7445 SoC family. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_NS16550_COM1 0xf040ab00 - -#define CONFIG_SYS_TEXT_BASE 0x80100000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x80200000 - -#define CONFIG_SYS_MALLOC_LEN ((10 * 1024) << 10) /* 10 MiB */ - -#include "bcmstb.h" - -#define BCMSTB_TIMER_LOW 0xf0412008 -#define BCMSTB_TIMER_HIGH 0xf041200c -#define BCMSTB_TIMER_FREQUENCY 0xf0412020 -#define BCMSTB_HIF_MSPI_BASE 0xf03e3400 -#define BCMSTB_BSPI_BASE 0xf03e3200 -#define BCMSTB_HIF_SPI_INTR2 0xf03e1a00 -#define BCMSTB_CS_REG 0xf03e0920 - -/* - * Environment configuration for SPI flash. - */ -#define CONFIG_ENV_OFFSET 0x1e0000 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/bcm_ep_board.h b/include/configs/bcm_ep_board.h deleted file mode 100644 index b67100a..0000000 --- a/include/configs/bcm_ep_board.h +++ /dev/null @@ -1,56 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef __BCM_EP_BOARD_H -#define __BCM_EP_BOARD_H - -#include - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory configuration - * (these must be defined elsewhere) - */ -#ifndef CONFIG_SYS_TEXT_BASE -#error CONFIG_SYS_TEXT_BASE must be defined! -#endif -#ifndef CONFIG_SYS_SDRAM_BASE -#error CONFIG_SYS_SDRAM_BASE must be defined! -#endif -#ifndef CONFIG_SYS_SDRAM_SIZE -#error CONFIG_SYS_SDRAM_SIZE must be defined! -#endif - -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Serial Info */ -#define CONFIG_SYS_NS16550_SERIAL - -#define CONFIG_ENV_SIZE 0x2000 - -/* console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* version string, parser, etc */ - -/* Enable Time Command */ - -#endif /* __BCM_EP_BOARD_H */ diff --git a/include/configs/bcm_northstar2.h b/include/configs/bcm_northstar2.h deleted file mode 100644 index 754bf2e..0000000 --- a/include/configs/bcm_northstar2.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Broadcom NS2. - */ - -#ifndef __BCM_NORTHSTAR2_H -#define __BCM_NORTHSTAR2_H - -#include - -#define CONFIG_HOSTNAME "northstar2" - -/* Physical Memory Map */ -#define V2M_BASE 0x80000000 -#define PHYS_SDRAM_1 V2M_BASE - -#define PHYS_SDRAM_1_SIZE (4UL * SZ_1G) -#define PHYS_SDRAM_2_SIZE (4UL * SZ_1G) -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* define text_base for U-boot image */ -#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x7ff00) -#define CONFIG_SYS_LOAD_ADDR 0x90000000 -#define CONFIG_SYS_MALLOC_LEN SZ_16M - -/* Serial Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 25000000 -#define CONFIG_SYS_NS16550_COM1 0x66100000 -#define CONFIG_SYS_NS16550_COM2 0x66110000 -#define CONFIG_SYS_NS16550_COM3 0x66120000 -#define CONFIG_SYS_NS16550_COM4 0x66130000 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_ENV_SIZE SZ_8K - -/* console configuration */ -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* version string, parser, etc */ - -#endif /* __BCM_NORTHSTAR2_H */ diff --git a/include/configs/bcmstb.h b/include/configs/bcmstb.h deleted file mode 100644 index b843705..0000000 --- a/include/configs/bcmstb.h +++ /dev/null @@ -1,174 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2018 Cisco Systems, Inc. - * - * Author: Thomas Fitzsimmons - * - * Configuration settings for the Broadcom BCMSTB SoC family. - */ - -#ifndef __BCMSTB_H -#define __BCMSTB_H - -#include "version.h" -#include - -#ifndef __ASSEMBLY__ - -#include - -struct bcmstb_boot_parameters { - u32 r0; - u32 r1; - u32 r2; - u32 r3; - u32 sp; - u32 lr; -}; - -extern struct bcmstb_boot_parameters bcmstb_boot_parameters; - -extern phys_addr_t prior_stage_fdt_address; - -#endif /* __ASSEMBLY__ */ - -/* - * CPU configuration. - */ -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory configuration. - * - * The prior stage BOLT bootloader sets up memory for us. - * - * An example boot memory layout after loading everything is: - * - * 0x0000 8000 vmlinux.bin.gz - * : [~31 MiB uncompressed max] - * 0x01ef f000 FIT containing signed public key - * : [~2 KiB in size] - * 0x01f0 0000 DTB copied from prior-stage-provided region - * : [~1 MiB max] - * 0x0200 0000 FIT containing ramdisk and device tree - * : initramfs.cpio.gz - * : [~208 MiB uncompressed max, to CMA/bmem low address] - * : [~80 MiB compressed max, to PSB low address] - * : device tree binary - * : [~60 KiB] - * 0x0700 0000 Prior stage bootloader (PSB) - * : - * 0x0761 7000 Prior-stage-provided device tree binary (DTB) - * : [~40 KiB in size] - * 0x0f00 0000 Contiguous memory allocator (CMA/bmem) low address - * : - * 0x8010 0000 U-Boot code at ELF load address - * : [~500 KiB in size, stripped] - * 0xc000 0000 Top of RAM - * - * Setting gd->relocaddr to CONFIG_SYS_TEXT_BASE in dram_init_banksize - * prevents U-Boot from relocating itself when it is run as an ELF - * program by the prior stage bootloader. - * - * We want to keep the ramdisk and FDT in the FIT image in-place, to - * accommodate stblinux's bmem and CMA regions. To accomplish this, - * we set initrd_high and fdt_high to 0xffffffff, and the load and - * entry addresses of the FIT ramdisk entry to 0x0. - * - * Overwriting the prior stage bootloader causes memory instability, - * so the compressed initramfs needs to fit between the load address - * and the PSB low address. In BOLT's default configuration this - * limits the compressed size of the initramfs to approximately 80 - * MiB. However, BOLT can be configured to allow loading larger - * initramfs images, in which case this limitation is eliminated. - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x2000000 - -/* - * CONFIG_SYS_LOAD_ADDR - 1 MiB. - */ -#define CONFIG_SYS_FDT_SAVE_ADDRESS 0x1f00000 -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 - -/* - * Large kernel image bootm configuration. - */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* - * NS16550 configuration. - */ -#define V_NS16550_CLK 81000000 - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * Serial console configuration. - */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} - -/* - * Informational display configuration. - */ -#define CONFIG_REVISION_TAG - -/* - * Command configuration. - */ -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_CACHE -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_MMC - -/* - * Flash configuration. - */ -#define CONFIG_ST_SMI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_MACRONIX - -/* - * Filesystem configuration. - */ -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT4 -#define CONFIG_FS_EXT4 -#define CONFIG_CMD_FS_GENERIC - -/* - * Environment configuration. - */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SIZE (64 << 10) /* 64 KiB */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_OVERWRITE - -/* - * Save the prior stage provided DTB. - */ -/* - * Enable in-place RFS with this initrd_high setting. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdtsaveaddr=" __stringify(CONFIG_SYS_FDT_SAVE_ADDRESS) "\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" - -/* - * Set fdtaddr to prior stage-provided DTB in board_late_init, when - * writeable environment is available. - */ -#define CONFIG_BOARD_LATE_INIT - -#endif /* __BCMSTB_H */ diff --git a/include/configs/beaver.h b/include/configs/beaver.h deleted file mode 100644 index 4c5826c..0000000 --- a/include/configs/beaver.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" - -/* VDD core PMIC */ -#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1 - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Beaver" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_BEAVER - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h deleted file mode 100644 index c05b06a..0000000 --- a/include/configs/bg0900.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut - */ -#ifndef __CONFIGS_BG0900_H__ -#define __CONFIGS_BG0900_H__ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_OVERWRITE - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "bootm" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_spi_firmware_filename=u-boot.sb\0" \ - "update_spi_firmware_maxsz=0x80000\0" \ - "update_spi_firmware=" /* Update the SPI flash firmware */ \ - "if sf probe 2:0 ; then " \ - "if tftp ${update_spi_firmware_filename} ; then " \ - "sf erase 0x0 +${filesize} ; " \ - "sf write ${loadaddr} 0x0 ${filesize} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_BG0900_H__ */ diff --git a/include/configs/bitmain_antminer_s9.h b/include/configs/bitmain_antminer_s9.h deleted file mode 100644 index a9f45f1..0000000 --- a/include/configs/bitmain_antminer_s9.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2018 Michal Simek - */ - -#ifndef __CONFIG_BITMAIN_ANTMINER_S9_H -#define __CONFIG_BITMAIN_ANTMINER_S9_H - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 - -#define CONFIG_BOOTP_SERVERIP - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "pxefile_addr_r=0x2000000\0" \ - "scriptaddr=0x3000000\0" \ - "kernel_addr_r=0x2000000\0" \ - "fdt_high=0xefff000\0" \ - "initrd_high=0xefff000\0" \ - "devnum=0\0" \ - "wdstop=mw f8005000 ABC000\0" \ - BOOTENV - -#include - -#endif /* __CONFIG_BITMAIN_ANTMINER_S9_H */ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h deleted file mode 100644 index 285e28b..0000000 --- a/include/configs/bk4r1.h +++ /dev/null @@ -1,270 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - * - * Copyright 2016 3ADEV - * Written-by: Albert ARIBAUD - * - * Configuration settings for BK4R1. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* Define the BK4r1-specific env commands */ -#define BK4_EXTRA_ENV_SETTINGS \ - "bootlimit=3\0" \ - "eraseuserdata=false\0" \ - "altbootcmd=led 5 on; " \ - "boot\0" \ - "set_gpio103=mw 0x400ff0c4 0x0080; mw 0x4004819C 0x000011bf\0" \ - "set_gpio102=mw 0x400ff0c4 0x40; mw 0x40048198 0x000011bf\0" \ - "set_gpio96=mw 0x40048180 0x282; mw 0x400ff0c4 0x1\0"\ - "set_gpio122=mw 0x400481e8 0x0282; mw 0x400ff0c4 0x04000000\0"\ - "set_gpio6=mw 0x40048018 0x282; mw 0x400ff008 0x40\0"\ - "manage_userdata=" MANAGE_USERDATA "\0"\ - "ncenable=true\0"\ - "ncserverip=192.168.0.77\0"\ - "if_netconsole=ping $ncserverip\0"\ - "start_netconsole=setenv ncip $serverip; setenv bootdelay 10;" \ - "setenv stdin nc; setenv stdout nc; setenv stderr nc; version;\0" \ - "preboot=" BK4_NET_INIT \ - "if ${ncenable}; then run if_netconsole start_netconsole; fi\0" - -/* BK4r1 boot command sets GPIO103/PTC30 to force USB hub out of reset*/ -#define BK4_BOOTCOMMAND "run set_gpio122; run set_gpio96; sf probe; " \ - "run manage_userdata; " - -/* Enable PREBOOT variable */ - -/* Set ARP_TIMEOUT to 500ms */ -#define CONFIG_ARP_TIMEOUT 500UL - -/* Set ARP_TIMEOUT_COUNT to 3 repetitions */ -#define CONFIG_NET_RETRY_COUNT 5 - -/* BK4r1 net init sets GPIO122/PTE17 to enable Ethernet */ -#define BK4_NET_INIT "run set_gpio122;" - -/* Check if userdata volume shall be erased */ -#define MANAGE_USERDATA "if ${eraseuserdata}; " \ - "then ubi part system; " \ - "ubi remove userdata; " \ - "ubi create userdata; " \ - "ubi detach; " \ - "setenv eraseuserdata false; " \ - "saveenv; " \ - "fi; " - -/* Autoboot options */ -#define CONFIG_AUTOBOOT_KEYED -#define CONFIG_AUTOBOOT_PROMPT \ - "Enter passphrase to stop autoboot, booting in %d seconds\n" -#define CONFIG_AUTOBOOT_STOP_STR "123" - -#include -#include - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 4 * SZ_1M) - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define IMX_FEC1_BASE ENET1_BASE_ADDR - -/* QSPI Configs*/ -#ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE (SZ_16M) -#define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SYS_FSL_QSPI_LE -#endif - -#define CONFIG_LOADADDR 0x82000000 - -/* We boot from the gfxRAM area of the OCRAM. */ -#define CONFIG_BOARD_SIZE_LIMIT 520192 - -/* boot command, including the target-defined one if any */ -#define CONFIG_BOOTCOMMAND BK4_BOOTCOMMAND "run bootcmd_nand" - -/* Extra env settings (including the target-defined ones if any) */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - BK4_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "blimg_file=u-boot.vyb\0" \ - "blimg_addr=0x81000000\0" \ - "dtbkernel_file=fitImage\0" \ - "dtbkernel_addr=0x82000000\0" \ - "ram_file=uRamdisk\0" \ - "ram_addr=0x83000000\0" \ - "filesys=rootfs.ubifs\0" \ - "sys_addr=0x81000000\0" \ - "nfs_root=/path/to/nfs/root\0" \ - "tftptimeout=1000\0" \ - "tftptimeoutcountmax=1000000\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "ipaddr=192.168.0.60\0" \ - "serverip=192.168.0.1\0" \ - "bootargs_base=setenv bootargs rw " \ - "console=ttyLP1,115200n8\0" \ - "bootargs_sd=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 rootwait\0" \ - "bootargs_nand=setenv bootargs ${bootargs} " \ - "ubi.mtd=5 rootfstype=" \ - "ubifs root=ubi0:rootfs${active_workset}\0" \ - "bootargs_ram=setenv bootargs ${bootargs} " \ - "root=/dev/ram rw initrd=${ram_addr}\0" \ - "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ - "fatload mmc 0:2 ${dtbkernel_addr} ${dtbkernel_file}; " \ - "bootm ${dtbkernel_addr}\0" \ - "bootcmd_nand=sf probe;run bootargs_base bootargs_nand bootargs_mtd; " \ - "ubi part dtbkernel; " \ - "ubi readvol ${dtbkernel_addr} dtbkernel${active_workset}; " \ - "led 0 on; " \ - "bootm ${dtbkernel_addr}\0" \ - "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ - "nand read ${fdt_addr} dtb; " \ - "nand read ${kernel_addr} kernel; " \ - "nand read ${ram_addr} root; " \ - "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ - "update_bootloader_from_sd=if fatload mmc 0:2 ${blimg_addr} " \ - "${blimg_file}; " \ - "then sf probe; " \ - "mtdparts default; " \ - "nand erase.part bootloader; " \ - "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ - "update_bootloader_from_tftp=if tftp ${blimg_addr} "\ - "${tftpdir}${blimg_file}; "\ - "then sf probe; " \ - "mtdparts default; " \ - "nand erase.part bootloader; " \ - "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ - "update_dtbkernel_from_sd=if fatload mmc 0:2 ${dtbkernel_addr} " \ - "${dtbkernel_file}; " \ - "then sf probe; " \ - "ubi part dtbkernel; " \ - "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ - "${filesize}; " \ - "ubi detach; fi\0" \ - "update_dtbkernel_from_tftp=if tftp ${dtbkernel_addr} " \ - "${tftpdir}${dtbkernel_file}; " \ - "then sf probe; " \ - "ubi part dtbkernel; " \ - "ubi write ${dtbkernel_addr} dtbkernel${active_workset} " \ - "${filesize}; " \ - "ubi detach; fi\0" \ - "update_ramdisk_from_sd=if fatload mmc 0:2 ${ram_addr} " \ - "${ram_file}; " \ - "then sf probe; " \ - "mtdparts default; " \ - "nand erase.part initrd; " \ - "nand write ${ram_addr} initrd ${filesize}; fi\0" \ - "update_ramdisk_from_tftp=if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ - "then sf probe; " \ - "nand erase.part initrd; " \ - "nand write ${ram_addr} initrd ${filesize}; fi\0" \ - "update_rootfs_from_sd=if fatload mmc 0:2 ${sys_addr} " \ - "${filesys}; " \ - "then sf probe; " \ - "ubi part system; " \ - "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ - "ubi detach; fi\0" \ - "update_rootfs_from_tftp=if tftp ${sys_addr} ${tftpdir}${filesys}; " \ - "then sf probe; " \ - "ubi part system; " \ - "ubi write ${sys_addr} rootfs${active_workset} ${filesize}; " \ - "ubi detach; fi\0" \ - "setup_dtbkernel=nand erase.part dtbkernel; " \ - "ubi part dtbkernel; " \ - "ubi create dtbkernel1 972000 s; " \ - "ubi create dtbkernel2 972000 s; " \ - "ubi detach\0" \ - "setup_system=nand erase.part system; " \ - "ubi part system; " \ - "ubi create rootfs1 15E15000 d; " \ - "ubi create rootfs2 15E15000 d; " \ - "ubi create userdata; " \ - "ubi detach\0" \ - "setup_nor1=" BK4_NET_INIT \ - "if tftp ${sys_addr} ${tftpdir}ubinor1.img; " \ - "then sf probe 0:0; " \ - "sf erase 0 01000000; " \ - "mtdparts default; " \ - "ubi part nor; " \ - "ubi create nor1fs; " \ - "ubi write ${sys_addr} nor1fs ${filesize}; " \ - "ubi detach; fi\0" \ - "setup_nor2=" BK4_NET_INIT \ - "if tftp ${sys_addr} ${tftpdir}ubinor2.img; " \ - "then sf probe 0:1; " \ - "sf erase 0 01000000; " \ - "mtdparts default; " \ - "ubi part nor; " \ - "ubi create nor2fs; " \ - "ubi write ${sys_addr} nor2fs ${filesize}; " \ - "ubi detach; fi\0" \ - "prepare_install_bk4r1_envs=" \ - "echo 'Preparing envs for SD card recovery!';" \ - "setenv ipaddr 192.168.0.99;" \ - "setenv serverip 192.168.0.50;" \ - "\0" \ - "install_bk4r1rs="\ - "led 0 on; " \ - "nand erase.chip; mtdparts default; "\ - "led 1 on; "\ - "run setup_dtbkernel; " \ - "run setup_system; " \ - "led 2 on;" \ - "run update_bootloader_from_sd; "\ - "run update_dtbkernel_from_sd; "\ - "run update_rootfs_from_sd; "\ - "setenv bootcmd 'run bootcmd_nand'; "\ - "saveenv; " \ - "led 3 on; " \ - "echo Finished - Please Power off, REMOVE SDCARD and set boot" \ - "source to NAND\0" \ - "active_workset=1\0" - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x80010000 -#define CONFIG_SYS_MEMTEST_END 0x87C00000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical memory map */ -#define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (SZ_512M) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE (SZ_128K) -#define CONFIG_ENV_SIZE (SZ_8K) -#define CONFIG_ENV_OFFSET 0x200000 -#define CONFIG_ENV_SIZE_REDUND (SZ_8K) -#define CONFIG_ENV_OFFSET_REDUND 0x220000 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h deleted file mode 100644 index 8774bde..0000000 --- a/include/configs/blanche.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/blanche.h - * This file is blanche board configuration. - * - * Copyright (C) 2016 Renesas Electronics Corporation - */ - -#ifndef __BLANCHE_H -#define __BLANCHE_H - -#include "rcar-gen2-common.h" - -/* STACK */ -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 -#define STACK_AREA_SIZE 0x00100000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) -#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -/* FLASH */ -#if !defined(CONFIG_MTD_NOR_FLASH) -#define CONFIG_SH_QSPI_BASE 0xE6B10000 -#else -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (CONFIG_SYS_FLASH_SIZE) } - -#define CONFIG_SYS_FLASH_ERASE_TOUT 3000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 3000 -#define CONFIG_SYS_FLASH_LOCK_TOUT 3000 -#define CONFIG_SYS_FLASH_UNLOCK_TOUT 3000 -#undef CONFIG_CMD_SF -#undef CONFIG_CMD_SPI -#endif - -/* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK - -/* ENV setting */ -#if !defined(CONFIG_MTD_NOR_FLASH) -#else -#undef CONFIG_ENV_ADDR -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) -#endif - -#endif /* __BLANCHE_H */ diff --git a/include/configs/bmips_bcm3380.h b/include/configs/bmips_bcm3380.h deleted file mode 100644 index 573ff3e..0000000 --- a/include/configs/bmips_bcm3380.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM3380_H -#define __CONFIG_BMIPS_BCM3380_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#endif /* __CONFIG_BMIPS_BCM3380_H */ diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h deleted file mode 100644 index c7e7119..0000000 --- a/include/configs/bmips_bcm6318.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM6318_H -#define __CONFIG_BMIPS_BCM6318_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 166500000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_OHCI_NEW - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#endif /* __CONFIG_BMIPS_BCM6318_H */ diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h deleted file mode 100644 index 45f26bb..0000000 --- a/include/configs/bmips_bcm63268.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM63268_H -#define __CONFIG_BMIPS_BCM63268_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_OHCI_NEW - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#endif /* __CONFIG_BMIPS_BCM63268_H */ diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h deleted file mode 100644 index 8d59438..0000000 --- a/include/configs/bmips_bcm6328.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM6328_H -#define __CONFIG_BMIPS_BCM6328_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_OHCI_NEW - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#endif /* __CONFIG_BMIPS_BCM6328_H */ diff --git a/include/configs/bmips_bcm6338.h b/include/configs/bmips_bcm6338.h deleted file mode 100644 index 38dd9e3..0000000 --- a/include/configs/bmips_bcm6338.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM6338_H -#define __CONFIG_BMIPS_BCM6338_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 120000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 - -#endif /* __CONFIG_BMIPS_BCM6338_H */ diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h deleted file mode 100644 index 061d6b2..0000000 --- a/include/configs/bmips_bcm6348.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM6348_H -#define __CONFIG_BMIPS_BCM6348_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 128000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* USB */ -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_OHCI_NEW - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 - -#endif /* __CONFIG_BMIPS_BCM6348_H */ diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h deleted file mode 100644 index 583217d..0000000 --- a/include/configs/bmips_bcm6358.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM6358_H -#define __CONFIG_BMIPS_BCM6358_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 150000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_OHCI_NEW - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#define CONFIG_SYS_FLASH_BASE 0xbe000000 -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 - -#endif /* __CONFIG_BMIPS_BCM6358_H */ diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h deleted file mode 100644 index 570bc3b..0000000 --- a/include/configs/bmips_bcm6362.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM6362_H -#define __CONFIG_BMIPS_BCM6362_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_OHCI_NEW - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h deleted file mode 100644 index ab5bdac..0000000 --- a/include/configs/bmips_bcm6368.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_BCM6368_H -#define __CONFIG_BMIPS_BCM6368_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* USB */ -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#define CONFIG_USB_OHCI_NEW - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#define CONFIG_SYS_FLASH_BASE 0xb8000000 -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 - -#endif /* __CONFIG_BMIPS_BCM6368_H */ diff --git a/include/configs/bmips_bcm6838.h b/include/configs/bmips_bcm6838.h deleted file mode 100644 index f1ff054..0000000 --- a/include/configs/bmips_bcm6838.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Philippe Reynes - */ - -#ifndef __CONFIG_BMIPS_BCM6838_H -#define __CONFIG_BMIPS_BCM6838_H - -#include - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* U-Boot */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_1M - -#if defined(CONFIG_BMIPS_BOOT_RAM) -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_INIT_SP_OFFSET SZ_8K -#endif - -#endif /* __CONFIG_BMIPS_BCM6838_H */ diff --git a/include/configs/bmips_common.h b/include/configs/bmips_common.h deleted file mode 100644 index 3cb2d40..0000000 --- a/include/configs/bmips_common.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#ifndef __CONFIG_BMIPS_COMMON_H -#define __CONFIG_BMIPS_COMMON_H - -#include - -/* ETH */ -#define CONFIG_PHY_RESET_DELAY 20 -#define CONFIG_SYS_RX_ETH_BUFFER 6 - -/* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } - -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN SZ_2M -#define CONFIG_SYS_BOOTPARAMS_LEN SZ_128K -#define CONFIG_SYS_CBSIZE SZ_512 - -/* U-Boot */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#endif /* __CONFIG_BMIPS_COMMON_H */ diff --git a/include/configs/boston.h b/include/configs/boston.h deleted file mode 100644 index 61aaa26..0000000 --- a/include/configs/boston.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2016 Imagination Technologies - */ - -#ifndef __CONFIGS_BOSTON_H__ -#define __CONFIGS_BOSTON_H__ - -/* - * General board configuration - */ -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - -/* - * CPU - */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 30000000 - -/* - * PCI - */ - -/* - * Memory map - */ -#ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 -#else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 -#endif - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x08000000) - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x10000000) - -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) - -/* - * Console - */ - -/* - * Flash - */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -/* - * Environment - */ -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#ifdef CONFIG_64BIT -# define CONFIG_ENV_ADDR \ - (0xffffffffb8000000 + (128 << 20) - CONFIG_ENV_SIZE) -#else -# define CONFIG_ENV_ADDR \ - (0xb8000000 + (128 << 20) - CONFIG_ENV_SIZE) -#endif - -#endif /* __CONFIGS_BOSTON_H__ */ diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h deleted file mode 100644 index a0f7ead..0000000 --- a/include/configs/broadcom_bcm963158.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Philippe Reynes - */ - -#include - -/* - * common - */ - -/* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (16 * 1024 * 1024) - -/* - * 63158 - */ - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#ifdef CONFIG_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif /* CONFIG_NAND */ - -/* - * bcm963158 - */ - -#define CONFIG_ENV_SIZE (8 * 1024) diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h deleted file mode 100644 index b0e9337..0000000 --- a/include/configs/broadcom_bcm968380gerg.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Philippe Reynes - */ - -#include -#include - -#define CONFIG_ENV_SIZE SZ_8K - -#ifdef CONFIG_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif /* CONFIG_NAND */ diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h deleted file mode 100644 index fdb6203..0000000 --- a/include/configs/broadcom_bcm968580xref.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Philippe Reynes - */ - -#include - -/* - * common - */ - -/* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 500000, 1500000 } -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 24 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* - * 6858 - */ - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* U-Boot */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_16M) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#ifdef CONFIG_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif /* CONFIG_NAND */ - -/* - * 968580xref - */ - -#define CONFIG_ENV_SIZE (8 * 1024) diff --git a/include/configs/brppt1.h b/include/configs/brppt1.h deleted file mode 100644 index bc0dabb..0000000 --- a/include/configs/brppt1.h +++ /dev/null @@ -1,203 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * brtpp1.h - * - * specific parts for B&R T-Series Motherboard - * - * Copyright (C) 2013 Hannes Schmelzer - - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - */ - -#ifndef __CONFIG_BRPPT1_H__ -#define __CONFIG_BRPPT1_H__ - -#include -#include -/* ------------------------------------------------------------------------- */ -/* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN SZ_32M - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_POWER_TPS65217 - -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -/*#define CONFIG_MACH_TYPE 3589*/ -#define CONFIG_MACH_TYPE 0xFFFFFFFF /* TODO: check with kernel*/ - -/* - * When we have NAND flash we expect to be making use of mtdparts, - * both for ease of use in U-Boot and for passing information on to - * the Linux kernel. - */ - -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 - -/* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x900 /* address 0x120000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x80 /* address 0x10000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x80 /* 64KiB */ - -/* NAND */ -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x140000 -#endif /* CONFIG_NAND */ -#endif /* CONFIG_SPL_OS_BOOT */ - -#ifdef CONFIG_NAND -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#endif /* CONFIG_NAND */ - -#ifdef CONFIG_NAND -#define NANDTGTS \ -"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ -"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ -"cfgscr=mw ${dtbaddr} 0; nand read ${cfgaddr} cfgscr && source ${cfgaddr};" \ -" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ -"nandargs=setenv bootargs console=${console} ${optargs} ${optargs_rot} " \ - "root=mtd6 rootfstype=jffs2 b_mode=${b_mode}\0" \ -"b_nand=nand read ${loadaddr} kernel; nand read ${dtbaddr} dtb; " \ - "run nandargs; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \ -"b_tgts_std=usb0 nand net\0" \ -"b_tgts_rcy=net usb0 nand\0" \ -"b_tgts_pme=usb0 nand net\0" -#else -#define NANDTGTS "" -#endif /* CONFIG_NAND */ - -#define MMCSPI_TGTS \ -"t30args#0=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ - "b_mode=${b_mode} root=/dev/mmcblk0p2 rootfstype=ext4\0" \ -"b_t30lgcy#0=" \ - "load ${loaddev}:2 ${loadaddr} /boot/PPTImage.md5 && " \ - "load ${loaddev}:2 ${loadaddr} /boot/zImage && " \ - "load ${loaddev}:2 ${dtbaddr} /boot/am335x-ppt30.dtb || " \ - "load ${loaddev}:1 ${dtbaddr} am335x-ppt30-legacy.dtb; "\ - "run t30args#0; run cfgscr; bootz ${loadaddr} - ${dtbaddr}\0" \ -"t30args#1=setenv bootargs ${optargs_rot} ${optargs} console=${console} " \ - "b_mode=${b_mode}\0" \ -"b_t30lgcy#1=" \ - "load ${loaddev}:1 ${loadaddr} zImage && " \ - "load ${loaddev}:1 ${dtbaddr} am335x-ppt30.dtb && " \ - "load ${loaddev}:1 ${ramaddr} rootfsPPT30.uboot && " \ - "run t30args#1; run cfgscr; bootz ${loadaddr} ${ramaddr} ${dtbaddr}\0" \ -"b_mmc0=load ${loaddev}:1 ${scraddr} bootscr.img && source ${scraddr}\0" \ -"b_mmc1=load ${loaddev}:1 ${scraddr} /boot/bootscr.img && source ${scraddr}\0" \ -"b_tgts_std=mmc0 mmc1 t30lgcy#0 t30lgcy#1 usb0 net\0" \ -"b_tgts_rcy=t30lgcy#1 usb0 net\0" \ -"b_tgts_pme=net usb0 mmc0 mmc1\0" \ -"loaddev=mmc 1\0" - -#ifdef CONFIG_ENV_IS_IN_MMC -#define MMCTGTS \ -MMCSPI_TGTS \ -"cfgscr=mw ${dtbaddr} 0;" \ -" mmc dev 1; mmc read ${cfgaddr} 200 80; source ${cfgaddr};" \ -" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" -#else -#define MMCTGTS "" -#endif /* CONFIG_MMC */ - -#ifdef CONFIG_SPI -#define SPITGTS \ -MMCSPI_TGTS \ -"cfgscr=mw ${dtbaddr} 0;" \ -" sf probe; sf read ${cfgaddr} 0xC0000 10000; source ${cfgaddr};" \ -" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" -#else -#define SPITGTS "" -#endif /* CONFIG_SPI */ - -#define LOAD_OFFSET(x) 0x8##x - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ -BUR_COMMON_ENV \ -"verify=no\0" \ -"autoload=0\0" \ -"scraddr=" __stringify(LOAD_OFFSET(0000000)) "\0" \ -"cfgaddr=" __stringify(LOAD_OFFSET(0020000)) "\0" \ -"dtbaddr=" __stringify(LOAD_OFFSET(0040000)) "\0" \ -"loadaddr=" __stringify(LOAD_OFFSET(0100000)) "\0" \ -"ramaddr=" __stringify(LOAD_OFFSET(2000000)) "\0" \ -"console=ttyO0,115200n8\0" \ -"optargs=consoleblank=0 quiet panic=2\0" \ -"b_break=0\0" \ -"b_usb0=usb start && load usb 0 ${scraddr} bootscr.img && source ${scraddr}\0" \ -"b_net=tftp ${scraddr} netscript.img && source ${scraddr}\0" \ -MMCTGTS \ -SPITGTS \ -NANDTGTS \ -"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ -" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ -" else setenv b_tgts ${b_tgts_std}; fi\0" \ -"b_default=run b_deftgts; for target in ${b_tgts};"\ -" do echo \"### booting ${target} ###\"; run b_${target};" \ -" if test ${b_break} = 1; then; exit; fi; done\0" -#endif /* !CONFIG_SPL_BUILD*/ - -#ifdef CONFIG_NAND -/* - * GPMC block. We support 1 device and the physical address to - * access CS0 at is 0x8000000. - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x8000000 -/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */ -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_NAND_OMAP_GPMC_WSCFG 1 -#endif /* CONFIG_NAND */ - -#if defined(CONFIG_SPI) -/* SPI Flash */ -/* Environment */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#elif defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#elif defined(CONFIG_ENV_IS_IN_NAND) -/* No NAND env support in SPL */ -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_ENV_SIZE -#else -#error "no storage for Environment defined!" -#endif - -#endif /* ! __CONFIG_BRPPT1_H__ */ diff --git a/include/configs/brsmarc1.h b/include/configs/brsmarc1.h deleted file mode 100644 index 19e796e..0000000 --- a/include/configs/brsmarc1.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * brsmarc1.h - * - * specific parts for B&R BRSMARC1 Motherboard - * - * Copyright (C) 2017 Hannes Schmelzer - - * B&R Industrial Automation GmbH - http://www.br-automation.com - * - */ - -#ifndef __CONFIG_BRSMARC1_H__ -#define __CONFIG_BRSMARC1_H__ - -#include -#include -/* ------------------------------------------------------------------------- */ -#define CONFIG_BOARD_TYPES - -/* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_MACH_TYPE 3589 - -#ifndef CONFIG_SPL_BUILD - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ -BUR_COMMON_ENV \ -"autoload=0\0" \ -"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ -"cfgscr=mw ${dtbaddr} 0;" \ -" sf probe && sf read ${scradr} 0xC0000 0x10000 && source ${scradr};" \ -" fdt addr ${dtbaddr} || cp ${fdtcontroladdr} ${dtbaddr} 4000\0" \ -"dtbaddr=0x84000000\0" \ -"loadaddr=0x82000000\0" \ -"b_break=0\0" \ -"b_tgts_std=mmc0 mmc1 def net usb0\0" \ -"b_tgts_rcy=def net usb0\0" \ -"b_tgts_pme=net usb0 mmc0 mmc1\0" \ -"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ -" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ -" else setenv b_tgts ${b_tgts_std}; fi\0" \ -"b_mmc0=load mmc 1 ${scradr} bootscr.img && source ${scradr}\0" \ -"b_mmc1=load mmc 1 ${loadaddr} arimg.ugz && run startsys\0" \ -"b_def=sf read ${loadaddr} 100000 700000; run startsys\0" \ -"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \ -"b_usb0=usb start && load usb 0 ${scradr} bootscr.img && source ${scradr}\0" \ -"b_default=run b_deftgts; for target in ${b_tgts};"\ -" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" \ -"vxargs=setenv bootargs cpsw(0,0)host:vxWorks h=${serverip}" \ -" e=${ipaddr}:${netmask} g=${gatewayip} u=vxWorksFTP pw=vxWorks\0" \ -"vxfdt=fdt addr ${dtbaddr}; fdt resize 0x8000;" \ -" fdt boardsetup\0" \ -"startsys=run vxargs && mw 0x80001100 0 && run vxfdt &&" \ -" bootm ${loadaddr} - ${dtbaddr}\0" -#endif /* !CONFIG_SPL_BUILD*/ - -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* SPI Flash */ - -/* Environment */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) - -#define CONFIG_CONS_INDEX 1 -#endif /* __CONFIG_BRSMARC1_H__ */ diff --git a/include/configs/brxre1.h b/include/configs/brxre1.h deleted file mode 100644 index c6e308b..0000000 --- a/include/configs/brxre1.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * brxre1.h - * - * specific parts for B&R KWB Motherboard - * - * Copyright (C) 2013 Hannes Schmelzer - - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - */ - -#ifndef __CONFIG_BRXRE1_H__ -#define __CONFIG_BRXRE1_H__ - -#include -#include -/* ------------------------------------------------------------------------- */ -#define CONFIG_AM335X_LCD -#define LCD_BPP LCD_COLOR32 - -/* memory */ -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_MACH_TYPE 3589 - -#ifndef CONFIG_SPL_BUILD - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ -BUR_COMMON_ENV \ -"autoload=0\0" \ -"scradr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ -"bootaddr=0x80001100\0" \ -"bootdev=cpsw(0,0)\0" \ -"vx_romfsbase=0x800E0000\0" \ -"vx_romfssize=0x20000\0" \ -"vx_memtop=0x8FBEF000\0" \ -"loadromfs=mmc read ${vx_romfsbase} 700 100\0" \ -"loadaddr=0x80100000\0" \ -"startvx=run loadromfs; bootvx ${loadaddr}\0" \ -"b_break=0\0" \ -"b_tgts_std=mmc def net usb0\0" \ -"b_tgts_rcy=def net usb0\0" \ -"b_tgts_pme=net usb0 mmc\0" \ -"b_deftgts=if test ${b_mode} = 12; then setenv b_tgts ${b_tgts_pme};" \ -" elif test ${b_mode} = 0; then setenv b_tgts ${b_tgts_rcy};" \ -" else setenv b_tgts ${b_tgts_std}; fi\0" \ -"b_mmc=load mmc 1 ${loadaddr} arimg && run startvx\0" \ -"b_def=mmc read ${loadaddr} 800 8000; run startvx\0" \ -"b_net=tftp ${scradr} netscript.img && source ${scradr}\0" \ -"b_usb0=usb start && load usb 0 ${scradr} usbscript.img && source ${scradr}\0" \ -"b_default=run b_deftgts; for target in ${b_tgts};"\ -" do run b_${target}; if test ${b_break} = 1; then; exit; fi; done\0" -#endif /* !CONFIG_SPL_BUILD*/ - -#define CONFIG_BOOTCOMMAND "mmc dev 1; run b_default" - -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* Environment */ -#define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_OFFSET 0x40000 /* TODO: Adresse definieren */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#endif /* __CONFIG_BRXRE1_H__ */ diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h deleted file mode 100644 index e1dc37b..0000000 --- a/include/configs/bubblegum_96.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Board configuration file for Bubblegum-96 - * - * Copyright (C) 2015 Actions Semi Co., Ltd. - * Copyright (C) 2018 Manivannan Sadhasivam - * - */ - -#ifndef _BUBBLEGUM_96_H_ -#define _BUGGLEGUM_96_H_ - -/* SDRAM Definitions */ -#define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_SDRAM_SIZE 0x80000000 - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (24000000) /* 24MHz */ - -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - -/* Some commands use this as the default load address */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0) - -/* - * This is the initial SP which is used only briefly for relocating the u-boot - * image to the top of SDRAM. After relocation u-boot moves the stack to the - * proper place. - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00) - -/* UART Definitions */ -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_ENV_SIZE 0x2000 - -/* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#endif diff --git a/include/configs/bur_am335x_common.h b/include/configs/bur_am335x_common.h deleted file mode 100644 index 42e3e56..0000000 --- a/include/configs/bur_am335x_common.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * bur_am335x_common.h - * - * common parts used by B&R AM335x based boards - * - * Copyright (C) 2016 Hannes Schmelzer - - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - */ - -#ifndef __BUR_AM335X_COMMON_H__ -#define __BUR_AM335X_COMMON_H__ -/* ------------------------------------------------------------------------- */ - -/* legacy #defines for non DM bur-board */ -#ifndef CONFIG_DM -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 - -#define CONFIG_I2C -#define CONFIG_SYS_I2C - -#endif /* CONFIG_DM */ - -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -/* Timer information */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_POWER_TPS65217 - -#include - -/* - * SPL related defines. The Public RAM memory map the ROM defines the - * area between 0x402F0400 and 0x4030B800 as a download area and - * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also - * supports X-MODEM loading via UART, and we leverage this and then use - * Y-MODEM to load u-boot.img, when booted over UART. We must also include - * the scratch space that U-Boot uses in SRAM. - */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif /* !CONFIG_SPL_BUILD, ... */ -/* - * Our DDR memory always starts at 0x80000000 and U-Boot shall have - * relocated itself to higher in memory by the time this value is used. - */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 -/* - * ---------------------------------------------------------------------------- - * DDR information. We say (for simplicity) that we have 1 bank, - * always, even when we have more. We always start at 0x80000000, - * and we place the initial stack pointer in our SRAM. - */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -/* - * Our platforms make use of SPL to initalize the hardware (primarily - * memory) enough for full U-Boot to be loaded. We also support Falcon - * Mode so that the Linux kernel can be booted directly from SPL - * instead, if desired. We make use of the general SPL framework found - * under common/spl/. Given our generally common memory map, we set a - * number of related defaults and sizes here. - */ -/* - * Place the image at the start of the ROM defined image space. - * We limit our size to the ROM-defined downloaded image area, and use the - * rest of the space for stack. We load U-Boot itself into memory at - * 0x80800000 for legacy reasons (to not conflict with older SPLs). We - * have our BSS be placed 1MiB after this, to allow for the default - * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. - * We have the SPL malloc pool at the end of the BSS area. - * - * ---------------------------------------------------------------------------- - */ -#define CONFIG_SPL_BSS_START_ADDR 0x80A00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN - -/* General parts of the framework, required. */ - -#endif /* ! __BUR_AM335X_COMMON_H__ */ diff --git a/include/configs/bur_cfg_common.h b/include/configs/bur_cfg_common.h deleted file mode 100644 index dff4123..0000000 --- a/include/configs/bur_cfg_common.h +++ /dev/null @@ -1,44 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * bur_cfg_common.h - * - * common parts used over all B&R boards - * - * Copyright (C) 2016 Hannes Schmelzer - - * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com - */ - -#ifndef __BUR_CFG_COMMON_H__ -#define __BUR_CFG_COMMON_H__ -/* ------------------------------------------------------------------------- */ -#define BUR_COMMON_ENV \ -"usbscript=usb start && fatload usb 0 ${scradr} usbscript.img &&" \ -" source ${scradr}\0" \ -"brdefaultip=if test -r ${ipaddr}; then; else" \ -" setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ -" setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ -"netconsole=echo switching to network console ...; " \ -"if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ -"setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ -"setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ -"setenv stdout nc;setenv stdin nc;setenv stderr nc\0" - -/* Network defines */ -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* Network console */ -#define CONFIG_NETCONSOLE 1 -#define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */ - -#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ - -/* As stated above, the following choices are optional. */ - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -#endif /* __BUR_CFG_COMMON_H__ */ diff --git a/include/configs/caddy2.h b/include/configs/caddy2.h deleted file mode 100644 index 89deeac..0000000 --- a/include/configs/caddy2.h +++ /dev/null @@ -1,333 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * esd vme8349 U-Boot configuration file - * Copyright (c) 2008, 2009 esd gmbh Hannover Germany - * - * (C) Copyright 2006-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * reinhard.arlt@esd-electronics.de - * Based on the MPC8349EMDS config. - */ - -/* - * vme8349 board configuration file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * DDR Setup - */ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM -#define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_SYS_READ_SPD vme8349_read_spd -#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) -#define CONFIG_DDR_2T_TIMING -#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x80080001 */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ - - -#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ - -#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ - -#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0xFIXME -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_GMII /* MII PHY management */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_PHY_M88E1111 -#define TSEC1_PHY_ADDR 0x08 -#define TSEC2_PHY_ADDR 0x10 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ -#define CONFIG_SYS_RTC_BUS_NUM 0x01 -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 - -/* Pass Ethernet MAC to VxWorks */ -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0x00100000 -#define CONFIG_SYS_GPIO1_DAT 0x00100000 - -#define CONFIG_SYS_GPIO2_PRELIM -#define CONFIG_SYS_GPIO2_DIR 0x78900000 -#define CONFIG_SYS_GPIO2_DAT 0x70100000 - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_HOSTNAME "VME8349" -#define CONFIG_ROOTPATH "/tftpboot/rootfs" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=vme8349\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ - "update=protect off fff00000 fff3ffff; " \ - "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=vme8349.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#ifndef __ASSEMBLY__ -int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/cardhu.h b/include/configs/cardhu.h deleted file mode 100644 index 8d541a1..0000000 --- a/include/configs/cardhu.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" - -/* VDD core PMIC */ -#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3 - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu" - -#define BOARD_EXTRA_ENV_SETTINGS \ - "board_name=cardhu-a04\0" \ - "fdtfile=tegra30-cardhu-a04.dtb\0" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/cei-tk1-som.h b/include/configs/cei-tk1-som.h deleted file mode 100644 index e6abfe2..0000000 --- a/include/configs/cei-tk1-som.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (c) Copyright 2016, Data61 - * Commonwealth Scientific and Industrial Research Organisation (CSIRO) - * - * Based on jetson-tk1.h which is: - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "CEI tk1-som" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#define CONFIG_ARMV7_PSCI 1 -#define CONFIG_ARMV7_PSCI_NR_CPUS 4 -/* Reserve top 1M for secure RAM */ -#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 -#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h deleted file mode 100644 index f109b22..0000000 --- a/include/configs/cgtqmx6eval.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * - * Congatec Conga-QEVAl board configuration file. - * - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * Based on Freescale i.MX6Q Sabre Lite board configuration file. - * Copyright (C) 2013, Adeneo Embedded - * Leo Sartre, - */ - -#ifndef __CONFIG_CGTQMX6EVAL_H -#define __CONFIG_CGTQMX6EVAL_H - -#include "mx6_common.h" - -#define CONFIG_MACH_TYPE 4122 - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* SPI NOR */ -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST - -/* Thermal support */ -#define CONFIG_IMX_THERMAL - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ - -#define CONFIG_USBD_HS - -/* Framebuffer */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI - -/* SATA */ -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 -#define CONFIG_PHY_ATHEROS - -/* Command definition */ - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p2" -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdtfile=undefined\0" \ - "fdt_addr_r=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ - "dfu_alt_info_spl=spl raw 0x400\0" \ - "dfu_alt_info_img=u-boot raw 0x10000\0" \ - "dfu_alt_info=spl raw 0x400\0" \ - "bootm_size=0x10000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-qmx6.dtb; fi; " \ - "if test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-qmx6.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; \0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\ - -#define CONFIG_BOOTCOMMAND \ - "run spilock;" \ - "run findfdt; " \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#if defined (CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#endif - -#endif /* __CONFIG_CGTQMX6EVAL_H */ diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h deleted file mode 100644 index 77ace93..0000000 --- a/include/configs/cherryhill.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, Bin Meng - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (2 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ - "stdout=vidconsole,serial\0" \ - "stderr=vidconsole,serial\0" - -/* Environment configuration */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OFFSET 0x005f0000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/chiliboard.h b/include/configs/chiliboard.h deleted file mode 100644 index 13c15bd..0000000 --- a/include/configs/chiliboard.h +++ /dev/null @@ -1,175 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Grinn - http://grinn-global.com/ - */ - -#ifndef __CONFIG_CHILIBOARD_H -#define __CONFIG_CHILIBOARD_H - -#include - -#ifndef CONFIG_SPL_BUILD -# define CONFIG_TIMESTAMP -#endif - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} ${optargs} " \ - "${mtdparts} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${fdt_addr} NAND.u-boot-spl-os; " \ - "nand read ${loadaddr} NAND.kernel; " \ - "bootz ${loadaddr} - ${fdt_addr}\0" - -#define CONFIG_BOOTCOMMAND \ - "run mmcboot; " \ - "run nandboot; " \ - "run netboot" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "fdt_addr=0x87800000\0" \ - "boot_fdt=try\0" \ - "console=ttyO0,115200n8\0" \ - "image=zImage\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "ip_dyn=yes\0" \ - "optargs=\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${boot_dir}/${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \ - "${boot_dir}/${fdt_file}\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} ${optargs} " \ - "${mtdparts} " \ - "root=${mmcroot}\0" \ - "mmcloados=run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadimage; then " \ - "run mmcloados;" \ - "fi;" \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} ${optargs} " \ - "${mtdparts} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - NANDARGS - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* PMIC support */ -#define CONFIG_POWER_TPS65217 - -/* SPL */ -/* Bootcount using the RTC block */ -#define CONFIG_SYS_BOOTCOUNT_BE - -/* NAND: device related configs */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -/* NAND: driver related configs */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 -/* NAND: SPL related configs */ - -/* USB configuration */ -#define CONFIG_ARCH_MISC_INIT -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -/* - * Disable MMC DM for SPL build and can be re-enabled after adding - * DM support in SPL - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_MMC -#undef CONFIG_TIMER -#endif - -#if defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#else -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#endif - -/* Network. */ -#define CONFIG_PHY_SMSC - -#endif /* ! __CONFIG_CHILIBOARD_H */ diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h deleted file mode 100644 index f26e463..0000000 --- a/include/configs/chromebook_link.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x003f8000 - -#define CONFIG_SPL_BOARD_LOAD_IMAGE - -#endif /* __CONFIG_H */ diff --git a/include/configs/chromebook_samus.h b/include/configs/chromebook_samus.h deleted file mode 100644 index 2f7dd69..0000000 --- a/include/configs/chromebook_samus.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -#undef CONFIG_STD_DEVICES_SETTINGS -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ - "stdout=vidconsole,serial\0" \ - "stderr=vidconsole,serial\0" - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x003f8000 - -#define CONFIG_TPL_TEXT_BASE 0xfffd8000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h deleted file mode 100644 index a7c2606..0000000 --- a/include/configs/chromebox_panther.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/ci20.h b/include/configs/ci20.h deleted file mode 100644 index 21a8632..0000000 --- a/include/configs/ci20.h +++ /dev/null @@ -1,71 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * CI20 configuration - * - * Copyright (c) 2013 Imagination Technologies - * Author: Paul Burton - */ - -#ifndef __CONFIG_CI20_H__ -#define __CONFIG_CI20_H__ - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Ingenic JZ4780 clock configuration. */ -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_MHZ 1200 -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -/* Memory configuration */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 -#define CONFIG_SYS_LOAD_ADDR 0x81000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x88000000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/* NS16550-ish UARTs */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_CONSOLE_IS_IN_ENV - -/* Ethernet: davicom DM9000 */ -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0xb6000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 2) - -/* Environment */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE (32 << 10) -#define CONFIG_ENV_OFFSET ((14 + 512) << 10) -#define CONFIG_ENV_OVERWRITE - -/* Command line configuration. */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ -#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ - -/* Miscellaneous configuration options */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -/* SPL */ -#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */ - -#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00) - -#define CONFIG_SPL_BSS_START_ADDR 0xf4004000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */ - -#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx" - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */ - -#endif /* __CONFIG_CI20_H__ */ diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h deleted file mode 100644 index d0a60c2..0000000 --- a/include/configs/cl-som-imx7.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 CompuLab, Ltd. - * - * Configuration settings for the CompuLab CL-SOM-iMX7 System-on-Module. - */ - -#ifndef __CL_SOM_IMX7_CONFIG_H -#define __CL_SOM_IMX7_CONFIG_H - -#include "mx7_common.h" - -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -#define CONFIG_BOARD_LATE_INIT - -/* Network */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PHYLIB -#define CONFIG_PHY_ATHEROS -/* ENET1 */ -#define IMX_FEC_BASE ENET_IPS_BASE_ADDR - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 - -/* I2C configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C2 /* Enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define SYS_I2C_BUS_SOM 0 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS SYS_I2C_BUS_SOM - -#define CONFIG_PCA953X -#define CONFIG_CMD_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } - -#undef CONFIG_SYS_AUTOLOAD -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_SYS_AUTOLOAD "no" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=off\0" \ - "script=boot.scr\0" \ - "loadscript=load ${storagetype} ${storagedev} ${loadaddr} ${script};\0" \ - "loadkernel=load ${storagetype} ${storagedev} ${loadaddr} ${kernel};\0" \ - "loadfdt=load ${storagetype} ${storagedev} ${fdtaddr} ${fdtfile};\0" \ - "bootscript=echo Running bootscript from ${storagetype} ...; source ${loadaddr};\0" \ - "storagebootcmd=echo Booting from ${storagetype} ...; run ${storagetype}args; run doboot;\0" \ - "kernel=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdtfile=imx7d-sbc-imx7.dtb\0" \ - "fdtaddr=0x83000000\0" \ - "mmcdev_def="__stringify(CONFIG_SYS_MMC_DEV)"\0" \ - "usbdev_def="__stringify(CONFIG_SYS_USB_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "usbpart=" __stringify(CONFIG_SYS_USB_IMG_LOAD_PART) "\0" \ - "doboot=bootz ${loadaddr} - ${fdtaddr}\0" \ - "mmc_config=mmc dev ${mmcdev}; mmc rescan\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mmcblk${mmcblk}p2 rootwait rw\0" \ - "mmcbootscript=" \ - "if run mmc_config; then " \ - "setenv storagetype mmc;" \ - "setenv storagedev ${mmcdev}:${mmcpart};" \ - "if run loadscript; then " \ - "run bootscript; " \ - "fi; " \ - "fi;\0" \ - "mmcboot=" \ - "if run mmc_config; then " \ - "setenv storagetype mmc;" \ - "setenv storagedev ${mmcdev}:${mmcpart};" \ - "if run loadkernel; then " \ - "if run loadfdt; then " \ - "run storagebootcmd;" \ - "fi; " \ - "fi; " \ - "fi;\0" \ - "sdbootscript=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; " \ - "run mmcbootscript\0" \ - "usbbootscript=setenv usbdev ${usbdev_def}; " \ - "setenv storagetype usb;" \ - "setenv storagedev ${usbdev}:${usbpart};" \ - "if run loadscript; then " \ - "run bootscript; " \ - "fi; " \ - "sdboot=setenv mmcdev ${mmcdev_def}; setenv mmcblk 0; run mmcboot\0" \ - "emmcbootscript=setenv mmcdev 1; setenv mmcblk 2; run mmcbootscript\0" \ - "emmcboot=setenv mmcdev 1; setenv mmcblk 2; run mmcboot\0" \ - -#define CONFIG_BOOTCOMMAND \ - "echo SD boot attempt ...; run sdbootscript; run sdboot; " \ - "echo eMMC boot attempt ...; run emmcbootscript; run emmcboot; " \ - "echo USB boot attempt ...; run usbbootscript; " - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* SPI Flash support */ - -/* FLASH and environment organization */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) - -/* MMC Config*/ -#ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -#endif - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* Uncomment to enable iMX thermal driver support */ -/*#define CONFIG_IMX_THERMAL*/ - -/* SPL */ -#include "imx7_spl.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/clearfog.h b/include/configs/clearfog.h deleted file mode 100644 index 9d20a5e..0000000 --- a/include/configs/clearfog.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Stefan Roese - */ - -#ifndef _CONFIG_CLEARFOG_H -#define _CONFIG_CLEARFOG_H - -/* - * High Level Configuration Options (easy to change) - */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* - * Commands configuration - */ - -/* - * SDIO/MMC Card Configuration - */ -#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -#define CONFIG_ENV_MIN_ENTRIES 128 - -/* Environment in MMC */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SECT_SIZE 0x200 -#define CONFIG_ENV_SIZE 0x10000 -/* - * For SD - reserve 1 LBA for MBR + 1M for u-boot image. The MMC/eMMC - * boot image starts @ LBA-0. - * As result in MMC/eMMC case it will be a 1 sector gap between u-boot - * image and environment - */ -#define CONFIG_ENV_OFFSET 0xf0000 -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* SATA support */ -#ifdef CONFIG_SCSI -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#endif - -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define RELOCATION_LIMITS_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -/* SPL */ - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI) -/* SPL related SPI defines */ -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS -#elif defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC) || defined(CONFIG_MVEBU_SPL_BOOT_DEVICE_SATA) -/* SPL related MMC defines */ -#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - -#ifdef CONFIG_MMC -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) -#else -#define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#ifdef CONFIG_USB_STORAGE -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_DEVICES_USB(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#define KERNEL_ADDR_R __stringify(0x800000) -#define FDT_ADDR_R __stringify(0x100000) -#define RAMDISK_ADDR_R __stringify(0x1800000) -#define SCRIPT_ADDR_R __stringify(0x200000) -#define PXEFILE_ADDR_R __stringify(0x300000) - -#define LOAD_ADDRESS_ENV_SETTINGS \ - "kernel_addr_r=" KERNEL_ADDR_R "\0" \ - "fdt_addr_r=" FDT_ADDR_R "\0" \ - "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ - "scriptaddr=" SCRIPT_ADDR_R "\0" \ - "pxefile_addr_r=" PXEFILE_ADDR_R "\0" - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - RELOCATION_LIMITS_ENV_SETTINGS \ - LOAD_ADDRESS_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "console=ttyS0,115200\0" \ - BOOTENV - -#endif /* CONFIG_SPL_BUILD */ - -#endif /* _CONFIG_CLEARFOG_H */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h deleted file mode 100644 index b957e9c..0000000 --- a/include/configs/cm_fx6.h +++ /dev/null @@ -1,228 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Config file for Compulab CM-FX6 board - * - * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ - * - * Author: Nikita Kiryanov - */ - -#ifndef __CONFIG_CM_FX6_H -#define __CONFIG_CM_FX6_H - -#include "mx6_common.h" - -/* Machine config */ -#define CONFIG_SYS_LITTLE_ENDIAN -#define CONFIG_MACH_TYPE 4273 - -/* MMC */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* RAM */ -#define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_2 MMDC1_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Serial console */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} - -/* SPI flash */ - -/* MTD support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_MTD -#endif - -/* Environment */ -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (768 * 1024) - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr_r=0x18000000\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdtfile=undefined\0" \ - "stdin=serial,usbkbd\0" \ - "stdout=serial,vga\0" \ - "stderr=serial,vga\0" \ - "panel=HDMI\0" \ - "autoload=no\0" \ - "uImage=uImage-cm-fx6\0" \ - "zImage=zImage-cm-fx6\0" \ - "kernel=uImage-cm-fx6\0" \ - "dtb=cm-fx6.dtb\0" \ - "console=ttymxc3,115200\0" \ - "ethprime=FEC0\0" \ - "video_hdmi=mxcfb0:dev=hdmi,1920x1080M-32@50,if=RGB32\0" \ - "video_dvi=mxcfb0:dev=dvi,1280x800M-32@50,if=RGB32\0" \ - "doboot=bootm ${kernel_addr_r}\0" \ - "doloadfdt=false\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "setboottypez=setenv kernel ${zImage};" \ - "setenv doboot bootz ${kernel_addr_r} - ${fdt_addr_r};" \ - "setenv doloadfdt true;\0" \ - "setboottypem=setenv kernel ${uImage};" \ - "setenv doboot bootm ${kernel_addr_r};" \ - "setenv doloadfdt false;\0"\ - "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ - "sataroot=/dev/sda2 rw rootwait\0" \ - "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=ubifs\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot} " \ - "${video} ${extrabootargs}\0" \ - "sataargs=setenv bootargs console=${console} root=${sataroot} " \ - "${video} ${extrabootargs}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} " \ - "${video} ${extrabootargs}\0" \ - "nandboot=if run nandloadkernel; then " \ - "run nandloadfdt;" \ - "run setboottypem;" \ - "run storagebootcmd;" \ - "run setboottypez;" \ - "run storagebootcmd;" \ - "fi;\0" \ - "run_eboot=echo Starting EBOOT ...; "\ - "mmc dev 2 && " \ - "mmc rescan && mmc read 10042000 a 400 && go 10042000\0" \ - "loadkernel=load ${storagetype} ${storagedev} ${kernel_addr_r} ${kernel};\0"\ - "loadfdt=load ${storagetype} ${storagedev} ${fdt_addr_r} ${dtb};\0" \ - "nandloadkernel=nand read ${kernel_addr_r} 0 780000;\0" \ - "nandloadfdt=nand read ${fdt_addr_r} 780000 80000;\0" \ - "setupmmcboot=setenv storagetype mmc; setenv storagedev 2;\0" \ - "setupsataboot=setenv storagetype sata; setenv storagedev 0;\0" \ - "setupnandboot=setenv storagetype nand;\0" \ - "storagebootcmd=echo Booting from ${storagetype} ...;" \ - "run ${storagetype}args; run doboot;\0" \ - "trybootk=if run loadkernel; then " \ - "if ${doloadfdt}; then " \ - "run loadfdt;" \ - "fi;" \ - "run storagebootcmd;" \ - "fi;\0" \ - "trybootsmz=" \ - "run setboottypem;" \ - "run trybootk;" \ - "run setboottypez;" \ - "run trybootk;\0" \ - "legacy_bootcmd=" \ - "run setupmmcboot;" \ - "mmc dev ${storagedev};" \ - "if mmc rescan; then " \ - "run trybootsmz;" \ - "fi;" \ - "run setupsataboot;" \ - "if sata init; then " \ - "run trybootsmz;" \ - "fi;" \ - "run setupnandboot;" \ - "run nandboot;\0" \ - "findfdt="\ - "if test $board_name = Utilite && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-utilite-pro.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; \0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(MMC, mmc, 2) \ - func(SATA, sata, 0) - -#include -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif - -/* NAND */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_ONFI_DETECTION -/* APBH DMA is required for NAND support */ -#endif - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_FEC_XCV_TYPE RGMII -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_PHY_ATHEROS -#define CONFIG_ETHPRIME "FEC0" -#define CONFIG_ARP_TIMEOUT 200UL -#define CONFIG_NET_RETRY_COUNT 5 - -/* USB */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 - -/* SATA */ -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_LBA48 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR - -/* Boot */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) -#define CONFIG_SERIAL_TAG - -/* misc */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* SPL */ -#include "imx6_spl.h" - -/* Display */ -#define CONFIG_IMX_HDMI - -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SOURCE -#define CONFIG_VIDEO_BMP_RLE8 - -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO - -/* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 - -#endif /* __CONFIG_CM_FX6_H */ diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h deleted file mode 100644 index 54f2cea..0000000 --- a/include/configs/cm_t335.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Config file for Compulab CM-T335 board - * - * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ - * - * Author: Ilya Ledvich - */ - -#ifndef __CONFIG_CM_T335_H -#define __CONFIG_CM_T335_H - -#define CONFIG_CM_T335 - -#include - -#undef CONFIG_MAX_RAM_BANK_SIZE -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ - -#define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 - -/* Clock Defines */ -#define V_OSCK 25000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#ifndef CONFIG_SPL_BUILD -#define MMCARGS \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ - "mmcrootfstype=ext4\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" - -#define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandroot=ubi0:rootfs rw\0" \ - "nandrootfstype=ubifs\0" \ - "nandargs=setenv bootargs console=${console} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} " \ - "ubi.mtd=${rootfs_name}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nboot ${loadaddr} nand0 900000; " \ - "bootm ${loadaddr}\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=82000000\0" \ - "console=ttyO0,115200n8\0" \ - "rootfs_name=rootfs\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - MMCARGS \ - NANDARGS - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" -#endif /* CONFIG_SPL_BUILD */ - -#define CONFIG_TIMESTAMP -#define CONFIG_SYS_AUTOLOAD "no" - -/* Serial console configuration */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 0 - -/* SPL */ - -/* Network. */ -#define CONFIG_PHY_ATHEROS - -/* NAND support */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#undef CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 - -#define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 -#endif - -/* GPIO pin + bank to pin ID mapping */ -#define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) - -/* Status LED */ -/* Status LED polarity is inversed, so init it in the "off" state */ - -/* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 - -#ifndef CONFIG_SPL_BUILD -/* - * Enable PCA9555 at I2C0-0x26. - * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. - */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } -#endif /* CONFIG_SPL_BUILD */ - -#endif /* __CONFIG_CM_T335_H */ - diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h deleted file mode 100644 index f9a6444..0000000 --- a/include/configs/cm_t35.h +++ /dev/null @@ -1,254 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 CompuLab, Ltd. - * Mike Rapoport - * Igor Grinberg - * - * Based on omap3_beagle.h - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * - * Configuration settings for the CompuLab CM-T35 and CM-T3730 boards - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -/* - * High Level Configuration Options - */ -#define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ - -#include /* get chip and board defs */ -#include - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* - * Size of malloc() pool - */ - /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* USB device configuration */ -#define CONFIG_USB_DEVICE -#define CONFIG_USB_TTY - -/* commands to include */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 0 -#define CONFIG_I2C_MULTI_BUS - -/* - * TWL4030 - */ - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ - -/* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=500\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nandroot=/dev/mtdblock4 rw\0" \ - "nandrootfstype=ubifs\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 2a0000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_TIMESTAMP -#define CONFIG_SYS_AUTOLOAD "no" - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */ - /* works on */ -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_ENV_ADDR 0x260000 - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Status LED */ -#define GREEN_LED_GPIO 186 /* CM-T35 Green LED is GPIO186 */ - -#define CONFIG_SPLASHIMAGE_GUARD - -/* Display Configuration */ -#define LCD_BPP LCD_COLOR16 - -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SOURCE -#define CONFIG_BMP_16BPP -#define CONFIG_SCF0403_LCD - -/* Defines for SPL */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -/* - * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: - * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT - */ -#define CONFIG_SYS_NAND_ECCPOS { 1, 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -/* - * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the - * older x-loader implementations. And move the BSS area so that it - * doesn't overlap with TEXT_BASE. - */ -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -/* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 - -#endif /* __CONFIG_H */ diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h deleted file mode 100644 index 1314cf9..0000000 --- a/include/configs/cm_t43.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * cm_t43.h - * - * Copyright (C) 2015 Compulab, Ltd. - */ - -#ifndef __CONFIG_CM_T43_H -#define __CONFIG_CM_T43_H - -#define CONFIG_CM_T43 -#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ - -#include - -/* Serial support */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM1 0x44e09000 -#if !defined(CONFIG_SPL_DM) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -/* CPSW Ethernet support */ -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_PHY_ATHEROS -#define CONFIG_SYS_RX_ETH_BUFFER 64 - -/* USB support */ -#define CONFIG_USB_XHCI_OMAP -#define CONFIG_AM437X_USB2PHY2_HOST - -/* Power */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65218 - -/* Enabling L2 Cache */ -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE 0x48242000 - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#define CONFIG_HSMMC2_8BIT - -#include -#undef CONFIG_SYS_MONITOR_LEN - -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x81200000\0" \ - "bootm_size=0x8000000\0" \ - "autoload=no\0" \ - "console=ttyO0,115200n8\0" \ - "fdtfile=am437x-sb-som-t43.dtb\0" \ - "kernel=zImage-cm-t43\0" \ - "bootscr=bootscr.img\0" \ - "emmcroot=/dev/mmcblk0p2 rw\0" \ - "emmcrootfstype=ext4 rootwait\0" \ - "emmcargs=setenv bootargs console=${console} " \ - "root=${emmcroot} " \ - "rootfstype=${emmcrootfstype}\0" \ - "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "emmcboot=echo Booting from emmc ... && " \ - "run emmcargs && " \ - "load mmc 1 ${loadaddr} ${kernel} && " \ - "load mmc 1 ${fdtaddr} ${fdtfile} && " \ - "bootz ${loadaddr} - ${fdtaddr}\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev 0; " \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "fi; " \ - "fi; " \ - "mmc dev 1; " \ - "if mmc rescan; then " \ - "run emmcboot; " \ - "fi;" - -/* SPL defines. */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -/* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 - -#endif /* __CONFIG_CM_T43_H */ diff --git a/include/configs/cm_t54.h b/include/configs/cm_t54.h deleted file mode 100644 index 2387f86..0000000 --- a/include/configs/cm_t54.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Config file for Compulab CM-T54 board - * - * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ - * - * Author: Dmitry Lifshitz - */ - -#ifndef __CONFIG_CM_T54_H -#define __CONFIG_CM_T54_H - -#define CONFIG_CM_T54 -#define CONFIG_DRAM_2G - -#define PARTS_DEFAULT - -#include - -/* EEPROM related defines */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_BUS 0 - -/* Enable SD/MMC CD and WP GPIOs */ -#define OMAP_HSMMC_USE_GPIO - -/* UART setup */ -#define CONFIG_SYS_NS16550_COM4 UART4_BASE - -/* MMC ENV related defines */ -#undef CONFIG_ENV_OFFSET -#undef CONFIG_ENV_SIZE - -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ -#define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_ENV_OFFSET 0xc0000 /* (in bytes) 768 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - -/* SATA Boot related defines */ -#define CONFIG_SPL_SATA_BOOT_DEVICE 0 -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 - -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -/* USB UHH support options */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 76 /* HSIC2 HUB #RESET */ -#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 83 /* HSIC3 ETH #RESET */ - -/* Enabled commands */ - -/* EEPROM */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define CONFIG_SYS_EEPROM_SIZE 256 - -/* USB Networking options */ - -/* - * Miscellaneous configurable options - */ -#undef CONFIG_SYS_AUTOLOAD -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_SYS_AUTOLOAD "no" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "baudrate=115200\0" \ - "bootdelay=3\0" \ - "autoload=no\0" \ - "bootscr=bootscr.img\0" \ - "fdtfile=omap5-sbc-t54.dtb\0" \ - "kernel=zImage-cm-t54\0" \ - "ramdisk=ramdisk-cm-t54.img\0" \ - "console=ttyO3\0" \ - "ramdisksize=16384\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk1p2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "root=${mmcroot} rw rootwait\0" \ - "ramroot=/dev/ram0\0" \ - "ramargs=setenv bootargs console=${console} " \ - "root=${ramroot} ramdisk_size=${ramdisksize} rw\0" \ - "mmcloadkernel=load mmc ${mmcdev} ${loadaddr} ${kernel}\0" \ - "mmcloadfdt=load mmc ${mmcdev} ${fdtaddr} ${fdtfile}\0" \ - "mmcloadramdisk=load mmc ${mmcdev} ${rdaddr} ${ramdisk}\0" \ - "mmcloadbootscript=load mmc ${mmcdev} ${loadaddr} ${bootsrc}\0" \ - "mmcbootscript=echo Running bootscript from mmc${mmcdev}...; " \ - "source ${loadaddr}\0" \ - "mmcbootlinux=echo Booting from mmc${mmcdev} ...; " \ - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ - "mmcboot=if mmc dev ${mmcdev} && mmc rescan; then " \ - "if run mmcloadbootscript; " \ - "then run mmcbootscript; " \ - "fi; " \ - "if run mmcloadkernel; then " \ - "if run mmcloadfdt; then " \ - "if run mmcloadramdisk; then " \ - "run ramargs; " \ - "run mmcbootlinux; " \ - "fi; " \ - "run mmcargs; " \ - "setenv rdaddr - ; " \ - "run mmcbootlinux; " \ - "fi; " \ - "fi; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "bootcmd=run mmcboot || setenv mmcdev 1; setenv mmcroot /dev/mmcblk0p2; run mmcboot;" - -#endif /* __CONFIG_CM_T54_H */ diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h deleted file mode 100644 index 337c875..0000000 --- a/include/configs/cobra5272.h +++ /dev/null @@ -1,336 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Sentec Cobra Board. - * - * (C) Copyright 2003 Josef Baumgartner - */ - -/* --- - * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board - * Date: 2004-03-29 - * Author: Florian Schlote - * - * For a description of configuration options please refer also to the - * general u-boot-1.x.x/README file - * --- - */ - -/* --- - * board/config.h - configuration options, board specific - * --- - */ - -#ifndef _CONFIG_COBRA5272_H -#define _CONFIG_COBRA5272_H - -/* --- - * Defines processor clock - important for correct timings concerning serial - * interface etc. - * --- - */ - -#define CONFIG_SYS_CLK 66000000 -#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ - -/* --- - * Enable use of Ethernet - * --- - */ -#define CONFIG_MCFFEC - -/* Enable Dma Timer */ -#define CONFIG_MCFTMR - -/* --- - * Define baudrate for UART1 (console output, tftp, ...) - * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud - * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command - * interface - * --- - */ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -/* --- - * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change - * timeout acc. to your needs - * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000 - * for 10 sec - * --- - */ - -#if 0 -#define CONFIG_WATCHDOG -#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */ -#endif - -/* --- - * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different - * bootloader residing in flash ('chainloading'); if you want to use - * chainloading or want to compile a u-boot binary that can be loaded into - * RAM via BDM set - * "#if 0" to "#if 1" - * You will need a first stage bootloader then, e. g. colilo or a working BDM - * cable (Background Debug Mode) - * - * Setting #if 0: u-boot will start from flash and relocate itself to RAM - * - * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE - * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000) - * - * --- - */ - -#if 0 -#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */ -#endif - -/* --- - * Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - * --- - */ - -#ifndef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_ENV_OFFSET 0x4000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR 0xffe04000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#endif - -#define LDS_BOARD_TEXT \ - . = DEFINED(env_offset) ? env_offset : .; \ - env/embedded.o(.text); - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#ifdef CONFIG_MCFFEC -# define CONFIG_MII_INIT 1 -# define CONFIG_SYS_DISCOVER_PHY -# define CONFIG_SYS_RX_ETH_BUFFER 8 -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -# define CONFIG_SYS_FEC0_PINMUX 0 -# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -# define MCFFEC_TOUT_LOOP 50000 -/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ -# ifndef CONFIG_SYS_DISCOVER_PHY -# define FECDUPLEX FULL -# define FECSPEED _100BASET -# else -# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# endif -# endif /* CONFIG_SYS_DISCOVER_PHY */ -#endif - -/* - *----------------------------------------------------------------------------- - * Define user parameters that have to be customized most likely - *----------------------------------------------------------------------------- - */ - -/*AUTOBOOT settings - booting images automatically by u-boot after power on*/ - -/* The following settings will be contained in the environment block ; if you -want to use a neutral environment all those settings can be manually set in -u-boot: 'set' command */ - -#if 0 - -#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please -enter a valid image address in flash */ - -/* User network settings */ - -#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */ -#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */ - -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address -from which user programs will be started */ - -/*---*/ - -/* - *----------------------------------------------------------------------------- - * End of user parameters to be customized - *----------------------------------------------------------------------------- - */ - -/* --- - * Defines memory range for test - * --- - */ - -#define CONFIG_SYS_MEMTEST_START 0x400 -#define CONFIG_SYS_MEMTEST_END 0x380000 - -/* --- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - * --- - */ - -/* --- - * Base register address - * --- - */ - -#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */ - -/* --- - * System Conf. Reg. & System Protection Reg. - * --- - */ - -#define CONFIG_SYS_SCR 0x0003 -#define CONFIG_SYS_SPR 0xffff - -/* --- - * Ethernet settings - * --- - */ - -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_SYS_ENET_BD_BASE 0x780000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in internal SRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* - *------------------------------------------------------------------------- - * RAM SIZE (is defined above) - *----------------------------------------------------------------------- - */ - -/* #define CONFIG_SYS_SDRAM_SIZE 16 */ - -/* - *----------------------------------------------------------------------- - */ - -#define CONFIG_SYS_FLASH_BASE 0xffe00000 - -#ifdef CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_BASE 0x20000 -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ - CF_CACR_DISD | CF_CACR_INVI | \ - CF_CACR_CEIB | CF_CACR_DCM | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Memory bank definitions - * - * Please refer also to Motorola Coldfire user manual - Chapter XXX - * - */ -#define CONFIG_SYS_BR0_PRELIM 0xFFE00201 -#define CONFIG_SYS_OR0_PRELIM 0xFFE00014 - -#define CONFIG_SYS_BR1_PRELIM 0 -#define CONFIG_SYS_OR1_PRELIM 0 - -#define CONFIG_SYS_BR2_PRELIM 0 -#define CONFIG_SYS_OR2_PRELIM 0 - -#define CONFIG_SYS_BR3_PRELIM 0 -#define CONFIG_SYS_OR3_PRELIM 0 - -#define CONFIG_SYS_BR4_PRELIM 0 -#define CONFIG_SYS_OR4_PRELIM 0 - -#define CONFIG_SYS_BR5_PRELIM 0 -#define CONFIG_SYS_OR5_PRELIM 0 - -#define CONFIG_SYS_BR6_PRELIM 0 -#define CONFIG_SYS_OR6_PRELIM 0 - -#define CONFIG_SYS_BR7_PRELIM 0x00000701 -#define CONFIG_SYS_OR7_PRELIM 0xFF00007C - -/*----------------------------------------------------------------------- - * LED config - */ -#define LED_STAT_0 0xffff /*all LEDs off*/ -#define LED_STAT_1 0xfffe -#define LED_STAT_2 0xfffd -#define LED_STAT_3 0xfffb -#define LED_STAT_4 0xfff7 -#define LED_STAT_5 0xffef -#define LED_STAT_6 0xffdf -#define LED_STAT_7 0xff00 /*all LEDs on*/ - -/*----------------------------------------------------------------------- - * Port configuration (GPIO) - */ -#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external -GPIO*/ -#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs -(1^=output, 0^=input) */ -#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */ -#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART -configuration */ -#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */ -#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */ -#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */ - -#endif /* _CONFIG_COBRA5272_H */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h deleted file mode 100644 index de94eb9..0000000 --- a/include/configs/colibri-imx6ull.h +++ /dev/null @@ -1,166 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 Toradex AG - * - * Configuration settings for the Colibri iMX6ULL module. - * - * based on colibri_imx7.h - */ - -#ifndef __COLIBRI_IMX6ULL_CONFIG_H -#define __COLIBRI_IMX6ULL_CONFIG_H - -#include "mx6_common.h" -#define CONFIG_IOMUX_LPSR - -#define PHYS_SDRAM_SIZE SZ_512M - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -/* Network */ -#define CONFIG_TFTP_TSIZE - -/* ENET1 */ -#define IMX_FEC_BASE ENET2_BASE_ADDR - -/* MMC Config */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -/* I2C configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - -#define FDT_FILE "imx6ull-colibri${variant}-${fdt_board}.dtb" - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x82100000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x81000000\0" \ - "pxefile_addr_r=0x87100000\0" \ - "ramdisk_addr_r=0x82200000\0" \ - "scriptaddr=0x87000000\0" - -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} " FDT_FILE " && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - -#define UBI_BOOTCMD \ - "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rw rootfstype=ubifs " \ - "ubi.fm_autoconvert=1\0" \ - "ubiboot=run setup; " \ - "setenv bootargs ${defargs} ${ubiargs} " \ - "${setupargs} ${vidargs}; echo Booting from NAND...; " \ - "ubi part ubi &&" \ - "ubi read ${kernel_addr_r} kernel && " \ - "ubi read ${fdt_addr_r} dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - -#define CONFIG_BOOTCOMMAND "run ubiboot; " \ - "setenv fdtfile " FDT_FILE " && run distro_bootcmd;" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include - -#define DFU_ALT_NAND_INFO "imx6ull-bcb part 0,1;u-boot1 part 0,2;u-boot2 part 0,3;u-boot-env part 0,4;ubi partubi 0,5" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ - UBI_BOOTCMD \ - "console=ttymxc0\0" \ - "defargs=user_debug=30\0" \ - "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ - "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ - "ip_dyn=yes\0" \ - "kernel_file=zImage\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ - "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ - "${board}/flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=mmc rescan && setenv interface mmc && " \ - "fatload ${interface} 0:1 ${loadaddr} " \ - "${board}/flash_blk.img && source ${loadaddr}\0" \ - "setup=setenv setupargs " \ - "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs} consoleblank=0\0" \ - "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ - "setusbupdate=usb start && setenv interface usb && " \ - "fatload ${interface} 0:1 ${loadaddr} " \ - "${board}/flash_blk.img && source ${loadaddr}\0" \ - "splashpos=m,m\0" \ - "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ - "vidargs=video=mxsfb:640x480M-16@60" - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x08000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#if defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -/* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ -#define CONFIG_SYS_NAND_BASE -1 -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -#define CONFIG_IMX_THERMAL - -#define CONFIG_USBD_HS - -/* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) -#define CONFIG_VIDEO_MXS -#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#endif - -#endif /* __COLIBRI_IMX6ULL_CONFIG_H */ diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h deleted file mode 100644 index ab98da6..0000000 --- a/include/configs/colibri-imx8x.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 Toradex - */ - -#ifndef __COLIBRI_IMX8X_H -#define __COLIBRI_IMX8X_H - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_DISPLAY_BOARDINFO_LATE - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5b010000 -#define USDHC2_BASE_ADDR 0x5b020000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -/* Networking */ -#define FEC_QUIRK_ENET_MAC - -#define CONFIG_TFTP_TSIZE - -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - -#define MEM_LAYOUT_ENV_SETTINGS \ - "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "ramdisk_addr_r=0x83800000\0" \ - "scriptaddr=0x80800000\0" - -#ifdef CONFIG_AHAB_BOOT -#define AHAB_ENV "sec_boot=yes\0" -#else -#define AHAB_ENV "sec_boot=no\0" -#endif - -/* Boot M4 */ -#define M4_BOOT_ENV \ - "m4_0_image=m4_0.bin\0" \ - "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${m4_0_image}\0" \ - "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ - -#define MFG_NAND_PARTITION "" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) -#include -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" - -#define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ - "rdinit=/linuxrc g_mass_storage.stall=0 " \ - "g_mass_storage.removable=1 g_mass_storage.idVendor=0x066F " \ - "g_mass_storage.idProduct=0x37FF " \ - "g_mass_storage.iSerialNumber=\"\" " MFG_NAND_PARTITION \ - "${vidargs} clk_ignore_unused\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffff\0" \ - "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} " \ - "${fdt_addr};\0" \ - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - AHAB_ENV \ - BOOTENV \ - CONFIG_MFG_ENV_SETTINGS \ - M4_BOOT_ENV \ - MEM_LAYOUT_ENV_SETTINGS \ - "boot_file=Image\0" \ - "console=ttyLP3 earlycon\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_file=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ - "fdtfile=fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "image=Image\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait " \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp " \ - "${vidargs}\0" \ - "nfsboot=run netargs; dhcp ${loadaddr} ${image}; tftp ${fdt_addr} " \ - "colibri-imx8x/${fdt_file}; booti ${loadaddr} - " \ - "${fdt_addr}\0" \ - "panel=NULL\0" \ - "script=boot.scr\0" \ - "update_uboot=askenv confirm Did you load u-boot-dtb.imx (y/N)?; " \ - "if test \"$confirm\" = \"y\"; then " \ - "setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt " \ - "${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 " \ - "${blkcnt}; fi\0" \ - "vidargs=video=imxdpufb5:off video=imxdpufb6:off video=imxdpufb7:off\0" - -/* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - -#define CONFIG_SYS_MEMTEST_START 0x88000000 -#define CONFIG_SYS_MEMTEST_END 0x89000000 - -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 eMMC */ -#define CONFIG_SYS_MMC_ENV_PART 1 - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_SYS_BOOTM_LEN SZ_64M /* Increase max gunzip size */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_2 0x880000000 -#define PHYS_SDRAM_1_SIZE SZ_2G /* 2 GB */ -#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */ - -/* Serial */ -#define CONFIG_BAUDRATE 115200 - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_CBSIZE SZ_2K -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 8000000 /* 8MHz */ - -#define BOOTAUX_RESERVED_MEM_BASE 0x88000000 -#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */ - -#endif /* __COLIBRI_IMX8X_H */ diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h deleted file mode 100644 index 1f2b89e..0000000 --- a/include/configs/colibri_imx6.h +++ /dev/null @@ -1,221 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2019 Toradex, Inc. - * - * Configuration settings for the Toradex Colibri iMX6 - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#undef CONFIG_DISPLAY_BOARDINFO - -#include -#include - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_MXC_I2C3_SPEED 400000 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* Network */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_TFTP_TSIZE - -/* USB Configs */ -/* Host */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -/* Client */ -#define CONFIG_USBD_HS - -/* Framebuffer and LCD */ -#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_CONSOLE_MUX -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FLASH - -#undef CONFIG_IPADDR -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#undef CONFIG_SERVERIP -#define CONFIG_SERVERIP 192.168.10.1 - -#define CONFIG_LOADADDR 0x12000000 - -#ifndef CONFIG_SPL_BUILD -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" -#else /* CONFIG_SPL_BUILD */ -#define BOOTENV -#endif /* CONFIG_SPL_BUILD */ - -#define DFU_ALT_EMMC_INFO \ - "u-boot.imx raw 0x2 0x3ff mmcpart 0;" \ - "boot part 0 1;" \ - "rootfs part 0 2;" \ - "zImage fat 0 1;" \ - "imx6dl-colibri-eval-v3.dtb fat 0 1;" \ - "imx6dl-colibri-cam-eval-v3.dtb fat 0 1" - -#define EMMC_BOOTCMD \ - "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} "\ - "rw,noatime rootfstype=ext4 " \ - "rootwait\0" \ - "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ - "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ - "${vidargs}; echo Booting from internal eMMC chip...; " \ - "run emmcdtbload; load mmc ${emmcdev}:${emmcbootpart} " \ - "${kernel_addr_r} ${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} ${dtbparam}\0" \ - "emmcbootpart=1\0" \ - "emmcdev=0\0" \ - "emmcdtbload=setenv dtbparam; load mmc ${emmcdev}:${emmcbootpart} " \ - "${fdt_addr_r} ${fdt_file} && " \ - "setenv dtbparam \" - ${fdt_addr_r}\" && true\0" \ - "emmcfinduuid=part uuid mmc ${mmcdev}:${emmcrootpart} uuid\0" \ - "emmcrootpart=2\0" - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x12100000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x11000000\0" \ - "pxefile_addr_r=0x17100000\0" \ - "ramdisk_addr_r=0x12200000\0" \ - "scriptaddr=0x17000000\0" - -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0:on root=/dev/nfs rw\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${setupargs} " \ - "${vidargs}; echo Booting via DHCP/TFTP/NFS...; " \ - "run nfsdtbload; dhcp ${kernel_addr_r} " \ - "&& run fdt_fixup && bootz ${kernel_addr_r} ${dtbparam}\0" \ - "nfsdtbload=setenv dtbparam; tftp ${fdt_addr_r} ${fdt_file} " \ - "&& setenv dtbparam \" - ${fdt_addr_r}\" && true\0" - -#define FDT_FILE "imx6dl-colibri-eval-v3.dtb" -#define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - "bootcmd=setenv fdtfile ${fdt_file}; run distro_bootcmd; " \ - "usb start ; " \ - "setenv stdout serial,vga ; setenv stdin serial,usbkbd\0" \ - "boot_file=zImage\0" \ - "console=ttymxc0\0" \ - "defargs=enable_wait_mode=off galcore.contiguousSize=50331648\0" \ - "dfu_alt_info=" DFU_ALT_EMMC_INFO "\0" \ - EMMC_BOOTCMD \ - "fdt_file=" FDT_FILE "\0" \ - "fdt_fixup=;\0" \ - MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ - "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ - "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ - "flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=setenv interface mmc; setenv drive 1; mmc rescan; load " \ - "${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "setup=setenv setupargs fec_mac=${ethaddr} " \ - "consoleblank=0 no_console_suspend=1 console=tty1 " \ - "console=${console},${baudrate}n8\0 " \ - "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ - "setusbupdate=usb start && setenv interface usb; setenv drive 0; " \ - "load ${interface} ${drive}:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "vidargs=video=mxcfb0:dev=lcd,640x480M@60,if=RGB666 " \ - "video=mxcfb1:off fbmem=8M\0 " - -/* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 48 - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_MMC) -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 -#endif - -#define CONFIG_CMD_TIME - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h deleted file mode 100644 index c2d9829..0000000 --- a/include/configs/colibri_imx7.h +++ /dev/null @@ -1,260 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016-2018 Toradex AG - * - * Configuration settings for the Colibri iMX7 module. - * - * based on mx7dsabresd.h: - * Copyright (C) 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __COLIBRI_IMX7_CONFIG_H -#define __COLIBRI_IMX7_CONFIG_H - -#include "mx7_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -/* Network */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_TFTP_TSIZE - -/* ENET1 */ -#define IMX_FEC_BASE ENET_IPS_BASE_ADDR - -/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#elif CONFIG_TARGET_COLIBRI_IMX7_EMMC -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#endif - -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - -#ifndef PARTS_DEFAULT -/* Define the default GPT table for eMMC */ -#define PARTS_DEFAULT \ - /* Android partitions */ \ - "partitions_android=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=boot,start=1M,size=32M,uuid=${uuid_gpt_boot};" \ - "name=environment,size=4M,uuid=${uuid_gpt_environment};" \ - "name=recovery,size=16M,uuid=${uuid_gpt_recovery};" \ - "name=system,size=1536M,uuid=${uuid_gpt_system};" \ - "name=cache,size=512M,uuid=${uuid_gpt_cache};" \ - "name=device,size=8M,uuid=${uuid_gpt_device};" \ - "name=misc,size=4M,uuid=${uuid_gpt_misc};" \ - "name=datafooter,size=2M,uuid=${uuid_gpt_datafooter};" \ - "name=metadata,size=2M,uuid=${uuid_gpt_metadata};" \ - "name=persistdata,size=2M,uuid=${uuid_gpt_persistdata};" \ - "name=userdata,size=128M,uuid=${uuid_gpt_userdata};" \ - "name=fbmisc,size=-,uuid=${uuid_gpt_fbmisc}\0" -#endif /* PARTS_DEFAULT */ - -#define EMMC_ANDROID_BOOTCMD \ - "android_args=androidboot.storage_type=emmc\0" \ - PARTS_DEFAULT \ - "android_fdt_addr=0x83700000\0" \ - "android_mmc_dev=0\0" \ - "m4binary=rpmsg_imu_freertos.elf\0" \ - "androidboot=ext4load mmc 0:a ${loadaddr} media/0/${m4binary}; "\ - "bootaux ${loadaddr}; " \ - "setenv loadaddr 0x88000000; " \ - "setenv bootm_boot_mode sec;" \ - "setenv bootargs androidboot.serialno=${serial#} " \ - "$android_args; " \ - "part start mmc ${android_mmc_dev} boot boot_start; " \ - "part size mmc ${android_mmc_dev} boot boot_size; " \ - "mmc read ${loadaddr} ${boot_start} ${boot_size}; " \ - "part start mmc ${android_mmc_dev} environment env_start; " \ - "part size mmc ${android_mmc_dev} environment env_size; " \ - "mmc read ${android_fdt_addr} ${env_start} ${env_size}; " \ - "bootm ${loadaddr} ${loadaddr} ${android_fdt_addr}\0 " - -#define EMMC_BOOTCMD \ - "set_emmcargs=setenv emmcargs ip=off root=PARTUUID=${uuid} ro " \ - "rootfstype=ext4 rootwait\0" \ - "emmcboot=run setup; run emmcfinduuid; run set_emmcargs; " \ - "setenv bootargs ${defargs} ${emmcargs} ${setupargs} " \ - "${vidargs}; echo Booting from internal eMMC chip...; " \ - "run m4boot && " \ - "load mmc ${emmcdev}:${emmcbootpart} ${fdt_addr_r} " \ - "${soc}-colibri-emmc-${fdt_board}.dtb && " \ - "load mmc ${emmcdev}:${emmcbootpart} ${kernel_addr_r} " \ - "${boot_file} && run fdt_fixup && " \ - "bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "emmcbootpart=1\0" \ - "emmcdev=0\0" \ - "emmcfinduuid=part uuid mmc ${emmcdev}:${emmcrootpart} uuid\0" \ - "emmcrootpart=2\0" - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x82000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x81000000\0" \ - "ramdisk_addr_r=0x82100000\0" \ - "scriptaddr=0x82500000\0" - -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${soc}-colibri${variant}-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - -#define UBI_BOOTCMD \ - "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ - "ubi.fm_autoconvert=1\0" \ - "ubiboot=run setup; " \ - "setenv bootargs ${defargs} ${ubiargs} " \ - "${setupargs} ${vidargs}; echo Booting from NAND...; " \ - "ubi part ubi && run m4boot && " \ - "ubi read ${kernel_addr_r} kernel && " \ - "ubi read ${fdt_addr_r} dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - -#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) -#define CONFIG_BOOTCOMMAND "run ubiboot ; echo ; echo ubiboot failed ; " \ - "setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;" -#define MODULE_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - UBI_BOOTCMD -#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) -#define CONFIG_BOOTCOMMAND \ - "setenv fdtfile ${soc}-colibri-emmc-${fdt_board}.dtb && run distro_bootcmd;" -#define MODULE_EXTRA_ENV_SETTINGS \ - "variant=-emmc\0" \ - EMMC_BOOTCMD \ - EMMC_ANDROID_BOOTCMD -#endif - -#if defined(CONFIG_TARGET_COLIBRI_IMX7_NAND) -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#elif defined(CONFIG_TARGET_COLIBRI_IMX7_EMMC) -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#endif -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ - MODULE_EXTRA_ENV_SETTINGS \ - "boot_file=zImage\0" \ - "console=ttymxc0\0" \ - "defargs=\0" \ - "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ - "m4boot=;\0" \ - "ip_dyn=yes\0" \ - "kernel_file=zImage\0" \ - "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ - "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ - "${board}/flash_eth.img && source ${loadaddr}\0" \ - "setsdupdate=mmc rescan && setenv interface mmc && " \ - "fatload ${interface} 0:1 ${loadaddr} " \ - "${board}/flash_blk.img && source ${loadaddr}\0" \ - "setup=setenv setupargs " \ - "console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs} consoleblank=0\0" \ - "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ - "setusbupdate=usb start && setenv interface usb && " \ - "fatload ${interface} 0:1 ${loadaddr} " \ - "${board}/flash_blk.img && source ${loadaddr}\0" \ - "splashpos=m,m\0" \ - "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ - "updlevel=2\0" - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x0c000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ - -#if defined(CONFIG_ENV_IS_IN_MMC) -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 -#elif defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#endif - -#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES -#endif - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -#define CONFIG_IMX_THERMAL - -#define CONFIG_USBD_HS - -/* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -#if defined(CONFIG_VIDEO) || defined(CONFIG_DM_VIDEO) -#define CONFIG_VIDEO_MXS -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#endif - -#endif diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h deleted file mode 100644 index bc3d40e..0000000 --- a/include/configs/colibri_pxa270.h +++ /dev/null @@ -1,184 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Toradex Colibri PXA270 configuration file - * - * Copyright (C) 2010 Marek Vasut - * Copyright (C) 2015-2016 Marcel Ziswiler - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Board Configuration Options - */ -#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ -/* Avoid overwriting factory configuration block */ -#define CONFIG_BOARD_SIZE_LIMIT 0x40000 - -/* - * Environment settings - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) -#define CONFIG_BOOTCOMMAND \ - "if fatload mmc 0 0xa0000000 uImage; then " \ - "bootm 0xa0000000; " \ - "fi; " \ - "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ - "bootm 0xa0000000; " \ - "fi; " \ - "bootm 0xc0000;" -#define CONFIG_TIMESTAMP -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * Serial Console Configuration - */ - -/* - * Bootloader Components Configuration - */ - -/* I2C support */ -#ifdef CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_PXA -#define CONFIG_PXA_STD_I2C -#define CONFIG_PXA_PWR_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -/* LCD support */ -#ifdef CONFIG_LCD -#define CONFIG_PXA_LCD -#define CONFIG_PXA_VGA -#define CONFIG_LCD_LOGO -#endif - -/* - * Networking Configuration - */ -#ifdef CONFIG_CMD_NET - -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x08000000 -#define DM9000_IO (CONFIG_DM9000_BASE) -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_NET_RETRY_COUNT 10 - -#define CONFIG_BOOTP_BOOTFILESIZE -#endif - -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Clock Configuration - */ -#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ - -/* - * DRAM Map - */ -#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ -#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ - -#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 - -/* - * NOR FLASH - */ -#ifdef CONFIG_CMD_FLASH -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ -#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT - -#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) -#endif - -#define CONFIG_SYS_MONITOR_BASE 0x0 -#define CONFIG_SYS_MONITOR_LEN 0x40000 - -/* Skip factory configuration block */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) -#define CONFIG_ENV_SIZE 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x40000 - -/* - * GPIO settings - */ -#define CONFIG_SYS_GPSR0_VAL 0x00000000 -#define CONFIG_SYS_GPSR1_VAL 0x00020000 -#define CONFIG_SYS_GPSR2_VAL 0x0002c000 -#define CONFIG_SYS_GPSR3_VAL 0x00000000 - -#define CONFIG_SYS_GPCR0_VAL 0x00000000 -#define CONFIG_SYS_GPCR1_VAL 0x00000000 -#define CONFIG_SYS_GPCR2_VAL 0x00000000 -#define CONFIG_SYS_GPCR3_VAL 0x00000000 - -#define CONFIG_SYS_GPDR0_VAL 0xc8008000 -#define CONFIG_SYS_GPDR1_VAL 0xfc02a981 -#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff -#define CONFIG_SYS_GPDR3_VAL 0x0061e804 - -#define CONFIG_SYS_GAFR0_L_VAL 0x80100000 -#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 -#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a -#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 -#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa -#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 -#define CONFIG_SYS_GAFR3_L_VAL 0x54000310 -#define CONFIG_SYS_GAFR3_U_VAL 0x00005401 - -#define CONFIG_SYS_PSSR_VAL 0x30 - -/* - * Clock settings - */ -#define CONFIG_SYS_CKEN 0x00500240 -#define CONFIG_SYS_CCCR 0x02000290 - -/* - * Memory settings - */ -#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 -#define CONFIG_SYS_MSC1_VAL 0x9ee1f994 -#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 -#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 -#define CONFIG_SYS_MDREFR_VAL 0x2003a031 -#define CONFIG_SYS_MDMRS_VAL 0x00220022 -#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 -#define CONFIG_SYS_SXCNFG_VAL 0x40044004 - -/* - * PCMCIA and CF Interfaces - */ -#define CONFIG_SYS_MECR_VAL 0x00000000 -#define CONFIG_SYS_MCMEM0_VAL 0x00028307 -#define CONFIG_SYS_MCMEM1_VAL 0x00014307 -#define CONFIG_SYS_MCATT0_VAL 0x00038787 -#define CONFIG_SYS_MCATT1_VAL 0x0001c787 -#define CONFIG_SYS_MCIO0_VAL 0x0002830f -#define CONFIG_SYS_MCIO1_VAL 0x0001430f - -#include "pxa-common.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h deleted file mode 100644 index cd7e168..0000000 --- a/include/configs/colibri_t20.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Lucas Stach - * - * Configuration settings for the Toradex Colibri T20 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_SDIO1 -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_TEGRA2 - -/* General networking support */ -#define CONFIG_TFTP_TSIZE - -/* LCD support */ -#define CONFIG_LCD_LOGO - -/* NAND support */ -#define CONFIG_TEGRA_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment in NAND, 64K is a bit excessive but erase block is 512K anyway */ -#define CONFIG_ENV_OFFSET (SZ_2M) -#undef CONFIG_ENV_SIZE /* undef size from tegra20-common.h */ -#define CONFIG_ENV_SIZE (SZ_64K) - -#define BOARD_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" - -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_t30.h b/include/configs/colibri_t30.h deleted file mode 100644 index 8ff6433..0000000 --- a/include/configs/colibri_t30.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2013-2016 Stefan Agner - * - * Configuration settings for the Toradex Colibri T30 modules. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra30-common.h" - -/* High-level configuration options */ - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_COLIBRI_T30 - -/* Environment in eMMC, before config block at the end of 1st "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE + \ - CONFIG_TDX_CFG_BLOCK_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 - -/* General networking support */ -#define CONFIG_TFTP_TSIZE - -/* Increase console I/O buffer size */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -/* Increase arguments buffer size */ -#undef CONFIG_SYS_BARGSIZE -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Increase maximum number of arguments */ -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 32 - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h deleted file mode 100644 index da9a842..0000000 --- a/include/configs/colibri_vf.h +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015-2019 Toradex, Inc. - * - * Configuration settings for the Toradex VF50/VF61 modules. - * - * Based on vf610twr.h: - * Copyright 2013 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_SYS_FSL_DCU_LE - -#define CONFIG_SYS_DCU_ADDR DCU0_BASE_ADDR -#define DCU_LAYER_MAX_NUM 64 -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_IPADDR 192.168.10.2 -#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_SERVERIP 192.168.10.1 - -#define CONFIG_LOADADDR 0x80008000 -#define CONFIG_FDTADDR 0x84000000 - -/* We boot from the gfxRAM area of the OCRAM. */ -#define CONFIG_BOARD_SIZE_LIMIT 520192 - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x82000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x81000000\0" \ - "pxefile_addr_r=0x87100000\0" \ - "ramdisk_addr_r=0x82100000\0" \ - "scriptaddr=0x87000000\0" - -#define NFS_BOOTCMD \ - "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ - "nfsboot=run setup; " \ - "setenv bootargs ${defargs} ${nfsargs} ${mtdparts} " \ - "${setupargs} ${vidargs}; echo Booting from NFS...;" \ - "dhcp ${kernel_addr_r} && " \ - "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - -#define SD_BOOTCMD \ - "set_sdargs=setenv sdargs root=PARTUUID=${uuid} ro rootwait\0" \ - "sdboot=run setup; run sdfinduuid; run set_sdargs; " \ - "setenv bootargs ${defargs} ${sdargs} ${mtdparts} " \ - "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ - "load mmc ${sddev}:${sdbootpart} ${kernel_addr_r} ${kernel_file} && " \ - "load mmc ${sddev}:${sdbootpart} ${fdt_addr_r} " \ - "${soc}-colibri-${fdt_board}.dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "sdbootpart=1\0" \ - "sddev=0\0" \ - "sdfinduuid=part uuid mmc ${sddev}:${sdrootpart} uuid\0" \ - "sdrootpart=2\0" - - -#define UBI_BOOTCMD \ - "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ - "ubi.fm_autoconvert=1\0" \ - "ubiboot=run setup; " \ - "setenv bootargs ${defargs} ${ubiargs} ${mtdparts} " \ - "${setupargs} ${vidargs}; echo Booting from NAND...; " \ - "ubi part ubi && " \ - "ubi read ${kernel_addr_r} kernel && " \ - "ubi read ${fdt_addr_r} dtb && " \ - "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ - -#define CONFIG_BOOTCOMMAND "run ubiboot; " \ - "setenv fdtfile ${soc}-colibri-${fdt_board}.dtb && run distro_bootcmd;" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include -#undef BOOTENV_RUN_NET_USB_START -#define BOOTENV_RUN_NET_USB_START "" - -#define DFU_ALT_NAND_INFO "vf-bcb part 0,1;u-boot part 0,2;ubi part 0,4" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - BOOTENV \ - MEM_LAYOUT_ENV_SETTINGS \ - NFS_BOOTCMD \ - SD_BOOTCMD \ - UBI_BOOTCMD \ - "console=ttyLP0\0" \ - "defargs=user_debug=30\0" \ - "dfu_alt_info=" DFU_ALT_NAND_INFO "\0" \ - "fdt_board=eval-v3\0" \ - "fdt_fixup=;\0" \ - "kernel_file=zImage\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "setsdupdate=mmc rescan && set interface mmc && " \ - "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "setup=setenv setupargs console=tty1 console=${console}" \ - ",${baudrate}n8 ${memargs}\0" \ - "setupdate=run setsdupdate || run setusbupdate\0" \ - "setusbupdate=usb start && set interface usb && " \ - "fatload ${interface} 0:1 ${loadaddr} flash_blk.img && " \ - "source ${loadaddr}\0" \ - "splashpos=m,m\0" \ - "video-mode=dcufb:640x480-16@60,monitor=lcd\0" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x80010000 -#define CONFIG_SYS_MEMTEST_END 0x87C00000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical memory map */ -#define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (256 * SZ_1M) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE (64 * 2048) -#define CONFIG_ENV_RANGE (4 * 64 * 2048) -#define CONFIG_ENV_OFFSET (12 * 64 * 2048) -#endif - -/* USB Host Support */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -/* USB DFU */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) - -#endif /* __CONFIG_H */ diff --git a/include/configs/comtrend_ar5315u.h b/include/configs/comtrend_ar5315u.h deleted file mode 100644 index 1da96c1..0000000 --- a/include/configs/comtrend_ar5315u.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_ar5387un.h b/include/configs/comtrend_ar5387un.h deleted file mode 100644 index 73e6a5d..0000000 --- a/include/configs/comtrend_ar5387un.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_ct5361.h b/include/configs/comtrend_ct5361.h deleted file mode 100644 index 72f9ecb..0000000 --- a/include/configs/comtrend_ct5361.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h deleted file mode 100644 index cb88805..0000000 --- a/include/configs/comtrend_vr3032u.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_ENV_SIZE SZ_8K - -#ifdef CONFIG_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif /* CONFIG_NAND */ diff --git a/include/configs/comtrend_wap5813n.h b/include/configs/comtrend_wap5813n.h deleted file mode 100644 index b67f654..0000000 --- a/include/configs/comtrend_wap5813n.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/condor.h b/include/configs/condor.h deleted file mode 100644 index e3c146e..0000000 --- a/include/configs/condor.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/condor.h - * This file is Condor board configuration. - * - * Copyright (C) 2019 Renesas Electronics Corporation - */ - -#ifndef __CONDOR_H -#define __CONDOR_H - -#include "rcar-gen3-common.h" - -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Environment compatibility */ -#undef CONFIG_ENV_SIZE_REDUND -#undef CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_OFFSET 0x700000 - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ -#define CONFIG_SYS_CLK_FREQ 33333333u - -/* Generic Timer Definitions (use in assembler source) */ -#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ - -#endif /* __CONDOR_H */ diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h deleted file mode 100644 index 93dcad4..0000000 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Stefan Roese - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x006ef000 - -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND \ - "load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \ - "load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;" \ - "run boot" - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel-ver=4.4.0-22\0" \ - "boot=zboot 03000000 0 04000000 ${filesize}\0" \ - "upd_uboot=tftp 100000 conga/u-boot.rom;" \ - "sf probe;sf update 100000 0 800000;saveenv\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/controlcenterd.h b/include/configs/controlcenterd.h deleted file mode 100644 index 19223e2..0000000 --- a/include/configs/controlcenterd.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - * (C) Copyright 2013 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - * based on P1022DS.h - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_SDCARD -#define CONFIG_RAMBOOT_SDCARD -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_RAMBOOT_SPIFLASH -#endif - -/* High Level Configuration Options */ -#define CONFIG_CONTROLCENTERD - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_SYS_CLK_FREQ 66666600 -#define CONFIG_DDR_CLK_FREQ 66666600 - -#define CONFIG_SYS_RAMBOOT - -#ifdef CONFIG_TRAILBLAZER - -#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -/* - * Config the L2 Cache - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull -#else -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#endif -#define CONFIG_SYS_L2_SIZE (256 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#else /* CONFIG_TRAILBLAZER */ - -#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#endif /* CONFIG_TRAILBLAZER */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Memory map - * - * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable - * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable - * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable - * - * Localbus non-cacheable - * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable - * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#ifdef CONFIG_TRAILBLAZER -/* leave CCSRBAR at default, because u-boot expects it to be exactly there */ -#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT -#else -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#endif -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) - -/* - * DDR Setup - */ - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE 1024 -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_SYS_MEMTEST_START 0x00000000 -#define CONFIG_SYS_MEMTEST_END 0x3fffffff - -#ifdef CONFIG_TRAILBLAZER -#define CONFIG_SPD_EEPROM -#define SPD_EEPROM_ADDRESS 0x52 -/*#define CONFIG_FSL_DDR_INTERACTIVE*/ -#endif - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_ELBC_BASE 0xe0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE -#endif - -#define CONFIG_UART_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) -#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) - -#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ -#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ - -#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM -#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * MMC - */ -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR - -#ifndef CONFIG_TRAILBLAZER - -/* - * Video - */ -#define CONFIG_FSL_DIU_FB -#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ - -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* - * SATA - */ -#define CONFIG_LBA48 - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -/* - * Ethernet - */ - -#define CONFIG_TSECV2 - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -/* - * USB - */ - -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#endif /* CONFIG_TRAILBLAZER */ - -/* - * Environment - */ -#if defined(CONFIG_TRAILBLAZER) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#elif defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_RAMBOOT_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* - * Command line configuration. - */ - -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#ifndef CONFIG_TRAILBLAZER -/* - * Board initialisation callbacks - */ -#endif /* CONFIG_TRAILBLAZER */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_HW_WATCHDOG -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ - -#ifdef CONFIG_TRAILBLAZER -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mp_holdoff=1\0" - -#else - -#define CONFIG_HOSTNAME "controlcenterd" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ - -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS1\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=controlcenterd.dtb\0" \ - "bdev=sda3\0" - -/* these are used and NUL-terminated in env_default.h */ -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* CONFIG_TRAILBLAZER */ - -#endif diff --git a/include/configs/controlcenterdc.h b/include/configs/controlcenterdc.h deleted file mode 100644 index f6d5328..0000000 --- a/include/configs/controlcenterdc.h +++ /dev/null @@ -1,187 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Stefan Roese - * Copyright (C) 2016 Mario Six - */ - -#ifndef _CONFIG_CONTROLCENTERDC_H -#define _CONFIG_CONTROLCENTERDC_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_CUSTOMER_BOARD_SUPPORT - -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_BOARD_LATE_INIT - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ - -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -#define CONFIG_LOADADDR 1000000 - -/* - * SDIO/MMC Card Configuration - */ -#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* - * Software (bit-bang) MII driver configuration - */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -#define CONFIG_BITBANGMII_MULTI - -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (160 << 10) - -#if defined(CONFIG_SECURED_MODE_IMAGE) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) -#else -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) -#endif - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH -/* SPL related SPI defines */ -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS -#endif - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD -/* SPL related MMC defines */ -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 -#define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10) -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_HOSTNAME "ccdc" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "ccdc.img" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth1\0" \ - "consoledev=ttyS1\0" \ - "u-boot=u-boot.bin\0" \ - "bootfile_addr=1000000\0" \ - "keyprogram_addr=3000000\0" \ - "keyprogram_file=keyprogram.img\0" \ - "fdtfile=controlcenterdc.dtb\0" \ - "load=tftpboot ${loadaddr} ${u-boot}\0" \ - "mmcdev=0:2\0" \ - "update=sf probe 1:0;" \ - " sf erase 0 +${filesize};" \ - " sf write ${fileaddr} 0 ${filesize}\0" \ - "upd=run load update\0" \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" \ - "loadkeyprogram=tpm flush_keys;" \ - " mmc rescan;" \ - " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\ - " source ${keyprogram_addr}:script@1\0" \ - "gpio1=gpio@22_25\0" \ - "gpio2=A29\0" \ - "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \ - "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \ - "bootfail=for i in ${blinkseq}; do" \ - " if test $i -eq 0; then" \ - " gpio clear ${gpio1}; gpio set ${gpio2};" \ - " elif test $i -eq 1; then" \ - " gpio clear ${gpio1}; gpio clear ${gpio2};" \ - " elif test $i -eq 2; then" \ - " gpio set ${gpio1}; gpio set ${gpio2};" \ - " else;" \ - " gpio clear ${gpio1}; gpio set ${gpio2};" \ - " fi; sleep 0.12; done\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ - "console=${consoledev},${baudrate} ${othbootargs}; " \ - "tftpboot ${bootfile_addr} ${bootfile}; " \ - "bootm ${bootfile_addr}" - -#define CONFIG_MMCBOOTCOMMAND \ - "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ - "console=${consoledev},${baudrate} ${othbootargs}; " \ - "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ - "bootm ${bootfile_addr}" - -#define CONFIG_BOOTCOMMAND \ - "if env exists keyprogram; then;" \ - " setenv keyprogram; run nfsboot;" \ - " fi;" \ - " run dobootfail" - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -#endif /* _CONFIG_CONTROLCENTERDC_H */ diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h deleted file mode 100644 index 1cf5c03..0000000 --- a/include/configs/coreboot.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, Bin Meng - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -/* ATA/IDE support */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 4 -#define CONFIG_SYS_ATA_BASE_ADDR 0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 -#define CONFIG_ATAPI - -#endif /* __CONFIG_H */ diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h deleted file mode 100644 index 60e09c1..0000000 --- a/include/configs/corenet_ds.h +++ /dev/null @@ -1,616 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2012 Freescale Semiconductor, Inc. - */ - -/* - * Corenet DS style board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/freescale/common/ics307_clk.h" - -#ifdef CONFIG_RAMBOOT_PBL -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#ifdef CONFIG_NAND -#define CONFIG_RAMBOOT_NAND -#endif -#define CONFIG_BOOTSCRIPT_COPY_RAM -#else -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg -#if defined(CONFIG_TARGET_P3041DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg -#elif defined(CONFIG_TARGET_P4080DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg -#elif defined(CONFIG_TARGET_P5020DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg -#elif defined(CONFIG_TARGET_P5040DS) -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg -#endif -#endif -#endif - -#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE -/* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ - (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SPIFLASH) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) -#elif defined(CONFIG_NAND) -#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_ADDR 0xffe20000 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_ENV_IS_NOWHERE) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) -#else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR -#endif -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * Local Bus Definitions - */ - -/* Set the local bus clock 1/8 of platform clock */ -#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 - -#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_SYS_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ - | BR_PS_16 | BR_V) -#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ - | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) - -#define CONFIG_SYS_BR1_PRELIM \ - (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 - -#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ -#ifdef CONFIG_PHYS_64BIT -#define PIXIS_BASE_PHYS 0xfffdf0000ull -#else -#define PIXIS_BASE_PHYS PIXIS_BASE -#endif - -#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) -#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ - -#define PIXIS_LBMAP_SWITCH 7 -#define PIXIS_LBMAP_MASK 0xf0 -#define PIXIS_LBMAP_SHIFT 4 -#define PIXIS_LBMAP_ALTBANK 0x40 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Nand Flash */ -#ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2<> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -/* Default address of microcode for the Linux Fman driver */ -#if defined(CONFIG_SPIFLASH) -/* - * env is stored at 0x100000, sector size is 0x10000, ucode is stored after - * env, so we got 0x110000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x110000 -#elif defined(CONFIG_SDCARD) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) -#elif defined(CONFIG_NAND) -#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -/* - * Slave has no ucode locally, it can fetch this from remote. When implementing - * in two corenet boards, slave's ucode could be stored in master's memory - * space, the address can be mapped from slave TLB->slave LAW-> - * slave SRIO or PCIE outbound window->master inbound window-> - * master LAW->the ucode address in master's memory space. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_TERANETICS -#endif - -#ifdef CONFIG_PCI -#if !defined(CONFIG_DM_PCI) -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c -#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d -#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e -#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f -#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 - -#define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c -#define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d -#define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e -#define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f -#define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 - -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#ifdef CONFIG_TARGET_P4080DS -#define __USB_PHY_TYPE ulpi -#else -#define __USB_PHY_TYPE utmi -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ - "bank_intlv=cs0_cs1;" \ - "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ - "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ - "netdev=eth0\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ - "tftpflash=tftpboot $loadaddr $uboot && " \ - "protect off $ubootaddr +$filesize && " \ - "erase $ubootaddr +$filesize && " \ - "cp.b $loadaddr $ubootaddr $filesize && " \ - "protect on $ubootaddr +$filesize && " \ - "cmp.b $loadaddr $ubootaddr $filesize\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=p4080ds/ramdisk.uboot\0" \ - "fdtaddr=1e00000\0" \ - "fdtfile=p4080ds/p4080ds.dtb\0" \ - "bdev=sda3\0" - -#define CONFIG_HDBOOT \ - "setenv bootargs root=/dev/$bdev rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h deleted file mode 100644 index f2df66e..0000000 --- a/include/configs/corvus.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common board functions for siemens AT91SAM9G45 based boards - * (C) Copyright 2013 Siemens AG - * - * Based on: - * U-Boot file: include/configs/at91sam9m10g45ek.h - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires - * adapting the initial boot program. - * Since the linker has to swallow that define, we must use a pure - * hex number here! - */ - -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ -#define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 -#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* DFU class support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) -#define DFU_MANIFEST_POLL_TIMEOUT 25000 - -#define CONFIG_SYS_LOAD_ADDR ATMEL_BASE_CS6 - -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_ENV_OFFSET_REDUND 0x180000 - -#define CONFIG_BOOTCOMMAND \ - "nand read 0x70000000 0x200000 0x300000;" \ - "bootm 0x70000000" - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - SZ_4M, 0x1000) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (12 * SZ_1K) -#define CONFIG_SPL_STACK (SZ_16K) - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_BSS_MAX_SIZE (SZ_2K) - -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - -#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K -#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - -#endif diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h deleted file mode 100644 index 8070af7..0000000 --- a/include/configs/cougarcanyon2.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, Bin Meng - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (2 << 20) - -#define CONFIG_SMSC_SIO1007 - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ - "stdout=serial,vga\0" \ - "stderr=serial,vga\0" - -/* Environment configuration */ -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x5ff000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h deleted file mode 100644 index 75f677f..0000000 --- a/include/configs/crownbay.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Bin Meng - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_SMSC_LPC47M - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -/* Environment configuration */ -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/crs305-1g-4s.h b/include/configs/crs305-1g-4s.h deleted file mode 100644 index a2df69a..0000000 --- a/include/configs/crs305-1g-4s.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Stefan Roese - */ - -#ifndef _CONFIG_CRS305_1G_4S_H -#define _CONFIG_CRS305_1G_4S_H - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) /* 64 MB */ -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ - -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 - -#endif /* _CONFIG_CRS305_1G_4S_H */ diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h deleted file mode 100644 index d152f23..0000000 --- a/include/configs/cyrus.h +++ /dev/null @@ -1,468 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Based on corenet_ds.h - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) -#error Must call Cyrus CONFIG with a specific CPU enabled. -#endif - -#define CONFIG_SDCARD -#define CONFIG_FSL_SATA_V2 -#define CONFIG_PCIE3 -#define CONFIG_PCIE4 -#ifdef CONFIG_ARCH_P5020 -#define CONFIG_SYS_FSL_RAID_ENGINE -#define CONFIG_SYS_DPAA_RMAN -#endif -#define CONFIG_SYS_DPAA_PME - -/* - * Corenet DS style board configuration file - */ -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg -#if defined(CONFIG_ARCH_P5020) -#define CONFIG_SYS_CLK_FREQ 133000000 -#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg -#elif defined(CONFIG_ARCH_P5040) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg -#endif - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#define CONFIG_SYS_MMC_MAX_DEVICE 1 - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (512 * 1658) -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ -#endif - -/* test POST memory test */ -#undef CONFIG_POST -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) -#else -#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR -#endif -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull -#endif - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull -#else -#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE -#endif - -#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull -#else -#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE -#endif - -/* Set the local bus clock 1/16 of platform clock */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) - -#define CONFIG_SYS_BR0_PRELIM \ -(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) -#define CONFIG_SYS_BR1_PRELIM \ -(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) - -#define CONFIG_SYS_OR0_PRELIM 0xfff00010 -#define CONFIG_SYS_OR1_PRELIM 0xfff00010 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#else -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ -{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 -#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 -#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 - -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 - -#define CONFIG_SYS_I2C_GENERIC_MAC -#define CONFIG_SYS_I2C_MAC1_BUS 3 -#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 -#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 -#define CONFIG_SYS_I2C_MAC2_BUS 0 -#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 -#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa - -#define CONFIG_RTC_MCP79411 1 -#define CONFIG_SYS_RTC_BUS_NUM 3 -#define CONFIG_SYS_I2C_RTC_ADDR 0x6f - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ - -/* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#else -#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE -#endif -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull -#else -#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE -#endif -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -/* Default address of microcode for the Linux Fman driver */ -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 825KB (1650 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) - -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC4" -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * USB - */ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - -#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI_FSL -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_EHCI_IS_TDI - /* _VIA_CONTROL_EP */ -#endif - -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define __USB_PHY_TYPE utmi - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ -"bank_intlv=cs0_cs1;" \ -"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ -"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"fdtaddr=1e00000\0" \ -"bdev=sda3\0" - -#define CONFIG_HDBOOT \ -"setenv bootargs root=/dev/$bdev rw " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_NFSBOOTCOMMAND \ -"setenv bootargs root=/dev/nfs rw " \ -"nfsroot=$serverip:$rootpath " \ -"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ -"setenv bootargs root=/dev/ram rw " \ -"console=$consoledev,$baudrate $othbootargs;" \ -"tftp $ramdiskaddr $ramdiskfile;" \ -"tftp $loadaddr $bootfile;" \ -"tftp $fdtaddr $fdtfile;" \ -"bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h deleted file mode 100644 index 41f0813..0000000 --- a/include/configs/da850evm.h +++ /dev/null @@ -1,282 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ -/* check if direct NOR boot config is used */ -#ifndef CONFIG_DIRECT_NOR_BOOT -#define CONFIG_USE_SPIFLASH -#endif - -/* - * SoC Configuration - */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -#ifdef CONFIG_DIRECT_NOR_BOOT -#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11) -#endif - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ -#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE -#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) - -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ - DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ - DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ - DAVINCI_SYSCFG_SUSPSRC_UART2 | \ - DAVINCI_SYSCFG_SUSPSRC_EMAC | \ - DAVINCI_SYSCFG_SUSPSRC_I2C) - -/* - * PLL configuration - */ - -#define CONFIG_SYS_DA850_PLL0_PLLM 24 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 - -/* - * DDR2 memory configuration - */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ - DV_DDR_PHY_EXT_STRBEN | \ - (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ - (1 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \ - (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ - (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ - (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ - (0x3 << DV_DDR_SDCR_CL_SHIFT) | \ - (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \ - (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) - -/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 - -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ - (14 << DV_DDR_SDTMR1_RFC_SHIFT) | \ - (2 << DV_DDR_SDTMR1_RP_SHIFT) | \ - (2 << DV_DDR_SDTMR1_RCD_SHIFT) | \ - (1 << DV_DDR_SDTMR1_WR_SHIFT) | \ - (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \ - (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ - (0 << DV_DDR_SDTMR1_WTR_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ - (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ - (0 << DV_DDR_SDTMR2_XP_SHIFT) | \ - (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (17 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ - (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ - (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \ - (0 << DV_DDR_SDTMR2_CKE_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000494 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) - -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) - -#ifdef CONFIG_USE_SPIFLASH -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - -/* - * I2C Configuration - */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 -#endif - -/* - * Flash & Environment - */ -#ifdef CONFIG_NAND -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_ENV_SECT_SIZE (128 << 10) -#endif -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { \ - 24, 25, 26, 27, 28, \ - 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ - 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ - 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ - 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_LOAD - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_NAND_SELF_INIT -#endif -#endif - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -#ifdef CONFIG_USE_NOR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */ -#define CONFIG_ENV_OFFSET (SZ_1M) -#define CONFIG_ENV_SIZE (10 << 10) /* 10KB */ -#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE -#define PHYS_FLASH_SIZE (8 << 20) /* Flash size 8MB */ -#define CONFIG_SYS_MAX_FLASH_SECT ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ)\ - + 3) -#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ -#endif - -#ifdef CONFIG_USE_SPIFLASH -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_OFFSET (512 << 10) -#define CONFIG_ENV_SECT_SIZE (64 << 10) -#endif -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_SPI_FLASH_MTD -#endif -#endif - -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_BOOTCOMMAND \ - "run envboot; " \ - "run mmcboot; " - -#define DEFAULT_LINUX_BOOT_ENV \ - "loadaddr=0xc0700000\0" \ - "fdtaddr=0xc0600000\0" \ - "scriptaddr=0xc0600000\0" - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "fdtfile=da850-evm.dtb\0" \ - "boot_fdt=yes\0" \ - "boot_fit=0\0" \ - "console=ttyS2,115200n8\0" \ - "hwconfig=dsp:wake=yes" - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#if !defined(CONFIG_NAND) && \ - !defined(CONFIG_USE_NOR) && \ - !defined(CONFIG_USE_SPIFLASH) -#define CONFIG_ENV_SIZE (16 << 10) -#endif - -/* USB Configs */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -#ifndef CONFIG_DIRECT_NOR_BOOT -/* defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_STACK 0x8001ff00 -#define CONFIG_SPL_MAX_FOOTPRINT 32768 -#define CONFIG_SPL_PAD_TO 32768 -#endif - -/* Load U-Boot Image From MMC */ - -/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 - -#ifdef CONFIG_DIRECT_NOR_BOOT -#define CONFIG_SYS_INIT_SP_ADDR 0x8001ff00 -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) -#endif /* CONFIG_DIRECT_NOR_BOOT */ - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/dalmore.h b/include/configs/dalmore.h deleted file mode 100644 index e8a4e3c..0000000 --- a/include/configs/dalmore.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra114-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Dalmore" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_DALMORE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h deleted file mode 100644 index 4f99805..0000000 --- a/include/configs/dart_6ul.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Board configuration file for Variscite DART-6UL Evaluation Kit - * Copyright (C) 2019 Parthiban Nallathambi - */ -#ifndef __DART_6UL_H -#define __DART_6UL_H - -#include -#include "mx6_common.h" - -/* SPL options */ -#include "imx6_spl.h" - -/* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#endif - -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_ENET_DEV 0 - -#if (CONFIG_FEC_ENET_DEV == 0) -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "eth0" -#elif (CONFIG_FEC_ENET_DEV == 1) -#define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x3 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "eth1" -#endif -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - -/* Environment settings */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (14 * SZ_64K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) - -/* Environment in SD */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 -#define MMC_ROOTFS_DEV 0 -#define MMC_ROOTFS_PART 2 - -/* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* MMC Configs */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT - -/* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_512M - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -#define CONFIG_IMX_THERMAL - -#define ENV_MMC \ - "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ - "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ - "fitpart=1\0" \ - "bootdelay=3\0" \ - "silent=1\0" \ - "optargs=rw rootwait\0" \ - "mmcautodetect=yes\0" \ - "mmcrootfstype=ext4\0" \ - "mmcfit_name=fitImage\0" \ - "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \ - "${mmcfit_name}\0" \ - "mmcargs=setenv bootargs " \ - "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \ - "console=${console} rootfstype=${mmcrootfstype}\0" \ - "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "console=ttymxc0,115200n8\0" \ - "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ - "fit_addr=0x82000000\0" \ - ENV_MMC - -#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(DHCP, dhcp, na) - -#include -#endif /* __DART_6UL_H */ diff --git a/include/configs/db-88f6281-bp.h b/include/configs/db-88f6281-bp.h deleted file mode 100644 index 1b5541e..0000000 --- a/include/configs/db-88f6281-bp.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef _CONFIG_DB_88F6281_BP_H -#define _CONFIG_DB_88F6281_BP_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ -#define CONFIG_SYS_TCLK 166666667 -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#define CONFIG_BUILD_TARGET "u-boot.kwb" - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */ -#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 */ -#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */ -#define CONFIG_KIRKWOOD_GPIO 1 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /* Console on UART0 */ - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 20000000 /* 20Mhz */ -#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K */ -#define CONFIG_ENV_SIZE 0x01000 -#define CONFIG_ENV_OFFSET 0xC0000 - -/* - * U-Boot bootcode configuration - */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4.0 MB for malloc */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/ - -/* size in bytes reserved for initial data */ - -#include -/* There is no PHY directly connected so don't ask it for link status */ -#undef CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /* (_8M - 1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ - -/* - * SDIO/MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default location for tftp and bootm */ - -#endif /* _CONFIG_DB_88F6281_BP_H */ diff --git a/include/configs/db-88f6720.h b/include/configs/db-88f6720.h deleted file mode 100644 index 79b9ccf..0000000 --- a/include/configs/db-88f6720.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Stefan Roese - */ - -#ifndef _CONFIG_DB_88F6720_H -#define _CONFIG_DB_88F6720_H - -/* - * High Level Configuration Options (easy to change) - */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ - -/* - * Commands configuration - */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Memory layout while starting into the bin_hdr via the - * BootROM: - * - * 0x4000.4000 - 0x4003.4000 headers space (192KiB) - * 0x4000.4030 bin_hdr start address - * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) - * 0x4007.fffc BootROM stack top - * - * The address space between 0x4007.fffc and 0x400f.fff is not locked in - * L2 cache thus cannot be used. - */ - -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS - -#endif /* _CONFIG_DB_88F6720_H */ diff --git a/include/configs/db-88f6820-amc.h b/include/configs/db-88f6820-amc.h deleted file mode 100644 index 61b91dd..0000000 --- a/include/configs/db-88f6820-amc.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Stefan Roese - */ - -#ifndef _CONFIG_DB_88F6820_AMC_H -#define _CONFIG_DB_88F6820_AMC_H - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ - -/* - * Commands configuration - */ - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* NAND */ -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * - * MMC is not populated on this board. - * NAND support may be added in the future. - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH -/* SPL related SPI defines */ -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS -#endif - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 - -#endif /* _CONFIG_DB_88F6820_AMC_H */ diff --git a/include/configs/db-88f6820-gp.h b/include/configs/db-88f6820-gp.h deleted file mode 100644 index 900c962..0000000 --- a/include/configs/db-88f6820-gp.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Stefan Roese - */ - -#ifndef _CONFIG_DB_88F6820_GP_H -#define _CONFIG_DB_88F6820_GP_H - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* - * Commands configuration - */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* - * SDIO/MMC Card Configuration - */ -#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH -/* SPL related SPI defines */ -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS -#endif - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD -/* SPL related MMC defines */ -#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -#endif /* _CONFIG_DB_88F6820_GP_H */ diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h deleted file mode 100644 index 907bd0d..0000000 --- a/include/configs/db-mv784mp-gp.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014-2015 Stefan Roese - */ - -#ifndef _CONFIG_DB_MV7846MP_GP_H -#define _CONFIG_DB_MV7846MP_GP_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_DB_784MP_GP /* Board target name for DDR training */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* SATA support */ -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* NAND */ -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Memory layout while starting into the bin_hdr via the - * BootROM: - * - * 0x4000.4000 - 0x4003.4000 headers space (192KiB) - * 0x4000.4030 bin_hdr start address - * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) - * 0x4007.fffc BootROM stack top - * - * The address space between 0x4007.fffc and 0x400f.fff is not locked in - * L2 cache thus cannot be used. - */ - -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS - -/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_SPD_EEPROM 0x4e -#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ - -#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/db-xc3-24g4xg.h b/include/configs/db-xc3-24g4xg.h deleted file mode 100644 index 86d11e4..0000000 --- a/include/configs/db-xc3-24g4xg.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Stefan Roese - */ - -#ifndef _CONFIG_DB_XC3_24G4G_H -#define _CONFIG_DB_XC3_24G4G_H - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage.cfg -#define CONFIG_SYS_TCLK 200000000 /* 200MHz */ - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ - -/* NAND */ -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" -#undef CONFIG_SYS_MAXARGS -#define CONFIG_SYS_MAXARGS 96 - -#endif /* _CONFIG_DB_XC3_24G4G_H */ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h deleted file mode 100644 index 16031c1..0000000 --- a/include/configs/devkit3250.h +++ /dev/null @@ -1,190 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Embest/Timll DevKit3250 board configuration file - * - * Copyright (C) 2011-2015 Vladimir Zapolskiy - */ - -#ifndef __CONFIG_DEVKIT3250_H__ -#define __CONFIG_DEVKIT3250_H__ - -/* SoC and board defines */ -#include -#include - -#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250 - -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * Memory configurations - */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_64M -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \ - - GENERATED_GBL_DATA_SIZE) - -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */ - -/* - * DMA - */ -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_DMA_LPC32XX -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_LPC32XX -#define CONFIG_SYS_I2C_SPEED 100000 - -/* - * GPIO - */ -#define CONFIG_LPC32XX_GPIO - -/* - * SSP/SPI - */ -#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 - -/* - * Ethernet - */ -#define CONFIG_RMII -#define CONFIG_PHY_SMSC -#define CONFIG_LPC32XX_ETH -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -/* - * NOR Flash - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 -#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE -#define CONFIG_SYS_FLASH_SIZE SZ_4M - -/* - * NAND controller - */ -#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } - -/* - * NAND chip timings - */ -#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14 -#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666 -#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000 -#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000 -#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14 -#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666 -#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000 -#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000 - -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE - -/* - * USB - */ -#define CONFIG_USB_OHCI_LPC32XX -#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d - -/* - * U-Boot General Configurations - */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Pass open firmware flat tree - */ - -/* - * Environment - */ -#define CONFIG_ENV_SIZE SZ_128K -#define CONFIG_ENV_OFFSET 0x000A0000 - -#define CONFIG_BOOTCOMMAND \ - "dhcp; " \ - "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \ - "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \ - "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \ - "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \ - "bootm ${loadaddr} - ${dtbaddr}" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "ethaddr=00:01:90:00:C0:81\0" \ - "dtbaddr=0x81000000\0" \ - "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \ - "tftpdir=vladimir/oe/devkit3250\0" \ - "userargs=oops=panic\0" - -/* - * U-Boot Commands - */ - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 - -/* - * SPL specific defines - */ -/* SPL will be executed at offset 0 */ - -/* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 - -/* Use the framework and generic lib */ - -/* SPL will use serial */ - -/* SPL loads an image from NAND */ -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_DRIVERS - -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_SOFTECC - -#define CONFIG_SPL_MAX_SIZE 0x20000 -#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE - -/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000 - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE - -/* See common/spl/spl.c spl_set_header_raw_uboot() */ -#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE - -/* - * Include SoC specific configuration - */ -#include - -#endif /* __CONFIG_DEVKIT3250_H__*/ diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h deleted file mode 100644 index baf1a73..0000000 --- a/include/configs/devkit8000.h +++ /dev/null @@ -1,181 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * - * (C) Copyright 2009 - * Frederik Kriewitz - * - * Configuration settings for the DevKit8000 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT8000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ - -#define CONFIG_SPL_BSS_START_ADDR 0x80000500 /* leave space for bootargs*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -/* Physical Memory Map */ - -#include - -#define CONFIG_REVISION_TAG 1 - -/* Size of malloc() pool */ -#undef CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) - -/* Hardware drivers */ -/* DM9000 */ -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x2c000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400) -#define CONFIG_DM9000_USE_16BIT 1 -#define CONFIG_DM9000_NO_SROM 1 -#undef CONFIG_DM9000_DEBUG - -/* TWL4030 */ - -/* Board NAND Info */ -#define CONFIG_JFFS2_NAND -/* nand device jffs2 lives on */ -#define CONFIG_JFFS2_DEV "nand0" -/* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_OFFSET 0x680000 -#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */ - /* partition */ - -/* BOOTP/DHCP options */ -#define CONFIG_BOOTP_NISDOMAIN -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_TIMEOFFSET -#undef CONFIG_BOOTP_VENDOREX - -/* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "mmcdev=0\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \ - "kernelopts=rw\0" \ - "commonargs=" \ - "setenv bootargs console=${console} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay}\0" \ - "mmcargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 " \ - "rootwait " \ - "${kernelopts}\0" \ - "nandargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=/dev/mtdblock4 " \ - "rootfstype=jffs2 " \ - "${kernelopts}\0" \ - "netargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \ - "${kernelopts} " \ - "dnsip1=${dnsip} " \ - "dnsip2=${dnsip2}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - "netboot=echo Booting from network ...; " \ - "dhcp ${loadaddr}; " \ - "run netargs; " \ - "bootm ${loadaddr}\0" \ - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi\0" - -#define CONFIG_BOOTCOMMAND "run autoboot" - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 0x01000000) /* 16MB */ - -/* SRAM config */ -#define CONFIG_SYS_SRAM_START 0x40200000 -#define CONFIG_SYS_SRAM_SIZE 0x10000 - -/* Defines for SPL */ - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 - -/* SPL OS boot options */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 - -#undef CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR -#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR -#undef CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x500 /* address 0xa0000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ - -#undef CONFIG_SYS_SPL_ARGS_ADDR -#define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) - -#endif /* __CONFIG_H */ diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h deleted file mode 100644 index a8e1850..0000000 --- a/include/configs/dfi-bt700.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Stefan Roese - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#ifndef CONFIG_INTERNAL_UART -/* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED -#endif - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x006ef000 - -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND \ - "load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;" \ - "load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \ - "run boot" - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel-ver=4.4.0-24\0" \ - "boot=zboot 03000000 0 04000000 ${filesize}\0" \ - "upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;" \ - "sf probe;sf update 100000 0 800000;saveenv\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h deleted file mode 100644 index a854d0b..0000000 --- a/include/configs/dh_imx6.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * DHCOM DH-iMX6 PDK board configuration - * - * Copyright (C) 2017 Marek Vasut - */ - -#ifndef __DH_IMX6_CONFIG_H -#define __DH_IMX6_CONFIG_H - -#include - -#include "mx6_common.h" - -/* - * SPI NOR layout: - * 0x00_0000-0x00_ffff ... U-Boot SPL - * 0x01_0000-0x0f_ffff ... U-Boot - * 0x10_0000-0x10_ffff ... U-Boot env #1 - * 0x11_0000-0x11_ffff ... U-Boot env #2 - * 0x12_0000-0x1f_ffff ... UNUSED - */ - -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ -#define CONFIG_SPL_TARGET "u-boot-with-spl.imx" - -/* Miscellaneous configurable options */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_BZIP2 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) - -/* Bootcounter */ -#define CONFIG_SYS_BOOTCOUNT_BE - -/* FEC ethernet */ -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_ARP_TIMEOUT 200UL - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_MMC_ENV_DEV 2 /* 1 = SDHC3, 2 = SDHC4 (eMMC) */ - -/* SATA Configs */ -#define CONFIG_LBA48 - -/* SPI Flash Configs */ -#if defined(CONFIG_SPL_BUILD) -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD -#endif - -/* UART */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_BAUDRATE 115200 - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ - -/* USB Gadget (DFU, UMS) */ -#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB IDs */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 -#endif -#endif - -/* Watchdog */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ - "fdt_addr=0x18000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x10008000\0" \ - "fdt_addr_r=0x13000000\0" \ - "ramdisk_addr_r=0x18000000\0" \ - "scriptaddr=0x14000000\0" \ - "fdtfile=imx6q-dhcom-pdk2.dtb\0"\ - BOOTENV - -#define CONFIG_BOOTCOMMAND "run distro_bootcmd" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 2) \ - func(USB, usb, 1) \ - func(SATA, sata, 0) \ - func(DHCP, dhcp, na) - -#include -#endif - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Environment */ -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_OFFSET (1024 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#endif - -#endif /* __DH_IMX6_CONFIG_H */ diff --git a/include/configs/display5.h b/include/configs/display5.h deleted file mode 100644 index d806415..0000000 --- a/include/configs/display5.h +++ /dev/null @@ -1,363 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Falcon Mode */ -#define CONFIG_CMD_SPL -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 -#define CONFIG_CMD_SPL_WRITE_SIZE (44 * SZ_1K) - -/* Falcon Mode - MMC support */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x3F00 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS \ - (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x100 /* 128KiB */ - -/* - * display5 SPI-NOR memory layout - * - * The definition can be found in Kconfig's - * CONFIG_MTDIDS_DEFAULT and CONFIG_MTDPARTS_DEFAULT - * - * 0x000000 - 0x020000 : SPI.SPL (128KiB) - * 0x020000 - 0x120000 : SPI.u-boot (1MiB) - * 0x120000 - 0x130000 : SPI.u-boot-env1 (64KiB) - * 0x130000 - 0x140000 : SPI.u-boot-env2 (64KiB) - * 0x140000 - 0x540000 : SPI.swupdate-kernel-FIT (4MiB) - * 0x540000 - 0x1540000 : SPI.swupdate-initramfs (16MiB) - * 0x1540000 - 0x1640000 : SPI.factory (1MiB) - */ - -/* SPI Flash Configs */ -#if defined(CONFIG_SPL_BUILD) -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD -#endif - -/* Below values are "dummy" - only to avoid build break */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x150000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x10000 - -#include "imx6_spl.h" - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - -#define CONFIG_MXC_UART_BASE UART5_BASE - -/* I2C Configs */ -#define CONFIG_I2C_MULTI_BUS - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 - -#ifndef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "if run check_em_pad; then " \ - "run recovery;" \ - "else if test ${BOOT_FROM} = FACTORY; then " \ - "run factory_nfs;" \ - "else " \ - "run boot_mmc;" \ - "fi;fi" -#endif - -#define PARTS_DEFAULT \ - /* Linux partitions */ \ - "partitions=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=kernel_raw1,start=128K,size=8M,uuid=${uuid_gpt_kernel_raw1};" \ - "name=rootfs1,size=1528M,uuid=${uuid_gpt_rootfs1};" \ - "name=kernel_raw2,size=8M,uuid=${uuid_gpt_kernel_raw2};" \ - "name=rootfs2,size=512M,uuid=${uuid_gpt_rootfs2};" \ - "name=data,size=-,uuid=${uuid_gpt_data}\0" - -#define SWUPDATE_RECOVERY_PROCEDURE \ - "echo '#######################';" \ - "echo '# RECOVERY SWUupdate #';" \ - "echo '#######################';" \ - "echo '#######################';" \ - "echo '# GPT verify #';" \ - "if gpt verify mmc ${mmcdev} ${partitions}; then " \ - "echo '# OK ! #';" \ - "else " \ - "echo '# FAILED ! #';" \ - "echo '# GPT RESTORATION #';" \ - "gpt write mmc ${mmcdev} ${partitions};" \ - "fi;" \ - "echo '#######################';" \ - "setenv loadaddr_swu_initramfs 0x14000000;" \ - "setenv bootargs console=${console} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}::off root=/dev/ram rw;" \ - "sf probe;" \ - "sf read ${loadaddr} swu-kernel;" \ - "sf read ${loadaddr_swu_initramfs} swu-initramfs;" \ - "bootm ${loadaddr} ${loadaddr_swu_initramfs};reset;" - -#define SETUP_BOOTARGS \ - "run set_rootfs_part;" \ - "setenv bootargs ${bootargs} console=${console} " \ - "root=/dev/mmcblk${mmcdev}p${rootfs_part} " \ - "rootwait rootfstype=ext4 rw; " \ - "run set_kernel_part;" \ - "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ - "mmc read ${loadaddr} ${lba_start} ${fitImg_fw_sz}; " \ - "setenv fdt_conf imx6q-${board}-${display}.dtb; " - -/* All the numbers are in LBAs */ -#define __TFTP_UPDATE_KERNEL \ - "tftp_mmc_fitImg=" \ - "if test ! -n ${kernel_part}; then " \ - "setenv kernel_part ${kernel_part_active};" \ - "fi;" \ - "if tftp ${loadaddr} ${kernel_file}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "part start mmc ${mmcdev} ${kernel_part} lba_start; " \ - "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ - "; fi\0" \ - -#define TFTP_UPDATE_KERNEL \ - "setenv kernel_part ${kernel_part_active};" \ - "run tftp_mmc_fitImg;" \ - "setenv kernel_part ${kernel_part_backup};" \ - "run tftp_mmc_fitImg;" \ - -#define __TFTP_UPDATE_ROOTFS \ - "tftp_mmc_rootfs=" \ - "if test ! -n ${rootfs_part}; then " \ - "setenv rootfs_part ${rootfs_part_active};" \ - "fi;" \ - "if tftp ${loadaddr} ${rootfs_file}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "part start mmc ${mmcdev} ${rootfs_part} lba_start; " \ - "mmc write ${loadaddr} ${lba_start} ${fw_sz}; " \ - "; fi\0" \ - -#define TFTP_UPDATE_ROOTFS \ - "setenv rootfs_part ${rootfs_part_active};" \ - "run tftp_mmc_rootfs;" \ - "run tftp_mmc_rootfs_bkp;" \ - - -#define TFTP_UPDATE_RECOVERY_SWU_KERNEL \ - "tftp_sf_fitImg_SWU=" \ - "if tftp ${loadaddr} ${kernel_file}; then " \ - "sf probe;" \ - "sf erase swu-kernel +${filesize};" \ - "sf write ${loadaddr} swu-kernel ${filesize};" \ - "; fi\0" \ - -#define TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ - "swu_initramfs_file=swupdate-image-display5.ext4.gz.u-boot\0" \ - "tftp_sf_initramfs_SWU=" \ - "if tftp ${loadaddr} ${swu_initramfs_file}; then " \ - "sf probe;" \ - "sf erase swu-initramfs +${filesize};" \ - "sf write ${loadaddr} swu-initramfs ${filesize};" \ - "; fi\0" \ - -#define TFTP_UPDATE_BOOTLOADER \ - "ubootfile=u-boot.img\0" \ - "ubootfileSPL=SPL\0" \ - "tftp_sf_uboot=" \ - "if tftp ${loadaddr} ${ubootfile}; then " \ - "sf probe;" \ - "sf erase u-boot +${filesize};" \ - "sf write ${loadaddr} u-boot ${filesize}" \ - "; fi\0" \ - "tftp_sf_SPL=" \ - "if tftp ${loadaddr} ${ubootfileSPL}; then " \ - "sf probe;" \ - "setexpr uboot_SPL_size ${filesize} + 0x400;" \ - "sf erase 0x0 +${uboot_SPL_size};" \ - "sf write ${loadaddr} 0x400 ${filesize};" \ - "fi\0" \ - -#define TFTP_UPDATE_SPINOR \ - "spinorfile=core-image-lwn-display5.spinor\0" \ - "spinorsize=0x2000000\0" \ - "tftp_sf_img=" \ - "if tftp ${loadaddr} ${spinorfile}; then " \ - "sf probe;" \ - "sf erase 0x0 ${spinorsize};" \ - "sf write ${loadaddr} 0x0 ${filesize};" \ - "fi\0" \ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - PARTS_DEFAULT \ - "gpio_recovery=93\0" \ - "check_em_pad=gpio input ${gpio_recovery};test $? -eq 0;\0" \ - "display=tianma-tm070-800x480\0" \ - "board=display5\0" \ - "mmcdev=0\0" \ - "altbootcmd=run recovery\0" \ - "bootdelay=1\0" \ - "baudrate=115200\0" \ - "bootcmd=" CONFIG_BOOTCOMMAND "\0" \ - "ethact=FEC\0" \ - "netdev=eth0\0" \ - "boot_os=y\0" \ - "hostname=display5\0" \ - "loadaddr=0x12000000\0" \ - "fdtaddr=0x12800000\0" \ - "console=ttymxc4,115200 quiet cma=256M\0" \ - "fdtfile=imx6q-display5.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_file=fitImage\0" \ - "fitImg_fw_sz=0x2200\0" \ - "up=run tftp_sf_SPL; run tftp_sf_uboot\0" \ - "download_kernel=" \ - "tftpboot ${loadaddr} ${kernel_file};\0" \ - "factory_nfs=" \ - "setenv ipaddr 192.168.1.102;" \ - "setenv gatewayip 192.168.1.1;" \ - "setenv netmask 255.255.255.0;" \ - "setenv serverip 192.168.1.2;" \ - "echo BOOT: FACTORY (LEG);" \ - "run boot_nfs\0" \ - "boot_swu_recovery=" SWUPDATE_RECOVERY_PROCEDURE "\0" \ - "recovery=" \ - "echo BOOT: RECOVERY: SWU;" \ - "run boot_swu_recovery\0" \ - "boot_tftp=" \ - "if run download_kernel; then " \ - "setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rootwait;" \ - "bootm ${loadaddr} - ${fdtaddr};reset;" \ - "fi\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}:eth0:on" \ - "\0" \ - "nfsargs=setenv bootargs " \ - "root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},nolock,nfsvers=3" \ - "\0" \ - "rootpath=/srv/tftp/DISP5/rootfs\0" \ - "boot_nfs=" \ - "if run download_kernel; then " \ - "run nfsargs;" \ - "run addip;" \ - "setenv bootargs ${bootargs} console=${console};" \ - "setenv fdt_conf imx6q-${board}-${display}.dtb; " \ - "bootm ${loadaddr}#conf@${fdt_conf};reset;" \ - "fi\0" \ - "falcon_setup=" \ - "if mmc dev ${mmcdev}; then " \ - SETUP_BOOTARGS \ - "spl export fdt ${loadaddr}#conf@${fdt_conf};" \ - "setexpr fw_sz ${fdtargslen} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${fdtargsaddr} " \ - __stringify(CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR)" ${fw_sz}; " \ - "fi\0" \ - "boot_mmc=" \ - "if mmc dev ${mmcdev}; then " \ - SETUP_BOOTARGS \ - "bootm ${loadaddr}#conf@${fdt_conf};reset;" \ - "fi\0" \ - "set_kernel_part=" \ - "if test ${BOOT_FROM} = ACTIVE; then " \ - "setenv kernel_part ${kernel_part_active};" \ - "echo BOOT: ACTIVE;" \ - "else if test ${BOOT_FROM} = BACKUP; then " \ - "setenv kernel_part ${kernel_part_backup};" \ - "echo BOOT: BACKUP;" \ - "else " \ - "run recovery;" \ - "fi;fi\0" \ - "set_rootfs_part=" \ - "if test ${BOOT_FROM} = ACTIVE; then " \ - "setenv rootfs_part ${rootfs_part_active};" \ - "else if test ${BOOT_FROM} = BACKUP; then " \ - "setenv rootfs_part ${rootfs_part_backup};" \ - "else " \ - "run recovery;" \ - "fi;fi\0" \ - "BOOT_FROM=ACTIVE\0" \ - TFTP_UPDATE_BOOTLOADER \ - TFTP_UPDATE_SPINOR \ - "kernel_part_active=1\0" \ - "kernel_part_backup=3\0" \ - __TFTP_UPDATE_KERNEL \ - "rootfs_part_active=2\0" \ - "rootfs_part_backup=4\0" \ - "rootfs_file=core-image-lwn-display5.ext4\0" \ - "rootfs_file_backup=core-image-lwn-backup-display5.ext4\0" \ - __TFTP_UPDATE_ROOTFS \ - "tftp_mmc_rootfs_bkp=" \ - "setenv rootfs_part ${rootfs_part_backup};" \ - "setenv rootfs_file ${rootfs_file_backup};" \ - "run tftp_mmc_rootfs\0" \ - TFTP_UPDATE_RECOVERY_SWU_KERNEL \ - TFTP_UPDATE_RECOVERY_SWU_INITRAMFS \ - "\0" \ - -/* Miscellaneous configurable options */ -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 2048 - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_STANDALONE_LOAD_ADDR 0x10001000 -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM - -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Watchdog */ -#if defined(CONFIG_SPL_BUILD) -#undef CONFIG_WDT -#undef CONFIG_WATCHDOG -#define CONFIG_HW_WATCHDOG -#endif - -/* ENV config */ -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE (SZ_64K) -/* The 0x120000 value corresponds to above SPI-NOR memory MAP */ -#define CONFIG_ENV_OFFSET (0x120000) -#define CONFIG_ENV_SECT_SIZE (SZ_64K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#endif - -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#endif /* __CONFIG_H */ diff --git a/include/configs/dns325.h b/include/configs/dns325.h deleted file mode 100644 index f72ee90..0000000 --- a/include/configs/dns325.h +++ /dev/null @@ -1,118 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Stefan Herbrechtsmeier - * - * Based on Kirkwood support: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -#ifndef _CONFIG_DNS325_H -#define _CONFIG_DNS325_H - -/* - * Machine number definition - */ -#define CONFIG_MACH_TYPE MACH_TYPE_DNS325 - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Remove or override few declarations from mv-common.h */ - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_NETCONSOLE -#endif - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif - -/* - * Enable GPI0 support - */ -#define CONFIG_KIRKWOOD_GPIO - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128KB */ -#endif - -#define CONFIG_ENV_SIZE 0x20000 /* 128KB */ -#define CONFIG_ENV_ADDR 0xe0000 -#define CONFIG_ENV_OFFSET 0xe0000 /* env starts here */ - -/* - * Default environment variables - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "loadaddr=0x800000\0" \ - "autoload=no\0" \ - "console=ttyS0,115200\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "optargs=\0" \ - "bootenv=uEnv.txt\0" \ - "importbootenv=echo Importing environment ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loadbootenv=fatload usb 0 ${loadaddr} ${bootenv}\0" \ - "setbootargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "${mtdparts} " \ - "root=${bootenvroot} " \ - "rootfstype=${bootenvrootfstype}\0" \ - "subbootcmd=run setbootargs; " \ - "if run bootenvloadimage; then " \ - "bootm ${loadaddr};" \ - "fi;\0" \ - "nandroot=ubi0:rootfs ubi.mtd=rootfs\0" \ - "nandrootfstype=ubifs\0" \ - "nandloadimage=nand read ${loadaddr} kernel\0" \ - "setnandbootenv=echo Booting from nand ...; " \ - "setenv bootenvroot ${nandroot}; " \ - "setenv bootenvrootfstype ${nandrootfstype}; " \ - "setenv bootenvloadimage ${nandloadimage}\0" - -#define CONFIG_BOOTCOMMAND \ - "if test -n ${bootenv} && usb start; then " \ - "if run loadbootenv; then " \ - "echo Loaded environment ${bootenv} from usb;" \ - "run importbootenv;" \ - "fi;" \ - "if test -n ${bootenvcmd}; then " \ - "echo Running bootenvcmd ...;" \ - "run bootenvcmd;" \ - "fi;" \ - "fi;" \ - "run setnandbootenv subbootcmd;" - -#endif /* _CONFIG_DNS325_H */ diff --git a/include/configs/dockstar.h b/include/configs/dockstar.h deleted file mode 100644 index f339788..0000000 --- a/include/configs/dockstar.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Eric C. Cooper - * - * Based on sheevaplug.h originally written by - * Prafulla Wadaskar - * (C) Copyright 2009 - * Marvell Semiconductor - */ - -#ifndef _CONFIG_DOCKSTAR_H -#define _CONFIG_DOCKSTAR_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x80000 -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:root; " \ - "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x1100000 ${initrd}; " \ - "bootm 0x800000 0x1100000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "kernel=/boot/uImage\0" \ - "initrd=/boot/uInitrd\0" \ - "bootargs_root=ubi.mtd=1 root=ubi0:root rootfstype=ubifs ro\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - -/* - * File system - */ - -#endif /* _CONFIG_DOCKSTAR_H */ diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h deleted file mode 100644 index 3487b8a..0000000 --- a/include/configs/dra7xx_evm.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Texas Instruments Incorporated. - * Lokesh Vutla - * - * Configuration settings for the TI DRA7XX board. - * See ti_omap5_common.h for omap5 common settings. - */ - -#ifndef __CONFIG_DRA7XX_EVM_H -#define __CONFIG_DRA7XX_EVM_H - -#include - -#define CONFIG_IODELAY_RECALIBRATION - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED 0x80000000 - -#ifndef CONFIG_QSPI_BOOT -/* MMC ENV related defines */ -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#endif - -#if (CONFIG_CONS_INDEX == 1) -#define CONSOLEDEV "ttyS0" -#elif (CONFIG_CONS_INDEX == 3) -#define CONSOLEDEV "ttyS2" -#endif -#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ -#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ - -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -#define CONFIG_SYS_OMAP_ABE_SYSCK - -#ifndef CONFIG_SPL_BUILD -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_QSPI -#endif - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_CMD_BOOTD -#ifdef CONFIG_SPL_DFU -#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_RAM -#endif -#endif - -#include - -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - -/* CPSW Ethernet */ -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_PHY_TI - -/* - * Default to using SPI for environment, etc. - * 0x000000 - 0x040000 : QSPI.SPL (256KiB) - * 0x040000 - 0x140000 : QSPI.u-boot (1MiB) - * 0x140000 - 0x1C0000 : QSPI.u-boot-spl-os (512KiB) - * 0x1C0000 - 0x1D0000 : QSPI.u-boot-env (64KiB) - * 0x1D0000 - 0x1E0000 : QSPI.u-boot-env.backup1 (64KiB) - * 0x1E0000 - 0x9E0000 : QSPI.kernel (8MiB) - * 0x9E0000 - 0x2000000 : USERLAND - */ -#define CONFIG_SYS_SPI_KERNEL_OFFS 0x1E0000 -#define CONFIG_SYS_SPI_ARGS_OFFS 0x140000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 -#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64 KB sectors */ -#define CONFIG_ENV_OFFSET 0x1C0000 -#define CONFIG_ENV_OFFSET_REDUND 0x1D0000 -#endif - -/* SPI SPL */ - -/* USB xHCI HOST */ -#define CONFIG_USB_XHCI_OMAP - -#define CONFIG_OMAP_USB2PHY2_HOST - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT - -/* NAND support */ -#ifdef CONFIG_NAND -/* NAND: device related configs */ -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -/* NAND: driver related configs */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00140000 -/* NAND: SPL related configs */ -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif -#endif /* !CONFIG_NAND */ - -/* Parallel NOR Support */ -#if defined(CONFIG_NOR) -/* NOR: device related configs */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_SIZE (64 * 1024 * 1024) /* 64 MB */ -/* #define CONFIG_INIT_IGNORE_ERROR */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BASE (0x08000000) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -/* Reduce SPL size by removing unlikey targets */ -#ifdef CONFIG_NOR_BOOT -#define CONFIG_ENV_SECT_SIZE (128 * 1024) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x001c0000 -#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 -#endif -#endif /* NOR support */ - -#endif /* __CONFIG_DRA7XX_EVM_H */ diff --git a/include/configs/draak.h b/include/configs/draak.h deleted file mode 100644 index 9a8d6a4..0000000 --- a/include/configs/draak.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/draak.h - * This file is Draak board configuration. - * - * Copyright (C) 2015 Renesas Electronics Corporation - */ - -#ifndef __DRAAK_H -#define __DRAAK_H - -#include "rcar-gen3-common.h" - -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Generic Timer Definitions (use in assembler source) */ -#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_SYS_FLASH_BANKS_LIST { 0x08000000 } -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -#endif /* __DRAAK_H */ diff --git a/include/configs/draco.h b/include/configs/draco.h deleted file mode 100644 index ffeb398..0000000 --- a/include/configs/draco.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_DRACO_H -#define __CONFIG_DRACO_H - -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_DRACO - -#include "siemens-am33x-common.h" - -#define DDR_PLL_FREQ 303 - -#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ -#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ - -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - "button_dfu0=27\0" \ - "led0=103,1,0\0" \ - "led1=64,0,1\0" - - /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - -#define CONFIG_PHY_SMSC - -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_OFFSET_REDUND 0x2E0000 -#define CONFIG_ENV_SIZE_REDUND 0x2000 -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - -/* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=draco\0" \ - "ubi_off=2048\0"\ - "nand_img_size=0x400000\0" \ - "optargs=\0" \ - "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 - -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ - -#define CONFIG_BOOTCOMMAND \ -"if dfubutton; then " \ - "run dfu_start; " \ - "reset; " \ -"fi;" \ -"run nand_boot;" \ -"run nand_boot_backup;" \ -"reset;" - -#else - -#define CONFIG_BOOTCOMMAND \ - "setenv autoload no; " \ - "dhcp; " \ - "if tftp 80000000 debrick.scr; then " \ - "source 80000000; " \ - "fi" -#endif -#endif /* CONFIG_SPL_BUILD */ -#endif /* ! __CONFIG_DRACO_H */ diff --git a/include/configs/dragonboard410c.h b/include/configs/dragonboard410c.h deleted file mode 100644 index bf0e031..0000000 --- a/include/configs/dragonboard410c.h +++ /dev/null @@ -1,94 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Board configuration file for Dragonboard 410C - * - * (C) Copyright 2015 Mateusz Kulikowski - */ - -#ifndef __CONFIGS_DRAGONBOARD410C_H -#define __CONFIGS_DRAGONBOARD410C_H - -#include -#include - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 0x80000000 -/* 1008 MB (the last ~30Mb are secured for TrustZone by ATF*/ -#define PHYS_SDRAM_1_SIZE 0x3da00000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* UART */ - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 19000000 - -/* Fixup - in init code we switch from device to host mode, - * it has to be done after each HCD reset */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include - -/* Does what recovery does */ -#define REFLASH(file, part) \ -"part start mmc 0 "#part" start && "\ -"part size mmc 0 "#part" size && "\ -"tftp $loadaddr "#file" && " \ -"mmc write $loadaddr $start $size && " - -#define CONFIG_ENV_REFLASH \ -"mmc dev 0 && "\ -"usb start && "\ -"dhcp && "\ -"tftp $loadaddr dragonboard/rescue/gpt_both0.bin && "\ -"mmc write $loadaddr 0 43 && " \ -"mmc rescan && "\ -REFLASH(dragonboard/rescue/NON-HLOS.bin, 1)\ -REFLASH(dragonboard/rescue/sbl1.mbn, 2)\ -REFLASH(dragonboard/rescue/rpm.mbn, 3)\ -REFLASH(dragonboard/rescue/tz.mbn, 4)\ -REFLASH(dragonboard/rescue/hyp.mbn, 5)\ -REFLASH(dragonboard/rescue/sec.dat, 6)\ -REFLASH(dragonboard/rescue/emmc_appsboot.mbn, 7)\ -REFLASH(dragonboard/u-boot.img, 8)\ -"usb stop &&"\ -"echo Reflash completed" - -/* Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "reflash="CONFIG_ENV_REFLASH"\0"\ - "loadaddr=0x81000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "linux_image=Image\0" \ - "kernel_addr_r=0x81000000\0"\ - "fdtfile=qcom/apq8016-sbc.dtb\0" \ - "fdt_addr_r=0x83000000\0"\ - "ramdisk_addr_r=0x84000000\0"\ - "scriptaddr=0x90000000\0"\ - "pxefile_addr_r=0x90100000\0"\ - BOOTENV - -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* mmc0 = emmc, mmc1 = sd */ -#define CONFIG_SYS_MMC_ENV_PART 2 /* Set env partition to BOOT2 partition */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#endif diff --git a/include/configs/dragonboard820c.h b/include/configs/dragonboard820c.h deleted file mode 100644 index a41df22..0000000 --- a/include/configs/dragonboard820c.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Board configuration file for Dragonboard 410C - * - * (C) Copyright 2017 Jorge Ramirez-Ortiz - */ - -#ifndef __CONFIGS_DRAGONBOARD820C_H -#define __CONFIGS_DRAGONBOARD820C_H - -#include -#include - -/* Physical Memory Map */ - -#define PHYS_SDRAM_SIZE 0xC0000000 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE 0x60000000 -#define PHYS_SDRAM_2 0x100000000 -#define PHYS_SDRAM_2_SIZE 0x5ea4ffff - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 19000000 - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#ifndef CONFIG_SPL_BUILD -#include -#endif - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x95000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "linux_image=uImage\0" \ - "kernel_addr_r=0x95000000\0"\ - "fdtfile=qcom/apq8096-db820c.dtb\0" \ - "fdt_addr_r=0x93000000\0"\ - "ramdisk_addr_r=0x91000000\0"\ - "scriptaddr=0x90000000\0"\ - "pxefile_addr_r=0x90100000\0"\ - BOOTENV - -#define CONFIG_ENV_SIZE 0x4000 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 64 - -#endif diff --git a/include/configs/dreamplug.h b/include/configs/dreamplug.h deleted file mode 100644 index f7f9141..0000000 --- a/include/configs/dreamplug.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Jason Cooper - * - * Based on work by: - * Marvell Semiconductor - * Written-by: Siddarth Gore - */ - -#ifndef _CONFIG_DREAMPLUG_H -#define _CONFIG_DREAMPLUG_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_MACH_TYPE MACH_TYPE_DREAMPLUG - -/* - * Commands configuration - */ - -/* - * mv-plug-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-plug-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */ -#endif - -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x1000 /* 4k */ -#define CONFIG_ENV_ADDR 0x100000 -#define CONFIG_ENV_OFFSET 0x100000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ - "${x_bootcmd_ethernet}; setenv ethact egiga1; " \ - "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "x_bootcmd_ethernet=ping 192.168.2.1\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ - "x_bootargs=console=ttyS0,115200\0" \ - "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_DREAMPLUG_H */ diff --git a/include/configs/ds109.h b/include/configs/ds109.h deleted file mode 100644 index 31abb4b..0000000 --- a/include/configs/ds109.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Jason Cooper - * - * Based on work by: - * Marvell Semiconductor - * Written-by: Siddarth Gore - */ - -#ifndef _CONFIG_DS109_H -#define _CONFIG_DS109_H - -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 527 - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ - -/* - * Commands configuration - */ -#define CONFIG_CMD_EXT2 - -/* - * mv-plug-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-plug-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64k */ -#endif - -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_ADDR 0x3d0000 -#define CONFIG_ENV_OFFSET 0x3d0000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \ - "${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "x_bootcmd_ethernet=ping 192.168.1.2\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootcmd_kernel=fatload usb 0 0x6400000 uImage\0" \ - "x_bootargs=console=ttyS0,115200\0" \ - "x_bootargs_root=root=/dev/sda2 rootdelay=10\0" \ - "ipaddr=192.168.1.5\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable one port */ -#define CONFIG_PHY_BASE_ADR 8 -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_DS109_H */ diff --git a/include/configs/ds414.h b/include/configs/ds414.h deleted file mode 100644 index 552c744..0000000 --- a/include/configs/ds414.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Stefan Roese - */ - -#ifndef _CONFIG_SYNOLOGY_DS414_H -#define _CONFIG_SYNOLOGY_DS414_H - -/* - * High Level Configuration Options (easy to change) - */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* - * Commands configuration - */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* USB/EHCI/XHCI configuration */ - -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* FIXME: broken XHCI support - * Below defines should enable support for the two rear USB3 ports. Sadly, this - * does not work because: - * - xhci-pci seems to not support DM_USB, so with that enabled it is not - * found. - * - USB init fails, controller does not respond in time */ - -#if !defined(CONFIG_USB_XHCI_HCD) -#define CONFIG_EHCI_IS_TDI -#endif - -/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Memory layout while starting into the bin_hdr via the - * BootROM: - * - * 0x4000.4000 - 0x4003.4000 headers space (192KiB) - * 0x4000.4030 bin_hdr start address - * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) - * 0x4007.fffc BootROM stack top - * - * The address space between 0x4007.fffc and 0x400f.fff is not locked in - * L2 cache thus cannot be used. - */ - -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ - -/* DS414 bus width is 32bits */ -#define CONFIG_DDR_32BIT - -/* Default Environment */ -#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm" -#define CONFIG_LOADADDR 0x80000 - -#endif /* _CONFIG_SYNOLOGY_DS414_H */ diff --git a/include/configs/duovero.h b/include/configs/duovero.h deleted file mode 100644 index dccb369..0000000 --- a/include/configs/duovero.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright: 2013 - * Gumstix, Inc - http://www.gumstix.com - * Maintainer: Ash Charles - * - * Configuration settings for the Gumstix DuoVero board. - * See omap4_common.h for OMAP4 common part - */ - -#ifndef __CONFIG_DUOVERO_H -#define __CONFIG_DUOVERO_H - -/* - * High Level Configuration Options - */ -#define CONFIG_DUOVERO -#define CONFIG_MACH_TYPE MACH_TYPE_DUOVERO - -#include - -#undef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS - -/* USB UHH support options */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 - -#define CONFIG_SYS_ENABLE_PADS_ALL - -/* GPIO */ - -/* ENV related config options */ - -#endif /* __CONFIG_DUOVERO_H */ diff --git a/include/configs/e2220-1170.h b/include/configs/e2220-1170.h deleted file mode 100644 index c636bf9..0000000 --- a/include/configs/e2220-1170.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _E2220_1170_H -#define _E2220_1170_H - -#include - -#include "tegra210-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA E2220-1170" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* _E2220_1170_H */ diff --git a/include/configs/eagle.h b/include/configs/eagle.h deleted file mode 100644 index f0e4bca..0000000 --- a/include/configs/eagle.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/eagle.h - * This file is Eagle board configuration. - * - * Copyright (C) 2015 Renesas Electronics Corporation - */ - -#ifndef __EAGLE_H -#define __EAGLE_H - -#include "rcar-gen3-common.h" - -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Environment compatibility */ -#undef CONFIG_ENV_SIZE_REDUND -#undef CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_OFFSET 0x700000 - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ -#define CONFIG_SYS_CLK_FREQ 33333333u - -/* Generic Timer Definitions (use in assembler source) */ -#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ - -#endif /* __EAGLE_H */ diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h deleted file mode 100644 index e266e1f..0000000 --- a/include/configs/eb_cpu5282.h +++ /dev/null @@ -1,254 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the BuS EB+CPU5283 boards (aka EB+MCF-EV123) - * - * (C) Copyright 2005-2009 BuS Elektronik GmbH & Co.KG - */ - -#ifndef _CONFIG_EB_CPU5282_H_ -#define _CONFIG_EB_CPU5282_H_ - -#undef CONFIG_SYS_HALT_BEFOR_RAM_JUMP - -/*----------------------------------------------------------------------* - * High Level Configuration Options (easy to change) * - *----------------------------------------------------------------------*/ - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT (0) - -#undef CONFIG_MONITOR_IS_IN_RAM /* starts uboot direct */ - -#define CONFIG_BOOTCOMMAND "printenv" - -/*----------------------------------------------------------------------* - * Options * - *----------------------------------------------------------------------*/ - -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_RESET_TO_RETRY -#define CONFIG_SPLASH_SCREEN - -#define CONFIG_HW_WATCHDOG - -#define STATUS_LED_ACTIVE 0 - -/*----------------------------------------------------------------------* - * Configuration for environment * - * Environment is in the second sector of the first 256k of flash * - *----------------------------------------------------------------------*/ - -#define CONFIG_ENV_ADDR 0xFF040000 -#define CONFIG_ENV_SECT_SIZE 0x00020000 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#define CONFIG_MCFTMR - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_LOAD_ADDR 0x20000 - -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x400000 -/*#define CONFIG_SYS_DRAM_TEST 1 */ -#undef CONFIG_SYS_DRAM_TEST - -/*----------------------------------------------------------------------* - * Clock and PLL Configuration * - *----------------------------------------------------------------------*/ -#define CONFIG_SYS_CLK 80000000 /* 8MHz * 8 */ - -/* PLL Configuration: Ext Clock * 8 (see table 9-4 of MCF user manual) */ - -#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */ -#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */ - -/*----------------------------------------------------------------------* - * Network * - *----------------------------------------------------------------------*/ - -#define CONFIG_MCFFEC -#define CONFIG_MII_INIT 1 -#define CONFIG_SYS_DISCOVER_PHY -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN - -#define CONFIG_SYS_FEC0_PINMUX 0 -#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE -#define MCFFEC_TOUT_LOOP 50000 - -#define CONFIG_OVERWRITE_ETHADDR_ONCE - -/*------------------------------------------------------------------------- - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - *-----------------------------------------------------------------------*/ - -#define CONFIG_SYS_MBAR 0x40000000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - *-----------------------------------------------------------------------*/ - -#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE0 0x00000000 -#define CONFIG_SYS_SDRAM_SIZE0 16 /* SDRAM size in MB */ - -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0 - -#define CONFIG_SYS_MONITOR_LEN 0x20000 -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE -#define CONFIG_SYS_INT_FLASH_BASE 0xF0000000 -#define CONFIG_SYS_INT_FLASH_ENABLE 0x21 - -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_ERASE_TOUT 10000000 - -#define CONFIG_SYS_FLASH_SIZE 16*1024*1024 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 - -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM) -#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ - CF_CACR_CEIB | CF_CACR_DBWE | \ - CF_CACR_EUSP) - -/*----------------------------------------------------------------------- - * Memory bank definitions - */ - -#define CONFIG_SYS_CS0_BASE 0xFF000000 -#define CONFIG_SYS_CS0_CTRL 0x00001980 -#define CONFIG_SYS_CS0_MASK 0x00FF0001 - -#define CONFIG_SYS_CS2_BASE 0xE0000000 -#define CONFIG_SYS_CS2_CTRL 0x00001980 -#define CONFIG_SYS_CS2_MASK 0x000F0001 - -#define CONFIG_SYS_CS3_BASE 0xE0100000 -#define CONFIG_SYS_CS3_CTRL 0x00001980 -#define CONFIG_SYS_CS3_MASK 0x000F0001 - -/*----------------------------------------------------------------------- - * Port configuration - */ -#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */ -#define CONFIG_SYS_PADDR 0x0000000 -#define CONFIG_SYS_PADAT 0x0000000 - -#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */ -#define CONFIG_SYS_PBDDR 0x0000000 -#define CONFIG_SYS_PBDAT 0x0000000 - -#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - -#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */ -#define CONFIG_SYS_PCDDR 0x0000000 -#define CONFIG_SYS_PCDAT 0x0000000 - -#define CONFIG_SYS_PASPAR 0x0F0F -#define CONFIG_SYS_PEHLPAR 0xC0 -#define CONFIG_SYS_PUAPAR 0x0F -#define CONFIG_SYS_DDRUA 0x05 -#define CONFIG_SYS_PJPAR 0xFF - -/*----------------------------------------------------------------------- - * I2C - */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL - -#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 -#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR - -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0 - -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_DS1338 -#define CONFIG_I2C_RTC_ADDR 0x68 -#endif - -/*----------------------------------------------------------------------- - * VIDEO configuration - */ - -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_VCXK 1 - -#define CONFIG_SYS_VCXK_DEFAULT_LINEALIGN 2 -#define CONFIG_SYS_VCXK_DOUBLEBUFFERED 1 -#define CONFIG_SYS_VCXK_BASE CONFIG_SYS_CS2_BASE - -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ACKNOWLEDGE_PIN 0x0001 - -#define CONFIG_SYS_VCXK_ENABLE_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_ENABLE_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_ENABLE_PIN 0x0002 - -#define CONFIG_SYS_VCXK_REQUEST_PORT MCFGPTB_GPTPORT -#define CONFIG_SYS_VCXK_REQUEST_DDR MCFGPTB_GPTDDR -#define CONFIG_SYS_VCXK_REQUEST_PIN 0x0004 - -#define CONFIG_SYS_VCXK_INVERT_PORT MCFGPIO_PORTE -#define CONFIG_SYS_VCXK_INVERT_DDR MCFGPIO_DDRE -#define CONFIG_SYS_VCXK_INVERT_PIN MCFGPIO_PORT2 - -#endif /* CONFIG_VIDEO */ -#endif /* _CONFIG_M5282EVB_H */ -/*---------------------------------------------------------------------*/ diff --git a/include/configs/ebisu.h b/include/configs/ebisu.h deleted file mode 100644 index 2e4974a..0000000 --- a/include/configs/ebisu.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/ebisu.h - * This file is Ebisu board configuration. - * - * Copyright (C) 2018 Renesas Electronics Corporation - */ - -#ifndef __EBISU_H -#define __EBISU_H - -#undef DEBUG - -#include "rcar-gen3-common.h" - -/* Ethernet RAVB */ -#define CONFIG_NET_MULTI -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Generic Timer Definitions (use in assembler source) */ -#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 2 -#define CONFIG_SYS_MMC_ENV_PART 2 - -#endif /* __EBISU_H */ diff --git a/include/configs/edb93xx.h b/include/configs/edb93xx.h deleted file mode 100644 index 84cbcdd..0000000 --- a/include/configs/edb93xx.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * U-Boot - Configuration file for Cirrus Logic EDB93xx boards - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef CONFIG_MK_edb9301 -#define CONFIG_EDB9301 -#elif defined(CONFIG_MK_edb9302) -#define CONFIG_EDB9302 -#elif defined(CONFIG_MK_edb9302a) -#define CONFIG_EDB9302A -#elif defined(CONFIG_MK_edb9307) -#define CONFIG_EDB9307 -#elif defined(CONFIG_MK_edb9307a) -#define CONFIG_EDB9307A -#elif defined(CONFIG_MK_edb9312) -#define CONFIG_EDB9312 -#elif defined(CONFIG_MK_edb9315) -#define CONFIG_EDB9315 -#elif defined(CONFIG_MK_edb9315a) -#define CONFIG_EDB9315A -#else -#error "no board defined" -#endif - -/* Initial environment and monitor configuration options. */ -#define CONFIG_CMDLINE_TAG 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_BOOTFILE "edb93xx.img" - -#ifdef CONFIG_EDB9301 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9301 -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#elif defined(CONFIG_EDB9302) -#define CONFIG_EP9302 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302 -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#elif defined(CONFIG_EDB9302A) -#define CONFIG_EP9302 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9302A -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#elif defined(CONFIG_EDB9307) -#define CONFIG_EP9307 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307 -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#elif defined(CONFIG_EDB9307A) -#define CONFIG_EP9307 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9307A -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#elif defined(CONFIG_EDB9312) -#define CONFIG_EP9312 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9312 -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#elif defined(CONFIG_EDB9315) -#define CONFIG_EP9315 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315 -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#elif defined(CONFIG_EDB9315A) -#define CONFIG_EP9315 -#define CONFIG_MACH_TYPE MACH_TYPE_EDB9315A -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#else -#error "no board defined" -#endif - -/* High-level configuration options */ -#define CONFIG_EP93XX 1 /* This is a Cirrus Logic 93xx SoC */ - -#define CONFIG_SYS_CLK_FREQ 14745600 /* EP93xx has a 14.7456 clock */ - -/* Monitor configuration */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ - -/* Serial port hardware configuration */ -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, \ - 115200, 230400} -#define CONFIG_SYS_SERIAL0 0x808C0000 -#define CONFIG_SYS_SERIAL1 0x808D0000 -/*#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} */ - -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} - -/* Status LED */ -/* Optional value */ - -/* Network hardware configuration */ -#define CONFIG_DRIVER_EP93XX_MAC -#define CONFIG_MII_SUPPRESS_PREAMBLE -#undef CONFIG_NETCONSOLE - -/* SDRAM configuration */ -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ - defined(CONFIG_EDB9307) || defined CONFIG_EDB9312 || \ - defined(CONFIG_EDB9315) -/* - * EDB9301/2 has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set - * the SROMLL bit on the processor, resulting in this non-contiguous memory map. - * - * The EDB9307, EDB9312, and EDB9315 have 2 banks of SDRAM consisting of - * 2x Samsung K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of - * 64 MB of SDRAM. - */ - -#define CONFIG_EDB93XX_SDCS3 - -#elif defined(CONFIG_EDB9302A) || \ - defined(CONFIG_EDB9307A) || defined(CONFIG_EDB9315A) -/* - * EDB9302a has 4 banks of SDRAM consisting of 1x Samsung K4S561632E-TC75 - * 256 Mbit SDRAM on a 16-bit data bus, for a total of 32MB of SDRAM. We set - * the SROMLL bit on the processor, resulting in this non-contiguous memory map. - * - * The EDB9307A and EDB9315A have 2 banks of SDRAM consisting of 2x Samsung - * K4S561632E-TC75 256 Mbit on a 32-bit data bus, for a total of 64 MB of SDRAM. - */ -#define CONFIG_EDB93XX_SDCS0 - -#else -#error "no SDCS configuration for this board" -#endif - -#if defined(CONFIG_EDB93XX_SDCS3) -#define CONFIG_SYS_LOAD_ADDR 0x01000000 /* Default load address */ -#define PHYS_SDRAM_1 0x00000000 -#elif defined(CONFIG_EDB93XX_SDCS0) -#define CONFIG_SYS_LOAD_ADDR 0xc1000000 /* Default load address */ -#define PHYS_SDRAM_1 0xc0000000 -#endif - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 32*1024 - GENERATED_GBL_DATA_SIZE) - -/* Must match kernel config */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) - -/* Run-time memory allocatons */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 - -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* ----------------------------------------------------------------------------- - * FLASH and environment organization - * - * The EDB9301, EDB9302(a), EDB9307a, EDB9315a have 1 bank of flash memory at - * 0x60000000 consisting of 1x Intel TE28F128J3C-150 128 Mbit flash on a 16-bit - * data bus, for a total of 16 MB of CFI-compatible flash. - * - * The EDB9307, EDB9312, and EDB9315 have 1 bank of flash memory at - * 0x60000000 consisting of 2x Micron MT28F128J3-12 128 Mbit flash on a 32-bit - * data bus, for a total of 32 MB of CFI-compatible flash. - * - * - * EDB9301/02(a)7a/15a EDB9307/12/15 - * 0x60000000 - 0x0003FFFF u-boot u-boot - * 0x60040000 - 0x0005FFFF environment #1 environment #1 - * 0x60060000 - 0x0007FFFF environment #2 environment #1 (continued) - * 0x60080000 - 0x0009FFFF unused environment #2 - * 0x600A0000 - 0x000BFFFF unused environment #2 (continued) - * 0x600C0000 - 0x00FFFFFF unused unused - * 0x61000000 - 0x01FFFFFF not present unused - */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT (256+8) - -#define PHYS_FLASH_1 CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -#define CONFIG_ENV_OVERWRITE /* Vendor params unprotected */ - -#define CONFIG_ENV_ADDR 0x60040000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) - -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_USB_OHCI_NEW -#define CONFIG_USB_OHCI_EP93XX -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ep93xx-ohci" -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x80020000 - -/* Define to disable flash configuration*/ -/* #define CONFIG_EP93XX_NO_FLASH_CFG */ - -/* Define this for indusrial rated chips */ -/* #define CONFIG_EDB93XX_INDUSTRIAL */ - -#endif /* !defined (__CONFIG_H) */ diff --git a/include/configs/edison.h b/include/configs/edison.h deleted file mode 100644 index 218b50a..0000000 --- a/include/configs/edison.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Intel Corp. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 128 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Memory */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_PHYSMEM - -#define CONFIG_SYS_STACK_SIZE (32 * 1024) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 - -/* Environment */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_ENV_SIZE (64 * 1024) -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024) - -/* RTC */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 - -#endif diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h deleted file mode 100644 index f071718..0000000 --- a/include/configs/edminiv2.h +++ /dev/null @@ -1,201 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Albert ARIBAUD - * - * Based on original Kirkwood support which is - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -#ifndef _CONFIG_EDMINIV2_H -#define _CONFIG_EDMINIV2_H - -/* - * SPL - */ - -#define CONFIG_SPL_MAX_SIZE 0x0000fff0 -#define CONFIG_SPL_STACK 0x00020000 -#define CONFIG_SPL_BSS_START_ADDR 0x00020000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x0001ffff -#define CONFIG_SYS_SPL_MALLOC_START 0x00040000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x0001ffff -#define CONFIG_SYS_UBOOT_BASE 0xfff90000 -#define CONFIG_SYS_UBOOT_START 0x00800000 - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_FEROCEON 1 /* CPU Core subversion */ -#define CONFIG_88F5182 1 /* SOC Name */ - -#include -/* - * CLKs configurations - */ - -/* - * Board-specific values for Orion5x MPP low level init: - * - MPPs 12 to 15 are SATA LEDs (mode 5) - * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for - * MPP16 to MPP19, mode 0 for others - */ - -#define ORION5X_MPP0_7 0x00000003 -#define ORION5X_MPP8_15 0x55550000 -#define ORION5X_MPP16_23 0x00005555 - -/* - * Board-specific values for Orion5x GPIO low level init: - * - GPIO3 is input (RTC interrupt) - * - GPIO16 is Power LED control (0 = on, 1 = off) - * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16) - * - GPIO18 is Power Button status (0 = Released, 1 = Pressed) - * - GPIO19 is SATA disk power toggle (toggles on 0-to-1) - * - GPIO22 is SATA disk power status () - * - GPIO23 is supply status for SATA disk () - * - GPIO24 is supply control for board (write 1 to power off) - * Last GPIO is 25, further bits are supposed to be 0. - * Enable mask has ones for INPUT, 0 for OUTPUT. - * Default is LED ON, board ON :) - */ - -#define ORION5X_GPIO_OUT_ENABLE 0xfef4f0ca -#define ORION5X_GPIO_OUT_VALUE 0x00000000 -#define ORION5X_GPIO_IN_POLARITY 0x000000d0 - -/* - * NS16550 Configuration - */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 } - -/* - * FLASH configuration - */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BASE 0xfff80000 - -/* auto boot */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ -/* - * Commands configuration - */ - -/* - * Network - */ - -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1} /* enable port 0 only */ -#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION /* don't randomize MAC */ -#define CONFIG_PHY_BASE_ADR 0x8 -#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */ -#define CONFIG_NETCONSOLE /* include NetConsole support */ -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#endif - -/* - * IDE - */ -#ifdef CONFIG_IDE -#define __io -#define CONFIG_IDE_PREINIT -/* ED Mini V has an IDE-compatible SATA connector for port 1 */ -#define CONFIG_MVSATA_IDE_USE_PORT1 -/* Needs byte-swapping for ATA data register */ -#define CONFIG_IDE_SWAP_IO -/* Data, registers and alternate blocks are at the same offset */ -#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100) -#define CONFIG_SYS_ATA_REG_OFFSET (0x0100) -#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100) -/* Each 8-bit ATA register is aligned to a 4-bytes address */ -#define CONFIG_SYS_ATA_STRIDE 4 -/* Controller supports 48-bits LBA addressing */ -#define CONFIG_LBA48 -/* A single bus, a single device */ -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -/* ATA registers base is at SATA controller base */ -#define CONFIG_SYS_ATA_BASE_ADDR ORION5X_SATA_BASE -/* ATA bus 0 is orion5x port 1 on ED Mini V2 */ -#define CONFIG_SYS_ATA_IDE0_OFFSET ORION5X_SATA_PORT1_OFFSET -/* end of IDE defines */ -#endif /* CMD_IDE */ - -/* - * Common USB/EHCI configuration - */ -#ifdef CONFIG_CMD_USB -#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE -#endif /* CONFIG_CMD_USB */ - -/* - * I2C related stuff - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE0 ORION5X_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 256) /* 256kB for malloc() */ - -/* - * Other required minimal configurations - */ - -#define CONFIG_SYS_LOAD_ADDR 0x00800000 -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x007fffff -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 - -/* Enable command line editing */ - -/* provide extensive help */ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* _CONFIG_EDMINIV2_H */ diff --git a/include/configs/efi-x86_app.h b/include/configs/efi-x86_app.h deleted file mode 100644 index 33418cf..0000000 --- a/include/configs/efi-x86_app.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Google, Inc - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#undef CONFIG_TPM_TIS_BASE_ADDRESS - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ - "stdout=vga,serial\0" \ - "stderr=vga,serial\0" - -#endif diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h deleted file mode 100644 index 1cf5c03..0000000 --- a/include/configs/efi-x86_payload.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, Bin Meng - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -/* ATA/IDE support */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 4 -#define CONFIG_SYS_ATA_BASE_ADDR 0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 -#define CONFIG_ATAPI - -#endif /* __CONFIG_H */ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h deleted file mode 100644 index fe28154..0000000 --- a/include/configs/el6x_common.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL6Q_COMMON_CONFIG_H -#define __EL6Q_COMMON_CONFIG_H - -#define CONFIG_BOARD_NAME EL6Q - -#include "mx6_common.h" - -#define CONFIG_IMX_THERMAL - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* I2C config */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -/* Commands */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_MXC_UART_BASE UART2_BASE - -#define CONFIG_BOARD_NAME EL6Q - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "board="__stringify(CONFIG_BOARD_NAME)"\0" \ - "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \ - "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \ - "console=" CONSOLE_DEV "\0" \ - "fdtfile=undefined\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_addr=0x18000000\0" \ - "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(PXE, PXE, na) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10800000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ - -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET 0x0 -#endif - -#endif /* __EL6Q_COMMON_CONFIG_H */ diff --git a/include/configs/elgin_rv1108.h b/include/configs/elgin_rv1108.h deleted file mode 100644 index aa6c4b0..0000000 --- a/include/configs/elgin_rv1108.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h deleted file mode 100644 index 8bc7a3a..0000000 --- a/include/configs/embestmx6boards.h +++ /dev/null @@ -1,150 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Eukréa Electromatique - * Author: Eric Bénard - * - * Configuration settings for the Embest RIoTboard - * - * based on mx6*sabre*.h which are : - * Copyright (C) 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __RIOTBOARD_CONFIG_H -#define __RIOTBOARD_CONFIG_H - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" - -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) - -#define CONFIG_IMX_THERMAL - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 - -#define CONFIG_PHY_ATHEROS - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_MMC) -/* RiOTboard */ -#define CONFIG_FDTFILE "imx6dl-riotboard.dtb" -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) -/* MarSBoard */ -#define CONFIG_FDTFILE "imx6q-marsboard.dtb" -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#endif - -/* Framebuffer */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -#include "mx6_common.h" - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -/* RiOTboard */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6dl-riotboard.dtb" - -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* offset 69KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* offset 69KB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* offset 69KB */ - -#endif - -/* 256M RAM (minimum), 32M uncompressed kernel, 16M compressed kernel, 1M fdt, - * 1M script, 1M pxe and the ramdisk at the end */ -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x12000000\0" \ - "fdt_addr_r=0x13000000\0" \ - "scriptaddr=0x13100000\0" \ - "pxefile_addr_r=0x13200000\0" \ - "ramdisk_addr_r=0x13300000\0" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#define CONSOLE_STDIN_SETTINGS \ - "stdin=serial\0" - -#define CONSOLE_STDOUT_SETTINGS \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONSOLE_ENV_SETTINGS \ - CONSOLE_STDIN_SETTINGS \ - CONSOLE_STDOUT_SETTINGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONSOLE_ENV_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ - "fdtfile=" CONFIG_FDTFILE "\0" \ - "finduuid=part uuid mmc 0:1 uuid\0" \ - BOOTENV - -#endif /* __RIOTBOARD_CONFIG_H */ diff --git a/include/configs/emsdp.h b/include/configs/emsdp.h deleted file mode 100644 index a872d48..0000000 --- a/include/configs/emsdp.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Synopsys, Inc. All rights reserved. - */ - -#ifndef _CONFIG_EMSDP_H_ -#define _CONFIG_EMSDP_H_ - -#include - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_SDRAM_BASE 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE SZ_16M - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_1M) - -#define CONFIG_SYS_MALLOC_LEN SZ_64K -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* - * Environment - */ -#define CONFIG_BOOTFILE "app.bin" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "upgrade_image=u-boot.bin\0" \ - "upgrade=emsdp rom unlock && " \ - "fatload mmc 0 ${loadaddr} ${upgrade_image} && " \ - "cp.b ${loadaddr} 0 ${filesize} && " \ - "dcache flush && " \ - "emsdp rom lock\0" - -#endif /* _CONFIG_EMSDP_H_ */ - diff --git a/include/configs/espresso7420.h b/include/configs/espresso7420.h deleted file mode 100644 index 5aeb009..0000000 --- a/include/configs/espresso7420.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the SAMSUNG ESPRESSO7420 board. - * Copyright (C) 2016 Samsung Electronics - * Thomas Abraham - */ - -#ifndef __CONFIG_ESPRESSO7420_H -#define __CONFIG_ESPRESSO7420_H - -#include - -#define CONFIG_BOARD_COMMON - -#define CONFIG_ESPRESSO7420 - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SPL_STACK CONFIG_IRAM_END -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_END - -/* select serial console configuration */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -/* DRAM Memory Banks */ -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ - -#endif /* __CONFIG_ESPRESSO7420_H */ diff --git a/include/configs/etamin.h b/include/configs/etamin.h deleted file mode 100644 index 726f8a5..0000000 --- a/include/configs/etamin.h +++ /dev/null @@ -1,216 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_ETAMIN_H -#define __CONFIG_ETAMIN_H - -#include "siemens-am33x-common.h" -/* NAND specific changes for etamin due to different page size */ -#undef CONFIG_SYS_NAND_PAGE_SIZE -#undef CONFIG_SYS_NAND_OOBSIZE -#undef CONFIG_SYS_NAND_BLOCK_SIZE -#undef CONFIG_SYS_NAND_ECCPOS -#undef CONFIG_SYS_NAND_U_BOOT_OFFS -#undef CONFIG_SYS_ENV_SECT_SIZE -#undef CONFIG_ENV_OFFSET -#undef CONFIG_NAND_OMAP_ECCSCHEME -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW - -#define CONFIG_ENV_OFFSET 0x980000 -#define CONFIG_SYS_ENV_SECT_SIZE (512 << 10) /* 512 KiB */ -#define CONFIG_SYS_NAND_PAGE_SIZE 4096 -#define CONFIG_SYS_NAND_OOBSIZE 224 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \ - 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ - 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \ - 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \ - 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \ - 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ - 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \ - 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \ - 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \ - 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \ - 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \ - 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \ - 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \ - 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \ - 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \ - 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \ - 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \ - 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \ - 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \ - } - -#undef CONFIG_SYS_NAND_ECCSIZE -#undef CONFIG_SYS_NAND_ECCBYTES -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 - -#define CONFIG_SYS_NAND_MAX_CHIPS 1 - -#undef CONFIG_SYS_MAX_NAND_DEVICE -#define CONFIG_SYS_MAX_NAND_DEVICE 3 -#define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */ -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ - CONFIG_SYS_NAND_BASE2} - -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define DDR_PLL_FREQ 303 - -/* FWD Button = 27 - * SRV Button = 87 */ -#define BOARD_DFU_BUTTON_GPIO 27 -#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ -/* In dfu mode keep led1 on */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - "button_dfu0=27\0" \ - "button_dfu1=87\0" \ - "led0=3,0,1\0" \ - "led1=4,0,0\0" \ - "led2=5,0,1\0" \ - "led3=87,0,1\0" \ - "led4=60,0,1\0" \ - "led5=63,0,1\0" - -/* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - -#define CONFIG_PHY_SMSC - -#define CONFIG_FACTORYSET - -/* use both define to compile a SPL compliance test */ -/* -#define CONFIG_SPL_CMT -#define CONFIG_SPL_CMT_DEBUG -*/ - -/* nedded by compliance test in read mode */ -#if defined(CONFIG_SPL_CMT) -#define CONFIG_SYS_DCACHE_OFF -#endif - -/* Define own nand partitions */ -#define CONFIG_ENV_OFFSET_REDUND 0xB80000 -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - - - -#undef COMMON_ENV_DFU_ARGS -#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ - "setenv bootargs ${bootargs};" \ - "mtdparts default;" \ - "draco_led 1;" \ - "dfu 0 mtd 0;" \ - "draco_led 0;\0" \ - -#undef DFU_ALT_INFO_NAND_V2 -#define DFU_ALT_INFO_NAND_V2 \ - "spl mtddev;" \ - "spl.backup1 mtddev;" \ - "spl.backup2 mtddev;" \ - "spl.backup3 mtddev;" \ - "u-boot mtddev;" \ - "u-boot.env0 mtddev;" \ - "u-boot.env1 mtddev;" \ - "rootfs mtddevubi" \ - -#undef CONFIG_ENV_SETTINGS_NAND_V2 -#define CONFIG_ENV_SETTINGS_NAND_V2 \ - "nand_active_ubi_vol=rootfs_a\0" \ - "rootfs_name=rootfs\0" \ - "kernel_name=uImage\0"\ - "nand_root_fs_type=ubifs rootwait=1\0" \ - "nand_args=run bootargs_defaults;" \ - "mtdparts default;" \ - "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ - "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ - "fi;" \ - "if test -n ${B}; then " \ - "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ - "fi;" \ - "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ - "ubi.mtd=rootfs,${ubi_off};" \ - "setenv bootargs ${bootargs} " \ - "root=${nand_root} noinitrd ${mtdparts} " \ - "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ - "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ - "=mtdoops\0" \ - COMMON_ENV_DFU_ARGS \ - "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \ - COMMON_ENV_NAND_BOOT \ - "ubi part rootfs ${ubi_off};" \ - "ubifsmount ubi0:${nand_active_ubi_vol};" \ - "ubifsload ${kloadaddr} boot/${kernel_name};" \ - "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \ - "bootm ${kloadaddr} - ${loadaddr}\0" \ - "nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \ - "bootm ${kloadaddr} - ${loadaddr}\0" \ - COMMON_ENV_NAND_CMDS - -#ifndef CONFIG_SPL_BUILD - -#define CONFIG_NAND_CS_INIT -#define ETAMIN_NAND_GPMC_CONFIG1 0x00000800 -#define ETAMIN_NAND_GPMC_CONFIG2 0x001e1e00 -#define ETAMIN_NAND_GPMC_CONFIG3 0x001e1e00 -#define ETAMIN_NAND_GPMC_CONFIG4 0x16051807 -#define ETAMIN_NAND_GPMC_CONFIG5 0x00151e1e -#define ETAMIN_NAND_GPMC_CONFIG6 0x16000f80 -#define CONFIG_MTD_CONCAT - -/* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=etamin\0" \ - "ubi_off=4096\0"\ - "nand_img_size=0x400000\0" \ - "optargs=\0" \ - "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 - -#ifndef CONFIG_RESTORE_FLASH - -#define CONFIG_BOOTCOMMAND \ -"if dfubutton; then " \ - "run dfu_start; " \ - "reset; " \ -"fi;" \ -"run nand_boot;" \ -"run nand_boot_backup;" \ -"reset;" - - -#else -#define CONFIG_BOOTCOMMAND \ - "setenv autoload no; " \ - "dhcp; " \ - "if tftp 80000000 debrick.scr; then " \ - "source 80000000; " \ - "fi" -#endif -#endif /* CONFIG_SPL_BUILD */ -#endif /* ! __CONFIG_ETAMIN_H */ diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h deleted file mode 100644 index c9e7c8c..0000000 --- a/include/configs/ethernut5.h +++ /dev/null @@ -1,149 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * egnite GmbH - * - * Configuation settings for Ethernut 5 with AT91SAM9XE. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* The first stage boot loader expects u-boot running at this address. */ - -/* The first stage boot loader takes care of low level initialization. */ -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Set our official architecture number. */ -#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5 - -/* CPU information */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ - -/* 32kB internal SRAM */ -#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ -#define CONFIG_SRAM_SIZE (32 << 10) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* 128MB SDRAM in 1 bank */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (128 << 20) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ - - CONFIG_SYS_MALLOC_LEN) - -/* 512kB on-chip NOR flash */ -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ -# define CONFIG_AT91_EFLASH -# define CONFIG_SYS_MAX_FLASH_SECT 32 -# define CONFIG_EFLASH_PROTSECTORS 1 - - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x3DE000 - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) -#endif - -/* JFFS2 */ -#ifdef CONFIG_CMD_JFFS2 -#define CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_NAND -#endif - -/* Ethernet */ -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_PHY_ID 0 -#define CONFIG_MACB_SEARCH_PHY - -/* MMC */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - -/* RTC */ -#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 -#endif - -/* I2C */ -#define CONFIG_SYS_MAX_I2C_BUS 1 - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0 - -#define I2C_SOFT_DECLARATIONS - -#define GPIO_I2C_SCL AT91_PIO_PORTA, 24 -#define GPIO_I2C_SDA AT91_PIO_PORTA, 23 - -#define I2C_INIT { \ - at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ - at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ - at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ -} - -#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) -#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) -#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) -#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) -#define I2C_DELAY udelay(100) -#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) - -/* DHCP/BOOTP options */ -#ifdef CONFIG_CMD_DHCP -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_SYS_AUTOLOAD "n" -#endif - -/* File systems */ - -/* Boot command */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \ - "sf read 0x22000000 0xc6000 0x294000; " \ - "bootm 0x22000000" - -/* Misc. u-boot settings */ - -#endif diff --git a/include/configs/evb_ast2500.h b/include/configs/evb_ast2500.h deleted file mode 100644 index e4b07e3..0000000 --- a/include/configs/evb_ast2500.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012-2020 ASPEED Technology Inc. - * Ryan Chen - * - * Copyright 2016 Google Inc - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x300000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x5000000) - -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE - -/* Memory Info */ -#define CONFIG_SYS_LOAD_ADDR 0x83000000 - -#define CONFIG_ENV_SIZE 0x20000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/evb_px5.h b/include/configs/evb_px5.h deleted file mode 100644 index e930420..0000000 --- a/include/configs/evb_px5.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIGS_PX5_EVB_H -#define __CONFIGS_PX5_EVB_H - -#include - -#define CONFIG_CONSOLE_SCROLL_LINES 10 -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/evb_rk3036.h b/include/configs/evb_rk3036.h deleted file mode 100644 index b03612c..0000000 --- a/include/configs/evb_rk3036.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#endif diff --git a/include/configs/evb_rk3128.h b/include/configs/evb_rk3128.h deleted file mode 100644 index 73ceab0..0000000 --- a/include/configs/evb_rk3128.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#ifndef __EVB_RK3128_H -#define __EVB_RK3128_H - -#include - -#define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/evb_rk3229.h b/include/configs/evb_rk3229.h deleted file mode 100644 index 6a91a82..0000000 --- a/include/configs/evb_rk3229.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h deleted file mode 100644 index ddd7012..0000000 --- a/include/configs/evb_rk3288.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/evb_rk3328.h b/include/configs/evb_rk3328.h deleted file mode 100644 index ed5888b..0000000 --- a/include/configs/evb_rk3328.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __EVB_RK3328_H -#define __EVB_RK3328_H - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 1 - -#define SDRAM_BANK_SIZE (2UL << 30) - -#define CONFIG_CONSOLE_SCROLL_LINES 10 - -#endif diff --git a/include/configs/evb_rk3399.h b/include/configs/evb_rk3399.h deleted file mode 100644 index b9c4d68..0000000 --- a/include/configs/evb_rk3399.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __EVB_RK3399_H -#define __EVB_RK3399_H - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define SDRAM_BANK_SIZE (2UL << 30) - -#endif diff --git a/include/configs/evb_rv1108.h b/include/configs/evb_rv1108.h deleted file mode 100644 index b742d98..0000000 --- a/include/configs/evb_rv1108.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * Default environment settings - */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ipaddr=172.16.12.50\0" \ - "serverip=172.16.12.69\0" \ - "" - -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND \ - "sf probe;" \ - "sf read 0x62000000 0x140800 0x500000;" \ - "dcache off;" \ - "go 0x62000000" - -#endif diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h deleted file mode 100644 index 5ae2b42..0000000 --- a/include/configs/exynos-common.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Common configuration settings for the SAMSUNG EXYNOS boards. - */ - -#ifndef __EXYNOS_COMMON_H -#define __EXYNOS_COMMON_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ - -#include /* get chip and board defs */ -#include - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Keep L2 Cache Disabled */ - -/* input clock of PLL: 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 -#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_ENV_OVERWRITE - -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - -/* select serial console configuration */ - -/* PWM */ -#define CONFIG_PWM - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h deleted file mode 100644 index 005f65d..0000000 --- a/include/configs/exynos4-common.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5 board. - */ - -#ifndef __CONFIG_EXYNOS4_COMMON_H -#define __CONFIG_EXYNOS4_COMMON_H - -#define CONFIG_EXYNOS4 /* Exynos4 Family */ - -#include "exynos-common.h" - -#define CONFIG_BOARD_COMMON - -#define CONFIG_REVISION_TAG - -/* SD/MMC configuration */ -#define CONFIG_MMC_DEFAULT_DEV 0 - -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - -/* Common environment variables */ -#define CONFIG_EXTRA_ENV_ITB \ - "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ - "${kernelname}\0" \ - "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${initrdaddr} " \ - "${initrdname}\0" \ - "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} " \ - "${fdtfile}\0" \ - "check_ramdisk=" \ - "if run loadinitrd; then " \ - "setenv initrd_addr ${initrdaddr};" \ - "else " \ - "setenv initrd_addr -;" \ - "fi;\0" \ - "check_dtb=" \ - "if run loaddtb; then " \ - "setenv fdt_addr ${fdtaddr};" \ - "else " \ - "setenv fdt_addr;" \ - "fi;\0" \ - "kernel_args=" \ - "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart}" \ - " ${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};\0" \ - "boot_fit=" \ - "setenv kerneladdr 0x42000000;" \ - "setenv kernelname Image.itb;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootm ${kerneladdr}#${board_name}\0" \ - "boot_uimg=" \ - "setenv kerneladdr 0x40007FC0;" \ - "setenv kernelname uImage;" \ - "run check_dtb;" \ - "run check_ramdisk;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootm ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ - "boot_zimg=" \ - "setenv kerneladdr 0x40007FC0;" \ - "setenv kernelname zImage;" \ - "run check_dtb;" \ - "run check_ramdisk;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootz ${kerneladdr} ${initrd_addr} ${fdt_addr};\0" \ - "autoboot=" \ - "if test -e mmc ${mmcdev}:${mmcbootpart} Image.itb; then; " \ - "run boot_fit;" \ - "elif test -e mmc ${mmcdev}:${mmcbootpart} zImage; then; " \ - "run boot_zimg;" \ - "elif test -e mmc ${mmcdev}:${mmcbootpart} uImage; then; " \ - "run boot_uimg;" \ - "fi;\0" - -#endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos5-common.h b/include/configs/exynos5-common.h deleted file mode 100644 index e0a4d76..0000000 --- a/include/configs/exynos5-common.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5 board. - */ - -#ifndef __CONFIG_EXYNOS5_COMMON_H -#define __CONFIG_EXYNOS5_COMMON_H - -#define CONFIG_EXYNOS5 /* Exynos5 Family */ - -#include "exynos-common.h" - -#define CONFIG_EXYNOS_SPL - -#ifdef FTRACE -#define CONFIG_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 -#endif - -/* Enable ACE acceleration for SHA1 and SHA256 */ -#define CONFIG_EXYNOS_ACE_SHA - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 -#define INFORM2_OFFSET 0x808 -#define INFORM3_OFFSET 0x80c - -/* select serial console configuration */ -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 - -/* Thermal Management Unit */ -#define CONFIG_EXYNOS_TMU - -/* MMC SPL */ -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -/* specific .lds file */ - -/* Boot Argument Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_RD_LVL - -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) - -/* U-Boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 -#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) - -/* I2C */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 - -/* SPI */ - -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#endif - -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable Time Command */ - -/* USB */ - -/* USB boot mode */ -#define CONFIG_USB_BOOTING -#define EXYNOS_COPY_USB_FNPTR_ADDR 0x02020070 -#define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 -#define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 2) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#ifndef MEM_LAYOUT_ENV_SETTINGS -/* 2GB RAM, bootm size of 256M, load scripts after that */ -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x42000000\0" \ - "fdt_addr_r=0x43000000\0" \ - "ramdisk_addr_r=0x43300000\0" \ - "scriptaddr=0x50000000\0" \ - "pxefile_addr_r=0x51000000\0" -#endif - -#ifndef EXYNOS_DEVICE_SETTINGS -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" -#endif - -#ifndef EXYNOS_FDTFILE_SETTING -#define EXYNOS_FDTFILE_SETTING -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS \ - EXYNOS_FDTFILE_SETTING \ - MEM_LAYOUT_ENV_SETTINGS \ - BOOTENV - -#endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h deleted file mode 100644 index a87182a..0000000 --- a/include/configs/exynos5-dt-common.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Google, Inc - * - * Configuration settings for generic Exynos 5 board - */ - -#ifndef __CONFIG_EXYNOS5_DT_COMMON_H -#define __CONFIG_EXYNOS5_DT_COMMON_H - -/* Console configuration */ -#undef EXYNOS_DEVICE_SETTINGS -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#define CONFIG_EXYNOS5_DT - -#define CONFIG_SYS_SPI_BASE 0x12D30000 -#define FLASH_SIZE (4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_SPI_BOOTING - -#define CONFIG_BOARD_COMMON - -/* Display */ -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - -/* Enable keyboard */ -#define CONFIG_KEYBOARD - -#endif diff --git a/include/configs/exynos5250-common.h b/include/configs/exynos5250-common.h deleted file mode 100644 index 65da381..0000000 --- a/include/configs/exynos5250-common.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -/* - * Copyright (C) 2012 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5250 board. - */ - -#ifndef __CONFIG_5250_H -#define __CONFIG_5250_H - -#define CONFIG_EXYNOS5250 - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 - -#define CONFIG_MACH_TYPE MACH_TYPE_SMDK5250 - -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_IRAM_STACK 0x02050000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - -#define CONFIG_USB_XHCI_EXYNOS - -/* DRAM Memory Banks */ -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ - -#endif /* __CONFIG_5250_H */ diff --git a/include/configs/exynos5420-common.h b/include/configs/exynos5420-common.h deleted file mode 100644 index 2d362f3..0000000 --- a/include/configs/exynos5420-common.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5420 SoC - */ - -#ifndef __CONFIG_EXYNOS5420_H -#define __CONFIG_EXYNOS5420_H - -#define CONFIG_EXYNOS5420 - -#define CONFIG_EXYNOS5_DT - -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 8002 - -#define CONFIG_VAR_SIZE_SPL - -#define CONFIG_IRAM_TOP 0x02074000 - -#define CONFIG_SPL_MAX_FOOTPRINT (30 * 1024) - -#define CONFIG_DEVICE_TREE_LIST "exynos5800-peach-pi" \ - "exynos5420-peach-pit exynos5420-smdk5420" - -#define CONFIG_PHY_IRAM_BASE 0x02020000 - -/* Address for relocating helper code (Last 4 KB of IRAM) */ -#define CONFIG_EXYNOS_RELOCATE_CODE_BASE (CONFIG_IRAM_TOP - 0x1000) - -/* - * Low Power settings - */ -#define CONFIG_LOWPOWER_FLAG 0x02020028 -#define CONFIG_LOWPOWER_ADDR 0x0202002C - -#define CONFIG_USB_XHCI_EXYNOS - -#endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/exynos7420-common.h b/include/configs/exynos7420-common.h deleted file mode 100644 index 157260c..0000000 --- a/include/configs/exynos7420-common.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Espresso7420 board. - * Copyright (C) 2016 Samsung Electronics - * Thomas Abraham - */ - -#ifndef __CONFIG_EXYNOS7420_COMMON_H -#define __CONFIG_EXYNOS7420_COMMON_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_EXYNOS7420 /* Exynos7 Family */ -#define CONFIG_S5P - -#include /* get chip and board defs */ -#include - -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* select serial console configuration */ - -/* Timer input clock frequency */ -#define COUNTER_FREQUENCY 24000000 - -/* Device Tree */ -#define CONFIG_DEVICE_TREE_LIST "exynos7420-espresso7420" - -/* IRAM Layout */ -#define CONFIG_IRAM_BASE 0x02100000 -#define CONFIG_IRAM_SIZE 0x58000 -#define CONFIG_IRAM_END (CONFIG_IRAM_BASE + CONFIG_IRAM_SIZE) -#define CPU_RELEASE_ADDR secondary_boot_addr - -/* select serial console configuration */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE - -/* Configuration of ENV Blocks */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - -#ifndef MEM_LAYOUT_ENV_SETTINGS -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x42000000\0" \ - "fdt_addr_r=0x43000000\0" \ - "ramdisk_addr_r=0x43300000\0" \ - "scriptaddr=0x50000000\0" \ - "pxefile_addr_r=0x51000000\0" -#endif - -#ifndef EXYNOS_DEVICE_SETTINGS -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" -#endif - -#ifndef EXYNOS_FDTFILE_SETTING -#define EXYNOS_FDTFILE_SETTING -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS \ - EXYNOS_FDTFILE_SETTING \ - MEM_LAYOUT_ENV_SETTINGS - -#endif /* __CONFIG_EXYNOS7420_COMMON_H */ diff --git a/include/configs/firefly-rk3288.h b/include/configs/firefly-rk3288.h deleted file mode 100644 index 9e4a669..0000000 --- a/include/configs/firefly-rk3288.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS \ - "stdin=serial,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/flea3.h b/include/configs/flea3.h deleted file mode 100644 index 4cd823f..0000000 --- a/include/configs/flea3.h +++ /dev/null @@ -1,193 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2007, Guennadi Liakhovetski - * - * Configuration for the flea3 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - - /* High Level Configuration Options */ -#define CONFIG_MX35 - -#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 - -/* Set TEXT at the beginning of the NOR flash */ - -/* This is required to setup the ESDC controller */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_SPD_BUS_NUM 2 /* I2C3 */ -#define CONFIG_SYS_MXC_I2C3_SLAVE 0xfe - -/* - * UART (console) - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART3_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * Command definition - */ - -#define CONFIG_NET_RETRY_COUNT 100 - - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -/* - * Ethernet on SOC (FEC) - */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 - -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) - -/* - * CFI FLASH driver setup - */ - -/* A non-standard buffered write algorithm */ - -/* - * NAND FLASH driver setup - */ -#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define CONFIG_HOSTNAME "flea3" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc2,${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "loadaddr=80800000\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "net_self=if run net_self_load;then " \ - "run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ - "else echo Images not loades;fi\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +80000;" \ - "erase ${uboot_addr} +80000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/galileo.h b/include/configs/galileo.h deleted file mode 100644 index 507d08c..0000000 --- a/include/configs/galileo.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -/* ns16550 UART is memory-mapped in Quark SoC */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -/* 10/100M Ethernet support */ -#define CONFIG_DESIGNWARE_ETH -#define CONFIG_DW_ALTDESCRIPTOR - -/* Environment configuration */ -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h deleted file mode 100644 index 482e471..0000000 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Atmel Corporation - * Copyright (C) 2019 Stefan Roese - * - * Configuation settings for the GARDENA smart Gateway (AT91SAM9G25) - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x7000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000 -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - -#endif diff --git a/include/configs/gardena-smart-gateway-mt7688.h b/include/configs/gardena-smart-gateway-mt7688.h deleted file mode 100644 index e83a96a..0000000 --- a/include/configs/gardena-smart-gateway-mt7688.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Stefan Roese - */ - -#ifndef __CONFIG_GARDENA_SMART_GATEWAY_H -#define __CONFIG_GARDENA_SMART_GATEWAY_H - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#ifdef CONFIG_BOOT_RAM -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 460800, 921600 } - -/* RAM */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 - -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 - -/* U-Boot */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/* Environment settings */ -#define CONFIG_ENV_OFFSET 0xa0000 -#define CONFIG_ENV_SIZE (64 << 10) -#define CONFIG_ENV_SECT_SIZE (64 << 10) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -#endif /* __CONFIG_GARDENA_SMART_GATEWAY_H */ diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h deleted file mode 100644 index 0ff4828..0000000 --- a/include/configs/gazerbeam.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * (C) Copyright 2015 - * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de - * - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -/* TODO: Check: Can this be unified with CONFIG_SYS_SDRAM_BASE? */ -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_SDRAM_BASE - -/* - * Memory test - * TODO: Migrate! - */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07e00000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -/* - * Environment - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - -/* TODO: Turn into string option and migrate to Kconfig */ -#define CONFIG_HOSTNAME "gazerbeam" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "u-boot=u-boot.bin\0" \ - "kernel_addr=1000000\0" \ - "fdt_addr=C00000\0" \ - "fdtfile=hrcon.dtb\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp ${kernel_addr} $bootfile;" \ - "tftp ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_MMCBOOTCOMMAND \ - "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ - "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h deleted file mode 100644 index 6de5119..0000000 --- a/include/configs/ge_bx50v3.h +++ /dev/null @@ -1,237 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Timesys Corporation - * Copyright (C) 2015 General Electric Company - * Copyright (C) 2014 Advantech - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the GE MX6Q Bx50v3 boards. - */ - -#ifndef __GE_BX50V3_CONFIG_H -#define __GE_BX50V3_CONFIG_H - -#include -#include - -#define CONFIG_BOARD_NAME "General Electric Bx50v3" - -#define CONFIG_MXC_UART_BASE UART3_BASE -#define CONSOLE_DEV "ttymxc2" - -#include "mx6_common.h" -#include - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART - -/* SATA Configs */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* USB Configs */ -#ifdef CONFIG_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_USBD_HS -#define CONFIG_USB_GADGET_MASS_STORAGE -#endif - -/* Networking Configs */ -#ifdef CONFIG_NET -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 4 -#define CONFIG_PHY_ATHEROS -#endif - -/* Serial Flash */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_LOADADDR 0x12000000 - -#ifdef CONFIG_NFS_CMD -#define NETWORKBOOT \ - "setnetworkboot=" \ - "setenv ipaddr 172.16.2.10; setenv serverip 172.16.2.20; " \ - "setenv gatewayip 172.16.2.20; setenv nfsserver 172.16.2.20; " \ - "setenv netmask 255.255.255.0; setenv ethaddr ca:fe:de:ca:f0:11; " \ - "setenv bootargs root=/dev/nfs nfsroot=${nfsserver}:/srv/nfs/,v3,tcp rw rootwait" \ - "setenv bootargs $bootargs ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off " \ - "setenv bootargs $bootargs cma=128M bootcause=POR console=${console} ${videoargs} " \ - "setenv bootargs $bootargs systemd.mask=helix-network-defaults.service " \ - "setenv bootargs $bootargs watchdog.handle_boot_enabled=1\0" \ - "networkboot=" \ - "run setnetworkboot; " \ - "nfs ${loadaddr} /srv/nfs/fitImage; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ - -#define CONFIG_NETWORKBOOTCOMMAND \ - "run networkboot; " \ - -#else -#define NETWORKBOOT \ - -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - NETWORKBOOT \ - "bootcause=POR\0" \ - "image=/boot/fitImage\0" \ - "fdt_high=0xffffffff\0" \ - "dev=mmc\0" \ - "devnum=2\0" \ - "rootdev=mmcblk0p\0" \ - "quiet=quiet loglevel=0\0" \ - "console=" CONSOLE_DEV "\0" \ - "setargs=setenv bootargs root=/dev/${rootdev}${partnum} " \ - "ro rootwait cma=128M " \ - "bootcause=${bootcause} " \ - "${quiet} console=${console} ${rtc_status} " \ - "${videoargs}" "\0" \ - "doquiet=" \ - "if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ - "then setenv quiet; fi\0" \ - "hasfirstboot=" \ - "ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \ - "/boot/bootcause/firstboot\0" \ - "swappartitions=" \ - "setexpr partnum 3 - ${partnum}\0" \ - "failbootcmd=" \ - "bx50_backlight_enable; " \ - "msg=\"Monitor failed to start. Try again, or contact GE Service for support.\"; " \ - "echo $msg; " \ - "setenv stdout vga; " \ - "echo \"\n\n\n\n \" $msg; " \ - "setenv stdout serial; " \ - "mw.b 0x7000A000 0xbc; " \ - "mw.b 0x7000A001 0x00; " \ - "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ - "altbootcmd=" \ - "run doquiet; " \ - "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ - "run hasfirstboot || setenv partnum 0; " \ - "if test ${partnum} != 0; then " \ - "setenv bootcause REVERT; " \ - "run swappartitions loadimage doboot; " \ - "fi; " \ - "run failbootcmd\0" \ - "loadimage=" \ - "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ - "doboot=" \ - "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ - "run setargs; " \ - "bootm ${loadaddr}#conf@${confidx}\0" \ - "tryboot=" \ - "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ - "run loadimage || run swappartitions && run loadimage || " \ - "setenv partnum 0 && echo MISSING IMAGE;" \ - "run doboot; " \ - "run failbootcmd\0" \ - -#define CONFIG_MMCBOOTCOMMAND \ - "if mmc dev ${devnum}; then " \ - "run doquiet; " \ - "run tryboot; " \ - "fi; " \ - -#define CONFIG_USBBOOTCOMMAND \ - "echo Unsupported; " \ - -#ifdef CONFIG_NFS_CMD -#define CONFIG_BOOTCOMMAND CONFIG_NETWORKBOOTCOMMAND -#elif CONFIG_CMD_USB -#define CONFIG_BOOTCOMMAND CONFIG_USBBOOTCOMMAND -#else -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND -#endif - - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) - -#define CONFIG_SYS_FSL_USDHC_NUM 3 - -/* Framebuffer */ -#define CONFIG_HIDE_LOGO_VERSION -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_CMD_BMP - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - -#define CONFIG_PCI -#define CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(1, 5) - -#define CONFIG_RTC_RX8010SJ -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 - -#define CONFIG_SYS_NUM_I2C_BUSES 11 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ - {1, {I2C_NULL_HOP} }, \ - {2, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ - } - -#define CONFIG_BCH - -#endif /* __GE_BX50V3_CONFIG_H */ diff --git a/include/configs/geekbox.h b/include/configs/geekbox.h deleted file mode 100644 index 91f4feb..0000000 --- a/include/configs/geekbox.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Andreas Färber - */ - -#ifndef __CONFIGS_GEEKBOX_H -#define __CONFIGS_GEEKBOX_H - -#include - -#define CONFIG_CONSOLE_SCROLL_LINES 10 - -#endif diff --git a/include/configs/goflexhome.h b/include/configs/goflexhome.h deleted file mode 100644 index 1d69a4e..0000000 --- a/include/configs/goflexhome.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Suriyan Ramasami - * - * Based on dockstar.h originally written by - * Copyright (C) 2010 Eric C. Cooper - * - * Based on sheevaplug.h originally written by - * Prafulla Wadaskar - * (C) Copyright 2009 - * Marvell Semiconductor - */ - -#ifndef _CONFIG_GOFLEXHOME_H -#define _CONFIG_GOFLEXHOME_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Default GPIO configuration and LED status - */ -#define GOFLEXHOME_OE_LOW (~(0)) -#define GOFLEXHOME_OE_HIGH (~(0)) -#define GOFLEXHOME_OE_VAL_LOW (1 << 29) /* USB_PWEN low */ -#define GOFLEXHOME_OE_VAL_HIGH (1 << 17) /* LED pin high */ - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0xC0000 -#define CONFIG_ENV_OFFSET 0xC0000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:root; " \ - "ubifsload 0x800000 ${kernel}; " \ - "bootm 0x800000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "kernel=/boot/uImage\0" \ - "bootargs_root=ubi.mtd=root root=ubi0:root rootfstype=ubifs ro\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - -/* - * * SATA Driver configuration - * */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_GOFLEXHOME_H */ diff --git a/include/configs/gose.h b/include/configs/gose.h deleted file mode 100644 index fcb9f17..0000000 --- a/include/configs/gose.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/gose.h - * - * Copyright (C) 2014 Renesas Electronics Corporation - */ - -#ifndef __GOSE_H -#define __GOSE_H - -#include "rcar-gen2-common.h" - -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 -#define STACK_AREA_SIZE 0x00100000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE (1048u * 1024 * 1024) -#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512u * 1024 * 1024) - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" - -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_CONS_SCIF0 -#define CONFIG_SH_SCIF_CLK_FREQ 65000000 -#endif - -#endif /* __GOSE_H */ diff --git a/include/configs/gplugd.h b/include/configs/gplugd.h deleted file mode 100644 index 7da8739..0000000 --- a/include/configs/gplugd.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * eInfochips Ltd. - * Written-by: Ajay Bhargav - * - * Based on Aspenite: - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - * Contributor: Mahavir Jain - */ - -#ifndef __CONFIG_GPLUGD_H -#define __CONFIG_GPLUGD_H - -/* - * High Level Configuration Options - */ -#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */ -#define CONFIG_ARMADA100 1 /* SOC Family Name */ -#define CONFIG_ARMADA168 1 /* SOC Used on this Board */ -#define CONFIG_MACH_TYPE MACH_TYPE_GPLUGD /* Machine type */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * There is no internal RAM in ARMADA100, using DRAM - * TBD: dcache to be used for this - */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x00200000) - -/* - * Commands configuration - */ - -/* Network configuration */ -#ifdef CONFIG_CMD_NET -#define CONFIG_ARMADA100_FEC - -/* DHCP Support */ -#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 -#endif /* CONFIG_CMD_NET */ - -/* GPIO Support */ -#define CONFIG_MARVELL_GPIO - -/* PHY configuration */ -#define CONFIG_RESET_PHY_R -/* 88E3015 register definition */ -#define PHY_LED_PAR_SEL_REG 22 -#define PHY_LED_MAN_REG 25 -#define PHY_LED_VAL 0x5b /* LINK LED1, ACT LED2 */ -/* GPIO Configuration for PHY */ -#define CONFIG_SYS_GPIO_PHY_RST 104 /* GPIO104 */ - -/* Flash Support */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -#ifdef CONFIG_SYS_NS16550_COM1 -#undef CONFIG_SYS_NS16550_COM1 -#endif /* CONFIG_SYS_NS16550_COM1 */ - -#define CONFIG_SYS_NS16550_COM1 ARMD1_UART3_BASE - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_SIZE 0x4000 - -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_ARMADA100 -#define CONFIG_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - -#endif /* __CONFIG_GPLUGD_H */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h deleted file mode 100644 index 26ca694..0000000 --- a/include/configs/grpeach.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Renesas GRPEACH board - * - * Copyright (C) 2017-2019 Renesas Electronics - */ - -#ifndef __GRPEACH_H -#define __GRPEACH_H - -/* Board Clock , P1 clock frequency (XTAL=13.33MHz) */ -#define CONFIG_SYS_CLK_FREQ 66666666 - -/* Serial Console */ -#define CONFIG_BAUDRATE 115200 - -/* Miscellaneous */ -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH -#define CONFIG_CMDLINE_TAG - -/* Internal RAM Size (RZ/A1=3M, RZ/A1M=5M, RZ/A1H=10M) */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 1024 * 1024) -#define CONFIG_SYS_LOAD_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) - -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OFFSET 0x80000 - -/* Malloc */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -/* Kernel Boot */ -#define CONFIG_BOOTARGS "ignore_loglevel" - -/* Network interface */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -#endif /* __GRPEACH_H */ diff --git a/include/configs/gru.h b/include/configs/gru.h deleted file mode 100644 index a0d27b6..0000000 --- a/include/configs/gru.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/guruplug.h b/include/configs/guruplug.h deleted file mode 100644 index 739ab32..0000000 --- a/include/configs/guruplug.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009-2014 - * Gerald Kerma - * Marvell Semiconductor - * Written-by: Siddarth Gore - */ - -#ifndef _CONFIG_GURUPLUG_H -#define _CONFIG_GURUPLUG_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ - -/* - * Standard filesystems - */ -#define CONFIG_BZIP2 - -/* - * mv-plug-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-plug-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */ -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:rootfs; " \ - "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x700000 ${fdt}; " \ - "ubifsumount; " \ - "fdt addr 0x700000; fdt resize; fdt chosen; " \ - "bootz 0x800000 - 0x700000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "kernel=/boot/zImage\0" \ - "fdt=/boot/guruplug-server-plus.dtb\0" \ - "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#endif /* _CONFIG_GURUPLUG_H */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h deleted file mode 100644 index a27627e..0000000 --- a/include/configs/gw_ventana.h +++ /dev/null @@ -1,341 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Gateworks Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SPL */ -/* Location in NAND to read U-Boot from */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * SZ_1M) - -/* Falcon Mode */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - NAND support: args@17MB kernel@18MB */ -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS (18 * SZ_1M) - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ - -#include "imx6_spl.h" /* common IMX6 SPL configuration */ -#include "mx6_common.h" - -#define CONFIG_MACH_TYPE 4520 /* Gateworks Ventana Platform */ - -/* Serial ATAG */ -#define CONFIG_SERIAL_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -/* Init Functions */ - -/* Driver Model */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_GPIO -#define CONFIG_DM_THERMAL -#endif - -/* Thermal */ -#define CONFIG_IMX_THERMAL - -/* Serial */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -#ifdef CONFIG_SPI_FLASH - -/* SPI */ -#ifdef CONFIG_CMD_SF - #define CONFIG_SPI_FLASH_MTD - /* GPIO 3-19 (21248) */ -#endif - -#elif defined(CONFIG_SPL_NAND_SUPPORT) -/* Enable NAND support */ -#ifdef CONFIG_CMD_NAND - #define CONFIG_SYS_MAX_NAND_DEVICE 1 - #define CONFIG_SYS_NAND_BASE 0x40000000 - #define CONFIG_SYS_NAND_5_ADDR_CYCLE - #define CONFIG_SYS_NAND_ONFI_DETECTION - - /* DMA stuff, needed for GPMI/MXS NAND support */ -#endif - -#endif /* CONFIG_SPI_FLASH */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_I2C_GSC 0 -#define CONFIG_I2C_EDID - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 1 - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR - #define CONFIG_LBA48 -#endif - -/* - * PCI express - */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCI_FIXUP_DEV -#define CONFIG_PCIE_IMX -#endif - -/* - * PMIC - */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define CONFIG_POWER_LTC3676 -#define CONFIG_POWER_LTC3676_I2C_ADDR 0x3c - -/* Various command support */ -#define CONFIG_CMD_UNZIP /* gzwrite */ - -/* Ethernet support */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_ARP_TIMEOUT 200UL - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USBD_HS -#define CONFIG_NETCONSOLE - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_HIDE_LOGO_VERSION /* Custom config to hide U-boot version */ - -/* Miscellaneous configurable options */ -#define CONFIG_HWCONFIG - -/* Memory configuration */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* Persistent Environment Config */ -#if defined(CONFIG_ENV_IS_IN_MMC) - #define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_SYS_MMC_ENV_PART 1 - #define CONFIG_ENV_OFFSET (709 * SZ_1K) - #define CONFIG_ENV_SIZE (128 * SZ_1K) - #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (128 * SZ_1K)) -#elif defined(CONFIG_ENV_IS_IN_NAND) - #define CONFIG_ENV_OFFSET (16 * SZ_1M) - #define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) - #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 * SZ_1K)) - #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) - #define CONFIG_ENV_OFFSET (512 * SZ_1K) - #define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) - #define CONFIG_ENV_SIZE (8 * SZ_1K) -#endif - -/* Environment */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.146 - -#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "pcidisable=1\0" \ - "splashpos=m,m\0" \ - "usb_pgood_delay=2000\0" \ - "console=ttymxc1\0" \ - "bootdevs=usb mmc sata flash\0" \ - "hwconfig=_UNKNOWN_\0" \ - "video=\0" \ - \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "disk=0\0" \ - "part=1\0" \ - \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x18000000\0" \ - "initrd_high=0xffffffff\0" \ - "fixfdt=" \ - "fdt addr ${fdt_addr}\0" \ - "bootdir=boot\0" \ - "loadfdt=" \ - "if ${fsload} ${fdt_addr} ${bootdir}/${fdt_file}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file1}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file1}; " \ - "run fixfdt; " \ - "elif ${fsload} ${fdt_addr} ${bootdir}/${fdt_file2}; then " \ - "echo Loaded DTB from ${bootdir}/${fdt_file2}; " \ - "run fixfdt; " \ - "fi\0" \ - \ - "fs=ext4\0" \ - "script=6x_bootscript-ventana\0" \ - "loadscript=" \ - "if ${fsload} ${loadaddr} ${bootdir}/${script}; then " \ - "source ${loadaddr}; " \ - "fi\0" \ - \ - "uimage=uImage\0" \ - "mmc_root=mmcblk0p1\0" \ - "mmc_boot=" \ - "setenv fsload \"${fs}load mmc ${disk}:${part}\"; " \ - "mmc dev ${disk} && mmc rescan && " \ - "setenv dtype mmc; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/${mmc_root} rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - \ - "sata_boot=" \ - "setenv fsload \"${fs}load sata ${disk}:${part}\"; " \ - "sata init && " \ - "setenv dtype sata; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" \ - "usb_boot=" \ - "setenv fsload \"${fs}load usb ${disk}:${part}\"; " \ - "usb start && usb dev ${disk} && " \ - "setenv dtype usb; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/sda1 rootfstype=${fs} " \ - "rootwait rw ${video} ${extra}; " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "bootm; " \ - "fi; " \ - "fi\0" - -#ifdef CONFIG_SPI_FLASH - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - "image_os=ventana/openwrt-imx6-imx6q-gw5400-a-squashfs.bin\0" \ - "image_uboot=ventana/u-boot_spi.imx\0" \ - \ - "spi_koffset=0x90000\0" \ - "spi_klen=0x200000\0" \ - \ - "spi_updateuboot=echo Updating uboot from " \ - "${serverip}:${image_uboot}...; " \ - "tftpboot ${loadaddr} ${image_uboot} && " \ - "sf probe && sf erase 0 80000 && " \ - "sf write ${loadaddr} 400 ${filesize}\0" \ - "spi_update=echo Updating OS from ${serverip}:${image_os} " \ - "to ${spi_koffset} ...; " \ - "tftp ${loadaddr} ${image_os} && " \ - "sf probe && " \ - "sf update ${loadaddr} ${spi_koffset} ${filesize}\0" \ - \ - "flash_boot=" \ - "if sf probe && " \ - "sf read ${loadaddr} ${spi_koffset} ${spi_klen}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=/dev/mtdblock3 " \ - "rootfstype=squashfs,jffs2 " \ - "${video} ${extra}; " \ - "bootm; " \ - "fi\0" -#else - #define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_EXTRA_ENV_SETTINGS_COMMON \ - \ - "image_rootfs=openwrt-imx6-ventana-rootfs.ubi\0" \ - "nand_update=echo Updating NAND from ${serverip}:${image_rootfs}...; " \ - "tftp ${loadaddr} ${image_rootfs} && " \ - "nand erase.part rootfs && " \ - "nand write ${loadaddr} rootfs ${filesize}\0" \ - \ - "flash_boot=" \ - "setenv fsload 'ubifsload'; " \ - "ubi part rootfs; " \ - "if ubi check boot; then " \ - "ubifsmount ubi0:boot; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=squashfs,ubifs; " \ - "setenv bootdir; " \ - "elif ubi check rootfs; then " \ - "ubifsmount ubi0:rootfs; " \ - "setenv root ubi0:rootfs ubi.mtd=2 " \ - "rootfstype=ubifs; " \ - "fi; " \ - "setenv dtype nand; run loadscript; " \ - "if ${fsload} ${loadaddr} ${bootdir}/${uimage}; then " \ - "setenv bootargs console=${console},${baudrate} " \ - "root=${root} ${video} ${extra}; " \ - "if run loadfdt; then " \ - "ubifsumount; " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "ubifsumount; bootm; " \ - "fi; " \ - "fi\0" -#endif - -#define CONFIG_BOOTCOMMAND \ - "for btype in ${bootdevs}; do " \ - "echo; echo Attempting ${btype} boot...; " \ - "if run ${btype}_boot; then; fi; " \ - "done" - -#endif /* __CONFIG_H */ diff --git a/include/configs/harmony.h b/include/configs/harmony.h deleted file mode 100644 index f873cea..0000000 --- a/include/configs/harmony.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD - -/* UARTD: keyboard satellite board UART, default */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE -#ifdef CONFIG_TEGRA_ENABLE_UARTA -/* UARTA: debug board UART */ -#define CONFIG_SYS_NS16550_COM2 NV_PA_APB_UARTA_BASE -#endif - -#define CONFIG_MACH_TYPE MACH_TYPE_HARMONY - -/* NAND support */ -#define CONFIG_TEGRA_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment in NAND (which is 512M), aligned to start of last sector */ -#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sector size */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/helios4.h b/include/configs/helios4.h deleted file mode 100644 index 4df3200..0000000 --- a/include/configs/helios4.h +++ /dev/null @@ -1,177 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Dennis Gilmore - */ - -#ifndef _CONFIG_HELIOS4_H -#define _CONFIG_HELIOS4_H - -#include - -/* - * High Level Configuration Options (easy to change) - */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* - * Commands configuration - */ - -/* - * SDIO/MMC Card Configuration - */ -#define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -#define CONFIG_ENV_MIN_ENTRIES 128 - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 2 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_SECT_SIZE SZ_64K -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_OFFSET SZ_1M -#endif - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -/* Environment in MMC */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SECT_SIZE 0x200 -#define CONFIG_ENV_SIZE 0x2000 -/* stay within first 1M */ -#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE) -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET -#endif - -#define CONFIG_PHY_MARVELL /* there is a marvell phy */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define RELOCATION_LIMITS_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -/* SPL */ -/* - * Select the boot device here - * - * Currently supported are: - * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash - * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) - */ -#define SPL_BOOT_SPI_NOR_FLASH 1 -#define SPL_BOOT_SDIO_MMC_CARD 2 - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH -#endif -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -#define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SDIO_MMC_CARD -#endif - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH -/* SPL related SPI defines */ -#define CONFIG_SPL_SPI_FLASH_SUPPORT -#define CONFIG_SPL_SPI_LOAD -#define CONFIG_SPL_SPI_SUPPORT -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS -#endif - -#if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD -/* SPL related MMC defines */ -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -#ifdef CONFIG_SPL_BUILD -#define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -#endif -#endif -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - -#ifdef CONFIG_MMC -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) -#else -#define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#ifdef CONFIG_USB_STORAGE -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_DEVICES_USB(func) -#endif - -#ifdef CONFIG_SATA -#define BOOT_TARGET_DEVICES_SATA(func) func(SATA, sata, 0) -#else -#define BOOT_TARGET_DEVICES_SATA(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_USB(func) \ - BOOT_TARGET_DEVICES_SATA(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#define KERNEL_ADDR_R __stringify(0x800000) -#define FDT_ADDR_R __stringify(0x100000) -#define RAMDISK_ADDR_R __stringify(0x1800000) -#define SCRIPT_ADDR_R __stringify(0x200000) -#define PXEFILE_ADDR_R __stringify(0x300000) - -#define LOAD_ADDRESS_ENV_SETTINGS \ - "kernel_addr_r=" KERNEL_ADDR_R "\0" \ - "fdt_addr_r=" FDT_ADDR_R "\0" \ - "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ - "scriptaddr=" SCRIPT_ADDR_R "\0" \ - "pxefile_addr_r=" PXEFILE_ADDR_R "\0" - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - RELOCATION_LIMITS_ENV_SETTINGS \ - LOAD_ADDRESS_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "console=ttyS0,115200\0" \ - BOOTENV - -#endif /* CONFIG_SPL_BUILD */ - -#endif /* _CONFIG_HELIOS4_H */ diff --git a/include/configs/highbank.h b/include/configs/highbank.h deleted file mode 100644 index c0e295b..0000000 --- a/include/configs/highbank.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Calxeda, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) - -#define CONFIG_SYS_TIMER_RATE (150000000/256) -#define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) -#define CONFIG_SYS_TIMER_COUNTS_DOWN - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -#define CONFIG_PL011_CLOCK 150000000 -#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) } - -#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ - -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -#define CONFIG_CALXEDA_XGMAC - -/* - * Command line configuration. - */ - -#define CONFIG_BOOT_RETRY_TIME -1 -#define CONFIG_RESET_TO_RETRY - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_LOAD_ADDR 0x800000 -#define CONFIG_SYS_64BIT_LBA - -/*----------------------------------------------------------------------- - * Physical Memory Map - * The DRAM is already setup, so do not touch the DT node later. - */ -#define PHYS_SDRAM_1_SIZE (4089 << 20) -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1_SIZE - 0x100000) - -/* Environment data setup -*/ -#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ -#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ -#define CONFIG_ENV_SIZE 0x2000 /* Size of Environ */ -#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x01000000 -#define CONFIG_SKIP_LOWLEVEL_INIT - -#endif diff --git a/include/configs/hikey.h b/include/configs/hikey.h deleted file mode 100644 index 60c6bde..0000000 --- a/include/configs/hikey.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Linaro - * - * Peter Griffin - * - * Configuration for HiKey 96boards CE. Parts were derived from other ARM - * configurations. - */ - -#ifndef __HIKEY_H -#define __HIKEY_H - -#include - -#define CONFIG_POWER -#define CONFIG_POWER_HI6553 - -#define CONFIG_REMAKE_ELF - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* Physical Memory Map */ - -/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ - -#define PHYS_SDRAM_1 0x00000000 - -/* 1008 MB (the last 16Mb are secured for TrustZone by ATF*/ -#define PHYS_SDRAM_1_SIZE 0x3EFFFFFF - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 19000000 - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xf6801000 -#define GICC_BASE 0xf6802000 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_DWC2_REG_ADDR 0xF72C0000 -/*#define CONFIG_DWC2_DFLT_SPEED_FULL*/ -#define CONFIG_DWC2_ENABLE_DYNAMIC_FIFO -#endif - -#define CONFIG_HIKEY_GPIO - -/* Command line configuration */ - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Initial environment variables */ - -/* - * Defines where the kernel and FDT will be put in RAM - */ - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(MMC, mmc, 1) \ - func(DHCP, dhcp, na) -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=Image\0" \ - "kernel_addr_r=0x00080000\0" \ - "fdtfile=hi6220-hikey.dtb\0" \ - "fdt_addr_r=0x02000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - BOOTENV - -/* Preserve environment on eMMC */ -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* Use eMMC */ -#define CONFIG_SYS_MMC_ENV_PART 2 /* Use Boot1 partition */ - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#endif /* __HIKEY_H */ diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h deleted file mode 100644 index f6f9c8d..0000000 --- a/include/configs/hikey960.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2019 Linaro - * Author: Manivannan Sadhasivam - */ - -#ifndef __HIKEY_H -#define __HIKEY_H - -#include - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* Physical Memory Map */ - -/* CONFIG_SYS_TEXT_BASE needs to align with where ATF loads bl33.bin */ - -#define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_1_SIZE 0xC0000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x80000) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 19000000 - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xe82b1000 -#define GICC_BASE 0xe82b2000 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M) - -#define CONFIG_ENV_SIZE 0x1000 - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "image=Image\0" \ - "fdtfile=hi3660-hikey960.dtb\0" \ - "fdt_addr_r=0x10000000\0" \ - "kernel_addr_r=0x11000000\0" \ - "scriptaddr=0x00020000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - BOOTENV - -#define CONFIG_ENV_SIZE 0x1000 - -/* TODO: Remove this once the SD clock is fixed */ -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1024 - -#endif /* __HIKEY_H */ diff --git a/include/configs/hrcon.h b/include/configs/hrcon.h deleted file mode 100644 index 8fb3211..0000000 --- a/include/configs/hrcon.h +++ /dev/null @@ -1,438 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of one chip NT5TU64M16HG from NANYA - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_BANK_BIT_3 \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00260802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (7 << TIMING_CFG1_CASLAT_SHIFT) \ - | (9 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26279222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x021848c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x08240100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_16) - /* 0x43100000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0242 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=4, AL=0 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#if 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 -#endif - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FPGA_DONE(k) 0x0010 - -#define CONFIG_SYS_FPGA_COUNT 1 - -#define CONFIG_SYS_MCLINK_MAX 3 - -#define CONFIG_SYS_FPGA_PTR \ - { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* Pass open firmware flat tree */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -#define CONFIG_PCA953X /* NXP PCA9554 */ -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_IHS -#define CONFIG_SYS_I2C_IHS_CH0 -#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_IHS_CH1 -#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2 -#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F -#define CONFIG_SYS_I2C_IHS_CH3 -#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_I2C_IHS_DUAL -#define CONFIG_SYS_I2C_IHS_CH0_1 -#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH1_1 -#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2_1 -#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH3_1 -#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F -#endif - -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define I2C_SOFT_DECLARATIONS2 -#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F -#define I2C_SOFT_DECLARATIONS3 -#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F -#define I2C_SOFT_DECLARATIONS4 -#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#define I2C_SOFT_DECLARATIONS5 -#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F -#define I2C_SOFT_DECLARATIONS6 -#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F -#define I2C_SOFT_DECLARATIONS7 -#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F -#define I2C_SOFT_DECLARATIONS8 -#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F - -#ifdef CONFIG_HRCON_DH -#define I2C_SOFT_DECLARATIONS9 -#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F -#define I2C_SOFT_DECLARATIONS10 -#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F -#define I2C_SOFT_DECLARATIONS11 -#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F -#define I2C_SOFT_DECLARATIONS12 -#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F -#endif - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} -#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} -#define CONFIG_HRCON_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#else -#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_HRCON_FANS { {6, 0x4c}, {7, 0x4c}, \ - {8, 0x4c} } -#endif - -#ifndef __ASSEMBLY__ -void fpga_gpio_set(unsigned int bus, int pin); -void fpga_gpio_clear(unsigned int bus, int pin); -int fpga_gpio_get(unsigned int bus, int pin); -void fpga_control_set(unsigned int bus, int pin); -void fpga_control_clear(unsigned int bus, int pin); -#endif - -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) -#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) - -#ifdef CONFIG_HRCON_DH -#define I2C_ACTIVE \ - do { \ - if (I2C_ADAP_HWNR > 7) \ - fpga_control_set(I2C_FPGA_IDX, 0x0004); \ - else \ - fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ - } while (0) -#else -#define I2C_ACTIVE { } -#endif -#define I2C_TRISTATE { } -#define I2C_READ \ - (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - } while (0) -#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ - -/* - * Software (bit-bang) MII driver configuration - */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -#define CONFIG_BITBANGMII_MULTI - -/* - * OSD Setup - */ -#define CONFIG_SYS_OSD_SCREENS 1 -#define CONFIG_SYS_DP501_DIFFERENTIAL -#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ - -#ifdef CONFIG_HRCON_DH -#define CONFIG_SYS_OSD_DH -#endif - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define TSEC1_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ -#if 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#else -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_HOSTNAME "hrcon" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "u-boot=u-boot.bin\0" \ - "kernel_addr=1000000\0" \ - "fdt_addr=C00000\0" \ - "fdtfile=hrcon.dtb\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp ${kernel_addr} $bootfile;" \ - "tftp ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_MMCBOOTCOMMAND \ - "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ - "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/hsdk.h b/include/configs/hsdk.h deleted file mode 100644 index 7735cc1..0000000 --- a/include/configs/hsdk.h +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Synopsys, Inc. All rights reserved. - */ - -#ifndef _CONFIG_HSDK_H_ -#define _CONFIG_HSDK_H_ - -#include - -/* - * CPU configuration - */ -#define NR_CPUS 4 -#define ARC_PERIPHERAL_BASE 0xF0000000 -#define ARC_DWMMC_BASE (ARC_PERIPHERAL_BASE + 0xA000) -#define ARC_DWGMAC_BASE (ARC_PERIPHERAL_BASE + 0x18000) - -/* - * Memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_1G - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN SZ_2M -#define CONFIG_SYS_BOOTM_LEN SZ_128M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -/* - * UART configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 33330000 -#define CONFIG_SYS_NS16550_MEM32 - -/* - * Ethernet PHY configuration - */ - -/* - * USB 1.1 configuration - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -/* - * Environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "upgrade=if mmc rescan && " \ - "fatload mmc 0:1 ${loadaddr} u-boot-update.scr && " \ - "iminfo ${loadaddr} && source ${loadaddr}; then; else echo " \ - "\"Fail to upgrade.\n" \ - "Do you have u-boot-update.scr and u-boot.head on first (FAT) SD card partition?\"" \ - "; fi\0" \ - "core_dccm_0=0x10\0" \ - "core_dccm_1=0x6\0" \ - "core_dccm_2=0x10\0" \ - "core_dccm_3=0x6\0" \ - "core_iccm_0=0x10\0" \ - "core_iccm_1=0x6\0" \ - "core_iccm_2=0x10\0" \ - "core_iccm_3=0x6\0" \ - "core_mask=0xF\0" \ - "dcache_ena=0x1\0" \ - "icache_ena=0x1\0" \ - "non_volatile_limit=0xE\0" \ - "hsdk_hs34=setenv core_mask 0x2; setenv icache_ena 0x0; \ -setenv dcache_ena 0x0; setenv core_iccm_1 0x7; \ -setenv core_dccm_1 0x8; setenv non_volatile_limit 0x0;\0" \ - "hsdk_hs36=setenv core_mask 0x1; setenv icache_ena 0x1; \ -setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ -setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \ - "hsdk_hs36_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \ -setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ -setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \ - "hsdk_hs38=setenv core_mask 0x1; setenv icache_ena 0x1; \ -setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ -setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE;\0" \ - "hsdk_hs38_ccm=setenv core_mask 0x2; setenv icache_ena 0x1; \ -setenv dcache_ena 0x1; setenv core_iccm_1 0x7; \ -setenv core_dccm_1 0x8; setenv non_volatile_limit 0xE;\0" \ - "hsdk_hs38x2=setenv core_mask 0x3; setenv icache_ena 0x1; \ -setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ -setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ -setenv core_iccm_1 0x6; setenv core_dccm_1 0x6;\0" \ - "hsdk_hs38x3=setenv core_mask 0x7; setenv icache_ena 0x1; \ -setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ -setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ -setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ -setenv core_iccm_2 0x10; setenv core_dccm_2 0x10;\0" \ - "hsdk_hs38x4=setenv core_mask 0xF; setenv icache_ena 0x1; \ -setenv dcache_ena 0x1; setenv core_iccm_0 0x10; \ -setenv core_dccm_0 0x10; setenv non_volatile_limit 0xE; \ -setenv core_iccm_1 0x6; setenv core_dccm_1 0x6; \ -setenv core_iccm_2 0x10; setenv core_dccm_2 0x10; \ -setenv core_iccm_3 0x6; setenv core_dccm_3 0x6;\0" - -/* - * Environment configuration - */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -/* Cli configuration */ -#define CONFIG_SYS_CBSIZE SZ_2K - -/* - * Callback configuration - */ -#define CONFIG_BOARD_LATE_INIT - -#endif /* _CONFIG_HSDK_H_ */ diff --git a/include/configs/huawei_hg556a.h b/include/configs/huawei_hg556a.h deleted file mode 100644 index 2aa5c66..0000000 --- a/include/configs/huawei_hg556a.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/ib62x0.h b/include/configs/ib62x0.h deleted file mode 100644 index 5e54441..0000000 --- a/include/configs/ib62x0.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011-2012 - * Gerald Kerma - * Luka Perkov - */ - -#ifndef _CONFIG_IB62x0_H -#define _CONFIG_IB62x0_H - -/* - * High level configuration options - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Compression configuration - */ -#define CONFIG_BZIP2 - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configuration - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0xe0000 - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:rootfs; " \ - "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x700000 ${fdt}; " \ - "ubifsumount; " \ - "fdt addr 0x700000; fdt resize; fdt chosen; " \ - "bootz 0x800000 - 0x700000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "kernel=/boot/zImage\0" \ - "fdt=/boot/ib62x0.dtb\0" \ - "bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0" - -/* - * Ethernet driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#undef CONFIG_RESET_PHY_R -#endif /* CONFIG_CMD_NET */ - -/* - * SATA driver configuration - */ -#ifdef CONFIG_IDE -#define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /* CONFIG_IDE */ - -/* - * RTC driver configuration - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MV -#endif /* CONFIG_CMD_DATE */ - -#endif /* _CONFIG_IB62x0_H */ diff --git a/include/configs/iconnect.h b/include/configs/iconnect.h deleted file mode 100644 index 87113d7..0000000 --- a/include/configs/iconnect.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009-2012 - * Wojciech Dubowik - * Luka Perkov - */ - -#ifndef _CONFIG_ICONNECT_H -#define _CONFIG_ICONNECT_H - -/* - * High level configuration options - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Machine type - */ -#define CONFIG_MACH_TYPE MACH_TYPE_ICONNECT - -/* - * Compression configuration - */ -#define CONFIG_BZIP2 - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configuration - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x80000 - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part rootfs; " \ - "ubifsmount ubi:rootfs; " \ - "ubifsload 0x800000 ${kernel}; " \ - "bootm 0x800000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "kernel=/boot/uImage\0" \ - "bootargs_root=noinitrd ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0" - -/* - * Ethernet driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 11 -#undef CONFIG_RESET_PHY_R -#endif /* CONFIG_CMD_NET */ - -/* - * File system - */ - -#endif /* _CONFIG_ICONNECT_H */ diff --git a/include/configs/ids8313.h b/include/configs/ids8313.h deleted file mode 100644 index 43cb14c..0000000 --- a/include/configs/ids8313.h +++ /dev/null @@ -1,306 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (c) 2011 IDS GmbH, Germany - * Sergej Stepanov - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_FSL_ELBC - -#define CONFIG_BOOT_RETRY_TIME 900 -#define CONFIG_BOOT_RETRY_MIN 30 -#define CONFIG_RESET_TO_RETRY - -#define CONFIG_SYS_SICRH 0x00000000 -#define CONFIG_SYS_SICRL (SICRL_LBC | SICRL_SPI_D) - -#define CONFIG_HWCONFIG - -/* - * Definitions for initial stack pointer and data area (in DCACHE ) - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ - - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * Internal Definitions - */ -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* - * Manually set up DDR parameters, - * as this board has not the SPD connected to I2C. - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN |\ - 0x00010000 |\ - CSCONFIG_ROW_BIT_13 |\ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_CONFIG_256 (CONFIG_SYS_DDR_CONFIG | \ - CSCONFIG_BANK_BIT_3) - -#define CONFIG_SYS_DDR_TIMING_3 (1 << 16) /* ext refrec */ -#define CONFIG_SYS_DDR_TIMING_0 ((3 << TIMING_CFG0_RWT_SHIFT) |\ - (3 << TIMING_CFG0_WRT_SHIFT) |\ - (3 << TIMING_CFG0_RRT_SHIFT) |\ - (3 << TIMING_CFG0_WWT_SHIFT) |\ - (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) |\ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) |\ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_MRS_CYC_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_1 ((4 << TIMING_CFG1_PRETOACT_SHIFT) |\ - (12 << TIMING_CFG1_ACTTOPRE_SHIFT) |\ - (4 << TIMING_CFG1_ACTTORW_SHIFT) |\ - (7 << TIMING_CFG1_CASLAT_SHIFT) |\ - (4 << TIMING_CFG1_REFREC_SHIFT) |\ - (4 << TIMING_CFG1_WRREC_SHIFT) |\ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) |\ - (2 << TIMING_CFG1_WRTORD_SHIFT)) -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ - (5 << TIMING_CFG2_CPO_SHIFT) |\ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) |\ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) |\ - (0 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) |\ - (1 << TIMING_CFG2_CKE_PLS_SHIFT) |\ - (6 << TIMING_CFG2_FOUR_ACT_SHIFT)) - -#define CONFIG_SYS_DDR_INTERVAL ((0x800 << SDRAM_INTERVAL_REFINT_SHIFT) |\ - (0x800 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN |\ - SDRAM_CFG_2T_EN | SDRAM_CFG_HSE |\ - SDRAM_CFG_DBW_32 |\ - SDRAM_CFG_SDRAM_TYPE_DDR2) - -#define CONFIG_SYS_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) |\ - (0x0242 << SDRAM_MODE_SD_SHIFT)) -#define CONFIG_SYS_DDR_MODE_2 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN |\ - DDRCDR_PZ_NOMZ |\ - DDRCDR_NZ_NOMZ |\ - DDRCDR_ODT |\ - DDRCDR_M_ODR |\ - DDRCDR_Q_DRN) - -/* - * on-board devices - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 - -/* - * NOR FLASH setup - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT -#define CONFIG_FLASH_SHOW_PROGRESS 50 - -#define CONFIG_SYS_FLASH_BASE 0xFF800000 -#define CONFIG_SYS_FLASH_SIZE 8 - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 - -/* - * NAND FLASH setup - */ -#define CONFIG_SYS_NAND_BASE 0xE1000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_PAGE_SIZE (2048) -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) -#define NAND_CACHE_PAGES 64 - - -/* - * MRAM setup - */ -#define CONFIG_SYS_MRAM_BASE 0xE2000000 -#define CONFIG_SYS_MRAM_SIZE 0x20000 /* 128 Kb */ - -#define CONFIG_SYS_OR_TIMING_MRAM - - -/* - * CPLD setup - */ -#define CONFIG_SYS_CPLD_BASE 0xE3000000 -#define CONFIG_SYS_CPLD_SIZE 0x8000 - -#define CONFIG_SYS_OR_TIMING_MRAM - - -/* - * HW-Watchdog - */ -#define CONFIG_WATCHDOG 1 -#define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF - -/* - * I2C setup - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 -#define CONFIG_RTC_PCF8563 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 - -/* - * Ethernet setup - */ -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x1 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC1_PHYIDX 0 -#endif - -#ifdef CONFIG_TSEC2 -#define CONFIG_HAS_ETH1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define TSEC2_PHY_ADDR 0x3 -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC2_PHYIDX 0 -#endif -#define CONFIG_ETHPRIME "TSEC1" - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) - -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_SYS_SCCR_USBDRCM 3 - -/* - * U-Boot environment setup - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (8 * 1024 * 1024) - -/* - * Environment Configuration - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ - + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_NETDEV eth1 -#define CONFIG_HOSTNAME "ids8313" -#define CONFIG_ROOTPATH "/opt/eldk-4.2/ppc_6xx" -#define CONFIG_BOOTFILE "ids8313/uImage" -#define CONFIG_UBOOTPATH "ids8313/u-boot.bin" -#define CONFIG_FDTFILE "ids8313/ids8313.dtb" -#define CONFIG_LOADADDR 0x400000 -#define CONFIG_ENV_FLAGS_LIST_STATIC "ethaddr:mo,eth1addr:mo" - -/* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x00C00000 - -#define CONFIG_SYS_LOAD_ADDR 0x100000 -#define CONFIG_LOADS_ECHO -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTCOMMAND "run boot_cramfs" -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_JFFS2_NAND -#define CONFIG_JFFS2_DEV "0" - -/* mtdparts command line support */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" __stringify(CONFIG_NETDEV) "\0" \ - "ethprime=TSEC1\0" \ - "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "tftpflash=tftpboot ${loadaddr} ${uboot}; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "cp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ - " ${filesize}; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ - " +${filesize}; " \ - "cmp.b ${loadaddr} " __stringify(CONFIG_SYS_TEXT_BASE) \ - " ${filesize}\0" \ - "console=ttyS0\0" \ - "fdtaddr=0x780000\0" \ - "kernel_addr=ff800000\0" \ - "fdtfile=" __stringify(CONFIG_FDTFILE) "\0" \ - "setbootargs=setenv bootargs " \ - "root=${rootdev} rw console=${console}," \ - "${baudrate} ${othbootargs}\0" \ - "setipargs=setenv bootargs root=${rootdev} rw " \ - "nfsroot=${serverip}:${rootpath} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off " \ - "console=${console},${baudrate} ${othbootargs}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv rootdev /dev/nfs;" \ - "run setipargs;run addmtd;" \ - "tftp ${loadaddr} ${bootfile};" \ - "tftp ${fdtaddr} ${fdtfile};" \ - "fdt addr ${fdtaddr};" \ - "bootm ${loadaddr} - ${fdtaddr}" - -/* UBI Support */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/imgtec_xilfpga.h b/include/configs/imgtec_xilfpga.h deleted file mode 100644 index 8e2d723..0000000 --- a/include/configs/imgtec_xilfpga.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, Imagination Technologies Ltd. - * - * Zubair Lutfullah Kakakhel - * - * Imagination Technologies Ltd. MIPSfpga - */ - -#ifndef __XILFPGA_CONFIG_H -#define __XILFPGA_CONFIG_H - -/* BootROM + MIG is pretty smart. DDR and Cache initialized */ -#define CONFIG_SKIP_LOWLEVEL_INIT - -/*-------------------------------------------- - * CPU configuration - */ -/* CPU Timer rate */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 50000000 - -/*---------------------------------------------------------------------- - * Memory Layout - */ - -/* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 Mbytes */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - 0x1000) - -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_LOAD_ADDR 0x80500000 /* default load address */ - -/*---------------------------------------------------------------------- - * Commands - */ - -/*------------------------------------------------------------ - * Console Configuration - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* ------------------------------------------------- - * Environment - */ -#define CONFIG_ENV_SIZE 0x4000 - -/* --------------------------------------------------------------------- - * Board boot configuration - */ -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#endif /* __XILFPGA_CONFIG_H */ diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h deleted file mode 100644 index 730e874..0000000 --- a/include/configs/imx27lite-common.h +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Heiko Schocher - * - * based on: - * Copyright (C) 2009 Ilya Yanok - */ - -#ifndef __IMX27LITE_COMMON_CONFIG_H -#define __IMX27LITE_COMMON_CONFIG_H - -/* - * SoC Configuration - */ -#define CONFIG_MX27 -#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Lowlevel configuration - */ -#define SDRAM_ESDCFG_REGISTER_VAL(cas) \ - (ESDCFG_TRC(10) | \ - ESDCFG_TRCD(3) | \ - ESDCFG_TCAS(cas) | \ - ESDCFG_TRRD(1) | \ - ESDCFG_TRAS(5) | \ - ESDCFG_TWR | \ - ESDCFG_TMRD(2) | \ - ESDCFG_TRP(2) | \ - ESDCFG_TXP(3)) - -#define SDRAM_ESDCTL_REGISTER_VAL \ - (ESDCTL_PRCT(0) | \ - ESDCTL_BL | \ - ESDCTL_PWDT(0) | \ - ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ_32 | \ - ESDCTL_COL10 | \ - ESDCTL_ROW13 | \ - ESDCTL_SDE) - -#define SDRAM_ALL_VAL 0xf00 - -#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */ -#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000 - -#define MPCTL0_VAL 0x1ef15d5 - -#define SPCTL0_VAL 0x043a1c09 - -#define CSCR_VAL 0x33f08107 - -#define PCDR0_VAL 0x120470c3 -#define PCDR1_VAL 0x03030303 -#define PCCR0_VAL 0xffffffff -#define PCCR1_VAL 0xfffffffc - -#define AIPI1_PSR0_VAL 0x20040304 -#define AIPI1_PSR1_VAL 0xdffbfcfb -#define AIPI2_PSR0_VAL 0x07ffc200 -#define AIPI2_PSR1_VAL 0xffffffff - -/* - * Memory Info - */ -/* malloc() len */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 512 * 1024) -/* memtest start address */ -#define CONFIG_SYS_MEMTEST_START 0xA0000000 -#define CONFIG_SYS_MEMTEST_END 0xA1000000 /* 16MB RAM test */ -#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ - -/* - * Serial Driver info - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * Flash & Environment - */ -/* Use buffered writes (~10x faster) */ -/* Use hardware sector protection */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ -/* CS2 Base address */ -#define PHYS_FLASH_1 0xc0000000 -/* Flash Base for U-Boot */ -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT (PHYS_FLASH_SIZE / \ - CONFIG_SYS_FLASH_SECT_SZ) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f - -/* - * MTD - */ - -/* - * NAND - */ -#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0xd8000000 -#define CONFIG_JFFS2_NAND -#define CONFIG_MXC_NAND_HWECC - -/* - * U-Boot general configuration - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "kernel_addr_r=a0800000\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "rootpath=/opt/eldk-4.2-arm/arm\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm\0" \ - "bootcmd=run net_nfs\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) -#endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h deleted file mode 100644 index 0826195..0000000 --- a/include/configs/imx6-engicam.h +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Amarula Solutions B.V. - * Copyright (C) 2016 Engicam S.r.l. - * - * Configuration settings for the Engicam i.MX6 SOM Starter Kits. - */ - -#ifndef __IMX6_ENGICAM_CONFIG_H -#define __IMX6_ENGICAM_CONFIG_H - -#include -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - -/* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE SZ_128K - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Environment */ -#ifndef CONFIG_ENV_IS_NOWHERE -/* Environment in MMC */ -# if defined(CONFIG_ENV_IS_IN_MMC) -# define CONFIG_ENV_OFFSET 0x100000 -/* Environment in NAND */ -# elif defined(CONFIG_ENV_IS_IN_NAND) -# define CONFIG_ENV_OFFSET 0x400000 -# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -# endif -#endif - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "image=uImage\0" \ - "fit_image=fit.itb\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=" FDT_ADDR "\0" \ - "boot_fdt=try\0" \ - "mmcpart=1\0" \ - "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=5 root=${nandroot} ${mtdparts}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "loadfit=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${fit_image}\0" \ - "altbootcmd=run recoveryboot\0"\ - "fitboot=echo Booting FIT image from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "_mmcboot=run mmcargs; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadfit; then " \ - "run fitboot; " \ - "else " \ - "if run loadimage; then " \ - "run _mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi\0" \ - "nandboot=echo Booting from nand ...; " \ - "if mtdparts; then " \ - "echo Starting nand boot ...; " \ - "else " \ - "mtdparts default; " \ - "fi; " \ - "run ubiargs; " \ - "nand read ${loadaddr} kernel 0x800000; " \ - "nand read ${fdt_addr} dtb 0x100000; " \ - "bootm ${loadaddr} - ${fdt_addr}\0" \ - "recoveryboot=if test ${modeboot} = mmcboot; then " \ - "run mmcboot; " \ - "else " \ - "run nandboot; " \ - "fi\0" - -#define CONFIG_BOOTCOMMAND "run $modeboot" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -#ifdef CONFIG_MX6UL -# define DRAM_OFFSET(x) 0x87##x -# define FDT_ADDR __stringify(DRAM_OFFSET(800000)) -#else -# define DRAM_OFFSET(x) 0x1##x -# define FDT_ADDR __stringify(DRAM_OFFSET(8000000)) -#endif - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - -/* UART */ -#ifdef CONFIG_MXC_UART -# ifdef CONFIG_MX6UL -# define CONFIG_MXC_UART_BASE UART1_BASE -# else -# define CONFIG_MXC_UART_BASE UART4_BASE -# endif -#endif - -/* MMC */ -#ifdef CONFIG_FSL_USDHC -# define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* NAND */ -#ifdef CONFIG_NAND_MXS -# define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_BASE 0x40000000 -# define CONFIG_SYS_NAND_5_ADDR_CYCLE -# define CONFIG_SYS_NAND_ONFI_DETECTION -# define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -# define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 - -/* MTD device */ -#endif - -/* Ethernet */ -#ifdef CONFIG_FEC_MXC -# ifdef CONFIG_TARGET_MX6Q_ICORE_RQS -# define CONFIG_FEC_MXC_PHYADDR 3 -# define CONFIG_FEC_XCV_TYPE RGMII -# else -# define CONFIG_FEC_MXC_PHYADDR 0 -# define CONFIG_FEC_XCV_TYPE RMII -# endif -#endif - -/* Falcon Mode */ -#ifdef CONFIG_SPL_OS_BOOT -# define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -# define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -# define CONFIG_CMD_SPL -# define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 -# define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) - -/* MMC support: args@1MB kernel@2MB */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ -#endif - -/* Framebuffer */ -#ifdef CONFIG_VIDEO_IPUV3 -# define CONFIG_IMX_VIDEO_SKIP - -# define CONFIG_SPLASH_SCREEN -# define CONFIG_SPLASH_SCREEN_ALIGN -# define CONFIG_BMP_16BPP -# define CONFIG_VIDEO_BMP_RLE8 -# define CONFIG_VIDEO_LOGO -# define CONFIG_VIDEO_BMP_LOGO -#endif - -/* SPL */ -#ifdef CONFIG_SPL -# ifdef CONFIG_ENV_IS_IN_NAND -# define CONFIG_SPL_NAND_SUPPORT -# else -# define CONFIG_SPL_MMC_SUPPORT -# endif - -# include "imx6_spl.h" -#endif - -#endif /* __IMX6_ENGICAM_CONFIG_H */ diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h deleted file mode 100644 index d6b7477..0000000 --- a/include/configs/imx6_logic.h +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Logic PD, Inc. - * - * Configuration settings for the LogicPD i.MX6 SOM. - */ - -#ifndef __IMX6LOGIC_CONFIG_H -#define __IMX6LOGIC_CONFIG_H - -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONSOLE_DEV "ttymxc0" - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - - -/* Ethernet Configs */ -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "bootm_size=0x10000000\0" \ - "fdt_addr_r=0x13000000\0" \ - "ramdisk_addr_r=0x14000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_file=rootfs.cpio.uboot\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "mmcdev=1\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "nandroot=ubi0:rootfs rootfstype=ubifs\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate}" \ - " root=PARTUUID=${uuid} rootwait rw ${mtdparts} ${optargs}\0" \ - "nandargs=setenv bootargs console=${console},${baudrate}" \ - " ubi.mtd=fs root=${nandroot} ${mtdparts} ${optargs}\0" \ - "ramargs=setenv bootargs console=${console},${baudrate}" \ - " root=/dev/ram rw ${mtdparts} ${optargs}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...;" \ - " source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};" \ - " setenv kernelsize ${filesize}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdt_file}\0" \ - "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr_r}" \ - " ${ramdisk_file}; setenv ramdisksize ${filesize}\0" \ - "mmcboot=echo Booting from mmc...; run finduuid; run mmcargs;" \ - "run loadimage; run loadfdt; bootz ${loadaddr} - ${fdt_addr_r}\0" \ - "mmcramboot=run ramargs; run loadimage;" \ - " run loadfdt; run loadramdisk;" \ - " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ - "nandboot=echo Booting from nand ...; " \ - " run nandargs;" \ - " nand read ${loadaddr} kernel ${kernelsize};" \ - " nand read ${fdt_addr_r} dtb;" \ - " bootz ${loadaddr} - ${fdt_addr_r}\0" \ - "nandramboot=echo Booting RAMdisk from nand ...; " \ - " nand read ${ramdisk_addr_r} fs ${ramdisksize};" \ - " nand read ${loadaddr} kernel ${kernelsize};" \ - " nand read ${fdt_addr_r} dtb;" \ - " run ramargs;" \ - " bootz ${loadaddr} ${ramdisk_addr_r} ${fdt_addr_r}\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs" \ - " ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr_r} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "autoboot=mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" -#define CONFIG_BOOTCOMMAND \ - "run autoboot" - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (1024 * 1024) -#define CONFIG_ENV_OFFSET 0x400000 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00500000 - -/* MTD device */ - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* EEPROM contains serial no, MAC addr and other Logic PD info */ -#define CONFIG_I2C_EEPROM - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ -#endif - -/* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ - -#endif /* __IMX6LOGIC_CONFIG_H */ diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h deleted file mode 100644 index a223930..0000000 --- a/include/configs/imx6_spl.h +++ /dev/null @@ -1,91 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Gateworks Corporation - * Author: Tim Harvey - */ -#ifndef __IMX6_SPL_CONFIG_H -#define __IMX6_SPL_CONFIG_H - -#ifdef CONFIG_SPL - -#ifdef CONFIG_MX6_OCRAM_256KB -/* - * see Figure 8.4.1 in IMX6DQ Reference manuals: - * - IMX6DQ OCRAM (IRAM) is from 0x00907000 to 0x0093FFFF - * - BOOT ROM stack is at 0x0093FFB8 - * - if icache/dcache is enabled (eFuse/strapping controlled) then the - * IMX BOOT ROM will setup MMU table at 0x00938000, therefore we need to - * fit between 0x00907000 and 0x00938000. - * - Additionally the BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00908000 - 0x00938000 - * or 192KB - */ -#define CONFIG_SPL_MAX_SIZE 0x30000 -#define CONFIG_SPL_STACK 0x0093FFB8 -/* - * Pad SPL to 196KB (4KB header + 192KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x31000 -#else -/* - * see Figure 8-3 in IMX6SDL Reference manuals: - * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF - * - BOOT ROM stack is at 0x0091FFB8 - * - if icache/dcache is enabled (eFuse/strapping controlled) then the - * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to - * fit between 0x00907000 and 0x00918000. - * - Additionally the BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00908000 - 0x00918000 - * or 64KB - */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_STACK 0x0091FFB8 -/* - * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x11000 - -#endif - -/* MMC support */ -#if defined(CONFIG_SPL_MMC_SUPPORT) -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ -#endif - -/* SATA support */ -#if defined(CONFIG_SPL_SATA_SUPPORT) -#define CONFIG_SPL_SATA_BOOT_DEVICE 0 -#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1 -#endif - -/* Define the payload for FAT/EXT support */ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -# ifdef CONFIG_OF_CONTROL -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -# else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -# endif -#endif - -#if defined(CONFIG_MX6SX) || defined(CONFIG_MX6SL) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define CONFIG_SPL_BSS_START_ADDR 0x88200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#else -#define CONFIG_SPL_BSS_START_ADDR 0x18200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x18300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#endif -#endif - -#endif diff --git a/include/configs/imx6dl-mamoj.h b/include/configs/imx6dl-mamoj.h deleted file mode 100644 index 7605e14..0000000 --- a/include/configs/imx6dl-mamoj.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Simone CIANNI - * Copyright (C) 2018 Raffaele RECALCATI - * Copyright (C) 2018 Jagan Teki - * - * Configuration settings for the BTicion i.MX6DL Mamoj board. - */ - -#ifndef __IMX6DL_MAMOJ_CONFIG_H -#define __IMX6DL_MAMOJ_CONFIG_H - -#include -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - -/* Total Size of Environment Sector */ -#define CONFIG_ENV_SIZE SZ_128K - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Environment */ -#ifndef CONFIG_ENV_IS_NOWHERE -/* Environment in MMC */ -# if defined(CONFIG_ENV_IS_IN_MMC) -# define CONFIG_ENV_OFFSET 0x100000 -# endif -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "scriptaddr=0x14000000\0" \ - "fdt_addr_r=0x13000000\0" \ - "kernel_addr_r=0x10008000\0" \ - "fdt_high=0xffffffff\0" \ - "dfu_alt_info_spl=spl raw 0x2 0x400\0" \ - "dfu_alt_info_uboot=u-boot raw 0x8a 0x11400\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 2) - -#include -#endif - -/* UART */ -#define CONFIG_MXC_UART_BASE UART3_BASE - -/* MMC */ -#define CONFIG_SYS_MMC_ENV_DEV 2 - -/* Ethernet */ -#define CONFIG_FEC_MXC_PHYADDR 1 - -/* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* Falcon */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_CMD_SPL -#define CONFIG_SYS_SPL_ARGS_ADDR 0x13000000 -#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) - -/* MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - -/* SPL */ -#include "imx6_spl.h" - -#endif /* __IMX6DL_MAMOJ_CONFIG_H */ diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h deleted file mode 100644 index 7ef7017..0000000 --- a/include/configs/imx7_spl.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SPL definitions for the i.MX7 SPL - * - * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com - * - * Author: Uri Mashiach - */ - -#ifndef __IMX7_SPL_CONFIG_H -#define __IMX7_SPL_CONFIG_H - -#ifdef CONFIG_SPL -/* - * see figure 6-22 in i.MX 7Dual/Solo Reference manuals: - * - IMX7D/S OCRAM free area RAM (OCRAM) is from 0x00910000 to - * 0x00946C00. - * - Set the stack at the end of the free area section, at 0x00946BB8. - * - The BOOT ROM loads what they consider the firmware image - * which consists of a 4K header in front of us that contains the IVT, DCD - * and some padding thus 'our' max size is really 0x00946BB8 - 0x00911000. - * 64KB is more then enough for the SPL. - */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_STACK 0x00946BB8 -/* - * Pad SPL to 68KB (4KB header + 64KB max size). This allows to write the - * SPL/U-Boot combination generated with u-boot-with-spl.imx directly to a - * boot media (given that boot media specific offset is configured properly). - */ -#define CONFIG_SPL_PAD_TO 0x11000 - -/* MMC support */ -#if defined(CONFIG_SPL_MMC_SUPPORT) -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ -#endif - -/* Define the payload for FAT/EXT support */ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -# ifdef CONFIG_OF_CONTROL -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img" -# else -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -# endif -#endif - -#define CONFIG_SPL_BSS_START_ADDR 0x88200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x88300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -#endif /* CONFIG_SPL */ - -#endif /* __IMX7_SPL_CONFIG_H */ diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h deleted file mode 100644 index a9d99ec..0000000 --- a/include/configs/imx8mm_evk.h +++ /dev/null @@ -1,153 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#ifndef __IMX8MM_EVK_H -#define __IMX8MM_EVK_H - -#include -#include - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CSF_SIZE SZ_8K -#endif - -#define CONFIG_SPL_MAX_SIZE (148 * 1024) -#define CONFIG_SYS_MONITOR_LEN SZ_512K -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_UBOOT_BASE \ - (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_STACK 0x920000 -#define CONFIG_SPL_BSS_START_ADDR 0x910000 -#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K /* 512 KB */ - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x930000 -/* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#endif - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=Image.itb\0" \ - "console=ttymxc1,115200 earlycon=ec_imx6q,0x30890000,115200\0" \ - "fdt_addr=0x43000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "boot_fit=try\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "initrd_addr=0x43800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ - "bootm ${loadaddr}; " \ - "else " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fit} = yes || test ${boot_fit} = try; then " \ - "bootm ${loadaddr}; " \ - "else " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "fi;" - -/* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x200000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_ENV_OVERWRITE -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (64 * SZ_64K) -#endif -#define CONFIG_ENV_SIZE SZ_4K -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_SIZE >> 1)) - -#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR - -/* Monitor Command Prompt */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* USDHC */ -#define CONFIG_FSL_USDHC - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_SYS_I2C_SPEED 100000 - -#endif diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h deleted file mode 100644 index d4d8d20..0000000 --- a/include/configs/imx8mq_evk.h +++ /dev/null @@ -1,233 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __IMX8M_EVK_H -#define __IMX8M_EVK_H - -#include -#include - -#define CONFIG_SPL_MAX_SIZE (124 * 1024) -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 - -#ifdef CONFIG_SPL_BUILD -/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ -#define CONFIG_SPL_WATCHDOG_SUPPORT -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x187FF0 -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_BSS_START_ADDR 0x00180000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ -#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 - -/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ -#define CONFIG_MALLOC_F_ADDR 0x182000 -/* For RAW image gives a error info not panic */ -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#undef CONFIG_DM_MMC -#undef CONFIG_DM_PMIC -#undef CONFIG_DM_PMIC_PFUZE100 - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#endif - -#define CONFIG_REMAKE_ELF - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -#undef CONFIG_CMD_EXPORTENV -#undef CONFIG_CMD_IMPORTENV -#undef CONFIG_CMD_IMLS - -#undef CONFIG_CMD_CRC32 - -/* ENET Config */ -/* ENET1 */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_MII -#define CONFIG_ETHPRIME "FEC" - -#define CONFIG_FEC_MXC -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#define FEC_QUIRK_ENET_MAC - -#define CONFIG_PHY_GIGE -#define IMX_FEC_BASE 0x30BE0000 - -#define CONFIG_PHYLIB -#define CONFIG_PHY_ATHEROS -#endif - -#define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ - "rdinit=/linuxrc " \ - "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ - "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ - "g_mass_storage.iSerialNumber=\"\" "\ - "clk_ignore_unused "\ - "\0" \ - "initrd_addr=0x43800000\0" \ - "initrd_high=0xffffffff\0" \ - "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_MFG_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=Image\0" \ - "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \ - "fdt_addr=0x43000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "boot_fdt=try\0" \ - "fdt_file=fsl-imx8mq-evk.dtb\0" \ - "initrd_addr=0x43800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "else " \ - "echo wait for boot; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "else " \ - "booti; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else booti ${loadaddr} - ${fdt_addr}; fi" - -/* Link Definitions */ -#define CONFIG_LOADADDR 0x40480000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_OFFSET (64 * SZ_64K) -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM 0x40000000 -#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - (PHYS_SDRAM_SIZE >> 1)) - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR - -/* Monitor Command Prompt */ -#undef CONFIG_SYS_PROMPT -#define CONFIG_SYS_PROMPT "u-boot=> " -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -#define CONFIG_IMX_BOOTAUX - -#define CONFIG_CMD_MMC - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_MXC_GPIO - -#define CONFIG_CMD_FUSE - -/* I2C Configs */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_OF_SYSTEM_SETUP - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_DM_PMIC -#endif - -#endif diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h deleted file mode 100644 index 2b8f85d..0000000 --- a/include/configs/imx8qm_mek.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __IMX8QM_MEK_H -#define __IMX8QM_MEK_H - -#include -#include - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 - -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ -#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 - -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#define CONFIG_OF_EMBED -#endif - -#define CONFIG_REMAKE_ELF - -#define CONFIG_BOARD_EARLY_INIT_F - -/* Flat Device Tree Definitions */ -#define CONFIG_OF_BOARD_SETUP - -#undef CONFIG_CMD_EXPORTENV -#undef CONFIG_CMD_IMPORTENV -#undef CONFIG_CMD_IMLS - -#undef CONFIG_CMD_CRC32 - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5B010000 -#define USDHC2_BASE_ADDR 0x5B020000 -#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=Image\0" \ - "panel=NULL\0" \ - "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "boot_fdt=try\0" \ - "fdt_file=imx8qm-mek.dtb\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "else " \ - "echo wait for boot; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "else " \ - "booti; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else booti ${loadaddr} - ${fdt_addr}; fi" - -/* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - -/* Default environment is in SD */ -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_OFFSET (64 * SZ_64K) -#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_2 0x880000000 -#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ -#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */ - -/* Serial */ -#define CONFIG_BAUDRATE 115200 - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 8000000 /* 8MHz */ - -/* Networking */ -#define CONFIG_FEC_XCV_TYPE RGMII -#define FEC_QUIRK_ENET_MAC - -#endif /* __IMX8QM_MEK_H */ diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h deleted file mode 100644 index 872805c..0000000 --- a/include/configs/imx8qxp_mek.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __IMX8QXP_MEK_H -#define __IMX8QXP_MEK_H - -#include -#include - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_MAX_SIZE (124 * 1024) -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800 -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 - -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_STACK 0x013E000 -#define CONFIG_SPL_BSS_START_ADDR 0x00128000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */ -#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 -#define CONFIG_MALLOC_F_ADDR 0x00120000 - -#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE - -#define CONFIG_SPL_ABORT_ON_RAW_IMAGE - -#define CONFIG_OF_EMBED -#endif - -#define CONFIG_REMAKE_ELF - -#define CONFIG_BOARD_EARLY_INIT_F - -/* Flat Device Tree Definitions */ -#define CONFIG_OF_BOARD_SETUP - -#undef CONFIG_CMD_EXPORTENV -#undef CONFIG_CMD_IMPORTENV -#undef CONFIG_CMD_IMLS - -#undef CONFIG_CMD_CRC32 - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define USDHC1_BASE_ADDR 0x5B010000 -#define USDHC2_BASE_ADDR 0x5B020000 - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=Image\0" \ - "panel=NULL\0" \ - "console=ttyLP0,${baudrate} earlycon\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "boot_fdt=try\0" \ - "fdt_file=imx8qxp-mek.dtb\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "else " \ - "echo wait for boot; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${loadaddr} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "booti ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "else " \ - "booti; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else booti ${loadaddr} - ${fdt_addr}; fi" - -/* Link Definitions */ -#define CONFIG_LOADADDR 0x80280000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_INIT_SP_ADDR 0x80200000 - -/* Default environment is in SD */ -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_OFFSET (64 * SZ_64K) -#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ -#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024) - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_2 0x880000000 -#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ -/* LPDDR4 board total DDR is 3GB */ -#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ - -/* Serial */ -#define CONFIG_BAUDRATE 115200 - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 8000000 /* 8MHz */ - -#ifndef CONFIG_DM_PCA953X -#define CONFIG_PCA953X -#define CONFIG_CMD_PCA953X -#define CONFIG_CMD_PCA953X_INFO -#endif - -/* Networking */ -#define CONFIG_FEC_XCV_TYPE RGMII -#define FEC_QUIRK_ENET_MAC - -#endif /* __IMX8QXP_MEK_H */ diff --git a/include/configs/integrator-common.h b/include/configs/integrator-common.h deleted file mode 100644 index 9223fc2..0000000 --- a/include/configs/integrator-common.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Linaro - * Linus Walleij - * Common ARM Integrator configuration settings - */ - -#define CONFIG_SYS_MEMTEST_START 0x100000 -#define CONFIG_SYS_MEMTEST_END 0x10000000 -#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ -#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* Size of malloc() pool */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * There are various dependencies on the core module (CM) fitted - * Users should refer to their CM user guide - */ -#include "armcoremodule.h" - -/* - * Initialize and remap the core module, use SPD to detect memory size - * If CONFIG_SKIP_LOWLEVEL_INIT is not defined & - * the core module has a CM_INIT register - * then the U-Boot initialisation code will - * e.g. ARM Boot Monitor or pre-loader is repeated once - * (to re-initialise any existing CM_INIT settings to safe values). - * - * This is usually not the desired behaviour since the platform - * will either reboot into the ARM monitor (or pre-loader) - * or continuously cycle thru it without U-Boot running, - * depending upon the setting of Integrator/CP switch S2-4. - * - * However it may be needed if Integrator/CP switch S2-1 - * is set OFF to boot direct into U-Boot. - * In that case comment out the line below. - */ -#define CONFIG_CM_INIT -#define CONFIG_CM_REMAP -#define CONFIG_CM_SPD_DETECT - -/* - * The ARM boot monitor initializes the board. - * However, the default U-Boot code also performs the initialization. - * If desired, this can be prevented by defining SKIP_LOWLEVEL_INIT - * - see documentation supplied with board for details of how to choose the - * image to run at reset/power up - * e.g. whether the ARM Boot Monitor runs before U-Boot - */ -/* #define CONFIG_SKIP_LOWLEVEL_INIT */ - -/* - * The ARM boot monitor does not relocate U-Boot. - * However, the default U-Boot code performs the relocation check, - * and may relocate the code if the memory map is changed. - * If necessary this can be prevented by defining SKIP_RELOCATE_UBOOT - */ -/* #define SKIP_CONFIG_RELOCATE_UBOOT */ - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/* - * FLASH and environment organization - * Top varies according to amount fitted - * Reserve top 4 blocks of flash - * - ARM Boot Monitor - * - Unused - * - SIB block - * - U-Boot environment - */ -#define CONFIG_SYS_FLASH_BASE 0x24000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -/* Timeout values in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h deleted file mode 100644 index 4a9c60d..0000000 --- a/include/configs/integratorap.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * Configuration for Integrator AP board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "integrator-common.h" - -/* Integrator/AP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ -#define CONFIG_BOOTCOMMAND "" - -/* Flash settings */ -#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_ENV_SIZE 32768 - -/*----------------------------------------------------------------------- - * PCI definitions - */ - -#define CONFIG_TULIP -#define CONFIG_EEPRO100 -#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - -/*----------------------------------------------------------------------- - * There are various dependencies on the core module (CM) fitted - * Users should refer to their CM user guide - * - when porting adjust u-boot/Makefile accordingly - * to define the necessary CONFIG_ s for the CM involved - * see e.g. integratorcp_CM926EJ-S_config - */ -#include "armcoremodule.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h deleted file mode 100644 index 56931b7..0000000 --- a/include/configs/integratorcp.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Texas Instruments. - * Kshitij Gupta - * Configuation settings for the TI OMAP Innovator board. - * - * (C) Copyright 2004 - * ARM Ltd. - * Philippe Robin, - * Configuration for Compact Integrator board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "integrator-common.h" - -/* Integrator CP-specific configuration */ -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer 1 is clocked at 1Mhz */ - -/* - * Hardware drivers - */ -#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT -#define CONFIG_SMC91111_BASE 0xC8000000 -#undef CONFIG_SMC91111_EXT_PHY - -/* - * Command line configuration. - */ -#define CONFIG_BOOTCOMMAND "tftpboot ; bootm" -#define CONFIG_SERVERIP 192.168.1.100 -#define CONFIG_IPADDR 192.168.1.104 -#define CONFIG_BOOTFILE "uImage" - -/* - * Miscellaneous configurable options - */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 -#define CONFIG_SYS_MONITOR_LEN 0x00100000 - -/* - * Move up the U-Boot & monitor area if more flash is fitted. - * If this U-Boot is to be run on Integrators with varying flash sizes, - * drivers/mtd/cfi_flash.c::flash_init() can read the Integrator CP_FLASHPROG - * register and dynamically assign CONFIG_ENV_ADDR & CONFIG_SYS_MONITOR_BASE - * - CONFIG_SYS_MONITOR_BASE is set to indicate that the environment is not - * embedded in the boot monitor(s) area - */ -#if ( PHYS_FLASH_SIZE == 0x04000000 ) - -#define CONFIG_ENV_ADDR 0x27F00000 -#define CONFIG_SYS_MONITOR_BASE 0x27F40000 - -#elif (PHYS_FLASH_SIZE == 0x02000000 ) - -#define CONFIG_ENV_ADDR 0x25F00000 -#define CONFIG_SYS_MONITOR_BASE 0x25F40000 - -#else - -#define CONFIG_ENV_ADDR 0x24F00000 -#define CONFIG_SYS_MONITOR_BASE 0x27F40000 - -#endif - -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ -#define CONFIG_ENV_SIZE 8192 /* 8KB */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/iot_devkit.h b/include/configs/iot_devkit.h deleted file mode 100644 index 1ba69d9..0000000 --- a/include/configs/iot_devkit.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Synopsys, Inc. All rights reserved. - */ - -#ifndef _CONFIG_IOT_DEVKIT_H_ -#define _CONFIG_IOT_DEVKIT_H_ - -#include - -/* - * MEMORY MAP - * - * eFlash: 0x0000_0000 - 0x0008_0000 (512K) - * ICCM: 0x2000_0000 - 0x2004_0000 (256K) - * SRAM: 0x3000_0000 - 0x3002_0000 (128K) - * DCCM: 0x8000_0000 - 0x8002_0000 (128K) - * Note: only data goes here, as IFQ cannot fetch instructions from DCCM - * - * - * RAM PARTITIONING - * - * +-----------+----------+---------------------+-------------+ - * | <-- Stack | .data | Malloc | Environment | - * +-----------+----------+---------------------+-------------+ - * : : : :\___________/ - * : : : : | - * : : : : CONFIG_ENV_SIZE - * : : \____________________/ - * : : | - * : : CONFIG_SYS_MALLOC_LEN - * : : - * : Specified explicitly by CONFIG_SYS_INIT_SP_ADDR - * : - * Specified explicitly by CONFIG_SYS_SDRAM_BASE - * - * NOTES: - * - Stack starts from CONFIG_SYS_INIT_SP_ADDR and grows down, - * i.e. towards CONFIG_SYS_SDRAM_BASE but nothing stops it from crossing - * that CONFIG_SYS_SDRAM_BASE in which case data won't be really saved on - * stack any longer and values popped from stack will contain garbage - * leading to unexpected behavior, typically but not limited to: - * - "Returning" back to bogus caller function - * - Reading data from weird addresses - */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define SRAM_BASE 0x30000000 -#define SRAM_SIZE SZ_128K - -#define DCCM_BASE 0x80000000 -#define DCCM_SIZE SZ_128K - -#define CONFIG_SYS_SDRAM_BASE DCCM_BASE -#define CONFIG_SYS_SDRAM_SIZE DCCM_SIZE - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - -#define CONFIG_SYS_MALLOC_LEN SZ_64K -#define CONFIG_SYS_BOOTM_LEN SZ_128K -#define CONFIG_SYS_LOAD_ADDR SRAM_BASE - -#define ROM_BASE CONFIG_SYS_MONITOR_BASE -#define ROM_SIZE SZ_256K - -#define RAM_DATA_BASE CONFIG_SYS_INIT_SP_ADDR -#define RAM_DATA_SIZE CONFIG_SYS_SDRAM_SIZE - \ - (CONFIG_SYS_INIT_SP_ADDR - \ - CONFIG_SYS_SDRAM_BASE) - \ - CONFIG_SYS_MALLOC_LEN - \ - CONFIG_ENV_SIZE - -/* - * Environment - */ -#define CONFIG_BOOTFILE "app.bin" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#endif /* _CONFIG_IOT_DEVKIT_H_ */ diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h deleted file mode 100644 index 639d87a..0000000 --- a/include/configs/j721e_evm.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration header file for K3 J721E EVM - * - * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ - * Lokesh Vutla - */ - -#ifndef __CONFIG_J721E_EVM_H -#define __CONFIG_J721E_EVM_H - -#include -#include -#include -#include -#include - -#define CONFIG_ENV_SIZE (128 << 10) - -/* DDR Configuration */ -#define CONFIG_SYS_SDRAM_BASE1 0x880000000 - -/* SPL Loader Configuration */ -#ifdef CONFIG_TARGET_J721E_A72_EVM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SPL_TEXT_BASE + \ - CONFIG_SYS_K3_NON_SECURE_MSRAM_SIZE) -#else -/* - * Maximum size in memory allocated to the SPL BSS. Keep it as tight as - * possible (to allow the build to go through), as this directly affects - * our memory footprint. The less we use for BSS the more we have available - * for everything else. - */ -#define CONFIG_SPL_BSS_MAX_SIZE 0xA000 -/* - * Link BSS to be within SPL in a dedicated region located near the top of - * the MCU SRAM, this way making it available also before relocation. Note - * that we are not using the actual top of the MCU SRAM as there is a memory - * location filled in by the boot ROM that we want to read out without any - * interference from the C context. - */ -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX -\ - CONFIG_SPL_BSS_MAX_SIZE) -/* Set the stack right below the SPL BSS section */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_BSS_START_ADDR -/* Configure R5 SPL post-relocation malloc pool in DDR */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_16M -#endif - -#ifdef CONFIG_SYS_K3_SPL_ATF -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "tispl.bin" -#endif - -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE - -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_CQSPI_REF_CLK 133333333 - -/* HyperFlash related configuration */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 - -/* U-Boot general configuration */ -#define EXTRA_ENV_J721E_BOARD_SETTINGS \ - "default_device_tree=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "findfdt=setenv fdtfile ${default_device_tree}\0" \ - "loadaddr=0x80080000\0" \ - "fdtaddr=0x82000000\0" \ - "overlayaddr=0x83000000\0" \ - "name_kern=Image\0" \ - "console=ttyS2,115200n8\0" \ - "args_all=setenv optargs earlycon=ns16550a,mmio32,0x02800000\0" \ - "run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}\0" - -/* U-Boot MMC-specific configuration */ -#define EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ - "boot=mmc\0" \ - "mmcdev=1\0" \ - "bootpart=1:2\0" \ - "bootdir=/boot\0" \ - "rd_spec=-\0" \ - "init_mmc=run args_all args_mmc\0" \ - "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "get_overlay_mmc=" \ - "fdt address ${fdtaddr};" \ - "fdt resize 0x100000;" \ - "for overlay in $name_overlays;" \ - "do;" \ - "load mmc ${bootpart} ${overlayaddr} ${bootdir}/${overlay} && " \ - "fdt apply ${overlayaddr};" \ - "done;\0" \ - "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ - "${bootdir}/${name_kern}\0" - -#ifdef DEFAULT_RPROCS -#undef DEFAULT_RPROCS -#endif -#define DEFAULT_RPROCS "" \ - "3 /lib/firmware/j7-main-r5f0_1-fw " \ - "4 /lib/firmware/j7-main-r5f1_0-fw " \ - "6 /lib/firmware/j7-c66_0-fw " \ - "7 /lib/firmware/j7-c66_1-fw " \ - "8 /lib/firmware/j7-c71_0-fw " - -/* Incorporate settings into the U-Boot environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_MMC_TI_ARGS \ - EXTRA_ENV_J721E_BOARD_SETTINGS \ - EXTRA_ENV_J721E_BOARD_SETTINGS_MMC \ - EXTRA_ENV_RPROC_SETTINGS \ - DEFAULT_UFS_TI_ARGS - -/* Now for the remaining common defines */ -#include - -#endif /* __CONFIG_J721E_EVM_H */ diff --git a/include/configs/jetson-tk1.h b/include/configs/jetson-tk1.h deleted file mode 100644 index 6504469..0000000 --- a/include/configs/jetson-tk1.h +++ /dev/null @@ -1,36 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Jetson TK1" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -/* Reserve top 1M for secure RAM */ -#define CONFIG_ARMV7_SECURE_BASE 0xfff00000 -#define CONFIG_ARMV7_SECURE_RESERVE_SIZE 0x00100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h deleted file mode 100644 index 5471274..0000000 --- a/include/configs/k2e_evm.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration header file for TI's k2e-evm - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - */ - -#ifndef __CONFIG_K2E_EVM_H -#define __CONFIG_K2E_EVM_H - -#include - -/* Platform type */ -#define CONFIG_SOC_K2E - -#ifdef CONFIG_TI_SECURE_DEVICE -#define DEFAULT_SEC_BOOT_ENV \ - DEFAULT_FIT_TI_ARGS \ - "findfdt=setenv fdtfile ${name_fdt}\0" -#else -#define DEFAULT_SEC_BOOT_ENV -#endif - -/* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ - DEFAULT_FW_INITRAMFS_BOOT_ENV \ - DEFAULT_SEC_BOOT_ENV \ - "boot=ubi\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=keystone-k2e-evm.dtb\0" \ - "name_mon=skern-k2e.bin\0" \ - "name_ubi=k2e-evm-ubifs.ubi\0" \ - "name_uboot=u-boot-spi-k2e-evm.gph\0" \ - "name_fs=arago-console-image-k2e-evm.cpio.gz\0" - -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_OFFSET 0x100000 - -#include - -#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS - -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - -/* Network */ -#define CONFIG_KSNET_NETCP_V1_5 -#define CONFIG_KSNET_CPSW_NUM_PORTS 9 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE - -#define CONFIG_DDR_SPD - -#endif /* __CONFIG_K2E_EVM_H */ diff --git a/include/configs/k2g_evm.h b/include/configs/k2g_evm.h deleted file mode 100644 index b39e956..0000000 --- a/include/configs/k2g_evm.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration header file for TI's k2g-evm - * - * (C) Copyright 2015 - * Texas Instruments Incorporated, - */ - -#ifndef __CONFIG_K2G_EVM_H -#define __CONFIG_K2G_EVM_H - -#include -#include - -/* Platform type */ -#define CONFIG_SOC_K2G - -/* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ - DEFAULT_MMC_TI_ARGS \ - DEFAULT_PMMC_BOOT_ENV \ - DEFAULT_FW_INITRAMFS_BOOT_ENV \ - DEFAULT_FIT_TI_ARGS \ - "boot=mmc\0" \ - "console=ttyS0,115200n8\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "rd_spec=-\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "findfdt="\ - "if test $board_name = 66AK2GGP; then " \ - "setenv name_fdt keystone-k2g-evm.dtb; " \ - "else if test $board_name = 66AK2GG1; then " \ - "setenv name_fdt keystone-k2g-evm.dtb; " \ - "else if test $board_name = 66AK2GIC; then " \ - "setenv name_fdt keystone-k2g-ice.dtb; " \ - "else if test $name_fdt = undefined; then " \ - "echo WARNING: Could not determine device tree to use;"\ - "fi;fi;fi;fi; setenv fdtfile ${name_fdt}\0" \ - "name_mon=skern-k2g.bin\0" \ - "name_ubi=k2g-evm-ubifs.ubi\0" \ - "name_uboot=u-boot-spi-k2g-evm.gph\0" \ - "init_mmc=run args_all args_mmc\0" \ - "init_fw_rd_mmc=load mmc ${bootpart} ${rdaddr} " \ - "${bootdir}/${name_fw_rd}; run set_rd_spec\0" \ - "soc_variant=k2g\0" \ - "get_fdt_mmc=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${name_fdt}\0"\ - "get_kern_mmc=load mmc ${bootpart} ${loadaddr} " \ - "${bootdir}/${name_kern}\0" \ - "get_mon_mmc=load mmc ${bootpart} ${addr_mon} ${bootdir}/${name_mon}\0"\ - "name_fs=arago-base-tisdk-image-k2g-evm.cpio\0" - -#ifndef CONFIG_TI_SECURE_DEVICE -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "run envboot; " \ - "run init_${boot}; " \ - "run get_mon_${boot} run_mon; " \ - "run set_name_pmmc get_pmmc_${boot} run_pmmc; " \ - "run get_kern_${boot}; " \ - "run init_fw_rd_${boot}; " \ - "run get_fdt_${boot}; " \ - "run run_kern" -#else -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "run envboot; " \ - "run run_mon_hs; " \ - "run init_${boot}; " \ - "run get_fit_${boot}; " \ - "bootm ${addr_fit}#${name_fdt}" -#endif - -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - -/* Network */ -#define CONFIG_KSNET_NETCP_V1_5 -#define CONFIG_KSNET_CPSW_NUM_PORTS 2 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE -#define PHY_ANEG_TIMEOUT 10000 /* PHY needs longer aneg time */ - -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_CADENCE_QSPI -#define CONFIG_CQSPI_REF_CLK 384000000 -#endif - -#define SPI_MTD_PARTS KEYSTONE_SPI1_MTD_PARTS - -#include - -#endif /* __CONFIG_K2G_EVM_H */ diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h deleted file mode 100644 index d4f2e96..0000000 --- a/include/configs/k2hk_evm.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration header file for TI's k2hk-evm - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - */ - -#ifndef __CONFIG_K2HK_EVM_H -#define __CONFIG_K2HK_EVM_H - -#include - -/* Platform type */ -#define CONFIG_SOC_K2HK - -#ifdef CONFIG_TI_SECURE_DEVICE -#define DEFAULT_SEC_BOOT_ENV \ - DEFAULT_FIT_TI_ARGS \ - "findfdt=setenv fdtfile ${name_fdt}\0" -#else -#define DEFAULT_SEC_BOOT_ENV -#endif - -/* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ - DEFAULT_FW_INITRAMFS_BOOT_ENV \ - DEFAULT_SEC_BOOT_ENV \ - "boot=ubi\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,2048\0" \ - "name_fdt=keystone-k2hk-evm.dtb\0" \ - "name_mon=skern-k2hk.bin\0" \ - "name_ubi=k2hk-evm-ubifs.ubi\0" \ - "name_uboot=u-boot-spi-k2hk-evm.gph\0" \ - "name_fs=arago-console-image-k2hk-evm.cpio.gz\0" - -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_OFFSET 0x100000 - -#include - -#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS - -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_2K - -/* Network */ -#define CONFIG_KSNET_NETCP_V1_0 -#define CONFIG_KSNET_CPSW_NUM_PORTS 5 - -#define CONFIG_DDR_SPD - -#endif /* __CONFIG_K2HK_EVM_H */ diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h deleted file mode 100644 index cfdb36e..0000000 --- a/include/configs/k2l_evm.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration header file for TI's k2l-evm - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - */ - -#ifndef __CONFIG_K2L_EVM_H -#define __CONFIG_K2L_EVM_H - -#include - -/* Platform type */ -#define CONFIG_SOC_K2L - -#ifdef CONFIG_TI_SECURE_DEVICE -#define DEFAULT_SEC_BOOT_ENV \ - DEFAULT_FIT_TI_ARGS \ - "findfdt=setenv fdtfile ${name_fdt}\0" -#else -#define DEFAULT_SEC_BOOT_ENV -#endif - -/* U-Boot general configuration */ -#define CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ - DEFAULT_FW_INITRAMFS_BOOT_ENV \ - DEFAULT_SEC_BOOT_ENV \ - "boot=ubi\0" \ - "args_ubi=setenv bootargs ${bootargs} rootfstype=ubifs " \ - "root=ubi0:rootfs rootflags=sync rw ubi.mtd=ubifs,4096\0" \ - "name_fdt=keystone-k2l-evm.dtb\0" \ - "name_mon=skern-k2l.bin\0" \ - "name_ubi=k2l-evm-ubifs.ubi\0" \ - "name_uboot=u-boot-spi-k2l-evm.gph\0" \ - "name_fs=arago-console-image-k2l-evm.cpio.gz\0" - -#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ -#define CONFIG_ENV_OFFSET 0x100000 - -#include - -#define SPI_MTD_PARTS KEYSTONE_SPI0_MTD_PARTS - -/* NAND Configuration */ -#define CONFIG_SYS_NAND_PAGE_4K - -/* Network */ -#define CONFIG_KSNET_NETCP_V1_5 -#define CONFIG_KSNET_CPSW_NUM_PORTS 5 -#define CONFIG_KSNET_MDIO_PHY_CONFIG_ENABLE - -#endif /* __CONFIG_K2L_EVM_H */ diff --git a/include/configs/kc1.h b/include/configs/kc1.h deleted file mode 100644 index e3a219c..0000000 --- a/include/configs/kc1.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Amazon Kindle Fire (first generation) codename kc1 config - * - * Copyright (C) 2016 Paul Kocialkowski - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -/* - * Build - */ - -/* - * CPU - */ - -#define CONFIG_SYS_L2_PL310 1 -#define CONFIG_SYS_PL310_BASE 0x48242000 - -/* - * Board - */ - -/* - * Clocks - */ - -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 - -/* - * DRAM - */ - -/* - * Memory - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) - -/* - * I2C - */ - -#define CONFIG_SYS_I2C -#define CONFIG_I2C_MULTI_BUS - -/* - * Power - */ - -#define CONFIG_TWL6030_POWER - -/* - * Input - */ - -#define CONFIG_TWL6030_INPUT - -/* - * SPL - */ - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) - -/* - * Console - */ - -#define CONFIG_SYS_CBSIZE 512 - -/* - * Serial - */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 -#define CONFIG_SYS_NS16550_COM3 UART3_BASE - -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ - 115200 } - -/* - * USB gadget - */ - -/* - * Environment - */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x82000000\0" \ - "loadaddr=0x82000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "fdtaddr=0x88000000\0" \ - "ramdisk_addr_r=0x88080000\0" \ - "pxefile_addr_r=0x80100000\0" \ - "scriptaddr=0x80000000\0" \ - "bootm_size=0x10000000\0" \ - "boot_mmc_dev=0\0" \ - "kernel_mmc_part=7\0" \ - "recovery_mmc_part=5\0" \ - "fdtfile=omap4-kc1.dtb\0" \ - "bootfile=/boot/extlinux/extlinux.conf\0" \ - "bootargs=console=ttyO2,115200 mem=512M\0" - -/* - * ATAGs - */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* - * Boot - */ - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_BOOTCOMMAND \ - "setenv boot_mmc_part ${kernel_mmc_part}; " \ - "if test reboot-${reboot-mode} = reboot-r; then " \ - "echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \ - "if test reboot-${reboot-mode} = reboot-b; then " \ - "echo fastboot; fastboot 0; fi; " \ - "part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \ - "part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \ - "mmc dev ${boot_mmc_dev}; " \ - "mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \ - "bootm ${kernel_addr_r};" - -/* - * Defaults - */ - -#include - -#endif diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h deleted file mode 100644 index 8433d8e..0000000 --- a/include/configs/km/keymile-common.h +++ /dev/null @@ -1,199 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008-2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_KEYMILE_H -#define __CONFIG_KEYMILE_H - -/* - * Miscellaneous configurable options - */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_HUSH_INIT_VAR - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* UBI Support for all Keymile boards */ -#define CONFIG_MTD_CONCAT - -#ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS -#define CONFIG_KM_DEF_ENV_BOOTPARAMS \ - "actual_bank=0\0" -#endif - -#ifndef CONFIG_KM_DEF_NETDEV -#define CONFIG_KM_DEF_NETDEV \ - "netdev=eth0\0" -#endif - -#ifndef CONFIG_KM_UBI_PARTITION_NAME_BOOT -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */ - -#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS -#define CONFIG_KM_UBI_PART_BOOT_OPTS "" -#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ - -#ifndef CONFIG_KM_UBI_PARTITION_NAME_APP -/* one flash chip only called boot */ -/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ -# define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ - CONFIG_KM_UBI_PART_BOOT_OPTS -# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ - "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" -#else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ -/* two flash chips called boot and app */ -/* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ -/* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ -# define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ - CONFIG_KM_UBI_PART_BOOT_OPTS " " \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP -# define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ - "ubiattach=if test ${boot_bank} -eq 0; then; " \ - "ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "; else; " \ - "ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0" -#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */ - -#ifdef CONFIG_NAND_ECC_BCH -#define CONFIG_KM_UIMAGE_NAME "ecc_bch_uImage\0" -#define CONFIG_KM_ECC_MODE " eccmode=bch" -#else -#define CONFIG_KM_UIMAGE_NAME "uImage\0" -#define CONFIG_KM_ECC_MODE -#endif - -/* - * boottargets - * - set 'subbootcmds' - * - set 'bootcmd' and 'altbootcmd' - * available targets: - * - 'release': for a standalone system kernel/rootfs from flash - */ -#define CONFIG_KM_DEF_ENV_BOOTTARGETS \ - "subbootcmds=ubiattach ubicopy checkfdt cramfsloadfdt " \ - "set_fdthigh cramfsloadkernel flashargs add_default " \ - "addpanic boot\0" \ - "develop=" \ - "tftp 200000 scripts/develop-${arch}.txt && " \ - "env import -t 200000 ${filesize} && " \ - "run setup_debug_env\0" \ - "ramfs=" \ - "tftp 200000 scripts/ramfs-${arch}.txt && " \ - "env import -t 200000 ${filesize} && " \ - "run setup_debug_env\0" \ - "" - -/* - * bootargs - * - modify 'bootargs' - * - * - 'add_default': default bootargs common for all arm/ppc boards - * - 'addpanic': add kernel panic options - * - 'flashargs': defaults arguments for flash base boot - * - */ -#define CONFIG_KM_DEF_ENV_BOOTARGS \ - "add_default=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off:" \ - " console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \ - " mem=${kernelmem} init=${init}" \ - CONFIG_KM_ECC_MODE \ - " phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\ - " " CONFIG_KM_UBI_LINUX_MTD " " \ - CONFIG_KM_DEF_BOOT_ARGS_CPU \ - "\0" \ - "addpanic=" \ - "setenv bootargs ${bootargs} panic=1 panic_on_oops=1\0" \ - "flashargs=" \ - "setenv bootargs " \ - "root=mtdblock:rootfs${boot_bank} " \ - "rootfstype=squashfs ro\0" \ - "" - -/* - * flash_boot - * - commands for booting from flash - * - * - 'cramfsloadkernel': copy kernel from a cramfs to ram - * - 'ubiattach': attach ubi partition - * - 'ubicopy': copy ubi volume to ram - * - volume names: bootfs0, bootfs1, bootfs2, ... - * - * processor specific settings - * - 'cramfsloadfdt': copy fdt from a cramfs to ram - */ -#define CONFIG_KM_DEF_ENV_FLASH_BOOT \ - "cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0" \ - "cramfsloadkernel=cramfsload ${load_addr_r} ${uimage}\0" \ - "ubicopy=ubi read "__stringify(CONFIG_KM_CRAMFS_ADDR) \ - " bootfs${boot_bank}\0" \ - "uimage=" CONFIG_KM_UIMAGE_NAME \ - CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI - -/* - * constants - * - KM specific constants and commands - * - * - 'default': setup default environment - */ -#define CONFIG_KM_DEF_ENV_CONSTANTS \ - "backup_bank=0\0" \ - "release=run newenv; reset\0" \ - "pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0" \ - "testbootcmd=setenv boot_bank ${test_bank}; " \ - "run ${subbootcmds}; reset\0" \ - "" - -#ifndef CONFIG_KM_DEF_ENV -#define CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ENV_BOOTPARAMS \ - CONFIG_KM_DEF_NETDEV \ - CONFIG_KM_DEF_ENV_CPU \ - CONFIG_KM_DEF_ENV_BOOTTARGETS \ - CONFIG_KM_DEF_ENV_BOOTARGS \ - CONFIG_KM_DEF_ENV_FLASH_BOOT \ - CONFIG_KM_DEF_ENV_CONSTANTS \ - "altbootcmd=run bootcmd\0" \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "bootcmd=km_checkbidhwk && " \ - "setenv bootcmd \'if km_checktestboot; then; " \ - "setenv boot_bank ${test_bank}; else; " \ - "setenv boot_bank ${actual_bank}; fi;" \ - "run ${subbootcmds}; reset\' && " \ - "setenv altbootcmd \'setenv boot_bank ${backup_bank}; " \ - "run ${subbootcmds}; reset\' && " \ - "saveenv && saveenv && boot\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r="__stringify(CONFIG_KM_FDT_ADDR) "\0" \ - "init=/sbin/init-overlay.sh\0" \ - "load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \ - "load=tftpboot ${load_addr_r} ${u-boot}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "" -#endif /* CONFIG_KM_DEF_ENV */ - -#endif /* __CONFIG_KEYMILE_H */ diff --git a/include/configs/km/km-mpc8309.h b/include/configs/km/km-mpc8309.h deleted file mode 100644 index 9aaea27..0000000 --- a/include/configs/km/km-mpc8309.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* QE microcode/firmware address */ -/* between the u-boot partition and env */ -#ifndef CONFIG_SYS_QE_FW_ADDR -#define CONFIG_SYS_QE_FW_ADDR 0xF00C0000 -#endif - -/* - * System IO Config - */ -/* 0x14000180 SICR_1 */ -#define CONFIG_SYS_SICRL (0 \ - | SICR_1_UART1_UART1RTS \ - | SICR_1_I2C_CKSTOP \ - | SICR_1_IRQ_A_IRQ \ - | SICR_1_IRQ_B_IRQ \ - | SICR_1_GPIO_A_GPIO \ - | SICR_1_GPIO_B_GPIO \ - | SICR_1_GPIO_C_GPIO \ - | SICR_1_GPIO_D_GPIO \ - | SICR_1_GPIO_E_GPIO \ - | SICR_1_GPIO_F_GPIO \ - | SICR_1_USB_A_UART2S \ - | SICR_1_USB_B_UART2RTS \ - | SICR_1_FEC1_FEC1 \ - | SICR_1_FEC2_FEC2 \ - ) - -/* 0x00080400 SICR_2 */ -#define CONFIG_SYS_SICRH (0 \ - | SICR_2_FEC3_FEC3 \ - | SICR_2_HDLC1_A_HDLC1 \ - | SICR_2_ELBC_A_LA \ - | SICR_2_ELBC_B_LCLK \ - | SICR_2_HDLC2_A_HDLC2 \ - | SICR_2_USB_D_GPIO \ - | SICR_2_PCI_PCI \ - | SICR_2_HDLC1_B_HDLC1 \ - | SICR_2_HDLC1_C_HDLC1 \ - | SICR_2_HDLC2_B_GPIO \ - | SICR_2_HDLC2_C_HDLC2 \ - | SICR_2_QUIESCE_B \ - ) - -/* GPR_1 */ -#define CONFIG_SYS_GPR1 0x50008060 - -#define CONFIG_SYS_GP1DIR 0x00000000 -#define CONFIG_SYS_GP1ODR 0x00000000 -#define CONFIG_SYS_GP2DIR 0xFF000000 -#define CONFIG_SYS_GP2ODR 0x00000000 - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_RD_NEVER | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - -/* ethernet port connected to piggy (UEC2) */ -#define CONFIG_HAS_ETH1 -#define CONFIG_UEC_ETH2 -#define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ -#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 -#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC2_PHY_ADDR 0 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 diff --git a/include/configs/km/km-mpc832x.h b/include/configs/km/km-mpc832x.h deleted file mode 100644 index d7186ab..0000000 --- a/include/configs/km/km-mpc832x.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * High Level Configuration Options - */ -#define CONFIG_KM8321 /* Keymile PBEC8321 board specific */ - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 - -/* - * System IO Config - */ -#define CONFIG_SYS_SICRL SICRL_IRQ_CKS - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_PZ_MAXZ | \ - DDRCDR_NZ_MAXZ | \ - DDRCDR_M_ODR) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_32_BE | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((0x064 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x200 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ODT_WR_CFG | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -#define CONFIG_SYS_DDR_MODE 0x47860242 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 128 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 - diff --git a/include/configs/km/km-mpc8360.h b/include/configs/km/km-mpc8360.h deleted file mode 100644 index bdbb8bf..0000000 --- a/include/configs/km/km-mpc8360.h +++ /dev/null @@ -1,90 +0,0 @@ -/* KMBEC FPGA (PRIO) */ -#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000 -#define CONFIG_SYS_KMBEC_FPGA_SIZE 64 - -/* - * High Level Configuration Options - */ - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH1 /* GETH1 */ -#define UEC_VERBOSE_DEBUG 1 - -#define CONFIG_SYS_UEC1_UCC_NUM 3 /* UCC4 */ -#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ -#define CONFIG_SYS_UEC1_TX_CLK QE_CLK17 -#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH -#define CONFIG_SYS_UEC1_PHY_ADDR 0 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII -#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 - -/* - * System IO Setup - */ -#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI) - -/** - * DDR RAM settings - */ -#define CONFIG_SYS_DDR_SDRAM_CFG (\ - SDRAM_CFG_SDRAM_TYPE_DDR2 | \ - SDRAM_CFG_SREN | \ - SDRAM_CFG_HSE) - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 - -#define CONFIG_SYS_DDR_CLK_CNTL (\ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CONFIG_SYS_DDR_INTERVAL (\ - (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (0x203 << SDRAM_INTERVAL_REFINT_SHIFT)) - -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f - -#define CONFIG_SYS_DDRCDR (\ - DDRCDR_EN | \ - DDRCDR_Q_DRN) -#define CONFIG_SYS_DDR_MODE 0x47860452 -#define CONFIG_SYS_DDR_MODE2 0x8080c000 - -#define CONFIG_SYS_DDR_TIMING_0 (\ - (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \ - (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \ - (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \ - (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \ - (0 << TIMING_CFG0_WWT_SHIFT) | \ - (0 << TIMING_CFG0_RRT_SHIFT) | \ - (0 << TIMING_CFG0_WRT_SHIFT) | \ - (0 << TIMING_CFG0_RWT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \ - (2 << TIMING_CFG1_WRTORD_SHIFT) | \ - (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \ - (3 << TIMING_CFG1_WRREC_SHIFT) | \ - (7 << TIMING_CFG1_REFREC_SHIFT) | \ - (3 << TIMING_CFG1_ACTTORW_SHIFT) | \ - (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \ - (3 << TIMING_CFG1_PRETOACT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_2 (\ - (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \ - (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \ - (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \ - (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \ - (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \ - (5 << TIMING_CFG2_CPO_SHIFT) | \ - (0 << TIMING_CFG2_ADD_LAT_SHIFT)) - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 - -/* EEprom support */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * PAXE on the local bus CS3 - */ -#define CONFIG_SYS_PAXE_BASE 0xA0000000 -#define CONFIG_SYS_PAXE_SIZE 256 diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h deleted file mode 100644 index c06143c..0000000 --- a/include/configs/km/km-mpc83xx.h +++ /dev/null @@ -1,156 +0,0 @@ -/* - * Internal Definitions - */ -#define BOOTFLASH_START 0xF0000000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */ - -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) - -#define CFG_83XX_DDR_USES_CS0 - -/* - * Manually set up DDR parameters - */ -#define CONFIG_DDR_II -#define CONFIG_SYS_DDR_SIZE 2048 /* MB */ - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_FLASH_BASE 0xF0000000 - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -/* - * Init Local Bus Memory Controller: - * - * Bank Bus Machine PortSz Size Device - * ---- --- ------- ------ ----- ------ - * 0 Local GPCM 16 bit 256MB FLASH - * 1 Local GPCM 8 bit 128MB GPIO/PIGGY - * - */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_SIZE 256 /* max FLASH size is 256M */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_NUM_I2C_BUSES 4 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 200000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 200000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_BUSES {{0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {1, {I2C_NULL_HOP} } } - -#if defined(CONFIG_CMD_NAND) -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE -#endif - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) - -/* - * Environment - */ - -#ifndef CONFIG_SYS_RAMBOOT -#ifndef CONFIG_ENV_ADDR -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#endif -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#ifndef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET (CONFIG_SYS_MONITOR_LEN) -#endif - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else /* CFG_SYS_RAMBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) -#define CONFIG_ENV_SIZE 0x2000 -#endif /* CFG_SYS_RAMBOOT */ - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - "newenv=" \ - "prot off " __stringify(CONFIG_ENV_ADDR) " +0x40000 && " \ - "era " __stringify(CONFIG_ENV_ADDR) " +0x40000\0" \ - "unlock=yes\0" \ - "" - -#if defined(CONFIG_UEC_ETH) -#define CONFIG_HAS_ETH0 -#endif - -/* - * QE UEC ethernet configuration - */ -#define CONFIG_UEC_ETH -#define CONFIG_ETHPRIME "UEC0" diff --git a/include/configs/km/km-powerpc.h b/include/configs/km/km-powerpc.h deleted file mode 100644 index 20b596f..0000000 --- a/include/configs/km/km-powerpc.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_KEYMILE_POWERPC_H -#define __CONFIG_KEYMILE_POWERPC_H - -/* Do boardspecific init for all boards */ - -#define CONFIG_JFFS2_CMDLINE - -/* EEprom support 24C08, 24C16, 24C64 */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* 8 Byte write page */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */ - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ - -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -/* Reserve 4 MB for malloc */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/****************************************************************************** - * (PRAM usage) - * ... ------------------------------------------------------- - * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM - * ... |<------------------- pram -------------------------->| - * ... ------------------------------------------------------- - * @END_OF_RAM: - * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose - * @CONFIG_KM_PHRAM: address for /var - * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) - * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM - */ - -/* size of rootfs in RAM */ -#define CONFIG_KM_ROOTFSSIZE 0x0 -/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable - * is not valid yet, which is the case for when u-boot copies itself to RAM */ -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM)>>10) - -/* architecture specific default bootargs */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" - -#define CONFIG_KM_DEF_ENV_CPU \ - "u-boot="CONFIG_HOSTNAME "/u-boot.bin\0" \ - "update=" \ - "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\ - "erase " __stringify(BOOTFLASH_START) " +${filesize} && "\ - "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \ - " ${filesize} && " \ - "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "" - -#endif /* __CONFIG_KEYMILE_POWERPC_H */ diff --git a/include/configs/km/km_arm.h b/include/configs/km/km_arm.h deleted file mode 100644 index 829a5c7..0000000 --- a/include/configs/km/km_arm.h +++ /dev/null @@ -1,211 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Prafulla Wadaskar - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2010-2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -/* - * for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html - */ - -#ifndef _CONFIG_KM_ARM_H -#define _CONFIG_KM_ARM_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KW88F6281 /* SOC Name */ - -#define CONFIG_MACH_TYPE MACH_TYPE_KM_KIRKWOOD - -#define CONFIG_NAND_ECC_BCH - -/* include common defines/options for all Keymile boards */ -#include "keymile-common.h" - -/* Reserve 4 MB for malloc */ -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -#include "asm/arch/config.h" - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */ -#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ - -/* architecture specific default bootargs */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU \ - "bootcountaddr=${bootcountaddr} ${mtdparts}" \ - " boardid=0x${IVM_BoardId} hwkey=0x${IVM_HWKey}" - -#define CONFIG_KM_DEF_ENV_CPU \ - "u-boot="CONFIG_HOSTNAME "/u-boot.kwb\0" \ - CONFIG_KM_UPDATE_UBOOT \ - "set_fdthigh=setenv fdt_high ${kernelmem}\0" \ - "checkfdt=" \ - "if cramfsls fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb; " \ - "then true; else setenv cramfsloadfdt true; " \ - "setenv boot bootm ${load_addr_r}; " \ - "echo No FDT found, booting with the kernel " \ - "appended one; fi\0" \ - "" - -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - -/* - * NAND Flash configuration - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* - * Other required minimal configurations - */ - -/* - * Ethernet Driver configuration - */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer autoneg timeout */ -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 - -/* - * I2C related stuff - */ -#undef CONFIG_I2C_MVTWSI -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_INIT_BOARD - -#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */ -#define CONFIG_SYS_NUM_I2C_BUSES 6 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ - } - -#ifndef __ASSEMBLY__ -#include -extern void __set_direction(unsigned pin, int high); -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); -#define KM_KIRKWOOD_SDA_PIN 8 -#define KM_KIRKWOOD_SCL_PIN 9 -#define KM_KIRKWOOD_SOFT_I2C_GPIOS 0x0300 -#define KM_KIRKWOOD_ENV_WP 38 - -#define I2C_ACTIVE __set_direction(KM_KIRKWOOD_SDA_PIN, 0) -#define I2C_TRISTATE __set_direction(KM_KIRKWOOD_SDA_PIN, 1) -#define I2C_READ (kw_gpio_get_value(KM_KIRKWOOD_SDA_PIN) ? 1 : 0) -#define I2C_SDA(bit) kw_gpio_set_value(KM_KIRKWOOD_SDA_PIN, bit) -#define I2C_SCL(bit) kw_gpio_set_value(KM_KIRKWOOD_SCL_PIN, bit) -#endif - -#define I2C_DELAY udelay(1) -#define I2C_SOFT_DECLARATIONS - -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x0 -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 - -/* EEprom support 24C128, 24C256 valid for environment eeprom */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 Byte write page */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * Environment variables configurations - */ -#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR -#define CONFIG_ENV_OFFSET 0xc0000 /* no bracets! */ -#define CONFIG_ENV_SIZE 0x02000 /* Size of Environment */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_TOTAL_SIZE 0x20000 /* no bracets! */ -#else -#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50 -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_EEPROM_WREN -#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */ -#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET) -#define CONFIG_I2C_ENV_EEPROM_BUS 5 /* I2C2 (Mux-Port 5) */ -#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */ -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#define KM_FLASH_GPIO_PIN 16 - -#define CONFIG_KM_UPDATE_UBOOT \ - "update=" \ - "sf probe 0;sf erase 0 +${filesize};" \ - "sf write ${load_addr_r} 0 ${filesize};\0" - -#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR -#define CONFIG_KM_NEW_ENV \ - "newenv=sf probe 0;" \ - "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ - __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" -#else -#define CONFIG_KM_NEW_ENV \ - "newenv=setenv addr 0x100000 && " \ - "i2c dev " __stringify(CONFIG_I2C_ENV_EEPROM_BUS) "; " \ - "mw.b ${addr} 0 4 && " \ - "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ - " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \ - "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \ - " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0" -#endif - -#ifndef CONFIG_KM_BOARD_EXTRA_ENV -#define CONFIG_KM_BOARD_EXTRA_ENV "" -#endif - -/* - * Default environment variables - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_BOARD_EXTRA_ENV \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_NEW_ENV \ - "arch=arm\0" \ - "" - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* address for the bootcount (taken from end of RAM) */ -#define BOOTCOUNT_ADDR (CONFIG_KM_RESERVED_PRAM) - -/* enable POST tests */ -#define CONFIG_POST (CONFIG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_SKIP_ENV_FLAGS -#define CONFIG_POST_EXTERNAL_WORD_FUNCS - -#endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/km_kirkwood.h b/include/configs/km_kirkwood.h deleted file mode 100644 index 6fce83c..0000000 --- a/include/configs/km_kirkwood.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Marvell Semiconductor - * Prafulla Wadaskar - * - * (C) Copyright 2009 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * (C) Copyright 2011-2012 - * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com - * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com - */ - -/* - * for linking errors see - * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html - */ - -#ifndef _CONFIG_KM_KIRKWOOD_H -#define _CONFIG_KM_KIRKWOOD_H - -/* KM_KIRKWOOD */ -#if defined(CONFIG_KM_KIRKWOOD) -#define CONFIG_HOSTNAME "km_kirkwood" -#define CONFIG_KM_DISABLE_PCIE - -/* KM_KIRKWOOD_PCI */ -#elif defined(CONFIG_KM_KIRKWOOD_PCI) -#define CONFIG_HOSTNAME "km_kirkwood_pci" -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE - -/* KM_KIRKWOOD_128M16 */ -#elif defined(CONFIG_KM_KIRKWOOD_128M16) -#define CONFIG_HOSTNAME "km_kirkwood_128m16" -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg -#define CONFIG_KM_DISABLE_PCIE - -/* KM_NUSA / KM_SUGP1 */ -#elif defined(CONFIG_KM_NUSA) || defined(CONFIG_KM_SUGP1) - -# if defined(CONFIG_KM_NUSA) -#define CONFIG_HOSTNAME "kmnusa" -# elif defined(CONFIG_KM_SUGP1) -#define CONFIG_HOSTNAME "kmsugp1" -#define KM_PCIE_RESET_MPP7 -#endif - -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg - -/* KM_MGCOGE3UN */ -#elif defined(CONFIG_KM_MGCOGE3UN) -#define CONFIG_HOSTNAME "mgcoge3un" -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-memphis.cfg -#define CONFIG_KM_BOARD_EXTRA_ENV "waitforne=true\0" -#define CONFIG_KM_DISABLE_PCIE - -/* KMCOGE5UN */ -#elif defined(CONFIG_KM_COGE5UN) -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_256M8_1.cfg -#define CONFIG_HOSTNAME "kmcoge5un" -#define CONFIG_KM_DISABLE_PCIE - -/* KM_SUV31 */ -#elif defined(CONFIG_KM_SUV31) -#define CONFIG_HOSTNAME "kmsuv31" -#undef CONFIG_SYS_KWD_CONFIG -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage_128M16_1.cfg -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE -#else -#error ("Board unsupported") -#endif - -/* include common defines/options for all arm based Keymile boards */ -#include "km/km_arm.h" - -#if defined(CONFIG_KM_PIGGY4_88E6352) -/* - * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via - * an Marvell 88E6352 simple switch. - * In this case we have to change the default settings for the etherent mac. - * There is NO ethernet phy. The ARM and Switch are conencted directly over - * RGMII in MAC-MAC mode - * In this case 1GBit full duplex and autoneg off - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_1000 |\ - MVGBE_SET_MII_SPEED_TO_100) - -#endif - -#ifdef CONFIG_KM_PIGGY4_88E6061 -/* - * Some keymile boards like mgcoge3un have their PIGGY4 connected via - * an Marvell 88E6061 simple switch. - * In this case we have to change the default settings for the - * ethernet phy connected to the kirkwood. - * In this case 100MB full duplex and autoneg off - */ -#define PORT_SERIAL_CONTROL_VALUE ( \ - MVGBE_FORCE_LINK_PASS | \ - MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \ - MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \ - MVGBE_ADV_NO_FLOW_CTRL | \ - MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ - MVGBE_FORCE_BP_MODE_NO_JAM | \ - (1 << 9) /* Reserved bit has to be 1 */ | \ - MVGBE_DO_NOT_FORCE_LINK_FAIL | \ - MVGBE_DIS_AUTO_NEG_SPEED_GMII | \ - MVGBE_DTE_ADV_0 | \ - MVGBE_MIIPHY_MAC_MODE | \ - MVGBE_AUTO_NEG_NO_CHANGE | \ - MVGBE_MAX_RX_PACKET_1552BYTE | \ - MVGBE_CLR_EXT_LOOPBACK | \ - MVGBE_SET_FULL_DUPLEX_MODE | \ - MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\ - MVGBE_SET_GMII_SPEED_TO_10_100 |\ - MVGBE_SET_MII_SPEED_TO_100) -#endif - -#ifdef CONFIG_KM_DISABLE_PCIE -#undef CONFIG_KIRKWOOD_PCIE_INIT -#endif - -#endif /* _CONFIG_KM_KIRKWOOD */ diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h deleted file mode 100644 index fc78b27..0000000 --- a/include/configs/kmcoge5ne.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Holger Brunck, Keymile GmbH Hannover, - * Christian Herzig, Keymile AG Switzerland, - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_HOSTNAME "kmcoge5ne" -#define CONFIG_KM_BOARD_NAME "kmcoge5ne" -#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0" -#define CONFIG_NAND_ECC_BCH -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ - -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc8360.h" - -/* - * System Clock Setup - */ -#define CONFIG_83XX_CLKIN 66000000 -#define CONFIG_SYS_CLK_FREQ 66000000 -#define CONFIG_83XX_PCICLK 66000000 - -/** - * KMCOGE5NE has 512 MB RAM - */ -#define CONFIG_SYS_DDR_CS0_CONFIG (\ - CSCONFIG_EN | \ - CSCONFIG_AP | \ - CSCONFIG_ODT_WR_ONLY_CURRENT | \ - CSCONFIG_BANK_BIT_3 | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10) - -/* - * BFTIC3 on the local bus CS4 - */ -#define CONFIG_SYS_BFTIC3_BASE 0xB0000000 -#define CONFIG_SYS_BFTIC3_SIZE 256 - -/* enable POST tests */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS) -#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */ -#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END -#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */ -#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */ - -#endif /* CONFIG */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h deleted file mode 100644 index bfa7ca2..0000000 --- a/include/configs/kmeter1.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 - * Holger Brunck, Keymile GmbH Hannover, - * Christian Herzig, Keymile AG Switzerland, - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_HOSTNAME "kmeter1" -#define CONFIG_KM_BOARD_NAME "kmeter1" -#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0" - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc8360.h" - -/* - * Serial Port - */ -#define CONFIG_CONS_INDEX 1 - -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ - CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | \ - CSCONFIG_ODT_WR_ONLY_CURRENT) -#endif /* CONFIG */ diff --git a/include/configs/kmopti2.h b/include/configs/kmopti2.h deleted file mode 100644 index 67e864f..0000000 --- a/include/configs/kmopti2.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_KM_BOARD_NAME "kmopti2" -#define CONFIG_HOSTNAME "kmopti2" - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h deleted file mode 100644 index 75480a8..0000000 --- a/include/configs/kmp204x.h +++ /dev/null @@ -1,442 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Keymile AG - * Valentin Longchamp - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#if defined(CONFIG_KMCOGE4) -#define CONFIG_HOSTNAME "kmcoge4" -#define CONFIG_KM_BOARD_NAME "kmcoge4" - -#else -#error ("Board not supported") -#endif - -#define CONFIG_KMP204X - -#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" - -/* an additionnal option is required for UBI as subpage access is - * supported in u-boot - */ -#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" - -#define CONFIG_NAND_ECC_BCH - -/* common KM defines */ -#include "km/keymile-common.h" - -#define CONFIG_SYS_RAMBOOT -#define CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg -#define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_SYS_DPAA_RMAN /* RMan */ - -/* Environment in SPI Flash */ -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB for u-boot */ -#define CONFIG_ENV_SIZE 0x004000 /* 16K env */ -#define CONFIG_ENV_SECT_SIZE 0x010000 -#define CONFIG_ENV_OFFSET_REDUND 0x110000 -#define CONFIG_ENV_TOTAL_SIZE 0x020000 - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(unsigned long dummy); -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BACKSIDE_L2_CACHE -#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - -#define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */ - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE -#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \ - CONFIG_RAMBOOT_TEXT_BASE) -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#define CONFIG_DDR_SPD - -#define CONFIG_SYS_SPD_BUS_NUM 0 -#define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/****************************************************************************** - * (PRAM usage) - * ... ------------------------------------------------------- - * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM - * ... |<------------------- pram -------------------------->| - * ... ------------------------------------------------------- - * @END_OF_RAM: - * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose - * @CONFIG_KM_PHRAM: address for /var - * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application) - * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM - */ - -/* size of rootfs in RAM */ -#define CONFIG_KM_ROOTFSSIZE 0x0 -/* pseudo-non volatile RAM [hex] */ -#define CONFIG_KM_PNVRAM 0x80000 -/* physical RAM MTD size [hex] */ -#define CONFIG_KM_PHRAM 0x100000 -/* reserved pram area at the end of memory [hex] - * u-boot reserves some memory for the MP boot page - */ -#define CONFIG_KM_RESERVED_PRAM 0x1000 -/* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable - * is not valid yet, which is the case for when u-boot copies itself to RAM - */ -#define CONFIG_PRAM ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10) - -#define CONFIG_KM_CRAMFS_ADDR 0x2000000 -#define CONFIG_KM_KERNEL_ADDR 0x1000000 /* max kernel size 15.5Mbytes */ -#define CONFIG_KM_FDT_ADDR 0x1F80000 /* max dtb size 0.5Mbytes */ - -/* - * Local Bus Definitions - */ - -/* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */ -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_2) - -/* Nand Flash */ -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xffa00000 -#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull - -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* NAND flash config */ -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \ - | OR_FCM_BCTLD /* LBCTL not ass */ \ - | OR_FCM_SCY_1 /* 1 clk wait cycle */ \ - | OR_FCM_RST /* 1 clk read setup */ \ - | OR_FCM_PGS /* Large page size */ \ - | OR_FCM_CST) /* 0.25 command setup */ - -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ - -/* QRIO FPGA */ -#define CONFIG_SYS_QRIO_BASE 0xfb000000 -#define CONFIG_SYS_QRIO_BASE_PHYS 0xffb000000ull - -#define CONFIG_SYS_QRIO_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \ - | BR_PS_8 /* Port Size 8 bits */ \ - | BR_DECC_OFF /* no error corr */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_QRIO_OR_PRELIM (OR_AM_64KB /* length 64K */ \ - | OR_GPCM_BCTLD /* no LCTL assert */ \ - | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \ - | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ - | OR_GPCM_TRLX /* relaxed tmgs */ \ - | OR_GPCM_EAD) /* extra bus clk cycles */ - -#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ - -#define CONFIG_MISC_INIT_F - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600) - -#define CONFIG_KM_CONSOLE_TTY "ttyS0" - -/* I2C */ - -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ -#define CONFIG_SYS_NUM_I2C_BUSES 3 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ - } -#ifndef __ASSEMBLY__ -void set_sda(int state); -void set_scl(int state); -int get_sda(void); -int get_scl(void); -#endif - -#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/ - -/* - * eSPI - Enhanced SPI - */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* Qman/Bman */ -#define CONFIG_SYS_BMAN_NUM_PORTALS 10 -#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 -#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull -#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE -#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ - CONFIG_SYS_BMAN_CENA_SIZE) -#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 -#define CONFIG_SYS_QMAN_NUM_PORTALS 10 -#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 -#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull -#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 -#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 -#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 -#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE -#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ - CONFIG_SYS_QMAN_CENA_SIZE) -#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) -#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 - -#define CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_DPAA_PME -/* Default address of microcode for the Linux Fman driver - * env is stored at 0x100000, sector size is 0x10000, x2 (redundant) - * ucode is stored after env, so we got 0x120000. - */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x120000 -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#define CONFIG_PHYLIB_10G - -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -/* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ -#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 -#define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_ETHPRIME "FM1@DTSEC5" - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Hardware Watchdog - */ -#define CONFIG_WATCHDOG /* enable CPU watchdog */ -#define CONFIG_WATCHDOG_PRESC 34 /* wdog prescaler 2^(64-34) (~10min) */ -#define CONFIG_WATCHDOG_RC WRC_CHIP /* reset chip on watchdog event */ - -/* - * additionnal command line configuration. - */ - -/* we don't need flash support */ -#undef CONFIG_JFFS2_CMDLINE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -#define __USB_PHY_TYPE utmi -#define CONFIG_USB_EHCI_FSL - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE -#ifndef CONFIG_KM_DEF_ENV /* if not set by keymile-common.h */ -#define CONFIG_KM_DEF_ENV "km-common=empty\0" -#endif - -/* architecture specific default bootargs */ -#define CONFIG_KM_DEF_BOOT_ARGS_CPU "" - -/* FIXME: FDT_ADDR is unspecified */ -#define CONFIG_KM_DEF_ENV_CPU \ - "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0" \ - "cramfsloadfdt=" \ - "cramfsload ${fdt_addr_r} " \ - "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ - "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0" \ - "update=" \ - "sf probe 0;sf erase 0 +${filesize};" \ - "sf write ${load_addr_r} 0 ${filesize};\0" \ - "set_fdthigh=true\0" \ - "checkfdt=true\0" \ - "" - -#define CONFIG_HW_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0" \ - "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \ - "usb_dr_mode=host\0" - -#define CONFIG_KM_NEW_ENV \ - "newenv=sf probe 0;" \ - "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \ - __stringify(CONFIG_ENV_TOTAL_SIZE)"\0" - -/* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */ -#ifndef CONFIG_KM_DEF_ARCH -#define CONFIG_KM_DEF_ARCH "arch=ppc_82xx\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_KM_DEF_ENV \ - CONFIG_KM_DEF_ARCH \ - CONFIG_KM_NEW_ENV \ - CONFIG_HW_ENV_SETTINGS \ - "EEprom_ivm=pca9547:70:9\0" \ - "" - -/* App2 Local bus */ -#define CONFIG_SYS_LBAPP2_BASE 0xE0000000 -#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull - -#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \ - | BR_PS_8 /* Port Size 8 bits */ \ - | BR_DECC_OFF /* no error corr */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ - -#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \ - | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \ - | OR_GPCM_CSNT /* LCS 1/4 clk before */ \ - | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \ - | OR_GPCM_TRLX /* relaxed tmgs */ \ - | OR_GPCM_EAD) /* extra bus clk cycles */ -/* Local bus app2 Base Address */ -#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM -/* Local bus app2 Options */ -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM - -#endif /* __CONFIG_H */ diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h deleted file mode 100644 index ba33e60..0000000 --- a/include/configs/kmsupx5.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_KM_BOARD_NAME "kmsupx5" -#define CONFIG_HOSTNAME "kmsupx5" - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/kmtegr1.h b/include/configs/kmtegr1.h deleted file mode 100644 index 701eb53..0000000 --- a/include/configs/kmtegr1.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_HOSTNAME "kmtegr1" -#define CONFIG_KM_BOARD_NAME "kmtegr1" -#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" -#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" - -#define CONFIG_ENV_ADDR 0xF0100000 -#define CONFIG_ENV_OFFSET 0x100000 - -#define CONFIG_NAND_ECC_BCH -#define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS 1 - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc8309.h" - -/* must be after the include because KMBEC_FPGA is otherwise undefined */ -#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/kmtepr2.h b/include/configs/kmtepr2.h deleted file mode 100644 index e0c907d..0000000 --- a/include/configs/kmtepr2.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_KM_BOARD_NAME "kmtepr2" -#define CONFIG_HOSTNAME "kmtepr2" - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h deleted file mode 100644 index 140076a..0000000 --- a/include/configs/koelsch.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/koelsch.h - * - * Copyright (C) 2013 Renesas Electronics Corporation - */ - -#ifndef __KOELSCH_H -#define __KOELSCH_H - -#include "rcar-gen2-common.h" - -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 -#define STACK_AREA_SIZE 0x00100000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) -#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" - -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_CONS_SCIF0 -#define CONFIG_SH_SCIF_CLK_FREQ 65000000 -#endif - -#endif /* __KOELSCH_H */ diff --git a/include/configs/kp_imx53.h b/include/configs/kp_imx53.h deleted file mode 100644 index 55bfa0f..0000000 --- a/include/configs/kp_imx53.h +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -#ifndef __CONFIG_H_ -#define __CONFIG_H_ - -#include -#include - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -/* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc1,115200\0" \ - "fdt_addr=0x75000000\0" \ - "fdt_high=0xffffffff\0" \ - "scriptaddr=0x74000000\0" \ - "kernel_file=fitImage\0"\ - "silent=1\0"\ - "rdinit=/sbin/init\0" \ - "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \ - "upd_image=st.4k\0" \ - "uboot_file=u-boot.imx\0" \ - "updargs=setenv bootargs console=${console} ${smp} ${displayargs}\0" \ - "initrd_ram_dev=/dev/ram\0" \ - "addswupdate=setenv bootargs ${bootargs} root=${initrd_ram_dev} rw\0" \ - "addkeys=setenv bootargs ${bootargs} di=${dig_in} key1=${key1}\0" \ - "loadusb=usb start; " \ - "fatload usb 0 ${loadaddr} ${upd_image}\0" \ - "up=if tftp ${loadaddr} ${uboot_file}; then " \ - "setexpr blkc ${filesize} / 0x200; " \ - "setexpr blkc ${blkc} + 1; " \ - "mmc write ${loadaddr} 0x2 ${blkc}" \ - "; fi\0" \ - "upwic=setenv wic_file kp-image-kp${boardsoc}.wic; "\ - "if tftp ${loadaddr} ${wic_file}; then " \ - "setexpr blkc ${filesize} / 0x200; " \ - "setexpr blkc ${blkc} + 1; " \ - "mmc write ${loadaddr} 0x0 ${blkc}" \ - "; fi\0" \ - "usbupd=echo Booting update from usb ...; " \ - "setenv bootargs; " \ - "run updargs; " \ - "run addinitrd; " \ - "run addswupdate; " \ - "run addkeys; " \ - "run loadusb; " \ - "bootm ${loadaddr}#${fit_config}\0" \ - BOOTENV - -#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * SZ_1M) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_OFFSET (SZ_1M) -#define CONFIG_ENV_SIZE (SZ_8K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif /* __CONFIG_H_ */ diff --git a/include/configs/kp_imx6q_tpc.h b/include/configs/kp_imx6q_tpc.h deleted file mode 100644 index f6746a9..0000000 --- a/include/configs/kp_imx6q_tpc.h +++ /dev/null @@ -1,134 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * K+P iMX6Q KP_IMX6Q_TPC board configuration - * - * Copyright (C) 2018 Lukasz Majewski - */ - -#ifndef __KP_IMX6Q_TPC_IMX6_CONFIG_H_ -#define __KP_IMX6Q_TPC_IMX6_CONFIG_H_ - -#include - -#include "mx6_common.h" - -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - -/* Miscellaneous configurable options */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (4 * SZ_1M) - -/* FEC ethernet */ -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_SYS_MMC_ENV_DEV 1 /* 0 = SDHC2, 1 = SDHC4 (eMMC) */ - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ -#endif - -/* Watchdog */ - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_LOADADDR 0x12000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ - "fdt_addr=0x18000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x10008000\0" \ - "fdt_addr_r=0x13000000\0" \ - "ramdisk_addr_r=0x18000000\0" \ - "scriptaddr=0x14000000\0" \ - "kernel_file=fitImage\0"\ - "rdinit=/sbin/init\0" \ - "addinitrd=setenv bootargs ${bootargs} rdinit=${rdinit} ${debug} \0" \ - "fit_config=mx6q_tpc70_conf\0" \ - "uboot_file=u-boot.img\0" \ - "SPL_file=SPL\0" \ - "wic_file=kp-image-kpimx6qtpc.wic\0" \ - "upd_image=st.4k\0" \ - "updargs=setenv bootargs console=${console} ${smp} ${displayargs}\0" \ - "initrd_ram_dev=/dev/ram\0" \ - "addswupdate=setenv bootargs ${bootargs} root=${initrd_ram_dev} rw\0" \ - "loadusb=usb start; " \ - "fatload usb 0 ${loadaddr} ${upd_image}\0" \ - "upd_uboot_sd=" \ - "if tftp ${loadaddr} ${uboot_file}; then " \ - "setexpr blkc ${filesize} / 0x200;" \ - "setexpr blkc ${blkc} + 1;" \ - "mmc write ${loadaddr} 0x8A ${blkc};" \ - "fi;\0" \ - "upd_SPL_sd=" \ - "if tftp ${loadaddr} ${SPL_file}; then " \ - "setexpr blkc ${filesize} / 0x200;" \ - "setexpr blkc ${blkc} + 1;" \ - "mmc write ${loadaddr} 0x2 ${blkc};" \ - "fi;\0" \ - "upd_SPL_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_SPL_sd\0" \ - "upd_uboot_mmc=mmc dev 1; mmc partconf 1 0 1 1; run upd_uboot_sd\0" \ - "up_mmc=run upd_SPL_mmc; run upd_uboot_mmc\0" \ - "up_sd=run upd_SPL_sd; run upd_uboot_sd\0" \ - "upd_wic=" \ - "if tftp ${loadaddr} ${wic_file}; then " \ - "setexpr blkc ${filesize} / 0x200;" \ - "setexpr blkc ${blkc} + 1;" \ - "mmc write ${loadaddr} 0x0 ${blkc};" \ - "fi;\0" \ - "usbupd=echo Booting update from usb ...; " \ - "setenv bootargs; " \ - "run updargs; " \ - "run addinitrd; " \ - "run addswupdate; " \ - "run loadusb; " \ - "bootm ${loadaddr}#${fit_config}\0" \ - BOOTENV - -#define CONFIG_BOOTCOMMAND "run usbupd; run distro_bootcmd" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) - -#include -#endif - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment */ -#define CONFIG_ENV_SIZE (SZ_8K) -#define CONFIG_ENV_OFFSET 0x100000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -#endif /* __KP_IMX6Q_TPC_IMX6_CONFIG_H_ */ diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h deleted file mode 100644 index 1ef7633..0000000 --- a/include/configs/kylin_rk3036.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -#ifndef CONFIG_SPL_BUILD - -/* Store env in emmc */ -#define CONFIG_SYS_MMC_ENV_DEV 0 /* emmc */ -#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ - -#endif - -#endif diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h deleted file mode 100644 index 5a2b040..0000000 --- a/include/configs/kzm9g.h +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Nobuhiro Iwamatsu - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __KZM9G_H -#define __KZM9G_H - -#define CONFIG_SH73A0 -#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G - -#include - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* MEMORY */ -#define KZM_SDRAM_BASE (0x40000000) -#define PHYS_SDRAM KZM_SDRAM_BASE -#define PHYS_SDRAM_SIZE (512 * 1024 * 1024) - -/* NOR Flash */ -#define KZM_FLASH_BASE (0x00000000) -#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE) -#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) -#define CONFIG_SYS_MAX_FLASH_BANKS (1) -#define CONFIG_SYS_MAX_FLASH_SECT (512) - -/* prompt */ -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF4 - -#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */ -#define CONFIG_SYS_INIT_RAM_SIZE (0x10000) -#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT) -#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000 - -/* FLASH */ -#undef CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */ -#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE -#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) - -/* Timeout for Flash erase operations (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -/* Timeout for Flash write operations (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -/* Timeout for Flash set sector lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -/* Timeout for Flash clear lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) - -#undef CONFIG_SYS_DIRECT_FLASH_TFTP - -/* GPIO / PFC */ -#define CONFIG_SH_GPIO_PFC - -/* Clock */ -#define CONFIG_GLOBAL_TIMER -#define CONFIG_SYS_CLK_FREQ (48000000) -#define CONFIG_SYS_CPU_CLK (1196000000) -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ -#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */ - -#define CONFIG_NFS_TIMEOUT 10000UL - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SH -#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5 -#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000 -#define CONFIG_SYS_I2C_SH_SPEED0 100000 -#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000 -#define CONFIG_SYS_I2C_SH_SPEED1 100000 -#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000 -#define CONFIG_SYS_I2C_SH_SPEED2 100000 -#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000 -#define CONFIG_SYS_I2C_SH_SPEED3 100000 -#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000 -#define CONFIG_SYS_I2C_SH_SPEED4 100000 -#define CONFIG_SH_I2C_8BIT -#define CONFIG_SH_I2C_DATA_HIGH 4 -#define CONFIG_SH_I2C_DATA_LOW 5 -#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */ - -#endif /* __KZM9G_H */ diff --git a/include/configs/lacie_kw.h b/include/configs/lacie_kw.h deleted file mode 100644 index 1ba28b5..0000000 --- a/include/configs/lacie_kw.h +++ /dev/null @@ -1,156 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Simon Guinot - */ - -#ifndef _CONFIG_LACIE_KW_H -#define _CONFIG_LACIE_KW_H - -/* - * Machine number definition - */ -#if defined(CONFIG_INETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_INETSPACE_V2 -#elif defined(CONFIG_NETSPACE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_V2 -#elif defined(CONFIG_NETSPACE_LITE_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_LITE_V2 -#elif defined(CONFIG_NETSPACE_MINI_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MINI_V2 -#elif defined(CONFIG_NETSPACE_MAX_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NETSPACE_MAX_V2 -#elif defined(CONFIG_D2NET_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_D2NET_V2 -#elif defined(CONFIG_NET2BIG_V2) -#define CONFIG_MACH_TYPE MACH_TYPE_NET2BIG_V2 -#else -#error "Unknown board" -#endif - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -/* SoC name */ -#if defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) -#define CONFIG_KW88F6192 -#else -#define CONFIG_KW88F6281 -#endif -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Core clock definition - */ -#define CONFIG_SYS_TCLK 166000000 /* 166MHz */ - -/* - * SDRAM configuration - */ - -/* - * Different SDRAM configuration and size for some of the boards derived - * from the Network Space v2 - */ -#if defined(CONFIG_INETSPACE_V2) -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-is2.cfg -#elif defined(CONFIG_NETSPACE_LITE_V2) || defined(CONFIG_NETSPACE_MINI_V2) -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-ns2l.cfg -#endif - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Remove or override few declarations from mv-common.h */ -#undef CONFIG_SYS_IDE_MAXBUS -#undef CONFIG_SYS_IDE_MAXDEVICE - -/* - * Enable platform initialisation via misc_init_r() function - */ - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_NETCONSOLE -#endif - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#if defined(CONFIG_NETSPACE_MAX_V2) || defined(CONFIG_D2NET_V2) || \ - defined(CONFIG_NET2BIG_V2) -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 2 -#else -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#endif -#endif /* CONFIG_MVSATA_IDE */ - -/* - * Enable GPI0 support - */ -#define CONFIG_KIRKWOOD_GPIO - -/* - * Enable I2C support - */ -#ifdef CONFIG_CMD_I2C -/* I2C EEPROM HT24LC04 (512B - 32 pages of 16 Bytes) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 16-byte page size */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* 8-bit device address */ -#if defined(CONFIG_NET2BIG_V2) -#define CONFIG_SYS_I2C_G762_ADDR 0x3e -#endif -#endif /* CONFIG_CMD_I2C */ - -/* - * Partition support - */ - -/* - * File systems support - */ - -/* - * Environment variables configurations - */ -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ -#define CONFIG_ENV_SIZE 0x1000 /* 4KB */ -#define CONFIG_ENV_ADDR 0x70000 -#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND \ - "dhcp && run netconsole; " \ - "if run usbload || run diskload; then bootm; fi" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "bootfile=uImage\0" \ - "loadaddr=0x800000\0" \ - "autoload=no\0" \ - "netconsole=" \ - "set stdin $stdin,nc; " \ - "set stdout $stdout,nc; " \ - "set stderr $stderr,nc;\0" \ - "diskload=ide reset && " \ - "ext2load ide 0:1 $loadaddr /boot/$bootfile\0" \ - "usbload=usb start && " \ - "fatload usb 0:1 $loadaddr /boot/$bootfile\0" - -#endif /* _CONFIG_LACIE_KW_H */ diff --git a/include/configs/lager.h b/include/configs/lager.h deleted file mode 100644 index db1dbc0..0000000 --- a/include/configs/lager.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/lager.h - * This file is lager board configuration. - * - * Copyright (C) 2013, 2014 Renesas Electronics Corporation - */ - -#ifndef __LAGER_H -#define __LAGER_H - -#include "rcar-gen2-common.h" - -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 -#define STACK_AREA_SIZE 0x00100000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) -#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" - -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_CONS_SCIF0 -#define CONFIG_SH_SCIF_CLK_FREQ 65000000 -#endif - -#endif /* __LAGER_H */ diff --git a/include/configs/legoev3.h b/include/configs/legoev3.h deleted file mode 100644 index c1eeca0..0000000 --- a/include/configs/legoev3.h +++ /dev/null @@ -1,147 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 David Lechner - * - * Based on da850evm.h - * - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC Configuration - */ -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) - -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID) - -/* - * I2C Configuration - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ - -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "uImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_HWCONFIG /* enable hwconfig */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_SETUP_INITRD_TAG -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan; then " \ - "if run loadbootscr; then " \ - "run bootscript; " \ - "else " \ - "if run loadbootenv; then " \ - "echo Loaded env from ${bootenvfile};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadimage; then " \ - "run mmcargs; " \ - "if run loadfdt; then " \ - "echo Using ${fdtfile}...;" \ - "run fdtfixup; " \ - "run fdtboot; "\ - "fi; " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; "\ - "run flashargs; " \ - "run flashboot" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootenvfile=uEnv.txt\0" \ - "fdtfile=da850-lego-ev3.dtb\0" \ - "memsize=64M\0" \ - "filesyssize=10M\0" \ - "verify=n\0" \ - "console=ttyS1,115200n8\0" \ - "bootscraddr=0xC0600000\0" \ - "fdtaddr=0xC0600000\0" \ - "loadaddr=0xC0007FC0\0" \ - "filesysaddr=0xC1180000\0" \ - "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \ - "importbootenv=echo Importing environment...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loadbootenv=fatload mmc 0 ${loadaddr} ${bootenvfile}\0" \ - "mmcargs=setenv bootargs console=${console} root=/dev/mmcblk0p2 rw " \ - "rootwait ${optargs}\0" \ - "mmcboot=bootm ${loadaddr}\0" \ - "flashargs=setenv bootargs initrd=${filesysaddr},${filesyssize} " \ - "root=/dev/ram0 rw rootfstype=squashfs console=${console} " \ - "${optargs}\0" \ - "flashboot=sf probe 0; " \ - "sf read ${fdtaddr} 0x40000 0x10000; " \ - "sf read ${loadaddr} 0x50000 0x400000; " \ - "sf read ${filesysaddr} 0x450000 0xA00000; " \ - "run fdtfixup; " \ - "run fdtboot\0" \ - "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \ - "loadfdt=fatload mmc 0 ${fdtaddr} ${fdtfile}\0" \ - "fdtfixup=fdt addr ${fdtaddr}; fdt resize; fdt chosen\0" \ - "fdtboot=bootm ${loadaddr} - ${fdtaddr}\0" \ - "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \ - "bootscript=source ${bootscraddr}\0" - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -#define CONFIG_ENV_SIZE (16 << 10) - -/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x80010000 - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/libretech-ac.h b/include/configs/libretech-ac.h deleted file mode 100644 index 419dc61..0000000 --- a/include/configs/libretech-ac.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for LibreTech AC - * - * Copyright (C) 2017 Baylibre, SAS - * Author: Neil Armstrong - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_OFFSET (-0x10000) - -#define BOOT_TARGET_DEVICES(func) \ - func(ROMUSB, romusb, na) \ - func(MMC, mmc, 0) \ - BOOT_TARGET_DEVICES_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/linkit-smart-7688.h b/include/configs/linkit-smart-7688.h deleted file mode 100644 index 4d30d98..0000000 --- a/include/configs/linkit-smart-7688.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Stefan Roese - */ - -#ifndef __CONFIG_LINKIT_SMART_7688_H -#define __CONFIG_LINKIT_SMART_7688_H - -/* CPU */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 290000000 - -/* RAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#ifdef CONFIG_BOOT_RAM -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* UART */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ - 230400, 460800, 921600 } - -/* RAM */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 - -/* Memory usage */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_CBSIZE 512 - -/* U-Boot */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/* Environment settings */ -#define CONFIG_ENV_OFFSET 0x80000 -#define CONFIG_ENV_SIZE (16 << 10) -#define CONFIG_ENV_SECT_SIZE (64 << 10) - -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -#endif /* __CONFIG_LINKIT_SMART_7688_H */ diff --git a/include/configs/lion_rk3368.h b/include/configs/lion_rk3368.h deleted file mode 100644 index cae0f1e..0000000 --- a/include/configs/lion_rk3368.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH - */ - -#ifndef __CONFIGS_LION_RK3368_H -#define __CONFIGS_LION_RK3368_H - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define KERNEL_LOAD_ADDR 0x280000 -#define DTB_LOAD_ADDR 0x5600000 -#define INITRD_LOAD_ADDR 0x5bf0000 -/* PHY needs longer aneg time at 1G */ -#define PHY_ANEG_TIMEOUT 8000 - -#endif diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h deleted file mode 100644 index 975f324..0000000 --- a/include/configs/liteboard.h +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * Copyright (C) 2016 Grinn - * - * Configuration settings for the Grinn liteBoard (i.MX6UL). - */ -#ifndef __LITEBOARD_CONFIG_H -#define __LITEBOARD_CONFIG_H - -#include -#include -#include "mx6_common.h" - -/* SPL options */ -#include "imx6_spl.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* MMC Configs */ -#ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#endif - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_MMCROOT "/dev/mmcblk0p2" - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_FEC_ENET_DEV 0 - -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" - -#define CONFIG_PHY_SMSC -#endif - -#define CONFIG_IMX_THERMAL - -#endif diff --git a/include/configs/ls1012a2g5rdb.h b/include/configs/ls1012a2g5rdb.h deleted file mode 100644 index cb32938..0000000 --- a/include/configs/ls1012a2g5rdb.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __LS1012A2G5RDB_H__ -#define __LS1012A2G5RDB_H__ - -#include "ls1012a_common.h" - -/* DDR */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -/* SATA */ -#define CONFIG_LIBATA -#define CONFIG_SCSI_AHCI -#define CONFIG_SCSI_AHCI_PLAT - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ - "kernel_addr=0x01000000\0" \ - "kernelheader_addr=0x800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "console=ttyS0,115200\0" \ - BOOTENV \ - "boot_scripts=ls1012ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "installer=load mmc 0:2 $load_addr " \ - "/flex_installer_arm64.itb; " \ - "bootm $load_addr#$board\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#else -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#endif -#endif - -#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO" -#define DEFAULT_PFE_MDIO1_NAME "PFE_MDIO1" - -#include - -#endif /* __LS1012A2G5RDB_H__ */ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h deleted file mode 100644 index dd2a679..0000000 --- a/include/configs/ls1012a_common.h +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor - */ - -#ifndef __LS1012A_COMMON_H -#define __LS1012A_COMMON_H - -#define CONFIG_GICV2 - -#include -#include - -#define CONFIG_SYS_CLK_FREQ 125000000 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -/* CSU */ -#define CONFIG_LAYERSCAPE_NS_ACCESS - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) - -/*SPI device */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_TFABOOT) -#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_FSL_SPI_INTERFACE -#define CONFIG_SF_DATAFLASH - -#define QSPI0_AMBA_BASE 0x40000000 -#define CONFIG_SPI_FLASH_SPANSION - -#define FSL_QSPI_FLASH_SIZE SZ_64M -#define FSL_QSPI_FLASH_NUM 2 - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENV_SIZE 0x40000 /* 256KB */ -#ifdef CONFIG_TFABOOT -#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ -#else -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#endif -#define CONFIG_ENV_SECT_SIZE 0x40000 -#endif - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -/* I2C */ -#define CONFIG_SYS_I2C - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 - -#ifndef CONFIG_SPL_BUILD -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(SCSI, scsi, 0) \ - func(DHCP, dhcp, na) -#include -#endif - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x1000000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#define QSPI_NOR_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ - "$kernel_start $kernel_size && "\ - "bootm $kernel_load" -#else -#define CONFIG_BOOTCOMMAND "pfe stop; sf probe 0:0; sf read $kernel_load "\ - "$kernel_start $kernel_size && "\ - "bootm $kernel_load" -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#include - -#endif /* __LS1012A_COMMON_H */ diff --git a/include/configs/ls1012afrdm.h b/include/configs/ls1012afrdm.h deleted file mode 100644 index 8c7d4e5..0000000 --- a/include/configs/ls1012afrdm.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1012ARDB_H__ -#define __LS1012ARDB_H__ - -#include "ls1012a_common.h" - -/* DDR */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#ifndef CONFIG_SPL_BUILD -#undef BOOT_TARGET_DEVICES -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) -#endif - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ - "kernel_addr=0x01000000\0" \ - "scriptaddr=0x80000000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x96000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0x96000000\0" \ - "kernel_size=0x2800000\0" \ - "console=ttyS0,115200\0" \ - BOOTENV \ - "boot_scripts=ls1012afrdm_boot.scr\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "installer=load usb 0:2 $load_addr " \ - "/flex_installer_arm64.itb; " \ - "bootm $load_addr#$board\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size && bootm $load_addr#$board\0" - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd" -#else -#define CONFIG_BOOTCOMMAND "pfe stop;run distro_bootcmd;run qspi_bootcmd" -#endif - -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#endif /* __LS1012ARDB_H__ */ diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h deleted file mode 100644 index 1b0f156..0000000 --- a/include/configs/ls1012afrwy.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __LS1012AFRWY_H__ -#define __LS1012AFRWY_H__ - -#include "ls1012a_common.h" - -/* Board Rev*/ -#define BOARD_REV_A_B 0x0 -#define BOARD_REV_C 0x00080000 -#define BOARD_REV_MASK 0x001A0000 -/* DDR */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define SYS_SDRAM_SIZE_512 0x20000000 -#define SYS_SDRAM_SIZE_1024 0x40000000 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_CMD_MEMINFO -#define CONFIG_CMD_MEMTEST -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -/* ENV */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ - CONFIG_ENV_OFFSET) - -#ifndef CONFIG_SPL_BUILD -#undef BOOT_TARGET_DEVICES -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) -#endif - -#undef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET 0x1D0000 -#undef FSL_QSPI_FLASH_SIZE -#define FSL_QSPI_FLASH_SIZE SZ_16M -#undef CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_SECT_SIZE 0x10000 /*64 KB*/ -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x10000 /*64 KB*/ - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ - "kernel_addr=0x01000000\0" \ - "kernel_size_sd=0x16000\0" \ - "kernelhdr_size_sd=0x10\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelheader_addr=0x1fc000\0" \ - "kernelheader_addr=0x1fc000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0x96000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "console=ttyS0,115200\0" \ - BOOTENV \ - "boot_scripts=ls1012afrwy_boot.scr\0" \ - "boot_script_hdr=hdr_ls1012afrwy_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ - "env exists secureboot " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "installer=load mmc 0:2 $load_addr " \ - "/flex_installer_arm64.itb; " \ - "bootm $load_addr#$board\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "sd_bootcmd=echo Trying load from sd card..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd ;" \ - "env exists secureboot && mmc read $kernelheader_addr_r "\ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\ - "env exists secureboot && esbc_halt;" -#else -#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run sd_bootcmd; "\ - "env exists secureboot && esbc_halt;" -#endif -#define CONFIG_CMD_MEMINFO -#define CONFIG_CMD_MEMTEST -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#include - -#include -#endif /* __LS1012AFRWY_H__ */ diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h deleted file mode 100644 index fb0d1ba..0000000 --- a/include/configs/ls1012aqds.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1012AQDS_H__ -#define __LS1012AQDS_H__ - -#include "ls1012a_common.h" - -/* DDR */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -/* - * QIXIS Definitions - */ -#define CONFIG_FSL_QIXIS - -#ifdef CONFIG_FSL_QIXIS -#define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_LBMAP_BRDCFG_REG 0x04 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x08 -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x08 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#endif - -/* - * I2C bus multiplexer - */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_CH7301 0xC -#define I2C_MUX_CH5 0xD -#define I2C_MUX_CH7 0xF - -#define I2C_MUX_CH_VOL_MONITOR 0xa - -/* -* RTC configuration -*/ -#define RTC -#define CONFIG_RTC_PCF8563 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -/* DSPI */ -#define CONFIG_FSL_DSPI1 - -#define MMAP_DSPI DSPI1_BASE_ADDR - -#define CONFIG_SYS_DSPI_CTAR0 1 - -#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ - DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ - DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ - DSPI_CTAR_DT(0)) -#define CONFIG_SPI_FLASH_SST /* cs1 */ - -#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ - DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ - DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ - DSPI_CTAR_DT(0)) -#define CONFIG_SPI_FLASH_STMICRO /* cs2 */ - -#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ - DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ - DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ - DSPI_CTAR_DT(0)) -#define CONFIG_SPI_FLASH_EON /* cs3 */ - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#include -#endif /* __LS1012AQDS_H__ */ diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h deleted file mode 100644 index a5e2740..0000000 --- a/include/configs/ls1012ardb.h +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1012ARDB_H__ -#define __LS1012ARDB_H__ - -#include "ls1012a_common.h" - -/* DDR */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_SYS_SDRAM_SIZE 0x40000000 -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - - -/* ENV */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ - CONFIG_ENV_OFFSET) -/* - * I2C IO expander - */ - -#define I2C_MUX_IO_ADDR 0x24 -#define I2C_MUX_IO2_ADDR 0x25 -#define I2C_MUX_IO_0 0 -#define I2C_MUX_IO_1 1 -#define SW_BOOT_MASK 0x03 -#define SW_BOOT_EMU 0x02 -#define SW_BOOT_BANK1 0x00 -#define SW_BOOT_BANK2 0x01 -#define SW_REV_MASK 0xF8 -#define SW_REV_A 0xF8 -#define SW_REV_B 0xF0 -#define SW_REV_C 0xE8 -#define SW_REV_C1 0xE0 -#define SW_REV_C2 0xD8 -#define SW_REV_D 0xD0 -#define SW_REV_E 0xC8 -#define __PHY_MASK 0xF9 -#define __PHY_ETH2_MASK 0xFB -#define __PHY_ETH1_MASK 0xFD - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - - -#define CONFIG_PCIE1 /* PCIE controller 1 */ - -#define CONFIG_PCI_SCAN_SHOW - -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=no\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ - "kernel_addr=0x01000000\0" \ - "kernelheader_addr=0x800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "console=ttyS0,115200\0" \ - BOOTENV \ - "boot_scripts=ls1012ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1012ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ - "env exists secureboot " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "installer=load mmc 0:2 $load_addr " \ - "/flex_installer_arm64.itb; " \ - "bootm $load_addr#$board\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#undef QSPI_NOR_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ - "env exists secureboot && esbc_halt;" -#else -#define CONFIG_BOOTCOMMAND "pfe stop; run distro_bootcmd; run qspi_bootcmd; "\ - "env exists secureboot && esbc_halt;" -#endif - -#include - -#endif /* __LS1012ARDB_H__ */ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h deleted file mode 100644 index ee570bc..0000000 --- a/include/configs/ls1021aiot.h +++ /dev/null @@ -1,251 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR - -#define CONFIG_SYS_FSL_CLK - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -/* - * DDR: 800 MHz ( 1600 MT/s data rate ) - */ - -#define DDR_SDRAM_CFG 0x470c0008 -#define DDR_CS0_BNDS 0x008000bf -#define DDR_CS0_CONFIG 0x80014302 -#define DDR_TIMING_CFG_0 0x50550004 -#define DDR_TIMING_CFG_1 0xbcb38c56 -#define DDR_TIMING_CFG_2 0x0040d120 -#define DDR_TIMING_CFG_3 0x010e1000 -#define DDR_TIMING_CFG_4 0x00000001 -#define DDR_TIMING_CFG_5 0x03401400 -#define DDR_SDRAM_CFG_2 0x00401010 -#define DDR_SDRAM_MODE 0x00061c60 -#define DDR_SDRAM_MODE_2 0x00180000 -#define DDR_SDRAM_INTERVAL 0x18600618 -#define DDR_DDR_WRLVL_CNTL 0x8655f605 -#define DDR_DDR_WRLVL_CNTL_2 0x05060607 -#define DDR_DDR_WRLVL_CNTL_3 0x05050505 -#define DDR_DDR_CDR1 0x80040000 -#define DDR_DDR_CDR2 0x00000001 -#define DDR_SDRAM_CLK_CNTL 0x02000000 -#define DDR_DDR_ZQ_CNTL 0x89080600 -#define DDR_CS0_CONFIG_2 0 -#define DDR_SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG2_D_INIT 0x00000010 -#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 -#define SDRAM_CFG2_FRC_SR 0x80000000 -#define SDRAM_CFG_BI 0x00000001 - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1021aiot/ls102xa_pbi.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aiot/ls102xa_rcw_sd.cfg -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_WATCHDOG_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 - -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -/* - * I2C - */ -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * MMC - */ -#define CONFIG_CMD_MMC - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT -#ifndef PCI_DEVICE_ID_FREESCALE_AHCI -#define PCI_DEVICE_ID_FREESCALE_AHCI 0x0440 -#endif -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_FREESCALE, \ - PCI_DEVICE_ID_FREESCALE_AHCI} - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -/* SPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SPI_FLASH_SPANSION - -/* QSPI */ -#define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SPI_FLASH_SPANSION -#endif - -/* DM SPI */ -#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) -#define CONFIG_CMD_SF -#define CONFIG_DM_SPI_FLASH -#endif - -/* - * eTSEC - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 1 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC2" - -#define CONFIG_PHY_ATHEROS - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 -#endif - -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ - -#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_CMD_MII - -#define CONFIG_CMDLINE_TAG - -#define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define COUNTER_FREQUENCY 12500000 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 256 - -#define CONFIG_FSL_DEVICE_DISABLE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ -"initrd_high=0xffffffff\0" \ -"fdt_high=0xffffffff\0" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MEMINFO - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_LS102XA_STREAM_ID - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -/* start of monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 - -/* - * Environment - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x100000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x100000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#endif - -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -#include - -#endif diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h deleted file mode 100644 index 66771e2..0000000 --- a/include/configs/ls1021aqds.h +++ /dev/null @@ -1,515 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARMV7_PSCI_1_0 - -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR - -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_DEEP_SLEEP - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#define CONFIG_QIXIS_I2C_ACCESS -#else -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#endif - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg -#endif - -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MONITOR_LEN 0xc0000 -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg - -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - -#define CONFIG_DDR_SPD -#define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -/* - * IFC Definitions - */ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_IFC -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) - -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1a) | \ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0xe) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} - -/* - * NAND Flash Definitions - */ -#define CONFIG_NAND_FSL_IFC - -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x7) | \ - FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0xe) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ - FTIM2_NAND_TREH(0xa) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#endif - -/* - * QIXIS Definitions - */ -#define CONFIG_FSL_QIXIS - -#ifdef CONFIG_FSL_QIXIS -#define QIXIS_BASE 0x7fb00000 -#define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_PWR_CTL 0x21 -#define QIXIS_PWR_CTL_POWEROFF 0x80 -#define QIXIS_RST_CTL_RESET 0x44 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_CTL_SYS 0x5 -#define QIXIS_CTL_SYS_EVTSW_MASK 0x0c -#define QIXIS_CTL_SYS_EVTSW_IRQ 0x04 -#define QIXIS_RST_FORCE_3 0x45 -#define QIXIS_RST_FORCE_3_PCIESLOT1 0x80 -#define QIXIS_PWR_CTL2 0x21 -#define QIXIS_PWR_CTL2_PCTL 0x2 - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) - -/* - * QIXIS Timing parameters for IFC GPCM - */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \ - FTIM0_GPCM_TEADC(0xe) | \ - FTIM0_GPCM_TEAHC(0xe)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \ - FTIM2_GPCM_TCH(0xe) | \ - FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#endif - -#if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 -#endif - -/* - * Serial Port - */ -#ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG -#else -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * I2C bus multiplexer - */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_CH7301 0xC - -/* - * MMC - */ - -/* SPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -/* QSPI */ -#define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - -/* DSPI */ - -/* DM SPI */ -#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) -#define CONFIG_DM_SPI_FLASH -#define CONFIG_SPI_FLASH_DATAFLASH -#endif -#endif - -/* - * Video - */ -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO - -#define CONFIG_FSL_DIU_CH7301 -#define CONFIG_SYS_I2C_DVI_BUS_NUM 0 -#define CONFIG_SYS_I2C_QIXIS_ADDR 0x66 -#define CONFIG_SYS_I2C_DVI_ADDR 0x75 -#endif - -/* - * eTSEC - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_MII_DEFAULT_TSEC 3 -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" - -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 2 -#define TSEC3_PHY_ADDR 3 - -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 - -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_PHY_REALTEK - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH2 - -#define CONFIG_FSL_SGMII_RISER 1 -#define SGMII_RISER_PHY_OFFSET 0x1b - -#ifdef CONFIG_FSL_SGMII_RISER -#define CONFIG_SYS_TBIPA_VALUE 8 -#endif - -#endif - -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_CMDLINE_TAG - -#define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define COUNTER_FREQUENCY 12500000 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 256 - -#define CONFIG_FSL_DEVICE_DISABLE - - -#define CONFIG_SYS_QE_FW_ADDR 0x60940000 - -#ifdef CONFIG_LPUART -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" -#endif - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_LS102XA_STREAM_ID - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#elif defined(CONFIG_NAND_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#include -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#endif diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h deleted file mode 100644 index b011cb2..0000000 --- a/include/configs/ls1021atsn.h +++ /dev/null @@ -1,250 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * Copyright 2016-2018 NXP Semiconductors - * Copyright 2019 Vladimir Oltean - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR - -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_DEEP_SLEEP - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE - -/* XHCI Support - enabled by default */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -#define DDR_SDRAM_CFG 0x470c0008 -#define DDR_CS0_BNDS 0x008000bf -#define DDR_CS0_CONFIG 0x80014302 -#define DDR_TIMING_CFG_0 0x50550004 -#define DDR_TIMING_CFG_1 0xbcb38c56 -#define DDR_TIMING_CFG_2 0x0040d120 -#define DDR_TIMING_CFG_3 0x010e1000 -#define DDR_TIMING_CFG_4 0x00000001 -#define DDR_TIMING_CFG_5 0x03401400 -#define DDR_SDRAM_CFG_2 0x00401010 -#define DDR_SDRAM_MODE 0x00061c60 -#define DDR_SDRAM_MODE_2 0x00180000 -#define DDR_SDRAM_INTERVAL 0x18600618 -#define DDR_DDR_WRLVL_CNTL 0x8655f605 -#define DDR_DDR_WRLVL_CNTL_2 0x05060607 -#define DDR_DDR_WRLVL_CNTL_3 0x05050505 -#define DDR_DDR_CDR1 0x80040000 -#define DDR_DDR_CDR2 0x00000001 -#define DDR_SDRAM_CLK_CNTL 0x02000000 -#define DDR_DDR_ZQ_CNTL 0x89080600 -#define DDR_CS0_CONFIG_2 0 -#define DDR_SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG2_D_INIT 0x00000010 -#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 -#define SDRAM_CFG2_FRC_SR 0x80000000 -#define SDRAM_CFG_BI 0x00000001 - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - "board/freescale/ls1021atsn/ls102xa_pbi.cfg" -#endif - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg" - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_SECURE_BOOT */ - -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw U-Boot image instead of FIT image. - */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ -#endif - -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x80000000 -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif -#define CONFIG_SYS_NS16550_CLK get_serial_clock() - -#define CONFIG_BAUDRATE 115200 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* QSPI */ -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_LAYERSCAPE_NS_ACCESS -#define COUNTER_FREQUENCY 12500000 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 256 - -#define CONFIG_FSL_DEVICE_DISABLE - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x61000000\0" \ - "kernelheader_addr=0x60800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x80008000\0" \ - "kernelheader_size=0x40000\0" \ - "fdt_addr_r=0x8f000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "load_addr=0x80008000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ - BOOTENV \ - "boot_scripts=ls1021atsn_boot.scr\0" \ - "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "run scan_dev_for_extlinux; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo && mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_LS102XA_STREAM_ID - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* Environment */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x20000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_ENV_SECT_SIZE 0x40000 -#endif - -#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */ - -#endif diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h deleted file mode 100644 index 31abee8..0000000 --- a/include/configs/ls1021atwr.h +++ /dev/null @@ -1,477 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_ARMV7_PSCI_1_0 - -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR - -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_DEEP_SLEEP - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024) - -#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -#define DDR_SDRAM_CFG 0x470c0008 -#define DDR_CS0_BNDS 0x008000bf -#define DDR_CS0_CONFIG 0x80014302 -#define DDR_TIMING_CFG_0 0x50550004 -#define DDR_TIMING_CFG_1 0xbcb38c56 -#define DDR_TIMING_CFG_2 0x0040d120 -#define DDR_TIMING_CFG_3 0x010e1000 -#define DDR_TIMING_CFG_4 0x00000001 -#define DDR_TIMING_CFG_5 0x03401400 -#define DDR_SDRAM_CFG_2 0x00401010 -#define DDR_SDRAM_MODE 0x00061c60 -#define DDR_SDRAM_MODE_2 0x00180000 -#define DDR_SDRAM_INTERVAL 0x18600618 -#define DDR_DDR_WRLVL_CNTL 0x8655f605 -#define DDR_DDR_WRLVL_CNTL_2 0x05060607 -#define DDR_DDR_WRLVL_CNTL_3 0x05050505 -#define DDR_DDR_CDR1 0x80040000 -#define DDR_DDR_CDR2 0x00000001 -#define DDR_SDRAM_CLK_CNTL 0x02000000 -#define DDR_DDR_ZQ_CNTL 0x89080600 -#define DDR_CS0_CONFIG_2 0 -#define DDR_SDRAM_CFG_MEM_EN 0x80000000 -#define SDRAM_CFG2_D_INIT 0x00000010 -#define DDR_CDR2_VREF_TRAIN_EN 0x00000080 -#define SDRAM_CFG2_FRC_SR 0x80000000 -#define SDRAM_CFG_BI 0x00000001 - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg -#endif - -#ifdef CONFIG_SECURE_BOOT -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. - */ -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_SECURE_BOOT */ - -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SPL_PAD_TO 0x1c000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ -#endif - -#define PHYS_SDRAM 0x80000000 -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -/* - * IFC Definitions - */ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_IFC -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TAVDS(0x0) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1A) | \ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWP(0x1c) | \ - FTIM2_NOR_TWPH(0x0e)) -#define CONFIG_SYS_NOR_FTIM3 0 - -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } - -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_WRITE_SWAPPED_DATA -#endif - -/* CPLD */ - -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) - -/* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ - FTIM0_GPCM_TEADC(0xf) | \ - FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3 - -/* - * Serial Port - */ -#ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG -#else -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif -#define CONFIG_SYS_NS16550_CLK get_serial_clock() -#endif - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * MMC - */ - -/* SPI */ -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -/* QSPI */ -#define QSPI0_AMBA_BASE 0x40000000 -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 - -/* DSPI */ -#endif - -/* DM SPI */ -#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) -#define CONFIG_DM_SPI_FLASH -#endif - -/* - * Video - */ -#ifdef CONFIG_VIDEO_FSL_DCU_FB -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO - -#define CONFIG_FSL_DCU_SII9022A -#define CONFIG_SYS_I2C_DVI_BUS_NUM 1 -#define CONFIG_SYS_I2C_DVI_ADDR 0x39 -#endif - -/* - * eTSEC - */ - -#ifdef CONFIG_TSEC_ENET -#define CONFIG_ETHPRIME "ethernet@2d10000" -#endif - -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -#define CONFIG_CMDLINE_TAG - -#define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LAYERSCAPE_NS_ACCESS -#define CONFIG_SMP_PEN_ADDR 0x01ee0200 -#define COUNTER_FREQUENCY 12500000 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 256 - -#define CONFIG_FSL_DEVICE_DISABLE - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include - -#ifdef CONFIG_LPUART -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x65000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - BOOTENV \ - "boot_scripts=ls1021atwr_boot.scr\0" \ - "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ - "env exists secureboot " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "installer=load mmc 0:2 $load_addr " \ - "/flex_installer_arm32.itb; " \ - "bootm $load_addr#ls1021atwr\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size && bootm $load_addr#$board\0" \ - "nor_bootcmd=echo Trying load from nor..;" \ - "cp.b $kernel_addr $load_addr " \ - "$kernel_size && bootm $load_addr#$board\0" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x61000000\0" \ - "kernelheader_addr=0x60800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "kernelheader_size=0x40000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ - BOOTENV \ - "boot_scripts=ls1021atwr_boot.scr\0" \ - "boot_script_hdr=hdr_ls1021atwr_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "nor_bootcmd=echo Trying load from nor..;" \ - "cp.b $kernel_addr $load_addr " \ - "$kernel_size; env exists secureboot " \ - "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo && mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" -#endif - -#undef CONFIG_BOOTCOMMAND -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt" -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#else -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;" \ - "env exists secureboot && esbc_halt;" -#endif - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_LS102XA_STREAM_ID - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_SYS_QE_FW_ADDR 0x60940000 - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x20000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ -#endif - -#include -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#endif diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h deleted file mode 100644 index 40fcd22..0000000 --- a/include/configs/ls1028a_common.h +++ /dev/null @@ -1,203 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#ifndef __L1028A_COMMON_H -#define __L1028A_COMMON_H - -#define CONFIG_REMAKE_ELF -#define CONFIG_FSL_LAYERSCAPE -#define CONFIG_MP - -#include -#include -#include - -/* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 - -#define CONFIG_CMD_MEMTEST -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -/* - * SMP Definitinos - */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#endif - -/* Serial Port */ -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) - -/* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) -#include - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "board=ls1028ardb\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ - "kernel_addr=0x01000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ - "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - BOOTENV \ - "boot_scripts=ls1028ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "emmc_bootcmd=echo Trying load from EMMC ..;" \ - "mmcinfo; mmc dev 1; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" - -#undef CONFIG_BOOTCOMMAND - -#define SD_BOOTCOMMAND \ - "run distro_bootcmd;run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ - -#ifndef CONFIG_CMDLINE_EDITING -#define CONFIG_CMDLINE_EDITING 1 -#endif - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define OCRAM_NONSECURE_SIZE 0x00010000 -#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 -#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_SECT_SIZE 0x40000 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/* I2C bus multiplexer */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ -#define I2C_MUX_CH_DEFAULT 0x8 - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -#ifdef CONFIG_SECURE_BOOT -#include -#endif - -/* Ethernet */ -/* smallest ENETC BD ring has 8 entries */ -#define CONFIG_SYS_RX_ETH_BUFFER 8 - -#endif /* __L1028A_COMMON_H */ diff --git a/include/configs/ls1028aqds.h b/include/configs/ls1028aqds.h deleted file mode 100644 index b0e9441..0000000 --- a/include/configs/ls1028aqds.h +++ /dev/null @@ -1,160 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#ifndef __LS1028A_QDS_H -#define __LS1028A_QDS_H - -#include "ls1028a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) - -/* DDR */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 - -#define CONFIG_QIXIS_I2C_ACCESS - -/* - * QIXIS Definitions - */ -#define CONFIG_FSL_QIXIS - -#ifdef CONFIG_FSL_QIXIS -#define QIXIS_BASE 0x7fb00000 -#define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_LBMAP_SWITCH 1 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 5 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x00 -#define QIXIS_LBMAP_SD 0x00 -#define QIXIS_LBMAP_EMMC 0x00 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_SD 0x8 -#define QIXIS_RCW_SRC_EMMC 0x9 -#define QIXIS_RCW_SRC_QSPI 0xf -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) -#endif - -/* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 1 -#define I2C_MUX_CH_RTC 0xB - -/* Store environment at top of flash */ -#define CONFIG_ENV_SIZE 0x2000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#ifndef CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT2 -#endif -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -/* DSPI */ -#ifdef CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON -#endif - -#ifndef SPL_NO_ENV -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "board=ls1028aqds\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x00f00000\0" \ - "kernel_addr=0x01000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ - "console=ttyS0,115200\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - BOOTENV \ - "boot_scripts=ls1028aqds_boot.scr\0" \ - "boot_script_hdr=hdr_ls1028aqds_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "scan_dev_for_boot=" \ - "echo Scanning ${devtype} " \ - "${devnum}:${distro_bootpart}...; " \ - "for prefix in ${boot_prefixes}; do " \ - "run scan_dev_for_scripts; " \ - "done;" \ - "\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "emmc_bootcmd=echo Trying load from EMMC ..;" \ - "mmcinfo; mmc dev 1; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" -#endif -#endif /* __LS1028A_QDS_H */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h deleted file mode 100644 index b77c36d..0000000 --- a/include/configs/ls1028ardb.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#ifndef __LS1028A_RDB_H -#define __LS1028A_RDB_H - -#include "ls1028a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) - -#define CONFIG_SYS_RTC_BUS_NUM 0 - -/* Store environment at top of flash */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_QIXIS_I2C_ACCESS - -/* - * QIXIS Definitions - */ -#define CONFIG_FSL_QIXIS - -#ifdef CONFIG_FSL_QIXIS -#define QIXIS_BASE 0x7fb00000 -#define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_LBMAP_SWITCH 2 -#define QIXIS_LBMAP_MASK 0xe0 -#define QIXIS_LBMAP_SHIFT 0x5 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x00 -#define QIXIS_LBMAP_SD 0x00 -#define QIXIS_LBMAP_EMMC 0x00 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_SD 0xf8 -#define QIXIS_RCW_SRC_EMMC 0xf9 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x10 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x11 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) -#endif - -/* SATA */ -#ifndef CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT2 -#endif -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#define SCSI_VEND_ID 0x1b4b -#define SCSI_DEV_ID 0x9170 -#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 - -#endif /* __LS1028A_RDB_H */ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h deleted file mode 100644 index 70447a2..0000000 --- a/include/configs/ls1043a_common.h +++ /dev/null @@ -1,336 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor - */ - -#ifndef __LS1043A_COMMON_H -#define __LS1043A_COMMON_H - -/* SPL build */ -#ifdef CONFIG_SPL_BUILD -#define SPL_NO_FMAN -#define SPL_NO_DSPI -#define SPL_NO_PCIE -#define SPL_NO_ENV -#define SPL_NO_MISC -#define SPL_NO_USB -#define SPL_NO_SATA -#define SPL_NO_QE -#define SPL_NO_EEPROM -#endif -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) -#define SPL_NO_MMC -#endif -#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) -#define SPL_NO_IFC -#endif - -#define CONFIG_REMAKE_ELF -#define CONFIG_GICV2 - -#include -#include - -/* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL - -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* SD boot SPL */ -#ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_MAX_SIZE 0x17000 -#define CONFIG_SPL_STACK 0x1001e000 -#define CONFIG_SPL_PAD_TO 0x1d000 - -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_SECURE_BOOT */ -#endif - -/* NAND SPL */ -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PBL_PAD -#define CONFIG_SPL_MAX_SIZE 0x1a000 -#define CONFIG_SPL_STACK 0x1001d000 -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -#endif /* ifdef CONFIG_SECURE_BOOT */ - -#ifdef CONFIG_U_BOOT_HDR_SIZE -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ - -#endif - -/* IFC */ -#ifndef SPL_NO_IFC -#if defined(CONFIG_TFABOOT) || \ - (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) -#define CONFIG_FSL_IFC -/* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address - * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting - */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#endif -#endif -#endif - -/* I2C */ -#define CONFIG_SYS_I2C - -/* PCIe */ -#ifndef SPL_NO_PCIE -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif -#endif - -/* Command line configuration */ - -/* MMC */ -#ifndef SPL_NO_MMC -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif -#endif - -/* DSPI */ -#ifndef SPL_NO_DSPI -#define CONFIG_FSL_DSPI -#ifdef CONFIG_FSL_DSPI -#define CONFIG_DM_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ -#define CONFIG_SPI_FLASH_SST /* cs1 */ -#define CONFIG_SPI_FLASH_EON /* cs2 */ -#endif -#endif - -/* FMan ucode */ -#ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 -#define CONFIG_SYS_QE_FW_ADDR 0x940000 - - -#else -#ifdef CONFIG_NAND_BOOT -/* Store Fman ucode at offeset 0x900000(72 blocks). */ -#define CONFIG_SYS_FMAN_FW_ADDR (72 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SD_BOOT) -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2040 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) -#define CONFIG_SYS_QE_FW_ADDR (512 * 0x4A00) -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 -#else -/* FMan fireware Pre-load address */ -#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 -#define CONFIG_SYS_QE_FW_ADDR 0x60940000 -#endif -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 - -#ifndef SPL_NO_MISC -#ifndef CONFIG_SPL_BUILD -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include -#endif - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x61000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernelheader_addr=0x60800000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ - "console=ttyS0,115200\0" \ - "boot_os=y\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - BOOTENV \ - "boot_scripts=ls1043ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ - "env exists secureboot " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "nor_bootcmd=echo Trying load from nor..;" \ - "cp.b $kernel_addr $load_addr " \ - "$kernel_size; env exists secureboot " \ - "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "nand_bootcmd=echo Trying load from NAND..;" \ - "nand info; nand read $load_addr " \ - "$kernel_start $kernel_size; env exists secureboot " \ - "&& nand read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" - - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#else -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#else -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#endif -#endif -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#include - -#endif /* __LS1043A_COMMON_H */ diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h deleted file mode 100644 index 0ea3ca0..0000000 --- a/include/configs/ls1043aqds.h +++ /dev/null @@ -1,445 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1043AQDS_H__ -#define __LS1043AQDS_H__ - -#include "ls1043a_common.h" - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_LAYERSCAPE_NS_ACCESS - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -/* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_DDR_SPD -#define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHYLIB_10G -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -/* PHY address on QSGMII riser card on slot 1 */ -#define QSGMII_CARD_PORT1_PHY_ADDR_S1 0x4 -#define QSGMII_CARD_PORT2_PHY_ADDR_S1 0x5 -#define QSGMII_CARD_PORT3_PHY_ADDR_S1 0x6 -#define QSGMII_CARD_PORT4_PHY_ADDR_S1 0x7 -/* PHY address on QSGMII riser card on slot 2 */ -#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 -#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 -#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA -#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB -#endif - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043aqds/ls1043aqds_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_nand.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1043aqds/ls1043aqds_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043aqds/ls1043aqds_rcw_sd_ifc.cfg -#endif -#endif - -/* LPUART */ -#ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG -#endif - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -/* - * IFC Definitions - */ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) - -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1a) | \ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0xe) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} - -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -/* - * NAND Flash Definitions - */ -#define CONFIG_NAND_FSL_IFC - -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x7) | \ - FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0xe) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ - FTIM2_NAND_TREH(0xa) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 << 10) -#endif - -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT -#endif - -/* - * QIXIS Definitions - */ -#define CONFIG_FSL_QIXIS - -#ifdef CONFIG_FSL_QIXIS -#define QIXIS_BASE 0x7fb00000 -#define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_LBMAP_NAND 0x09 -#define QIXIS_LBMAP_SD 0x00 -#define QIXIS_LBMAP_SD_QSPI 0xff -#define QIXIS_LBMAP_QSPI 0xff -#define QIXIS_RCW_SRC_NAND 0x106 -#define QIXIS_RCW_SRC_SD 0x040 -#define QIXIS_RCW_SRC_QSPI 0x045 -#define QIXIS_RST_CTL_RESET 0x41 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) - -/* - * QIXIS Timing parameters for IFC GPCM - */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ - FTIM0_GPCM_TEADC(0x20) | \ - FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#endif - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 -#else -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 -#endif -#endif - -/* - * I2C bus multiplexer - */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_CH7301 0xC -#define I2C_MUX_CH5 0xD -#define I2C_MUX_CH7 0xF - -#define I2C_MUX_CH_VOL_MONITOR 0xa - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -#define CONFIG_VID_FLS_ENV "ls1043aqds_vdd_mv" -#ifndef CONFIG_SPL_BUILD -#define CONFIG_VID -#endif -#define CONFIG_VOL_MONITOR_IR36021_SET -#define CONFIG_VOL_MONITOR_INA220 -/* The lowest and highest voltage allowed for LS1043AQDS */ -#define VDD_MV_MIN 819 -#define VDD_MV_MAX 1212 - -/* QSPI device */ -#if defined(CONFIG_TFABOOT) || \ - (defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)) -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 -#endif -#endif - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#else -#ifdef CONFIG_NAND_BOOT -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#endif -#endif - -#define CONFIG_CMDLINE_TAG - -#include - -#endif /* __LS1043AQDS_H__ */ diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h deleted file mode 100644 index d2979ef..0000000 --- a/include/configs/ls1043ardb.h +++ /dev/null @@ -1,310 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2015 Freescale Semiconductor - */ - -#ifndef __LS1043ARDB_H__ -#define __LS1043ARDB_H__ - -#include "ls1043a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -#define CONFIG_LAYERSCAPE_NS_ACCESS - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -/* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#ifndef CONFIG_SPL -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1043ardb/ls1043ardb_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_nand.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg -#define CONFIG_CMD_SPL -#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x10000 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x500 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 30 -#endif - -/* - * NOR Flash Definitions - */ -#define CONFIG_SYS_NOR_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) - -/* NOR Flash Timing Params */ -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TAVDS(0x0) | \ - FTIM0_NOR_TEAHC(0xc)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1c) | \ - FTIM1_NOR_TRAD_NOR(0xb) | \ - FTIM1_NOR_TSEQRAD_NOR(0x9)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x1) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x8) | \ - FTIM2_NOR_TWP(0x10)) -#define CONFIG_SYS_NOR_FTIM3 0 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } - -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -/* - * NAND Flash Definitions - */ -#ifndef SPL_NO_IFC -#define CONFIG_NAND_FSL_IFC -#endif - -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x7) | \ - FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0xe) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ - FTIM2_NAND_TREH(0xa) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x20000 /* block aligned */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 << 10) -#endif - -/* - * CPLD - */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE - -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) - -/* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ - FTIM0_GPCM_TEADC(0xf) | \ - FTIM0_GPCM_TEAHC(0xf)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0xff)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 - -/* IFC Timing Params */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#else -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 -#endif -#endif - -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 - -/* EEPROM */ -#ifndef SPL_NO_EEPROM -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#endif - -/* - * Environment - */ -#ifndef SPL_NO_ENV -#define CONFIG_ENV_OVERWRITE -#endif - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x500000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#else -#if defined(CONFIG_NAND_BOOT) -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (24 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#endif -#endif - -/* FMan */ -#ifndef SPL_NO_FMAN -#define AQR105_IRQ_MASK 0x40000000 - -#ifdef CONFIG_NET -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 - -#define QSGMII_PORT1_PHY_ADDR 0x4 -#define QSGMII_PORT2_PHY_ADDR 0x5 -#define QSGMII_PORT3_PHY_ADDR 0x6 -#define QSGMII_PORT4_PHY_ADDR 0x7 - -#define FM1_10GEC1_PHY_ADDR 0x1 - -#define CONFIG_ETHPRIME "FM1@DTSEC3" -#endif -#endif - -/* SATA */ -#ifndef SPL_NO_SATA -#ifndef CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT2 -#endif -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 2 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#define SCSI_VEND_ID 0x1b4b -#define SCSI_DEV_ID 0x9170 -#define CONFIG_SCSI_DEV_LIST {SCSI_VEND_ID, SCSI_DEV_ID} -#endif - -#include - -#endif /* __LS1043ARDB_H__ */ diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h deleted file mode 100644 index 59c43f1..0000000 --- a/include/configs/ls1046a_common.h +++ /dev/null @@ -1,290 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor - * Copyright 2019 NXP - */ - -#ifndef __LS1046A_COMMON_H -#define __LS1046A_COMMON_H - -/* SPL build */ -#ifdef CONFIG_SPL_BUILD -#define SPL_NO_QBMAN -#define SPL_NO_FMAN -#define SPL_NO_ENV -#define SPL_NO_MISC -#define SPL_NO_QSPI -#define SPL_NO_USB -#define SPL_NO_SATA -#endif -#if defined(CONFIG_SPL_BUILD) && \ - (defined(CONFIG_NAND_BOOT) || defined(CONFIG_QSPI_BOOT)) -#define SPL_NO_MMC -#endif -#if defined(CONFIG_SPL_BUILD) && \ - !defined(CONFIG_SPL_FSL_LS_PPA) -#define SPL_NO_IFC -#endif - -#define CONFIG_REMAKE_ELF -#define CONFIG_GICV2 - -#include -#include - -/* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL - -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* SD boot SPL */ -#ifdef CONFIG_SD_BOOT -#define CONFIG_SPL_MAX_SIZE 0x1f000 /* 124 KiB */ -#define CONFIG_SPL_STACK 0x10020000 -#define CONFIG_SPL_PAD_TO 0x21000 /* 132 KiB */ -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_SECURE_BOOT */ -#endif - -#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) -#define CONFIG_SPL_TARGET "spl/u-boot-spl.pbl" -#define CONFIG_SPL_MAX_SIZE 0x1f000 -#define CONFIG_SPL_STACK 0x10020000 -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#endif - -/* NAND SPL */ -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PBL_PAD -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_ENV_SUPPORT -#define CONFIG_SPL_WATCHDOG_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT - -#define CONFIG_SPL_NAND_SUPPORT -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#define CONFIG_SPL_MAX_SIZE 0x17000 /* 90 KiB */ -#define CONFIG_SPL_STACK 0x1001f000 -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SPL_BSS_START_ADDR 0x8f000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 -#define CONFIG_SYS_MONITOR_LEN 0xa0000 -#endif - -/* I2C */ -#define CONFIG_SYS_I2C - -/* PCIe */ -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* SATA */ -#ifndef SPL_NO_SATA -#define CONFIG_SCSI_AHCI_PLAT - -#define CONFIG_SYS_SATA AHCI_BASE_ADDR - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#endif - -/* Command line configuration */ - -/* MMC */ -#ifndef SPL_NO_MMC -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif -#endif - -/* FMan ucode */ -#ifndef SPL_NO_FMAN -#define CONFIG_SYS_DPAA_FMAN -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#endif - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_FMAN_FW_ADDR 0x900000 -#else -#ifdef CONFIG_SD_BOOT -/* - * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is - * about 1MB (2048 blocks), Env is stored after the image, and the env size is - * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 18432(0x4800). - */ -#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x4800) -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_FMAN_FW_ADDR 0x40900000 -#elif defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_FMAN_FW_ADDR (36 * CONFIG_SYS_NAND_BLOCK_SIZE) -#else -#define CONFIG_SYS_FMAN_FW_ADDR 0x60900000 -#endif -#endif -#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 - -#ifndef CONFIG_SPL_BUILD -#define BOOT_TARGET_DEVICES(func) \ - func(SCSI, scsi, 0) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include -#endif - -#if defined(CONFIG_TARGET_LS1046AFRWY) -#define LS1046A_BOOT_SRC_AND_HDR\ - "boot_scripts=ls1046afrwy_boot.scr\0" \ - "boot_script_hdr=hdr_ls1046afrwy_bs.out\0" -#else -#define LS1046A_BOOT_SRC_AND_HDR\ - "boot_scripts=ls1046ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1046ardb_bs.out\0" -#endif -#ifndef SPL_NO_MISC -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x65000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernelhdr_size_sd=0x10\0" \ - "console=ttyS0,115200\0" \ - CONFIG_MTDPARTS_DEFAULT "\0" \ - BOOTENV \ - LS1046A_BOOT_SRC_AND_HDR \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ - "env exists secureboot " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_start $kernel_size; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ - "bootm $load_addr#$board\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" - -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#include - -#endif /* __LS1046A_COMMON_H */ diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h deleted file mode 100644 index 8609ebf..0000000 --- a/include/configs/ls1046afrwy.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2019 NXP - */ - -#ifndef __LS1046AFRWY_H__ -#define __LS1046AFRWY_H__ - -#include "ls1046a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -#define CONFIG_LAYERSCAPE_NS_ACCESS - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_SYS_UBOOT_BASE 0x40100000 - -/* IFC */ -#define CONFIG_FSL_IFC -/* - * NAND Flash Definitions - */ -#define CONFIG_NAND_FSL_IFC - -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x7) | \ - FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0xe) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ - FTIM2_NAND_TREH(0xa) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define I2C_RETIMER_ADDR 0x18 - -/* I2C bus multiplexer */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ -#define I2C_MUX_CH_DEFAULT 0x1 /* Channel 0*/ -#define I2C_MUX_CH_RTC 0x1 /* Channel 0*/ - -/* RTC */ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 0 I2C bus 0*/ -#define CONFIG_SYS_RTC_BUS_NUM 0 - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ - CONFIG_ENV_OFFSET) - -/* FMan */ -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET - -#define QSGMII_PORT1_PHY_ADDR 0x1c -#define QSGMII_PORT2_PHY_ADDR 0x1d -#define QSGMII_PORT3_PHY_ADDR 0x1e -#define QSGMII_PORT4_PHY_ADDR 0x1f - -#define FDT_SEQ_MACADDR_FROM_ENV - -#define CONFIG_ETHPRIME "FM1@DTSEC3" - -#endif - -/* QSPI device */ -#ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE SZ_64M -#define FSL_QSPI_FLASH_NUM 1 -#endif - -#undef CONFIG_BOOTCOMMAND -#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;;" -#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" - -#include - -#endif /* __LS1046AFRWY_H__ */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h deleted file mode 100644 index eea738e..0000000 --- a/include/configs/ls1046aqds.h +++ /dev/null @@ -1,478 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor, Inc. - */ - -#ifndef __LS1046AQDS_H__ -#define __LS1046AQDS_H__ - -#include "ls1046a_common.h" - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_LAYERSCAPE_NS_ACCESS - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -/* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_DDR_SPD -#define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#define CONFIG_DDR_ECC -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -/* DSPI */ -#ifdef CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_STMICRO /* cs0 */ -#define CONFIG_SPI_FLASH_SST /* cs1 */ -#define CONFIG_SPI_FLASH_EON /* cs2 */ -#endif - -/* QSPI */ -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 -#endif -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHYLIB_10G -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F -/* PHY address on QSGMII riser card on slot 2 */ -#define QSGMII_CARD_PORT1_PHY_ADDR_S2 0x8 -#define QSGMII_CARD_PORT2_PHY_ADDR_S2 0x9 -#define QSGMII_CARD_PORT3_PHY_ADDR_S2 0xA -#define QSGMII_CARD_PORT4_PHY_ADDR_S2 0xB -#endif - -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1046aqds/ls1046aqds_pbi.cfg -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_nand.cfg -#endif - -#ifdef CONFIG_SD_BOOT -#ifdef CONFIG_SD_BOOT_QSPI -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_sd_qspi.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046aqds/ls1046aqds_rcw_sd_ifc.cfg -#endif -#endif - -/* IFC */ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_FSL_IFC -/* - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address - * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting - */ -#define CONFIG_SYS_FLASH_BASE 0x60000000 -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#endif -#endif - -/* LPUART */ -#ifdef CONFIG_LPUART -#define CONFIG_LPUART_32B_REG -#define CFG_UART_MUX_MASK 0x6 -#define CFG_UART_MUX_SHIFT 1 -#define CFG_LPUART_EN 0x2 -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* - * IFC Definitions - */ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \ - + 0x8000000) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) - -#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_TRHZ_80) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TAVDS(0x6) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1a) | \ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ - FTIM2_NOR_TCH(0x8) | \ - FTIM2_NOR_TWPH(0xe) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0 - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \ - CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} - -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS -#define CONFIG_SYS_WRITE_SWAPPED_DATA - -/* - * NAND Flash Definitions - */ -#define CONFIG_NAND_FSL_IFC - -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) - -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x7) | \ - FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0xe) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ - FTIM2_NAND_TREH(0xa) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) -#endif - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SPL_PAD_TO 0x40000 /* block aligned */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10) -#endif - -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_EARLY_INIT -#endif - -/* - * QIXIS Definitions - */ -#define CONFIG_FSL_QIXIS - -#ifdef CONFIG_FSL_QIXIS -#define QIXIS_BASE 0x7fb00000 -#define QIXIS_BASE_PHYS QIXIS_BASE -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_LBMAP_NAND 0x09 -#define QIXIS_LBMAP_SD 0x00 -#define QIXIS_LBMAP_SD_QSPI 0xff -#define QIXIS_LBMAP_QSPI 0xff -#define QIXIS_RCW_SRC_NAND 0x110 -#define QIXIS_RCW_SRC_SD 0x040 -#define QIXIS_RCW_SRC_QSPI 0x045 -#define QIXIS_RST_CTL_RESET 0x41 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ - CSOR_NOR_NOR_MODE_AVD_NOR | \ - CSOR_NOR_TRHZ_80) - -/* - * QIXIS Timing parameters for IFC GPCM - */ -#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xc) | \ - FTIM0_GPCM_TEADC(0x20) | \ - FTIM0_GPCM_TEAHC(0x10)) -#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0x50) | \ - FTIM1_GPCM_TRAD(0x1f)) -#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0x8) | \ - FTIM2_GPCM_TCH(0x8) | \ - FTIM2_GPCM_TWP(0xf0)) -#define CONFIG_SYS_FPGA_FTIM3 0x0 -#endif - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 -#else -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3 -#endif -#endif - -/* - * I2C bus multiplexer - */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH_CH7301 0xC -#define I2C_MUX_CH5 0xD -#define I2C_MUX_CH6 0xE -#define I2C_MUX_CH7 0xF - -#define I2C_MUX_CH_VOL_MONITOR 0xa - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x40 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 - -#define CONFIG_VID_FLS_ENV "ls1046aqds_vdd_mv" -#ifndef CONFIG_SPL_BUILD -#define CONFIG_VID -#endif -#define CONFIG_VOL_MONITOR_IR36021_SET -#define CONFIG_VOL_MONITOR_INA220 -/* The lowest and highest voltage allowed for LS1046AQDS */ -#define VDD_MV_MIN 819 -#define VDD_MV_MAX 1212 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -/* - * Environment - */ -#define CONFIG_ENV_OVERWRITE - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x500000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#else -#ifdef CONFIG_NAND_BOOT -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET (12 * CONFIG_SYS_NAND_BLOCK_SIZE) -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_SECT_SIZE 0x10000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#endif -#endif - -#define CONFIG_CMDLINE_TAG - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#define QSPI_NOR_BOOTCOMMAND "sf probe && sf read $kernel_load " \ - "e0000 f00000 && bootm $kernel_load" -#define IFC_NOR_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ - "$kernel_size && bootm $kernel_load" -#define SD_BOOTCOMMAND "mmc info; mmc read $kernel_load" \ - "$kernel_addr_sd $kernel_size_sd && bootm $kernel_load" -#else -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ - "e0000 f00000 && bootm $kernel_load" -#else -#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ - "$kernel_size && bootm $kernel_load" -#endif -#endif - -#include - -#endif /* __LS1046AQDS_H__ */ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h deleted file mode 100644 index 2d20f15..0000000 --- a/include/configs/ls1046ardb.h +++ /dev/null @@ -1,233 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2016 Freescale Semiconductor - * Copyright 2019 NXP - */ - -#ifndef __LS1046ARDB_H__ -#define __LS1046ARDB_H__ - -#include "ls1046a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 - -#define CONFIG_LAYERSCAPE_NS_ACCESS - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -/* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_DDR_SPD -#define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1046ardb/ls1046ardb_pbi.cfg -#ifdef CONFIG_EMMC_BOOT -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046ardb/ls1046ardb_rcw_emmc.cfg -#else -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1046ardb/ls1046ardb_rcw_sd.cfg -#endif -#elif defined(CONFIG_QSPI_BOOT) -#define CONFIG_SYS_FSL_PBL_RCW \ - board/freescale/ls1046ardb/ls1046ardb_rcw_qspi.cfg -#define CONFIG_SYS_FSL_PBL_PBI \ - board/freescale/ls1046ardb/ls1046ardb_qspi_pbi.cfg -#define CONFIG_SYS_UBOOT_BASE 0x40100000 -#define CONFIG_SYS_SPL_ARGS_ADDR 0x90000000 -#endif - -#ifndef SPL_NO_IFC -/* IFC */ -#define CONFIG_FSL_IFC -/* - * NAND Flash Definitions - */ -#define CONFIG_NAND_FSL_IFC -#endif - -#define CONFIG_SYS_NAND_BASE 0x7e800000 -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_NAND \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_8 /* 8-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x7) | \ - FTIM0_NAND_TWH(0xa)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0xe) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \ - FTIM2_NAND_TREH(0xa) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -/* - * CPLD - */ -#define CONFIG_SYS_CPLD_BASE 0x7fb00000 -#define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE - -#define CONFIG_SYS_CPLD_CSPR_EXT (0x0) -#define CONFIG_SYS_CPLD_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ - CSPR_PORT_SIZE_8 | \ - CSPR_MSEL_GPCM | \ - CSPR_V) -#define CONFIG_SYS_CPLD_AMASK IFC_AMASK(64 * 1024) -#define CONFIG_SYS_CPLD_CSOR CSOR_NOR_ADM_SHIFT(16) - -/* CPLD Timing parameters for IFC GPCM */ -#define CONFIG_SYS_CPLD_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CPLD_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CPLD_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CPLD_FTIM3 0x0 - -/* IFC Timing Params */ -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_CPLD_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_CPLD_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_CPLD_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_CPLD_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_CPLD_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_CPLD_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#define I2C_RETIMER_ADDR 0x18 - -/* PMIC */ -#define CONFIG_POWER -#ifdef CONFIG_POWER -#define CONFIG_POWER_I2C -#endif - -/* - * Environment - */ -#ifndef SPL_NO_ENV -#define CONFIG_ENV_OVERWRITE -#endif - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 -#define CONFIG_ENV_ADDR CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET -#else -#if defined(CONFIG_SD_BOOT) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256KB */ -#endif -#endif - -#define AQR105_IRQ_MASK 0x80000000 -/* FMan */ -#ifndef SPL_NO_FMAN - -#ifdef CONFIG_NET -#define CONFIG_PHY_REALTEK -#endif - -#ifdef CONFIG_SYS_DPAA_FMAN -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 - -#define SGMII_PHY1_ADDR 0x3 -#define SGMII_PHY2_ADDR 0x4 - -#define FM1_10GEC1_PHY_ADDR 0x0 - -#define FDT_SEQ_MACADDR_FROM_ENV - -#define CONFIG_ETHPRIME "FM1@DTSEC3" -#endif - -#endif - -/* QSPI device */ -#ifndef SPL_NO_QSPI -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 26) -#define FSL_QSPI_FLASH_NUM 2 -#endif -#endif - -#ifndef SPL_NO_MISC -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;;" -#define SD_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#else -#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;;" -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "run distro_bootcmd;run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#endif -#endif -#endif - -#include - -#endif /* __LS1046ARDB_H__ */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h deleted file mode 100644 index 6f04dba..0000000 --- a/include/configs/ls1088a_common.h +++ /dev/null @@ -1,254 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017-2018 NXP - */ - -#ifndef __LS1088_COMMON_H -#define __LS1088_COMMON_H - -/* SPL build */ -#ifdef CONFIG_SPL_BUILD -#define SPL_NO_BOARDINFO -#define SPL_NO_QIXIS -#define SPL_NO_PCI -#define SPL_NO_ENV -#define SPL_NO_RTC -#define SPL_NO_USB -#define SPL_NO_SATA -#define SPL_NO_QSPI -#define SPL_NO_IFC -#undef CONFIG_DISPLAY_CPUINFO -#endif - -#define CONFIG_REMAKE_ELF - -#include -#include -#include - -#define LS1088ARDB_PB_BOARD 0x4A -/* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif - -/* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 -#else -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FSL_QSPI_BASE + \ - CONFIG_ENV_OFFSET) -#endif -#endif - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 -/* - * SMP Definitinos - */ -#define CPU_RELEASE_ADDR secondary_boot_func - -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#endif - - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) - -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#if !defined(SPL_NO_IFC) || defined(CONFIG_TARGET_LS1088AQDS) -/* IFC */ -#define CONFIG_FSL_IFC -#endif - -/* - * During booting, IFC is mapped at the region of 0x30000000. - * But this region is limited to 256MB. To accommodate NOR, promjet - * and FPGA. This region is divided as below: - * 0x30000000 - 0x37ffffff : 128MB : NOR flash - * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet - * 0x3C000000 - 0x40000000 : 64MB : FPGA etc - * - * To accommodate bigger NOR flash and other devices, we will map IFC - * chip selects to as below: - * 0x5_1000_0000..0x5_1fff_ffff Memory Hole - * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) - * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB - * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) - * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) - * - * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address - * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting - */ - -#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 - -#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 - -#ifndef __ASSEMBLY__ -unsigned long long get_qixis_addr(void); -#endif - -#define QIXIS_BASE get_qixis_addr() -#define QIXIS_BASE_PHYS 0x20000000 -#define QIXIS_BASE_PHYS_EARLY 0xC000000 - - -#define CONFIG_SYS_NAND_BASE 0x530000000ULL -#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 - - -/* MC firmware */ -/* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 - -/* Define phy_reset function to boot the MC based on mcinitcmd. - * This happens late enough to properly fixup u-boot env MAC addresses. - */ -#define CONFIG_RESET_PHY_R - -/* - * Carve out a DDR region which will not be used by u-boot/Linux - * - * It will be used by MC and Debug Server. The MC region must be - * 512MB aligned, so the min size to hide is 512MB. - */ - -#if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) -#endif -/* Command line configuration */ -#define CONFIG_CMD_CACHE - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) - -/* SATA */ -#ifdef CONFIG_SCSI -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#endif - -/* Physical Memory Map */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 - -/* #define CONFIG_DISPLAY_CPUINFO */ - -#ifndef SPL_NO_ENV -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581000000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" \ - "mcinitcmd=fsl_mc start mc 0x580a00000" \ - " 0x580e00000 \0" - -#ifndef CONFIG_TFABOOT -#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \ - "sf read 0x80001000 0xd00000 0x100000;"\ - " fsl_mc lazyapply dpl 0x80001000 &&" \ - " sf read $kernel_load $kernel_start" \ - " $kernel_size && bootm $kernel_load" -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\ - " fsl_mc lazyapply dpl 0x80001000 &&" \ - " mmc read $kernel_load $kernel_start" \ - " $kernel_size && bootm $kernel_load" -#else /* NOR BOOT*/ -#define CONFIG_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \ - " cp.b $kernel_start $kernel_load" \ - " $kernel_size && bootm $kernel_load" -#endif -#endif /* CONFIG_TFABOOT */ -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#ifdef CONFIG_SPL -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" -#define CONFIG_SPL_MAX_SIZE 0x16000 -#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) -/* - * HDR would be appended at end of image and copied to DDR along - * with U-Boot image. Here u-boot max. size is 512K. So if binary - * size increases then increase this size in case of secure boot as - * it uses raw u-boot image instead of fit image. - */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif /* ifdef CONFIG_SECURE_BOOT */ - -#endif -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#endif /* __LS1088_COMMON_H */ diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h deleted file mode 100644 index 85e2061..0000000 --- a/include/configs/ls1088aqds.h +++ /dev/null @@ -1,572 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __LS1088A_QDS_H -#define __LS1088A_QDS_H - -#include "ls1088a_common.h" - - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_MISC_INIT_R - -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x500000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_SECT_SIZE 0x40000 -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#endif -#endif - -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_QIXIS_I2C_ACCESS -#define SYS_NO_FLASH - -#undef CONFIG_CMD_IMLS -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#else -#define CONFIG_QIXIS_I2C_ACCESS -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C_EARLY_INIT -#endif -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#endif - -#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 - - -/* - * IFC Definitions - */ -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) - -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TAVDS(0x6) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1a) | \ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \ - FTIM2_NOR_TCH(0x8) | \ - FTIM2_NOR_TWPH(0xe) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#ifndef SYS_NO_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} -#endif -#endif - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_FSL_QIXIS -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_LBMAP_SWITCH 6 -#define QIXIS_QMAP_MASK 0xe0 -#define QIXIS_QMAP_SHIFT 5 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x0e -#define QIXIS_LBMAP_ALTBANK 0x2e -#define QIXIS_LBMAP_SD 0x00 -#define QIXIS_LBMAP_EMMC 0x00 -#define QIXIS_LBMAP_IFC 0x00 -#define QIXIS_LBMAP_SD_QSPI 0x0e -#define QIXIS_LBMAP_QSPI 0x0e -#define QIXIS_RCW_SRC_IFC 0x25 -#define QIXIS_RCW_SRC_SD 0x40 -#define QIXIS_RCW_SRC_EMMC 0x41 -#define QIXIS_RCW_SRC_QSPI 0x62 -#define QIXIS_RST_CTL_RESET 0x41 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 -#define QIXIS_STAT_PRES1 0xb -#define QIXIS_SDID_MASK 0x07 -#define QIXIS_ESDHC_NO_ADAPTER 0x7 - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) - -#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024) -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) -#else -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12) -#endif -/* QIXIS Timing parameters*/ -#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0x3E)) -#define SYS_FPGA_CS_FTIM3 0x0 - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 -#else -#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3 -#endif -#endif - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 - -/* - * I2C bus multiplexer - */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 -#define I2C_RETIMER_ADDR2 0x19 -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH5 0xD - -#define I2C_MUX_CH_VOL_MONITOR 0xA - -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 -#define I2C_SVDD_MONITOR_ADDR 0x4F - -#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv" -#define CONFIG_VID - -/* The lowest and highest voltage allowed for LS1088AQDS */ -#define VDD_MV_MIN 819 -#define VDD_MV_MAX 1212 - -#define CONFIG_VOL_MONITOR_LTC3882_SET -#define CONFIG_VOL_MONITOR_LTC3882_READ - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 - -#define PWM_CHANNEL0 0x0 - -/* -* RTC configuration -*/ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* QSPI device */ -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define FSL_QSPI_FLASH_SIZE (1 << 26) -#define FSL_QSPI_FLASH_NUM 2 - -#endif - -#ifdef CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON -#if !defined(CONFIG_TFABOOT) && \ - !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#endif -#endif - -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#define CONFIG_FSL_MEMAC - -/* MMC */ -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) - -/* Initial environment variables */ -#ifdef CONFIG_SECURE_BOOT -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x90100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x1000000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \ - "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \ - "sf read 0xa0e00000 0xe00000 0x100000;" \ - "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \ - "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \ - "mcmemsize=0x70000000 \0" -#else /* if !(CONFIG_SECURE_BOOT) */ -#ifdef CONFIG_TFABOOT -#define QSPI_MC_INIT_CMD \ - "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ - "sf read 0x80100000 0xE00000 0x100000;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" -#define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" -#define IFC_MC_INIT_CMD \ - "fsl_mc start mc 0x580A00000 0x580E00000\0" - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x90100000\0" \ - "kernel_addr=0x100000\0" \ - "kernel_addr_sd=0x800\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x1000000\0" \ - "kernel_start_sd=0x8000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_size_sd=0x14000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ - "sf read 0x80100000 0xE00000 0x100000;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ - "mcmemsize=0x70000000 \0" -#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \ - "sf read 0x80001000 0xd00000 0x100000;"\ - " fsl_mc lazyapply dpl 0x80001000 &&" \ - " sf read $kernel_load $kernel_start" \ - " $kernel_size && bootm $kernel_load" -#define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\ - " fsl_mc lazyapply dpl 0x80001000 &&" \ - " mmc read $kernel_load $kernel_start_sd" \ - " $kernel_size_sd && bootm $kernel_load" -#define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \ - " cp.b $kernel_start $kernel_load" \ - " $kernel_size && bootm $kernel_load" -#else -#if defined(CONFIG_QSPI_BOOT) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x90100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x1000000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ - "sf read 0x80100000 0xE00000 0x100000;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ - "mcmemsize=0x70000000 \0" -#elif defined(CONFIG_SD_BOOT) -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x90100000\0" \ - "kernel_addr=0x800\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x8000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x14000\0" \ - "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ - "mcmemsize=0x70000000 \0" -#else /* NOR BOOT */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x90100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x1000000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \ - "mcmemsize=0x70000000 \0" -#endif -#endif /* CONFIG_TFABOOT */ -#endif /* CONFIG_SECURE_BOOT */ - -#ifdef CONFIG_FSL_MC_ENET -#define CONFIG_FSL_MEMAC -#define CONFIG_PHYLIB -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHY_TERANETICS -#define RGMII_PHY1_ADDR 0x1 -#define RGMII_PHY2_ADDR 0x2 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1d -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F - -#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 -#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 -#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 -#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 -#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 -#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 -#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 -#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 -#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 -#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 -#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa -#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb -#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc -#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd -#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe -#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf - -#define CONFIG_ETHPRIME "DPMAC1@xgmii" -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ - -#endif - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) \ - func(DHCP, dhcp, na) -#include - -#include - -#endif /* __LS1088A_QDS_H */ diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h deleted file mode 100644 index b71f704..0000000 --- a/include/configs/ls1088ardb.h +++ /dev/null @@ -1,574 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - */ - -#ifndef __LS1088A_RDB_H -#define __LS1088A_RDB_H - -#include "ls1088a_common.h" - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x500000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#else -#if defined(CONFIG_QSPI_BOOT) -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_SECT_SIZE 0x40000 -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET (3 * 1024 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 -#else -#define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x20000 -#endif -#endif /* CONFIG_TFABOOT */ - -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#ifndef CONFIG_SPL_BUILD -#define CONFIG_QIXIS_I2C_ACCESS -#endif -#define SYS_NO_FLASH -#undef CONFIG_CMD_IMLS -#endif - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 100000000 -#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */ -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -#define CONFIG_DDR_SPD -#ifdef CONFIG_EMU -#define CONFIG_SYS_FSL_DDR_EMU -#define CONFIG_SYS_MXC_I2C1_SPEED 40000000 -#define CONFIG_SYS_MXC_I2C2_SPEED 40000000 -#else -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif -#define SPD_EEPROM_ADDRESS 0x51 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024) - -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#ifndef SYS_NO_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif -#endif - -#ifndef SPL_NO_IFC -#define CONFIG_NAND_FSL_IFC -#endif - -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE -#define CONFIG_CMD_NAND - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#ifndef SPL_NO_QIXIS -#define CONFIG_FSL_QIXIS -#endif - -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define QIXIS_BRDCFG4_OFFSET 0x54 -#define QIXIS_LBMAP_SWITCH 2 -#define QIXIS_QMAP_MASK 0xe0 -#define QIXIS_QMAP_SHIFT 5 -#define QIXIS_LBMAP_MASK 0x1f -#define QIXIS_LBMAP_SHIFT 5 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_SD 0x00 -#define QIXIS_LBMAP_EMMC 0x00 -#define QIXIS_LBMAP_SD_QSPI 0x00 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_SD 0x40 -#define QIXIS_RCW_SRC_EMMC 0x41 -#define QIXIS_RCW_SRC_QSPI 0x62 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_FPGA_CSPR_EXT (0x0) -#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) - -#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024) -#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0) -/* QIXIS Timing parameters*/ -#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0x3E)) -#define SYS_FPGA_CS_FTIM3 0x0 - -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR -#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL -#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR -#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3 -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#endif - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 -#define I2C_SVDD_MONITOR_ADDR 0x4F - -#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv" -#define CONFIG_VID - -/* The lowest and highest voltage allowed for LS1088ARDB */ -#define VDD_MV_MIN 819 -#define VDD_MV_MAX 1212 - -#define CONFIG_VOL_MONITOR_LTC3882_SET -#define CONFIG_VOL_MONITOR_LTC3882_READ - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 - -#define PWM_CHANNEL0 0x0 - -/* - * I2C bus multiplexer - */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 -#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ -#define I2C_RETIMER_ADDR 0x18 -#define I2C_MUX_CH_DEFAULT 0x8 -#define I2C_MUX_CH5 0xD - -#ifndef SPL_NO_RTC -/* -* RTC configuration -*/ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -#ifndef SPL_NO_QSPI -/* QSPI device */ -#if defined(CONFIG_TFABOOT) || \ - defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) -#define FSL_QSPI_FLASH_SIZE (1 << 26) -#define FSL_QSPI_FLASH_NUM 2 -#endif -#endif - -#define CONFIG_CMD_MEMINFO -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x9fffffff - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#endif - -#define CONFIG_FSL_MEMAC - -#ifndef SPL_NO_ENV -/* Initial environment variables */ -#ifdef CONFIG_TFABOOT -#define QSPI_MC_INIT_CMD \ - "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ - "sf read 0x80100000 0xE00000 0x100000;" \ - "env exists secureboot && " \ - "sf read 0x80700000 0x700000 0x40000 && " \ - "sf read 0x80740000 0x740000 0x40000 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" -#define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x10 && " \ - "mmc read 0x80740000 0x3A00 0x10 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" -#else -#if defined(CONFIG_QSPI_BOOT) -#define MC_INIT_CMD \ - "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \ - "sf read 0x80100000 0xE00000 0x100000;" \ - "env exists secureboot && " \ - "sf read 0x80700000 0x700000 0x40000 && " \ - "sf read 0x80740000 0x740000 0x40000 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ - "mcmemsize=0x70000000\0" -#elif defined(CONFIG_SD_BOOT) -#define MC_INIT_CMD \ - "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x10 && " \ - "mmc read 0x80740000 0x3A00 0x10 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ - "mcmemsize=0x70000000\0" -#endif -#endif /* CONFIG_TFABOOT */ - -#undef CONFIG_EXTRA_ENV_SETTINGS -#ifdef CONFIG_TFABOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ - "BOARD=ls1088ardb\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x1000000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernel_start=0x580100000\0" \ - "kernelheader_start=0x580800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr=0x800000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "kernelheader_size=0x40000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_size_sd=0x10\0" \ - QSPI_MC_INIT_CMD \ - "mcmemsize=0x70000000\0" \ - BOOTENV \ - "boot_scripts=ls1088ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr}; "\ - "env exists secureboot " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "installer=load mmc 0:2 $load_addr " \ - "/flex_installer_arm64.itb; " \ - "env exists mcinitcmd && run mcinitcmd && " \ - "mmc read 0x80001000 0x6800 0x800;" \ - "fsl_mc lazyapply dpl 0x80001000;" \ - "bootm $load_addr#ls1088ardb\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size ; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - "bootm $load_addr#$BOARD\0" \ - "sd_bootcmd=echo Trying load from sd card..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd ;" \ - "env exists secureboot && mmc read $kernelheader_addr_r "\ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$BOARD\0" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "BOARD=ls1088ardb\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x1000000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x4000\0" \ - "kernel_start=0x580100000\0" \ - "kernelheader_start=0x580800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr=0x800000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "kernelheader_size=0x40000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_size_sd=0x10\0" \ - MC_INIT_CMD \ - BOOTENV \ - "boot_scripts=ls1088ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1088ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "installer=load mmc 0:2 $load_addr " \ - "/flex_installer_arm64.itb; " \ - "env exists mcinitcmd && run mcinitcmd && " \ - "mmc read 0x80001000 0x6800 0x800;" \ - "fsl_mc lazyapply dpl 0x80001000;" \ - "bootm $load_addr#ls1088ardb\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_addr $kernel_size ; env exists secureboot " \ - "&& sf read $kernelheader_addr_r $kernelheader_addr " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - "bootm $load_addr#$BOARD\0" \ - "sd_bootcmd=echo Trying load from sd card..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd ;" \ - "env exists secureboot && mmc read $kernelheader_addr_r "\ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$BOARD\0" -#endif /* CONFIG_TFABOOT */ - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_TFABOOT -#define QSPI_NOR_BOOTCOMMAND \ - "sf read 0x80001000 0xd00000 0x100000;" \ - "env exists mcinitcmd && env exists secureboot " \ - " && sf read 0x80780000 0x780000 0x100000 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ - "&& fsl_mc lazyapply dpl 0x80001000;" \ - "run distro_bootcmd;run qspi_bootcmd;" \ - "env exists secureboot && esbc_halt;" -#define SD_BOOTCOMMAND \ - "env exists mcinitcmd && mmcinfo; " \ - "mmc read 0x80001000 0x6800 0x800; " \ - "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x10 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ - "&& fsl_mc lazyapply dpl 0x80001000;" \ - "run distro_bootcmd;run sd_bootcmd;" \ - "env exists secureboot && esbc_halt;" -#else -#if defined(CONFIG_QSPI_BOOT) -/* Try to boot an on-QSPI kernel first, then do normal distro boot */ -#define CONFIG_BOOTCOMMAND \ - "sf read 0x80001000 0xd00000 0x100000;" \ - "env exists mcinitcmd && env exists secureboot " \ - " && sf read 0x80780000 0x780000 0x100000 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ - "&& fsl_mc lazyapply dpl 0x80001000;" \ - "run distro_bootcmd;run qspi_bootcmd;" \ - "env exists secureboot && esbc_halt;" - -/* Try to boot an on-SD kernel first, then do normal distro boot */ -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_BOOTCOMMAND \ - "env exists mcinitcmd && mmcinfo; " \ - "mmc read 0x80001000 0x6800 0x800; " \ - "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x10 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ - "&& fsl_mc lazyapply dpl 0x80001000;" \ - "run distro_bootcmd;run sd_bootcmd;" \ - "env exists secureboot && esbc_halt;" -#endif -#endif /* CONFIG_TFABOOT */ - -/* MAC/PHY configuration */ -#ifdef CONFIG_FSL_MC_ENET -#define CONFIG_PHYLIB - -#define CONFIG_PHY_VITESSE -#define AQ_PHY_ADDR1 0x00 -#define AQR105_IRQ_MASK 0x00000004 - -#define QSGMII1_PORT1_PHY_ADDR 0x0c -#define QSGMII1_PORT2_PHY_ADDR 0x0d -#define QSGMII1_PORT3_PHY_ADDR 0x0e -#define QSGMII1_PORT4_PHY_ADDR 0x0f -#define QSGMII2_PORT1_PHY_ADDR 0x1c -#define QSGMII2_PORT2_PHY_ADDR 0x1d -#define QSGMII2_PORT3_PHY_ADDR 0x1e -#define QSGMII2_PORT4_PHY_ADDR 0x1f - -#define CONFIG_ETHPRIME "DPMAC1@xgmii" -#define CONFIG_PHY_GIGE -#endif -#endif - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -#ifndef SPL_NO_ENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) \ - func(DHCP, dhcp, na) -#include -#endif - -#include - -#endif /* __LS1088A_RDB_H */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h deleted file mode 100644 index 6be581a..0000000 --- a/include/configs/ls2080a_common.h +++ /dev/null @@ -1,226 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017 NXP - * Copyright (C) 2014 Freescale Semiconductor - */ - -#ifndef __LS2_COMMON_H -#define __LS2_COMMON_H - -#define CONFIG_REMAKE_ELF -#define CONFIG_GICV3 - -#include -#include - -/* Link Definitions */ -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#else -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) -#endif - -/* We need architecture specific misc initializations */ - -/* Link Definitions */ -#ifndef CONFIG_TFABOOT -#ifndef CONFIG_QSPI_BOOT -#else -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */ -#define CONFIG_ENV_SECT_SIZE 0x40000 -#endif -#endif - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#ifndef CONFIG_SYS_FSL_DDR4 -#define CONFIG_SYS_DDR_RAW_TIMING -#endif - -#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ - -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 - -/* - * SMP Definitinos - */ -#define CPU_RELEASE_ADDR secondary_boot_func - -#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL -/* - * DDR controller use 0 as the base address for binding. - * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access. - */ -#define CONFIG_SYS_DP_DDR_BASE_PHY 0 -#define CONFIG_DP_DDR_CTRL 2 -#define CONFIG_DP_DDR_NUM_CTRLS 1 -#endif - -/* Generic Timer Definitions */ -/* - * This is not an accurate number. It is used in start.S. The frequency - * will be udpated later when get_bus_freq(0) is available. - */ -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - -/* I2C */ -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#endif - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_serial_clock()) - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* IFC */ -#define CONFIG_FSL_IFC - -/* - * During booting, IFC is mapped at the region of 0x30000000. - * But this region is limited to 256MB. To accommodate NOR, promjet - * and FPGA. This region is divided as below: - * 0x30000000 - 0x37ffffff : 128MB : NOR flash - * 0x38000000 - 0x3BFFFFFF : 64MB : Promjet - * 0x3C000000 - 0x40000000 : 64MB : FPGA etc - * - * To accommodate bigger NOR flash and other devices, we will map IFC - * chip selects to as below: - * 0x5_1000_0000..0x5_1fff_ffff Memory Hole - * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB) - * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB - * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet) - * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet) - * - * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation. - * CONFIG_SYS_FLASH_BASE has the final address (core view) - * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view) - * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address - * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting - */ - -#define CONFIG_SYS_FLASH_BASE 0x580000000ULL -#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000 -#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 - -#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000 -#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000 - -#ifndef __ASSEMBLY__ -unsigned long long get_qixis_addr(void); -#endif -#define QIXIS_BASE get_qixis_addr() -#define QIXIS_BASE_PHYS 0x20000000 -#define QIXIS_BASE_PHYS_EARLY 0xC000000 -#define QIXIS_STAT_PRES1 0xb -#define QIXIS_SDID_MASK 0x07 -#define QIXIS_ESDHC_NO_ADAPTER 0x7 - -#define CONFIG_SYS_NAND_BASE 0x530000000ULL -#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000 - -/* MC firmware */ -/* TODO Actual DPL max length needs to be confirmed with the MC FW team */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -/* For LS2085A */ -#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000 -#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000 - -/* Define phy_reset function to boot the MC based on mcinitcmd. - * This happens late enough to properly fixup u-boot env MAC addresses. - */ -#define CONFIG_RESET_PHY_R - -/* - * Carve out a DDR region which will not be used by u-boot/Linux - * - * It will be used by MC and Debug Server. The MC region must be - * 512MB aligned, so the min size to hide is 512MB. - */ -#ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (128UL * 1024 * 1024) -#endif - -/* Command line configuration */ - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) - -/* Physical Memory Map */ -/* fixme: these need to be checked against the board */ -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581000000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "console=ttyAMA0,38400n8\0" \ - "mcinitcmd=fsl_mc start mc 0x580a00000" \ - " 0x580e00000 \0" - -#ifndef CONFIG_TFABOOT -#ifdef CONFIG_SD_BOOT -#define CONFIG_BOOTCOMMAND "mmc read 0x80200000 0x6800 0x800;"\ - " fsl_mc apply dpl 0x80200000 &&" \ - " mmc read $kernel_load $kernel_start" \ - " $kernel_size && bootm $kernel_load" -#else -#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \ - " cp.b $kernel_start $kernel_load" \ - " $kernel_size && bootm $kernel_load" -#endif -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SPL_MAX_SIZE 0x16000 -#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0) -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" - -#ifdef CONFIG_NAND_BOOT -#define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#endif -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#include - -#endif /* __LS2_COMMON_H */ diff --git a/include/configs/ls2080a_emu.h b/include/configs/ls2080a_emu.h deleted file mode 100644 index d5cb3e4..0000000 --- a/include/configs/ls2080a_emu.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor - */ - -#ifndef __LS2_EMU_H -#define __LS2_EMU_H - -#include "ls2080a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133333333 - -#define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR_EMU /* Support emulator */ -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD on I2C bus 1 */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 - -/* Debug Server firmware */ -#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL - -/* - * This trick allows users to load MC images into DDR directly without - * copying from NOR flash. It dramatically improves speed. - */ -#define CONFIG_SYS_LS_MC_FW_IN_DDR -#define CONFIG_SYS_LS_MC_DPL_IN_DDR -#define CONFIG_SYS_LS_MC_DPC_IN_DDR - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 - -/* Store environment at top of flash */ -#define CONFIG_ENV_SIZE 0x1000 - -#endif /* __LS2_EMU_H */ diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h deleted file mode 100644 index a526658..0000000 --- a/include/configs/ls2080a_simu.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Freescale Semiconductor - */ - -#ifndef __LS2_SIMU_H -#define __LS2_SIMU_H - -#include "ls2080a_common.h" - -#define CONFIG_SYS_CLK_FREQ 100000000 -#define CONFIG_DDR_CLK_FREQ 133333333 - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SMSC 91C111 ethernet configuration */ -#define CONFIG_SMC91111 -#define CONFIG_SMC91111_BASE (0x2210000) - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#endif - -/* - * NOR Flash Timing Params - */ -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \ - FTIM0_NOR_TEADC(0x1) | \ - FTIM0_NOR_TEAHC(0x1)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \ - FTIM1_NOR_TRAD_NOR(0x1)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \ - FTIM2_NOR_TCH(0x0) | \ - FTIM2_NOR_TWP(0x1)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -/* Debug Server firmware */ -#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580C00000ULL - -/* MC firmware */ -#define CONFIG_SYS_LS_MC_DPL_IN_NOR -#define CONFIG_SYS_LS_MC_DPL_ADDR 0x5806C0000ULL - -#define CONFIG_SYS_LS_MC_DPC_IN_NOR -#define CONFIG_SYS_LS_MC_DPC_ADDR 0x5806F8000ULL - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000 - -/* Store environment at top of flash */ -#define CONFIG_ENV_SIZE 0x1000 - -#endif /* __LS2_SIMU_H */ diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h deleted file mode 100644 index e2a8975..0000000 --- a/include/configs/ls2080aqds.h +++ /dev/null @@ -1,500 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017, 2019 NXP - * Copyright 2015 Freescale Semiconductor - */ - -#ifndef __LS2_QDS_H -#define __LS2_QDS_H - -#include "ls2080a_common.h" - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#ifdef CONFIG_FSL_QSPI -#define CONFIG_QIXIS_I2C_ACCESS -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C_EARLY_INIT -#endif -#define CONFIG_SYS_I2C_IFDR_DIV 0x7e -#endif - -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) - -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 -#define SPD_EEPROM_ADDRESS5 0x55 -#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x500000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) - -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR1_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1a) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} -#endif - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ - | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \ - | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \ - FTIM0_NAND_TWP(0x18) | \ - FTIM0_NAND_TWCHT(0x07) | \ - FTIM0_NAND_TWH(0x0a)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \ - FTIM1_NAND_TWBE(0x39) | \ - FTIM1_NAND_TRR(0x0e) | \ - FTIM1_NAND_TRP(0x18)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ - FTIM2_NAND_TREH(0x0a) | \ - FTIM2_NAND_TWHRE(0x1e)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) - -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_LBMAP_SWITCH 0x06 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_LBMAP_NAND 0x09 -#define QIXIS_LBMAP_SD 0x00 -#define QIXIS_LBMAP_QSPI 0x0f -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RCW_SRC_NAND 0x107 -#define QIXIS_RCW_SRC_SD 0x40 -#define QIXIS_RCW_SRC_QSPI 0x62 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) - -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#if defined(CONFIG_SPL) -#if defined(CONFIG_NAND_BOOT) -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK2_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#define CONFIG_ENV_OFFSET (896 * 1024) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 * 1024) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (640 * 1024) -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x20000 -#endif -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY -#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR -#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY -#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_TFABOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 -#endif -#endif - -/* Debug Server firmware */ -#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL - -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 - -/* - * I2C - */ -#define I2C_MUX_PCA_ADDR 0x77 -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 - -/* SPI */ -#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) -#ifdef CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_STMICRO -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SPI_FLASH_EON -#endif - -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SPI_FLASH_SPANSION -#define FSL_QSPI_FLASH_SIZE (1 << 26) /* 64MB */ -#define FSL_QSPI_FLASH_NUM 4 -#endif -/* - * Verify QSPI when boot from NAND, QIXIS brdcfg9 need configure. - * If boot from on-board NAND, ISO1 = 1, ISO2 = 0, IBOOT = 0 - * If boot from IFCCard NAND, ISO1 = 0, ISO2 = 0, IBOOT = 1 - */ -#define FSL_QIXIS_BRDCFG9_QSPI 0x1 - -#endif - -/* - * MMC - */ -#ifdef CONFIG_MMC -#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \ - QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER) -#endif - -/* - * RTC configuration - */ -#define RTC -#define CONFIG_RTC_DS3231 1 -#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_RTC_ENABLE_32KHZ_OUTPUT - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -#define CONFIG_FSL_MEMAC - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -/* Initial environment variables */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581000000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "mcmemsize=0x40000000\0" \ - "mcinitcmd=esbc_validate 0x580700000;" \ - "esbc_validate 0x580740000;" \ - "fsl_mc start mc 0x580a00000" \ - " 0x580e00000 \0" -#else -#ifdef CONFIG_TFABOOT -#define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ - "mmc read 0x80e00000 0x7000 0x800;" \ - "fsl_mc start mc 0x80a00000 0x80e00000\0" -#define IFC_MC_INIT_CMD \ - "fsl_mc start mc 0x580a00000" \ - " 0x580e00000 \0" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x80100000\0" \ - "loadaddr_sd=0x90100000\0" \ - "kernel_addr=0x581000000\0" \ - "kernel_addr_sd=0x8000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581000000\0" \ - "kernel_start_sd=0x8000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_size_sd=0x14000\0" \ - "load_addr=0xa0000000\0" \ - "kernelheader_addr=0x580800000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernelheader_size=0x40000\0" \ - "BOARD=ls2088aqds\0" \ - "mcmemsize=0x70000000 \0" \ - IFC_MC_INIT_CMD \ - "nor_bootcmd=echo Trying load from nor..;" \ - "cp.b $kernel_addr $load_addr " \ - "$kernel_size ; env exists secureboot && " \ - "cp.b $kernelheader_addr $kernelheader_addr_r " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - "bootm $load_addr#$BOARD\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "bootm $load_addr#$BOARD\0" -#elif defined(CONFIG_SD_BOOT) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x90100000\0" \ - "kernel_addr=0x800\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x8000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x14000\0" \ - "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ - "mcmemsize=0x70000000 \0" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "loadaddr=0x80100000\0" \ - "kernel_addr=0x100000\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_start=0x581000000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "mcmemsize=0x40000000\0" \ - "mcinitcmd=fsl_mc start mc 0x580a00000" \ - " 0x580e00000 \0" -#endif /* CONFIG_TFABOOT */ -#endif /* CONFIG_SECURE_BOOT */ - -#ifdef CONFIG_TFABOOT -#define SD_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ - "&& esbc_validate $load_addr; " \ - "env exists mcinitcmd && run mcinitcmd " \ - "&& mmc read 0x80d00000 0x6800 0x800 " \ - "&& fsl_mc lazyapply dpl 0x80d00000; " \ - "run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" - -#define IFC_NOR_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ - "&& fsl_mc lazyapply dpl 0x580d00000;" \ - "run nor_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#endif - -#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) -#define CONFIG_FSL_MEMAC -#define CONFIG_PHYLIB_10G -#define CONFIG_PHY_VITESSE -#define CONFIG_PHY_REALTEK -#define CONFIG_PHY_TERANETICS -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1d -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F - -#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0 -#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1 -#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2 -#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3 -#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4 -#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5 -#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6 -#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7 -#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8 -#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9 -#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa -#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb -#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc -#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd -#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe -#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf - -#define CONFIG_ETHPRIME "DPMAC1@xgmii" - -#endif - -#include - -#endif /* __LS2_QDS_H */ diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h deleted file mode 100644 index 2bf8217..0000000 --- a/include/configs/ls2080ardb.h +++ /dev/null @@ -1,604 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2017, 2019 NXP - * Copyright 2015 Freescale Semiconductor - */ - -#ifndef __LS2_RDB_H -#define __LS2_RDB_H - -#include "ls2080a_common.h" - -#ifdef CONFIG_FSL_QSPI -#ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_QIXIS_I2C_ACCESS -#endif -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C_EARLY_INIT -#endif -#endif - -#define I2C_MUX_CH_VOL_MONITOR 0xa -#define I2C_VOL_MONITOR_ADDR 0x38 -#define CONFIG_VOL_MONITOR_IR36021_READ -#define CONFIG_VOL_MONITOR_IR36021_SET - -#define CONFIG_VID_FLS_ENV "ls2080ardb_vdd_mv" -#ifndef CONFIG_SPL_BUILD -#define CONFIG_VID -#endif -/* step the IR regulator in 5mV increments */ -#define IR_VDD_STEP_DOWN 5 -#define IR_VDD_STEP_UP 5 -/* The lowest and highest voltage allowed for LS2080ARDB */ -#define VDD_MV_MIN 819 -#define VDD_MV_MAX 1212 - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ 133333333 -#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4) - -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 -#define SPD_EEPROM_ADDRESS5 0x55 -#define SPD_EEPROM_ADDRESS6 0x56 /* dummy address */ -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#ifdef CONFIG_SYS_FSL_HAS_DP_DDR -#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR 1 -#endif - -/* SATA */ -#define CONFIG_SCSI_AHCI_PLAT - -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_OFFSET 0x500000 /* 5MB */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_ENV_OFFSET) -#define CONFIG_ENV_SECT_SIZE 0x40000 -#endif - -#if !defined(CONFIG_FSL_QSPI) || defined(CONFIG_TFABOOT) - -#define CONFIG_SYS_NOR0_CSPR_EXT (0x0) -#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024) -#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024) - -#define CONFIG_SYS_NOR0_CSPR \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR0_CSPR_EARLY \ - (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \ - CSPR_PORT_SIZE_16 | \ - CSPR_MSEL_NOR | \ - CSPR_V) -#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12) -#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ - FTIM0_NOR_TEADC(0x5) | \ - FTIM0_NOR_TEAHC(0x5)) -#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \ - FTIM1_NOR_TRAD_NOR(0x1a) |\ - FTIM1_NOR_TSEQRAD_NOR(0x13)) -#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ - FTIM2_NOR_TCH(0x4) | \ - FTIM2_NOR_TWPH(0x0E) | \ - FTIM2_NOR_TWP(0x1c)) -#define CONFIG_SYS_NOR_FTIM3 0x04000000 -#define CONFIG_SYS_IFC_CCR 0x01000000 - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x40000000} -#endif - -#define CONFIG_NAND_FSL_IFC -#define CONFIG_SYS_NAND_MAX_ECCPOS 256 -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 - -#define CONFIG_SYS_NAND_CSPR_EXT (0x0) -#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \ - | CSPR_MSEL_NAND /* MSEL = NAND */ \ - | CSPR_V) -#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024) - -#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ - | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ - | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ - | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ - | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ - | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ - | CSOR_NAND_PB(128)) /* Pages Per Block 128*/ - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* ONFI NAND Flash mode0 Timing Params */ -#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x0e) | \ - FTIM0_NAND_TWP(0x30) | \ - FTIM0_NAND_TWCHT(0x0e) | \ - FTIM0_NAND_TWH(0x14)) -#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x64) | \ - FTIM1_NAND_TWBE(0xab) | \ - FTIM1_NAND_TRR(0x1c) | \ - FTIM1_NAND_TRP(0x30)) -#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x1e) | \ - FTIM2_NAND_TREH(0x14) | \ - FTIM2_NAND_TWHRE(0x3c)) -#define CONFIG_SYS_NAND_FTIM3 0x0 - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE - -#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_LBMAP_SWITCH 0x06 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SHIFT 0 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x04 -#define QIXIS_LBMAP_NAND 0x09 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_RCW_SRC_NAND 0x119 -#define QIXIS_RST_FORCE_MEM 0x01 - -#define CONFIG_SYS_CSPR3_EXT (0x0) -#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) -#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \ - | CSPR_PORT_SIZE_8 \ - | CSPR_MSEL_GPCM \ - | CSPR_V) - -#define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) -#define CONFIG_SYS_CSOR3 CSOR_GPCM_ADM_SHIFT(12) -/* QIXIS Timing parameters for IFC CS3 */ -#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ - FTIM0_GPCM_TEADC(0x0e) | \ - FTIM0_GPCM_TEAHC(0x0e)) -#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ - FTIM1_GPCM_TRAD(0x3f)) -#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ - FTIM2_GPCM_TCH(0xf) | \ - FTIM2_GPCM_TWP(0x3E)) -#define CONFIG_SYS_CS3_FTIM3 0x0 - -#if defined(CONFIG_SPL) && defined(CONFIG_NAND) -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR2_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#ifndef CONFIG_TFABOOT -#define CONFIG_ENV_OFFSET (2048 * 1024) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 -#endif -#define CONFIG_SPL_PAD_TO 0x80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (1024 * 1024) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 * 1024) -#else -#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT -#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY -#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR -#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK -#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR -#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 -#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 -#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 -#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 -#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT -#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR -#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK -#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR -#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0 -#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1 -#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2 -#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3 - -#ifndef CONFIG_TFABOOT -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000) -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE 0x2000 -#endif -#endif - -/* Debug Server firmware */ -#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR -#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL -#endif -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 - -#ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_FSL_QIXIS /* use common QIXIS code */ -#define QIXIS_QMAP_MASK 0x07 -#define QIXIS_QMAP_SHIFT 5 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0x62 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_RST_CTL_RESET_EN 0x30 -#endif - -/* - * I2C - */ -#ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 -#endif -#define I2C_MUX_PCA_ADDR 0x75 -#define I2C_MUX_PCA_ADDR_PRI 0x75 /* Primary Mux*/ - -/* I2C bus multiplexer */ -#define I2C_MUX_CH_DEFAULT 0x8 - -/* SPI */ -#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI) -#ifdef CONFIG_FSL_DSPI -#define CONFIG_SPI_FLASH_STMICRO -#endif -#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */ -#define FSL_QSPI_FLASH_NUM 2 -#endif - -/* - * RTC configuration - */ -#define RTC -#ifdef CONFIG_TARGET_LS2081ARDB -#define CONFIG_RTC_PCF8563 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 -#else -#define CONFIG_RTC_DS3231 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -#define CONFIG_FSL_MEMAC - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) \ - func(DHCP, dhcp, na) -#include - -#ifdef CONFIG_TFABOOT -#define QSPI_MC_INIT_CMD \ - "env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000;" \ - "fsl_mc start mc 0x20a00000 0x20e00000 \0" -#define SD_MC_INIT_CMD \ - "mmcinfo;mmc read 0x80a00000 0x5000 0x1200;" \ - "mmc read 0x80e00000 0x7000 0x800;" \ - "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x10 && " \ - "mmc read 0x80740000 0x3A00 0x10 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80a00000 0x80e00000\0" -#define IFC_MC_INIT_CMD \ - "env exists secureboot && " \ - "esbc_validate 0x580700000 && " \ - "esbc_validate 0x580740000; " \ - "fsl_mc start mc 0x580a00000 0x580e00000 \0" -#else -#ifdef CONFIG_QSPI_BOOT -#define MC_INIT_CMD \ - "mcinitcmd=env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000;" \ - "fsl_mc start mc 0x20a00000 0x20e00000 \0" -#elif defined(CONFIG_SD_BOOT) -#define MC_INIT_CMD \ - "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \ - "mmc read 0x80100000 0x7000 0x800;" \ - "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x10 && " \ - "mmc read 0x80740000 0x3A00 0x10 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80000000 0x80100000\0" \ - "mcmemsize=0x70000000\0" -#else -#define MC_INIT_CMD \ - "mcinitcmd=env exists secureboot && " \ - "esbc_validate 0x580700000 && " \ - "esbc_validate 0x580740000; " \ - "fsl_mc start mc 0x580a00000 0x580e00000 \0" -#endif -#endif - -/* Initial environment variables */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#ifdef CONFIG_TFABOOT -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x581000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernelheader_addr=0x580800000\0" \ - "kernel_addr_r=0x81000000\0" \ - "kernelheader_size=0x40000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "console=ttyAMA0,38400n8\0" \ - "mcmemsize=0x70000000\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "bootm $load_addr#$board\0" \ - QSPI_MC_INIT_CMD \ - BOOTENV \ - "boot_scripts=ls2088ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_start $kernel_size ; env exists secureboot &&" \ - "sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - " bootm $load_addr#$board\0" \ - "nor_bootcmd=echo Trying load from nor..;" \ - "cp.b $kernel_addr $load_addr " \ - "$kernel_size ; env exists secureboot && " \ - "cp.b $kernelheader_addr $kernelheader_addr_r " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - "bootm $load_addr#$board\0" -#else -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_addr=0x581000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x800000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernelheader_addr=0x580800000\0" \ - "kernel_addr_r=0x81000000\0" \ - "kernelheader_size=0x40000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "console=ttyAMA0,38400n8\0" \ - "mcmemsize=0x70000000\0" \ - "sd_bootcmd=echo Trying load from SD ..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "bootm $load_addr#$board\0" \ - MC_INIT_CMD \ - BOOTENV \ - "boot_scripts=ls2088ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls2088ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ - "env exists secureboot " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "qspi_bootcmd=echo Trying load from qspi..;" \ - "sf probe && sf read $load_addr " \ - "$kernel_start $kernel_size ; env exists secureboot &&" \ - "sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - " bootm $load_addr#$board\0" \ - "nor_bootcmd=echo Trying load from nor..;" \ - "cp.b $kernel_addr $load_addr " \ - "$kernel_size ; env exists secureboot && " \ - "cp.b $kernelheader_addr $kernelheader_addr_r " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - "bootm $load_addr#$board\0" -#endif - -#ifdef CONFIG_TFABOOT -#define QSPI_NOR_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ - "env exists mcinitcmd && " \ - "fsl_mc lazyapply dpl 0x20d00000; " \ - "run distro_bootcmd;run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;" - -/* Try to boot an on-SD kernel first, then do normal distro boot */ -#define SD_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ - "&& esbc_validate $load_addr; " \ - "env exists mcinitcmd && run mcinitcmd " \ - "&& mmc read 0x80d00000 0x6800 0x800 " \ - "&& fsl_mc lazyapply dpl 0x80d00000; " \ - "run distro_bootcmd;run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" - -/* Try to boot an on-NOR kernel first, then do normal distro boot */ -#define IFC_NOR_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ - "&& fsl_mc lazyapply dpl 0x580d00000;" \ - "run distro_bootcmd;run nor_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#else -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_QSPI_BOOT -/* Try to boot an on-QSPI kernel first, then do normal distro boot */ -#define CONFIG_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ - "env exists mcinitcmd && " \ - "fsl_mc lazyapply dpl 0x20d00000; " \ - "run distro_bootcmd;run qspi_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#elif defined(CONFIG_SD_BOOT) -/* Try to boot an on-SD kernel first, then do normal distro boot */ -#define CONFIG_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& mmcinfo && mmc read $load_addr 0x3c00 0x800 " \ - "&& esbc_validate $load_addr; " \ - "env exists mcinitcmd && run mcinitcmd " \ - "&& mmc read 0x88000000 0x6800 0x800 " \ - "&& fsl_mc lazyapply dpl 0x88000000; " \ - "run distro_bootcmd;run sd_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#else -/* Try to boot an on-NOR kernel first, then do normal distro boot */ -#define CONFIG_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x580780000; env exists mcinitcmd "\ - "&& fsl_mc lazyapply dpl 0x580d00000;" \ - "run distro_bootcmd;run nor_bootcmd; " \ - "env exists secureboot && esbc_halt;" -#endif -#endif - -/* MAC/PHY configuration */ -#ifdef CONFIG_FSL_MC_ENET -#define CONFIG_PHY_CORTINA -#define CONFIG_SYS_CORTINA_FW_IN_NOR -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_CORTINA_FW_ADDR 0x20980000 -#else -#define CONFIG_CORTINA_FW_ADDR 0x580980000 -#endif -#define CONFIG_CORTINA_FW_LENGTH 0x40000 - -#define CORTINA_PHY_ADDR1 0x10 -#define CORTINA_PHY_ADDR2 0x11 -#define CORTINA_PHY_ADDR3 0x12 -#define CORTINA_PHY_ADDR4 0x13 -#define AQ_PHY_ADDR1 0x00 -#define AQ_PHY_ADDR2 0x01 -#define AQ_PHY_ADDR3 0x02 -#define AQ_PHY_ADDR4 0x03 -#define AQR405_IRQ_MASK 0x36 - -#define CONFIG_ETHPRIME "DPMAC1@xgmii" -#endif - -#include - -#endif /* __LS2_RDB_H */ diff --git a/include/configs/lsxl.h b/include/configs/lsxl.h deleted file mode 100644 index 3ba5548..0000000 --- a/include/configs/lsxl.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2012 Michael Walle - * Michael Walle - */ - -#ifndef _CONFIG_LSXL_H -#define _CONFIG_LSXL_H - -/* - * Version number information - */ -#if defined(CONFIG_LSCHLV2) -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lschl.cfg -#define CONFIG_MACH_TYPE 3006 -#define CONFIG_SYS_TCLK 166666667 /* 166 MHz */ -#elif defined(CONFIG_LSXHL) -#define CONFIG_SYS_KWD_CONFIG $(CONFIG_BOARDDIR)/kwbimage-lsxhl.cfg -#define CONFIG_MACH_TYPE 2663 -/* CONFIG_SYS_TCLK is 200000000 by default */ -#else -#error "unknown board" -#endif - -/* - * General configuration options - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KW88F6281 /* SOC Name */ - -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -#define CONFIG_KIRKWOOD_GPIO - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* loading initramfs images without uimage header */ - -/* - * Environment variables configurations - */ -#ifdef CONFIG_SPI_FLASH -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 8 -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K */ -#endif - -#define CONFIG_ENV_SIZE 0x10000 /* 64k */ -#define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_LOADADDR 0x00800000 - -#if defined(CONFIG_LSXHL) -#define CONFIG_FDTFILE "kirkwood-lsxhl.dtb" -#elif defined(CONFIG_LSCHLV2) -#define CONFIG_FDTFILE "kirkwood-lschlv2.dtb" -#else -#error "Unsupported board" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootsource=legacy\0" \ - "hdpart=0:1\0" \ - "kernel_addr=0x00800000\0" \ - "ramdisk_addr=0x01000000\0" \ - "fdt_addr=0x00ff0000\0" \ - "bootcmd_legacy=sata init " \ - "&& load sata ${hdpart} ${kernel_addr} /uImage.buffalo "\ - "&& load sata ${hdpart} ${ramdisk_addr} /initrd.buffalo "\ - "&& bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "bootcmd_net=bootp ${kernel_addr} vmlinuz " \ - "&& tftpboot ${ramdisk_addr} initrd.img " \ - "&& setenv ramdisk_len ${filesize} " \ - "&& tftpboot ${fdt_addr} " CONFIG_FDTFILE " " \ - "&& bootz ${kernel_addr} " \ - "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ - "bootcmd_hdd=sata init " \ - "&& load sata ${hdpart} ${kernel_addr} /vmlinuz " \ - "&& load sata ${hdpart} ${ramdisk_addr} /initrd.img " \ - "&& setenv ramdisk_len ${filesize} " \ - "&& load sata ${hdpart} ${fdt_addr} /dtb " \ - "&& bootz ${kernel_addr} " \ - "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ - "bootcmd_usb=usb start " \ - "&& load usb 0:1 ${kernel_addr} /vmlinuz " \ - "&& load usb 0:1 ${ramdisk_addr} /initrd.img " \ - "&& setenv ramdisk_len ${filesize} " \ - "&& load usb 0:1 ${fdt_addr} " CONFIG_FDTFILE " " \ - "&& bootz ${kernel_addr} " \ - "${ramdisk_addr}:${ramdisk_len} ${fdt_addr}\0" \ - "bootcmd_rescue=run config_nc_dhcp; run nc\0" \ - "eraseenv=sf probe 0 " \ - "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \ - " +" __stringify(CONFIG_ENV_SIZE) "\0" \ - "config_nc_dhcp=setenv autoload_old ${autoload}; " \ - "setenv autoload no " \ - "&& bootp " \ - "&& setenv ncip " \ - "&& setenv autoload ${autoload_old}; " \ - "setenv autoload_old\0" \ - "standard_env=setenv ipaddr; setenv netmask; setenv serverip; " \ - "setenv ncip; setenv gatewayip; setenv ethact; " \ - "setenv bootfile; setenv dnsip; " \ - "setenv bootsource legacy; run ser\0" \ - "restore_env=run standard_env; saveenv; reset\0" \ - "ser=setenv stdin serial; setenv stdout serial; " \ - "setenv stderr serial\0" \ - "nc=setenv stdin nc; setenv stdout nc; setenv stderr nc\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {0, 1} /* enable port 1 only */ -#define CONFIG_PHY_BASE_ADR 7 -#undef CONFIG_RESET_PHY_R -#endif /* CONFIG_CMD_NET */ - -#ifdef CONFIG_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_SYS_64BIT_LBA -#define CONFIG_LBA48 -#endif - -#endif /* _CONFIG_LSXL_H */ diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h deleted file mode 100644 index 110d497..0000000 --- a/include/configs/lx2160a_common.h +++ /dev/null @@ -1,282 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __LX2_COMMON_H -#define __LX2_COMMON_H - -#include -#include -#include - -#define CONFIG_REMAKE_ELF -#define CONFIG_FSL_LAYERSCAPE -#define CONFIG_GICV3 -#define CONFIG_FSL_TZPC_BP147 -#define CONFIG_FSL_MEMAC - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_FLASH_BASE 0x20000000 - -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_BOARD_EARLY_INIT_F 1 - -/* DDR */ -#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */ -#define CONFIG_SYS_FSL_DDR_INTLV_256B /* force 256 byte interleaving */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 -#define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL -#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 2 -#define CONFIG_SYS_SDRAM_SIZE 0x200000000UL -#define CONFIG_DDR_SPD -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS1 0x51 -#define SPD_EEPROM_ADDRESS2 0x52 -#define SPD_EEPROM_ADDRESS3 0x53 -#define SPD_EEPROM_ADDRESS4 0x54 -#define SPD_EEPROM_ADDRESS5 0x55 -#define SPD_EEPROM_ADDRESS6 0x56 -#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 -#define CONFIG_FSL_DDR_BIST /* enable built-in memory test */ -#define CONFIG_SYS_MONITOR_LEN (936 * 1024) - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) - -/* SMP Definitinos */ -#define CPU_RELEASE_ADDR secondary_boot_func - -/* Generic Timer Definitions */ -/* - * This is not an accurate number. It is used in start.S. The frequency - * will be udpated later when get_bus_freq(0) is available. - */ - -#define COUNTER_FREQUENCY 25000000 /* 25MHz */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) - -/* Serial Port */ -#define CONFIG_PL01X_SERIAL -#define CONFIG_PL011_CLOCK (get_bus_freq(0) / 4) -#define CONFIG_SYS_SERIAL0 0x21c0000 -#define CONFIG_SYS_SERIAL1 0x21d0000 -#define CONFIG_SYS_SERIAL2 0x21e0000 -#define CONFIG_SYS_SERIAL3 0x21f0000 -/*below might needs to be removed*/ -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2, \ - (void *)CONFIG_SYS_SERIAL3 } -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* MC firmware */ -#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000 -#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000 -#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000 -#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000 - -/* Define phy_reset function to boot the MC based on mcinitcmd. - * This happens late enough to properly fixup u-boot env MAC addresses. - */ -#define CONFIG_RESET_PHY_R - -/* - * Carve out a DDR region which will not be used by u-boot/Linux - * - * It will be used by MC and Debug Server. The MC region must be - * 512MB aligned, so the min size to hide is 512MB. - */ -#ifdef CONFIG_FSL_MC_ENET -#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (256UL * 1024 * 1024) -#endif - -/* I2C bus multiplexer */ -#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ -#define I2C_MUX_CH_DEFAULT 0x8 - -/* RTC */ -#define RTC -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* Qixis */ -#define CONFIG_FSL_QIXIS -#define CONFIG_QIXIS_I2C_ACCESS -#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 - -/* PCI */ -#ifdef CONFIG_PCI -#define CONFIG_SYS_PCI_64BIT -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* MMC */ -#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 -#endif - -/* SATA */ - -#ifdef CONFIG_SCSI -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1 -#define CONFIG_SYS_SATA2 AHCI_BASE_ADDR2 -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) -#endif - -/* USB */ -#ifdef CONFIG_USB -#define CONFIG_HAS_FSL_XHCI_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -/* FlexSPI */ -#ifdef CONFIG_NXP_FSPI -#define NXP_FSPI_FLASH_SIZE SZ_64M -#define NXP_FSPI_FLASH_NUM 1 -#endif - -#ifndef __ASSEMBLY__ -unsigned long get_board_sys_clk(void); -unsigned long get_board_ddr_clk(void); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() -#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ / 4) - -#define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0x500000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_ENV_OFFSET) - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* Initial environment variables */ -#define XSPI_MC_INIT_CMD \ - "env exists secureboot && " \ - "esbc_validate 0x20700000 && " \ - "esbc_validate 0x20740000 ;" \ - "fsl_mc start mc 0x20a00000 0x20e00000\0" - -#define SD_MC_INIT_CMD \ - "mmc read 0x80a00000 0x5000 0x1200;" \ - "mmc read 0x80e00000 0x7000 0x800;" \ - "env exists secureboot && " \ - "mmc read 0x80700000 0x3800 0x10 && " \ - "mmc read 0x80740000 0x3A00 0x10 && " \ - "esbc_validate 0x80700000 && " \ - "esbc_validate 0x80740000 ;" \ - "fsl_mc start mc 0x80a00000 0x80e00000\0" - -#define EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "fdt_high=0xa0000000\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "fdt_addr=0x64f00000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x7C0000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "kernel_addr_r=0x81000000\0" \ - "kernelheader_size=0x40000\0" \ - "fdt_addr_r=0x90000000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernelhdr_addr_sd=0x3E00\0" \ - "kernel_size_sd=0x1d000\0" \ - "kernelhdr_size_sd=0x10\0" \ - "console=ttyAMA0,38400n8\0" \ - BOOTENV \ - "mcmemsize=0x70000000\0" \ - XSPI_MC_INIT_CMD \ - "boot_scripts=lx2160ardb_boot.scr\0" \ - "boot_script_hdr=hdr_lx2160ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" - -#define XSPI_NOR_BOOTCOMMAND \ - "env exists mcinitcmd && env exists secureboot "\ - "&& esbc_validate 0x20780000; " \ - "env exists mcinitcmd && " \ - "fsl_mc lazyapply dpl 0x20d00000; " \ - "run distro_bootcmd;run xspi_bootcmd; " \ - "env exists secureboot && esbc_halt;" - -#define SD_BOOTCOMMAND \ - "env exists mcinitcmd && mmcinfo; " \ - "mmc read 0x80d00000 0x6800 0x800; " \ - "env exists mcinitcmd && env exists secureboot " \ - " && mmc read 0x80780000 0x3C00 0x10 " \ - "&& esbc_validate 0x80780000;env exists mcinitcmd " \ - "&& fsl_mc lazyapply dpl 0x80d00000;" \ - "run distro_bootcmd;run sd_bootcmd;" \ - "env exists secureboot && esbc_halt;" - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(MMC, mmc, 0) \ - func(SCSI, scsi, 0) -#include - -#endif /* __LX2_COMMON_H */ diff --git a/include/configs/lx2160aqds.h b/include/configs/lx2160aqds.h deleted file mode 100644 index 662e601..0000000 --- a/include/configs/lx2160aqds.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018-2019 NXP - */ - -#ifndef __LX2_QDS_H -#define __LX2_QDS_H - -#include "lx2160a_common.h" - -/* Qixis */ -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_XMAP_SHIFT 5 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_RCW_SRC_SD 0x08 -#define NON_EXTENDED_DUTCFG -#define QIXIS_SDID_MASK 0x07 -#define QIXIS_ESDHC_NO_ADAPTER 0x7 - -/* SYSCLK */ -#define QIXIS_SYSCLK_100 0x0 -#define QIXIS_SYSCLK_125 0x1 -#define QIXIS_SYSCLK_133 0x2 - -/* DDRCLK */ -#define QIXIS_DDRCLK_100 0x0 -#define QIXIS_DDRCLK_125 0x1 -#define QIXIS_DDRCLK_133 0x2 - -#define BRDCFG4_EMI1SEL_MASK 0xF8 -#define BRDCFG4_EMI1SEL_SHIFT 3 -#define BRDCFG4_EMI2SEL_MASK 0x07 -#define BRDCFG4_EMI2SEL_SHIFT 0 - -/* VID */ - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 -#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv" -#define CONFIG_VID - -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 925 - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PWM_CHANNEL0 0x0 - -#define CONFIG_VOL_MONITOR_LTC3882_SET -#define CONFIG_VOL_MONITOR_LTC3882_READ - -/* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 0 -#define I2C_MUX_CH_RTC 0xB - -/* - * MMC - */ -#ifdef CONFIG_MMC -#ifndef __ASSEMBLY__ -u8 qixis_esdhc_detect_quirk(void); -#endif -#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk() -#endif - -/* MAC/PHY configuration */ -#if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_MII -#define CONFIG_ETHPRIME "DPMAC17@rgmii-id" - -#define AQ_PHY_ADDR1 0x00 -#define AQ_PHY_ADDR2 0x01 -#define AQ_PHY_ADDR3 0x02 -#define AQ_PHY_ADDR4 0x03 - -#define CORTINA_NO_FW_UPLOAD -#define CORTINA_PHY_ADDR1 0x0 - -#define INPHI_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR2 0x1 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F - -#endif - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXTRA_ENV_SETTINGS \ - "lx2160aqds_vdd_mv=800\0" \ - "BOARD=lx2160aqds\0" \ - "xspi_bootcmd=echo Trying load from flexspi..;" \ - "sf probe 0:0 && sf read $load_addr " \ - "$kernel_start $kernel_size ; env exists secureboot &&" \ - "sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - " bootm $load_addr#$BOARD\0" \ - "sd_bootcmd=echo Trying load from sd card..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd ;" \ - "env exists secureboot && mmc read $kernelheader_addr_r "\ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$BOARD\0" - -#include - -#endif /* __LX2_QDS_H */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h deleted file mode 100644 index c6bacb6..0000000 --- a/include/configs/lx2160ardb.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2018 NXP - */ - -#ifndef __LX2_RDB_H -#define __LX2_RDB_H - -#include "lx2160a_common.h" - -/* Qixis */ -#define QIXIS_XMAP_MASK 0x07 -#define QIXIS_XMAP_SHIFT 5 -#define QIXIS_RST_CTL_RESET_EN 0x30 -#define QIXIS_LBMAP_DFLTBANK 0x00 -#define QIXIS_LBMAP_ALTBANK 0x20 -#define QIXIS_LBMAP_QSPI 0x00 -#define QIXIS_RCW_SRC_QSPI 0xff -#define QIXIS_RST_CTL_RESET 0x31 -#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 -#define QIXIS_RCFG_CTL_RECONFIG_START 0x21 -#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 -#define QIXIS_LBMAP_MASK 0x0f -#define QIXIS_LBMAP_SD -#define QIXIS_RCW_SRC_SD 0x08 -#define NON_EXTENDED_DUTCFG - -/* VID */ - -#define I2C_MUX_CH_VOL_MONITOR 0xA -/* Voltage monitor on channel 2*/ -#define I2C_VOL_MONITOR_ADDR 0x63 -#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 -#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 -#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 -#define CONFIG_VID_FLS_ENV "lx2160ardb_vdd_mv" -#define CONFIG_VID - -/* The lowest and highest voltage allowed*/ -#define VDD_MV_MIN 775 -#define VDD_MV_MAX 855 - -/* PM Bus commands code for LTC3882*/ -#define PMBUS_CMD_PAGE 0x0 -#define PMBUS_CMD_READ_VOUT 0x8B -#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05 -#define PMBUS_CMD_VOUT_COMMAND 0x21 -#define PWM_CHANNEL0 0x0 - -#define CONFIG_VOL_MONITOR_LTC3882_SET -#define CONFIG_VOL_MONITOR_LTC3882_READ - -/* RTC */ -#define CONFIG_SYS_RTC_BUS_NUM 4 - -/* MAC/PHY configuration */ -#if defined(CONFIG_FSL_MC_ENET) -#define CONFIG_MII -#define CONFIG_ETHPRIME "DPMAC1@xgmii" - -#define AQR107_PHY_ADDR1 0x04 -#define AQR107_PHY_ADDR2 0x05 -#define AQR107_IRQ_MASK 0x0C - -#define CORTINA_NO_FW_UPLOAD -#define CORTINA_PHY_ADDR1 0x0 -#define INPHI_PHY_ADDR1 0x0 - -#define RGMII_PHY_ADDR1 0x01 -#define RGMII_PHY_ADDR2 0x02 - -#endif - -/* EMC2305 */ -#define I2C_MUX_CH_EMC2305 0x09 -#define I2C_EMC2305_ADDR 0x4D -#define I2C_EMC2305_CMD 0x40 -#define I2C_EMC2305_PWM 0x80 - -/* EEPROM */ -#define CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 - -/* Initial environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXTRA_ENV_SETTINGS \ - "lx2160ardb_vdd_mv=800\0" \ - "BOARD=lx2160ardb\0" \ - "xspi_bootcmd=echo Trying load from flexspi..;" \ - "sf probe 0:0 && sf read $load_addr " \ - "$kernel_start $kernel_size ; env exists secureboot &&" \ - "sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - " bootm $load_addr#$BOARD\0" \ - "sd_bootcmd=echo Trying load from sd card..;" \ - "mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd ;" \ - "env exists secureboot && mmc read $kernelheader_addr_r "\ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$BOARD\0" - -#include - -#endif /* __LX2_RDB_H */ diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h deleted file mode 100644 index 113e844..0000000 --- a/include/configs/m53menlo.h +++ /dev/null @@ -1,247 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -/* - * Menlosystems M53Menlo configuration - * Copyright (C) 2012-2017 Marek Vasut - * Copyright (C) 2014-2017 Olaf Mandel - */ - -#ifndef __M53MENLO_CONFIG_H__ -#define __M53MENLO_CONFIG_H__ - -#include - -#define CONFIG_REVISION_TAG -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Memory configurations - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) -#define PHYS_SDRAM_SIZE (gd->ram_size) -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x8ff00000 - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* - * Serial Driver - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 -#endif - -/* - * NAND - */ -#define CONFIG_ENV_SIZE (16 * 1024) -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_MXC_NAND_HWECC - -/* Environment is in NAND */ -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (4 * CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_OFFSET (8 * CONFIG_ENV_SECT_SIZE) /* 1 MiB */ -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) -#endif - -/* - * Ethernet on SOC (FEC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_MII -#define CONFIG_DISCOVER_PHY -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC0" -#endif - -/* - * I2C - */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_RTC_BUS_NUM 1 /* I2C2 */ -#endif - -/* - * RTC - */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 -#endif - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#endif - -/* - * SATA - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* - * LCD - */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASHIMAGE_GUARD -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) - -/* LVDS display */ -#define CONFIG_SYS_LDB_CLOCK 33260000 -#define CONFIG_IMX_VIDEO_SKIP -#define CONFIG_SPLASH_SOURCE - -/* IIM Fuses */ -#define CONFIG_FSL_IIM - -/* Watchdog */ - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTFILE "boot/fitImage" -#define CONFIG_LOADADDR 0x70800000 -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * NAND SPL - */ -#define CONFIG_SPL_TARGET "u-boot-with-nand-spl.imx" -#define CONFIG_SPL_PAD_TO 0x8000 -#define CONFIG_SPL_STACK 0x70004000 - -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 - -/* - * Extra Environments - */ -#define CONFIG_HOSTNAME "m53menlo" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttymxc0\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "rootpath=/srv/\0" \ - "kernel_addr_r=0x72000000\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "netdev=eth0\0" \ - "splashsource=mmc_fs\0" \ - "splashfile=boot/usplash.bmp.gz\0" \ - "splashimage=0x88000000\0" \ - "splashpos=m,m\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc addmtd\0" \ - "mmcload=" \ - "mmc rescan ; load mmc ${mmcdev}:${mmcpart} " \ - "${kernel_addr_r} ${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=/dev/mmcblk0p${mmcpart} rw " \ - "rootwait\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "netload=tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}${hostname},v3,tcp\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:1 ${bootscript} ; then " \ - "if load mmc 0:1 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" - -#if defined(CONFIG_SPL_BUILD) -#undef CONFIG_WATCHDOG -#define CONFIG_HW_WATCHDOG -#endif - -#endif /* __M53MENLO_CONFIG_H__ */ diff --git a/include/configs/malta.h b/include/configs/malta.h deleted file mode 100644 index f536234..0000000 --- a/include/configs/malta.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2013 Gabor Juhos - */ - -#ifndef _MALTA_CONFIG_H -#define _MALTA_CONFIG_H - -/* - * System configuration - */ -#define CONFIG_MALTA - -#define CONFIG_MEMSIZE_IN_BYTES - -#define CONFIG_PCI_GT64120 -#define CONFIG_PCI_MSC01 -#define CONFIG_PCNET -#define CONFIG_PCNET_79C973 -#define PCNET_HAS_PROM - -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 - -/* - * CPU Configuration - */ -#define CONFIG_SYS_MHZ 250 /* arbitrary value */ -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -/* - * Memory map - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#ifdef CONFIG_64BIT -# define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 -#else -# define CONFIG_SYS_SDRAM_BASE 0x80000000 -#endif -#define CONFIG_SYS_MEM_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x01000000) -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x00800000) - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - -/* - * Serial driver - */ -#define CONFIG_SYS_NS16550_PORT_MAPPED - -/* - * Flash configuration - */ -#ifdef CONFIG_64BIT -# define CONFIG_SYS_FLASH_BASE 0xffffffffbe000000 -#else -# define CONFIG_SYS_FLASH_BASE 0xbe000000 -#endif -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* - * Environment - */ -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE) - -/* - * IDE/ATA - */ -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 2 -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01f0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 - -/* - * Commands - */ - -#endif /* _MALTA_CONFIG_H */ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h deleted file mode 100644 index 9d5fbcd..0000000 --- a/include/configs/maxbcm.h +++ /dev/null @@ -1,79 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Stefan Roese - */ - -#ifndef _CONFIG_DB_MV7846MP_GP_H -#define _CONFIG_DB_MV7846MP_GP_H - -/* - * High Level Configuration Options (easy to change) - */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* - * Commands configuration - */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* SPI NOR flash default params, used by sf commands */ - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Memory layout while starting into the bin_hdr via the - * BootROM: - * - * 0x4000.4000 - 0x4003.4000 headers space (192KiB) - * 0x4000.4030 bin_hdr start address - * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) - * 0x4007.fffc BootROM stack top - * - * The address space between 0x4007.fffc and 0x400f.fff is not locked in - * L2 cache thus cannot be used. - */ - -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ - -/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ -#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ - -#endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h deleted file mode 100644 index 667dac7..0000000 --- a/include/configs/mccmon6.h +++ /dev/null @@ -1,282 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016-2017 - * Lukasz Majewski, DENX Software Engineering, lukma@denx.de - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#include "imx6_spl.h" - -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x80000) -#define CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_OS_BASE (CONFIG_SYS_FLASH_BASE + 0x180000) -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + 0x1980000) -#define CONFIG_SYS_FDT_SIZE (48 * SZ_1K) -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* - * Below defines are set but NOT really used since we by - * design force U-Boot run when we boot in development - * mode from SD card (SD2) - */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR (0x800) -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (0x80) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR (0x1000) -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "imx6q-mccmon.dtb" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* NOR 16-bit mode */ -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_FLASH_VERIFY - -/* NOR Flash MTD */ -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { (CONFIG_SYS_FLASH_BASE) } -#define CONFIG_SYS_FLASH_BANKS_SIZES { (32 * SZ_1M) } - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200 quiet\0" \ - "fdtfile=imx6q-mccmon6.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "boot_os=yes\0" \ - "disable_giga=yes\0" \ - "download_kernel=" \ - "tftpboot ${kernel_addr} ${kernel_file};" \ - "tftpboot ${fdt_addr} ${fdtfile};\0" \ - "get_boot_medium=" \ - "setenv boot_medium nor;" \ - "setexpr.l _src_sbmr1 *0x020d8004;" \ - "setexpr _b_medium ${_src_sbmr1} '&' 0x00000040;" \ - "if test ${_b_medium} = 40; then " \ - "setenv boot_medium sdcard;" \ - "fi\0" \ - "kernel_file=uImage\0" \ - "load_kernel=" \ - "load mmc ${bootdev}:${bootpart} ${kernel_addr} uImage;" \ - "load mmc ${bootdev}:${bootpart} ${fdt_addr} ${fdtfile};\0" \ - "boot_sd=" \ - "echo '#######################';" \ - "echo '# Factory SDcard Boot #';" \ - "echo '#######################';" \ - "setenv mmcdev 1;" \ - "setenv mmcfactorydev 0;" \ - "setenv mmcfactorypart 1;" \ - "run factory_flash_img;\0" \ - "boot_nor=" \ - "setenv kernelnor 0x08180000;" \ - "setenv dtbnor 0x09980000;" \ - "setenv bootargs console=${console} " \ - CONFIG_MTDPARTS_DEFAULT " " \ - "root=/dev/mmcblk1 rootfstype=ext4 rw rootwait noinitrd;" \ - "cp.l ${dtbnor} ${dtbloadaddr} 0x8000;" \ - "bootm ${kernelnor} - ${dtbloadaddr};\0" \ - "boot_recovery=" \ - "echo '#######################';" \ - "echo '# RECOVERY SWU Boot #';" \ - "echo '#######################';" \ - "setenv rootfsloadaddr 0x13000000;" \ - "setenv swukernelnor 0x08980000;" \ - "setenv swurootfsnor 0x09180000;" \ - "setenv swudtbnor 0x099A0000;" \ - "setenv bootargs console=${console} " \ - CONFIG_MTDPARTS_DEFAULT " " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}::off root=/dev/ram rw;" \ - "cp.l ${swurootfsnor} ${rootfsloadaddr} 0x200000;" \ - "cp.l ${swudtbnor} ${dtbloadaddr} 0x8000;" \ - "bootm ${swukernelnor} ${rootfsloadaddr} ${dtbloadaddr};\0" \ - "boot_tftp=" \ - "echo '#######################';" \ - "echo '# TFTP Boot #';" \ - "echo '#######################';" \ - "if run download_kernel; then " \ - "setenv bootargs console=${console} " \ - "root=/dev/mmcblk0p2 rootwait;" \ - "bootm ${kernel_addr} - ${fdt_addr};" \ - "fi\0" \ - "bootcmd=" \ - "if test -n ${recovery_status}; then " \ - "run boot_recovery;" \ - "else " \ - "if test ! -n ${boot_medium}; then " \ - "run get_boot_medium;" \ - "if test ${boot_medium} = sdcard; then " \ - "run boot_sd;" \ - "else " \ - "run boot_nor;" \ - "fi;" \ - "else " \ - "if test ${boot_medium} = tftp; then " \ - "run boot_tftp;" \ - "fi;" \ - "fi;" \ - "fi\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "fdt_addr=0x18000000\0" \ - "bootdev=1\0" \ - "bootpart=1\0" \ - "kernel_addr=" __stringify(CONFIG_LOADADDR) "\0" \ - "netdev=eth0\0" \ - "load_addr=0x11000000\0" \ - "dtbloadaddr=0x12000000\0" \ - "uboot_file=u-boot.img\0" \ - "SPL_file=SPL\0" \ - "load_uboot=tftp ${load_addr} ${uboot_file}\0" \ - "nor_img_addr=0x11000000\0" \ - "nor_img_file=core-image-lwn-mccmon6.nor\0" \ - "emmc_img_file=core-image-lwn-mccmon6.ext4\0" \ - "nor_bank_start=" __stringify(CONFIG_SYS_FLASH_BASE) "\0" \ - "nor_img_size=0x02000000\0" \ - "factory_script_file=factory.scr\0" \ - "factory_load_script=" \ - "if test -e mmc ${mmcdev}:${mmcfactorypart} " \ - "${factory_script_file}; then " \ - "load mmc ${mmcdev}:${mmcfactorypart} " \ - "${loadaddr} ${factory_script_file};" \ - "fi\0" \ - "factory_script=echo Running factory script from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "factory_flash_img="\ - "echo 'Flash mccmon6 with factory images'; " \ - "if run factory_load_script; then " \ - "run factory_script;" \ - "else " \ - "echo No factory script: ${factory_script_file} found on " \ - "device ${mmcdev};" \ - "run factory_nor_img;" \ - "run factory_eMMC_img;" \ - "fi\0" \ - "factory_eMMC_img="\ - "echo 'Update mccmon6 eMMC image'; " \ - "if load mmc ${mmcdev}:${mmcfactorypart} " \ - "${loadaddr} ${emmc_img_file}; then " \ - "setexpr fw_sz ${filesize} / 0x200;" \ - "setexpr fw_sz ${fw_sz} + 1;" \ - "mmc dev ${mmcfactorydev};" \ - "mmc write ${loadaddr} 0x0 ${fw_sz};" \ - "fi\0" \ - "factory_nor_img="\ - "echo 'Update mccmon6 NOR image'; " \ - "if load mmc ${mmcdev}:${mmcfactorypart} " \ - "${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "nor_update=" \ - "protect off ${nor_bank_start} +${nor_img_size};" \ - "erase ${nor_bank_start} +${nor_img_size};" \ - "setexpr nor_img_size ${nor_img_size} / 4; " \ - "cp.l ${nor_img_addr} ${nor_bank_start} ${nor_img_size}\0" \ - "tftp_nor_uboot="\ - "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \ - "setenv nor_img_file u-boot.img; " \ - "setenv nor_img_size 0x80000; " \ - "setenv nor_bank_start 0x08080000; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "tftp_nor_uImg="\ - "echo 'Update mccmon6 NOR uImage via TFTP'; " \ - "setenv nor_img_file uImage; " \ - "setenv nor_img_size 0x500000; " \ - "setenv nor_bank_start 0x08180000; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "tftp_nor_dtb="\ - "echo 'Update mccmon6 NOR DTB via TFTP'; " \ - "setenv nor_img_file imx6q-mccmon6.dtb; " \ - "setenv nor_img_size 0x20000; " \ - "setenv nor_bank_start 0x09980000; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "tftp_nor_img="\ - "echo 'Update mccmon6 NOR image via TFTP'; " \ - "if tftpboot ${nor_img_addr} ${nor_img_file}; then " \ - "run nor_update;" \ - "fi\0" \ - "tftp_nor_SPL="\ - "if tftp ${load_addr} SPL_padded; then " \ - "erase 0x08000000 +0x20000;" \ - "cp.b ${load_addr} 0x08000000 0x20000;" \ - "fi;\0" \ - "tftp_sd_SPL="\ - "if mmc dev 1; then " \ - "if tftp ${load_addr} ${SPL_file}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${load_addr} 0x2 ${fw_sz};" \ - "fi;" \ - "fi;\0" \ - "tftp_sd_uboot="\ - "if mmc dev 1; then " \ - "if run load_uboot; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${load_addr} 0x8A ${fw_sz};" \ - "fi;" \ - "fi;\0" - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (SZ_128K) - -/* Envs are stored in NOR flash */ -#define CONFIG_ENV_SECT_SIZE (SZ_128K) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x60000) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#endif /* __CONFIG_H * */ diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h deleted file mode 100644 index d212a7f..0000000 --- a/include/configs/medcom-wide.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* NAND support */ -#define CONFIG_TEGRA_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment in NAND, aligned to start of last sector */ -#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/meerkat96.h b/include/configs/meerkat96.h deleted file mode 100644 index d0450af..0000000 --- a/include/configs/meerkat96.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Linaro Ltd. - * Copyright (C) 2016 NXP Semiconductors - * - * Configuration settings for Meerkat96 board. - */ - -#ifndef __MEERKAT96_CONFIG_H -#define __MEERKAT96_CONFIG_H - -#include "mx7_common.h" -#include - -#define PHYS_SDRAM_SIZE SZ_512M - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment configs */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (8 * SZ_64K) - -/* USB configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - -#endif diff --git a/include/configs/meesc.h b/include/configs/meesc.h deleted file mode 100644 index 3a173a2..0000000 --- a/include/configs/meesc.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2009-2015 - * Daniel Gorsulowski - * esd electronic system design gmbh - * - * Configuation settings for the esd MEESC board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires - * adapting the initial boot program. - * Since the linker has to swallow that define, we must use a pure - * hex number here! - */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ - -/* Misc CPU related */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SERIAL_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ - -/* - * Hardware drivers - */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * SDRAM: 1 bank, min 32, max 128 MB - * Initialized before u-boot gets started. - */ -#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */ -#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000) - -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ -# define CONFIG_SYS_NAND_DBW_8 -# define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -# define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#undef CONFIG_RESET_PHY_R - -/* hw-controller addresses */ -#define CONFIG_ET1100_BASE 0x70000000 - -#ifdef CONFIG_SYS_USE_DATAFLASH - -/* bootstrap + u-boot + env in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 - -#elif CONFIG_SYS_USE_NANDFLASH - -/* bootstrap + u-boot + env + linux in nandflash */ -# define CONFIG_ENV_OFFSET 0xC0000 -# define CONFIG_ENV_SIZE 0x20000 - -#endif - -#define CONFIG_SYS_CBSIZE 512 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - 128*1024, 0x1000) - -#endif diff --git a/include/configs/meson64.h b/include/configs/meson64.h deleted file mode 100644 index f8d3eee..0000000 --- a/include/configs/meson64.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Amlogic Meson 64bits SoCs - * (C) Copyright 2016 Beniamino Galvani - */ - -#ifndef __MESON64_CONFIG_H -#define __MESON64_CONFIG_H - -/* Generic Interrupt Controller Definitions */ -#if defined(CONFIG_MESON_AXG) -#define GICD_BASE 0xffc01000 -#define GICC_BASE 0xffc02000 -#else /* MESON GXL and GXBB */ -#define GICD_BASE 0xc4301000 -#define GICC_BASE 0xc4302000 -#endif - -/* For splashscreen */ -#ifdef CONFIG_DM_VIDEO -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_BMP_16BPP -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define STDOUT_CFG "vidconsole,serial" -#else -#define STDOUT_CFG "serial" -#endif - -#ifdef CONFIG_USB_KEYBOARD -#define STDIN_CFG "usbkbd,serial" -#else -#define STDIN_CFG "serial" -#endif - -#define CONFIG_CPU_ARMV8 -#define CONFIG_REMAKE_ELF -#ifndef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x2000 -#endif -#define CONFIG_SYS_MAXARGS 32 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_INIT_SP_ADDR 0x20000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64 MiB */ - -/* ROM USB boot support, auto-execute boot.scr at scriptaddr */ -#define BOOTENV_DEV_ROMUSB(devtypeu, devtypel, instance) \ - "bootcmd_romusb=" \ - "if test \"${boot_source}\" = \"usb\" && " \ - "test -n \"${scriptaddr}\"; then " \ - "echo '(ROM USB boot)'; " \ - "source ${scriptaddr}; " \ - "fi\0" - -#define BOOTENV_DEV_NAME_ROMUSB(devtypeu, devtypel, instance) \ - "romusb " - -#ifdef CONFIG_CMD_USB -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_DEVICES_USB(func) -#endif - -#ifndef BOOT_TARGET_DEVICES -#define BOOT_TARGET_DEVICES(func) \ - func(ROMUSB, romusb, na) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ - BOOT_TARGET_DEVICES_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -#endif - -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "stdin=" STDIN_CFG "\0" \ - "stdout=" STDOUT_CFG "\0" \ - "stderr=" STDOUT_CFG "\0" \ - "fdt_addr_r=0x08008000\0" \ - "scriptaddr=0x08000000\0" \ - "kernel_addr_r=0x08080000\0" \ - "pxefile_addr_r=0x01080000\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - BOOTENV -#endif - -#include - -#endif /* __MESON64_CONFIG_H */ diff --git a/include/configs/meson64_android.h b/include/configs/meson64_android.h deleted file mode 100644 index 055fb44..0000000 --- a/include/configs/meson64_android.h +++ /dev/null @@ -1,136 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Android Amlogic Meson 64bits SoCs - * - * Copyright (C) 2019 Baylibre, SAS - * Author: Jerome Brunet - */ - -#ifndef __MESON64_ANDROID_CONFIG_H -#define __MESON64_ANDROID_CONFIG_H - -#define CONFIG_SYS_MMC_ENV_DEV 2 -#define CONFIG_SYS_MMC_ENV_PART 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_OFFSET (-0x10000) - - -#define BOOTENV_DEV_FASTBOOT(devtypeu, devtypel, instance) \ - "bootcmd_fastboot=" \ - "sm reboot_reason reason;" \ - "setenv run_fastboot 0;" \ - "if test \"${boot_source}\" = \"usb\"; then " \ - "echo Fastboot forced by usb rom boot;" \ - "setenv run_fastboot 1;" \ - "fi;" \ - "if gpt verify mmc ${mmcdev} ${partitions}; then; " \ - "else " \ - "echo Broken MMC partition scheme;" \ - "setenv run_fastboot 1;" \ - "fi;" \ - "if test \"${reason}\" = \"bootloader\" -o " \ - "\"${reason}\" = \"fastboot\"; then " \ - "echo Fastboot asked by reboot reason;" \ - "setenv run_fastboot 1;" \ - "fi;" \ - "if test \"${skip_fastboot}\" -eq 1; then " \ - "echo Fastboot skipped by environment;" \ - "setenv run_fastboot 0;" \ - "fi;" \ - "if test \"${force_fastboot}\" -eq 1; then " \ - "echo Fastboot forced by environment;" \ - "setenv run_fastboot 1;" \ - "fi;" \ - "if test \"${run_fastboot}\" -eq 1; then " \ - "echo Running Fastboot...;" \ - "fastboot 0;" \ - "fi\0" - -#define BOOTENV_DEV_NAME_FASTBOOT(devtypeu, devtypel, instance) \ - "fastboot " - -/* TOFIX: Run actual recovery instead of fastboot */ -#define BOOTENV_DEV_RECOVERY(devtypeu, devtypel, instance) \ - "bootcmd_recovery=" \ - "pinmux dev pinctrl@14;" \ - "pinmux dev pinctrl@40;" \ - "sm reboot_reason reason;" \ - "setenv run_recovery 0;" \ - "if run check_button; then " \ - "echo Recovery button is pressed;" \ - "setenv run_recovery 1;" \ - "elif test \"${reason}\" = \"recovery\" -o " \ - "\"${reason}\" = \"update\"; then " \ - "echo Recovery asked by reboot reason;" \ - "setenv run_recovery 1;" \ - "fi;" \ - "if test \"${skip_recovery}\" -eq 1; then " \ - "echo Recovery skipped by environment;" \ - "setenv run_recovery 0;" \ - "fi;" \ - "if test \"${force_recovery}\" -eq 1; then " \ - "echo Recovery forced by environment;" \ - "setenv run_recovery 1;" \ - "fi;" \ - "if test \"${run_recovery}\" -eq 1; then " \ - "echo Running Recovery...;" \ - "fastboot 0;" \ - "fi\0" - -#define BOOTENV_DEV_NAME_RECOVERY(devtypeu, devtypel, instance) \ - "recovery " - -#define BOOTENV_DEV_SYSTEM(devtypeu, devtypel, instance) \ - "bootcmd_system=" \ - "echo Loading Android boot partition...;" \ - "mmc dev ${mmcdev};" \ - "setenv bootargs ${bootargs} console=${console} androidboot.serialno=${serial#};" \ - "part start mmc ${mmcdev} ${bootpart} boot_start;" \ - "part size mmc ${mmcdev} ${bootpart} boot_size;" \ - "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \ - "echo Running Android...;" \ - "bootm ${loadaddr};" \ - "fi;" \ - "echo Failed to boot Android...;" \ - "reset\0" - -#define BOOTENV_DEV_NAME_SYSTEM(devtypeu, devtypel, instance) \ - "system " - -#define BOOT_TARGET_DEVICES(func) \ - func(FASTBOOT, fastboot, na) \ - func(RECOVERY, recovery, na) \ - func(SYSTEM, system, na) \ - -#define PREBOOT_LOAD_LOGO \ - "mmc dev ${mmcdev};" \ - "part start mmc ${mmcdev} ${logopart} boot_start;" \ - "part size mmc ${mmcdev} ${logopart} boot_size;" \ - "if mmc read ${loadaddr} ${boot_start} ${boot_size}; then " \ - "bmp display ${loadaddr} m m;" \ - "fi;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "partitions=" PARTS_DEFAULT "\0" \ - "mmcdev=2\0" \ - "bootpart=1\0" \ - "logopart=2\0" \ - "gpio_recovery=88\0" \ - "check_button=gpio input ${gpio_recovery};test $? -eq 0;\0" \ - "load_logo=" PREBOOT_LOAD_LOGO "\0" \ - "console=/dev/ttyAML0\0" \ - "bootargs=no_console_suspend\0" \ - "stdin=" STDIN_CFG "\0" \ - "stdout=" STDOUT_CFG "\0" \ - "stderr=" STDOUT_CFG "\0" \ - "loadaddr=0x01000000\0" \ - "fdt_addr_r=0x01000000\0" \ - "scriptaddr=0x08000000\0" \ - "kernel_addr_r=0x01080000\0" \ - "pxefile_addr_r=0x01080000\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "fdtfile=amlogic/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" BOOTENV - -#include - -#endif /* __MESON64_ANDROID_CONFIG_H */ diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h deleted file mode 100644 index f1d0def..0000000 --- a/include/configs/microblaze-generic.h +++ /dev/null @@ -1,198 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2010 Michal Simek - * - * Michal SIMEK - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "../board/xilinx/microblaze-generic/xparameters.h" - -/* MicroBlaze CPU */ -#define MICROBLAZE_V5 1 - -#define CONFIG_SYS_BOOTM_LEN (64 * 1024 * 1024) - -/* linear and spi flash memory */ -#ifdef XILINX_FLASH_START -#define FLASH -#undef SPIFLASH -#undef RAMENV /* hold environment in flash */ -#else -#undef FLASH -#undef SPIFLASH -#define RAMENV /* hold environment in RAM */ -#endif - -/* uart */ -/* The following table includes the supported baudrates */ -# define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -/* setting reset address */ -/*#define CONFIG_SYS_RESET_ADDRESS CONFIG_SYS_TEXT_BASE*/ - -#define CONFIG_SYS_MALLOC_LEN 0xC0000 - -/* Stack location before relocation */ -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_F_LEN) - -/* - * CFI flash memory layout - Example - * CONFIG_SYS_FLASH_BASE = 0x2200_0000; - * CONFIG_SYS_FLASH_SIZE = 0x0080_0000; 8MB - * - * SECT_SIZE = 0x20000; 128kB is one sector - * CONFIG_ENV_SIZE = SECT_SIZE; 128kB environment store - * - * 0x2200_0000 CONFIG_SYS_FLASH_BASE - * FREE 256kB - * 0x2204_0000 CONFIG_ENV_ADDR - * ENV_AREA 128kB - * 0x2206_0000 - * FREE - * 0x2280_0000 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - * - */ - -#ifdef FLASH -# define CONFIG_SYS_FLASH_BASE XILINX_FLASH_START -# define CONFIG_SYS_FLASH_SIZE XILINX_FLASH_SIZE -/* ?empty sector */ -# define CONFIG_SYS_FLASH_EMPTY_INFO 1 -/* max number of memory banks */ -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -/* max number of sectors on one chip */ -# define CONFIG_SYS_MAX_FLASH_SECT 512 -/* hardware flash protection */ -/* use buffered writes (20x faster) */ -# ifdef RAMENV -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - -# else /* FLASH && !RAMENV */ -/* 128K(one sector) for env */ -# define CONFIG_ENV_SECT_SIZE 0x20000 -# define CONFIG_ENV_ADDR \ - (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) -# define CONFIG_ENV_SIZE 0x20000 -# endif /* FLASH && !RAMBOOT */ -#else /* !FLASH */ - -#ifdef SPIFLASH -# ifdef RAMENV -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) - -# else /* SPIFLASH && !RAMENV */ -/* 128K(two sectors) for env */ -# define CONFIG_ENV_SECT_SIZE 0x10000 -# define CONFIG_ENV_SIZE (2 * CONFIG_ENV_SECT_SIZE) -/* Warning: adjust the offset in respect of other flash content and size */ -# define CONFIG_ENV_OFFSET (128 * CONFIG_ENV_SECT_SIZE) /* at 8MB */ -# endif /* SPIFLASH && !RAMBOOT */ -#else /* !SPIFLASH */ - -/* ENV in RAM */ -# define CONFIG_ENV_SIZE 0x1000 -# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SIZE) -#endif /* !SPIFLASH */ -#endif /* !FLASH */ - -#define XILINX_USE_ICACHE 1 -#define XILINX_USE_DCACHE 1 - -#if defined(XILINX_USE_ICACHE) -# define CONFIG_ICACHE -#else -# undef CONFIG_ICACHE -#endif - -#if defined(XILINX_USE_DCACHE) -# define CONFIG_DCACHE -#else -# undef CONFIG_DCACHE -#endif - -#ifndef XILINX_DCACHE_BYTE_SIZE -#define XILINX_DCACHE_BYTE_SIZE 32768 -#endif - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#if defined(CONFIG_MTD_PARTITIONS) -/* MTD partitions */ - -/* default mtd partition table */ -#endif - -/* size of console buffer */ -#define CONFIG_SYS_CBSIZE 512 -/* max number of command args */ -#define CONFIG_SYS_MAXARGS 15 -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0 - -#define CONFIG_HOSTNAME "microblaze-generic" -#define CONFIG_BOOTCOMMAND "base 0;tftp 11000000 image.img;bootm" - -/* architecture dependent code */ -#define CONFIG_SYS_USR_EXCEP /* user exception */ - -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS "unlock=yes\0" \ - "nor0=flash-0\0"\ - "mtdparts=mtdparts=flash-0:"\ - "256k(u-boot),256k(env),3m(kernel),"\ - "1m(romfs),1m(cramfs),-(jffs2)\0"\ - "nc=setenv stdout nc;"\ - "setenv stdin nc\0" \ - "serial=setenv stdout serial;"\ - "setenv stdin serial\0" -#endif - -#if defined(CONFIG_XILINX_AXIEMAC) -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 -#endif - -/* SPL part */ - -#ifdef CONFIG_SYS_FLASH_BASE -# define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_FLASH_BASE -#endif - -/* for booting directly linux */ - -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ - 0x40000) -#define CONFIG_SYS_FDT_SIZE (16 << 10) -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_TEXT_BASE + \ - 0x1000000) - -/* SP location before relocation, must use scratch RAM */ -/* BRAM start */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x0 -/* BRAM size - will be generated */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 - -# define CONFIG_SPL_STACK_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_MALLOC_F_LEN) - -/* Just for sure that there is a space for stack */ -#define CONFIG_SPL_STACK_SIZE 0x100 - -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_INIT_RAM_SIZE - \ - CONFIG_SYS_INIT_RAM_ADDR - \ - CONFIG_SYS_MALLOC_F_LEN - \ - CONFIG_SPL_STACK_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/microchip_mpfs_icicle.h b/include/configs/microchip_mpfs_icicle.h deleted file mode 100644 index 82c7fbb..0000000 --- a/include/configs/microchip_mpfs_icicle.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Microchip Technology Inc. - * Padmarao Begari - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * CPU and Board Configuration Options - */ -#define CONFIG_BOOTP_SEND_HOSTNAME - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* - * Print Buffer Size - */ -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* - * max number of command args - */ -#define CONFIG_SYS_MAXARGS 16 - -/* - * Boot Argument Buffer Size - */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * Size of malloc() pool - * 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough - */ -#define CONFIG_SYS_MALLOC_LEN (512 << 10) - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_0_SIZE 0x40000000 /* 1 GB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 - -/* Init Stack Pointer */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x200000) - -#define CONFIG_SYS_LOAD_ADDR 0x80000000 /* SDRAM */ - -/* - * memtest works on DRAM - */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) - -/* When we use RAM as ENV */ -#define CONFIG_ENV_SIZE 0x2000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h deleted file mode 100644 index d0fe582..0000000 --- a/include/configs/minnowmax.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Google, Inc - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ - "stdout=vidconsole,serial\0" \ - "stderr=vidconsole,serial\0" \ - "usb_pgood_delay=40\0" - -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x006ef000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/miqi_rk3288.h b/include/configs/miqi_rk3288.h deleted file mode 100644 index c9691a0..0000000 --- a/include/configs/miqi_rk3288.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h deleted file mode 100644 index 3ce4b70..0000000 --- a/include/configs/mpc8308_p1m.h +++ /dev/null @@ -1,319 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. - * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -/* - * On-board devices - * - * TSECs - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC2 - -#define CONFIG_SYS_GPIO1_PRELIM -/* GPIO Default input/output settings */ -#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 -/* - * Default GPIO values: - * LED#1 enabled; WLAN enabled; Both COM LED on (orange) - */ -#define CONFIG_SYS_GPIO1_DAT 0x08008C00 - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of two chips HY5PS12621BFP-C4 from HYNIX - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (6 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x27256222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x121048c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03600100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=3, AL=1 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT - -#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) -/* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) - -/* - * SJA1000 CAN controller on Local Bus - */ -#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 - - -/* - * CPLD on Local Bus - */ -#define CONFIG_SYS_CPLD_BASE 0xFBFF8000 - - -/* - * Serial Port - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2_NAME "eTSEC1" -#define TSEC1_PHY_ADDR 1 -#define TSEC2_PHY_ADDR 2 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS 0 -#define TSEC2_FLAGS 0 - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=${consoledev},${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs}\0" \ - "kernel_addr=FC0A0000\0" \ - "fdt_addr=FC2A0000\0" \ - "ramdisk_addr=FC2C0000\0" \ - "u-boot=mpc8308_p1m/u-boot.bin\0" \ - "kernel_addr_r=1000000\0" \ - "fdt_addr_r=C00000\0" \ - "hostname=mpc8308_p1m\0" \ - "bootfile=mpc8308_p1m/uImage\0" \ - "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ - "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} - ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${fdt_addr_r} ${fdtfile};" \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "bootcmd=run flash_self\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h deleted file mode 100644 index 5f67893..0000000 --- a/include/configs/mt7623.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Configuration for MediaTek MT7623 SoC - * - * Copyright (C) 2018 MediaTek Inc. - * Author: Weijie Gao - */ - -#ifndef __MT7623_H -#define __MT7623_H - -#include - -/* Miscellaneous configurable options */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG - -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - -/* Environment */ -#define CONFIG_ENV_SIZE SZ_4K -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Preloader -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) - -/* UBoot -> Kernel */ -#define CONFIG_LOADADDR 0x84000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* MMC */ -#define MMC_SUPPORTS_TUNING - -/* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* This is needed for kernel booting */ -#define FDT_HIGH "fdt_high=0xac000000\0" - -/* Extra environment variables */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - FDT_HIGH - -/* Ethernet */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.2 - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET 0x100000 - -#endif diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h deleted file mode 100644 index 741b6fb..0000000 --- a/include/configs/mt7629.h +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Configuration for MediaTek MT7629 SoC - * - * Copyright (C) 2018 MediaTek Inc. - * Author: Ryder Lee - */ - -#ifndef __MT7629_H -#define __MT7629_H - -#include - -/* Miscellaneous configurable options */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG - -#define CONFIG_SYS_MAXARGS 8 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_CBSIZE SZ_1K -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - -/* Environment */ -#define CONFIG_ENV_SIZE SZ_4K -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Defines for SPL */ -#define CONFIG_SPL_STACK 0x106000 -#define CONFIG_SPL_MAX_SIZE SZ_64K -#define CONFIG_SPL_MAX_FOOTPRINT SZ_64K -#define CONFIG_SPL_PAD_TO 0x10000 - -#define CONFIG_SPI_ADDR 0x30000000 -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) - -/* SPL -> Uboot */ -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) - -/* UBoot -> Kernel */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x40000000 -#define CONFIG_LOADADDR 0x42007f1c -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 - -/* Ethernet */ -#define CONFIG_IPADDR 192.168.1.1 -#define CONFIG_SERVERIP 192.168.1.2 - -#endif diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h deleted file mode 100644 index a041ddb..0000000 --- a/include/configs/mv-common.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -/* - * This file contains Marvell Board Specific common defincations. - * This file should be included in board config header file. - * - * It supports common definations for Kirkwood platform - * TBD: support for Orion5X platforms - */ - -#ifndef _MV_COMMON_H -#define _MV_COMMON_H - -/* - * High Level Configuration Options (easy to change) - */ - -/* - * Custom CONFIG_SYS_TEXT_BASE can be done in .h - */ - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE -#endif - -/* auto boot */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 * 4) /* 4MiB for malloc() */ - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* ====> Include platform Common Definitions */ -#include - -/* ====> Include driver Common Definitions */ -/* - * Common NAND configuration - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -#endif /* _MV_COMMON_H */ diff --git a/include/configs/mv-plug-common.h b/include/configs/mv-plug-common.h deleted file mode 100644 index 486650f..0000000 --- a/include/configs/mv-plug-common.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009-2015 - * Marvell Semiconductor - */ - -#ifndef _CONFIG_MARVELL_PLUG_H -#define _CONFIG_MARVELL_PLUG_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -#endif /* _CONFIG_MARVELL_PLUG_H */ diff --git a/include/configs/mvebu_armada-37xx.h b/include/configs/mvebu_armada-37xx.h deleted file mode 100644 index bc24903..0000000 --- a/include/configs/mvebu_armada-37xx.h +++ /dev/null @@ -1,108 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Stefan Roese - */ - -#ifndef _CONFIG_MVEBU_ARMADA_37XX_H -#define _CONFIG_MVEBU_ARMADA_37XX_H - -/* - * High Level Configuration Options (easy to change) - */ - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* auto boot */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400, 460800, 921600 } - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* End of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) - -/* - * I2C - */ -#define CONFIG_I2C_MV -#define CONFIG_SYS_I2C_SLAVE 0x0 - -/* - * SPI Flash configuration - */ - -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -/* - * Ethernet Driver configuration - */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_ARP_TIMEOUT 200 -#define CONFIG_NET_RETRY_COUNT 50 - -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - -/* USB ethernet */ - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(SCSI, scsi, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "scriptaddr=0x4d00000\0" \ - "pxefile_addr_r=0x4e00000\0" \ - "fdt_addr_r=0x4f00000\0" \ - "kernel_addr_r=0x5000000\0" \ - "ramdisk_addr_r=0x8000000\0" \ - BOOTENV - -#endif /* _CONFIG_MVEBU_ARMADA_37XX_H */ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h deleted file mode 100644 index 3be3683..0000000 --- a/include/configs/mvebu_armada-8k.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Stefan Roese - */ - -#ifndef _CONFIG_MVEBU_ARMADA_8K_H -#define _CONFIG_MVEBU_ARMADA_8K_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* auto boot */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400, 460800, 921600 } - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -/* End of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) - -#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -/* When runtime detection fails this is the default */ -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* - * Ethernet Driver configuration - */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_ARP_TIMEOUT 200 -#define CONFIG_NET_RETRY_COUNT 50 - -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - -/* USB ethernet */ - -/* - * SATA/SCSI/AHCI configuration - */ -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -/* - * PCI configuration - */ -#ifdef CONFIG_PCIE_DW_MVEBU -#define CONFIG_E1000 -#endif - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(SCSI, scsi, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "scriptaddr=0x4d00000\0" \ - "pxefile_addr_r=0x4e00000\0" \ - "fdt_addr_r=0x4f00000\0" \ - "kernel_addr_r=0x5000000\0" \ - "ramdisk_addr_r=0x8000000\0" \ - "fdtfile=marvell/" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - BOOTENV - -#endif /* _CONFIG_MVEBU_ARMADA_8K_H */ diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h deleted file mode 100644 index 330f020..0000000 --- a/include/configs/mx23_olinuxino.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut - */ -#ifndef __CONFIGS_MX23_OLINUXINO_H__ -#define __CONFIGS_MX23_OLINUXINO_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE 4105 - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_OVERWRITE - -/* Environment is in MMC */ -#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* Status LED */ - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Ethernet */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "console=ttyAMA0\0" \ - "fdt_file=imx23-olinuxino.dtb\0" \ - "fdt_addr=0x41000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "usb start; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${uimage}; " \ - "if test ${boot_fdt} = yes; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootm ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootm; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;" \ - "fi; " \ - "else " \ - "bootm; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_MX23_OLINUXINO_H__ */ diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h deleted file mode 100644 index da1d53c..0000000 --- a/include/configs/mx23evk.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale i.MX23 EVK board config - * - * Copyright (C) 2013 Otavio Salvador - * on behalf of O.S. Systems Software LTDA. - */ -#ifndef __CONFIGS_MX23EVK_H__ -#define __CONFIGS_MX23EVK_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX23EVK - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_OVERWRITE - -/* Environment is in MMC */ -#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Framebuffer support */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environments */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttyAMA0\0" \ - "fdt_file=imx23-evk.dtb\0" \ - "fdt_addr=0x41000000\0" \ - "boot_fdt=try\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else " \ - "echo ERR: Fail to boot from MMC; " \ - "fi; " \ - "fi; " \ - "else exit; fi" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_MX23EVK_H__ */ diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h deleted file mode 100644 index 6537e3a..0000000 --- a/include/configs/mx25pdk.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* High Level Configuration Options */ - -#define CONFIG_SYS_TEXT_BASE 0x81200000 -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_SYS_TIMER_RATE 32768 -#define CONFIG_SYS_TIMER_COUNTER \ - (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_MACH_TYPE MACH_TYPE_MX25_3DS - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -/* Physical Memory Map */ - -#define PHYS_SDRAM_1 0x80000000 -#define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IMX_RAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE IMX_RAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Memory Test */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE/2) -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - -/* Serial Info */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* No NOR flash present */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -/* U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x1f -#define CONFIG_ENV_OVERWRITE - -/* ESDHC driver */ -#define CONFIG_SYS_FSL_ESDHC_ADDR IMX_MMC_SDHC1_BASE -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/* PMIC Configs */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC34704 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x54 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ - -/* RTC */ -#define CONFIG_RTC_IMXDI - -/* Fuse API support */ -#define CONFIG_FSL_IIM -#define CONFIG_CMD_FUSE - -/* Ethernet Configs */ - - -#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */ -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "splashpos=m,m\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x82000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h deleted file mode 100644 index dd04580..0000000 --- a/include/configs/mx28evk.h +++ /dev/null @@ -1,251 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Freescale Semiconductor, Inc. - * Author: Fabio Estevam - * - * Based on m28evk.h: - * Copyright (C) 2011 Marek Vasut - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_MX28EVK_H__ -#define __CONFIGS_MX28EVK_H__ - -/* System configurations */ -#define CONFIG_MACH_TYPE MACH_TYPE_MX28EVK - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#ifndef CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE (16 * 1024) -#else -#define CONFIG_ENV_SIZE (4 * 1024) -#endif -#define CONFIG_ENV_OVERWRITE - -/* Environment is in MMC */ -#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* Environment is in NAND */ -#if defined(CONFIG_CMD_NAND) && defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_RANGE (512 * 1024) -#define CONFIG_ENV_OFFSET 0x300000 -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) -#endif - -/* Environment is in SPI flash */ -#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET 0x40000 /* 256K */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x1000 -#endif - -/* UBI and NAND partitioning */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_MDIO_BASE MXS_ENET0_BASE -#define CONFIG_MX28_FEC_MAC_IN_OCOTP -#endif - -/* RTC */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MXS -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT1 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Framebuffer support */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (512 << 10) -#endif - -/* Boot Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ubifs_file=filesystem.ubifs\0" \ - "update_nand_full_filename=u-boot.nand\0" \ - "update_nand_firmware_filename=u-boot.sb\0" \ - "update_nand_firmware_maxsz=0x100000\0" \ - "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ - "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ - "nand device 0 ; " \ - "nand info ; " \ - "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ - "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ - "update_nand_firmware_full=" /* Update FCB, DBBT and FW */ \ - "if tftp ${update_nand_full_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "nand scrub -y 0x0 ${filesize} ; " \ - "nand write.raw ${loadaddr} 0x0 ${fcb_sz} ; " \ - "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ - "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ - "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ - "fi\0" \ - "update_nand_firmware=" /* Update only firmware */ \ - "if tftp ${update_nand_firmware_filename} ; then " \ - "run update_nand_get_fcb_size ; " \ - "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ - "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ - "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ - "nand erase ${fcb_sz} ${fw_sz} ; " \ - "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ - "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ - "fi\0" \ - "update_nand_kernel=" /* Update kernel */ \ - "mtdparts default; " \ - "nand erase.part kernel; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "nand write ${loadaddr} kernel ${filesize}\0" \ - "update_nand_fdt=" /* Update fdt */ \ - "mtdparts default; " \ - "nand erase.part fdt; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${fdt_file}; " \ - "nand write ${loadaddr} fdt ${filesize}\0" \ - "update_nand_filesystem=" /* Update filesystem */ \ - "mtdparts default; " \ - "nand erase.part filesystem; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${ubifs_file}; " \ - "ubi part filesystem; " \ - "ubi create filesystem; " \ - "ubi write ${loadaddr} filesystem ${filesize}\0" \ - "nandargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "rootfstype=ubifs ubi.mtd=6 root=ubi0_0 ${mtdparts}\0" \ - "nandboot=" /* Boot from NAND */ \ - "mtdparts default; " \ - "run nandargs; " \ - "nand read ${loadaddr} kernel 0x00400000; " \ - "if test ${boot_fdt} = yes; then " \ - "nand read ${fdt_addr} fdt 0x00080000; " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = no; then " \ - "bootz; " \ - "else " \ - "echo \"ERROR: Set boot_fdt to yes or no.\"; " \ - "fi; " \ - "fi\0" \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console_fsl=ttyAM0\0" \ - "console_mainline=ttyAMA0\0" \ - "fdt_file=imx28-evk.dtb\0" \ - "fdt_addr=0x41000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw rootwait\0" \ - "mmcargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console_mainline},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi;" \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_MX28EVK_H__ */ diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h deleted file mode 100644 index 04e3b8f..0000000 --- a/include/configs/mx31pdk.h +++ /dev/null @@ -1,146 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Magnus Lilja - * - * (C) Copyright 2004 - * Texas Instruments. - * Richard Woodruff - * Kshitij Gupta - * - * Configuration settings for the Freescale i.MX31 PDK board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* High Level Configuration Options */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS - -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_SIZE 2048 - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 1 -#define CONFIG_FSL_PMIC_CS 2 -#define CONFIG_FSL_PMIC_CLK 1000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \ - "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bootcmd=run bootcmd_net\0" \ - "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ - "tftpboot 0x81000000 uImage-mx31; bootm\0" \ - "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ - "nand erase 0x0 0x40000; " \ - "nand write 0x81000000 0x0 0x40000\0" - -/* - * Miscellaneous configurable options - */ - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x80010000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x81000000 - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) - -/* - * environment organization - */ -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_OFFSET_REDUND 0x60000 -#define CONFIG_ENV_SIZE (128 * 1024) - -/* - * NAND driver - */ -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -/* NAND configuration for the NAND_SPL */ - -/* Start copying real U-Boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 -/* Load U-Boot to this address */ -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST - -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 - -/* Configuration of lowlevel_init.S (clocks and SDRAM) */ -#define CCM_CCMR_SETUP 0x074B0BF5 -#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ - PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ - PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ - PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) -#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ - PLL_MFN(12)) - -#define ESDMISC_MDDR_SETUP 0x00000004 -#define ESDMISC_MDDR_RESET_DL 0x0000000c -#define ESDCFG0_MDDR_SETUP 0x006ac73a - -#define ESDCTL_ROW_COL (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2)) -#define ESDCTL_SETTINGS (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \ - ESDCTL_DSIZ(2) | ESDCTL_BL(1)) -#define ESDCTL_PRECHARGE (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE) -#define ESDCTL_AUTOREFRESH (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH) -#define ESDCTL_LOADMODEREG (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG) -#define ESDCTL_RW ESDCTL_SETTINGS - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h deleted file mode 100644 index e153dfb..0000000 --- a/include/configs/mx35pdk.h +++ /dev/null @@ -1,225 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010, Stefano Babic - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Copyright (C) 2007, Guennadi Liakhovetski - * - * Configuration for the MX35pdk Freescale board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - - /* High Level Configuration Options */ -#define CONFIG_MX35 - -#define CONFIG_SYS_FSL_CLK - -/* Set TEXT at the beginning of the NOR flash */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* - * PMIC Configs - */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x08 -#define CONFIG_RTC_MC13XXX - -/* - * MFD MC9SDZ60 - */ -#define CONFIG_FSL_MC9SDZ60 -#define CONFIG_SYS_FSL_MC9SDZ60_I2C_ADDR 0x69 - -/* - * UART (console) - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * Command definition - */ - -#define CONFIG_NET_RETRY_COUNT 100 - - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -/* - * Ethernet on the debug board (SMC911) - */ -#define CONFIG_HAS_ETH1 -#define CONFIG_ETHPRIME - -/* - * Ethernet on SOC (FEC) - */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR + 0x10000) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE / 2) -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) - -#if defined(CONFIG_FSL_ENV_IN_NAND) - #define CONFIG_ENV_OFFSET (1024 * 1024) -#endif - -/* - * CFI FLASH driver setup - */ - -/* A non-standard buffered write algorithm */ -#define CONFIG_FLASH_SPANSION_S29WS_N - -/* - * NAND FLASH driver setup - */ -#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -/* EHCI driver */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_USB_EHCI_MXC -#define CONFIG_MXC_USB_PORT 0 -#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERFACE_DIFF_UNI | \ - MXC_EHCI_POWER_PINS_ENABLED | \ - MXC_EHCI_OC_PIN_ACTIVE_LOW) -#define CONFIG_MXC_USB_PORTSC (MXC_EHCI_UTMI_16BIT | MXC_EHCI_MODE_UTMI) - -/* mmc driver */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define CONFIG_HOSTNAME "mx35pdk" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth1\0" \ - "ethprime=smc911x\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "loadaddr=80800000\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +80000;" \ - "erase ${uboot_addr} +80000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h deleted file mode 100644 index fc498b2..0000000 --- a/include/configs/mx51evk.h +++ /dev/null @@ -1,189 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007, Guennadi Liakhovetski - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX51EVK Board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - - /* High Level Configuration Options */ - -#define CONFIG_SYS_FSL_CLK - -#include - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_MACH_TYPE MACH_TYPE_MX51_BABBAGE -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_FSL_IIM - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_SPI -#define CONFIG_POWER_FSL -#define CONFIG_FSL_PMIC_BUS 0 -#define CONFIG_FSL_PMIC_CS 0 -#define CONFIG_FSL_PMIC_CLK 2500000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX - -/* - * MMC Configs - * */ -#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - -/* - * Eth Configs - */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -/* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI -#define CONFIG_MXC_USB_FLAGS MXC_EHCI_POWER_PINS_ENABLED - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ETHPRIME "FEC0" - -#define CONFIG_LOADADDR 0x92000000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdt_file=imx51-babbage.dtb\0" \ - "fdt_addr=0x91000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo ERROR: Cannot load the DT; " \ - "exit; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x90010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 -#define CONFIG_SYS_MAIN_PWR_ON - -/*----------------------------------------------------------------------- - * environment organization - */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h deleted file mode 100644 index d25629f..0000000 --- a/include/configs/mx53ard.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX53ARD Freescale board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_MX53_ARD - -#include - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI -#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_MXC_NAND_HWECC - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - -/* Eth Configs */ -#define CONFIG_HAS_ETH1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ - -#define CONFIG_ETHPRIME "smc911x" - -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "uimage=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr=0x78000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${uimage}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define MX53ARD_CS1GCR1 (CSEN | DSZ(2)) -#define MX53ARD_CS1RCR1 (RCSN(2) | OEN (1) | RWSC(22)) -#define MX53ARD_CS1RCR2 RBEN(2) -#define MX53ARD_CS1WCR1 (WCSN(2) | WEN(2) | WBEN(2) | WWSC(22)) - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h deleted file mode 100644 index bbe0574..0000000 --- a/include/configs/mx53cx9020.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG - * Patrick Bruenn - * - * Configuration settings for Beckhoff CX9020. - * - * Based on Freescale's Linux i.MX mx53loco.h file: - * Copyright (C) 2010-2011 Freescale Semiconductor. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_REVISION_TAG - -#define CONFIG_MXC_UART_BASE UART2_BASE - -#define CONFIG_FPGA_COUNT 1 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - -/* bootz: zImage/initrd.img support */ - -/* Eth Configs */ -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_ETHPRIME "FEC0" -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -/* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ - -#define CONFIG_LOADADDR 0x70010000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr_r=0x71ff0000\0" \ - "pxefile_addr_r=0x73000000\0" \ - "ramdisk_addr_r=0x72000000\0" \ - "console=ttymxc1,115200\0" \ - "uenv=/boot/uEnv.txt\0" \ - "optargs=\0" \ - "cmdline=\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcrootfstype=ext4 rootwait fixrtc\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/mmcblk${mmcdev}p${mmcpart} ro " \ - "rootfstype=${mmcrootfstype} " \ - "${cmdline}\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadpxe=dhcp;setenv kernel_addr_r ${loadaddr};pxe get;pxe boot;\0" \ - "loadrd=load mmc ${bootpart} ${ramdisk_addr_r} ${bootdir}/${rdfile};" \ - "setenv rdsize ${filesize}\0" \ - "loadfdt=echo loading ${fdt_path} ...;" \ - "load mmc ${bootpart} ${fdt_addr_r} ${fdt_path}\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "echo Checking for: ${uenv} ...;" \ - "setenv bootpart ${mmcdev}:${mmcpart};" \ - "if test -e mmc ${bootpart} ${uenv}; then " \ - "load mmc ${bootpart} ${loadaddr} ${uenv};" \ - "env import -t ${loadaddr} ${filesize};" \ - "echo Loaded environment from ${uenv};" \ - "if test -n ${dtb}; then " \ - "setenv fdt_file ${dtb};" \ - "echo Using: dtb=${fdt_file} ...;" \ - "fi;" \ - "echo Checking for uname_r in ${uenv}...;" \ - "if test -n ${uname_r}; then " \ - "echo Running uname_boot ...;" \ - "run uname_boot;" \ - "fi;" \ - "fi;" \ - "fi;\0" \ - "uname_boot="\ - "setenv bootdir /boot; " \ - "setenv bootfile vmlinuz-${uname_r}; " \ - "setenv ccatfile /boot/ccat.rbf; " \ - "echo loading CCAT firmware from ${ccatfile}; " \ - "load mmc ${bootpart} ${loadaddr} ${ccatfile}; " \ - "fpga load 0 ${loadaddr} ${filesize}; " \ - "if test -e mmc ${bootpart} ${bootdir}/${bootfile}; then " \ - "echo loading ${bootdir}/${bootfile} ...; " \ - "run loadimage;" \ - "setenv fdt_path /boot/dtbs/${uname_r}/${fdt_file}; " \ - "if test -e mmc ${bootpart} ${fdt_path}; then " \ - "run loadfdt;" \ - "else " \ - "echo; echo unable to find ${fdt_file} ...;" \ - "echo booting legacy ...;"\ - "run mmcargs;" \ - "echo debug: [${bootargs}] ... ;" \ - "echo debug: [bootz ${loadaddr}] ... ;" \ - "bootz ${loadaddr}; " \ - "fi;" \ - "run mmcargs;" \ - "echo debug: [${bootargs}] ... ;" \ - "echo debug: [bootz ${loadaddr} - ${fdt_addr_r}];" \ - "bootz ${loadaddr} - ${fdt_addr_r}; " \ - "else " \ - "echo loading from dhcp ...; " \ - "run loadpxe; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "run mmcboot;" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) -#define PHYS_SDRAM_SIZE (gd->ram_size) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -/* Framebuffer and LCD */ -#define CONFIG_IMX_VIDEO_SKIP - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h deleted file mode 100644 index 17ff13d..0000000 --- a/include/configs/mx53evk.h +++ /dev/null @@ -1,126 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX53-EVK Freescale board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_MX53_EVK - -#include - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* PMIC Configs */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 8 -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_RTC_MC13XXX - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - -/* Eth Configs */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ - -#define CONFIG_ETHPRIME "FEC0" - -#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h deleted file mode 100644 index 65a5993..0000000 --- a/include/configs/mx53loco.h +++ /dev/null @@ -1,194 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu - * - * Configuration settings for Freescale MX53 low cost board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO - -#include - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_REVISION_TAG - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 - -/* Eth Configs */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -/* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_DIALOG_POWER -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ - - -#define CONFIG_ETHPRIME "FEC0" - -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdt_addr=0x71000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ - "mmcargs=setenv bootargs console=ttymxc0,${baudrate} root=${mmcroot}\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo ERROR: Cannot load the DT; " \ - "exit; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) -#define PHYS_SDRAM_SIZE (gd->ram_size) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment starts at 768k = 768 * 1024 = 786432 */ -#define CONFIG_ENV_OFFSET 786432 -/* - * Detect overlap between U-Boot image and environment area in build-time - * - * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.imx offset - * CONFIG_BOARD_SIZE_LIMIT = 768k - 1k = 767k = 785408 - * - * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so - * write the direct value here - */ -#define CONFIG_BOARD_SIZE_LIMIT 785408 -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#ifdef CONFIG_CMD_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 1 - #define CONFIG_DWC_AHSATA_PORT_ID 0 - #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_BASE_ADDR - #define CONFIG_LBA48 -#endif - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx53ppd.h b/include/configs/mx53ppd.h deleted file mode 100644 index 59988ef..0000000 --- a/include/configs/mx53ppd.h +++ /dev/null @@ -1,214 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * Jason Liu - * - * Configuration settings for Freescale MX53 low cost board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONSOLE_DEV "ttymxc0" - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_REVISION_TAG - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* Eth Configs */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -/* USB Configs */ -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_MCS7830 -#define CONFIG_USB_ETHER_SMSC95XX -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_SYS_I2C_RTC_ADDR 0x30 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_DIALOG_POWER -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 - -/* Command definition */ - -#define CONFIG_ETHPRIME "FEC0" - -#define CONFIG_LOADADDR 0x72000000 /* loadaddr env var */ - -#define PPD_CONFIG_NFS \ - "nfsserver=192.168.252.95\0" \ - "gatewayip=192.168.252.95\0" \ - "netmask=255.255.255.0\0" \ - "ipaddr=192.168.252.99\0" \ - "kernsize=0x2000\0" \ - "use_dhcp=0\0" \ - "nfsroot=/opt/springdale/rd\0" \ - "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ - "${kern_ipconf} nfsroot=${nfsserver}:${nfsroot},v3,tcp rw\0" \ - "choose_ip=if test $use_dhcp = 1; then setenv kern_ipconf ip=dhcp; " \ - "setenv getcmd dhcp; else setenv kern_ipconf " \ - "ip=${ipaddr}:${nfsserver}:${gatewayip}:${netmask}::eth0:off; " \ - "setenv getcmd tftp; fi\0" \ - "nfs=run choose_ip setargs bootargs_nfs; ${getcmd} ${loadaddr} " \ - "${nfsserver}:${image}; bootm ${loadaddr}\0" \ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - PPD_CONFIG_NFS \ - "image=/boot/fitImage\0" \ - "fdt_high=0xffffffff\0" \ - "dev=mmc\0" \ - "devnum=2\0" \ - "rootdev=mmcblk0p\0" \ - "quiet=quiet loglevel=0\0" \ - "console=" CONSOLE_DEV "\0" \ - "lvds=ldb\0" \ - "setargs=setenv bootargs ${lvds} jtag=on mem=2G " \ - "vt.global_cursor_default=0 bootcause=${bootcause} ${quiet} " \ - "console=${console} ${rtc_status}\0" \ - "bootargs_emmc=setenv bootargs root=/dev/${rootdev}${partnum} ro " \ - "rootwait ${bootargs}\0" \ - "doquiet=if ext2load ${dev} ${devnum}:5 0x7000A000 /boot/console; " \ - "then setenv quiet; fi\0" \ - "hasfirstboot=ext2load ${dev} ${devnum}:${partnum} 0x7000A000 " \ - "/boot/bootcause/firstboot\0" \ - "swappartitions=setexpr partnum 3 - ${partnum}\0" \ - "failbootcmd=" \ - "ppd_lcd_enable; " \ - "msg=\"Monitor failed to start. " \ - "Try again, or contact GE Service for support.\"; " \ - "echo $msg; " \ - "setenv stdout vga; " \ - "echo \"\n\n\n\n \" $msg; " \ - "setenv stdout serial; " \ - "mw.b 0x7000A000 0xbc; " \ - "mw.b 0x7000A001 0x00; " \ - "ext4write ${dev} ${devnum}:5 0x7000A000 /boot/failures 2\0" \ - "altbootcmd=" \ - "run doquiet; " \ - "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ - "run hasfirstboot || setenv partnum 0; " \ - "if test ${partnum} != 0; then " \ - "setenv bootcause REVERT; " \ - "run swappartitions loadimage doboot; " \ - "fi; " \ - "run failbootcmd\0" \ - "loadimage=" \ - "ext2load ${dev} ${devnum}:${partnum} ${loadaddr} ${image}\0" \ - "doboot=" \ - "echo Booting from ${dev}:${devnum}:${partnum} ...; " \ - "run setargs; " \ - "run bootargs_emmc; " \ - "bootm ${loadaddr}\0" \ - "tryboot=" \ - "setenv partnum 1; run hasfirstboot || setenv partnum 2; " \ - "run loadimage || run swappartitions && run loadimage || " \ - "setenv partnum 0 && echo MISSING IMAGE;" \ - "run doboot; " \ - "run failbootcmd\0" \ - "video-mode=" \ - "lcd:800x480-24@60,monitor=lcd\0" \ - -#define CONFIG_MMCBOOTCOMMAND \ - "if mmc dev ${devnum}; then " \ - "run doquiet; " \ - "run tryboot; " \ - "fi; " \ - -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAXARGS 48 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (gd->bd->bi_dram[0].size) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (gd->bd->bi_dram[1].size) -#define PHYS_SDRAM_SIZE (gd->ram_size) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* FLASH and environment organization */ -#define CONFIG_ENV_OFFSET (12 * 64 * 1024) -#define CONFIG_ENV_SIZE (10 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define CONFIG_CMD_FUSE -#define CONFIG_FSL_IIM - -#define CONFIG_SYS_I2C_SPEED 100000 - -/* I2C1 */ -#define CONFIG_SYS_NUM_I2C_BUSES 9 -#define CONFIG_SYS_I2C_MAX_HOPS 1 -#define CONFIG_SYS_I2C_BUSES { {0, {I2C_NULL_HOP} }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 0} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 3} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 4} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 5} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 6} } }, \ - {0, {{I2C_MUX_PCA9547, 0x70, 7} } }, \ - } - -#define CONFIG_BCH - -/* Backlight Control */ -#define CONFIG_IMX6_PWM_PER_CLK 66666000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h deleted file mode 100644 index e606ee8..0000000 --- a/include/configs/mx53smd.h +++ /dev/null @@ -1,121 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX53SMD Freescale board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_MX53_SMD - -#include - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_FSL_CLK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/* Eth Configs */ -#define CONFIG_HAS_ETH1 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1F - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition */ - -#define CONFIG_ETHPRIME "FEC0" - -#define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "mmcargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm\0" \ - "netargs=setenv bootargs console=ttymxc0,${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "dhcp ${uimage}; bootm\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x70010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_2 CSD1_BASE_ADDR -#define PHYS_SDRAM_2_SIZE (512 * 1024 * 1024) -#define PHYS_SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h deleted file mode 100644 index 07b1e06..0000000 --- a/include/configs/mx6_common.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef __MX6_COMMON_H -#define __MX6_COMMON_H - -#if (defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) -#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK -#else -#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE L2_PL310_BASE -#endif - -#endif -#define CONFIG_BOARD_POSTCLK_INIT -#define CONFIG_MXC_GPT_HCLK - -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - -#include -#include -#include - -#ifndef CONFIG_MX6 -#define CONFIG_MX6 -#endif - -#define CONFIG_SYS_FSL_CLK - -/* ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Boot options */ -#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6SLL) || \ - defined(CONFIG_MX6SX) || \ - defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) -#define CONFIG_LOADADDR 0x82000000 -#else -#define CONFIG_LOADADDR 0x12000000 -#endif -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 - -/* MMC */ - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#endif - -#endif diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h deleted file mode 100644 index 3cf2f1c..0000000 --- a/include/configs/mx6cuboxi.h +++ /dev/null @@ -1,137 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * Configuration settings for the SolidRun mx6 based boards - */ -#ifndef __MX6CUBOXI_CONFIG_H -#define __MX6CUBOXI_CONFIG_H - -#include "mx6_common.h" - -#include "imx6_spl.h" - -#define CONFIG_IMX_THERMAL - -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) -#define CONFIG_MXC_UART - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* SATA Configuration */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_PHY_ATHEROS - -/* Framebuffer */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -/* USB */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* Command definition */ - -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONSOLE_DEV "ttymxc0" -#define CONFIG_SYS_MMC_ENV_DEV 0 /* SDHC2 */ - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "som_rev=undefined\0" \ - "has_emmc=undefined\0" \ - "fdtfile=undefined\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_addr=0x18000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "ramdiskaddr=0x13000000\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_high=0xffffffff\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV ",115200\0" \ - "bootm_size=0x10000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "finduuid=part uuid mmc 0:1 uuid\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "findfdt="\ - "if test ${board_rev} = MX6Q; then " \ - "setenv fdtprefix imx6q; fi; " \ - "if test ${board_rev} = MX6DL; then " \ - "setenv fdtprefix imx6dl; fi; " \ - "if test ${som_rev} = V15; then " \ - "setenv fdtsuffix -som-v15; fi; " \ - "if test ${has_emmc} = yes; then " \ - "setenv emmcsuffix -emmc; fi; " \ - "if test ${board_name} = HUMMINGBOARD2 ; then " \ - "setenv fdtfile ${fdtprefix}-hummingboard2${emmcsuffix}${fdtsuffix}.dtb; fi; " \ - "if test ${board_name} = HUMMINGBOARD ; then " \ - "setenv fdtfile ${fdtprefix}-hummingboard${emmcsuffix}${fdtsuffix}.dtb; fi; " \ - "if test ${board_name} = CUBOXI ; then " \ - "setenv fdtfile ${fdtprefix}-cubox-i${emmcsuffix}${fdtsuffix}.dtb; fi; " \ - "if test ${fdtfile} = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; \0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(SATA, sata, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* CONFIG_SPL_BUILD */ - -/* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE) - -#endif /* __MX6CUBOXI_CONFIG_H */ diff --git a/include/configs/mx6memcal.h b/include/configs/mx6memcal.h deleted file mode 100644 index 58d5ebf..0000000 --- a/include/configs/mx6memcal.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2018 Freescale Semiconductor, Inc. - * - * Configuration settings for the virtual mx6memcal board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SPL */ - -#include "mx6_common.h" -#include "imx6_spl.h" - -#undef CONFIG_MMC -#undef CONFIG_SPL_MMC_SUPPORT -#undef CONFIG_GENERIC_MMC -#undef CONFIG_CMD_FUSE - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) - -#define CONFIG_MXC_UART -#ifdef CONFIG_SERIAL_CONSOLE_UART1 -#if defined(CONFIG_MX6SL) -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR -#else -#define CONFIG_MXC_UART_BASE UART1_BASE -#endif -#elif defined(CONFIG_SERIAL_CONSOLE_UART2) -#define CONFIG_MXC_UART_BASE UART2_BASE -#else -#error please define serial console (CONFIG_SERIAL_CONSOLE_UARTx) -#endif -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_MXC_USB_PORTSC PORT_PTS_UTMI - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h deleted file mode 100644 index 6e4e751..0000000 --- a/include/configs/mx6qarm2.h +++ /dev/null @@ -1,133 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q Armadillo2 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART4_BASE - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc3\0" \ - "fdt_file=imx6q-arm2.dtb\0" \ - "fdt_addr=0x18000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=1\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 1 - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h deleted file mode 100644 index 56b10d8..0000000 --- a/include/configs/mx6sabre_common.h +++ /dev/null @@ -1,200 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q SabreSD board. - */ - -#ifndef __MX6QSABRE_COMMON_CONFIG_H -#define __MX6QSABRE_COMMON_CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_IMX_THERMAL - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 - -#define CONFIG_PHY_ATHEROS - -#ifdef CONFIG_SUPPORT_EMMC_BOOT -#define EMMC_ENV \ - "emmcdev=2\0" \ - "update_emmc_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "if mmc dev ${emmcdev} 1; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" -#else -#define EMMC_ENV "" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdtfile=undefined\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ - "dfu_alt_info_spl=spl raw 0x400\0" \ - "dfu_alt_info_img=u-boot raw 0x10000\0" \ - "dfu_alt_info=spl raw 0x400\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - EMMC_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdtfile = undefined; then " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabresd.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt;" \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (768 * 1024) -#endif - -/* Framebuffer */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -#define CONFIG_USBD_HS - -#endif /* __MX6QSABRE_COMMON_CONFIG_H */ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h deleted file mode 100644 index e444930..0000000 --- a/include/configs/mx6sabreauto.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q SabreAuto board. - */ - -#ifndef __MX6SABREAUTO_CONFIG_H -#define __MX6SABREAUTO_CONFIG_H - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_MACH_TYPE 3529 -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } - -#include "mx6sabre_common.h" - -/* Falcon Mode */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ -#endif - -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR -#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024) -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#endif - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -#endif /* __MX6SABREAUTO_CONFIG_H */ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h deleted file mode 100644 index ec15375..0000000 --- a/include/configs/mx6sabresd.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q SabreSD board. - */ - -#ifndef __MX6SABRESD_CONFIG_H -#define __MX6SABRESD_CONFIG_H - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_MACH_TYPE 3980 -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONSOLE_DEV "ttymxc0" - -#include "mx6sabre_common.h" - -/* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ - -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC3 */ -#endif - -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19) -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Enabled USB controller number */ -#endif - -#endif /* __MX6SABRESD_CONFIG_H */ diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h deleted file mode 100644 index 5d649f6..0000000 --- a/include/configs/mx6slevk.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6SL EVK board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_MACH_TYPE MACH_TYPE_MX6SL_EVK - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PHY_SMSC - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sl-evk.dtb\0" \ - "fdt_addr=0x88000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=1\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc 1:2 uuid\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_512M) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE SZ_8K - -#if defined CONFIG_SPI_BOOT -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#else -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#endif - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SDHC2*/ -#endif - -#define CONFIG_IMX_THERMAL - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h deleted file mode 100644 index b96e631..0000000 --- a/include/configs/mx6sllevk.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013-2016 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6SL EVK board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "epdc_waveform=epdc_splash.bin\0" \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sll-evk.dtb\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=1\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "usb start; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_128M) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_2G - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_SYS_MMC_ENV_PART 0 /* user partition */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ - -#define CONFIG_ENV_OFFSET (12 * SZ_64K) - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ - -#define CONFIG_IMX_THERMAL - -#define CONFIG_IOMUX_LPSR - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h deleted file mode 100644 index c4d8a89..0000000 --- a/include/configs/mx6sxsabreauto.h +++ /dev/null @@ -1,162 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6SX Sabreauto board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sx-sabreauto.dtb\0" \ - "fdt_addr=0x88000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR - -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Network */ - -#define CONFIG_FEC_MXC - -#define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 - -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" - -#define CONFIG_PHY_ATHEROS - -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -#define CONFIG_IMX_THERMAL - -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_FSL_QSPI_AHB -#define FSL_QSPI_FLASH_SIZE SZ_32M -#define FSL_QSPI_FLASH_NUM 2 -#endif - -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#define CONFIG_ENV_SIZE SZ_8K - -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC3*/ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h deleted file mode 100644 index dc4181d..0000000 --- a/include/configs/mx6sxsabresd.h +++ /dev/null @@ -1,210 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6SX Sabresd board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI2 B flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000 - -#define UPDATE_M4_ENV \ - "m4image=m4_qspi.bin\0" \ - "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ - "update_m4_from_sd=" \ - "if sf probe 1:0; then " \ - "if run loadm4image; then " \ - "setexpr fw_sz ${filesize} + 0xffff; " \ - "setexpr fw_sz ${fw_sz} / 0x10000; " \ - "setexpr fw_sz ${fw_sz} * 0x10000; " \ - "sf erase 0x0 ${fw_sz}; " \ - "sf write ${loadaddr} 0x0 ${filesize}; " \ - "fi; " \ - "fi\0" \ - "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" -#else -#define UPDATE_M4_ENV "" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - UPDATE_M4_ENV \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sx-sdb.dtb\0" \ - "fdt_addr=0x88000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \ - "mmcdev=2\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc 2:2 uuid\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test test $board_rev = REVA ; then " \ - "setenv fdt_file imx6sx-sdb-reva.dtb; fi; " \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt; " \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR - -/* I2C Configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* Network */ -#define CONFIG_FEC_MXC - -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 - -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" - -#define CONFIG_PHY_ATHEROS - -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1) -#endif - -#define CONFIG_IMX_THERMAL - -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_FSL_QSPI_LE -#define CONFIG_SYS_FSL_QSPI_AHB -#ifdef CONFIG_MX6SX_SABRESD_REVA -#define FSL_QSPI_FLASH_SIZE SZ_16M -#else -#define FSL_QSPI_FLASH_SIZE SZ_32M -#endif -#define FSL_QSPI_FLASH_NUM 2 -#endif - -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MXS -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR -#endif -#endif - -#define CONFIG_ENV_OFFSET (14 * SZ_64K) -#define CONFIG_ENV_SIZE SZ_8K - -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h deleted file mode 100644 index 87f8869..0000000 --- a/include/configs/mx6ul_14x14_evk.h +++ /dev/null @@ -1,212 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. - */ -#ifndef __MX6UL_14X14_EVK_CONFIG_H -#define __MX6UL_14X14_EVK_CONFIG_H - -#include -#include -#include "mx6_common.h" -#include - -#define is_mx6ul_9x9_evk() CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) - -/* SPL options */ -#include "imx6_spl.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* MMC Configs */ -#ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_NAND_MXS -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#endif - -#endif - -/* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -#ifdef CONFIG_DM_GPIO -#define CONFIG_DM_74X164 -#endif - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdt_file = undefined; then " \ - "if test $board_name = EVK && test $board_rev = 9X9; then " \ - "setenv fdt_file imx6ul-9x9-evk.dtb; fi; " \ - "if test $board_name = EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ul-14x14-evk.dtb; fi; " \ - "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt;" \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ -#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ - -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_FSL_QSPI_AHB -#define FSL_QSPI_FLASH_NUM 1 -#define FSL_QSPI_FLASH_SIZE SZ_32M -#endif - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_FEC_ENET_DEV 1 - -#if (CONFIG_FEC_ENET_DEV == 0) -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x2 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "eth0" -#elif (CONFIG_FEC_ENET_DEV == 1) -#define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "eth1" -#endif -#endif - -#define CONFIG_IMX_THERMAL - -#ifndef CONFIG_SPL_BUILD -#if defined(CONFIG_DM_VIDEO) -#define CONFIG_VIDEO_MXS -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif -#endif - -#endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h deleted file mode 100644 index 3bcd0d3..0000000 --- a/include/configs/mx6ullevk.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6UL 14x14 EVK board. - */ -#ifndef __MX6ULLEVK_CONFIG_H -#define __MX6ULLEVK_CONFIG_H - - -#include -#include -#include "mx6_common.h" -#include - -#define PHYS_SDRAM_SIZE SZ_512M - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* MMC Configs */ -#ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* NAND pin conflicts with usdhc2 */ -#ifdef CONFIG_SYS_USE_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#endif -#endif - -/* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdt_file = undefined; then " \ - "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ - "if test $board_name = EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ - "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; " \ - "fi; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "run findfdt;" \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ -#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ -#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ - -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET (12 * SZ_64K) - -#define CONFIG_IMX_THERMAL - -#define CONFIG_IOMUX_LPSR - -#define CONFIG_SOFT_SPI - -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_FSL_QSPI_AHB -#define FSL_QSPI_FLASH_NUM 1 -#define FSL_QSPI_FLASH_SIZE SZ_32M -#endif - -#endif diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common.h deleted file mode 100644 index b6ded77..0000000 --- a/include/configs/mx7_common.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX7. - */ - -#ifndef __MX7_COMMON_H -#define __MX7_COMMON_H - -#include -#include -#include - -#ifndef CONFIG_MX7 -#define CONFIG_MX7 -#endif - -/* Timer settings */ -#define CONFIG_MXC_GPT_HCLK -#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ -#define COUNTER_FREQUENCY CONFIG_SC_TIMER_CLK -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - -/* Enable iomux-lpsr support */ -#define CONFIG_IOMUX_LPSR - -#define CONFIG_LOADADDR 0x80800000 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 32 - -/* UART */ -#define CONFIG_MXC_UART - -/* MMC */ - -#define CONFIG_ARMV7_SECURE_BASE 0x00900000 - -#define CONFIG_ARMV7_PSCI_1_0 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT -#endif - -/* - * If we have defined the OPTEE ram size and not OPTEE it means that we were - * launched by OPTEE, because of that we shall skip all the low level - * initialization since it was already done by ATF or OPTEE - */ -#if (CONFIG_OPTEE_TZDRAM_SIZE != 0) -#ifndef CONFIG_OPTEE -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif -#endif - -#endif diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h deleted file mode 100644 index e1f92da..0000000 --- a/include/configs/mx7dsabresd.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX7D SABRESD board. - */ - -#ifndef __MX7D_SABRESD_CONFIG_H -#define __MX7D_SABRESD_CONFIG_H - -#include "mx7_common.h" - -#define PHYS_SDRAM_SIZE SZ_1G - -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -/* Network */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_PHY_BROADCOM -/* ENET1 */ -#define IMX_FEC_BASE ENET_IPS_BASE_ADDR - -/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#ifdef CONFIG_IMX_BOOTAUX -/* Set to QSPI1 A flash at default */ -#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000 - -#define UPDATE_M4_ENV \ - "m4image=m4_qspi.bin\0" \ - "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \ - "update_m4_from_sd=" \ - "if sf probe 0:0; then " \ - "if run loadm4image; then " \ - "setexpr fw_sz ${filesize} + 0xffff; " \ - "setexpr fw_sz ${fw_sz} / 0x10000; " \ - "setexpr fw_sz ${fw_sz} * 0x10000; " \ - "sf erase 0x0 ${fw_sz}; " \ - "sf write ${loadaddr} 0x0 ${filesize}; " \ - "fi; " \ - "fi\0" \ - "m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0" -#else -#define UPDATE_M4_ENV "" -#endif - -#define CONFIG_MFG_ENV_SETTINGS \ - "mfgtool_args=setenv bootargs console=${console},${baudrate} " \ - "rdinit=/linuxrc " \ - "g_mass_storage.stall=0 g_mass_storage.removable=1 " \ - "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\ - "g_mass_storage.iSerialNumber=\"\" "\ - "clk_ignore_unused "\ - "\0" \ - "initrd_addr=0x83800000\0" \ - "initrd_high=0xffffffff\0" \ - "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \ - -#define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=image raw 0 0x800000;"\ - "u-boot raw 0 0x4000;"\ - "bootimg part 0 1;"\ - "rootfs part 0 2\0" \ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - UPDATE_M4_ENV \ - CONFIG_MFG_ENV_SETTINGS \ - CONFIG_DFU_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx7d-sdb.dtb\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_SIZE SZ_8K - -/* - * If want to use nand, define CONFIG_NAND_MXS and rework board - * to support nand, since emmc has pin conflicts with nand - */ -#ifdef CONFIG_NAND_MXS -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ -#endif - -#define CONFIG_ENV_OFFSET (12 * SZ_64K) -#ifdef CONFIG_NAND_MXS -#define CONFIG_SYS_FSL_USDHC_NUM 1 -#else -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#endif - -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ -#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ - -/* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) - -#define CONFIG_IMX_THERMAL - -#define CONFIG_USBD_HS - -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MXS -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#endif - -#ifdef CONFIG_FSL_QSPI -#define CONFIG_SYS_FSL_QSPI_AHB -#define FSL_QSPI_FLASH_NUM 1 -#define FSL_QSPI_FLASH_SIZE SZ_64M -#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR -#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h deleted file mode 100644 index 3b02362..0000000 --- a/include/configs/mx7ulp_evk.h +++ /dev/null @@ -1,163 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX7ULP EVK board. - */ - -#ifndef __MX7ULP_EVK_CONFIG_H -#define __MX7ULP_EVK_CONFIG_H - -#include -#include - -#define CONFIG_BOARD_POSTCLK_INIT -#define CONFIG_SYS_BOOTM_LEN 0x1000000 - -#define SRC_BASE_ADDR CMC1_RBASE -#define IRAM_BASE_ADDR OCRAM_0_BASE -#define IOMUXC_BASE_ADDR IOMUXC1_RBASE - -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ -#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_ENV_OFFSET (12 * SZ_64K) -#define CONFIG_ENV_SIZE SZ_8K - -/* Using ULP WDOG for reset */ -#define WDOG_BASE_ADDR WDG1_RBASE - -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */ - -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -/*#define CONFIG_REVISION_TAG*/ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - -#define CONFIG_BOARD_EARLY_INIT_F - -/* UART */ -#define LPUART_BASE LPUART4_RBASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "=> " -#define CONFIG_SYS_CBSIZE 512 - -#define CONFIG_SYS_MAXARGS 256 - -/* Physical Memory Map */ - -#define PHYS_SDRAM 0x60000000 -#define PHYS_SDRAM_SIZE SZ_1G -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM - -#define CONFIG_LOADADDR 0x60800000 - -#define CONFIG_SYS_MEMTEST_END 0x9E000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttyLP0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx7ulp-evk.dtb\0" \ - "fdt_addr=0x63000000\0" \ - "boot_fdt=try\0" \ - "earlycon=lpuart32,0x402D0010\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "usb start; "\ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi" - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE SZ_256K - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -#define CONFIG_CMD_CACHE -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h deleted file mode 100644 index e079f80..0000000 --- a/include/configs/mxs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* - * Copyright (C) 2013 Marek Vasut - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __CONFIGS_MXS_H__ -#define __CONFIGS_MXS_H__ - -/* - * Includes - */ - -#if defined(CONFIG_MX23) && defined(CONFIG_MX28) -#error Select either CONFIG_MX23 or CONFIG_MX28 , never both! -#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28) -#error Select one of CONFIG_MX23 or CONFIG_MX28 ! -#endif - -#include - -#if defined(CONFIG_MX23) -#include -#elif defined(CONFIG_MX28) -#include -#endif - -/* - * CPU specifics - */ - -/* Startup hooks */ - -/* SPL */ -#ifndef CONFIG_SPL_FRAMEWORK -#define CONFIG_SPL_NO_CPU_SUPPORT -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/mxs" -#endif - -/* Memory sizes */ -#define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ -#define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ -#define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ - -/* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 -#if defined(CONFIG_MX23) -#define CONFIG_SYS_INIT_RAM_SIZE (32 * 1024) -#elif defined(CONFIG_MX28) -#define CONFIG_SYS_INIT_RAM_SIZE (128 * 1024) -#endif - -/* Point initial SP in SRAM so SPL can use it too. */ -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * We need to sacrifice first 4 bytes of RAM here to avoid triggering some - * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot - * binary. In case there was more of this mess, 0x100 bytes are skipped. - * - * In case of a HAB boot, we cannot for some weird reason use the first 4KiB - * of DRAM when loading. Moreover, we use the first 4 KiB for IVT and CST - * blocks, thus U-Boot starts at offset +8 KiB of DRAM start. - * - * As for the SPL, we must avoid the first 4 KiB as well, but we load the - * IVT and CST to 0x8000, so we don't need to waste the subsequent 4 KiB. - */ - -/* U-Boot general configuration */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* Booting Linux */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -/* - * Drivers - */ -/* - * DUART Serial Driver. - * Conflicts with AUART driver which can be set by board. - */ -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } -/* Default baudrate can be overridden by board! */ - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_FEC_MXC -#ifndef CONFIG_ETHPRIME -#define CONFIG_ETHPRIME "FEC0" -#endif -#ifndef CONFIG_FEC_XCV_TYPE -#define CONFIG_FEC_XCV_TYPE RMII -#endif -#endif - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MXS -#endif - -/* NAND */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#endif - -/* OCOTP */ -#ifdef CONFIG_CMD_FUSE -#define CONFIG_MXS_OCOTP -#endif - -/* SPI */ -#ifdef CONFIG_CMD_SPI -#define CONFIG_SPI_HALF_DUPLEX -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MXS -#define CONFIG_EHCI_IS_TDI -#endif - -#endif /* __CONFIGS_MXS_H__ */ diff --git a/include/configs/nas220.h b/include/configs/nas220.h deleted file mode 100644 index bdfa42f..0000000 --- a/include/configs/nas220.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Evgeni Dobrev - * - * based on work from: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -#ifndef _CONFIG_NAS220_H -#define _CONFIG_NAS220_H - -/* - * Machine type ID - */ -#define CONFIG_MACH_TYPE MACH_TYPE_RD88F6192_NAS - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* #define CPU Core subversion */ -#define CONFIG_KW88F6192 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* power-on led, regulator, sata0, sata1 */ -#define NAS220_GE_OE_VAL_LOW ((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28)) -#define NAS220_GE_OE_VAL_HIGH (0) -#define NAS220_GE_OE_LOW (~((1 << 12)|(1 << 14)|(1 << 24)|(1 << 28))) -#define NAS220_GE_OE_HIGH (~(0)) - -/* PHY related */ -#define MV88E1116_LED_FCTRL_REG 10 -#define MV88E1116_CPRSP_CR3_REG 21 -#define MV88E1116_MAC_CTRL_REG 21 -#define MV88E1116_PGADR_REG 22 -#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) -#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x10000 -#endif - -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_OFFSET 0xa0000 - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs=console=ttyS0,115200\0" \ - "mtdparts=mtdparts=orion_nand:0xa0000@0x0(uboot),"\ - "0x010000@0xa0000(env),"\ - "0x500000@0xc0000(uimage),"\ - "0x1a40000@0x5c0000(rootfs)\0" \ - "mtdids=nand0=orion_nand\0"\ - "autostart=no\0"\ - "autoload=no\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 8 -#endif /* CONFIG_CMD_NET */ - -/* - * USB/EHCI - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_KIRKWOOD /* on Kirkwood platform */ -#define CONFIG_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - -/* - * File system - */ -#define CONFIG_JFFS2_NAND -#define CONFIG_JFFS2_LZO - -/* - * SATA - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif - -/* - * EFI partition - */ - -#define CONFIG_KIRKWOOD_GPIO - -#endif /* _CONFIG_NAS220_H */ - diff --git a/include/configs/netgear_cg3100d.h b/include/configs/netgear_cg3100d.h deleted file mode 100644 index e5a9601..0000000 --- a/include/configs/netgear_cg3100d.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h deleted file mode 100644 index 3baa17a..0000000 --- a/include/configs/netgear_dgnd3700v2.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h deleted file mode 100644 index 23c370b..0000000 --- a/include/configs/nitrogen6x.h +++ /dev/null @@ -1,168 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - * - * Configuration settings for the Boundary Devices Nitrogen6X - * and Freescale i.MX6Q Sabre Lite boards. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_MACH_TYPE 3769 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#define CONFIG_USBD_HS -#define CONFIG_NETCONSOLE - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_I2C_EDID - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* Framebuffer and LCD */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (6 * 1024 * 1024) -#define CONFIG_BMP_16BPP -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -#ifdef CONFIG_CMD_MMC -#define DISTRO_BOOT_DEV_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) -#else -#define DISTRO_BOOT_DEV_MMC(func) -#endif - -#ifdef CONFIG_CMD_SATA -#define DISTRO_BOOT_DEV_SATA(func) func(SATA, sata, 0) -#else -#define DISTRO_BOOT_DEV_SATA(func) -#endif - -#ifdef CONFIG_USB_STORAGE -#define DISTRO_BOOT_DEV_USB(func) func(USB, usb, 0) -#else -#define DISTRO_BOOT_DEV_USB(func) -#endif - -#ifdef CONFIG_CMD_PXE -#define DISTRO_BOOT_DEV_PXE(func) func(PXE, pxe, na) -#else -#define DISTRO_BOOT_DEV_PXE(func) -#endif - -#ifdef CONFIG_CMD_DHCP -#define DISTRO_BOOT_DEV_DHCP(func) func(DHCP, dhcp, na) -#else -#define DISTRO_BOOT_DEV_DHCP(func) -#endif - - -#if defined(CONFIG_SABRELITE) -#define FDTFILE "fdtfile=imx6q-sabrelite.dtb\0" -#else -/* FIXME: nitrogen6x covers multiple configs. Define fdtfile for each supported config. */ -#define FDTFILE -#endif - -#define BOOT_TARGET_DEVICES(func) \ - DISTRO_BOOT_DEV_MMC(func) \ - DISTRO_BOOT_DEV_SATA(func) \ - DISTRO_BOOT_DEV_USB(func) \ - DISTRO_BOOT_DEV_PXE(func) \ - DISTRO_BOOT_DEV_DHCP(func) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc1\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr_r=0x18000000\0" \ - FDTFILE \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "ramdiskaddr=0x13000000\0" \ - "ip_dyn=yes\0" \ - "usb_pgood_delay=2000\0" \ - BOOTENV - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x10010000 -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#endif - -/* - * PCI express - */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/nokia_rx51.h b/include/configs/nokia_rx51.h deleted file mode 100644 index fd755bb..0000000 --- a/include/configs/nokia_rx51.h +++ /dev/null @@ -1,321 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011-2012 - * Pali Rohár - * - * (C) Copyright 2010 - * Alistair Buxton - * - * Derived from Beagle Board code: - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * - * Configuration settings for the Nokia RX-51 aka N900. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_SYS_L2CACHE_OFF /* pretend there is no L2 CACHE */ - -#define CONFIG_MACH_TYPE MACH_TYPE_NOKIA_RX51 - -/* - * Nokia X-Loader loading secondary image to address 0x80400000 - * NOLO loading boot image to random place, so it doesn't really - * matter what we set this to. We have to copy u-boot to this address - */ - -#include /* get chip and board defs */ -#include -#include -#include - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_SKIP_LOWLEVEL_INIT /* X-Loader set everything up */ - -#define CONFIG_CMDLINE_TAG /* enable passing kernel command line string */ -#define CONFIG_INITRD_TAG /* enable passing initrd */ -#define CONFIG_REVISION_TAG /* enable passing revision tag*/ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - -/* - * Size of malloc() pool - */ -#define CONFIG_UBI_SIZE (512 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + CONFIG_UBI_SIZE + \ - (128 << 10)) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, 115200 } - -/* USB device configuration */ -#define CONFIG_USB_DEVICE -#define CONFIG_USBD_VENDORID 0x0421 -#define CONFIG_USBD_PRODUCTID 0x01c8 -#define CONFIG_USBD_MANUFACTURER "Nokia" -#define CONFIG_USBD_PRODUCT_NAME "N900" - -/* commands to include */ - -#define CONFIG_SYS_I2C - -/* - * TWL4030 - */ - -#define GPIO_SLIDE 71 - -/* - * Board ONENAND Info. - */ - -#define PART1_NAME "bootloader" -#define PART1_SIZE 128 -#define PART1_MULL 1024 -#define PART1_SUFF "k" -#define PART1_OFFS 0x00000000 -#define PART1_MASK 0x00000003 - -#define PART2_NAME "config" -#define PART2_SIZE 384 -#define PART2_MULL 1024 -#define PART2_SUFF "k" -#define PART2_OFFS 0x00020000 -#define PART2_MASK 0x00000000 - -#define PART3_NAME "log" -#define PART3_SIZE 256 -#define PART3_MULL 1024 -#define PART3_SUFF "k" -#define PART3_OFFS 0x00080000 -#define PART3_MASK 0x00000000 - -#define PART4_NAME "kernel" -#define PART4_SIZE 2 -#define PART4_MULL 1024*1024 -#define PART4_SUFF "m" -#define PART4_OFFS 0x000c0000 -#define PART4_MASK 0x00000000 - -#define PART5_NAME "initfs" -#define PART5_SIZE 2 -#define PART5_MULL 1024*1024 -#define PART5_SUFF "m" -#define PART5_OFFS 0x002c0000 -#define PART5_MASK 0x00000000 - -#define PART6_NAME "rootfs" -#define PART6_SIZE 257280 -#define PART6_MULL 1024 -#define PART6_SUFF "k" -#define PART6_OFFS 0x004c0000 -#define PART6_MASK 0x00000000 - -#ifdef ONENAND_SUPPORT - -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#endif - -/* Watchdog support */ -#define CONFIG_HW_WATCHDOG - -/* - * Framebuffer - */ -/* Video console */ -#define CONFIG_VIDEO_LOGO -#define VIDEO_FB_16BPP_PIXEL_SWAP -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_SPLASH_SCREEN - -/* functions for cfb_console */ -#define VIDEO_KBD_INIT_FCT rx51_kp_init() -#define VIDEO_TSTC_FCT rx51_kp_tstc -#define VIDEO_GETC_FCT rx51_kp_getc -#ifndef __ASSEMBLY__ -struct stdio_dev; -int rx51_kp_init(void); -int rx51_kp_tstc(struct stdio_dev *sdev); -int rx51_kp_getc(struct stdio_dev *sdev); -#endif - -/* Environment information */ -#ifdef CONFIG_MTDPARTS_DEFAULT -#define MTDPARTS "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define MTDPARTS -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - MTDPARTS \ - "usbtty=cdc_acm\0" \ - "stdin=vga\0" \ - "stdout=vga\0" \ - "stderr=vga\0" \ - "setcon=setenv stdin ${con};" \ - "setenv stdout ${con};" \ - "setenv stderr ${con}\0" \ - "sercon=setenv con serial; run setcon\0" \ - "usbcon=setenv con usbtty; run setcon\0" \ - "vgacon=setenv con vga; run setcon\0" \ - "slide=gpio input " __stringify(GPIO_SLIDE) "\0" \ - "switchmmc=mmc dev ${mmcnum}\0" \ - "kernaddr=0x82008000\0" \ - "initrdaddr=0x84008000\0" \ - "scriptaddr=0x86008000\0" \ - "fileload=${mmctype}load mmc ${mmcnum}:${mmcpart} " \ - "${loadaddr} ${mmcfile}\0" \ - "kernload=setenv loadaddr ${kernaddr};" \ - "setenv mmcfile ${mmckernfile};" \ - "run fileload\0" \ - "initrdload=setenv loadaddr ${initrdaddr};" \ - "setenv mmcfile ${mmcinitrdfile};" \ - "run fileload\0" \ - "scriptload=setenv loadaddr ${scriptaddr};" \ - "setenv mmcfile ${mmcscriptfile};" \ - "run fileload\0" \ - "scriptboot=echo Running ${mmcscriptfile} from mmc " \ - "${mmcnum}:${mmcpart} ...; source ${scriptaddr}\0" \ - "kernboot=echo Booting ${mmckernfile} from mmc " \ - "${mmcnum}:${mmcpart} ...; bootm ${kernaddr}\0" \ - "kerninitrdboot=echo Booting ${mmckernfile} ${mmcinitrdfile} from mmc "\ - "${mmcnum}:${mmcpart} ...; bootm ${kernaddr} ${initrdaddr}\0" \ - "attachboot=echo Booting attached kernel image ...;" \ - "setenv setup_omap_atag 1;" \ - "bootm ${attkernaddr};" \ - "setenv setup_omap_atag\0" \ - "trymmcscriptboot=if run switchmmc; then " \ - "if run scriptload; then " \ - "run scriptboot;" \ - "fi;" \ - "fi\0" \ - "trymmckernboot=if run switchmmc; then " \ - "if run kernload; then " \ - "run kernboot;" \ - "fi;" \ - "fi\0" \ - "trymmckerninitrdboot=if run switchmmc; then " \ - "if run initrdload; then " \ - "if run kernload; then " \ - "run kerninitrdboot;" \ - "fi;" \ - "fi; " \ - "fi\0" \ - "trymmcpartboot=setenv mmcscriptfile boot.scr; run trymmcscriptboot;" \ - "setenv mmckernfile uImage; run trymmckernboot\0" \ - "trymmcallpartboot=setenv mmcpart 1; run trymmcpartboot;" \ - "setenv mmcpart 2; run trymmcpartboot;" \ - "setenv mmcpart 3; run trymmcpartboot;" \ - "setenv mmcpart 4; run trymmcpartboot\0" \ - "trymmcboot=if run switchmmc; then " \ - "setenv mmctype fat;" \ - "run trymmcallpartboot;" \ - "setenv mmctype ext2;" \ - "run trymmcallpartboot;" \ - "setenv mmctype ext4;" \ - "run trymmcallpartboot;" \ - "fi\0" \ - "emmcboot=setenv mmcnum 1; run trymmcboot\0" \ - "sdboot=setenv mmcnum 0; run trymmcboot\0" \ - "menucmd=bootmenu\0" \ - "bootmenu_0=Attached kernel=run attachboot\0" \ - "bootmenu_1=Internal eMMC=run emmcboot\0" \ - "bootmenu_2=External SD card=run sdboot\0" \ - "bootmenu_3=U-Boot boot order=boot\0" \ - "bootmenu_delay=30\0" \ - "" - -#define CONFIG_POSTBOOTMENU \ - "echo;" \ - "echo Extra commands:;" \ - "echo run sercon - Use serial port for control.;" \ - "echo run usbcon - Use usbtty for control.;" \ - "echo run vgacon - Use framebuffer/keyboard.;" \ - "echo run sdboot - Boot from SD card slot.;" \ - "echo run emmcboot - Boot internal eMMC memory.;" \ - "echo run attachboot - Boot attached kernel image.;" \ - "echo" - -#define CONFIG_BOOTCOMMAND \ - "run sdboot;" \ - "run emmcboot;" \ - "run attachboot;" \ - "echo" - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + 0x01F00000)/*31MB*/ - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 - -/* - * FLASH and environment organization - */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * Attached kernel image - */ - -#define SDRAM_SIZE 0x10000000 /* 256 MB */ -#define SDRAM_END (CONFIG_SYS_SDRAM_BASE + SDRAM_SIZE) - -#define IMAGE_MAXSIZE 0x1FF800 /* 2 MB - 2 kB */ -#define KERNEL_OFFSET 0x40000 /* 256 kB */ -#define KERNEL_MAXSIZE (IMAGE_MAXSIZE-KERNEL_OFFSET) -#define KERNEL_ADDRESS (SDRAM_END-KERNEL_MAXSIZE) - -/* Reserve protected RAM for attached kernel */ -#define CONFIG_PRAM ((KERNEL_MAXSIZE >> 10)+1) - -#endif /* __CONFIG_H */ diff --git a/include/configs/novena.h b/include/configs/novena.h deleted file mode 100644 index cdc437c..0000000 --- a/include/configs/novena.h +++ /dev/null @@ -1,205 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Novena U-Boot. - * - * Copyright (C) 2014 Marek Vasut - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* System configurations */ -#define CONFIG_KEYBOARD - -#include "mx6_common.h" - -/* U-Boot Commands */ - -/* U-Boot general configurations */ - -/* U-Boot environment */ -#define CONFIG_ENV_SIZE (16 * 1024) -/* - * Environment is on MMC, starting at offset 512KiB from start of the card. - * Please place first partition at offset 1MiB from the start of the card - * as recommended by GNU/fdisk. See below for details: - * http://homepage.ntlworld.com./jonathan.deboynepollard/FGA/disc-partition-alignment.html - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET (512 * 1024) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#endif - -/* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_HOSTNAME "novena" - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 - -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) - -/* SPL */ -#include "imx6_spl.h" /* common IMX6 SPL configuration */ - -/* Ethernet Configuration */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x7 -#define CONFIG_ARP_TIMEOUT 200UL -#endif - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_SPD_BUS_NUM 0 - -/* I2C EEPROM */ -#ifdef CONFIG_CMD_EEPROM -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_BUS 2 -#endif - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* PCI express */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(3, 29) -#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(7, 12) -#endif - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -/* SATA Configs */ -#define CONFIG_LBA48 - -/* UART */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -/* Gadget part */ -#define CONFIG_USBD_HS -#define CONFIG_NETCONSOLE -#endif - -/* Video output */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -/* Extra U-Boot environment. */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "consdev=ttymxc1\0" \ - "baudrate=115200\0" \ - "bootdev=/dev/mmcblk0p1\0" \ - "rootdev=/dev/mmcblk0p2\0" \ - "netdev=eth0\0" \ - "kernel_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ - "pxefile_addr_r="__stringify(CONFIG_LOADADDR)"\0" \ - "scriptaddr="__stringify(CONFIG_LOADADDR)"\0" \ - "ramdisk_addr_r=0x28000000\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdtfile=imx6q-novena.dtb\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "ext4load mmc 0:1 ${kernel_addr_r} ${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "update_sd_spl_filename=SPL\0" \ - "update_sd_uboot_filename=u-boot.img\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if dhcp ${update_sd_spl_filename} ; then " \ - "mmc write ${loadaddr} 2 0x200 ; " \ - "fi ; " \ - "if dhcp ${update_sd_uboot_filename} ; then " \ - "fatwrite mmc 0:1 ${loadaddr} u-boot.img ${filesize} ; "\ - "fi ; " \ - "fi\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(SATA, sata, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#else -#define CONFIG_EXTRA_ENV_SETTINGS -#endif /* CONFIG_SPL_BUILD */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/nsa310s.h b/include/configs/nsa310s.h deleted file mode 100644 index eb465e0..0000000 --- a/include/configs/nsa310s.h +++ /dev/null @@ -1,76 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 - * Gerald Kerma - * Tony Dinh - * Luka Perkov - */ - -#ifndef _CONFIG_NSA310S_H -#define _CONFIG_NSA310S_H - -/* high level configuration options */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6192 1 /* SOC Name */ -#define CONFIG_KW88F6702 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* compression configuration */ -#define CONFIG_BZIP2 - -/* commands configuration */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* environment variables configuration */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 -#endif -#define CONFIG_ENV_SIZE 0x20000 -#define CONFIG_ENV_OFFSET 0xe0000 - -/* default environment variables */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \ - "ubi part root; " \ - "ubifsmount ubi:rootfs; " \ - "ubifsload 0x800000 ${kernel}; " \ - "ubifsload 0x700000 ${fdt}; " \ - "ubifsumount; " \ - "fdt addr 0x700000; fdt resize; fdt chosen; " \ - "bootz 0x800000 - 0x700000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=console=ttyS0,115200\0" \ - "mtdids=nand0=orion_nand\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "kernel=/boot/zImage\0" \ - "fdt=/boot/nsa310s.dtb\0" \ - "bootargs_root=ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw\0" - -/* Ethernet driver configuration */ -#ifdef CONFIG_CMD_NET -#define CONFIG_NETCONSOLE -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 1 -#define CONFIG_RESET_PHY_R -#endif /* CONFIG_CMD_NET */ - -/* SATA driver configuration */ -#ifdef CONFIG_IDE -#define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#endif /* CONFIG_IDE */ - -/* RTC driver configuration */ -#ifdef CONFIG_CMD_DATE -#define CONFIG_RTC_MV -#endif /* CONFIG_CMD_DATE */ - -#endif /* _CONFIG_NSA310S_H */ diff --git a/include/configs/nsim.h b/include/configs/nsim.h deleted file mode 100644 index 61217bb..0000000 --- a/include/configs/nsim.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013-2016 Synopsys, Inc. All rights reserved. - */ - -#ifndef _CONFIG_NSIM_H_ -#define _CONFIG_NSIM_H_ - -#include - -/* - * Memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_256M - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN SZ_2M -#define CONFIG_SYS_BOOTM_LEN SZ_32M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -/* - * Environment configuration - */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -/* - * Console configuration - */ - -#endif /* _CONFIG_NSIM_H_ */ diff --git a/include/configs/nyan-big.h b/include/configs/nyan-big.h deleted file mode 100644 index fca4eb5..0000000 --- a/include/configs/nyan-big.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Google/NVIDIA Nyan-big" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) - -/* Align LCD to 1MB boundary */ -#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#undef CONFIG_LOADADDR -#define CONFIG_LOADADDR 0x82408000 - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h deleted file mode 100644 index 9f2d43e..0000000 --- a/include/configs/odroid.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Samsung Electronics - * Sanghee Kim - * Piotr Wilczek - * Przemyslaw Marczak - * - * Configuation settings for the Odroid-U3 (EXYNOS4412) board. - */ - -#ifndef __CONFIG_ODROID_U3_H -#define __CONFIG_ODROID_U3_H - -#include - -#define CONFIG_SYS_L2CACHE_OFF -#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE 0x10502000 -#endif - -#define CONFIG_MACH_TYPE 4289 - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -/* Reserve the last 1 MiB for the secure firmware */ -#define CONFIG_SYS_MEM_TOP_HIDE (1UL << 20UL) -#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#include - -/* select serial console configuration */ - -/* Console configuration */ - -#define CONFIG_BOOTCOMMAND "run distro_bootcmd ; run autoboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV -#define CONFIG_ENV_SIZE SZ_16K -#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ -#define CONFIG_ENV_OVERWRITE - -/* Partitions name */ -#define PARTS_BOOT "boot" -#define PARTS_ROOT "platform" - -#define CONFIG_DFU_ALT \ - "uImage fat 0 1;" \ - "zImage fat 0 1;" \ - "Image.itb fat 0 1;" \ - "uInitrd fat 0 1;" \ - "exynos4412-odroidu3.dtb fat 0 1;" \ - "exynos4412-odroidx2.dtb fat 0 1;" \ - ""PARTS_BOOT" part 0 1;" \ - ""PARTS_ROOT" part 0 2\0" \ - -#define CONFIG_SET_DFU_ALT_INFO -#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) - -#define CONFIG_DFU_ALT_BOOT_EMMC \ - "u-boot raw 0x3e 0x800 mmcpart 1;" \ - "bl1 raw 0x0 0x1e mmcpart 1;" \ - "bl2 raw 0x1e 0x1d mmcpart 1;" \ - "tzsw raw 0x83e 0x138 mmcpart 1\0" - -#define CONFIG_DFU_ALT_BOOT_SD \ - "u-boot raw 0x3f 0x800;" \ - "bl1 raw 0x1 0x1e;" \ - "bl2 raw 0x1f 0x1d;" \ - "tzsw raw 0x83f 0x138\0" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) - -#include - -/* - * Bootable media layout: - * dev: SD eMMC(part boot) - * BL1 1 0 - * BL2 31 30 - * UBOOT 63 62 - * TZSW 2111 2110 - * ENV 2560 2560(part user) - * - * MBR Primary partiions: - * Num Name Size Offset - * 1. BOOT: 100MiB 2MiB - * 2. ROOT: - -*/ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadbootscript=load mmc ${mmcbootdev}:${mmcbootpart} ${scriptaddr} " \ - "boot.scr\0" \ - "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kernel_addr_r} " \ - "${kernelname}\0" \ - "loadinitrd=load mmc ${mmcbootdev}:${mmcbootpart} ${ramdisk_addr_r} " \ - "${initrdname}\0" \ - "loaddtb=load mmc ${mmcbootdev}:${mmcbootpart} ${fdt_addr_r} " \ - "${fdtfile}\0" \ - "check_ramdisk=" \ - "if run loadinitrd; then " \ - "setenv initrd_addr ${ramdisk_addr_r};" \ - "else " \ - "setenv initrd_addr -;" \ - "fi;\0" \ - "check_dtb=" \ - "if run loaddtb; then " \ - "setenv fdt_addr ${fdt_addr_r};" \ - "else " \ - "setenv fdt_addr;" \ - "fi;\0" \ - "kernel_args=" \ - "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart}" \ - " rootwait ${console} ${opts}\0" \ - "boot_script=" \ - "run loadbootscript;" \ - "source ${scriptaddr}\0" \ - "boot_fit=" \ - "setenv kernelname Image.itb;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootm ${kernel_addr_r}#${board_name}\0" \ - "boot_uimg=" \ - "setenv kernelname uImage;" \ - "run check_dtb;" \ - "run check_ramdisk;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootm ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \ - "boot_zimg=" \ - "setenv kernelname zImage;" \ - "run check_dtb;" \ - "run check_ramdisk;" \ - "run loadkernel;" \ - "run kernel_args;" \ - "bootz ${kernel_addr_r} ${initrd_addr} ${fdt_addr};\0" \ - "autoboot=" \ - "if test -e mmc 0 boot.scr; then; " \ - "run boot_script; " \ - "elif test -e mmc 0 Image.itb; then; " \ - "run boot_fit;" \ - "elif test -e mmc 0 zImage; then; " \ - "run boot_zimg;" \ - "elif test -e mmc 0 uImage; then; " \ - "run boot_uimg;" \ - "fi;\0" \ - "console=" CONFIG_DEFAULT_CONSOLE \ - "mmcbootdev=0\0" \ - "mmcbootpart=1\0" \ - "mmcrootdev=0\0" \ - "mmcrootpart=2\0" \ - "dfu_alt_system="CONFIG_DFU_ALT \ - "dfu_alt_info=Please reset the board\0" \ - "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ - "consoleoff=set console console=ram; save; reset\0" \ - "initrdname=uInitrd\0" \ - "ramdisk_addr_r=0x42000000\0" \ - "scriptaddr=0x42000000\0" \ - "fdt_addr_r=0x40800000\0" \ - "kernel_addr_r=0x41000000\0" \ - BOOTENV - -/* GPT */ - -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - -/* - * Supported Odroid boards: X3, U3 - * TODO: Add Odroid X support - */ -#define CONFIG_MISC_COMMON - -#undef CONFIG_REVISION_TAG - -#endif /* __CONFIG_H */ diff --git a/include/configs/odroid_xu3.h b/include/configs/odroid_xu3.h deleted file mode 100644 index af6004e..0000000 --- a/include/configs/odroid_xu3.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * Hyungwon Hwang - */ - -#ifndef __CONFIG_ODROID_XU3_H -#define __CONFIG_ODROID_XU3_H - -#include -#include - -#define CONFIG_BOARD_COMMON - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 - -/* select serial console configuration */ - -#define TZPC_BASE_OFFSET 0x10000 - -#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -/* Reserve the last 22 MiB for the secure firmware */ -#define CONFIG_SYS_MEM_TOP_HIDE (22UL << 20UL) -#define CONFIG_TZSW_RESERVED_DRAM_SIZE CONFIG_SYS_MEM_TOP_HIDE - -#undef CONFIG_ENV_SIZE -#undef CONFIG_ENV_OFFSET -#define CONFIG_ENV_SIZE (SZ_1K * 16) -#define CONFIG_ENV_OFFSET (SZ_1K * 3136) /* ~3 MiB offset */ - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - -/* USB */ -#define CONFIG_USB_EHCI_EXYNOS - -/* DFU */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#define DFU_MANIFEST_POLL_TIMEOUT 25000 - -/* THOR */ -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_USB_GADGET_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D - -/* UMS */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - -/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */ -#undef CONFIG_EXYNOS_TMU - -#define CONFIG_DFU_ALT_SYSTEM \ - "uImage fat 0 1;" \ - "zImage fat 0 1;" \ - "Image.itb fat 0 1;" \ - "uInitrd fat 0 1;" \ - "boot.scr fat 0 1;" \ - "boot.cmd fat 0 1;" \ - "exynos5422-odroidxu3.dtb fat 0 1;" \ - "exynos5422-odroidxu3-lite.dtb fat 0 1;" \ - "exynos5422-odroidxu4.dtb fat 0 1;" \ - "exynos5422-odroidhc1.dtb fat 0 1;" \ - "boot part 0 1;" \ - "root part 0 2\0" - -#define CONFIG_DFU_ALT_BOOT_EMMC \ - "u-boot raw 0x3e 0x800 mmcpart 1;" \ - "bl1 raw 0x0 0x1e mmcpart 1;" \ - "bl2 raw 0x1e 0x1d mmcpart 1;" \ - "tzsw raw 0x83e 0x200 mmcpart 1;" \ - "params.bin raw 0x1880 0x20\0" - -#define CONFIG_DFU_ALT_BOOT_SD \ - "u-boot raw 0x3f 0x800;" \ - "bl1 raw 0x1 0x1e;" \ - "bl2 raw 0x1f 0x1d;" \ - "tzsw raw 0x83f 0x200;" \ - "params.bin raw 0x1880 0x20\0" - -/* Enable: board/samsung/common/misc.c to use set_dfu_alt_info() */ -#define CONFIG_MISC_COMMON -#define CONFIG_SET_DFU_ALT_INFO -#define CONFIG_SET_DFU_ALT_BUF_LEN (SZ_1K) - -/* Set soc_rev, soc_id, board_rev, board_name, fdtfile */ -#define CONFIG_ODROID_REV_AIN 9 -#define CONFIG_REVISION_TAG - -/* - * Need to override existing one (smdk5420) with odroid so set_board_info will - * use proper prefix when creating full board_name (SYS_BOARD + type) - */ -#undef CONFIG_SYS_BOARD -#define CONFIG_SYS_BOARD "odroid" - -/* Define new extra env settings, including DFU settings */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS \ - EXYNOS_FDTFILE_SETTING \ - MEM_LAYOUT_ENV_SETTINGS \ - BOOTENV \ - "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE \ - "fdtfile=exynos5422-odroidxu3.dtb\0" \ - "board_name=odroidxu3\0" \ - "mmcbootdev=0\0" \ - "mmcrootdev=0\0" \ - "mmcbootpart=1\0" \ - "mmcrootpart=2\0" \ - "dfu_alt_system="CONFIG_DFU_ALT_SYSTEM \ - "dfu_alt_info=Autoset by THOR/DFU command run.\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h deleted file mode 100644 index e8c6083..0000000 --- a/include/configs/omap3_beagle.h +++ /dev/null @@ -1,225 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * - * Configuration settings for the TI OMAP3530 Beagle board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). - */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* NAND */ -#if defined(CONFIG_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K -#define CONFIG_ENV_ADDR 0x260000 -#define CONFIG_ENV_OVERWRITE -/* NAND: SPL falcon mode configs */ -#if defined(CONFIG_SPL_OS_BOOT) -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 -#endif /* CONFIG_SPL_OS_BOOT */ -#endif /* CONFIG_NAND */ - -/* USB EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 - -/* Enable Multi Bus support for I2C */ -#define CONFIG_I2C_MULTI_BUS - -/* DSS Support */ - -/* TWL4030 LED Support */ - -#define MEM_LAYOUT_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV - -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance "; " \ - "run mmcboot\0" -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#if defined(CONFIG_NAND) - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \ - "echo NAND boot disabled: No mtdids and/or mtdparts; " \ - "else " \ - "run nandboot; " \ - "fi\0" -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ - func(UBIFS, ubifs, 0) \ - func(NAND, nand, 0) - -#else /* !CONFIG_NAND */ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) - -#endif /* CONFIG_NAND */ - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_high=0xffffffff\0" \ - "console=ttyO2,115200n8\0" \ - "bootdir=/boot\0" \ - "bootenv=uEnv.txt\0" \ - "bootfile=zImage\0" \ - "bootpart=0:2\0" \ - "bootubivol=rootfs\0" \ - "bootubipart=rootfs\0" \ - "usbtty=cdc_acm\0" \ - "mpurate=auto\0" \ - "buddy=none\0" \ - "camera=none\0" \ - "vram=12M\0" \ - "dvimode=640x480MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "defaultargs=setenv defargs " \ - "mpurate=${mpurate} " \ - "buddy=${buddy} "\ - "camera=${camera} "\ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay}\0" \ - "optargs=\0" \ - "findfdt=" \ - "if test $beaglerev = AxBx; then " \ - "setenv fdtfile omap3-beagle.dtb; fi; " \ - "if test $beaglerev = Cx; then " \ - "setenv fdtfile omap3-beagle.dtb; fi; " \ - "if test $beaglerev = C4; then " \ - "setenv fdtfile omap3-beagle.dtb; fi; " \ - "if test $beaglerev = xMAB; then " \ - "setenv fdtfile omap3-beagle-xm-ab.dtb; fi; " \ - "if test $beaglerev = xMC; then " \ - "setenv fdtfile omap3-beagle-xm.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=run defaultargs; setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${defargs} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "userbutton_xm=gpio input 4;\0" \ - "userbutton_nonxm=gpio input 7;\0" \ - "userbutton=if gpio input 173; then " \ - "run userbutton_xm; " \ - "else " \ - "run userbutton_nonxm; " \ - "fi;\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \ - "mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "if run userbutton; then " \ - "setenv bootenv uEnv.txt;" \ - "else " \ - "setenv bootenv user.txt;" \ - "fi;" \ - "run loadbootenv && run importbootenv; " \ - "run ext4bootenv && run importbootenv; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "fi\0" \ - "validatefdt=" \ - "if test $beaglerev = xMAB; then " \ - "if test ! -e mmc ${bootpart} ${bootdir}/${fdtfile}; then " \ - "setenv fdtfile omap3-beagle-xm.dtb; " \ - "fi; " \ - "fi; \0" \ - "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loaddtb=run validatefdt; ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcboot=run mmcbootenv; " \ - "if run loadimage && run loaddtb; then " \ - "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \ - "run mmcargs; " \ - "if test ${bootfile} = uImage; then " \ - "bootm ${loadaddr} - ${fdtaddr}; " \ - "fi; " \ - "if test ${bootfile} = zImage; then " \ - "bootz ${loadaddr} - ${fdtaddr}; " \ - "fi; " \ - "fi\0" \ - "nandroot=ubi0:rootfs ubi.mtd=rootfs rw\0" \ - "nandrootfstype=ubifs rootwait\0" \ - "nandargs=run defaultargs; setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${defargs} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \ - "echo Booting uImage from NAND MTD 'kernel' partition ...; " \ - "run nandargs; " \ - "bootm ${loadaddr} - ${fdtaddr}; " \ - "fi\0" \ - "loadramdisk=ext4load mmc ${bootpart} ${rdaddr} ${bootdir}/${ramdisk}\0" \ - "ramdisk=rootfs.ext2.gz.uboot\0" \ - "ramdisk_size=16384\0" \ - "ramroot=/dev/ram rw\0" \ - "ramrootfstype=ext2\0" \ - "ramargs=run defaultargs; setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${defargs} " \ - "${optargs} " \ - "root=${ramroot} ramdisk_size=${ramdisk_size} " \ - "rootfstype=${ramrootfstype}\0" \ - "ramboot=run mmcbootenv; " \ - "if run loadimage && run loaddtb && run loadramdisk; then " \ - "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} w/ramdisk ...; " \ - "run ramargs; " \ - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}; " \ - "fi\0" \ - BOOTENV - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_cairo.h b/include/configs/omap3_cairo.h deleted file mode 100644 index 9e2b752..0000000 --- a/include/configs/omap3_cairo.h +++ /dev/null @@ -1,217 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the QUIPOS Cairo board. - * - * Copyright (C) DENX GmbH - * - * Author : - * Albert ARIBAUD - * - * Derived from EVM code by - * Manikandan Pillai - * Itself derived from Beagle Board and 3430 SDP code by - * Richard Woodruff - * Syed Mohammed Khasim - * - * Also derived from include/configs/omap3_beagle.h - */ - -#ifndef __OMAP3_CAIRO_CONFIG_H -#define __OMAP3_CAIRO_CONFIG_H - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. We use this rather than the inherited defines from - * ti_armv7_common.h for backwards compatibility. - */ -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 << 10) /* 512 KB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#include - -#define CONFIG_REVISION_TAG 1 -#define CONFIG_ENV_OVERWRITE - -/* Enable Multi Bus support for I2C */ -#define CONFIG_I2C_MULTI_BUS 1 - -/* Probe all devices */ -#define CONFIG_SYS_I2C_NOPROBES { {0x0, 0x0} } - -/* - * TWL4030 - */ - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "machid=ffffffff\0" \ - "fdt_high=0x87000000\0" \ - "baudrate=115200\0" \ - "fec_addr=00:50:C2:7E:90:F0\0" \ - "netmask=255.255.255.0\0" \ - "ipaddr=192.168.2.9\0" \ - "gateway=192.168.2.1\0" \ - "serverip=192.168.2.10\0" \ - "nfshost=192.168.2.10\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "bootargs_mmc_ramdisk=mem=128M " \ - "console=ttyO1,115200n8 " \ - "root=/dev/ram0 rw " \ - "initrd=0x81600000,16M " \ - "mpurate=600 ramdisk_size=16384 omapfb.rotate=1 " \ - "omapfb.rotate_type=1 omap_vout.vid1_static_vrfb_alloc=y\0" \ - "mmcboot=mmc init; " \ - "fatload mmc 0 0x80000000 uImage; " \ - "fatload mmc 0 0x81600000 ramdisk.gz; " \ - "setenv bootargs ${bootargs_mmc_ramdisk}; " \ - "bootm 0x80000000\0" \ - "bootargs_nfs=mem=99M console=ttyO0,115200n8 noinitrd rw ip=dhcp " \ - "root=/dev/nfs " \ - "nfsroot=192.168.2.10:/home/spiid/workdir/Quipos/rootfs,nolock " \ - "mpurate=600 omapfb.rotate=1 omapfb.rotate_type=1 " \ - "omap_vout.vid1_static_vrfb_alloc=y\0" \ - "boot_nfs=run get_kernel; setenv bootargs ${bootargs_nfs}; " \ - "bootm 0x80000000\0" \ - "bootargs_nand=mem=128M console=ttyO1,115200n8 noinitrd " \ - "root=/dev/mtdblock4 rw rootfstype=jffs2 mpurate=600 " \ - "omap_vout.vid1_static_vrfb_alloc=y omapfb.rotate=1 " \ - "omapfb.rotate_type=1\0" \ - "boot_nand=nand read.i 0x80000000 280000 300000; setenv " \ - "bootargs ${bootargs_nand}; bootm 0x80000000\0" \ - "ledorange=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ - "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ - "i2c mw 60 09 10 1; i2c mw 60 06 10 1\0" \ - "ledgreen=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ - "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; i2c " \ - "mw 60 09 00 1; i2c mw 60 06 10 1\0" \ - "ledoff=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ - "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ - "i2c mw 60 09 00 1; i2c mw 60 06 0 1\0" \ - "ledred=i2c dev 1; i2c mw 60 00 00 1; i2c mw 60 14 FF 1; " \ - "i2c mw 60 15 FF 1; i2c mw 60 16 FF 1; i2c mw 60 17 FF 1; " \ - "i2c mw 60 09 10 1; i2c mw 60 06 0 1\0" \ - "flash_xloader=mw.b 0x81600000 0xff 0x20000; " \ - "nand erase 0 20000; " \ - "fatload mmc 0 0x81600000 MLO; " \ - "nandecc hw; " \ - "nand write.i 0x81600000 0 20000;\0" \ - "flash_uboot=mw.b 0x81600000 0xff 0x40000; " \ - "nand erase 80000 40000; " \ - "fatload mmc 0 0x81600000 u-boot.bin; " \ - "nandecc sw; " \ - "nand write.i 0x81600000 80000 40000;\0" \ - "flash_kernel=mw.b 0x81600000 0xff 0x300000; " \ - "nand erase 280000 300000; " \ - "fatload mmc 0 0x81600000 uImage; " \ - "nandecc sw; " \ - "nand write.i 0x81600000 280000 300000;\0" \ - "flash_rootfs=fatload mmc 0 0x81600000 rootfs.jffs2; " \ - "nandecc sw; " \ - "nand write.jffs2 0x680000 0xFF ${filesize}; " \ - "nand erase 680000 ${filesize}; " \ - "nand write.jffs2 81600000 680000 ${filesize};\0" \ - "flash_scrub=nand scrub; " \ - "run flash_xloader; " \ - "run flash_uboot; " \ - "run flash_kernel; " \ - "run flash_rootfs;\0" \ - "flash_all=run ledred; " \ - "nand erase.chip; " \ - "run ledorange; " \ - "run flash_xloader; " \ - "run flash_uboot; " \ - "run flash_kernel; " \ - "run flash_rootfs; " \ - "run ledgreen; " \ - "run boot_nand; \0" \ - -#define CONFIG_BOOTCOMMAND \ - "if fatload mmc 0 0x81600000 MLO; then run flash_all; " \ - "else run boot_nand; fi" - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_ADDR 0x260000 - -/* Defines for SPL */ - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - -/* env defaults */ -#define CONFIG_BOOTFILE "uImage" - -/* Provide the MACH_TYPE value the vendor kernel requires */ -#define CONFIG_MACH_TYPE 3063 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ - -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ - /* on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ - -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#endif /* __OMAP3_CAIRO_CONFIG_H */ diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h deleted file mode 100644 index 8e98977..0000000 --- a/include/configs/omap3_evm.h +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the TI OMAP3 EVM board. - * - * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * Author : - * Manikandan Pillai - * Derived from Beagle Board and 3430 SDP code by - * Richard Woodruff - * Syed Mohammed Khasim - * - * Manikandan Pillai - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). - */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* NAND */ -#if defined(CONFIG_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ - 10, 11, 12, 13} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW -#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K -#define CONFIG_ENV_ADDR 0x260000 -#define CONFIG_ENV_OVERWRITE -/* NAND: SPL falcon mode configs */ -#if defined(CONFIG_SPL_OS_BOOT) -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 -#endif /* CONFIG_SPL_OS_BOOT */ -#endif /* CONFIG_NAND */ - -#define MEM_LAYOUT_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV - -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance "; " \ - "run mmcboot\0" -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#if defined(CONFIG_NAND) - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \ - "echo NAND boot disabled: No mtdids and/or mtdparts; " \ - "else " \ - "run nandboot; " \ - "fi\0" -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ - func(UBIFS, ubifs, 0) \ - func(NAND, nand, 0) - -#else /* !CONFIG_NAND */ - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) - -#endif /* CONFIG_NAND */ - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "fdt_high=0xffffffff\0" \ - "console=ttyO0,115200n8\0" \ - "bootdir=/boot\0" \ - "bootenv=uEnv.txt\0" \ - "bootfile=zImage\0" \ - "bootpart=0:2\0" \ - "bootubivol=rootfs\0" \ - "bootubipart=rootfs\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "ext4bootenv=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc${mmcdev} ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "mmcbootenv=setenv bootpart ${mmcdev}:${mmcpart}; " \ - "mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "run loadbootenv && run importbootenv; " \ - "run ext4bootenv && run importbootenv; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "fi\0" \ - "loadimage=ext4load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loaddtb=ext4load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcboot=run mmcbootenv; " \ - "if run loadimage && run loaddtb; then " \ - "echo Booting ${bootdir}/${bootfile} from mmc ${bootpart} ...; " \ - "run mmcargs; " \ - "if test ${bootfile} = uImage; then " \ - "bootm ${loadaddr} - ${fdtaddr}; " \ - "fi; " \ - "if test ${bootfile} = zImage; then " \ - "bootz ${loadaddr} - ${fdtaddr}; " \ - "fi; " \ - "fi\0" \ - "nandroot=ubi0:rootfs ubi.mtd=rootfs rw noinitrd\0" \ - "nandrootfstype=ubifs rootwait\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandboot=if nand read ${loadaddr} kernel && nand read ${fdtaddr} dtb; then " \ - "echo Booting uImage from NAND MTD 'kernel' partition ...; " \ - "run nandargs; " \ - "bootm ${loadaddr} - ${fdtaddr}; " \ - "fi\0" \ - BOOTENV - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_igep00x0.h b/include/configs/omap3_igep00x0.h deleted file mode 100644 index 4ad7dc1..0000000 --- a/include/configs/omap3_igep00x0.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common configuration settings for IGEP technology based boards - * - * (C) Copyright 2012 - * ISEE 2007 SL, - */ - -#ifndef __IGEP00X0_H -#define __IGEP00X0_H - -#include - -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). - */ - -#define CONFIG_REVISION_TAG 1 - -/* TPS65950 */ -#define PBIASLITEVMODE1 (1 << 8) - -/* LED */ -#define IGEP0020_GPIO_LED 27 -#define IGEP0030_GPIO_LED 16 - -/* Board and revision detection GPIOs */ -#define IGEP0030_USB_TRANSCEIVER_RESET 54 -#define GPIO_IGEP00X0_BOARD_DETECTION 28 -#define GPIO_IGEP00X0_REVISION_DETECTION 129 - -#ifndef CONFIG_SPL_BUILD - -/* Environment */ -#define ENV_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define MEM_LAYOUT_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "scriptaddr=0x87E00000\0" \ - "pxefile_addr_r=0x87F00000\0" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#include - -#define ENV_FINDFDT \ - "findfdt="\ - "if test ${board_name} = igep0020; then " \ - "if test ${board_rev} = F; then " \ - "setenv fdtfile omap3-igep0020-rev-f.dtb; " \ - "else " \ - "setenv fdtfile omap3-igep0020.dtb; fi; fi; " \ - "if test ${board_name} = igep0030; then " \ - "if test ${board_rev} = G; then " \ - "setenv fdtfile omap3-igep0030-rev-g.dtb; " \ - "else " \ - "setenv fdtfile omap3-igep0030.dtb; fi; fi; " \ - "if test ${fdtfile} = ''; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_FINDFDT \ - ENV_DEVICE_SETTINGS \ - MEM_LAYOUT_SETTINGS \ - BOOTENV - -#endif - -#define CONFIG_SYS_MTDPARTS_RUNTIME - -/* OneNAND config */ -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024) - -/* NAND config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW - -#endif /* __IGEP00X0_H */ diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h deleted file mode 100644 index 90292ae..0000000 --- a/include/configs/omap3_logic.h +++ /dev/null @@ -1,210 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Logic Product Development - * Peter Barada - * - * Configuration settings for the Logic OMAP35x/DM37x SOM LV/Torpedo - * reference boards. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ - -#include - -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB) in - * order to allow for BCH8 to fit in. - */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Hardware drivers */ - -/* I2C */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C64 */ - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_USB_EHCI_OMAP -#endif -#ifdef CONFIG_USB_EHCI_OMAP -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 4 -#endif - -/* Board NAND Info. */ -#ifdef CONFIG_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ - /* NAND devices */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ - 13, 14, 16, 17, 18, 19, 20, 21, 22, \ - 23, 24, 25, 26, 27, 28, 30, 31, 32, \ - 33, 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 44, 45, 46, 47, 48, 49, 50, 51, \ - 52, 53, 54, 55, 56} - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#endif - -/* Environment information */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mmcdev=0\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=fs noinitrd\0" \ - "nandrootfstype=ubifs rootwait\0" \ - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "run defaultboot;" \ - "fi; " \ - "else run defaultboot; fi\0" \ - "defaultboot=run mmcramboot\0" \ - "consoledevice=ttyS0\0" \ - "setconsole=setenv console ${consoledevice},${baudrate}n8\0" \ - "dump_bootargs=echo 'Bootargs: '; echo $bootargs\0" \ - "rotation=0\0" \ - "vrfb_arg=if itest ${rotation} -ne 0; then " \ - "setenv bootargs ${bootargs} omapfb.vrfb=y " \ - "omapfb.rotate=${rotation}; " \ - "fi\0" \ - "optargs=ignore_loglevel early_printk no_console_suspend\0" \ - "common_bootargs=run setconsole; setenv bootargs " \ - "${bootargs} "\ - "console=${console} " \ - "${mtdparts} "\ - "${optargs}; " \ - "run vrfb_arg\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo 'Running bootscript from mmc ...'; " \ - "source ${loadaddr}\0" \ - "loadimage=mmc rescan; " \ - "load mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "ramdisksize=64000\0" \ - "ramdiskimage=rootfs.ext2.gz.uboot\0" \ - "loadramdisk=mmc rescan; " \ - "load mmc ${mmcdev} ${rdaddr} ${ramdiskimage}\0" \ - "ramargs=setenv bootargs "\ - "root=/dev/ram rw ramdisk_size=${ramdisksize}\0" \ - "mmcargs=setenv bootargs "\ - "root=PARTUUID=${uuid} " \ - "rootfstype=${mmcrootfstype} rw\0" \ - "nandargs=setenv bootargs "\ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nfsargs=setenv serverip ${tftpserver}; " \ - "setenv bootargs root=/dev/nfs " \ - "nfsroot=${nfsrootpath} " \ - "ip=${ipaddr}:${tftpserver}:${gatewayip}:${netmask}::eth0:off\0" \ - "nfsrootpath=/opt/nfs-exports/omap\0" \ - "autoload=no\0" \ - "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "loadfdt=mmc rescan; " \ - "load mmc ${mmcdev} ${fdtaddr} ${fdtimage}\0" \ - "mmcbootcommon=echo Booting with DT from mmc${mmcdev} ...; " \ - "run finduuid; "\ - "run mmcargs; " \ - "run common_bootargs; " \ - "run dump_bootargs; " \ - "run loadimage; " \ - "run loadfdt;\0 " \ - "mmcbootz=setenv bootfile zImage; " \ - "run mmcbootcommon; "\ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "mmcboot=setenv bootfile uImage; "\ - "run mmcbootcommon; "\ - "bootm ${loadaddr} - ${fdtaddr}\0" \ - "mmcrambootcommon=echo 'Booting kernel from MMC w/ramdisk...'; " \ - "run ramargs; " \ - "run common_bootargs; " \ - "run dump_bootargs; " \ - "run loadimage; " \ - "run loadfdt; " \ - "run loadramdisk\0" \ - "mmcramboot=setenv bootfile uImage; " \ - "run mmcrambootcommon; " \ - "bootm ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ - "mmcrambootz=setenv bootfile zImage; " \ - "run mmcrambootcommon; " \ - "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ - "tftpboot=echo 'Booting kernel/ramdisk rootfs from tftp...'; " \ - "run ramargs; " \ - "run common_bootargs; " \ - "run dump_bootargs; " \ - "tftpboot ${loadaddr} ${zimage}; " \ - "tftpboot ${rdaddr} ${ramdiskimage}; " \ - "bootm ${loadaddr} ${rdaddr}\0" \ - "tftpbootz=echo 'Booting kernel NFS rootfs...'; " \ - "dhcp;" \ - "run nfsargs;" \ - "run common_bootargs;" \ - "run dump_bootargs;" \ - "tftpboot $loadaddr zImage;" \ - "bootz $loadaddr\0" \ - "nandbootcommon=echo 'Booting kernel from NAND...';" \ - "run nandargs;" \ - "run common_bootargs;" \ - "run dump_bootargs;" \ - "nand read ${loadaddr} kernel;" \ - "nand read ${fdtaddr} spl-os;\0" \ - "nandbootz=run nandbootcommon; "\ - "bootz ${loadaddr} - ${fdtaddr}\0"\ - "nandboot=run nandbootcommon; "\ - "bootm ${loadaddr} - ${fdtaddr}\0"\ - -#define CONFIG_BOOTCOMMAND \ - "run autoboot" - -/* Miscellaneous configurable options */ - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -/* FLASH and environment organization */ - -/* **** PISMO SUPPORT *** */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#endif - -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_SYS_FLASH_SIZE 0x4000000 - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_ADDR 0x260000 - -/* Defines for SPL */ - -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h deleted file mode 100644 index 38a10e2..0000000 --- a/include/configs/omap3_overo.h +++ /dev/null @@ -1,189 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Gumstix Overo board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -/* - * We are only ever GP parts and will utilize all of the "downloaded image" - * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). - */ - -/* call misc_init_r */ - -/* pass the revision tag */ -#define CONFIG_REVISION_TAG - -/* override size of malloc() pool */ -#undef CONFIG_SYS_MALLOC_LEN -/* Shift 128 << 15 provides 4 MiB heap to support UBI commands. - * Shift 128 << 10 provides 128 KiB heap for limited-memory devices. */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 15)) - -/* I2C Support */ - -/* TWL4030 LED */ - -/* USB EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 183 - -/* commands to include */ - -#ifdef CONFIG_NAND -/* NAND block size is 128 KiB. Synchronize these values with - * overo_nand_partitions in mach-omap2/board-overo.c in Linux: - * xloader 4 * NAND_BLOCK_SIZE = 512 KiB - * uboot 14 * NAND_BLOCK_SIZE = 1792 KiB - * uboot environtment 2 * NAND_BLOCK_SIZE = 256 KiB - * linux 64 * NAND_BLOCK_SIZE = 8 MiB - * rootfs remainder - */ -#endif /* CONFIG_NAND */ - -/* Board NAND Info. */ -/* Environment information */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=auto\0" \ - "optargs=\0" \ - "vram=12M\0" \ - "dvimode=1024x768MR-16@60\0" \ - "defaultdisplay=dvi\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "nandroot=ubi0:rootfs ubi.mtd=4\0" \ - "nandrootfstype=ubifs\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "mpurate=${mpurate} " \ - "vram=${vram} " \ - "omapfb.mode=dvi:${dvimode} " \ - "omapdss.def_disp=${defaultdisplay} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running boot script from mmc ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} uEnv.txt\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "loadzimage=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "loadubizimage=ubifsload ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadubifdt=ubifsload ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcbootfdt=echo Booting with DT from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "if nand read ${loadaddr} linux; then " \ - "bootm ${loadaddr};" \ - "fi;\0" \ - "nanddtsboot=echo Booting from nand with DTS...; " \ - "run nandargs; " \ - "ubi part rootfs; "\ - "ubifsmount ubi0:rootfs; "\ - "run loadubifdt; "\ - "run loadubizimage; "\ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "fi;" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot;" \ - "fi;" \ - "if run loadzimage; then " \ - "if test -z \"${fdtfile}\"; then " \ - "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ - "fi;" \ - "if run loadfdt; then " \ - "run mmcbootfdt;" \ - "fi;" \ - "fi;" \ - "fi;" \ - "run nandboot; " \ - "if test -z \"${fdtfile}\"; then "\ - "setenv fdtfile omap3-${boardname}-${expansionname}.dtb;" \ - "fi;" \ - "run nanddtsboot; " \ - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -/* FLASH and environment organization */ -#if defined(CONFIG_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_OFFSET 0x240000 -#define CONFIG_ENV_ADDR 0x240000 - -/* Initial RAM setup */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ - 13, 14, 16, 17, 18, 19, 20, 21, 22, \ - 23, 24, 25, 26, 27, 28, 30, 31, 32, \ - 33, 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 44, 45, 46, 47, 48, 49, 50, 51, \ - 52, 53, 54, 55, 56} -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h deleted file mode 100644 index 98f243f..0000000 --- a/include/configs/omap3_pandora.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008-2010 - * Gražvydas Ignotas - * - * Configuration settings for the OMAP3 Pandora. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* override base for compatibility with MLO the device ships with */ - -#include - -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_SYS_DEVICE_NULLDEV 1 - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_SW -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 - - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd; " \ - "setenv bootargs ${bootargs_ubi}; " \ - "if mmc rescan && load mmc 0:1 ${loadaddr} autoboot.scr; then " \ - "source ${loadaddr}; " \ - "fi; " \ - "ubi part boot && ubifsmount ubi:boot && " \ - "ubifsload ${loadaddr} uImage && bootm ${loadaddr}" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "usbtty=cdc_acm\0" \ - "bootargs_ubi=ubi.mtd=4 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs " \ - "rw rootflags=bulk_read vram=6272K omapfb.vram=0:3000K\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - BOOTENV \ - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) -#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ - 0x01F00000) /* 31MB */ - -#if defined(CONFIG_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE - - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_ADDR 0x260000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h deleted file mode 100644 index 4dc22a7..0000000 --- a/include/configs/omap3_zoom1.h +++ /dev/null @@ -1,135 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * Nishanth Menon - * - * Configuration settings for the TI OMAP3430 Zoom MDK board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include /* get chip and board defs */ -#include -#include - -/* Remove SPL boot option - we do not support that on LDP yet */ - -/* Generic NAND definition conflicts with debug_base */ -#undef CONFIG_SYS_NAND_BASE - -#define CONFIG_REVISION_TAG 1 - -/* - * Hardware drivers - */ - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 -/* Change these to suit your needs */ -#define CONFIG_USBD_VENDORID 0x0451 -#define CONFIG_USBD_PRODUCTID 0x5678 -#define CONFIG_USBD_MANUFACTURER "Texas Instruments" -#define CONFIG_USBD_PRODUCT_NAME "Zoom1" - -#if defined(CONFIG_CMD_NAND) -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif -#endif - -/* - * TWL4030 - */ - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ - -/* Environment information */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "fdtaddr=0x80f80000\0" \ - "bootfile=uImage\0" \ - "fdtfile=omap3-ldp.dtb\0" \ - "bootdir=/\0" \ - "bootpart=0:1\0" \ - "usbtty=cdc_acm\0" \ - "console=ttyO2,115200n8\0" \ - "mmcdev=0\0" \ - "videomode=1024x768@60,vxres=1024,vyres=768\0" \ - "videospec=omapfb:vram:2M,vram:4M\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ - "nandargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "loadzimage=setenv bootfile zImage; if run loadimage; then run loadfdt;fi\0"\ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "mmczboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else if run loadzimage; then " \ - "run mmczboot; " \ - "else run nandboot; " \ - "fi; fi;" \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1) /* memtest */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_2 + \ - 0x01F00000) /* 31MB */ - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#if defined(CONFIG_CMD_NAND) -#define CONFIG_SYS_FLASH_BASE NAND_BASE -#endif - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#define CONFIG_ENV_ADDR 0x260000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h deleted file mode 100644 index 835b7c2..0000000 --- a/include/configs/omap4_panda.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments Incorporated. - * Steve Sakoman - * - * Configuration settings for the TI OMAP4 Panda board. - * See ti_omap4_common.h for OMAP4 common part - */ - -#ifndef __CONFIG_PANDA_H -#define __CONFIG_PANDA_H - -/* - * High Level Configuration Options - */ - -/* USB UHH support options */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 1 -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 62 - -/* USB Networking options */ - -#define CONFIG_UBOOT_ENABLE_PADS_ALL - -#include - -/* GPIO */ - -/* ENV related config options */ - -#define CONFIG_ENV_OVERWRITE - -#endif /* __CONFIG_PANDA_H */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h deleted file mode 100644 index 1a0f9ca..0000000 --- a/include/configs/omap4_sdp4430.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments Incorporated. - * Aneesh V - * Steve Sakoman - * - * Configuration settings for the TI SDP4430 board. - * See ti_omap4_common.h for OMAP4 common part - */ - -#ifndef __CONFIG_SDP4430_H -#define __CONFIG_SDP4430_H - -/* - * High Level Configuration Options - */ -#define CONFIG_MACH_TYPE MACH_TYPE_OMAP_4430SDP - -#include - -/* ENV related config options */ -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ -#define CONFIG_ENV_OFFSET 0xE0000 - -#endif /* __CONFIG_SDP4430_H */ diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h deleted file mode 100644 index 3710a71..0000000 --- a/include/configs/omap5_uevm.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Texas Instruments Incorporated. - * Sricharan R - * - * Configuration settings for the TI EVM5430 board. - * See ti_omap5_common.h for omap5 common settings. - */ - -#ifndef __CONFIG_OMAP5_EVM_H -#define __CONFIG_OMAP5_EVM_H - -#include - -#ifndef CONFIG_SPL_BUILD -/* Define the default GPT table for eMMC */ -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}" -#endif - -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - DFU_ALT_INFO_EMMC \ - DFU_ALT_INFO_RAM - -#include - -#define CONFIG_SYS_NS16550_COM3 UART3_BASE - -/* MMC ENV related defines */ -#define CONFIG_SYS_MMC_ENV_DEV 1 /* SLOT2: eMMC(1) */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT - -/* Enhance our eMMC support / experience. */ -#define CONFIG_HSMMC2_8BIT - -/* Required support for the TCA642X GPIO we have on the uEVM */ -#define CONFIG_TCA642X -#define CONFIG_SYS_I2C_TCA642X_BUS_NUM 4 -#define CONFIG_SYS_I2C_TCA642X_ADDR 0x22 - -/* USB UHH support options */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 80 -#define CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 79 - -/* Enabled commands */ - -/* USB Networking options */ - -#define CONSOLEDEV "ttyS2" - -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ - CONFIG_SYS_SCSI_MAX_LUN) - -#endif /* __CONFIG_OMAP5_EVM_H */ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h deleted file mode 100644 index 1c41e7e..0000000 --- a/include/configs/omapl138_lcdk.h +++ /dev/null @@ -1,240 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ - * - * Based on davinci_dvevm.h. Original Copyrights follow: - * - * Copyright (C) 2007 Sergey Kubushyn - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Board - */ - -/* - * SoC Configuration - */ -#define CONFIG_MACH_OMAPL138_LCDK -#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID) -#define CONFIG_SYS_OSCIN_FREQ 24000000 -#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE -#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Memory Info - */ -#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ - -#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE -#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000 - -/* memtest start addr */ -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) - -/* memtest will be run on 16MB */ -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024) - -#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \ - DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \ - DAVINCI_SYSCFG_SUSPSRC_SPI1 | \ - DAVINCI_SYSCFG_SUSPSRC_UART2 | \ - DAVINCI_SYSCFG_SUSPSRC_EMAC | \ - DAVINCI_SYSCFG_SUSPSRC_I2C) - -/* - * PLL configuration - */ - -/* Requires CONFIG_SYS_DA850_PLL0_POSTDIV=0, set in Kconfig */ -#define CONFIG_SYS_DA850_PLL0_PLLM 18 -#define CONFIG_SYS_DA850_PLL1_PLLM 21 - -/* - * DDR2 memory configuration - */ -#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \ - DV_DDR_PHY_EXT_STRBEN | \ - (0x5 << DV_DDR_PHY_RD_LATENCY_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDBCR ( \ - (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \ - (1 << DV_DDR_SDCR_DDREN_SHIFT) | \ - (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \ - (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \ - (4 << DV_DDR_SDCR_CL_SHIFT) | \ - (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ - (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) - -/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */ -#define CONFIG_SYS_DA850_DDR2_SDBCR2 0 - -#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \ - (19 << DV_DDR_SDTMR1_RFC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RP_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \ - (2 << DV_DDR_SDTMR1_WR_SHIFT) | \ - (6 << DV_DDR_SDTMR1_RAS_SHIFT) | \ - (8 << DV_DDR_SDTMR1_RC_SHIFT) | \ - (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \ - (1 << DV_DDR_SDTMR1_WTR_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \ - (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \ - (2 << DV_DDR_SDTMR2_XP_SHIFT) | \ - (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \ - (20 << DV_DDR_SDTMR2_XSNR_SHIFT) | \ - (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \ - (1 << DV_DDR_SDTMR2_RTP_SHIFT) | \ - (2 << DV_DDR_SDTMR2_CKE_SHIFT)) - -#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000492 -#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30 - -/* - * Serial Driver info - */ -#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID) - -#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE -#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID) - -/* - * I2C Configuration - */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED 25000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ -#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20 - -/* - * Flash & Environment - */ -#ifdef CONFIG_NAND -#define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ -#define CONFIG_ENV_SIZE (128 << 9) -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST -#define CONFIG_SYS_NAND_PAGE_2K -#define CONFIG_SYS_NAND_CS 3 -#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE -#define CONFIG_SYS_NAND_MASK_CLE 0x10 -#define CONFIG_SYS_NAND_MASK_ALE 0x8 -#undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST -#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_DST - \ - CONFIG_SYS_NAND_U_BOOT_SIZE - \ - CONFIG_SYS_MALLOC_LEN - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_NAND_ECCPOS { \ - 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ - 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ - 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ - 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 } -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 10 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_LOAD -#endif - -/* - * Network & Ethernet Configuration - */ -#ifdef CONFIG_DRIVER_TI_EMAC -#undef CONFIG_DRIVER_TI_EMAC_USE_RMII -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -/* - * U-Boot general configuration - */ -#define CONFIG_BOOTFILE "zImage" /* Boot file name */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */ -#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000) - -/* - * USB Configs - */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 - -/* - * Linux Information - */ -#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100) -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTCOMMAND \ - "run envboot; " \ - "run mmcboot; " - -#define DEFAULT_LINUX_BOOT_ENV \ - "loadaddr=0xc0700000\0" \ - "fdtaddr=0xc0600000\0" \ - "scriptaddr=0xc0600000\0" - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "fdtfile=da850-lcdk.dtb\0" \ - "boot_fdt=yes\0" \ - "boot_fit=0\0" \ - "console=ttyS2,115200n8\0" - -#ifdef CONFIG_CMD_BDI -#define CONFIG_CLOCKS -#endif - -/* SD/MMC */ - -#ifdef CONFIG_ENV_IS_IN_MMC -#undef CONFIG_ENV_SIZE -#undef CONFIG_ENV_OFFSET -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ -#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */ -#endif - -/* defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SPL_STACK 0x8001ff00 -#define CONFIG_SPL_MAX_FOOTPRINT 32768 -#define CONFIG_SPL_PAD_TO 32768 - -/* additions for new relocation code, must added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0xc0000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ - GENERATED_GBL_DATA_SIZE) - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/openrd.h b/include/configs/openrd.h deleted file mode 100644 index 62d8862..0000000 --- a/include/configs/openrd.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Net Insight - * Written-by: Simon Kagstrom - * - * Based on sheevaplug.h: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -#ifndef _CONFIG_OPENRD_H -#define _CONFIG_OPENRD_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */ -#define CONFIG_KW88F6281 1 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "${x_bootcmd_usb}; bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console=ttyS0,115200 " \ - CONFIG_MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -# ifdef CONFIG_BOARD_IS_OPENRD_BASE -# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -# else -# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */ -# endif -# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE -# define CONFIG_PHY_BASE_ADR 0x0 -# define PHY_NO "88E1121" -# else -# define CONFIG_PHY_BASE_ADR 0x8 -# define PHY_NO "88E1116" -# endif -#endif /* CONFIG_CMD_NET */ - -/* - * SATA Driver configuration - */ -#ifdef CONFIG_MVSATA_IDE -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /*CONFIG_MVSATA_IDE*/ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */ - -#endif /* _CONFIG_OPENRD_BASE_H */ diff --git a/include/configs/opos6uldev.h b/include/configs/opos6uldev.h deleted file mode 100644 index 309b471..0000000 --- a/include/configs/opos6uldev.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Armadeus Systems - * - * Configuration settings for the OPOS6ULDev board - */ - -#ifndef __OPOS6ULDEV_CONFIG_H -#define __OPOS6ULDEV_CONFIG_H - -#include "mx6_common.h" - -#ifdef CONFIG_SPL -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_REGULATOR -#endif -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 << 20) - -/* Miscellaneous configurable options */ -#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR - -/* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* USB */ -#ifdef CONFIG_USB_EHCI_MX6 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -/* Ethernet */ -#ifdef CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#endif - -/* LCD */ -#ifndef CONFIG_SPL_BUILD -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_SPLASH_SOURCE -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_MXS -#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif -#endif - -/* Environment is stored in the eMMC boot partition */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 -#define CONFIG_ENV_SIZE (10 * 1024) -#define CONFIG_ENV_OFFSET (1024 * 1024) /* 1 MB */ -#define CONFIG_ENV_OFFSET_REDUND (1536 * 1024) /* 512KB from CONFIG_ENV_OFFSET */ - -#define CONFIG_ENV_VERSION 100 -#define CONFIG_BOARD_NAME opos6ul -#define ACFG_CONSOLE_DEV ttymxc0 -#define CONFIG_SYS_AUTOLOAD "no" -#define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" -#define CONFIG_BOOTCOMMAND "run emmcboot" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ - "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ - "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ - "fdt_addr=0x88000000\0" \ - "fdt_high=0xffffffff\0" \ - "fdt_name=" __stringify(CONFIG_BOARD_NAME) "dev\0" \ - "initrd_high=0xffffffff\0" \ - "ip_dyn=yes\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "kernelimg=" __stringify(CONFIG_BOARD_NAME) "-linux.bin\0" \ - "videomode=video=ctfb:x:800,y:480,depth:18,pclk:33033,le:96,ri:96,up:20,lo:21,hs:64,vs:4,sync:0,vmode:0\0" \ - "check_env=if test -n ${flash_env_version}; " \ - "then env default env_version; " \ - "else env set flash_env_version ${env_version}; env save; " \ - "fi; " \ - "if itest ${flash_env_version} != ${env_version}; then " \ - "echo \"*** Warning - Environment version" \ - " change suggests: run flash_reset_env; reset\"; " \ - "env default flash_reset_env; " \ - "else exit; fi; \0" \ - "flash_reset_env=env default -f -a && saveenv && " \ - "echo Environment variables erased!\0" \ - "download_uboot_spl=tftpboot ${loadaddr} ${board_name}-u-boot.spl\0" \ - "flash_uboot_spl=" \ - "if mmc dev 0 1; then " \ - "setexpr sz ${filesize} / 0x200; " \ - "setexpr sz ${sz} + 1; " \ - "if mmc write ${loadaddr} 0x2 ${sz}; then " \ - "echo Flashing of U-boot SPL succeed; " \ - "else echo Flashing of U-boot SPL failed; " \ - "fi; " \ - "fi;\0" \ - "download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img\0" \ - "flash_uboot_img=" \ - "if mmc dev 0 1; then " \ - "setexpr sz ${filesize} / 0x200; " \ - "setexpr sz ${sz} + 1; " \ - "if mmc write ${loadaddr} 0x8a ${sz}; then " \ - "echo Flashing of U-boot image succeed; " \ - "else echo Flashing of U-boot image failed; " \ - "fi; " \ - "fi;\0" \ - "update_uboot=run download_uboot_spl flash_uboot_spl " \ - "download_uboot_img flash_uboot_img\0" \ - "download_kernel=tftpboot ${loadaddr} ${kernelimg}\0" \ - "flash_kernel=" \ - "if ext4write mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} ${filesize}; then " \ - "echo kernel update succeed; " \ - "else echo kernel update failed; " \ - "fi;\0" \ - "update_kernel=run download_kernel flash_kernel\0" \ - "download_dtb=tftpboot ${fdt_addr} imx6ul-${fdt_name}.dtb\0" \ - "flash_dtb=" \ - "if ext4write mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb ${filesize}; then " \ - "echo dtb update succeed; " \ - "else echo dtb update in failed; " \ - "fi;\0" \ - "update_dtb=run download_dtb flash_dtb\0" \ - "download_rootfs=tftpboot ${loadaddr} ${board_name}-rootfs.ext4\0" \ - "flash_rootfs=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0x40800 ${nbblocks}; then " \ - "echo Flashing of rootfs image succeed; " \ - "else echo Flashing of rootfs image failed; " \ - "fi; " \ - "fi;\0" \ - "update_rootfs=run download_rootfs flash_rootfs\0" \ - "flash_failsafe=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0x800 ${nbblocks}; then " \ - "echo Flashing of rootfs image in failsafe partition succeed; " \ - "else echo Flashing of rootfs image in failsafe partition failed; " \ - "fi; " \ - "fi;\0" \ - "update_failsafe=run download_rootfs flash_failsafe\0" \ - "download_userdata=tftpboot ${loadaddr} ${board_name}-user_data.ext4\0" \ - "flash_userdata=" \ - "if mmc dev 0 0; then " \ - "setexpr nbblocks ${filesize} / 0x200; " \ - "setexpr nbblocks ${nbblocks} + 1; " \ - "if mmc write ${loadaddr} 0 ${nbblocks}; then " \ - "echo Flashing of user_data image succeed; " \ - "else echo Flashing of user_data image failed; " \ - "fi; " \ - "fi;\0" \ - "update_userdata=run download_userdata flash_userdata; mmc rescan\0" \ - "erase_userdata=" \ - "if mmc dev 0 0; then " \ - "echo Erasing eMMC User Data partition, no way out...; " \ - "mw ${loadaddr} 0 0x200000; " \ - "mmc write ${loadaddr} 0 0x1000; " \ - "mmc write ${loadaddr} 0x800 0x1000; " \ - "mmc write ${loadaddr} 0x40800 0x1000; " \ - "mmc write ${loadaddr} 0x440800 0x1000; " \ - "fi;" \ - "mmc rescan\0" \ - "update_all=run update_rootfs update_uboot\0" \ - "initargs=setenv bootargs console=${consoledev},${baudrate} ${extrabootargs}\0" \ - "addipargs=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ - "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ - "addmmcargs=setenv bootargs ${bootargs} root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "emmcboot=run initargs; run addmmcargs; " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} /boot/${kernelimg} && " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} /boot/imx6ul-${fdt_name}.dtb && " \ - "bootz ${loadaddr} - ${fdt_addr};\0" \ - "emmcsafeboot=setenv mmcpart 1; setenv mmcroot /dev/mmcblk0p1 ro; run emmcboot;\0" \ - "addnfsargs=setenv bootargs ${bootargs} root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "nfsboot=run initargs; run addnfsargs addipargs; " \ - "nfs ${loadaddr} ${serverip}:${rootpath}/boot/${kernelimg} && " \ - "nfs ${fdt_addr} ${serverip}:${rootpath}/boot/imx6ul-${fdt_name}.dtb && " \ - "bootz ${loadaddr} - ${fdt_addr};\0" - -#endif /* __OPOS6ULDEV_CONFIG_H */ diff --git a/include/configs/origen.h b/include/configs/origen.h deleted file mode 100644 index 44561ac..0000000 --- a/include/configs/origen.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Samsung Electronics - * - * Configuration settings for the SAMSUNG ORIGEN (EXYNOS4210) board. - */ - -#ifndef __CONFIG_ORIGEN_H -#define __CONFIG_ORIGEN_H - -#include - -/* High Level Configuration Options */ -#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ -#define CONFIG_ORIGEN 1 /* working with ORIGEN*/ - -/* ORIGEN has 4 bank of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN - -/* select serial console configuration */ - -/* Console configuration */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* MMC SPL */ -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x40007000\0" \ - "rdaddr=0x48000000\0" \ - "kerneladdr=0x40007000\0" \ - "ramdiskaddr=0x48000000\0" \ - "console=ttySAC2,115200n8\0" \ - "mmcdev=0\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "fi; " \ - "fi;" \ - "load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " - -#define CONFIG_CLK_1000_400_200 - -/* MIU (Memory Interleaving Unit) */ -#define CONFIG_MIU_2BIT_21_7_INTERLEAVED - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ -#define RESERVE_BLOCK_SIZE (512) -#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) - -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 - -/* U-Boot copy size from boot Media to DRAM.*/ -#define COPY_BL2_SIZE 0x80000 -#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) -#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) - -#endif /* __CONFIG_H */ diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h deleted file mode 100644 index 4efef89..0000000 --- a/include/configs/ot1200.h +++ /dev/null @@ -1,103 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. - * Copyright (C) 2014 Bachmann electronic GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* UART Configs */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* SF Configs */ - -/* IO expander */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x20 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x20, 16} } - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* OCOTP Configs */ -#define CONFIG_IMX_OTP -#define IMX_OTP_BASE OCOTP_BASE_ADDR -#define IMX_OTP_ADDR_MAX 0x7F -#define IMX_OTP_DATA_ERROR_VAL 0xBADABADA -#define IMX_OTPWRITE_ENABLED - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* - * SATA Configs - */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* SPL */ -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x5 -#define CONFIG_PHY_SMSC - -#ifndef CONFIG_SPL -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_BUS 1 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 -#endif - -/* Thermal support */ -#define CONFIG_IMX_THERMAL - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (64 * 1024) /* 64 kb */ -#define CONFIG_ENV_OFFSET (1024 * 1024) -/* M25P16 has an erase size of 64 KiB */ -#define CONFIG_ENV_SECT_SIZE (64 * 1024) - -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_BOOTP_BOOTFILE - -#endif /* __CONFIG_H */ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h deleted file mode 100644 index 1481d68..0000000 --- a/include/configs/p1_p2_rdb_pc.h +++ /dev/null @@ -1,889 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2010-2011 Freescale Semiconductor, Inc. - */ - -/* - * QorIQ RDB boards configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#if defined(CONFIG_TARGET_P1020MBG) -#define CONFIG_BOARDNAME "P1020MBG-PC" -#define CONFIG_VSC7385_ENET -#define CONFIG_SLIC -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0xe4 -#define __SW_BOOT_SD 0x54 -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - -#if defined(CONFIG_TARGET_P1020UTM) -#define CONFIG_BOARDNAME "P1020UTM-PC" -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0xe0 -#define __SW_BOOT_SD 0x50 -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - -#if defined(CONFIG_TARGET_P1020RDB_PC) -#define CONFIG_BOARDNAME "P1020RDB-PC" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_VSC7385_ENET -#define CONFIG_SLIC -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0x5c -#define __SW_BOOT_SPI 0x1c -#define __SW_BOOT_SD 0x9c -#define __SW_BOOT_NAND 0xec -#define __SW_BOOT_PCIE 0x6c -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - -/* - * P1020RDB-PD board has user selectable switches for evaluating different - * frequency and boot options for the P1020 device. The table that - * follow describe the available options. The front six binary number was in - * accordance with SW3[1:6]. - * 111101 533 533 267 667 NOR Core0 boot; Core1 hold-off - * 101101 667 667 333 667 NOR Core0 boot; Core1 hold-off - * 011001 800 800 400 667 NOR Core0 boot; Core1 hold-off - * 001001 800 800 400 667 SD/MMC Core0 boot; Core1 hold-off - * 001101 800 800 400 667 SPI Core0 boot; Core1 hold-off - * 010001 800 800 400 667 NAND Core0 boot; Core1 hold-off - * 011101 800 800 400 667 PCIe-2 Core0 boot; Core1 hold-off - */ -#if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_BOARDNAME "P1020RDB-PD" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_VSC7385_ENET -#define CONFIG_SLIC -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0x64 -#define __SW_BOOT_SPI 0x34 -#define __SW_BOOT_SD 0x24 -#define __SW_BOOT_NAND 0x44 -#define __SW_BOOT_PCIE 0x74 -#define CONFIG_SYS_L2_SIZE (256 << 10) -/* - * Dynamic MTD Partition support with mtdparts - */ -#endif - -#if defined(CONFIG_TARGET_P1021RDB) -#define CONFIG_BOARDNAME "P1021RDB-PC" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_VSC7385_ENET -#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of - addresses in the LBC */ -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0x5c -#define __SW_BOOT_SPI 0x1c -#define __SW_BOOT_SD 0x9c -#define __SW_BOOT_NAND 0xec -#define __SW_BOOT_PCIE 0x6c -#define CONFIG_SYS_L2_SIZE (256 << 10) -/* - * Dynamic MTD Partition support with mtdparts - */ -#endif - -#if defined(CONFIG_TARGET_P1024RDB) -#define CONFIG_BOARDNAME "P1024RDB" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SLIC -#define __SW_BOOT_MASK 0xf3 -#define __SW_BOOT_NOR 0x00 -#define __SW_BOOT_SPI 0x08 -#define __SW_BOOT_SD 0x04 -#define __SW_BOOT_NAND 0x0c -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - -#if defined(CONFIG_TARGET_P1025RDB) -#define CONFIG_BOARDNAME "P1025RDB" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_SLIC - -#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of - addresses in the LBC */ -#define __SW_BOOT_MASK 0xf3 -#define __SW_BOOT_NOR 0x00 -#define __SW_BOOT_SPI 0x08 -#define __SW_BOOT_SD 0x04 -#define __SW_BOOT_NAND 0x0c -#define CONFIG_SYS_L2_SIZE (256 << 10) -#endif - -#if defined(CONFIG_TARGET_P2020RDB) -#define CONFIG_BOARDNAME "P2020RDB-PC" -#define CONFIG_NAND_FSL_ELBC -#define CONFIG_VSC7385_ENET -#define __SW_BOOT_MASK 0x03 -#define __SW_BOOT_NOR 0xc8 -#define __SW_BOOT_SPI 0x28 -#define __SW_BOOT_SD 0x68 /* or 0x18 */ -#define __SW_BOOT_NAND 0xe8 -#define __SW_BOOT_PCIE 0xa8 -#define CONFIG_SYS_L2_SIZE (512 << 10) -/* - * Dynamic MTD Partition support with mtdparts - */ -#endif - -#ifdef CONFIG_SDCARD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) -#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_SPIFLASH -#define CONFIG_SPL_SPI_FLASH_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_SPL_MAX_SIZE (128 * 1024) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) -#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10) -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SPL_COMMON_INIT_DDR -#endif -#endif - -#ifdef CONFIG_NAND -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_NAND_INIT -#define CONFIG_SPL_COMMON_INIT_DDR -#define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_TPL_TEXT_BASE 0xf8f81000 -#define CONFIG_SYS_MPC85XX_NO_RESETVEC -#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) -#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SPL_INIT_MINIMAL -#define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_SIZE 4096 -#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000 -#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) -#endif /* not CONFIG_TPL_BUILD */ - -#define CONFIG_SPL_PAD_TO 0x20000 -#define CONFIG_TPL_PAD_TO 0x20000 -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#endif - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#ifndef CONFIG_SYS_MONITOR_BASE -#ifdef CONFIG_TPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE -#elif defined(CONFIG_SPL_BUILD) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif -#endif - -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_LBA48 - -#if defined(CONFIG_TARGET_P2020RDB) -#define CONFIG_SYS_CLK_FREQ 100000000 -#else -#define CONFIG_SYS_CLK_FREQ 66666666 -#endif -#define CONFIG_DDR_CLK_FREQ 66666666 - -#define CONFIG_HWCONFIG -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE -#define CONFIG_BTB - -#define CONFIG_ENABLE_36BIT_PHYS - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_ADDR_MAP 1 -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ -#endif - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x1fffffff - -#define CONFIG_SYS_CCSRBAR 0xffe00000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k - SPL code*/ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_SYS_DDR_RAW_TIMING -#define CONFIG_DDR_SPD -#define CONFIG_SYS_SPD_BUS_NUM 1 -#define SPD_EEPROM_ADDRESS 0x52 - -#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 -#else -#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#endif -#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19)) -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 - -/* Default settings for DDR3 */ -#ifndef CONFIG_TARGET_P2020RDB -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f -#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000 - -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 - -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x04401050 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846 -#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF -#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000 -#define CONFIG_SYS_DDR_MODE_1 0x40461520 -#define CONFIG_SYS_DDR_MODE_2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x0C300000 -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Memory map - * - * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable - * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3) - * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1 - * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable - * (early boot only) - * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 - * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 - * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 - * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 - * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable - * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable - * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable - */ - -/* - * Local Bus Definitions - */ -#if (defined(CONFIG_TARGET_P1020MBG) || defined(CONFIG_TARGET_P1020RDB_PD)) -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ -#define CONFIG_SYS_FLASH_BASE 0xec000000 -#elif defined(CONFIG_TARGET_P1020UTM) -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ -#define CONFIG_SYS_FLASH_BASE 0xee000000 -#else -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */ -#define CONFIG_SYS_FLASH_BASE 0xef000000 -#endif - -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) -#else -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE -#endif - -#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ - | BR_PS_16 | BR_V) - -#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 - -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Nand Flash */ -#ifdef CONFIG_NAND_FSL_ELBC -#define CONFIG_SYS_NAND_BASE 0xff800000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull -#else -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#endif - -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#if defined(CONFIG_TARGET_P1020RDB_PD) -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#else -#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) -#endif - -#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ - | (2< - */ - -#ifndef _P2371_0000_H -#define _P2371_0000_H - -#include - -#include "tegra210-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-0000" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* _P2371_0000_H */ diff --git a/include/configs/p2371-2180.h b/include/configs/p2371-2180.h deleted file mode 100644 index 7205a17..0000000 --- a/include/configs/p2371-2180.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _P2371_2180_H -#define _P2371_2180_H - -#include - -#include "tegra210-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2371-2180" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -/* Crystal is 38.4MHz. clk_m runs at half that rate */ -#define COUNTER_FREQUENCY 19200000 - -#endif /* _P2371_2180_H */ diff --git a/include/configs/p2571.h b/include/configs/p2571.h deleted file mode 100644 index 02db6bb..0000000 --- a/include/configs/p2571.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _P2571_H -#define _P2571_H - -#include - -#include "tegra210-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571" - -/* Board-specific serial config */ -#define CONFIG_SERIAL_MULTI -#define CONFIG_TEGRA_ENABLE_UARTA - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* _P2571_H */ diff --git a/include/configs/p2771-0000.h b/include/configs/p2771-0000.h deleted file mode 100644 index e546c1d..0000000 --- a/include/configs/p2771-0000.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2013-2016, NVIDIA CORPORATION. - */ - -#ifndef _P2771_0000_H -#define _P2771_0000_H - -#include - -#include "tegra186-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000" - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) - -#define BOARD_EXTRA_ENV_SETTINGS \ - "calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \ - "ramdisk_addr_r\0" \ - "kernel_addr_r_align=00200000\0" \ - "kernel_addr_r_offset=00080000\0" \ - "kernel_addr_r_size=02000000\0" \ - "kernel_addr_r_aliases=loadaddr\0" \ - "fdt_addr_r_align=00200000\0" \ - "fdt_addr_r_offset=00000000\0" \ - "fdt_addr_r_size=00200000\0" \ - "scriptaddr_align=00200000\0" \ - "scriptaddr_offset=00000000\0" \ - "scriptaddr_size=00200000\0" \ - "pxefile_addr_r_align=00200000\0" \ - "pxefile_addr_r_offset=00000000\0" \ - "pxefile_addr_r_size=00200000\0" \ - "ramdisk_addr_r_align=00200000\0" \ - "ramdisk_addr_r_offset=00000000\0" \ - "ramdisk_addr_r_size=02000000\0" - -#include "tegra-common-post.h" - -/* Crystal is 38.4MHz. clk_m runs at half that rate */ -#define COUNTER_FREQUENCY 19200000 - -#endif diff --git a/include/configs/paz00.h b/include/configs/paz00.h deleted file mode 100644 index b76958c..0000000 --- a/include/configs/paz00.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved. - * - * See file CREDITS for list of people who contributed to this - * project. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_PAZ00 - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h deleted file mode 100644 index 943fca9..0000000 --- a/include/configs/pcl063.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Collabora Ltd. - * - * Based on include/configs/xpress.h: - * Copyright (C) 2015-2016 Stefan Roese - */ -#ifndef __PCL063_H -#define __PCL063_H - -#include -#include "mx6_common.h" - -/* SPL options */ -#include "imx6_spl.h" - -/* - * There is a bug in some i.MX6UL processors that results in the initial - * portion of OCRAM being unavailable when booting from (at least) an SD - * card. - * - * Tweak the SPL text base address to avoid this. - */ - -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - -/* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* MMC Configs */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_256M - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_ENV_SIZE (16 << 10) -#define CONFIG_ENV_OFFSET (512 << 10) - -/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - -#define CONFIG_IMX_THERMAL - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200n8\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "fdt_addr_r=0x82000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=0x81000000\0" \ - "pxefile_addr_r=0x87100000\0" \ - "ramdisk_addr_r=0x82100000\0" \ - "scriptaddr=0x87000000\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(UBIFS, ubifs, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#endif /* __PCL063_H */ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h deleted file mode 100644 index 650caaa..0000000 --- a/include/configs/pcl063_ull.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Board configuration file for Phytec phyBOARD-i.MX6ULL-Segin SBC - * Copyright (C) 2019 Parthiban Nallathambi - * - * Based on include/configs/xpress.h: - * Copyright (C) 2015-2016 Stefan Roese - */ -#ifndef __PCL063_ULL_H -#define __PCL063_ULL_H - -#include -#include "mx6_common.h" - -/* SPL options */ -#include "imx6_spl.h" - -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M) - -/* Environment settings */ -#define CONFIG_ENV_SIZE (0x4000) -#define CONFIG_ENV_OFFSET (0x80000) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) - -/* Environment in SD */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 -#define MMC_ROOTFS_DEV 0 -#define MMC_ROOTFS_PART 2 - -/* Console configs */ -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* MMC Configs */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT - -/* I2C configs */ -#ifdef CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_SPEED 100000 -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE SZ_256M - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - -#define CONFIG_IMX_THERMAL - -#define ENV_MMC \ - "mmcdev=" __stringify(MMC_ROOTFS_DEV) "\0" \ - "mmcpart=" __stringify(MMC_ROOTFS_PART) "\0" \ - "fitpart=1\0" \ - "bootdelay=3\0" \ - "silent=1\0" \ - "optargs=rw rootwait\0" \ - "mmcautodetect=yes\0" \ - "mmcrootfstype=ext4\0" \ - "mmcfit_name=fitImage\0" \ - "mmcloadfit=fatload mmc ${mmcdev}:${fitpart} ${fit_addr} " \ - "${mmcfit_name}\0" \ - "mmcargs=setenv bootargs " \ - "root=/dev/mmcblk${mmcdev}p${mmcpart} ${optargs} " \ - "console=${console} rootfstype=${mmcrootfstype}\0" \ - "mmc_mmc_fit=run mmcloadfit;run mmcargs addcon; bootm ${fit_addr}\0" \ - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "console=ttymxc0,115200n8\0" \ - "addcon=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ - "fit_addr=0x82000000\0" \ - ENV_MMC - -#define CONFIG_BOOTCOMMAND "run mmc_mmc_fit" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(DHCP, dhcp, na) - -#include - -#endif /* __PCL063_ULL_H */ diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h deleted file mode 100644 index fdbc075..0000000 --- a/include/configs/pcm051.h +++ /dev/null @@ -1,133 +0,0 @@ -/* - * pcm051.h - * - * Phytec phyCORE-AM335x (pcm051) boards information header - * - * Copyright (C) 2013 Lemonage Software GmbH - * Author Lars Poeschel - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_PCM051_H -#define __CONFIG_PCM051_H - -#include - -#define CONFIG_MACH_TYPE MACH_TYPE_PCM051 - -/* set to negative value for no autoboot */ -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance"; "\ - "setenv bootpart " #instance":2 ; "\ - "run mmcboot\0" - -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel "=" \ - "run nandboot\0" - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ - func(MMC, mmc, 1) \ - func(LEGACY_MMC, legacy_mmc, 1) \ - func(NAND, nand, 0) - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd" - -#include - -#include -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - "bootfile=uImage\0" \ - "fdtfile=am335x-wega-rdk.dtb\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ - "ramrootfstype=ext2\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootscript=load mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc${mmcdev} ...; " \ - "source ${loadaddr}\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run args_mmc; " \ - "bootm ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootm ${loadaddr}\0" \ - BOOTENV - -/* Clock Defines */ -#define V_OSCK 25000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* - * memtest works on 8 MB in DRAM after skipping 32MB from - * start addr of ram disk - */ -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + (64 << 20)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + (8 * 1024 * 1024)) - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ -#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ -#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ -#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ -#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ -#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ - -/* I2C Configuration */ -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -#define CONFIG_SYS_BAUDRATE_TABLE { 110, 300, 600, 1200, 2400, \ -4800, 9600, 14400, 19200, 28800, 38400, 56000, 57600, 115200 } - -/* CPU */ - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#endif - -/* - * USB configuration - */ -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -#define CONFIG_PHY_SMSC - -#endif /* ! __CONFIG_PCM051_H */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h deleted file mode 100644 index fb8f3c8..0000000 --- a/include/configs/pcm052.h +++ /dev/null @@ -1,185 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Configuration settings for the phytec PCM-052 SoM. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -/* QSPI Configs*/ -#ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE (SZ_16M) -#define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SYS_FSL_QSPI_LE -#endif - - -#define CONFIG_LOADADDR 0x82000000 - -/* We boot from the gfxRAM area of the OCRAM. */ -#define CONFIG_BOARD_SIZE_LIMIT 520192 - -/* if no target-specific extra environment settings were defined by the - target, define an empty one */ -#ifndef PCM052_EXTRA_ENV_SETTINGS -#define PCM052_EXTRA_ENV_SETTINGS -#endif - -/* if no target-specific boot command was defined by the target, - define an empty one */ -#ifndef PCM052_BOOTCOMMAND -#define PCM052_BOOTCOMMAND -#endif - -/* if no target-specific extra environment settings were defined by the - target, define an empty one */ -#ifndef PCM052_NET_INIT -#define PCM052_NET_INIT -#endif - -/* boot command, including the target-defined one if any */ -#define CONFIG_BOOTCOMMAND PCM052_BOOTCOMMAND "run bootcmd_nand" - -/* Extra env settings (including the target-defined ones if any) */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - PCM052_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "blimg_file=u-boot.vyb\0" \ - "blimg_addr=0x81000000\0" \ - "kernel_file=zImage\0" \ - "kernel_addr=0x82000000\0" \ - "fdt_file=zImage.dtb\0" \ - "fdt_addr=0x81000000\0" \ - "ram_file=uRamdisk\0" \ - "ram_addr=0x83000000\0" \ - "filesys=rootfs.ubifs\0" \ - "sys_addr=0x81000000\0" \ - "tftploc=/path/to/tftp/directory/\0" \ - "nfs_root=/path/to/nfs/root\0" \ - "tftptimeout=1000\0" \ - "tftptimeoutcountmax=1000000\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "bootargs_base=setenv bootargs rw " \ - " mem=" __stringify(CONFIG_PCM052_DDR_SIZE) "M " \ - "console=ttyLP1,115200n8\0" \ - "bootargs_sd=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 rootwait\0" \ - "bootargs_net=setenv bootargs ${bootargs} root=/dev/nfs ip=dhcp " \ - "nfsroot=${serverip}:${nfs_root},v3,tcp\0" \ - "bootargs_nand=setenv bootargs ${bootargs} " \ - "ubi.mtd=5 rootfstype=ubifs root=ubi0:rootfs\0" \ - "bootargs_ram=setenv bootargs ${bootargs} " \ - "root=/dev/ram rw initrd=${ram_addr}\0" \ - "bootargs_mtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "bootcmd_sd=run bootargs_base bootargs_sd bootargs_mtd; " \ - "fatload mmc 0:1 ${kernel_addr} ${kernel_file}; " \ - "fatload mmc 0:1 ${fdt_addr} ${fdt_file}; " \ - "bootz ${kernel_addr} - ${fdt_addr}\0" \ - "bootcmd_net=run bootargs_base bootargs_net bootargs_mtd; " \ - "tftpboot ${kernel_addr} ${tftpdir}${kernel_file}; " \ - "tftpboot ${fdt_addr} ${tftpdir}${fdt_file}; " \ - "bootz ${kernel_addr} - ${fdt_addr}\0" \ - "bootcmd_nand=run bootargs_base bootargs_nand bootargs_mtd; " \ - "nand read ${fdt_addr} dtb; " \ - "nand read ${kernel_addr} kernel; " \ - "bootz ${kernel_addr} - ${fdt_addr}\0" \ - "bootcmd_ram=run bootargs_base bootargs_ram bootargs_mtd; " \ - "nand read ${fdt_addr} dtb; " \ - "nand read ${kernel_addr} kernel; " \ - "nand read ${ram_addr} root; " \ - "bootz ${kernel_addr} ${ram_addr} ${fdt_addr}\0" \ - "update_bootloader_from_tftp=" PCM052_NET_INIT \ - "if tftp ${blimg_addr} "\ - "${tftpdir}${blimg_file}; then " \ - "mtdparts default; " \ - "nand erase.part bootloader; " \ - "nand write ${blimg_addr} bootloader ${filesize}; fi\0" \ - "update_kernel_from_sd=if fatload mmc 0:2 ${kernel_addr} " \ - "${kernel_file}; " \ - "then mtdparts default; " \ - "nand erase.part kernel; " \ - "nand write ${kernel_addr} kernel ${filesize}; " \ - "if fatload mmc 0:2 ${fdt_addr} ${fdt_file}; then " \ - "nand erase.part dtb; " \ - "nand write ${fdt_addr} dtb ${filesize}; fi\0" \ - "update_kernel_from_tftp=" PCM052_NET_INIT \ - "if tftp ${fdt_addr} ${tftpdir}${fdt_file}; " \ - "then setenv fdtsize ${filesize}; " \ - "if tftp ${kernel_addr} ${tftpdir}${kernel_file}; then " \ - "mtdparts default; " \ - "nand erase.part dtb; " \ - "nand write ${fdt_addr} dtb ${fdtsize}; " \ - "nand erase.part kernel; " \ - "nand write ${kernel_addr} kernel ${filesize}; fi; fi\0" \ - "update_rootfs_from_tftp=" PCM052_NET_INIT \ - "if tftp ${sys_addr} ${tftpdir}${filesys}; " \ - "then mtdparts default; " \ - "nand erase.part root; " \ - "ubi part root; " \ - "ubi create rootfs; " \ - "ubi write ${sys_addr} rootfs ${filesize}; fi\0" \ - "update_ramdisk_from_tftp=" PCM052_NET_INIT \ - "if tftp ${ram_addr} ${tftpdir}${ram_file}; " \ - "then mtdparts default; " \ - "nand erase.part root; " \ - "nand write ${ram_addr} root ${filesize}; fi\0" - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x80010000 -#define CONFIG_SYS_MEMTEST_END 0x87C00000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Physical memory map */ -#define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (CONFIG_PCM052_DDR_SIZE * SZ_1M) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_SIZE (SZ_8K) - -#define CONFIG_ENV_OFFSET (12 * SZ_64K) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SECT_SIZE (SZ_128K) -#define CONFIG_ENV_SIZE (SZ_8K) -#define CONFIG_ENV_OFFSET 0xA0000 -#define CONFIG_ENV_SIZE_REDUND (SZ_8K) -#define CONFIG_ENV_OFFSET_REDUND 0xC0000 -#endif - -#endif diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h deleted file mode 100644 index 855bc44..0000000 --- a/include/configs/pcm058.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic - */ - - -#ifndef __PCM058_CONFIG_H -#define __PCM058_CONFIG_H - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#include "mx6_common.h" - -/* Thermal */ -#define CONFIG_IMX_THERMAL - -/* Serial */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" - -#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) - -/* Early setup */ - - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 3 - -/* SPI Flash */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#ifndef CONFIG_SPL_BUILD -/* Enable NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Filesystem support */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -/* Environment organization */ -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_OFFSET (1024 * SZ_1K) -#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET (0x1E0000) -#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) -#endif - -#endif diff --git a/include/configs/pdu001.h b/include/configs/pdu001.h deleted file mode 100644 index e4c2872..0000000 --- a/include/configs/pdu001.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * pdu001.h - * - * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/ - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_PDU001_H -#define __CONFIG_PDU001_H - -#include - -/* Using 32K of volatile storage for environment */ -#define CONFIG_ENV_SIZE 0x4000 - -#define MACH_TYPE_PDU001 5075 -#define CONFIG_MACH_TYPE MACH_TYPE_PDU001 -#define CONFIG_BOARD_LATE_INIT - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#if CONFIG_CONS_INDEX == 1 - #define CONSOLE_DEV "ttyO0" -#elif CONFIG_CONS_INDEX == 2 - #define CONSOLE_DEV "ttyO1" -#elif CONFIG_CONS_INDEX == 3 - #define CONSOLE_DEV "ttyO2" -#elif CONFIG_CONS_INDEX == 4 - #define CONSOLE_DEV "ttyO3" -#elif CONFIG_CONS_INDEX == 5 - #define CONSOLE_DEV "ttyO4" -#elif CONFIG_CONS_INDEX == 6 - #define CONSOLE_DEV "ttyO5" -#endif - -#define CONFIG_BOOTCOMMAND \ - "run eval_boot_device;" \ - "setenv bootargs console=${console} " \ - "vt.global_cursor_default=0 " \ - "root=/dev/mmcblk${mmc_boot}p${root_fs_partition} " \ - "rootfstype=ext4 " \ - "rootwait " \ - "rootdelay=1;" \ - "fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \ - "fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \ - "bootz ${loadaddr} - ${fdtaddr}" - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "fdtfile=am335x-pdu001.dtb\0" \ - "bootfile=zImage\0" \ - "console=" CONSOLE_DEV ",115200n8\0" \ - "root_fs_partition=2\0" \ - "eval_boot_device=" \ - "if test $boot_device = emmc; then " \ - "setenv mmc_boot 0;" \ - "elif test $boot_device = sdcard; then " \ - "setenv mmc_boot 1;" \ - "else " \ - "echo Bootdevice is neither MMC0 nor MMC1;" \ - "reset;" \ - "fi;" \ - "\0" -#endif - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_COM1 UART0_BASE -#define CONFIG_SYS_NS16550_COM2 UART1_BASE -#define CONFIG_SYS_NS16550_COM3 UART2_BASE -#define CONFIG_SYS_NS16550_COM4 UART3_BASE -#define CONFIG_SYS_NS16550_COM5 UART4_BASE -#define CONFIG_SYS_NS16550_COM6 UART5_BASE -#define CONFIG_BAUDRATE 115200 - -#endif /* ! __CONFIG_PDU001_H */ diff --git a/include/configs/peach-pi.h b/include/configs/peach-pi.h deleted file mode 100644 index a732e06..0000000 --- a/include/configs/peach-pi.h +++ /dev/null @@ -1,41 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Samsung Electronics - * - * Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board. - */ - -#ifndef __CONFIG_PEACH_PI_H -#define __CONFIG_PEACH_PI_H - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x22000000\0" \ - "fdt_addr_r=0x23000000\0" \ - "ramdisk_addr_r=0x23300000\0" \ - "scriptaddr=0x30000000\0" \ - "pxefile_addr_r=0x31000000\0" - -#include -#include -#include - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* select serial console configuration */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -/* Display */ -#ifdef CONFIG_LCD -#define CONFIG_EXYNOS_FB -#define CONFIG_EXYNOS_DP -#define LCD_BPP LCD_COLOR16 -#endif - -#define CONFIG_POWER_TPS65090_EC - -/* DRAM Memory Banks */ -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ - -#endif /* __CONFIG_PEACH_PI_H */ diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h deleted file mode 100644 index 6c5960c..0000000 --- a/include/configs/peach-pit.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board. - */ - -#ifndef __CONFIG_PEACH_PIT_H -#define __CONFIG_PEACH_PIT_H - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x22000000\0" \ - "fdt_addr_r=0x23000000\0" \ - "ramdisk_addr_r=0x23300000\0" \ - "scriptaddr=0x30000000\0" \ - "pxefile_addr_r=0x31000000\0" - -#include -#include -#include - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* select serial console configuration */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -/* DRAM Memory Banks */ -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ - -#endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/pengwyn.h b/include/configs/pengwyn.h deleted file mode 100644 index a535d0c..0000000 --- a/include/configs/pengwyn.h +++ /dev/null @@ -1,170 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * pengwyn.h - * - * Copyright (C) 2013 Lothar Felten - * - * based on am335x_evm.h, Copyright (C) 2011 Texas Instruments Inc. - */ - -#ifndef __CONFIG_PENGWYN_H -#define __CONFIG_PENGWYN_H - - -#include - -/* Clock Defines */ -#define V_OSCK 24000000 -#define V_SCLK V_OSCK - -/* set env size */ -#define CONFIG_ENV_SIZE 0x4000 - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "fdtfile=am335x-pengwyn.dtb\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "rootpath=/export/rootfs\0" \ - "nfsopts=nolock\0" \ - "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ - "::off\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ - "loadfdt=load mmc ${bootpart} ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "mmcloados=run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr};\0" \ - "mmcboot=mmc dev ${mmcdev}; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loadimage; then " \ - "run loadfdt;" \ - "run mmcloados;" \ - "fi;" \ - "fi;\0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "tftp ${loadaddr} ${bootfile}; " \ - "tftp ${fdtaddr} ${fdtfile}; " \ - "run netargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ - "nandrootfstype=ubifs rootwait=1\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${fdtaddr} u-boot-spl-os; " \ - "nand read ${loadaddr} kernel; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" -#endif - -#define CONFIG_BOOTCOMMAND \ - "run mmcboot;" \ - "run nandboot;" - -/* NS16550 Configuration: primary UART via FTDI */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_ENV_EEPROM_IS_ON_I2C -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* SPL */ - -/* NAND support */ - -/* NAND Configuration. */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 4096 -#define CONFIG_SYS_NAND_OOBSIZE 224 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*4096) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ - 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,\ - 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49,\ - 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65,\ - 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81,\ - 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97,\ - 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113,\ - 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133,\ - 134, 135, 136, 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153,\ - 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173,\ - 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193,\ - 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209} - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 26 -#define CONFIG_SYS_NAND_ECCSTEPS 8 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW -/* END NAND Configuration. */ - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -/* #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 - -/* Size must be a multiple of Nand erase size (524288 b) */ -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -/* NAND: SPL falcon mode configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x280000 -#endif - -/* - * USB configuration. We enable MUSB support, both for host and for - * gadget. We set USB0 as peripheral and USB1 as host, based on the - * board schematic and physical port wired to each. Then for host we - * add mass storage support. - */ -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -/* Network */ -#define CONFIG_PHY_RESET 1 -#define CONFIG_PHY_NATSEMI -#define CONFIG_PHY_REALTEK - -#endif /* ! __CONFIG_PENGWYN_H */ diff --git a/include/configs/pepper.h b/include/configs/pepper.h deleted file mode 100644 index 662fce3..0000000 --- a/include/configs/pepper.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Gumstix, Inc. - http://www.gumstix.com/ - */ - -#ifndef __CONFIG_PEPPER_H -#define __CONFIG_PEPPER_H - -#include - -/* Clock defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - -/* Mach type */ -#define CONFIG_MACH_TYPE MACH_TYPE_PEPPER - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "fdtfile=am335x-pepper.dtb\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=load mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t ${loadaddr} ${filesize}\0" \ - "mmcload=load mmc ${mmcdev}:2 ${loadaddr} ${bootdir}/${bootfile}; " \ - "load mmc ${mmcdev}:2 ${fdtaddr} ${bootdir}/${fdtfile}\0" \ - "loaduimage=fatload mmc ${mmcdev}:1 ${loadaddr} uImage\0" \ - "uimageboot=echo Booting from mmc${mmcdev} ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - "ubiboot=echo Booting from nand (ubifs) ...; " \ - "run ubiargs; run ubiload; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run mmcload; then " \ - "run mmcboot;" \ - "fi;" \ - "if run loaduimage; then " \ - "run uimageboot;" \ - "fi;" \ - "fi;" \ - -/* Serial console configuration */ -#define CONFIG_SYS_NS16550_COM1 0x44e09000 - -/* Ethernet support */ -#define CONFIG_PHY_RESET_DELAY 1000 - -/* SPL */ - -#endif /* __CONFIG_PEPPER_H */ diff --git a/include/configs/pfla02.h b/include/configs/pfla02.h deleted file mode 100644 index 8731d89..0000000 --- a/include/configs/pfla02.h +++ /dev/null @@ -1,148 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic - */ - - -#ifndef __PCM058_CONFIG_H -#define __PCM058_CONFIG_H - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -#include "mx6_common.h" - -/* Thermal */ -#define CONFIG_IMX_THERMAL - -/* Serial */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" - -/* Early setup */ - - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - -/* Ethernet */ -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 3 - -/* SPI Flash */ - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 0 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_CMD_NAND -/* Enable NAND support */ -#define CONFIG_CMD_NAND_TRIMFFS -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Filesystem support */ - -/* Various command support */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* Environment organization */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_OFFSET (1024 * SZ_1K) -#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_OFFSET (0x1E0000) -#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K) -#endif - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \ - "addmtd=run mtdnand;run mtdspi;" \ - "setenv bootargs ${bootargs} ${mtdparts}\0" \ - "mtdnand=setenv mtdparts mtdparts=gpmi-nand:" \ - "40m(Kernels),400m(root),-(nand)\0" \ - "mtdspi=setenv mtdparts ${mtdparts}" \ - "';spi2.0:1024k(bootloader)," \ - "64k(env1),64k(env2),-(rescue)'\0" \ - "bootcmd=if test -n ${rescue};" \ - "then run swupdate;fi;run nandboot;run swupdate\0" \ - "bootfile=uImage\0" \ - "bootimage=uImage\0" \ - "console=ttymxc3\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_file=pfla02.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "miscargs=panic=1 quiet\0" \ - "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \ - "mmcboot=if run mmcload;then " \ - "run mmcargs addcons addmisc;" \ - "bootm;fi\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p1\0" \ - "ubiroot=1\0" \ - "nandargs=setenv bootargs ubi.mtd=1 " \ - "root=ubi0:rootfs${ubiroot} rootfstype=ubifs\0" \ - "nandboot=run mtdnand;ubi part nand0,0;" \ - "ubi readvol ${kernel_addr_r} kernel${ubiroot};" \ - "run nandargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \ - "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \ - "run nfsargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "net_nfs_fit=tftp ${kernel_addr_r} ${board_name}/${fitfile};" \ - "run nfsargs addip addcons addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs" \ - " nfsroot=${serverip}:${nfsroot},v3 panic=1\0" \ - "swupdate=setenv bootargs root=/dev/ram;" \ - "run addip addcons addmtd addmisc;" \ - "sf probe;" \ - "sf read ${kernel_addr_r} 120000 600000;" \ - "sf read 14000000 730000 800000;" \ - "bootm ${kernel_addr_r} 14000000\0" - -#endif diff --git a/include/configs/phycore_am335x_r2.h b/include/configs/phycore_am335x_r2.h deleted file mode 100644 index ca28b6f..0000000 --- a/include/configs/phycore_am335x_r2.h +++ /dev/null @@ -1,127 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * phycore_am335x_r2.h - * - * Phytec phyCORE-AM335x R2 (PCL060 / PCM060) boards information header - * - * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ - * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH - * Copyright (C) 2019 DENX Software Engineering GmbH - */ - -#ifndef __CONFIG_PHYCORE_AM335x_R2_H -#define __CONFIG_PHYCORE_AM335x_R2_H - -#include - -#define CONFIG_MACH_TYPE MACH_TYPE_SBC_PHYCORE_AM335X -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 - -#ifdef CONFIG_NAND -#define NANDARGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nandargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype}\0" \ - "nandroot=ubi0:root ubi.mtd=NAND.UBI\0" \ - "nandrootfstype=ubifs rootwait rw fsck.repair=yes\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "ubi part NAND.UBI; " \ - "ubi readvol ${fdtaddr} oftree; " \ - "ubi readvol ${loadaddr} kernel; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" - -#else -#define NANDARGS "" -#endif - -/* set to negative value for no autoboot */ -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance "; "\ - "setenv bootpart " #instance ":1 ; "\ - "setenv rootpart " #instance ":2 ; "\ - "run mmcboot\0" - -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "run nandboot\0" - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ - func(MMC, mmc, 1) \ - func(LEGACY_MMC, legacy_mmc, 1) \ - func(NAND, nand, 0) - -#include -#include -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_MMC_TI_ARGS \ - DEFAULT_LINUX_BOOT_ENV \ - "bootfile=zImage\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "console=ttyS0,115200\0" \ - "optargs=\0" \ - "mmcrootfstype=ext2 rootwait\0" \ - "finduuid=part uuid mmc ${rootpart} uuid\0" \ - "boot_fit=0\0" \ - NANDARGS \ - BOOTENV - -/* Clock Macros */ -#define V_OSCK 25000000 /* Clock output from T2 */ -#define V_SCLK V_OSCK - -#define CONFIG_POWER_TPS65910 - -#ifdef CONFIG_NAND -/* NAND: device related configs */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -/* NAND: driver related configs */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW - -/* NAND: SPL related configs */ -#ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00200000 /* kernel offset */ -#endif -#endif /* !CONFIG_NAND */ - -/* CPU */ - -#ifdef CONFIG_SPI_BOOT -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 -#elif defined(CONFIG_ENV_IS_IN_NAND) -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE -#endif - -#endif /* ! __CONFIG_PHYCORE_AM335x_R2_H */ diff --git a/include/configs/phycore_rk3288.h b/include/configs/phycore_rk3288.h deleted file mode 100644 index 9135aa6..0000000 --- a/include/configs/phycore_rk3288.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 PHYTEC Messtechnik GmbH - * Author: Wadim Egorov - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include - -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) - -#define CONFIG_SYS_MMC_ENV_DEV 1 - -#endif diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h deleted file mode 100644 index d3ab557..0000000 --- a/include/configs/pic32mzdask.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2015 Purna Chandra Mandal - * - * Microchip PIC32MZ[DA] Starter Kit. - */ - -#ifndef __PIC32MZDASK_CONFIG_H -#define __PIC32MZDASK_CONFIG_H - -/* System Configuration */ - -/*-------------------------------------------- - * CPU configuration - */ -/* CPU Timer rate */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 100000000 - -/*---------------------------------------------------------------------- - * Memory Layout - */ -#define CONFIG_SYS_SRAM_BASE 0x80000000 -#define CONFIG_SYS_SRAM_SIZE 0x00080000 /* 512K */ - -/* Initial RAM for temporary stack, global data */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_ADDR \ - (CONFIG_SYS_SRAM_BASE + CONFIG_SYS_SRAM_SIZE - CONFIG_SYS_INIT_RAM_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE - 1) - -/* SDRAM Configuration (for final code, data, stack, heap) */ -#define CONFIG_SYS_SDRAM_BASE 0x88000000 -#define CONFIG_SYS_MALLOC_LEN (256 << 10) -#define CONFIG_SYS_BOOTPARAMS_LEN (4 << 10) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (192 << 10) - -#define CONFIG_SYS_LOAD_ADDR 0x88500000 /* default load address */ -#define CONFIG_SYS_ENV_ADDR 0x88300000 -#define CONFIG_SYS_FDT_ADDR 0x89d00000 - -/* Memory Test */ -#define CONFIG_SYS_MEMTEST_START 0x88000000 -#define CONFIG_SYS_MEMTEST_END 0x88080000 - -/*---------------------------------------------------------------------- - * Commands - */ - -/*------------------------------------------------------------ - * Console Configuration - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/*----------------------------------------------------------------------- - * Networking Configuration - */ -#define CONFIG_PHY_SMSC -#define CONFIG_SYS_RX_ETH_BUFFER 8 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_ARP_TIMEOUT 500 /* millisec */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/*-------------------------------------------------- - * USB Configuration - */ - -/* ------------------------------------------------- - * Environment - */ -#define CONFIG_ENV_SIZE 0x4000 - -/* --------------------------------------------------------------------- - * Board boot configuration - */ -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define MEM_LAYOUT_ENV_SETTINGS \ - "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ - "fdt_addr_r="__stringify(CONFIG_SYS_FDT_ADDR)"\0" \ - "scriptaddr="__stringify(CONFIG_SYS_ENV_ADDR)"\0" - -#define CONFIG_LEGACY_BOOTCMD_ENV \ - "legacy_bootcmd= " \ - "if load mmc 0 ${scriptaddr} uEnv.txt; then " \ - "env import -tr ${scriptaddr} ${filesize}; " \ - "if test -n \"${bootcmd_uenv}\" ; then " \ - "echo Running bootcmd_uenv ...; " \ - "run bootcmd_uenv; " \ - "fi; " \ - "fi; \0" - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ - CONFIG_LEGACY_BOOTCMD_ENV \ - BOOTENV - -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "run distro_bootcmd || run legacy_bootcmd" - -#endif /* __PIC32MZDASK_CONFIG_H */ diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h deleted file mode 100644 index 5bbb9ea..0000000 --- a/include/configs/pico-imx6.h +++ /dev/null @@ -1,164 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * Configuration settings for the pico-imx6 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000 - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE - -/* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -#define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=" \ - "spl raw 0x2 0x400;" \ - "u-boot raw 0x8a 0x1000;" \ - "/boot/zImage ext4 0 1;" \ - "rootfs part 0 1\0" \ - -#define BOOTMENU_ENV \ - "bootmenu_0=Boot using PICO-Hobbit baseboard=" \ - "setenv baseboard hobbit; saveenv; run base_boot\0" \ - "bootmenu_1=Boot using PICO-Pi baseboard=" \ - "setenv baseboard pi; saveenv; run base_boot\0" \ - "bootmenu_2=Boot using PICO-Dwarf baseboard=" \ - "setenv baseboard dwarf; saveenv; run base_boot\0" \ - "bootmenu_3=Boot using PICO-Nymph baseboard=" \ - "setenv baseboard nymph; saveenv; run base_boot\0" \ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - BOOTMENU_ENV \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_addr=0x18000000\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - CONFIG_DFU_ENV_SETTINGS \ - "finduuid=part uuid mmc 0:1 uuid\0" \ - "findfdt="\ - "if test $baseboard = hobbit && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-pico-hobbit.dtb; fi; " \ - "if test $baseboard = pi && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-pico-pi.dtb; fi; " \ - "if test $baseboard = dwarf && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-pico-dwarf.dtb; fi; " \ - "if test $baseboard = nymph && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-pico-nymph.dtb; fi; " \ - "if test $baseboard = hobbit && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-pico-hobbit.dtb; fi; " \ - "if test $baseboard = pi && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-pico-pi.dtb; fi; " \ - "if test $baseboard = dwarf && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-pico-dwarf.dtb; fi; " \ - "if test $baseboard = nymph && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-pico-nymph.dtb; fi; " \ - "if test $fdtfile = ask; then " \ - "echo WARNING: Could not determine dtb to use; fi; \0" \ - "default_boot=" \ - "if test $baseboard = ask ; then " \ - "bootmenu -1; " \ - "else " \ - "run base_boot;" \ - "fi; \0" \ - "base_boot=run findfdt; run finduuid; run distro_bootcmd\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "ramdiskaddr=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) - -#include - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -/* Environment starts at 768k = 768 * 1024 = 786432 */ -#define CONFIG_ENV_OFFSET 786432 -/* - * Detect overlap between U-Boot image and environment area in build-time - * - * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset - * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 - * - * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so - * write the direct value here - */ -#define CONFIG_BOARD_SIZE_LIMIT 715776 -#define CONFIG_SYS_MMC_ENV_DEV 0 - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define CONFIG_MII -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 -#define CONFIG_PHYLIB -#define CONFIG_PHY_ATHEROS - -/* Framebuffer */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -#endif /* __CONFIG_H * */ diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h deleted file mode 100644 index 22dfac7..0000000 --- a/include/configs/pico-imx6ul.h +++ /dev/null @@ -1,167 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Technexion Ltd. - * - * Configuration settings for the Technexion PICO-IMX6UL-EMMC board. - */ -#ifndef __PICO_IMX6UL_CONFIG_H -#define __PICO_IMX6UL_CONFIG_H - - -#include -#include -#include "mx6_common.h" -#include -#include "imx6_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ -#endif - -/* Network support */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET2_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 -#define CONFIG_FEC_XCV_TYPE RMII - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART6_BASE_ADDR - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -#define CONFIG_USBD_HS - -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -#define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=" \ - "spl raw 0x2 0x400;" \ - "u-boot raw 0x8a 0x400;" \ - "/boot/zImage ext4 0 1;" \ - "/boot/imx6ul-pico-hobbit.dtb ext4 0 1;" \ - "/boot/imx6ul-pico-pi.dtb ext4 0 1;" \ - "rootfs part 0 1\0" \ - -#define BOOTMENU_ENV \ - "bootmenu_0=Boot using PICO-Dwarf baseboard=" \ - "setenv fdtfile imx6ul-pico-dwarf.dtb\0" \ - "bootmenu_1=Boot using PICO-Hobbit baseboard=" \ - "setenv fdtfile imx6ul-pico-hobbit.dtb\0" \ - "bootmenu_2=Boot using PICO-Pi baseboard=" \ - "setenv fdtfile imx6ul-pico-pi.dtb\0" \ - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "splashpos=m,m\0" \ - "console=ttymxc5\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ - BOOTMENU_ENV \ - "fdt_addr=0x83000000\0" \ - "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x83000000\0" \ - "ramdiskaddr=0x83000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "mmcautodetect=yes\0" \ - CONFIG_DFU_ENV_SETTINGS \ - "findfdt=" \ - "if test $fdtfile = ask ; then " \ - "bootmenu -1; fi;" \ - "if test $fdtfile != ask ; then " \ - "saveenv; fi;\0" \ - "finduuid=part uuid mmc 0:1 uuid\0" \ - "partitions=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ - "fastboot_partition_alias_system=rootfs\0" \ - "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + SZ_128M - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - -/* environment organization */ -#define CONFIG_ENV_SIZE SZ_8K -/* Environment starts at 768k = 768 * 1024 = 786432 */ -#define CONFIG_ENV_OFFSET 786432 -/* - * Detect overlap between U-Boot image and environment area in build-time - * - * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset - * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 - * - * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so - * write the direct value here - */ -#define CONFIG_BOARD_SIZE_LIMIT 715776 - - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 - -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_MXS -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR -#endif - -#endif /* __PICO_IMX6UL_CONFIG_H */ diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h deleted file mode 100644 index 607784e..0000000 --- a/include/configs/pico-imx7d.h +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 NXP Semiconductors - * - * Configuration settings for the i.MX7D Pico board. - */ - -#ifndef __PICO_IMX7D_CONFIG_H -#define __PICO_IMX7D_CONFIG_H - -#include "mx7_common.h" - -#include "imx7_spl.h" - -#ifdef CONFIG_SPL_OS_BOOT -/* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x88000000 - -/* Falcon Mode - MMC support: args@1MB kernel@2MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */ -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) - -#define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR - -/* Network */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 1 - -#define CONFIG_PHY_ATHEROS - -/* ENET1 */ -#define IMX_FEC_BASE ENET_IPS_BASE_ADDR - -/* MMC Config */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=" \ - "spl raw 0x2 0x400;" \ - "u-boot raw 0x8a 0x1000;" \ - "/boot/zImage ext4 0 1;" \ - "/boot/imx7d-pico-hobbit.dtb ext4 0 1;" \ - "/boot/imx7d-pico-pi.dtb ext4 0 1;" \ - "rootfs part 0 1\0" \ - -/* When booting with FIT specify the node entry containing boot.scr */ -#if defined(CONFIG_FIT) -#define PICO_BOOT_ENV \ - BOOTENV \ - "fdtovaddr=0x83100000\0" \ - "scriptaddr=0x83200000\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "rootwait rw\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "iminfo ${scriptaddr};" \ - "if test $? -eq 1; then hab_failsafe; fi;" \ - "source ${scriptaddr}:bootscr\0" -#else -#define PICO_BOOT_ENV \ - "bootmenu_0=Boot using PICO-Hobbit baseboard=" \ - "setenv fdtfile imx7d-pico-hobbit.dtb\0" \ - "bootmenu_1=Boot using PICO-Dwarf baseboard=" \ - "setenv fdtfile imx7d-pico-dwarf.dtb\0" \ - "bootmenu_2=Boot using PICO-Nymph baseboard=" \ - "setenv fdtfile imx7d-pico-nymph.dtb\0" \ - "bootmenu_3=Boot using PICO-Pi baseboard=" \ - "setenv fdtfile imx7d-pico-pi.dtb\0" \ - BOOTENV -#endif - - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "image=zImage\0" \ - "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "console=ttymxc4\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "videomode=video=ctfb:x:800,y:480,depth:24,mode:0,pclk:30000,le:46,ri:210,up:22,lo:23,hs:20,vs:10,sync:0,vmode:0\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_addr_r=0x83000000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x83000000\0" \ - "ramdiskaddr=0x83000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - CONFIG_DFU_ENV_SETTINGS \ - "findfdt=" \ - "if test $fdtfile = ask ; then " \ - "bootmenu -1; fi;" \ - "if test $fdtfile != ask ; then " \ - "saveenv; fi;\0" \ - "finduuid=part uuid mmc 0:1 uuid\0" \ - "partitions=" \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=rootfs,size=0,uuid=${uuid_gpt_rootfs}\0" \ - "fastboot_partition_alias_system=rootfs\0" \ - "setup_emmc=mmc dev 0; gpt write mmc 0 $partitions; reset;\0" \ - PICO_BOOT_ENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* I2C configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_MXC_I2C3 -#define CONFIG_SYS_I2C_MXC_I2C4 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 - -#ifdef CONFIG_DM_VIDEO -#define CONFIG_VIDEO_MXS -#define CONFIG_VIDEO_LOGO -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#endif - -/* FLASH and environment organization */ -#define CONFIG_ENV_SIZE SZ_8K - -/* Environment starts at 768k = 768 * 1024 = 786432 */ -#define CONFIG_ENV_OFFSET 786432 -/* - * Detect overlap between U-Boot image and environment area in build-time - * - * CONFIG_BOARD_SIZE_LIMIT = CONFIG_ENV_OFFSET - u-boot.img offset - * CONFIG_BOARD_SIZE_LIMIT = 768k - 69k = 699k = 715776 - * - * Currently CONFIG_BOARD_SIZE_LIMIT does not handle expressions, so - * write the direct value here - */ -#define CONFIG_BOARD_SIZE_LIMIT 715776 - -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -#define CONFIG_IMX_THERMAL - -#endif diff --git a/include/configs/picosam9g45.h b/include/configs/picosam9g45.h deleted file mode 100644 index ad41d16..0000000 --- a/include/configs/picosam9g45.h +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the mini-box PICOSAM9G45 board. - * (C) Copyright 2015 Inter Act B.V. - * - * Based on: - * U-Boot file: include/configs/at91sam9m10g45ek.h - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO -#define CONFIG_LCD_INFO_BELOW_LOGO -#define CONFIG_ATMEL_LCD -#define CONFIG_ATMEL_LCD_RGB565 -/* board specific(not enough SRAM) */ -#define CONFIG_AT91SAM9G45_LCD_BASE 0x23E00000 - -/* LED */ -#define CONFIG_AT91_LED -#define CONFIG_GREEN_LED AT91_PIN_PD31 /* this is the user1 led */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* SDRAM */ -#define PHYS_SDRAM_1 ATMEL_BASE_CS1 /* on DDRSDRC1 */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ -#define PHYS_SDRAM_2 ATMEL_BASE_CS6 /* on DDRSDRC0 */ -#define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#ifdef CONFIG_SYS_USE_MMC -/* bootstrap + u-boot + env + linux in mmc */ -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 - -#define CONFIG_SYS_MONITOR_LEN 0x80000 - -#ifdef CONFIG_SYS_USE_MMC - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#endif -#endif diff --git a/include/configs/platinum.h b/include/configs/platinum.h deleted file mode 100644 index 1b57e99..0000000 --- a/include/configs/platinum.h +++ /dev/null @@ -1,202 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_CONFIG_H__ -#define __PLATINUM_CONFIG_H__ - -/* SPL */ - -/* Location in NAND to read U-Boot from */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024) - -#include "imx6_spl.h" /* common IMX6 SPL configuration */ -#include "mx6_common.h" - -/* - * Hardware configuration - */ - -/* UART config */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C config */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC config */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -/* Ethernet config */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR - -/* USB config */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* Memory config */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#ifndef PHYS_SDRAM_SIZE -#define PHYS_SDRAM_SIZE (1024 << 20) -#endif - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) - -#ifdef CONFIG_CMD_NAND - -/* NAND config */ -#ifndef CONFIG_SYS_NAND_MAX_CHIPS -#define CONFIG_SYS_NAND_MAX_CHIPS 2 -#endif -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA config, needed for GPMI/MXS NAND support */ - -/* Environment in NAND */ -#define CONFIG_ENV_OFFSET (16 << 20) -#define CONFIG_ENV_SECT_SIZE (128 << 10) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#else /* CONFIG_CMD_NAND */ - -/* Environment in MMC */ -#define CONFIG_ENV_SIZE (8 << 10) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif /* CONFIG_CMD_NAND */ - -/* - * U-Boot configuration - */ - -/* Board startup config */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - PHYS_SDRAM_SIZE - (12 << 20)) - -#define CONFIG_BOOTCOMMAND "run bootubi_scr" - -/* Miscellaneous configurable options */ - -/* MTD/UBI/UBIFS config */ - -/* - * Environment configuration - */ - -#if (CONFIG_SYS_NAND_MAX_CHIPS == 1) -#define CONFIG_COMMON_ENV_UBI \ - "setubipartition=env set ubipartition ubi\0" \ - "setubirfs=env set ubirfs $ubipartition:rootfs$boot_vol\0" -#elif (CONFIG_SYS_NAND_MAX_CHIPS == 2) -#define CONFIG_COMMON_ENV_UBI \ - "setubipartition=env set ubipartition ubi$boot_vol\0" \ - "setubirfs=env set ubirfs ubi0:rootfs\0" -#endif - -#define CONFIG_COMMON_ENV_MISC \ - "user=user\0" \ - "project="CONFIG_PLATINUM_PROJECT"\0" \ - "uimage=uImage\0" \ - "dtb="CONFIG_PLATINUM_CPU"-platinum-"CONFIG_PLATINUM_PROJECT".dtb\0" \ - "serverip=serverip\0" \ - "memaddrlinux=0x10800000\0" \ - "memaddrsrc=0x11000000\0" \ - "memaddrdtb=0x12000000\0" \ - "console=ttymxc0\0" \ - "baudrate=115200\0" \ - "boot_scr=boot.uboot\0" \ - "boot_vol=0\0" \ - "mtdids="CONFIG_MTDIDS_DEFAULT"\0" \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ - "mmcfs=ext2\0" \ - "mmcrootpart=1\0" \ - \ - "setnfspath=env set nfspath /home/nfs/$user/$project/root\0" \ - "settftpfilelinux=env set tftpfilelinux $user/$project/$uimage\0" \ - "settftpfiledtb=env set tftpfiledtb $user/$project/$dtb\0" \ - "setubifilelinux=env set ubifilelinux boot/$uimage\0" \ - "setubipfiledtb=env set ubifiledtb boot/$dtb\0" \ - "setmmcrootdev=env set mmcrootdev /dev/mmcblk0p$mmcrootpart\0" \ - "setmmcfilelinux=env set mmcfilelinux /boot/$uimage\0" \ - "setmmcfiledtb=env set mmcfiledtb /boot/$dtb\0" \ - \ - "loadtftpkernel=dhcp $memaddrlinux $tftpfilelinux\0" \ - "loadtftpdtb=dhcp $memaddrdtb $tftpfiledtb\0" \ - "loadubikernel=ubifsload $memaddrlinux $ubifilelinux\0" \ - "loadubidtb=ubifsload $memaddrdtb $ubifiledtb\0" \ - "loadmmckernel=${mmcfs}load mmc 0:$mmcrootpart $memaddrlinux " \ - "$mmcfilelinux\0" \ - "loadmmcdtb=${mmcfs}load mmc 0:$mmcrootpart $memaddrdtb " \ - "$mmcfiledtb\0" \ - \ - "ubipart=ubi part $ubipartition\0" \ - "ubimount=ubifsmount $ubirfs\0" \ - \ - "setbootargscommon=env set bootargs $bootargs " \ - "console=$console,$baudrate enable_wait_mode=off\0" \ - "setbootargsmtd=env set bootargs $bootargs $mtdparts\0" \ - "setbootargsdhcp=env set bootargs $bootargs ip=dhcp\0" \ - "setbootargsubirfs=env set bootargs $bootargs " \ - "ubi.mtd=$ubipartition root=$ubirfs rootfstype=ubifs\0" \ - "setbootargsnfsrfs=env set bootargs $bootargs root=/dev/nfs " \ - "nfsroot=$serverip:$nfspath,v3,tcp\0" \ - "setbootargsmmcrfs=env set bootargs $bootargs " \ - "root=$mmcrootdev rootwait rw\0" \ - \ - "bootnet=run settftpfilelinux settftpfiledtb setnfspath " \ - "setbootargscommon setbootargsmtd setbootargsdhcp " \ - "setbootargsnfsrfs;" \ - "run loadtftpkernel loadtftpdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootnet_ubirfs=run settftpfilelinux settftpfiledtb;" \ - "run setubipartition setubirfs;" \ - "run setbootargscommon setbootargsmtd " \ - "setbootargsubirfs;" \ - "run loadtftpkernel loadtftpdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootubi=run setubipartition setubirfs setubifilelinux " \ - "setubipfiledtb;" \ - "run setbootargscommon setbootargsmtd " \ - "setbootargsubirfs;" \ - "run ubipart ubimount loadubikernel loadubidtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - "bootubi_scr=run setubipartition setubirfs;" \ - "run ubipart ubimount;" \ - "if ubifsload ${memaddrsrc} boot/${boot_scr}; " \ - "then source ${memaddrsrc}; else run bootubi; fi\0" \ - "bootmmc=run setmmcrootdev setmmcfilelinux setmmcfiledtb " \ - "setbootargscommon setbootargsmmcrfs;" \ - "run loadmmckernel loadmmcdtb;" \ - "bootm $memaddrlinux - $memaddrdtb\0" \ - \ - "bootcmd="CONFIG_BOOTCOMMAND"\0" - -#define CONFIG_COMMON_ENV_SETTINGS CONFIG_COMMON_ENV_MISC \ - CONFIG_COMMON_ENV_UBI -#endif /* __PLATINUM_CONFIG_H__ */ diff --git a/include/configs/platinum_picon.h b/include/configs/platinum_picon.h deleted file mode 100644 index 1b55e73..0000000 --- a/include/configs/platinum_picon.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_PICON_CONFIG_H__ -#define __PLATINUM_PICON_CONFIG_H__ - -#define CONFIG_PLATINUM_BOARD "Barco Picon" -#define CONFIG_PLATINUM_PROJECT "picon" -#define CONFIG_PLATINUM_CPU "imx6dl" - -#include - -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_HOSTNAME "picon" - -#define CONFIG_PLATFORM_ENV_SETTINGS "\0" - -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS - -#endif /* __PLATINUM_PICON_CONFIG_H__ */ diff --git a/include/configs/platinum_titanium.h b/include/configs/platinum_titanium.h deleted file mode 100644 index b402883..0000000 --- a/include/configs/platinum_titanium.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Barco (www.barco.com) - */ - -#ifndef __PLATINUM_TITANIUM_CONFIG_H__ -#define __PLATINUM_TITANIUM_CONFIG_H__ - -#define CONFIG_PLATINUM_BOARD "Barco Titanium" -#define CONFIG_PLATINUM_PROJECT "titanium" -#define CONFIG_PLATINUM_CPU "imx6q" - -#define PHYS_SDRAM_SIZE (512 << 20) -#define CONFIG_SYS_NAND_MAX_CHIPS 1 - -#include - -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 4 - -#define CONFIG_PHY_RESET_DELAY 1000 - -#define CONFIG_HOSTNAME "titanium" - -#define CONFIG_PLATFORM_ENV_SETTINGS "\0" - -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS - -#endif /* __PLATINUM_TITANIUM_CONFIG_H__ */ diff --git a/include/configs/plutux.h b/include/configs/plutux.h deleted file mode 100644 index 43856ba..0000000 --- a/include/configs/plutux.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* NAND support */ -#define CONFIG_TEGRA_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment in NAND, aligned to start of last sector */ -#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h deleted file mode 100644 index 99ca1f7..0000000 --- a/include/configs/pm9261.h +++ /dev/null @@ -1,270 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * Ilko Iliev - * - * Configuation settings for the RONETIX PM9261 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ - -#include -/* ARM asynchronous clock */ - -#define MASTER_PLL_DIV 15 -#define MASTER_PLL_MUL 162 -#define MAIN_PLL_DIV 2 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 - -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9261" - -#define CONFIG_MACH_TYPE MACH_TYPE_PM9261 - -/* clocks */ -/* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOR_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_PLLXR_OUT(3) | \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_MCKR_CSS_SLOW | \ - AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) - -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_MCKR_CSS_PLLA | \ - AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) - -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOC_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOC_PPUDR_VAL 0xFFFF0000 - -/* EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash */ -#define CONFIG_SYS_MATRIX_EBICSA_VAL \ - (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_EBI_CS1A) - -/* SDRAM */ -/* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 AT91_SDRAMC_MODE_NORMAL -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_3 | \ - AT91_SDRAMC_DBW_32 | \ - (1 << 8) | /* Write Recovery Delay */ \ - (7 << 12) | /* Row Cycle Delay */ \ - (3 << 16) | /* Row Precharge Delay */ \ - (2 << 20) | /* Row to Column Delay */ \ - (5 << 24) | /* Active to Precharge Delay */ \ - (1 << 28)) /* Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ - AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ - AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | \ - AT91_SMC_MODE_TDF_CYCLE(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_CR_PROCRST | \ - AT91_RSTC_MR_ERSTL(1) | \ - AT91_RSTC_MR_ERSTL(2)) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ - AT91_WDT_MR_WDV(0xfff) | \ - AT91_WDT_MR_WDDIS | \ - AT91_WDT_MR_WDD(0xfff)) - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#undef CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Hardware drivers - */ - -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_BGR555 1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 - -/* SDRAM */ -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD22 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 22) -/* our CLE is AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 21) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16) - -/* NOR flash */ -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -/* Ethernet */ -#define CONFIG_DRIVER_DM9000 1 -#define CONFIG_DM9000_BASE 0x30000000 -#define DM9000_IO CONFIG_DM9000_BASE -#define DM9000_DATA (CONFIG_DM9000_BASE + 4) -#define CONFIG_DM9000_USE_16BIT 1 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#undef CONFIG_SYS_USE_DATAFLASH_CS0 -#undef CONFIG_SYS_USE_NANDFLASH -#define CONFIG_SYS_USE_FLASH 1 - -#ifdef CONFIG_SYS_USE_DATAFLASH_CS0 - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x22000000 0x84000 0x210000; " \ - "bootm 0x22000000" - -#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CONFIG_SYS_USE_NANDFLASH */ - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" - -#elif defined (CONFIG_SYS_USE_FLASH) - -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* JFFS Partition offset set */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 - -#define CONFIG_BOOTCOMMAND "run flashboot" - -#define CONFIG_CON_ROT "fbcon=rotate:3 " - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "partition=nand0,0\0" \ - "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - CONFIG_CON_ROT \ - "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot 0x22000000 vmImage;" \ - "run ramargs;run addip;bootm 22000000\0" \ - "nfsboot=tftpboot 0x22000000 vmImage;" \ - "run nfsargs;run addip;bootm 22000000\0" \ - "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ - "" -#else -#error "Undefined memory device" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ - GENERATED_GBL_DATA_SIZE) - -#endif diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h deleted file mode 100644 index 595acf1..0000000 --- a/include/configs/pm9263.h +++ /dev/null @@ -1,300 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * Ilko Iliev - * - * Configuation settings for the RONETIX PM9263 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include - -/* ARM asynchronous clock */ - -#define MASTER_PLL_DIV 6 -#define MASTER_PLL_MUL 65 -#define MAIN_PLL_DIV 2 /* 2 or 4 */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ - -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" - -#define CONFIG_MACH_TYPE MACH_TYPE_PM9263 - -/* clocks */ -#define CONFIG_SYS_MOR_VAL \ - (AT91_PMC_MOR_MOSCEN | \ - (255 << 8)) /* Main Oscillator Start-up Time */ -#define CONFIG_SYS_PLLAR_VAL \ - (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ - AT91_PMC_PLLXR_OUT(3) | \ - AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ - (2 << 28) | /* PLL Clock Frequency Range */ \ - ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) - -#if (MAIN_PLL_DIV == 2) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_MCKR_CSS_SLOW | \ - AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) -/* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_MCKR_CSS_PLLA | \ - AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_2) -#else -/* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL \ - (AT91_PMC_MCKR_CSS_SLOW | \ - AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_4) -/* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL \ - (AT91_PMC_MCKR_CSS_PLLA | \ - AT91_PMC_MCKR_PRES_1 | \ - AT91_PMC_MCKR_MDIV_4) -#endif -/* define PDC[31:16] as DATA[31:16] */ -#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 -/* no pull-up for D[31:16] */ -#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 -/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ - (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ - AT91_MATRIX_CSA_EBI_CS1A) - -/* SDRAM */ -/* SDRAMC_MR Mode register */ -#define CONFIG_SYS_SDRC_MR_VAL1 0 -/* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA -/* SDRAMC_CR - Configuration register*/ -#define CONFIG_SYS_SDRC_CR_VAL \ - (AT91_SDRAMC_NC_9 | \ - AT91_SDRAMC_NR_13 | \ - AT91_SDRAMC_NB_4 | \ - AT91_SDRAMC_CAS_2 | \ - AT91_SDRAMC_DBW_32 | \ - (2 << 8) | /* tWR - Write Recovery Delay */ \ - (7 << 12) | /* tRC - Row Cycle Delay */ \ - (2 << 16) | /* tRP - Row Precharge Delay */ \ - (2 << 20) | /* tRCD - Row to Column Delay */ \ - (5 << 24) | /* tRAS - Active to Precharge Delay */ \ - (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ - -/* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM -#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE -#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH -#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR -#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL -#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ -#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ - -/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL \ - (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ - AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) -#define CONFIG_SYS_SMC0_PULSE0_VAL \ - (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ - AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) -#define CONFIG_SYS_SMC0_CYCLE0_VAL \ - (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) -#define CONFIG_SYS_SMC0_MODE0_VAL \ - (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ - AT91_SMC_MODE_DBW_16 | \ - AT91_SMC_MODE_TDF | \ - AT91_SMC_MODE_TDF_CYCLE(6)) - -/* user reset enable */ -#define CONFIG_SYS_RSTC_RMR_VAL \ - (AT91_RSTC_KEY | \ - AT91_RSTC_CR_PROCRST | \ - AT91_RSTC_MR_ERSTL(1) | \ - AT91_RSTC_MR_ERSTL(2)) - -/* Disable Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL \ - (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ - AT91_WDT_MR_WDV(0xfff) | \ - AT91_WDT_MR_WDDIS | \ - AT91_WDT_MR_WDD(0xfff)) - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -#undef CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_USER_LOWLEVEL_INIT 1 - -/* - * Hardware drivers - */ -/* LCD */ -#define LCD_BPP LCD_COLOR8 -#define CONFIG_LCD_LOGO 1 -#undef LCD_TEST_PATTERN -#define CONFIG_LCD_INFO 1 -#define CONFIG_LCD_INFO_BELOW_LOGO 1 -#define CONFIG_ATMEL_LCD 1 -#define CONFIG_ATMEL_LCD_BGR555 1 - -#define CONFIG_LCD_IN_PSRAM 1 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE 1 - -/* SDRAM */ -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ - -/* NOR flash, if populated */ -#define PHYS_FLASH_1 0x10000000 -#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_DBW_8 1 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(30) - -#endif - -#define CONFIG_JFFS2_CMDLINE 1 -#define CONFIG_JFFS2_NAND 1 -#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ -#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ -#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition size*/ - -/* PSRAM */ -#define PHYS_PSRAM 0x70000000 -#define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ -/* Slave EBI1, PSRAM connected */ -#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ - AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ - AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ - AT91_MATRIX_SCFG_SLOT_CYCLE(255)) - -/* Ethernet */ -#define CONFIG_MACB 1 -#define CONFIG_RMII 1 -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R 1 - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#define CONFIG_SYS_USE_FLASH 1 -#undef CONFIG_SYS_USE_DATAFLASH -#undef CONFIG_SYS_USE_NANDFLASH - -#ifdef CONFIG_SYS_USE_DATAFLASH - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_ENV_OFFSET 0x4200 -#define CONFIG_ENV_SIZE 0x4200 -#define CONFIG_ENV_SECT_SIZE 0x210 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x22000000 0x84000 0x294000; " \ - "bootm 0x22000000" - -#elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ - -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_OFFSET_REDUND 0x80000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" - -#elif defined(CONFIG_SYS_USE_FLASH) /* CFG_USE_FLASH */ - -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_OVERWRITE 1 - -/* JFFS Partition offset set */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 - -#define CONFIG_BOOTCOMMAND "run flashboot" -#define CONFIG_ROOTPATH "/ronetix/rootfs" - -#define CONFIG_CON_ROT "fbcon=rotate:3 " - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "partition=nand0,0\0" \ - "ramargs=setenv bootargs $(bootargs) $(mtdparts)\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - CONFIG_CON_ROT \ - "nfsroot=$(serverip):$(rootpath) $(mtdparts)\0" \ - "addip=setenv bootargs $(bootargs) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"\ - ":$(hostname):eth0:off\0" \ - "ramboot=tftpboot 0x22000000 vmImage;" \ - "run ramargs;run addip;bootm 22000000\0" \ - "nfsboot=tftpboot 0x22000000 vmImage;" \ - "run nfsargs;run addip;bootm 22000000\0" \ - "flashboot=run ramargs;run addip;bootm 0x10050000\0" \ - "" - -#else -#error "Undefined memory device" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - \ - GENERATED_GBL_DATA_SIZE) - -#endif diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h deleted file mode 100644 index ae87f9b..0000000 --- a/include/configs/pm9g45.h +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Ilko Iliev - * Asen Dimov - * Ronetix GmbH - * - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * Configuation settings for the PM9G45 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x70000000 -#define CONFIG_SYS_SDRAM_SIZE 0x08000000 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD3 -#define CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT -#endif - -/* Ethernet */ -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#ifdef CONFIG_NAND_BOOT -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_ENV_OFFSET 0x140000 -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_ENV_SIZE 0x20000 - -#define CONFIG_BOOTCOMMAND \ - "nand read 0x70000000 0x200000 0x300000;" \ - "bootm 0x70000000" -#elif CONFIG_SD_BOOT -/* bootstrap + u-boot + env + linux in mmc */ -#define CONFIG_ENV_SIZE 0x4000 - -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ - "fatload mmc 0:1 0x72000000 zImage; " \ - "bootz 0x72000000 - 0x71000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \ - 128 * 1024, 0x1000) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE 0x010000 -#define CONFIG_SPL_STACK 0x310000 - -#define CONFIG_SYS_MONITOR_LEN 0x80000 - -#ifdef CONFIG_SD_BOOT - -#define CONFIG_SPL_BSS_START_ADDR 0x70000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 -#define CONFIG_SYS_SPL_MALLOC_START 0x70080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_SOFTECC -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } -#endif - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#endif diff --git a/include/configs/pogo_e02.h b/include/configs/pogo_e02.h deleted file mode 100644 index 68d7268..0000000 --- a/include/configs/pogo_e02.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 - * David Purdy - * - * Based on Kirkwood support: - * (C) Copyright 2009 - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -#ifndef _CONFIG_POGO_E02_H -#define _CONFIG_POGO_E02_H - -/* - * Machine type definition and ID - */ -#define CONFIG_MACH_TYPE MACH_TYPE_POGO_E02 - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */ -#define CONFIG_KW88F6281 /* SOC Name */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ - -/* - * Commands configuration - */ - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#endif - -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */ - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND \ - "setenv bootargs $(bootargs_console); " \ - "run bootcmd_usb; " \ - "bootm 0x00800000 0x01100000" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=mtdparts=orion_nand:1M(u-boot),4M(uImage)," \ - "32M(rootfs),-(data)\0"\ - "mtdids=nand0=orion_nand\0"\ - "bootargs_console=console=ttyS0,115200\0" \ - "bootcmd_usb=usb start; ext2load usb 0:1 0x00800000 /uImage; " \ - "ext2load usb 0:1 0x01100000 /uInitrd\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - -/* - * File system - */ - -#endif /* _CONFIG_POGO_E02_H */ diff --git a/include/configs/poplar.h b/include/configs/poplar.h deleted file mode 100644 index be9a0b5..0000000 --- a/include/configs/poplar.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Linaro - * - * Jorge Ramirez-Ortiz - * - * Configuration for Poplar 96boards CE. Parts were derived from other ARM - * configurations. - */ - -#ifndef _POPLAR_H_ -#define _POPLAR_H_ - -#include - -/* DRAM banks */ - -/* SYS */ -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#define CONFIG_SYS_INIT_SP_ADDR 0x200000 -#define CONFIG_SYS_LOAD_ADDR 0x800000 -#define CONFIG_SYS_MALLOC_LEN SZ_32M - -/* ATF bl33.bin load address (must match) */ - -/* USB configuration */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/***************************************************************************** - * Initial environment variables - *****************************************************************************/ - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) -#ifndef CONFIG_SPL_BUILD -#include -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loader_mmc_blknum=0x0\0" \ - "loader_mmc_nblks=0x780\0" \ - "env_mmc_blknum=0xf80\0" \ - "env_mmc_nblks=0x80\0" \ - "kernel_addr_r=0x30000000\0" \ - "pxefile_addr_r=0x32000000\0" \ - "scriptaddr=0x32000000\0" \ - "fdt_addr_r=0x32200000\0" \ - "fdtfile=hisilicon/hi3798cv200-poplar.dtb\0" \ - "ramdisk_addr_r=0x32400000\0" \ - BOOTENV - - -/* Command line configuration */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_OFFSET (0xf80 * 512) /* env_mmc_blknum bytes */ -#define CONFIG_ENV_SIZE (0x80 * 512) /* env_mmc_nblks bytes */ - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 -#define CONFIG_SYS_MAXARGS 64 - -#endif /* _POPLAR_H_ */ diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h deleted file mode 100644 index ddd7012..0000000 --- a/include/configs/popmetal_rk3288.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/porter.h b/include/configs/porter.h deleted file mode 100644 index db42176..0000000 --- a/include/configs/porter.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/porter.h - * This file is Porter board configuration. - * - * Copyright (C) 2015 Renesas Electronics Corporation - * Copyright (C) 2015 Cogent Embedded, Inc. - */ - -#ifndef __PORTER_H -#define __PORTER_H - -#include "rcar-gen2-common.h" - -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 -#define STACK_AREA_SIZE 0x00100000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE (2048u * 1024 * 1024) -#define RCAR_GEN2_UBOOT_SDRAM_SIZE (1024u * 1024 * 1024) - -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" - -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_CONS_SCIF0 -#define CONFIG_SH_SCIF_CLK_FREQ 65000000 -#endif - -#endif /* __PORTER_H */ diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h deleted file mode 100644 index 4d6085d..0000000 --- a/include/configs/puma_rk3399.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH - */ - -#ifndef __PUMA_RK3399_H -#define __PUMA_RK3399_H - -#include - -#if defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_SYS_MMC_ENV_DEV 1 -#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) -#define CONFIG_ENV_SECT_SIZE (8 * 1024) -#endif - -#define SDRAM_BANK_SIZE (2UL << 30) - -#define CONFIG_SERIAL_TAG -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BMP_16BPP -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP - -#endif diff --git a/include/configs/pumpkin.h b/include/configs/pumpkin.h deleted file mode 100644 index b2dda64..0000000 --- a/include/configs/pumpkin.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Pumpkin board - * - * Copyright (C) 2019 BayLibre, SAS - * Author: Fabien Parent - -#define CONFIG_ENV_SIZE SZ_4K -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN SZ_4M - -#define CONFIG_CPU_ARMV8 -#define COUNTER_FREQUENCY 13000000 - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_NS16550_COM1 0x11005000 -#define CONFIG_SYS_NS16550_CLK 26000000 - -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -/* Environment settings */ -#include - -#define MMCBOOT \ - "mmcdev=0\0" \ - "kernel_partition=2\0" \ - "rootfs_partition=3\0" \ - "mmc_discover_partition=" \ - "part start mmc ${mmcdev} ${kernel_partition} kernel_part_addr;" \ - "part size mmc ${mmcdev} ${kernel_partition} kernel_part_size;\0" \ - "mmcboot=" \ - "mmc dev ${mmcdev};" \ - "run mmc_discover_partition;" \ - "mmc read ${kerneladdr} ${kernel_part_addr} ${kernel_part_size};" \ - "setenv bootargs ${bootargs} root=/dev/mmcblk${mmcdev}p${rootfs_partition} rootwait; " \ - "bootm ${kerneladdr}; \0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kerneladdr=0x4A000000\0" \ - MMCBOOT \ - "bootcmd=run mmcboot;\0" - -#endif diff --git a/include/configs/pxa-common.h b/include/configs/pxa-common.h deleted file mode 100644 index e25800a..0000000 --- a/include/configs/pxa-common.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Toradex Colibri PXA270 configuration file - * - * Copyright (C) 2010 Marek Vasut - */ - -#ifndef __CONFIG_PXA_COMMON_H__ -#define __CONFIG_PXA_COMMON_H__ - -#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH - -/* - * KGDB - */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 -#endif - -/* - * MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_PXA_MMC_GENERIC -#endif - -/* - * OHCI USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_BOARD_INIT -#ifdef CONFIG_CPU_PXA27X -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#else -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x4c000000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "pxa-ohci" -#endif - -#endif /* __CONFIG_PXA_COMMON_H__ */ diff --git a/include/configs/pxm2.h b/include/configs/pxm2.h deleted file mode 100644 index 543eb2d..0000000 --- a/include/configs/pxm2.h +++ /dev/null @@ -1,129 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * siemens pxm2 - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_PXM2_H -#define __CONFIG_PXM2_H - -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_PXM2 - -#include "siemens-am33x-common.h" - -#define DDR_IOCTRL_VAL 0x18b -#define DDR_PLL_FREQ 266 - -#define BOARD_DFU_BUTTON_GPIO 59 -#define BOARD_LCD_POWER 111 -#define BOARD_BACK_LIGHT 112 -#define BOARD_TOUCH_POWER 57 - -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - "button_dfu0=59\0" \ - "led0=117,0,1\0" \ - - /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 1GB */ - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - -#define CONFIG_PHY_ATHEROS - -#define CONFIG_FACTORYSET - -#ifndef CONFIG_SPL_BUILD - -/* Use common default */ - -/* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=pxm2\0" \ - "ubi_off=2048\0"\ - "nand_img_size=0x500000\0" \ - "optargs=\0" \ - "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - "splashpos=m,m\0" \ - CONFIG_ENV_SETTINGS_V1 \ - CONFIG_ENV_SETTINGS_NAND_V1 \ - "mmc_dev=0\0" \ - "mmc_root=/dev/mmcblk0p2 rw\0" \ - "mmc_root_fs_type=ext4 rootwait\0" \ - "mmc_load_uimage=" \ - "mmc rescan; " \ - "setenv bootfile uImage;" \ - "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ - "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "mmc_args=run bootargs_defaults;" \ - "mtdparts default;" \ - "setenv bootargs ${bootargs} " \ - "root=${mmc_root} ${mtdparts}" \ - "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ - "eth=${ethaddr} " \ - "\0" \ - "mmc_boot=run mmc_args; " \ - "run mmc_load_uimage; " \ - "bootm ${kloadaddr}\0" \ - "" - -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ - -#define CONFIG_BOOTCOMMAND \ - "if dfubutton; then " \ - "run dfu_start; " \ - "reset; " \ - "fi; " \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmc_dev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run mmc_load_uimage; then " \ - "run mmc_args;" \ - "bootm ${kloadaddr};" \ - "fi;" \ - "fi;" \ - "run nand_boot;" \ - "reset;" - -#else - -#define CONFIG_BOOTCOMMAND \ - "setenv autoload no; " \ - "dhcp; " \ - "if tftp 80000000 debrick.scr; then " \ - "source 80000000; " \ - "fi" -#endif -#endif /* CONFIG_SPL_BUILD */ - -#if defined(CONFIG_VIDEO) -#define CONFIG_VIDEO_DA8XX -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE -#define PWM_TICKS 0x1388 -#define PWM_DUTY 0x200 -#endif - -#endif /* ! __CONFIG_PXM2_H */ diff --git a/include/configs/qemu-arm.h b/include/configs/qemu-arm.h deleted file mode 100644 index c7aaafa..0000000 --- a/include/configs/qemu-arm.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Tuomas Tynkkynen - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* Physical memory map */ - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 - -/* The DTB generated by QEMU is placed at start of RAM, stay away from there */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) -#define CONFIG_SYS_MALLOC_LEN SZ_16M - -/* For timer, QEMU emulates an ARMv7/ARMv8 architected timer */ -#define CONFIG_SYS_HZ 1000 - -/* Environment options */ -#define CONFIG_ENV_ADDR 0x4000000 -#define CONFIG_ENV_SIZE SZ_256K - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(SCSI, scsi, 0) \ - func(VIRTIO, virtio, 0) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr=0x40000000\0" \ - "scriptaddr=0x40200000\0" \ - "pxefile_addr_r=0x40300000\0" \ - "kernel_addr_r=0x40400000\0" \ - "ramdisk_addr_r=0x44000000\0" \ - BOOTENV - -#define CONFIG_SYS_CBSIZE 512 - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#ifdef CONFIG_TFABOOT -#define CONFIG_SYS_FLASH_BASE 0x4000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#else -#define CONFIG_SYS_FLASH_BASE 0x0 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#endif -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* Sector: 256K, Bank: 64M */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h deleted file mode 100644 index 1937829..0000000 --- a/include/configs/qemu-mips.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * This file contains the configuration parameters for qemu-mips target. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_QEMU_MIPS - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "bootfile=/tftpboot/vmlinux\0" \ - "load=tftp 80500000 ${u-boot}\0" \ - "" - -#define CONFIG_BOOTCOMMAND "bootp;bootelf" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#define CONFIG_DRIVER_NE2000 -#define CONFIG_DRIVER_NE2000_BASE 0xb4000300 - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 115200 -#define CONFIG_SYS_NS16550_COM1 0xb40003f8 - -#ifdef CONFIG_SYS_BIG_ENDIAN -#define CONFIG_IDE_SWAP_IO -#endif - -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 - -#define CONFIG_SYS_IDE_MAXDEVICE 4 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MALLOC_LEN (256 << 10) - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MHZ 132 - -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -/* Cached addr */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x81000000 - -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -/* We boot from this flash, selected with dip switch */ -#define CONFIG_SYS_FLASH_BASE 0xbfc00000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE) - -#define CONFIG_ENV_OVERWRITE 1 - -#define MEM_SIZE 128 - -#endif /* __CONFIG_H */ diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h deleted file mode 100644 index fe384ec..0000000 --- a/include/configs/qemu-mips64.h +++ /dev/null @@ -1,100 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -/* - * This file contains the configuration parameters for qemu-mips64 target. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_QEMU_MIPS - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addmisc=setenv bootargs ${bootargs} " \ - "console=ttyS0,${baudrate} " \ - "panic=1\0" \ - "bootfile=/tftpboot/vmlinux\0" \ - "load=tftp ffffffff80500000 ${u-boot}\0" \ - "" - -#define CONFIG_BOOTCOMMAND "bootp;bootelf" - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#define CONFIG_DRIVER_NE2000 -#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300 - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 115200 -#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8 - -#ifdef CONFIG_SYS_BIG_ENDIAN -#define CONFIG_IDE_SWAP_IO -#endif - -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_BASE_ADDR 0xffffffffb4000000 - -#define CONFIG_SYS_IDE_MAXDEVICE 4 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MALLOC_LEN (256 << 10) - -#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 - -#define CONFIG_SYS_MHZ 132 - -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -/* Cached addr */ -#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000 - -/* default load address */ -#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000 - -#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000 -#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -/* The following #defines are needed to get flash environment right */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -/* We boot from this flash, selected with dip switch */ -#define CONFIG_SYS_FLASH_BASE 0xffffffffbfc00000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -/* Address and size of Primary Environment Sector */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (4 << 20) - CONFIG_ENV_SIZE) - -#define CONFIG_ENV_OVERWRITE 1 - -#define MEM_SIZE 128 - -#endif /* __CONFIG_H */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h deleted file mode 100644 index 424235e..0000000 --- a/include/configs/qemu-ppce500.h +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2014 Freescale Semiconductor, Inc. - */ - -/* - * Corenet DS style board configuration file - */ -#ifndef __QEMU_PPCE500_H -#define __QEMU_PPCE500_H - -#define CONFIG_SYS_MPC85XX_NO_RESETVEC - -#define CONFIG_SYS_RAMBOOT - -#define CONFIG_PCI1 1 /* PCI controller 1 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* Needed to fill the ccsrbar pointer */ - -/* Virtual address to CCSRBAR */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 -/* Physical address should be a function call */ -#ifndef __ASSEMBLY__ -extern unsigned long long get_phys_ccsrbar_addr_early(void); -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH (get_phys_ccsrbar_addr_early() >> 32) -#define CONFIG_SYS_CCSRBAR_PHYS_LOW get_phys_ccsrbar_addr_early() -#else -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#endif - -/* Virtual address range for PCI region maps */ -#define CONFIG_SYS_PCI_MAP_START 0x80000000 -#define CONFIG_SYS_PCI_MAP_END 0xe8000000 - -/* Virtual address to a temporary map if we need it (max 128MB) */ -#define CONFIG_SYS_TMPVIRT 0xe8000000 - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_CHIP_SELECTS_PER_CTRL 0 - -#define CONFIG_SYS_CLK_FREQ 33000000 - -#define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_INIT_RAM_ADDR 0x00100000 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0x0 -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0x00100000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -#define CONFIG_LBA48 - -/* - * Environment - */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_BOOTCOMMAND \ - "test -n \"$qemu_kernel_addr\" && bootm $qemu_kernel_addr - $fdt_addr_r\0" - -#endif /* __QEMU_PPCE500_H */ diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h deleted file mode 100644 index fa9b9af..0000000 --- a/include/configs/qemu-riscv.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018, Bin Meng - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#ifdef CONFIG_SPL - -#define CONFIG_SPL_MAX_SIZE 0x00100000 -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 - -#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x80200000 - -#endif - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - -/* Environment options */ -#define CONFIG_ENV_SIZE SZ_128K - -#ifndef CONFIG_SPL_BUILD -#define BOOT_TARGET_DEVICES(func) \ - func(QEMU, qemu, na) \ - func(VIRTIO, virtio, 0) \ - func(DHCP, dhcp, na) - -#include - -#define BOOTENV_DEV_QEMU(devtypeu, devtypel, instance) \ - "bootcmd_qemu=" \ - "if env exists kernel_start; then " \ - "bootm ${kernel_start} - ${fdtcontroladdr};" \ - "fi;\0" - -#define BOOTENV_DEV_NAME_QEMU(devtypeu, devtypel, instance) \ - "qemu " - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ - BOOTENV -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h deleted file mode 100644 index c557420..0000000 --- a/include/configs/qemu-x86.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Bin Meng - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define BOOT_TARGET_DEVICES(func) \ - func(USB, usb, 0) \ - func(SCSI, scsi, 0) \ - func(VIRTIO, virtio, 0) \ - func(IDE, ide, 0) \ - func(DHCP, dhcp, na) - -#include -#include - -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE SZ_256K - -#define CONFIG_PREBOOT "pci enum" - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -/* - * ATA/SATA support for QEMU x86 targets - * - Only legacy IDE controller is supported for QEMU '-M pc' target - * - AHCI controller is supported for QEMU '-M q35' target - */ -#define CONFIG_SYS_IDE_MAXBUS 2 -#define CONFIG_SYS_IDE_MAXDEVICE 4 -#define CONFIG_SYS_ATA_BASE_ADDR 0 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0 -#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 -#define CONFIG_ATAPI - -#define CONFIG_SPL_BOARD_LOAD_IMAGE - -#endif /* __CONFIG_H */ diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h deleted file mode 100644 index 0b16fb0..0000000 --- a/include/configs/r2dplus.h +++ /dev/null @@ -1,69 +0,0 @@ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_CPU_SH7751 1 -#define __LITTLE_ENDIAN__ 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* SCIF */ -#define CONFIG_CONS_SCIF1 1 - -#define CONFIG_ENV_OVERWRITE 1 - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x8C000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#define CONFIG_SYS_PBSIZE 256 - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024) -/* Address of u-boot image in Flash */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* - * NOR Flash ( Spantion S29GL256P ) - */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_MAX_FLASH_BANKS (1) -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } - -#define CONFIG_ENV_SECT_SIZE 0x40000 -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* - * SuperH Clock setting - */ -#define CONFIG_SYS_CLK_FREQ 60000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */ - -/* - * IDE support - */ -#define CONFIG_IDE_RESET 1 -#define CONFIG_SYS_PIO_MODE 1 -#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 -#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ -#define CONFIG_IDE_SWAP_IO - -/* - * SuperH PCI Bridge Configration - */ -#define CONFIG_SH7751_PCI - -#endif /* __CONFIG_H */ diff --git a/include/configs/r7780mp.h b/include/configs/r7780mp.h deleted file mode 100644 index 6ea7f38..0000000 --- a/include/configs/r7780mp.h +++ /dev/null @@ -1,116 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas R7780MP board - * - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * Copyright (C) 2008 Yusuke Goda - */ - -#ifndef __R7780RP_H -#define __R7780RP_H - -#define CONFIG_CPU_SH7780 1 -#define CONFIG_R7780MP 1 -#define CONFIG_SYS_R7780MP_OLD_FLASH 1 -#define __LITTLE_ENDIAN__ 1 - -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CONS_SCIF0 1 - -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_SYS_SDRAM_BASE (0x08000000) -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) - -/* Flash board support */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#ifdef CONFIG_SYS_R7780MP_OLD_FLASH -/* NOR Flash (S29PL127J60TFI130) */ -# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -# define CONFIG_SYS_MAX_FLASH_BANKS (2) -# define CONFIG_SYS_MAX_FLASH_SECT 270 -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\ - CONFIG_SYS_FLASH_BASE + 0x100000,\ - CONFIG_SYS_FLASH_BASE + 0x400000,\ - CONFIG_SYS_FLASH_BASE + 0x700000, } -#else /* CONFIG_SYS_R7780MP_OLD_FLASH */ -/* NOR Flash (Spantion S29GL256P) */ -# define CONFIG_SYS_MAX_FLASH_BANKS (1) -# define CONFIG_SYS_MAX_FLASH_SECT 256 -# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif /* CONFIG_SYS_R7780MP_OLD_FLASH */ - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) -/* Address of u-boot image in Flash */ -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (1204 * 1024) - -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) -#define CONFIG_SYS_RX_ETH_BUFFER (8) - -#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE -#undef CONFIG_SYS_FLASH_QUIET_TEST -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 33333333 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -/* PCI Controller */ -#if defined(CONFIG_CMD_PCI) -#define CONFIG_SH4_PCI -#define CONFIG_SH7780_PCI -#define CONFIG_SH7780_PCI_LSR 0x07f00001 -#define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE -#define CONFIG_PCI_SCAN_SHOW 1 -#define __mem_pci - -#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ - -#define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ -#define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE -#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE -#endif /* CONFIG_CMD_PCI */ - -#if defined(CONFIG_CMD_NET) -/* AX88796L Support(NE2000 base chip) */ -#define CONFIG_DRIVER_AX88796L -#define CONFIG_DRIVER_NE2000_BASE 0xA4100000 -#endif - -/* Compact flash Support */ -#if defined(CONFIG_IDE) -#define CONFIG_IDE_RESET 1 -#define CONFIG_SYS_PIO_MODE 1 -#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000 -#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */ -#define CONFIG_IDE_SWAP_IO -#endif /* CONFIG_IDE */ - -#endif /* __R7780RP_H */ diff --git a/include/configs/rastaban.h b/include/configs/rastaban.h deleted file mode 100644 index c69535a..0000000 --- a/include/configs/rastaban.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_RASTABAN_H -#define __CONFIG_RASTABAN_H - -#include "siemens-am33x-common.h" - -#define DDR_PLL_FREQ 303 - -/* FWD Button = 27 - * SRV Button = 87 */ -#define BOARD_DFU_BUTTON_GPIO 27 -#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ -/* In dfu mode keep led1 on */ -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - "button_dfu0=27\0" \ - "button_dfu1=87\0" \ - "led0=3,0,1\0" \ - "led1=4,0,0\0" \ - "led2=5,0,1\0" \ - "led3=62,0,1\0" \ - "led4=60,0,1\0" \ - "led5=63,0,1\0" - - /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - -#define CONFIG_PHY_SMSC - -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_OFFSET_REDUND 0x2E0000 -#define CONFIG_ENV_SIZE_REDUND 0x2000 -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - -/* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=rastaban\0" \ - "ubi_off=2048\0"\ - "nand_img_size=0x400000\0" \ - "optargs=\0" \ - "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 - -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ - -#define CONFIG_BOOTCOMMAND \ -"if dfubutton; then " \ - "run dfu_start; " \ - "reset; " \ -"fi;" \ -"run nand_boot;" \ -"run nand_boot_backup;" \ -"reset;" - -#else - -#define CONFIG_BOOTCOMMAND \ - "setenv autoload no; " \ - "dhcp; " \ - "if tftp 80000000 debrick.scr; then " \ - "source 80000000; " \ - "fi" -#endif -#endif /* CONFIG_SPL_BUILD */ -#endif /* ! __CONFIG_RASTABAN_H */ diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h deleted file mode 100644 index 71a5909..0000000 --- a/include/configs/rcar-gen2-common.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/rcar-gen2-common.h - * - * Copyright (C) 2013,2014 Renesas Electronics Corporation - */ - -#ifndef __RCAR_GEN2_COMMON_H -#define __RCAR_GEN2_COMMON_H - -#include - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#ifdef CONFIG_SPL -#define CONFIG_SPL_TARGET "spl/u-boot-spl.srec" -#endif - -#ifndef CONFIG_PINCTRL_PFC -#define CONFIG_SH_GPIO_PFC -#endif - -/* console */ -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 38400, 115200 } - -#define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x50000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - -/* ENV setting */ -#define CONFIG_ENV_ADDR 0xC0000 - -/* Common ENV setting */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_SECT_SIZE (256 * 1024) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN) - -/* SF MTD */ -#if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD) -#else -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#undef CONFIG_SPI_FLASH_MTD -#endif - -/* Timer */ -#define CONFIG_TMU_TIMER -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ -#define CONFIG_SYS_TIMER_RATE (CONFIG_SYS_CLK_FREQ / 8) - -#endif /* __RCAR_GEN2_COMMON_H */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h deleted file mode 100644 index 95bd97c..0000000 --- a/include/configs/rcar-gen3-common.h +++ /dev/null @@ -1,82 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/rcar-gen3-common.h - * This file is R-Car Gen3 common configuration file. - * - * Copyright (C) 2015-2017 Renesas Electronics Corporation - */ - -#ifndef __RCAR_GEN3_COMMON_H -#define __RCAR_GEN3_COMMON_H - -#include - -#define CONFIG_REMAKE_ELF - -#ifdef CONFIG_SPL -#define CONFIG_SPL_TARGET "spl/u-boot-spl.scif" -#endif - -/* boot option */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 -#define GICD_BASE 0xF1010000 -#define GICC_BASE 0xF1020000 - -/* console */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400 } - -/* MEMORY */ -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -#define DRAM_RSV_SIZE 0x08000000 -#define CONFIG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) -#define CONFIG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) -#define CONFIG_SYS_LOAD_ADDR 0x58000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_VERY_BIG_RAM -#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -/* ENV setting */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" - -#define CONFIG_BOOTCOMMAND \ - "tftp 0x48080000 Image; " \ - "tftp 0x48000000 Image-"CONFIG_DEFAULT_FDT_FILE"; " \ - "booti 0x48080000 - 0x48000000" - -/* SPL support */ -#if defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796) || defined(CONFIG_R8A77965) -#define CONFIG_SPL_BSS_START_ADDR 0xe633f000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 -#else -#define CONFIG_SPL_BSS_START_ADDR 0xe631f000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 -#endif -#define CONFIG_SPL_STACK 0xe6304000 -#define CONFIG_SPL_MAX_SIZE 0x7000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_CONS_SCIF2 -#define CONFIG_SH_SCIF_CLK_FREQ 65000000 -#endif - -#endif /* __RCAR_GEN3_COMMON_H */ diff --git a/include/configs/rk3036_common.h b/include/configs/rk3036_common.h deleted file mode 100644 index 7f148ef..0000000 --- a/include/configs/rk3036_common.h +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Rockchip Electronics Co., Ltd - */ -#ifndef __CONFIG_RK3036_COMMON_H -#define __CONFIG_RK3036_COMMON_H - -#include -#include "rockchip-common.h" - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 -#define COUNTER_FREQUENCY 24000000 -#define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_HZ_CLOCK 24000000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 -#define CONFIG_SPL_STACK 0x10081fff - -#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (4 << 10) -#define CONFIG_ROCKCHIP_CHIP_TAG "RK30" - -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define SDRAM_BANK_SIZE (512UL << 20UL) -#define SDRAM_MAX_SIZE (CONFIG_NR_DRAM_BANKS * SDRAM_BANK_SIZE) - -#ifndef CONFIG_SPL_BUILD - -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x60000000\0" \ - "pxefile_addr_r=0x60100000\0" \ - "fdt_addr_r=0x61f00000\0" \ - "kernel_addr_r=0x62000000\0" \ - "ramdisk_addr_r=0x64000000\0" - -#include - -/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, - * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_high=0x7fffffff\0" \ - "partitions=" PARTS_DEFAULT \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV -#endif - -#endif diff --git a/include/configs/rk3128_common.h b/include/configs/rk3128_common.h deleted file mode 100644 index d0c9e5c..0000000 --- a/include/configs/rk3128_common.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_RK3128_COMMON_H -#define __CONFIG_RK3128_COMMON_H - -#include "rockchip-common.h" - -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_ROCKCHIP_STIMER_BASE 0x200440a0 -#define COUNTER_FREQUENCY 24000000 -#define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_HZ_CLOCK 24000000 - -#define CONFIG_IRAM_BASE 0x10080000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - -/* RAW SD card / eMMC locations. */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define SDRAM_MAX_SIZE 0x80000000 - -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -#ifndef CONFIG_SPL_BUILD - -/* usb mass storage */ - -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x60500000\0" \ - "pxefile_addr_r=0x60600000\0" \ - "fdt_addr_r=0x61f00000\0" \ - "kernel_addr_r=0x62000000\0" \ - "ramdisk_addr_r=0x64000000\0" - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - BOOTENV - -#endif - -#endif diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h deleted file mode 100644 index 3bcc048..0000000 --- a/include/configs/rk3188_common.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef __CONFIG_RK3188_COMMON_H -#define __CONFIG_RK3188_COMMON_H - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#include -#include "rockchip-common.h" - -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_CBSIZE 1024 - -#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM -/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ -#endif -#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 -#define CONFIG_SYS_LOAD_ADDR 0x60800800 - -#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) -#define CONFIG_ROCKCHIP_CHIP_TAG "RK31" -#define CONFIG_IRAM_BASE 0x10080000 - -/* spl size 32kb sram - 2kb bootrom */ -#define CONFIG_SPL_MAX_SIZE (0x8000 - 0x800) -#define CONFIG_ROCKCHIP_SERIAL 1 - -#define CONFIG_SPL_STACK 0x10087fff - -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define SDRAM_BANK_SIZE (2UL << 30) -#define SDRAM_MAX_SIZE 0x80000000 - -#ifndef CONFIG_SPL_BUILD -/* usb otg */ - -/* usb host support */ -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x60000000\0" \ - "pxefile_addr_r=0x60100000\0" \ - "fdt_addr_r=0x61f00000\0" \ - "kernel_addr_r=0x62000000\0" \ - "ramdisk_addr_r=0x64000000\0" - -#include - -/* Linux fails to load the fdt if it's loaded above 256M on a Rock board, - * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_high=0x6fffffff\0" \ - "initrd_high=0x6fffffff\0" \ - "partitions=" PARTS_DEFAULT \ - ENV_MEM_LAYOUT_SETTINGS \ - ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV - -#endif /* CONFIG_SPL_BUILD */ - -#endif diff --git a/include/configs/rk322x_common.h b/include/configs/rk322x_common.h deleted file mode 100644 index 7e0c831..0000000 --- a/include/configs/rk322x_common.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2017 Rockchip Electronics Co., Ltd - */ -#ifndef __CONFIG_RK322X_COMMON_H -#define __CONFIG_RK322X_COMMON_H - -#include -#include "rockchip-common.h" - -#define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - -#define CONFIG_ROCKCHIP_STIMER_BASE 0x110d0020 -#define COUNTER_FREQUENCY 24000000 -#define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_HZ_CLOCK 24000000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x61100000 -#define CONFIG_SYS_LOAD_ADDR 0x61800800 -#define CONFIG_SPL_MAX_SIZE 0x100000 - -#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (28 << 10) -#define CONFIG_ROCKCHIP_CHIP_TAG "RK32" -#define CONFIG_IRAM_BASE 0x10080000 - -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define SDRAM_BANK_SIZE (512UL << 20UL) -#define SDRAM_MAX_SIZE 0x80000000 - -#ifndef CONFIG_SPL_BUILD - -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x60000000\0" \ - "pxefile_addr_r=0x60100000\0" \ - "fdt_addr_r=0x61f00000\0" \ - "kernel_addr_r=0x62000000\0" \ - "ramdisk_addr_r=0x64000000\0" - -#include - -/* Linux fails to load the fdt if it's loaded above 512M on a evb-rk3036 board, - * so limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_high=0x7fffffff\0" \ - "partitions=" PARTS_DEFAULT \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV -#endif - -#endif diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h deleted file mode 100644 index 910fe58..0000000 --- a/include/configs/rk3288_common.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef __CONFIG_RK3288_COMMON_H -#define __CONFIG_RK3288_COMMON_H - -#include -#include "rockchip-common.h" - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64MB */ - -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff810020 -#define COUNTER_FREQUENCY 24000000 -#define CONFIG_SYS_ARCH_TIMER -#define CONFIG_SYS_HZ_CLOCK 24000000 - -#ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM -/* Bootrom will load u-boot binary to 0x0 once return from SPL */ -#endif -#define CONFIG_SYS_INIT_SP_ADDR 0x00100000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 -#define CONFIG_SPL_STACK 0xff718000 - -#define CONFIG_IRAM_BASE 0xff700000 - -/* RAW SD card / eMMC locations. */ - -/* FAT sd card locations. */ -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SYS_SDRAM_BASE 0 -#define SDRAM_BANK_SIZE (2UL << 30) -#define SDRAM_MAX_SIZE 0xfe000000 - -#define CONFIG_SYS_MONITOR_LEN (600 * 1024) - -#ifndef CONFIG_SPL_BUILD - -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00000000\0" \ - "pxefile_addr_r=0x00100000\0" \ - "fdt_addr_r=0x01f00000\0" \ - "kernel_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x04000000\0" - -#include - -/* Linux fails to load the fdt if it's loaded above 256M on a Rock 2 board, so - * limit the fdt reallocation to that */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x0fffffff\0" \ - "initrd_high=0x0fffffff\0" \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ENV_MEM_LAYOUT_SETTINGS \ - ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV -#endif - -#endif diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h deleted file mode 100644 index 3ff3331..0000000 --- a/include/configs/rk3328_common.h +++ /dev/null @@ -1,54 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_RK3328_COMMON_H -#define __CONFIG_RK3328_COMMON_H - -#include "rockchip-common.h" - -#define CONFIG_IRAM_BASE 0xff090000 - -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff1d0020 - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x2000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - -/* FAT sd card locations. */ -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define SDRAM_MAX_SIZE 0xff000000 - -#ifndef CONFIG_SPL_BUILD - -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00500000\0" \ - "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x01f00000\0" \ - "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x04000000\0" - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - BOOTENV - -#endif - -/* rockchip ohci host driver */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 - -#endif diff --git a/include/configs/rk3368_common.h b/include/configs/rk3368_common.h deleted file mode 100644 index e4b2114..0000000 --- a/include/configs/rk3368_common.h +++ /dev/null @@ -1,52 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Andreas Färber - */ - -#ifndef __CONFIG_RK3368_COMMON_H -#define __CONFIG_RK3368_COMMON_H - -#include "rockchip-common.h" - -#define CONFIG_SYS_CACHELINE_SIZE 64 - -#include -#include - -#define CONFIG_SYS_SDRAM_BASE 0 -#define SDRAM_MAX_SIZE 0xff000000 -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff830020 -#define COUNTER_FREQUENCY 24000000 - -#define CONFIG_IRAM_BASE 0xff8c0000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00280000 - -#define CONFIG_SPL_MAX_SIZE 0x60000 -#define CONFIG_SPL_BSS_START_ADDR 0x400000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x20000 -#define CONFIG_SPL_STACK 0x00188000 - -#ifndef CONFIG_SPL_BUILD -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00500000\0" \ - "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x5600000\0" \ - "kernel_addr_r=0x280000\0" \ - "ramdisk_addr_r=0x5bf0000\0" - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV - -#endif - -#endif diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h deleted file mode 100644 index 126c347..0000000 --- a/include/configs/rk3399_common.h +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_RK3399_COMMON_H -#define __CONFIG_RK3399_COMMON_H - -#include "rockchip-common.h" - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define COUNTER_FREQUENCY 24000000 -#define CONFIG_ROCKCHIP_STIMER_BASE 0xff8680a0 - -#define CONFIG_IRAM_BASE 0xff8c0000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x00300000 -#define CONFIG_SYS_LOAD_ADDR 0x00800800 - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) -#define CONFIG_SPL_STACK 0x00400000 -#define CONFIG_SPL_MAX_SIZE 0x100000 -#define CONFIG_SPL_BSS_START_ADDR 0x00400000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 -#else -#define CONFIG_SPL_STACK 0xff8effff -#define CONFIG_SPL_MAX_SIZE 0x30000 - 0x2000 -/* BSS setup */ -#define CONFIG_SPL_BSS_START_ADDR 0xff8e0000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x10000 -#endif - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ - -/* MMC/SD IP block */ -#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000 - -/* RAW SD card / eMMC locations. */ - -/* FAT sd card locations. */ -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SYS_SDRAM_BASE 0 -#define SDRAM_MAX_SIZE 0xf8000000 - -#ifndef CONFIG_SPL_BUILD - -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x00500000\0" \ - "pxefile_addr_r=0x00600000\0" \ - "fdt_addr_r=0x01f00000\0" \ - "kernel_addr_r=0x02080000\0" \ - "ramdisk_addr_r=0x04000000\0" - -#ifndef ROCKCHIP_DEVICE_SETTINGS -#define ROCKCHIP_DEVICE_SETTINGS -#endif - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - ROCKCHIP_DEVICE_SETTINGS \ - BOOTENV - -#endif - -/* enable usb config for usb ether */ - -#endif diff --git a/include/configs/rock.h b/include/configs/rock.h deleted file mode 100644 index d917757..0000000 --- a/include/configs/rock.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/rock2.h b/include/configs/rock2.h deleted file mode 100644 index 917caf4..0000000 --- a/include/configs/rock2.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/rock960_rk3399.h b/include/configs/rock960_rk3399.h deleted file mode 100644 index 746d24c..0000000 --- a/include/configs/rock960_rk3399.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Manivannan Sadhasivam - */ - -#ifndef __ROCK960_RK3399_H -#define __ROCK960_RK3399_H - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 1 - -#define SDRAM_BANK_SIZE (2UL << 30) - -#endif diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h deleted file mode 100644 index 68e1105..0000000 --- a/include/configs/rockchip-common.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef _ROCKCHIP_COMMON_H_ -#define _ROCKCHIP_COMMON_H_ -#include - -#define CONFIG_SYS_NS16550_MEM32 - -#ifndef CONFIG_SPL_BUILD - -/* First try to boot from SD (index 0), then eMMC (index 1) */ -#if CONFIG_IS_ENABLED(CMD_MMC) - #define BOOT_TARGET_MMC(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) -#else - #define BOOT_TARGET_MMC(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_USB) - #define BOOT_TARGET_USB(func) func(USB, usb, 0) -#else - #define BOOT_TARGET_USB(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_PXE) - #define BOOT_TARGET_PXE(func) func(PXE, pxe, na) -#else - #define BOOT_TARGET_PXE(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_DHCP) - #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) -#else - #define BOOT_TARGET_DHCP(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_MMC(func) \ - BOOT_TARGET_USB(func) \ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) - -#ifdef CONFIG_ARM64 -#define ROOT_UUID "B921B045-1DF0-41C3-AF44-4C6F280D3FAE;\0" -#else -#define ROOT_UUID "69DAD710-2CE4-4E3C-B16C-21A1D49ABED3;\0" -#endif -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=loader1,start=32K,size=4000K,uuid=${uuid_gpt_loader1};" \ - "name=loader2,start=8MB,size=4MB,uuid=${uuid_gpt_loader2};" \ - "name=trust,size=4M,uuid=${uuid_gpt_atf};" \ - "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \ - "name=rootfs,size=-,uuid="ROOT_UUID - -#endif - -#endif /* _ROCKCHIP_COMMON_H_ */ diff --git a/include/configs/rpi.h b/include/configs/rpi.h deleted file mode 100644 index 77d2d54..0000000 --- a/include/configs/rpi.h +++ /dev/null @@ -1,192 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2012-2016 Stephen Warren - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -#if defined(CONFIG_TARGET_RPI_2) || defined(CONFIG_TARGET_RPI_3_32B) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* Architecture, CPU, etc.*/ - -/* Use SoC timer for AArch32, but architected timer for AArch64 */ -#ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER \ - (&((struct bcm2835_timer_regs *)BCM2835_TIMER_PHYSADDR)->clo) -#endif - -/* - * 2835 is a SKU in a series for which the 2708 is the first or primary SoC, - * so 2708 has historically been used rather than a dedicated 2835 ID. - * - * We don't define a machine type for bcm2709/bcm2836 since the RPi Foundation - * chose to use someone else's previously registered machine ID (3139, MX51_GGC) - * rather than obtaining a valid ID:-/ - * - * For the bcm2837, hopefully a machine type is not needed, since everything - * is DT. - */ -#ifdef CONFIG_BCM2835 -#define CONFIG_MACH_TYPE MACH_TYPE_BCM2708 -#endif - -/* Memory layout */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE -/* - * The board really has 256M. However, the VC (VideoCore co-processor) shares - * the RAM, and uses a configurable portion at the top. We tell U-Boot that a - * smaller amount of RAM is present in order to avoid stomping on the area - * the VC uses. - */ -#define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_SDRAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MALLOC_LEN SZ_4M -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x00200000 -#define CONFIG_LOADADDR 0x00200000 - -#ifdef CONFIG_ARM64 -#define CONFIG_SYS_BOOTM_LEN SZ_64M -#endif - -/* Devices */ -/* GPIO */ -#define CONFIG_BCM2835_GPIO -/* LCD */ -#define CONFIG_LCD_DT_SIMPLEFB -#define CONFIG_VIDEO_BCM2835 - -#ifdef CONFIG_CMD_USB -#define CONFIG_TFTP_TSIZE -#endif - -/* Console configuration */ -#define CONFIG_SYS_CBSIZE 1024 - -/* Environment */ -#define CONFIG_ENV_SIZE SZ_16K -#define CONFIG_SYS_LOAD_ADDR 0x1000000 - -/* Shell */ - -/* ATAGs support for bootm/bootz */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -/* Environment */ -#define ENV_DEVICE_SETTINGS \ - "stdin=serial,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#ifdef CONFIG_ARM64 -#define FDT_HIGH "ffffffffffffffff" -#define INITRD_HIGH "ffffffffffffffff" -#else -#define FDT_HIGH "ffffffff" -#define INITRD_HIGH "ffffffff" -#endif - -/* - * Memory layout for where various images get loaded by boot scripts: - * - * I suspect address 0 is used as the SMP pen on the RPi2, so avoid this. - * - * Older versions of the boot firmware place the firmware-loaded DTB at 0x100, - * newer versions place it in high memory. So prevent U-Boot from doing its own - * DTB + initrd relocation so that we won't accidentally relocate the initrd - * over the firmware-loaded DTB and generally try to lay out things starting - * from the bottom of RAM. - * - * kernel_addr_r has different constraints on ARM and Aarch64. For 32-bit ARM, - * it must be within the first 128M of RAM in order for the kernel's - * CONFIG_AUTO_ZRELADDR option to work. The kernel itself will be decompressed - * to 0x8000 but the decompressor clobbers 0x4000-0x8000 as well. The - * decompressor also likes to relocate itself to right past the end of the - * decompressed kernel, so in total the sum of the compressed and and - * decompressed kernel needs to be reserved. - * - * For Aarch64, the kernel image is uncompressed and must be loaded at - * text_offset bytes (specified in the header of the Image) into a 2MB - * boundary. The 'booti' command relocates the image if necessary. Linux uses - * a default text_offset of 0x80000. In summary, loading at 0x80000 - * satisfies all these constraints and reserving memory up to 0x02400000 - * permits fairly large (roughly 36M) kernels. - * - * scriptaddr and pxefile_addr_r can be pretty much anywhere that doesn't - * conflict with something else. Reserving 1M for each of them at - * 0x02400000-0x02500000 and 0x02500000-0x02600000 should be plenty. - * - * On ARM, both the DTB and any possible initrd must be loaded such that they - * fit inside the lowmem mapping in Linux. In practice, this usually means not - * more than ~700M away from the start of the kernel image but this number can - * be larger OR smaller depending on e.g. the 'vmalloc=xxxM' command line - * parameter given to the kernel. So reserving memory from low to high - * satisfies this constraint again. Reserving 1M at 0x02600000-0x02700000 for - * the DTB leaves rest of the free RAM to the initrd starting at 0x02700000. - * Even with the smallest possible CPU-GPU memory split of the CPU getting - * only 64M, the remaining 25M starting at 0x02700000 should allow quite - * large initrds before they start colliding with U-Boot. - */ -#define ENV_MEM_LAYOUT_SETTINGS \ - "fdt_high=" FDT_HIGH "\0" \ - "initrd_high=" INITRD_HIGH "\0" \ - "kernel_addr_r=0x00080000\0" \ - "scriptaddr=0x02400000\0" \ - "pxefile_addr_r=0x02500000\0" \ - "fdt_addr_r=0x02600000\0" \ - "ramdisk_addr_r=0x02700000\0" - -#if CONFIG_IS_ENABLED(CMD_MMC) - #define BOOT_TARGET_MMC(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) -#else - #define BOOT_TARGET_MMC(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_USB) - #define BOOT_TARGET_USB(func) func(USB, usb, 0) -#else - #define BOOT_TARGET_USB(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_PXE) - #define BOOT_TARGET_PXE(func) func(PXE, pxe, na) -#else - #define BOOT_TARGET_PXE(func) -#endif - -#if CONFIG_IS_ENABLED(CMD_DHCP) - #define BOOT_TARGET_DHCP(func) func(DHCP, dhcp, na) -#else - #define BOOT_TARGET_DHCP(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_MMC(func) \ - BOOT_TARGET_USB(func) \ - BOOT_TARGET_PXE(func) \ - BOOT_TARGET_DHCP(func) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "dhcpuboot=usb start; dhcp u-boot.uimg; bootm\0" \ - ENV_DEVICE_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV - - -#endif diff --git a/include/configs/rut.h b/include/configs/rut.h deleted file mode 100644 index 296bdc2..0000000 --- a/include/configs/rut.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * siemens rut - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_RUT_H -#define __CONFIG_RUT_H - -#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT - -#include "siemens-am33x-common.h" - -#define RUT_IOCTRL_VAL 0x18b -#define DDR_PLL_FREQ 303 - - /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */ - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ - -#define CONFIG_PHY_NATSEMI - -#define CONFIG_FACTORYSET - -/* Watchdog */ -#define WATCHDOG_TRIGGER_GPIO 14 - -#ifndef CONFIG_SPL_BUILD - -/* Use common default */ - -/* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=rut\0" \ - "ubi_off=2048\0"\ - "nand_img_size=0x500000\0" \ - "splashpos=m,m\0" \ - "optargs=fixrtc --no-log consoleblank=0 \0" \ - CONFIG_ENV_SETTINGS_V1 \ - CONFIG_ENV_SETTINGS_NAND_V1 \ - "mmc_dev=0\0" \ - "mmc_root=/dev/mmcblk0p2 rw\0" \ - "mmc_root_fs_type=ext4 rootwait\0" \ - "mmc_load_uimage=" \ - "mmc rescan; " \ - "setenv bootfile uImage;" \ - "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \ - "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "mmc_args=run bootargs_defaults;" \ - "mtdparts default;" \ - "setenv bootargs ${bootargs} " \ - "root=${mmc_root} ${mtdparts}" \ - "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \ - "eth=${ethaddr} " \ - "\0" \ - "mmc_boot=run mmc_args; " \ - "run mmc_load_uimage; " \ - "bootm ${kloadaddr}\0" \ - "" - -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ - -#define CONFIG_BOOTCOMMAND \ - "if mmc rescan; then " \ - "echo SD/MMC found on device ${mmc_dev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run mmc_load_uimage; then " \ - "run mmc_args;" \ - "bootm ${kloadaddr};" \ - "fi;" \ - "fi;" \ - "run nand_boot;" \ - "reset;" - -#else - -#define CONFIG_BOOTCOMMAND \ - "setenv autoload no; " \ - "dhcp; " \ - "if tftp 80000000 debrick.scr; then " \ - "source 80000000; " \ - "fi" -#endif - -#endif /* CONFIG_SPL_BUILD */ - -#if defined(CONFIG_VIDEO) -#define CONFIG_VIDEO_DA8XX -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_VIDEO_BMP_LOGO -#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE - -#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */ -#define CONFIG_FORMIKE -#define DISPL_PLL_SPREAD_SPECTRUM -#endif - -#endif /* ! __CONFIG_RUT_H */ diff --git a/include/configs/rv1108_common.h b/include/configs/rv1108_common.h deleted file mode 100644 index 758e85e..0000000 --- a/include/configs/rv1108_common.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ -#ifndef __CONFIG_RV1108_COMMON_H -#define __CONFIG_RV1108_COMMON_H - -#include -#include "rockchip-common.h" - -#define CONFIG_IRAM_BASE 0x10080000 - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) -/* TIMER1,initialized by ddr initialize code */ -#define CONFIG_SYS_TIMER_BASE 0x10350020 -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) - -#define CONFIG_SYS_SDRAM_BASE 0x60000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000) - -/* rockchip ohci host driver */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - -#ifndef CONFIG_SPL_BUILD -#define ENV_MEM_LAYOUT_SETTINGS \ - "scriptaddr=0x60000000\0" \ - "fdt_addr_r=0x61f00000\0" \ - "kernel_addr_r=0x62000000\0" \ - "ramdisk_addr_r=0x64000000\0" - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "partitions=" PARTS_DEFAULT \ - BOOTENV -#endif diff --git a/include/configs/s32v234evb.h b/include/configs/s32v234evb.h deleted file mode 100644 index cc6d920..0000000 --- a/include/configs/s32v234evb.h +++ /dev/null @@ -1,189 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015-2016 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale S32V234 EVB board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_S32V234 - -/* Config GIC */ -#define CONFIG_GICV2 -#define GICD_BASE 0x7D001000 -#define GICC_BASE 0x7D002000 - -#define CONFIG_REMAKE_ELF -#undef CONFIG_RUN_FROM_IRAM_ONLY - -#define CONFIG_RUN_FROM_DDR1 -#undef CONFIG_RUN_FROM_DDR0 - -/* Run by default from DDR1 */ -#ifdef CONFIG_RUN_FROM_DDR0 -#define DDR_BASE_ADDR 0x80000000 -#else -#define DDR_BASE_ADDR 0xC0000000 -#endif - -#define CONFIG_MACH_TYPE 4146 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Config CACHE */ -#define CONFIG_CMD_CACHE - -#define CONFIG_SYS_FULL_VA - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (1000000000) /* 1000MHz */ -#define CONFIG_SYS_FSL_ERRATUM_A008585 - -/* Size of malloc() pool */ -#ifdef CONFIG_RUN_FROM_IRAM_ONLY -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1 * 1024 * 1024) -#else -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#endif - -#define LINFLEXUART_BASE LINFLEXD0_BASE_ADDR - -#define CONFIG_DEBUG_UART_LINFLEXUART -#define CONFIG_DEBUG_UART_BASE LINFLEXUART_BASE - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_UART_PORT (1) - -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#define CONFIG_CMD_MMC -/* #define CONFIG_CMD_EXT2 EXT2 Support */ - -#if 0 - -/* Ethernet config */ -#define CONFIG_CMD_MII -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 -#endif - -#if 0 /* Disable until the FLASH will be implemented */ -#define CONFIG_SYS_USE_NAND -#endif - -#ifdef CONFIG_SYS_USE_NAND -/* Nand Flash Configs */ -#define CONFIG_JFFS2_NAND -#define MTD_NAND_FSL_NFC_SWECC 1 -#define CONFIG_NAND_FSL_NFC -#define CONFIG_SYS_NAND_BASE 0x400E0000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE -#define CONFIG_SYS_NAND_SELECT_DEVICE -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ -#endif - -#define CONFIG_LOADADDR 0xC307FFC0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "boot_scripts=boot.scr.uimg boot.scr\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - "console=ttyLF0,115200\0" \ - "fdt_file=s32v234-evb.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr_r=0xC2000000\0" \ - "kernel_addr_r=0xC307FFC0\0" \ - "ramdisk_addr_r=0xC4000000\0" \ - "ramdisk=rootfs.uimg\0"\ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "loadramdisk=fatload mmc ${mmcdev}:${mmcpart} ${ramdisk_addr} ${ramdisk}\0" \ - "jtagboot=echo Booting using jtag...; " \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "jtagsdboot=echo Booting loading Linux with ramdisk from SD...; " \ - "run loaduimage; run loadramdisk; run loadfdt;"\ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "boot_net_usb_start=true\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd" - -#include - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "=> " - -#define CONFIG_SYS_MEMTEST_START (DDR_BASE_ADDR) -#define CONFIG_SYS_MEMTEST_END (DDR_BASE_ADDR + 0x7C00000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -#ifdef CONFIG_RUN_FROM_IRAM_ONLY -#define CONFIG_SYS_MALLOC_BASE (DDR_BASE_ADDR) -#endif - -#if 0 -/* Configure PXE */ -#define CONFIG_BOOTP_PXE_CLIENTARCH 0x100 -#endif - -/* Physical memory map */ -/* EVB board has 2x256 MB DDR chips, DDR0 and DDR1, u-boot is using just one */ -#define PHYS_SDRAM (DDR_BASE_ADDR) -#define PHYS_SDRAM_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_ENV_OFFSET (12 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - - -#define CONFIG_BOOTP_BOOTFILESIZE - -#endif diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h deleted file mode 100644 index be6f011..0000000 --- a/include/configs/s5p_goni.h +++ /dev/null @@ -1,180 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009 Samsung Electronics - * Minkyu Kang - * Kyungmin Park - * - * Configuation settings for the SAMSUNG Universal (s5pc100) board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_S5PC110 1 /* which is in a S5PC110 */ - -#include -#include /* get chip and board defs */ - -/* input clock of PLL: has 24MHz input clock at S5PC110 */ -#define CONFIG_SYS_CLK_FREQ_C110 24000000 - -/* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 - -/* Text Base */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_INITRD_TAG - -/* Size of malloc() pool before and after relocation */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) - -/* - * select serial console configuration - */ - -/* MMC */ -#define SDHCI_MAX_HOSTS 4 - -/* PWM */ -#define CONFIG_PWM 1 - -/* USB Composite download gadget - g_dnl */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB Samsung's IDs */ - -#define CONFIG_G_DNL_THOR_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 - -/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ - -/* partitions definitions */ -#define PARTS_CSA "csa-mmc" -#define PARTS_BOOTLOADER "u-boot" -#define PARTS_BOOT "boot" -#define PARTS_ROOT "platform" -#define PARTS_DATA "data" -#define PARTS_CSC "csc" -#define PARTS_UMS "ums" - -#define CONFIG_DFU_ALT \ - "u-boot raw 0x80 0x400;" \ - "uImage ext4 0 2;" \ - "exynos3-goni.dtb ext4 0 2;" \ - ""PARTS_ROOT" part 0 5\0" - -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name="PARTS_CSA",size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ - "name="PARTS_BOOTLOADER",size=60MiB," \ - "uuid=${uuid_gpt_"PARTS_BOOTLOADER"};" \ - "name="PARTS_BOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ - "name="PARTS_ROOT",size=1GiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ - "name="PARTS_DATA",size=3GiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ - "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ - "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ - -#define CONFIG_BOOTCOMMAND "run mmcboot" - -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - -#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext4" \ - " ${console} ${meminfo}" - -#define CONFIG_COMMON_BOOT "${console} ${meminfo} ${mtdparts}" - -#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x100000;" \ - " onenand write 0x32008000 0x0 0x100000\0" - -#define CONFIG_MISC_COMMON - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_UPDATEB \ - "updatek=" \ - "onenand erase 0xc00000 0x600000;" \ - "onenand write 0x31008000 0xc00000 0x600000\0" \ - "updateu=" \ - "onenand erase 0x01560000 0x1eaa0000;" \ - "onenand write 0x32000000 0x1260000 0x8C0000\0" \ - "bootk=" \ - "run loaduimage;" \ - "bootm 0x30007FC0\0" \ - "flashboot=" \ - "set bootargs root=/dev/mtdblock${bootblock} " \ - "rootfstype=${rootfstype} ${opts} " \ - "${lcdinfo} " CONFIG_COMMON_BOOT "; run bootk\0" \ - "ubifsboot=" \ - "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - "${opts} ${lcdinfo} " \ - CONFIG_COMMON_BOOT "; run bootk\0" \ - "tftpboot=" \ - "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - "${opts} ${lcdinfo} " CONFIG_COMMON_BOOT \ - "; tftp 0x30007FC0 uImage; bootm 0x30007FC0\0" \ - "ramboot=" \ - "set bootargs " CONFIG_RAMDISK_BOOT \ - "initrd=0x33000000,8M ramdisk=8192\0" \ - "mmcboot=" \ - "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ - "rootfstype=${rootfstype} ${opts} ${lcdinfo} " \ - CONFIG_COMMON_BOOT "; run bootk\0" \ - "boottrace=setenv opts initcall_debug; run bootcmd\0" \ - "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ - "verify=n\0" \ - "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE \ - "meminfo=mem=80M mem=256M@0x40000000 mem=128M@0x50000000\0" \ - "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x30007FC0 uImage\0" \ - "mmcdev=0\0" \ - "mmcbootpart=2\0" \ - "mmcrootpart=5\0" \ - "partitions=" PARTS_DEFAULT \ - "bootblock=9\0" \ - "ubiblock=8\0" \ - "ubi=enabled\0" \ - "opts=always_resume=1\0" \ - "dfu_alt_info=" CONFIG_DFU_ALT "\0" - -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4000000) - -/* Goni has 3 banks of DRAM, but swap the bank */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* OneDRAM Bank #0 */ -#define PHYS_SDRAM_1_SIZE (80 << 20) /* 80 MB in Bank #0 */ -#define PHYS_SDRAM_2 0x40000000 /* mDDR DMC1 Bank #1 */ -#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in Bank #1 */ -#define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */ -#define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ - -/* FLASH and environment organization */ -#define CONFIG_MMC_DEFAULT_DEV 0 -#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 -#define CONFIG_SYS_ONENAND_BASE 0xB0000000 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - -#endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h deleted file mode 100644 index 832032d..0000000 --- a/include/configs/s5pc210_universal.h +++ /dev/null @@ -1,172 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Samsung Electronics - * Minkyu Kang - * - * Configuation settings for the SAMSUNG Universal (EXYNOS4210) board. - */ - -#ifndef __CONFIG_UNIVERSAL_H -#define __CONFIG_UNIVERSAL_H - -#include - -#define CONFIG_TIZEN /* TIZEN lib */ - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_L2CACHE_OFF 1 - -/* Universal has 2 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE - -#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ - -/* select serial console configuration */ - -/* Console configuration */ - -#define CONFIG_BOOTCOMMAND "run mmcboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -/* Actual modem binary size is 16MiB. Add 2MiB for bad block handling */ - -#define NORMAL_MTDPARTS_DEFAULT CONFIG_MTDPARTS_DEFAULT - -#define MBRPARTS_DEFAULT "20M(permanent)"\ - ",20M(boot)"\ - ",1G(system)"\ - ",100M(swap)"\ - ",-(UMS)\0" - -#define CONFIG_ENV_UBI_MTD " ubi.mtd=${ubiblock} ubi.mtd=4 ubi.mtd=7" -#define CONFIG_BOOTBLOCK "10" -#define CONFIG_UBIBLOCK "9" - -#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ - -#define CONFIG_ENV_UBIFS_OPTION " rootflags=bulk_read,no_chk_data_crc " -#define CONFIG_ENV_FLASHBOOT CONFIG_ENV_UBI_MTD CONFIG_ENV_UBIFS_OPTION \ - "${mtdparts}" - -#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "updateb=" \ - "onenand erase 0x0 0x100000;" \ - "onenand write 0x42008000 0x0 0x100000\0" \ - "updatek=" \ - "onenand erase 0xc00000 0x500000;" \ - "onenand write 0x41008000 0xc00000 0x500000\0" \ - "bootk=" \ - "run loaduimage; bootm 0x40007FC0\0" \ - "updatebackup=" \ - "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ - "mmc dev 0 0\0" \ - "updatebootb=" \ - "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ - "lpj=lpj=3981312\0" \ - "ubifsboot=" \ - "set bootargs root=ubi0!rootfs rootfstype=ubifs ${lpj} " \ - CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ - CONFIG_ENV_COMMON_BOOT "; run bootk\0" \ - "tftpboot=" \ - "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - CONFIG_ENV_FLASHBOOT " ${opts} ${lcdinfo} " \ - CONFIG_ENV_COMMON_BOOT \ - "; tftp 0x40007FC0 uImage; bootm 0x40007FC0\0" \ - "nfsboot=" \ - "set bootargs root=/dev/nfs rw " \ - "nfsroot=${nfsroot},nolock,tcp " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ - "; run bootk\0" \ - "ramfsboot=" \ - "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \ - "${console} ${meminfo} " \ - "initrd=0x43000000,8M ramdisk=8192\0" \ - "mmcboot=" \ - "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ - "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run loaduimage; bootm 0x40007FC0\0" \ - "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ - "boottrace=setenv opts initcall_debug; run bootcmd\0" \ - "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ - "verify=n\0" \ - "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT \ - "mbrparts=" MBRPARTS_DEFAULT \ - "meminfo=crashkernel=32M@0x50000000\0" \ - "nfsroot=/nfsroot/arm\0" \ - "bootblock=" CONFIG_BOOTBLOCK "\0" \ - "ubiblock=" CONFIG_UBIBLOCK" \0" \ - "ubi=enabled\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ - "mmcdev=0\0" \ - "mmcbootpart=2\0" \ - "mmcrootpart=3\0" \ - "opts=always_resume=1" - -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND -#define CONFIG_SYS_ONENAND_BASE 0x0C000000 - -#define CONFIG_USB_GADGET_DWC2_OTG_PHY - -/* - * SPI Settings - */ -#define CONFIG_SOFT_SPI - -#ifndef __ASSEMBLY__ -void universal_spi_scl(int bit); -void universal_spi_sda(int bit); -int universal_spi_read(void); -#endif - -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - -/* Download menu - Samsung common */ -#define CONFIG_LCD_MENU - -/* Download menu - definitions for check keys */ -#ifndef __ASSEMBLY__ - -#define KEY_PWR_PMIC_NAME "MAX8998_PMIC" -#define KEY_PWR_STATUS_REG MAX8998_REG_STATUS1 -#define KEY_PWR_STATUS_MASK (1 << 7) -#define KEY_PWR_INTERRUPT_REG MAX8998_REG_IRQ1 -#define KEY_PWR_INTERRUPT_MASK (1 << 7) - -#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 -#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 -#endif /* __ASSEMBLY__ */ - -/* LCD console */ -#define LCD_BPP LCD_COLOR16 - -/* - * LCD Settings - */ -#define CONFIG_BMP_16BPP -#define CONFIG_LD9040 -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) - -#endif /* __CONFIG_H */ diff --git a/include/configs/sagem_f@st1704.h b/include/configs/sagem_f@st1704.h deleted file mode 100644 index 5a526d9..0000000 --- a/include/configs/sagem_f@st1704.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/salvator-x.h b/include/configs/salvator-x.h deleted file mode 100644 index 1bf2234..0000000 --- a/include/configs/salvator-x.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/salvator-x.h - * This file is Salvator-X board configuration. - * - * Copyright (C) 2015 Renesas Electronics Corporation - */ - -#ifndef __SALVATOR_X_H -#define __SALVATOR_X_H - -#include "rcar-gen3-common.h" - -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Generic Timer Definitions (use in assembler source) */ -#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MMC_ENV_PART 2 - -#endif /* __SALVATOR_X_H */ diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h deleted file mode 100644 index 5f89ae4..0000000 --- a/include/configs/sam9x60ek.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the SAM9X60EK board. - * - * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries - * - * Author: Sandeep Sheriker M - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* 24 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID 0 /* ignored in arm */ - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) - * NB: in this case, USB 1.1 devices won't be recognized. - */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 megs */ - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_NAND_ATMEL -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#define CONFIG_MTD_DEVICE -#endif - -/* PMECC & PMERRLOC */ -#define CONFIG_ATMEL_NAND_HWECC -#define CONFIG_ATMEL_NAND_HW_PMECC -#define CONFIG_PMECC_CAP 8 -#define CONFIG_PMECC_SECTOR_SIZE 512 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#ifdef CONFIG_SD_BOOT -/* bootstrap + u-boot + env + linux in sd card */ -#define CONFIG_BOOTCOMMAND \ - "fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \ - "fatload mmc 0:1 0x22000000 zImage;" \ - "bootz 0x22000000 - 0x21000000" - -#elif defined(CONFIG_NAND_BOOT) -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET_REDUND 0x100000 -#define CONFIG_BOOTCOMMAND "nand read " \ - "0x22000000 0x200000 0x600000; " \ - "nand read 0x21000000 0x180000 0x20000; " \ - "bootz 0x22000000 - 0x21000000" - -#elif defined(CONFIG_QSPI_BOOT) -/* bootstrap + u-boot + env + linux in SPI NOR flash */ -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x21000000 0x180000 0x80000; " \ - "sf read 0x22000000 0x200000 0x600000; " \ - "bootz 0x22000000 - 0x21000000" -#endif - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - -#endif diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h deleted file mode 100644 index 7343201..0000000 --- a/include/configs/sama5d27_som1_ek.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration file for the SAMA5D27 SOM1 EK Board. - * - * Copyright (C) 2017 Microchip Corporation - * Wenyou Yang - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x8000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* NAND flash */ -#undef CONFIG_CMD_NAND - -/* SPI flash */ - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_SD_BOOT -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d27_som1_ek.dtb; " \ - "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" -#endif - -#ifdef CONFIG_QSPI_BOOT -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" -#endif - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - -#endif diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h deleted file mode 100644 index 6bcbc06..0000000 --- a/include/configs/sama5d27_wlsom1_ek.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration file for the SAMA5D27 WLSOM1 EK Board. - * - * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries - * - * Author: Nicolas Ferre - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* SPL */ -#define CONFIG_SPL_TEXT_BASE 0x200000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - -#endif diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h deleted file mode 100644 index 17028ca..0000000 --- a/include/configs/sama5d2_icp.h +++ /dev/null @@ -1,67 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration file for the SAMA5D2 ICP Board. - * - * Copyright (C) 2018 Microchip Corporation - * Eugen Hristev - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_MISC_INIT_R - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* NAND flash */ -#undef CONFIG_CMD_NAND - -/* SPI flash */ -#define CONFIG_SF_DEFAULT_SPEED 66000000 - -#undef CONFIG_BOOTCOMMAND -#ifdef CONFIG_SD_BOOT -/* u-boot env in sd/mmc card */ -#define FAT_ENV_INTERFACE "mmc" -#define FAT_ENV_DEVICE_AND_PART "0" -#define FAT_ENV_FILE "uboot.env" -/* bootstrap + u-boot + env in sd card */ -#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 at91-sama5d2_icp.dtb; " \ - "fatload mmc 0:1 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" -#undef CONFIG_BOOTARGS -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" -#endif - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - -#endif diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h deleted file mode 100644 index f42e26a..0000000 --- a/include/configs/sama5d2_ptc_ek.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration file for the SAMA5D2 PTC EK Board. - * - * Copyright (C) 2017 Microchip Technology Inc. - * Wenyou Yang - * Ludovic Desroches - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -#undef CONFIG_SYS_AT91_MAIN_CLOCK -#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* NAND Flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE BIT(21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE BIT(22) -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h deleted file mode 100644 index 4873395..0000000 --- a/include/configs/sama5d2_xplained.h +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration file for the SAMA5D2 Xplained Board. - * - * Copyright (C) 2015 Atmel Corporation - * Wenyou Yang - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* SerialFlash */ - -#ifdef CONFIG_SD_BOOT - -/* bootstrap + u-boot + env in sd card */ -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_BOOTCOMMAND "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x21000000 at91-sama5d2_xplained.dtb; " \ - "fatload mmc " CONFIG_ENV_FAT_DEVICE_AND_PART " 0x22000000 zImage; " \ - "bootz 0x22000000 - 0x21000000" - -#elif CONFIG_SPI_BOOT - -/* bootstrap + u-boot + env in sd card, but kernel + dtb in eMMC */ -#undef CONFIG_BOOTCOMMAND - -#define CONFIG_BOOTCOMMAND "ext4load mmc 0:1 0x21000000 /boot/at91-sama5d2_xplained.dtb; " \ - "ext4load mmc 0:1 0x22000000 /boot/zImage; " \ - "bootz 0x22000000 - 0x21000000" - -#endif - -#ifdef CONFIG_QSPI_BOOT -#undef CONFIG_ENV_SPI_BUS -#undef CONFIG_BOOTCOMMAND -#define CONFIG_ENV_SPI_BUS 1 -#define CONFIG_BOOTCOMMAND "sf probe 1:0; " \ - "sf read 0x21000000 0x180000 0x80000; " \ - "sf read 0x22000000 0x200000 0x600000; "\ - "bootz 0x22000000 - 0x21000000" - -#endif - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - -#endif diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h deleted file mode 100644 index 696933d..0000000 --- a/include/configs/sama5d3_xplained.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the SAMA5D3 Xplained board. - * - * Copyright (C) 2014 Atmel Corporation - * Bo Shen - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP 32 - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP (1 << 6) - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x318000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00600000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "SAMA5D3 Xplained" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#endif -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h deleted file mode 100644 index 3a712b5..0000000 --- a/include/configs/sama5d3xek.h +++ /dev/null @@ -1,98 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the SAMA5D3xEK board. - * - * Copyright (C) 2012 - 2013 Atmel - * - * based on at91sam9m10g45ek.h by: - * Stelian Pop - * Lead Tech Design - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -/* - * This needs to be defined for the OHCI code to work but it is defined as - * ATMEL_ID_UHPHS in the CPU specific header files. - */ -#define ATMEL_ID_UHP 32 - -/* - * Specify the clock enable bit in the PMC_SCER register. - */ -#define ATMEL_PMC_UHP (1 << 6) - -/* board specific (not enough SRAM) */ -#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000 - -/* NOR flash */ -#ifdef CONFIG_MTD_NOR_FLASH -#define CONFIG_SYS_FLASH_BASE 0x10000000 -#define CONFIG_SYS_MAX_FLASH_SECT 131 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#endif - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x318000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -/* SerialFlash */ - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x60000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL_CLK_SEL_UPLL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#endif -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h deleted file mode 100644 index 1773412..0000000 --- a/include/configs/sama5d4_xplained.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the SAMA5D4 Xplained ultra board. - * - * Copyright (C) 2014 Atmel - * Bo Shen - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x80000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#endif -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 224 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h deleted file mode 100644 index 6cf07a1..0000000 --- a/include/configs/sama5d4ek.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the SAMA5D4EK board. - * - * Copyright (C) 2014 Atmel - * Bo Shen - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x20000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x218000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x80000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x18000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#elif CONFIG_NAND_BOOT -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#endif -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x1000 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 224 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/sandbox.h b/include/configs/sandbox.h deleted file mode 100644 index 5d75021..0000000 --- a/include/configs/sandbox.h +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#ifdef FTRACE -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x00100000 -#endif - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_IO_TRACE -#endif - -#ifndef CONFIG_TIMER -#define CONFIG_SYS_TIMER_RATE 1000000 -#endif - -#define CONFIG_LMB - -#define CONFIG_HOST_MAX_DEVICES 4 - -/* - * Size of malloc() pool, before and after relocation - */ -#define CONFIG_MALLOC_F_ADDR 0x0010000 -#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -/* turn on command-line edit/c/auto */ - -#define CONFIG_ENV_SIZE 8192 - -/* SPI - enable all SPI flash types for testing purposes */ - -#define CONFIG_I2C_EDID - -/* Memory things - we don't really want a memory test */ -#define CONFIG_SYS_LOAD_ADDR 0x00000000 -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1000) -#define CONFIG_SYS_FDT_LOAD_ADDR 0x100 - -#define CONFIG_PHYSMEM - -/* Size of our emulated memory */ -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_SDRAM_SIZE (128 << 20) -#define CONFIG_SYS_MONITOR_BASE 0 - -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -#define BOOT_TARGET_DEVICES(func) \ - func(HOST, host, 1) \ - func(HOST, host, 0) - -#ifdef __ASSEMBLY__ -#define BOOTENV -#else -#include -#endif - -#define CONFIG_KEEP_SERVERADDR -#define CONFIG_UDP_CHECKSUM -#define CONFIG_TIMESTAMP -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_BOOTP_SERVERIP - -#ifndef SANDBOX_NO_SDL -#define CONFIG_SANDBOX_SDL -#endif - -/* LCD and keyboard require SDL support */ -#ifdef CONFIG_SANDBOX_SDL -#define LCD_BPP LCD_COLOR16 -#define CONFIG_LCD_BMP_RLE8 -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN_ALIGN - -#define CONFIG_KEYBOARD - -#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" -#else -#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" -#endif - -#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \ - "eth1addr=00:00:11:22:33:45\0" \ - "eth3addr=00:00:11:22:33:46\0" \ - "eth5addr=00:00:11:22:33:47\0" \ - "ipaddr=1.2.3.4\0" - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x10000000\0" \ - "kernel_addr_r=0x1000000\0" \ - "fdt_addr_r=0xc00000\0" \ - "ramdisk_addr_r=0x2000000\0" \ - "scriptaddr=0x1000\0" \ - "pxefile_addr_r=0x2000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - SANDBOX_SERIAL_SETTINGS \ - SANDBOX_ETH_SETTINGS \ - BOOTENV \ - MEM_LAYOUT_ENV_SETTINGS - -#define CONFIG_GZIP_COMPRESSED -#define CONFIG_BZIP2 - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0 -#define CONFIG_SYS_IDE_MAXDEVICE 2 -#define CONFIG_SYS_ATA_BASE_ADDR 0x100 -#define CONFIG_SYS_ATA_DATA_OFFSET 0 -#define CONFIG_SYS_ATA_REG_OFFSET 1 -#define CONFIG_SYS_ATA_ALT_OFFSET 2 -#define CONFIG_SYS_ATA_STRIDE 4 -#endif - -#define CONFIG_SCSI_AHCI_PLAT -#define CONFIG_SYS_SCSI_MAX_DEVICE 2 -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8 -#define CONFIG_SYS_SCSI_MAX_LUN 4 - -#define CONFIG_SYS_SATA_MAX_DEVICE 2 - -#define CONFIG_MISC_INIT_F - -#endif diff --git a/include/configs/sandbox_spl.h b/include/configs/sandbox_spl.h deleted file mode 100644 index f536882..0000000 --- a/include/configs/sandbox_spl.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2016 Google, Inc - */ - -#ifndef __SANDBOX_SPL_CONFIG_H -#define __SANDBOX_SPL_CONFIG_H - -#include - -#endif diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h deleted file mode 100644 index 1beff23..0000000 --- a/include/configs/sansa_fuze_plus.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut - */ -#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__ -#define __CONFIGS_SANSA_FUZE_PLUS_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_OVERWRITE - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_FONT_4X6 -#define CONFIG_VIDEO_MXS_MODE_SYSTEM -#define CONFIG_SYS_BLACK_IN_WRITE -#define LCD_BPP LCD_COLOR16 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - -#define CONFIG_NETCONSOLE -#endif - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_SANSA_FUZE_PLUS_H__ */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h deleted file mode 100644 index d2053cc..0000000 --- a/include/configs/sbc8349.h +++ /dev/null @@ -1,341 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * WindRiver SBC8349 U-Boot configuration file. - * Copyright (c) 2006, 2007 Wind River Systems, Inc. - * - * Paul Gortmaker - * Based on the MPC8349EMDS config. - */ - -/* - * sbc8349 board configuration file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -/* Don't enable PCI2 on sbc834x - it doesn't exist physically. */ -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * DDR Setup - */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ -#define CONFIG_SYS_83XX_DDR_USES_CS0 /* WRS; Fsl board uses CS2/CS3 */ - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) -#define CONFIG_DDR_2T_TIMING - -#if defined(CONFIG_SPD_EEPROM) -/* - * Determine DDR configuration from I2C interface. - */ -#define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */ - -#else -/* - * Manually set up DDR parameters - * NB: manual DDR setup untested on sbc834x - */ -#define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ -#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ - -#if defined(CONFIG_DDR_32BIT) -/* set burst length to 8 for 32-bit data path */ - /* DLL,normal,seq,4/2.5, 8 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000023 -#else -/* the default burst length is 4 - for 64-bit data path */ - /* DLL,normal,seq,4/2.5, 4 burst len */ -#define CONFIG_SYS_DDR_MODE 0x00000022 -#endif -#endif - -/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 - /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 - /* Size of used area in RAM*/ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ - -#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69}, {1, 0x69} } -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0xFIXME -#endif - -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_PHY_BCM5421S 1 -#define TSEC1_PHY_ADDR 0x19 -#define TSEC2_PHY_ADDR 0x1a -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_HOSTNAME "SBC8349" -#define CONFIG_ROOTPATH "/tftpboot/rootfs" -#define CONFIG_BOOTFILE "uImage" - - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 800000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=sbc8349\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ - "update=protect off ff800000 ff83ffff; " \ - "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=sbc8349.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h deleted file mode 100644 index 6aa40ca..0000000 --- a/include/configs/sbc8548.h +++ /dev/null @@ -1,560 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2007,2009 Wind River Systems - * Copyright 2007 Embedded Specialties, Inc. - * Copyright 2004, 2007 Freescale Semiconductor. - */ - -/* - * sbc8548 board configuration file - * Please refer to doc/README.sbc8548 for more info. - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * Top level Makefile configuration choices - */ -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI1 -#endif - -#ifdef CONFIG_66 -#define CONFIG_SYS_CLK_DIV 1 -#endif - -#ifdef CONFIG_33 -#define CONFIG_SYS_CLK_DIV 2 -#endif - -#ifdef CONFIG_PCIE -#define CONFIG_PCIE1 -#endif - -/* - * High Level Configuration Options - */ - -/* - * If you want to boot from the SODIMM flash, instead of the soldered - * on flash, set this, and change JP12, SW2:8 accordingly. - */ -#undef CONFIG_SYS_ALT_BOOT - -#undef CONFIG_RIO - -#ifdef CONFIG_PCI -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#endif - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - -/* - * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] - */ -#ifndef CONFIG_SYS_CLK_DIV -#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ -#endif -#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV) - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -/* - * A hardware errata caused the LBC SDRAM SPD and the DDR2 SPD - * to collide, meaning you couldn't reliably read either. So - * physically remove the LBC PC100 SDRAM module from the board - * before enabling the two SPD options below, or check that you - * have the hardware fix on your board via "i2c probe" and looking - * for a device at 0x53. - */ -#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_SPD - -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* - * The hardware fix for the I2C address collision puts the DDR - * SPD at 0x53, but if we are running on an older board w/o the - * fix, it will still be at 0x51. We check 0x53 1st. - */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ -#define ALT_SPD_EEPROM_ADDRESS 0x53 /* CTLR 0 DIMM 0 */ - -/* - * Make sure required options are set - */ -#ifndef CONFIG_SPD_EEPROM - #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ - #define CONFIG_SYS_DDR_CONTROL 0xc300c000 -#endif - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * FLASH on the Local Bus - * Two banks, one 8MB the other 64MB, using the CFI driver. - * JP12+SW2.8 are used to swap CS0 and CS6, defaults are to have - * CS0 the 8MB boot flash, and CS6 the 64MB flash. - * - * Default: - * ec00_0000 efff_ffff 64MB SODIMM - * ff80_0000 ffff_ffff 8MB soldered flash - * - * Alternate: - * ef80_0000 efff_ffff 8MB soldered flash - * fc00_0000 ffff_ffff 64MB SODIMM - * - * BR0_8M: - * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0 - * Port Size = 8 bits = BRx[19:20] = 01 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - * - * BR0_64M: - * Base address 0 = 0xfc00_0000 = BR0[0:16] = 1111 1100 0000 0000 0 - * Port Size = 32 bits = BRx[19:20] = 11 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0_8M - * 1111 1100 0000 0000 0001 1000 0000 0001 = fc001801 BR0_64M - */ -#define CONFIG_SYS_BR0_8M 0xff800801 -#define CONFIG_SYS_BR0_64M 0xfc001801 - -/* - * BR6_8M: - * Base address 6 = 0xef80_0000 = BR6[0:16] = 1110 1111 1000 0000 0 - * Port Size = 8 bits = BRx[19:20] = 01 - * Use GPCM = BRx[24:26] = 000 - * Valid = BRx[31] = 1 - - * BR6_64M: - * Base address 6 = 0xec00_0000 = BR6[0:16] = 1110 1100 0000 0000 0 - * Port Size = 32 bits = BRx[19:20] = 11 - * - * 0 4 8 12 16 20 24 28 - * 1110 1111 1000 0000 0000 1000 0000 0001 = ef800801 BR6_8M - * 1110 1100 0000 0000 0001 1000 0000 0001 = ec001801 BR6_64M - */ -#define CONFIG_SYS_BR6_8M 0xef800801 -#define CONFIG_SYS_BR6_64M 0xec001801 - -/* - * OR0_8M: - * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0 - * XAM = OR0[17:18] = 11 - * CSNT = OR0[20] = 1 - * ACS = half cycle delay = OR0[21:22] = 11 - * SCY = 6 = OR0[24:27] = 0110 - * TRLX = use relaxed timing = OR0[29] = 1 - * EAD = use external address latch delay = OR0[31] = 1 - * - * OR0_64M: - * Addr Mask = 64M = OR1[0:16] = 1111 1100 0000 0000 0 - * - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0_8M - * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR0_64M - */ -#define CONFIG_SYS_OR0_8M 0xff806e65 -#define CONFIG_SYS_OR0_64M 0xfc006e65 - -/* - * OR6_8M: - * Addr Mask = 8M = OR6[0:16] = 1111 1111 1000 0000 0 - * XAM = OR6[17:18] = 11 - * CSNT = OR6[20] = 1 - * ACS = half cycle delay = OR6[21:22] = 11 - * SCY = 6 = OR6[24:27] = 0110 - * TRLX = use relaxed timing = OR6[29] = 1 - * EAD = use external address latch delay = OR6[31] = 1 - * - * OR6_64M: - * Addr Mask = 64M = OR6[0:16] = 1111 1100 0000 0000 0 - * - * 0 4 8 12 16 20 24 28 - * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR6_8M - * 1111 1100 0000 0000 0110 1110 0110 0101 = fc006e65 OR6_64M - */ -#define CONFIG_SYS_OR6_8M 0xff806e65 -#define CONFIG_SYS_OR6_64M 0xfc006e65 - -#ifndef CONFIG_SYS_ALT_BOOT /* JP12 in default position */ -#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ -#define CONFIG_SYS_ALT_FLASH 0xec000000 /* 64MB "user" flash */ - -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_8M -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_8M - -#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_64M -#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_64M -#else /* JP12 in alternate position */ -#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* start 64MB Flash */ -#define CONFIG_SYS_ALT_FLASH 0xef800000 /* 8MB soldered flash */ - -#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_BR0_64M -#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_OR0_64M - -#define CONFIG_SYS_BR6_PRELIM CONFIG_SYS_BR6_8M -#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_OR6_8M -#endif - -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_ALT_FLASH} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* CS5 = Local bus peripherals controlled by the EPLD */ - -#define CONFIG_SYS_BR5_PRELIM 0xf8000801 -#define CONFIG_SYS_OR5_PRELIM 0xff006e65 -#define CONFIG_SYS_EPLD_BASE 0xf8000000 -#define CONFIG_SYS_LED_DISP_BASE 0xf8000000 -#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000 -#define CONFIG_SYS_BD_REV 0xf8300000 -#define CONFIG_SYS_EEPROM_BASE 0xf8b00000 - -/* - * SDRAM on the Local Bus (CS3 and CS4) - * Note that most boards have a hardware errata where both the - * LBC SDRAM and the DDR2 SDRAM decode at 0x51, making it impossible - * to use CONFIG_DDR_SPD unless you physically remove the LBC DIMM. - * A hardware workaround is also available, see README.sbc8548 file. - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ - -/* - * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR3, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - */ - -#define CONFIG_SYS_BR3_PRELIM 0xf0001861 - -/* - * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR3, need: - * 64MB mask for AM, OR3[0:7] = 1111 1100 - * XAM, OR3[17:18] = 11 - * 10 columns OR3[19-21] = 011 - * 12 rows OR3[23-25] = 011 - * EAD set for extra time OR[31] = 0 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 - */ - -#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 - -/* - * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. - * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. - * - * For BR4, need: - * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 - * port-size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 - * - */ - -#define CONFIG_SYS_BR4_PRELIM 0xf4001861 - -/* - * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR4, need: - * 64MB mask for AM, OR3[0:7] = 1111 1100 - * XAM, OR3[17:18] = 11 - * 10 columns OR3[19-21] = 011 - * 12 rows OR3[23-25] = 011 - * EAD set for extra time OR[31] = 0 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 - */ - -#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 - -#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ - -/* - * Common settings for all Local Bus SDRAM commands. - */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ - | LSDMR_BSMA1516 \ - | LSDMR_PRETOACT3 \ - | LSDMR_ACTTORW3 \ - | LSDMR_BUFCMD \ - | LSDMR_BL8 \ - | LSDMR_WRC2 \ - | LSDMR_CL3 \ - ) - -#define CONFIG_SYS_LBC_LSDMR_PCHALL \ - (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_ARFRSH \ - (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_MRW \ - (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_RFEN \ - (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_RFEN) - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* - * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and - * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM - * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg - * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right - * thing for MONITOR_LEN in both cases. - */ -#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */ - -#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ -#endif - -#ifdef CONFIG_RIO -/* - * RapidIO MMU - */ -#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 -#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ -#endif - -#if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC1" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0x19 -#define TSEC2_PHY_ADDR 0x1a - -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 - -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: eTSEC[0-3] */ -#define CONFIG_ETHPRIME "eTSEC0" -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#define CONFIG_ENV_SIZE 0x2000 -#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000) -#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */ -#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#else -#warning undefined environment size/location. -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_IPADDR 192.168.0.55 - -#define CONFIG_HOSTNAME "sbc8548" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx" -#define CONFIG_BOOTFILE "/uImage" -#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */ - -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ - -#define CONFIG_EXTRA_ENV_SETTINGS \ -"netdev=eth0\0" \ -"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -"tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \ - "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ -"consoledev=ttyS0\0" \ -"ramdiskaddr=2000000\0" \ -"ramdiskfile=uRamdisk\0" \ -"fdtaddr=1e00000\0" \ -"fdtfile=sbc8548.dtb\0" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h deleted file mode 100644 index d1535b6..0000000 --- a/include/configs/sbc8641d.h +++ /dev/null @@ -1,520 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2007 Wind River Systems - * Copyright 2007 Embedded Specialties, Inc. - * Joe Hamman - * - * Copyright 2006 Freescale Semiconductor. - * - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - */ - -/* - * SBC8641D board configuration file - * - * Make sure you change the MAC address and other network params first, - * search for CONFIG_SERVERIP, etc in this file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ - -#ifdef RUN_DIAG -#define CONFIG_SYS_DIAG_ADDR 0xff800000 -#endif - -#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 - -/* - * virtual address to be used for temporary mappings. There - * should be 128k free at this VA. - */ -#define CONFIG_SYS_SCRATCH_VA 0xe8000000 - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ - -#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup*/ -#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef -#define CACHE_LINE_INTERLEAVING 0x20000000 -#define PAGE_INTERLEAVING 0x21000000 -#define BANK_INTERLEAVING 0x22000000 -#define SUPER_BANK_INTERLEAVING 0x23000000 - -#define CONFIG_ALTIVEC 1 - -/* - * L2CR setup -- make sure this is right for your board! - */ -#define CONFIG_SYS_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2CR_L2E) - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) -#endif - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xf8000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW - -/* - * DDR Setup - */ -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 -#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -#if defined(CONFIG_SPD_EEPROM) - /* - * Determine DDR configuration from I2C interface. - */ - #define SPD_EEPROM_ADDRESS1 0x51 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS2 0x52 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS3 0x53 /* DDR DIMM */ - #define SPD_EEPROM_ADDRESS4 0x54 /* DDR DIMM */ - -#else - /* - * Manually set up DDR1 & DDR2 parameters - */ - - #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ - - #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F - #define CONFIG_SYS_DDR_CS1_BNDS 0x00000000 - #define CONFIG_SYS_DDR_CS2_BNDS 0x00000000 - #define CONFIG_SYS_DDR_CS3_BNDS 0x00000000 - #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 - #define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000 - #define CONFIG_SYS_DDR_CS2_CONFIG 0x00000000 - #define CONFIG_SYS_DDR_CS3_CONFIG 0x00000000 - #define CONFIG_SYS_DDR_TIMING_3 0x00000000 - #define CONFIG_SYS_DDR_TIMING_0 0x00220802 - #define CONFIG_SYS_DDR_TIMING_1 0x38377322 - #define CONFIG_SYS_DDR_TIMING_2 0x002040c7 - #define CONFIG_SYS_DDR_CFG_1A 0x43008008 - #define CONFIG_SYS_DDR_CFG_2 0x24401000 - #define CONFIG_SYS_DDR_MODE_1 0x23c00542 - #define CONFIG_SYS_DDR_MODE_2 0x00000000 - #define CONFIG_SYS_DDR_MODE_CTL 0x00000000 - #define CONFIG_SYS_DDR_INTERVAL 0x05080100 - #define CONFIG_SYS_DDR_DATA_INIT 0x00000000 - #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 - #define CONFIG_SYS_DDR_CFG_1B 0xC3008008 - - #define CONFIG_SYS_DDR2_CS0_BNDS 0x0010001F - #define CONFIG_SYS_DDR2_CS1_BNDS 0x00000000 - #define CONFIG_SYS_DDR2_CS2_BNDS 0x00000000 - #define CONFIG_SYS_DDR2_CS3_BNDS 0x00000000 - #define CONFIG_SYS_DDR2_CS0_CONFIG 0x80010102 - #define CONFIG_SYS_DDR2_CS1_CONFIG 0x00000000 - #define CONFIG_SYS_DDR2_CS2_CONFIG 0x00000000 - #define CONFIG_SYS_DDR2_CS3_CONFIG 0x00000000 - #define CONFIG_SYS_DDR2_EXT_REFRESH 0x00000000 - #define CONFIG_SYS_DDR2_TIMING_0 0x00220802 - #define CONFIG_SYS_DDR2_TIMING_1 0x38377322 - #define CONFIG_SYS_DDR2_TIMING_2 0x002040c7 - #define CONFIG_SYS_DDR2_CFG_1A 0x43008008 - #define CONFIG_SYS_DDR2_CFG_2 0x24401000 - #define CONFIG_SYS_DDR2_MODE_1 0x23c00542 - #define CONFIG_SYS_DDR2_MODE_2 0x00000000 - #define CONFIG_SYS_DDR2_MODE_CTL 0x00000000 - #define CONFIG_SYS_DDR2_INTERVAL 0x05080100 - #define CONFIG_SYS_DDR2_DATA_INIT 0x00000000 - #define CONFIG_SYS_DDR2_CLK_CTRL 0x03800000 - #define CONFIG_SYS_DDR2_CFG_1B 0xC3008008 - -#endif - -/* #define CONFIG_ID_EEPROM 1 -#define ID_EEPROM_ADDR 0x57 */ - -/* - * The SBC8641D contains 16MB flash space at ff000000. - */ -#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ - -/* Flash */ -#define CONFIG_SYS_BR0_PRELIM 0xff001001 /* port size 16bit */ -#define CONFIG_SYS_OR0_PRELIM 0xff006e65 /* 16MB Boot Flash area */ - -/* 64KB EEPROM */ -#define CONFIG_SYS_BR1_PRELIM 0xf0000801 /* port size 16bit */ -#define CONFIG_SYS_OR1_PRELIM 0xffff6e65 /* 64K EEPROM area */ - -/* EPLD - User switches, board id, LEDs */ -#define CONFIG_SYS_BR2_PRELIM 0xf1000801 /* port size 16bit */ -#define CONFIG_SYS_OR2_PRELIM 0xfff06e65 /* EPLD (switches, board ID, LEDs) area */ - -/* Local bus SDRAM 128MB */ -#define CONFIG_SYS_BR3_PRELIM 0xe0001861 /* port size ?bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (1st half) */ -#define CONFIG_SYS_BR4_PRELIM 0xe4001861 /* port size ?bit */ -#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 /* 128MB local bus SDRAM area (2nd half) */ - -/* Disk on Chip (DOC) 128MB */ -#define CONFIG_SYS_BR5_PRELIM 0xe8001001 /* port size ?bit */ -#define CONFIG_SYS_OR5_PRELIM 0xf8006e65 /* 128MB local bus SDRAM area (2nd half) */ - -/* LCD */ -#define CONFIG_SYS_BR6_PRELIM 0xf4000801 /* port size ?bit */ -#define CONFIG_SYS_OR6_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ - -/* Control logic & misc peripherals */ -#define CONFIG_SYS_BR7_PRELIM 0xf2000801 /* port size ?bit */ -#define CONFIG_SYS_OR7_PRELIM 0xfff06e65 /* 128MB local bus SDRAM area (2nd half) */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 131 /* sectors per device */ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ - -#define CONFIG_SYS_WRITE_SWAPPED_DATA -#define CONFIG_SYS_FLASH_EMPTY_INFO - -#undef CONFIG_CLOCKS_IN_MHZ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#ifndef CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ -#else -#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ -#endif -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* Serial Port */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } - -/* - * RapidIO MMU - */ -#define CONFIG_SYS_SRIO1_MEM_BASE 0xc0000000 /* base address */ -#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BASE -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 128M */ - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS -#define CONFIG_SYS_PCIE1_MEM_VIRT CONFIG_SYS_PCIE1_MEM_BUS -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BUS 0xe2000000 -#define CONFIG_SYS_PCIE1_IO_PHYS CONFIG_SYS_PCIE1_IO_BUS -#define CONFIG_SYS_PCIE1_IO_VIRT CONFIG_SYS_PCIE1_IO_BUS -#define CONFIG_SYS_PCIE1_IO_SIZE 0x1000000 /* 16M */ - -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS -#define CONFIG_SYS_PCIE2_MEM_VIRT CONFIG_SYS_PCIE2_MEM_BUS -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0xe3000000 -#define CONFIG_SYS_PCIE2_IO_PHYS CONFIG_SYS_PCIE2_IO_BUS -#define CONFIG_SYS_PCIE2_IO_VIRT CONFIG_SYS_PCIE2_IO_BUS -#define CONFIG_SYS_PCIE2_IO_SIZE 0x1000000 /* 16M */ - -#if defined(CONFIG_PCI) - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xe0000000 - #define PCI_ENET0_MEMADDR 0xe0000000 - #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ - -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_SATA_ULI5288 -#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 -#define CONFIG_SYS_SCSI_MAX_LUN 1 -#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) -#endif - -#endif /* CONFIG_PCI */ - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "eTSEC4" - -#define TSEC1_PHY_ADDR 0x1F -#define TSEC2_PHY_ADDR 0x00 -#define TSEC3_PHY_ADDR 0x01 -#define TSEC4_PHY_ADDR 0x02 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC4_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS TSEC_GIGABIT -#define TSEC4_FLAGS TSEC_GIGABIT - -#define CONFIG_SYS_TBIPA_VALUE 0x1e /* Set TBI address not to conflict with TSEC1_PHY_ADDR */ - -#define CONFIG_ETHPRIME "eTSEC1" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * BAT0 2G Cacheable, non-guarded - * 0x0000_0000 2G DDR - */ -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U - -/* - * BAT1 1G Cache-inhibited, guarded - * 0x8000_0000 512M PCI-Express 1 Memory - * 0xa000_0000 512M PCI-Express 2 Memory - * Changed it for operating from 0xd0000000 - */ -#define CONFIG_SYS_DBAT1L ( CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U - -/* - * BAT2 512M Cache-inhibited, guarded - * 0xc000_0000 512M RapidIO Memory - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_SRIO1_MEM_BASE | BATU_BL_512M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_SRIO1_MEM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U - -/* - * BAT3 4M Cache-inhibited, guarded - * 0xf800_0000 4M CCSR - */ -#define CONFIG_SYS_DBAT3L ( CONFIG_SYS_CCSRBAR | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_4M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) -#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATL_PP_RW | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ - | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU -#endif - -/* - * BAT4 32M Cache-inhibited, guarded - * 0xe200_0000 16M PCI-Express 1 I/O - * 0xe300_0000 16M PCI-Express 2 I/0 - * Note that this is at 0xe0000000 - */ -#define CONFIG_SYS_DBAT4L ( CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U - -/* - * BAT5 128K Cacheable, non-guarded - * 0xe401_0000 128K Init RAM for stack in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L -#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U - -/* - * BAT6 32M Cache-inhibited, guarded - * 0xfe00_0000 32M FLASH - */ -#define CONFIG_SYS_DBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT6L ((CONFIG_SYS_FLASH_BASE & 0xfe000000) | BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U - -/* Map the last 1M of flash where we're running from reset */ -#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ - | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY - -#define CONFIG_SYS_DBAT7L 0x00000000 -#define CONFIG_SYS_DBAT7U 0x00000000 -#define CONFIG_SYS_IBAT7L 0x00000000 -#define CONFIG_SYS_IBAT7U 0x00000000 - -/* - * Environment - */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* Cache Configuration */ -#define CONFIG_SYS_DCACHE_SIZE 32768 -#define CONFIG_SYS_CACHELINE_SIZE 32 -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ - -#define CONFIG_HAS_ETH0 1 -#define CONFIG_HAS_ETH1 1 -#define CONFIG_HAS_ETH2 1 -#define CONFIG_HAS_ETH3 1 - -#define CONFIG_IPADDR 192.168.0.50 - -#define CONFIG_HOSTNAME "sbc8641d" -#define CONFIG_ROOTPATH "/opt/eldk/ppc_74xx" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_SERVERIP 192.168.0.2 -#define CONFIG_GATEWAYIP 192.168.0.1 -#define CONFIG_NETMASK 255.255.255.0 - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=2000000\0" \ - "ramdiskfile=uRamdisk\0" \ - "dtbaddr=400000\0" \ - "dtbfile=sbc8641d.dtb\0" \ - "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ - "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ - "maxcpus=1" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr - $dtbaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $dtbaddr $dtbfile;" \ - "bootm $loadaddr $ramdiskaddr $dtbaddr" - -#define CONFIG_FLASHBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "bootm ffd00000 ffb00000 ffa00000" - -#define CONFIG_BOOTCOMMAND CONFIG_FLASHBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h deleted file mode 100644 index cc10892..0000000 --- a/include/configs/sc_sps_1.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * SchulerControl GmbH, SC_SPS_1 module config - * - * Copyright (C) 2012 Marek Vasut - * on behalf of DENX Software Engineering GmbH - */ -#ifndef __CONFIGS_SC_SPS_1_H__ -#define __CONFIGS_SC_SPS_1_H__ - -/* System configuration */ -#define CONFIG_MACH_TYPE MACH_TYPE_SC_SPS_1 - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_SIZE (16 * 1024) - -/* Environment is in MMC */ -#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* FEC Ethernet on SoC */ -#ifdef CONFIG_CMD_NET -#define CONFIG_FEC_MXC -#define CONFIG_PHY_SMSC -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -#endif - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_BOOTCOMMAND "bootm" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "update_sd_firmware_filename=u-boot.sd\0" \ - "update_sd_firmware=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_sd_firmware_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} 0x800 ${fw_sz} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_SC_SPS_1_H__ */ diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h deleted file mode 100644 index 5df013b..0000000 --- a/include/configs/seaboard.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* LP0 suspend / resume */ -#define CONFIG_TEGRA_LP0 -#define CONFIG_TEGRA_PMU -#define CONFIG_TPS6586X_POWER -#define CONFIG_TEGRA_CLOCK_SCALING - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_SEABOARD - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -/* NAND support */ -#define CONFIG_TEGRA_NAND - -/* Max number of NAND devices */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/secomx6quq7.h b/include/configs/secomx6quq7.h deleted file mode 100644 index 2d219b2..0000000 --- a/include/configs/secomx6quq7.h +++ /dev/null @@ -1,88 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Seco S.r.l - * - * Configuration settings for the Seco Boards. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_BOARD_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* Ethernet Configuration */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "ethprime=FEC0\0" \ - "netdev=eth0\0" \ - "ethprime=FEC0\0" \ - "uboot=u-boot.bin\0" \ - "kernel=uImage\0" \ - "nfsroot=/opt/eldk/arm\0" \ - "ip_local=10.0.0.5::10.0.0.1:255.255.255.0::eth0:off\0" \ - "ip_server=10.0.0.1\0" \ - "nfs_path=/targetfs \0" \ - "memory=mem=1024M\0" \ - "bootdev=mmc dev 0; ext2load mmc 0:1\0" \ - "root=root=/dev/mmcblk0p1\0" \ - "option=rootwait rw fixrtc rootflags=barrier=1\0" \ - "cpu_freq=arm_freq=996\0" \ - "setbootargs=setenv bootargs console=ttymxc1,115200 ${root}" \ - " ${option} ${memory} ${cpu_freq}\0" \ - "setbootargs_nfs=setenv bootargs console=ttymxc1,115200" \ - " root=/dev/nfs nfsroot=${ip_server}:${nfs_path}" \ - " nolock,wsize=4096,rsize=4096 ip=:::::eth0:dhcp" \ - " ${memory} ${cpu_freq}\0" \ - "setbootdev=setenv boot_dev ${bootdev} 10800000 /boot/uImage\0" \ - "bootcmd=run setbootargs; run setbootdev; run boot_dev;" \ - " bootm 0x10800000\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#if defined(CONFIG_ENV_IS_IN_MMC) - #define CONFIG_ENV_OFFSET (6 * 128 * 1024) - #define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_DYNAMIC_MMC_DEVNO -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/sei510.h b/include/configs/sei510.h deleted file mode 100644 index d37b4c6..0000000 --- a/include/configs/sei510.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for the SEI510 - * - * Copyright (C) 2019 Baylibre, SAS - * Author: Jerome Brunet - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;" -#define CACHE_UUID "99207ae6-5207-11e9-999e-6f77a3612069;" -#define SYSTEM_UUID "99f9b7ac-5207-11e9-8507-c3c037e393f3;" -#define VENDOR_UUID "9d082802-5207-11e9-954c-cbbce08ba108;" -#define USERDATA_UUID "9b976e42-5207-11e9-8f16-ff47ac594b22;" -#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;" - -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \ - "name=logo,size=2M,uuid=" LOGO_UUID \ - "name=cache,size=256M,uuid=" CACHE_UUID \ - "name=system,size=1536M,uuid=" SYSTEM_UUID \ - "name=vendor,size=256M,uuid=" VENDOR_UUID \ - "name=userdata,size=5341M,uuid=" USERDATA_UUID \ - "name=rootfs,size=-,uuid=" ROOT_UUID - - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/sei610.h b/include/configs/sei610.h deleted file mode 100644 index 6d09316..0000000 --- a/include/configs/sei610.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for the SEI510 - * - * Copyright (C) 2019 Baylibre, SAS - * Author: Jerome Brunet - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define LOGO_UUID "43a3305d-150f-4cc9-bd3b-38fca8693846;" -#define CACHE_UUID "99207ae6-5207-11e9-999e-6f77a3612069;" -#define SYSTEM_UUID "99f9b7ac-5207-11e9-8507-c3c037e393f3;" -#define VENDOR_UUID "9d082802-5207-11e9-954c-cbbce08ba108;" -#define USERDATA_UUID "9b976e42-5207-11e9-8f16-ff47ac594b22;" -#define ROOT_UUID "ddb8c3f6-d94d-4394-b633-3134139cc2e0;" - -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name=boot,size=64M,bootable,uuid=${uuid_gpt_boot};" \ - "name=logo,size=2M,uuid=" LOGO_UUID \ - "name=cache,size=256M,uuid=" CACHE_UUID \ - "name=system,size=1536M,uuid=" SYSTEM_UUID \ - "name=vendor,size=256M,uuid=" VENDOR_UUID \ - "name=userdata,size=12795M,uuid=" USERDATA_UUID \ - "name=rootfs,size=-,uuid=" ROOT_UUID - -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/sfr_nb4_ser.h b/include/configs/sfr_nb4_ser.h deleted file mode 100644 index 2aa5c66..0000000 --- a/include/configs/sfr_nb4_ser.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Álvaro Fernández Rojas - */ - -#include -#include - -#define CONFIG_REMAKE_ELF - -#define CONFIG_ENV_SIZE SZ_8K diff --git a/include/configs/sh7752evb.h b/include/configs/sh7752evb.h deleted file mode 100644 index cd7f51c..0000000 --- a/include/configs/sh7752evb.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the sh7752evb board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __SH7752EVB_H -#define __SH7752EVB_H - -#define CONFIG_CPU_SH7752 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* MEMORY */ -#define SH7752EVB_SDRAM_BASE (0x40000000) -#define SH7752EVB_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF2 1 - -#define CONFIG_SYS_MEMTEST_START (SH7752EVB_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 480 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (SH7752EVB_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (SH7752EVB_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - 128 * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 18 -#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 -#define CONFIG_SH_ETHER_USE_GETHER 1 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII -#define CONFIG_PHY_VITESSE - -#define SH7752EVB_ETHERNET_MAC_BASE_SPI 0x00090000 -#define SH7752EVB_SPI_SECTOR_SIZE (64 * 1024) -#define SH7752EVB_ETHERNET_MAC_BASE SH7752EVB_ETHERNET_MAC_BASE_SPI -#define SH7752EVB_ETHERNET_MAC_SIZE 17 -#define SH7752EVB_ETHERNET_NUM_CH 2 - -/* SPI */ -#define CONFIG_SH_SPI_BASE 0xfe002000 - -/* MMCIF */ -#define CONFIG_SH_MMCIF_ADDR 0xffcb0000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* ENV setting */ -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_ADDR (0x00080000) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=bootp; bootm\0" - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 48000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ -#endif /* __SH7752EVB_H */ diff --git a/include/configs/sh7753evb.h b/include/configs/sh7753evb.h deleted file mode 100644 index 6b00bd7..0000000 --- a/include/configs/sh7753evb.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the sh7753evb board - * - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __SH7753EVB_H -#define __SH7753EVB_H - -#define CONFIG_CPU_SH7753 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* MEMORY */ -#define SH7753EVB_SDRAM_BASE (0x40000000) -#define SH7753EVB_SDRAM_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF2 1 - -#define CONFIG_SYS_MEMTEST_START (SH7753EVB_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 480 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (SH7753EVB_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (SH7753EVB_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - 128 * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 18 -#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 -#define CONFIG_SH_ETHER_USE_GETHER 1 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII -#define CONFIG_PHY_VITESSE - -#define SH7753EVB_ETHERNET_MAC_BASE_SPI 0x00090000 -#define SH7753EVB_SPI_SECTOR_SIZE (64 * 1024) -#define SH7753EVB_ETHERNET_MAC_BASE SH7753EVB_ETHERNET_MAC_BASE_SPI -#define SH7753EVB_ETHERNET_MAC_SIZE 17 -#define SH7753EVB_ETHERNET_NUM_CH 2 - -/* SPI */ -#define CONFIG_SH_SPI_BASE 0xfe002000 - -/* MMCIF */ -#define CONFIG_SH_MMCIF_ADDR 0xffcb0000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* ENV setting */ -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_ADDR (0x00080000) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=bootp; bootm\0" - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 48000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ -#endif /* __SH7753EVB_H */ diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h deleted file mode 100644 index f1955a1..0000000 --- a/include/configs/sh7757lcr.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the sh7757lcr board - * - * Copyright (C) 2011 Renesas Solutions Corp. - */ - -#ifndef __SH7757LCR_H -#define __SH7757LCR_H - -#define CONFIG_CPU_SH7757 1 -#define CONFIG_SH7757LCR_DDR_ECC 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* MEMORY */ -#define SH7757LCR_SDRAM_BASE (0x80000000) -#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024) -#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */ -#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024) - -#define CONFIG_SYS_PBSIZE 256 -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } - -/* SCIF */ -#define CONFIG_CONS_SCIF2 1 - -#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 224 * 1024 * 1024) -#undef CONFIG_SYS_MEMTEST_SCRATCH -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE) -#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 + 16) * 1024 * 1024) - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 1 -#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - -#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 -#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) -#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI -#define SH7757LCR_ETHERNET_MAC_SIZE 17 -#define SH7757LCR_ETHERNET_NUM_CH 2 - -/* Gigabit Ether */ -#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2 - -/* SPI */ -#define CONFIG_SH_SPI_BASE 0xfe002000 - -/* MMCIF */ -#define CONFIG_SH_MMCIF_ADDR 0xffcb0000 -#define CONFIG_SH_MMCIF_CLK 48000000 - -/* SH7757 board */ -#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000 -#define SH7757LCR_GRA_OFFSET 0x1f000000 -#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000 -#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024) -#define SH7757LCR_PCIEBRG_ADDR 0x00090000 -#define SH7757LCR_PCIEBRG_SIZE (96 * 1024) - -/* ENV setting */ -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_ADDR (0x00080000) -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netboot=bootp; bootm\0" - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 48000000 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ -#endif /* __SH7757LCR_H */ diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h deleted file mode 100644 index 10961b1..0000000 --- a/include/configs/sh7763rdp.h +++ /dev/null @@ -1,77 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas SH7763RDP board - * - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - */ - -#ifndef __SH7763RDP_H -#define __SH7763RDP_H - -#define CONFIG_CPU_SH7763 1 -#define __LITTLE_ENDIAN 1 - -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_DISPLAY_BOARDINFO - -/* SCIF */ -#define CONFIG_CONS_SCIF2 1 - -#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */ -#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate - settings for this board */ - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE (0x8C000000) -#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) - -/* Flash(NOR) */ -#define CONFIG_SYS_FLASH_BASE (0xA0000000) -#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT) -#define CONFIG_SYS_MAX_FLASH_BANKS (1) -#define CONFIG_SYS_MAX_FLASH_SECT (520) - -/* U-Boot setting */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_MONITOR_LEN (128 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -#undef CONFIG_SYS_FLASH_QUIET_TEST -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -/* Timeout for Flash erase operations (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -/* Timeout for Flash write operations (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -/* Timeout for Flash set sector lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -/* Timeout for Flash clear lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) -/* Use hardware flash sectors protection instead of U-Boot software protection */ -#undef CONFIG_SYS_DIRECT_FLASH_TFTP -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE)) -/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE)) - -/* Clock */ -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -/* Ether */ -#define CONFIG_SH_ETHER_USE_PORT (1) -#define CONFIG_SH_ETHER_PHY_ADDR (0x01) -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII - -#endif /* __SH7763RDP_H */ diff --git a/include/configs/sheep_rk3368.h b/include/configs/sheep_rk3368.h deleted file mode 100644 index 238838f..0000000 --- a/include/configs/sheep_rk3368.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2017 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIGS_PX5_EVB_H -#define __CONFIGS_PX5_EVB_H - -#include - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define KERNEL_LOAD_ADDR 0x280000 -#define DTB_LOAD_ADDR 0x5600000 -#define INITRD_LOAD_ADDR 0x5bf0000 - -#define CONFIG_CONSOLE_SCROLL_LINES 10 - -#endif diff --git a/include/configs/sheevaplug.h b/include/configs/sheevaplug.h deleted file mode 100644 index deec717..0000000 --- a/include/configs/sheevaplug.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009-2014 - * Gerald Kerma - * Marvell Semiconductor - * Written-by: Prafulla Wadaskar - */ - -#ifndef _CONFIG_SHEEVAPLUG_H -#define _CONFIG_SHEEVAPLUG_H - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ - -/* - * Commands configuration - */ - -/* - * Standard filesystems - */ -#define CONFIG_BZIP2 - -/* - * mv-plug-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-plug-common.h" - -/* - * Environment variables configurations - */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */ -#endif -/* - * max 4k env size is enough, but in case of nand - * it has to be rounded to sector size - */ -#define CONFIG_ENV_SIZE 0x20000 /* 128k */ -#define CONFIG_ENV_ADDR 0x80000 -#define CONFIG_ENV_OFFSET 0x80000 /* env starts here */ -/* - * Environment is right behind U-Boot in flash. Make sure U-Boot - * doesn't grow into the environment area. - */ -#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET - -/* - * Default environment variables - */ -#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \ - "setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \ - "bootm 0x6400000;" - -#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \ - "=ttyS0,115200 mtdparts="CONFIG_MTDPARTS_DEFAULT \ - "x_bootcmd_kernel=nand read 0x6400000 0x100000 0x400000\0" \ - "x_bootcmd_usb=usb start\0" \ - "x_bootargs_root=root=/dev/mtdblock3 rw rootfstype=jffs2\0" - -/* - * Ethernet Driver configuration - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ -#define CONFIG_PHY_BASE_ADR 0 -#endif /* CONFIG_CMD_NET */ - -/* - * SDIO/MMC Card Configuration - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MVEBU_MMC -#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE -#endif /* CONFIG_CMD_MMC */ - -/* - * SATA driver configuration - */ -#ifdef CONFIG_IDE -#define __io -#define CONFIG_IDE_PREINIT -#define CONFIG_MVSATA_IDE_USE_PORT0 -#define CONFIG_MVSATA_IDE_USE_PORT1 -#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET -#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET -#endif /* CONFIG_IDE */ - -#endif /* _CONFIG_SHEEVAPLUG_H */ diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h deleted file mode 100644 index ea6cc38..0000000 --- a/include/configs/siemens-am33x-common.h +++ /dev/null @@ -1,468 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * siemens am33x common board options - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_SIEMENS_AM33X_COMMON_H -#define __CONFIG_SIEMENS_AM33X_COMMON_H - -#include - -#define CONFIG_DMA_COHERENT -#define CONFIG_DMA_COHERENT_SIZE (1 << 20) - -#define CONFIG_SYS_MALLOC_LEN (16 * 1024 * 1024) -#ifdef CONFIG_SIEMENS_MACH_TYPE -#define CONFIG_MACH_TYPE CONFIG_SIEMENS_MACH_TYPE -#endif - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* commands to include */ - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_ROOTPATH "/opt/eldk" -#endif - -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_SYS_AUTOLOAD "yes" - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK) - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 32 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * memtest works on 8 MB in DRAM after skipping 32MB from - * start addr of ram disk - */ -#define CONFIG_SYS_MEMTEST_START (PHYS_DRAM_1 + (64 * 1024 * 1024)) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + (8 * 1024 * 1024)) - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */ - - /* Physical Memory Map */ -#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - /* Platform/Board specific defs */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x44e09000 -#define CONFIG_SYS_NS16550_COM4 0x481a6000 - - -/* I2C Configuration */ -#define CONFIG_I2C -#define CONFIG_SYS_I2C - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW - -#define CONFIG_SYS_NAND_ECCSTEPS 4 -#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ - CONFIG_SYS_NAND_ECCSTEPS) - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -#ifndef CONFIG_SPL_BUILD -/* - * USB configuration - */ -#define CONFIG_AM335X_USB0 -#define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL -#define CONFIG_AM335X_USB1 -#define CONFIG_AM335X_USB1_MODE MUSB_HOST - -/* USB DRACO ID as default */ -#define CONFIG_USBD_HS - -/* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20) -#define DFU_MANIFEST_POLL_TIMEOUT 25000 - -#endif /* CONFIG_SPL_BUILD */ - -/* - * Default to using SPI for environment, etc. We have multiple copies - * of SPL as the ROM will check these locations. - * 0x0 - 0x20000 : First copy of SPL - * 0x20000 - 0x40000 : Second copy of SPL - * 0x40000 - 0x60000 : Third copy of SPL - * 0x60000 - 0x80000 : Fourth copy of SPL - * 0x80000 - 0xDF000 : U-Boot - * 0xDF000 - 0xE0000 : U-Boot Environment - * 0xE0000 - 0x442000 : Linux Kernel - * 0x442000 - 0x800000 : Userland - */ -#if defined(CONFIG_SPI_BOOT) -# define CONFIG_ENV_OFFSET (892 << 10) /* 892 KiB in */ -# define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ -#endif /* SPI support */ - -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* NAND support */ -#ifdef CONFIG_NAND -/* UBI Support */ - -/* Commen environment */ -#define COMMON_ENV_DFU_ARGS "dfu_args=run bootargs_defaults;" \ - "setenv bootargs ${bootargs};" \ - "mtdparts default;" \ - "draco_led 1;" \ - "dfu 0 nand 0;" \ - "draco_led 0;\0" \ - -#define COMMON_ENV_NAND_BOOT \ - "nand_boot=echo Booting from nand; " \ - "if test ${upgrade_available} -eq 1; then " \ - "if test ${bootcount} -gt ${bootlimit}; " \ - "then " \ - "setenv upgrade_available 0;" \ - "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ - "setenv partitionset_active B; " \ - "env delete A; " \ - "fi;" \ - "if test -n ${B}; then " \ - "setenv partitionset_active A; " \ - "env delete B; " \ - "fi;" \ - "saveenv; " \ - "fi;" \ - "fi;" \ - "echo set ${partitionset_active}...;" \ - "run nand_args; " - -#define COMMON_ENV_NAND_CMDS "flash_self=run nand_boot\0" \ - "flash_self_test=setenv testargs test; " \ - "run nand_boot\0" \ - "dfu_start=echo Preparing for dfu mode ...; " \ - "run dfu_args; \0" - -#define COMMON_ENV_SETTINGS \ - "verify=no \0" \ - "project_dir=targetdir\0" \ - "upgrade_available=0\0" \ - "altbootcmd=run bootcmd\0" \ - "partitionset_active=A\0" \ - "loadaddr=0x82000000\0" \ - "kloadaddr=0x81000000\0" \ - "script_addr=0x81900000\0" \ - "console=console=ttyMTD,mtdoops console=ttyO0,115200n8 panic=5\0" \ - "nfsopts=nolock rw\0" \ - "ip_method=none\0" \ - "bootenv=uEnv.txt\0" \ - "bootargs_defaults=setenv bootargs " \ - "console=${console} " \ - "${testargs} " \ - "${optargs}\0" \ - "siemens_help=echo; "\ - "echo Type 'run flash_self' to use kernel and root " \ - "filesystem on memory; echo Type 'run flash_self_test' to " \ - "use kernel and root filesystem on memory, boot in test " \ - "mode; echo Not ready yet: 'run flash_nfs' to use kernel " \ - "from memory and root filesystem over NFS; echo Type " \ - "'run net_nfs' to get Kernel over TFTP and mount root " \ - "filesystem over NFS; " \ - "echo Set partitionset_active variable to 'A' " \ - "or 'B' to select kernel and rootfs partition; " \ - "echo" \ - "\0" - -/* - * Variant 1 partition layout - * chip-size = 256MiB - *| name | size | address area | - *------------------------------------------------------- - *| spl | 128.000 KiB | 0x 0..0x 1ffff | - *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | - *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | - *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | - *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | - *| uboot.env | 128.000 KiB | 0x 260000..0x 27ffff | - *| kernel_a | 5.000 MiB | 0x 280000..0x 77ffff | - *| kernel_b | 5.000 MiB | 0x 780000..0x c7ffff | - *| mtdoops | 8.000 MiB | 0x c80000..0x 147ffff | - *| rootfs | 235.500 MiB | 0x 1480000..0x fffffff | - *------------------------------------------------------- - - "mtdparts=omap2-nand.0:" \ - "128k(spl)," \ - "128k(spl.backup1)," \ - "128k(spl.backup2)," \ - "128k(spl.backup3)," \ - "1920k(u-boot)," \ - "128k(uboot.env)," \ - "5120k(kernel_a)," \ - "5120k(kernel_b)," \ - "8192k(mtdoops)," \ - "-(rootfs)" - */ - -#define DFU_ALT_INFO_NAND_V1 \ - "spl part 0 1;" \ - "spl.backup1 part 0 2;" \ - "spl.backup2 part 0 3;" \ - "spl.backup3 part 0 4;" \ - "u-boot part 0 5;" \ - "u-boot.env part 0 6;" \ - "kernel_a part 0 7;" \ - "kernel_b part 0 8;" \ - "rootfs partubi 0 10" - -#define CONFIG_ENV_SETTINGS_NAND_V1 \ - "nand_active_ubi_vol=rootfs_a\0" \ - "nand_active_ubi_vol_A=rootfs_a\0" \ - "nand_active_ubi_vol_B=rootfs_b\0" \ - "nand_root_fs_type=ubifs rootwait=1\0" \ - "nand_src_addr=0x280000\0" \ - "nand_src_addr_A=0x280000\0" \ - "nand_src_addr_B=0x780000\0" \ - "nand_args=run bootargs_defaults;" \ - "mtdparts default;" \ - "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ - "setenv nand_active_ubi_vol ${nand_active_ubi_vol_A};" \ - "setenv nand_src_addr ${nand_src_addr_A};" \ - "fi;" \ - "if test -n ${B}; then " \ - "setenv nand_active_ubi_vol ${nand_active_ubi_vol_B};" \ - "setenv nand_src_addr ${nand_src_addr_B};" \ - "fi;" \ - "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ - "ubi.mtd=9,${ubi_off};" \ - "setenv bootargs ${bootargs} " \ - "root=${nand_root} noinitrd ${mtdparts} " \ - "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ - "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ - "=mtdoops\0" \ - COMMON_ENV_DFU_ARGS \ - "dfu_alt_info=" DFU_ALT_INFO_NAND_V1 "\0" \ - COMMON_ENV_NAND_BOOT \ - "nand read.i ${kloadaddr} ${nand_src_addr} " \ - "${nand_img_size}; bootm ${kloadaddr}\0" \ - COMMON_ENV_NAND_CMDS - -#define CONFIG_ENV_SETTINGS_V1 \ - COMMON_ENV_SETTINGS \ - "net_args=run bootargs_defaults;" \ - "mtdparts default;" \ - "setenv bootfile ${project_dir}/kernel/uImage;" \ - "setenv rootpath /home/projects/${project_dir}/rootfs;" \ - "setenv bootargs ${bootargs} " \ - "root=/dev/nfs ${mtdparts} " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} " \ - "ip=${ipaddr}:${serverip}:" \ - "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ - "net_nfs=echo Booting from network ...; " \ - "run net_args; " \ - "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \ - "bootm ${kloadaddr}\0" - -/* - * Variant 2 partition layout (default) - * chip-size = 256MiB or 512 MiB - *| name | size | address area | - *------------------------------------------------------- - *| spl | 128.000 KiB | 0x 0..0x 1ffff | - *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | - *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | - *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | - *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | - *| uboot.env0 | 512.000 KiB | 0x 260000..0x 2Dffff | - *| uboot.env1 | 512.000 KiB | 0x 2E0000..0x 35ffff | - *| mtdoops | 512.000 KiB | 0x 360000..0x 3dffff | - *| (256) rootfs | 252.125 MiB | 0x 3E0000..0x fffffff | - *| (512) rootfs | 508.125 MiB | 0x 3E0000..0x1fffffff | - *------------------------------------------------------- - */ - -#define DFU_ALT_INFO_NAND_V2 \ - "spl part 0 1;" \ - "spl.backup1 part 0 2;" \ - "spl.backup2 part 0 3;" \ - "spl.backup3 part 0 4;" \ - "u-boot part 0 5;" \ - "u-boot.env0 part 0 6;" \ - "u-boot.env1 part 0 7;" \ - "rootfs partubi 0 9" \ - -#define CONFIG_ENV_SETTINGS_NAND_V2 \ - "nand_active_ubi_vol=rootfs_a\0" \ - "rootfs_name=rootfs\0" \ - "kernel_name=uImage\0"\ - "nand_root_fs_type=ubifs rootwait=1\0" \ - "nand_args=run bootargs_defaults;" \ - "mtdparts default;" \ - "setenv ${partitionset_active} true;" \ - "if test -n ${A}; then " \ - "setenv nand_active_ubi_vol ${rootfs_name}_a;" \ - "fi;" \ - "if test -n ${B}; then " \ - "setenv nand_active_ubi_vol ${rootfs_name}_b;" \ - "fi;" \ - "setenv nand_root ubi0:${nand_active_ubi_vol} rw " \ - "ubi.mtd=rootfs,2048;" \ - "setenv bootargs ${bootargs} " \ - "root=${nand_root} noinitrd ${mtdparts} " \ - "rootfstype=${nand_root_fs_type} ip=${ip_method} " \ - "console=ttyMTD,mtdoops console=ttyO0,115200n8 mtdoops.mtddev" \ - "=mtdoops\0" \ - COMMON_ENV_DFU_ARGS \ - "dfu_alt_info=" DFU_ALT_INFO_NAND_V2 "\0" \ - COMMON_ENV_NAND_BOOT \ - "ubi part rootfs ${ubi_off};" \ - "ubifsmount ubi0:${nand_active_ubi_vol};" \ - "ubifsload ${kloadaddr} boot/${kernel_name};" \ - "ubifsload ${loadaddr} boot/${dtb_name}.dtb;" \ - "bootm ${kloadaddr} - ${loadaddr}\0" \ - "nand_boot_backup=ubifsload ${loadaddr} boot/am335x-draco.dtb;" \ - "bootm ${kloadaddr} - ${loadaddr}\0" \ - COMMON_ENV_NAND_CMDS - -#define CONFIG_ENV_SETTINGS_V2 \ - COMMON_ENV_SETTINGS \ - "net_args=run bootargs_defaults;" \ - "mtdparts default;" \ - "setenv bootfile ${project_dir}/kernel/uImage;" \ - "setenv bootdtb ${project_dir}/kernel/dtb;" \ - "setenv rootpath /home/projects/${project_dir}/rootfs;" \ - "setenv bootargs ${bootargs} " \ - "root=/dev/nfs ${mtdparts} " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} " \ - "ip=${ipaddr}:${serverip}:" \ - "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ - "net_nfs=echo Booting from network ...; " \ - "run net_args; " \ - "tftpboot ${kloadaddr} ${serverip}:${bootfile}; " \ - "tftpboot ${loadaddr} ${serverip}:${bootdtb}; " \ - "bootm ${kloadaddr} - ${loadaddr}\0" - -/* - * Variant 3 partition layout - * chip-size = 512MiB - *| name | size | address area | - *------------------------------------------------------- - *| spl | 128.000 KiB | 0x 0..0x 1ffff | - *| spl.backup1 | 128.000 KiB | 0x 20000..0x 3ffff | - *| spl.backup2 | 128.000 KiB | 0x 40000..0x 5ffff | - *| spl.backup3 | 128.000 KiB | 0x 60000..0x 7ffff | - *| u-boot | 1.875 MiB | 0x 80000..0x 25ffff | - *| uboot.env0 | 512.000 KiB | 0x 260000..0x 2Dffff | - *| uboot.env1 | 512.000 KiB | 0x 2E0000..0x 35ffff | - *| rootfs | 300.000 MiB | 0x 360000..0x12f5ffff | - *| mtdoops | 512.000 KiB | 0x12f60000..0x12fdffff | - *|configuration | 104.125 MiB | 0x12fe0000..0x1fffffff | - *------------------------------------------------------- - - "mtdparts=omap2-nand.0:" \ - "128k(spl)," \ - "128k(spl.backup1)," \ - "128k(spl.backup2)," \ - "128k(spl.backup3)," \ - "1920k(u-boot)," \ - "512k(u-boot.env0)," \ - "512k(u-boot.env1)," \ - "300m(rootfs)," \ - "512k(mtdoops)," \ - "-(configuration)" - - */ - -#define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND - devices */ -#if !defined(CONFIG_SPI_BOOT) -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ -#endif -#endif - -/* Reboot after 60 sec if bootcmd fails */ -#define CONFIG_RESET_TO_RETRY -#define CONFIG_BOOT_RETRY_TIME 60 - -#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h deleted file mode 100644 index 736ceb1..0000000 --- a/include/configs/sifive-fu540.h +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2019 Western Digital Corporation or its affiliates. - * - * Authors: - * Anup Patel - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_2M) - -#define CONFIG_SYS_MALLOC_LEN SZ_8M - -#define CONFIG_SYS_BOOTM_LEN SZ_64M - -#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000 - -/* Environment options */ -#define CONFIG_ENV_SIZE SZ_128K - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "kernel_addr_r=0x84000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "scriptaddr=0x88100000\0" \ - "pxefile_addr_r=0x88200000\0" \ - "ramdisk_addr_r=0x88300000\0" \ - BOOTENV - -#define CONFIG_PREBOOT \ - "setenv fdt_addr ${fdtcontroladdr};" \ - "fdt addr ${fdtcontroladdr};" - -#endif /* __CONFIG_H */ diff --git a/include/configs/silk.h b/include/configs/silk.h deleted file mode 100644 index a78da46..0000000 --- a/include/configs/silk.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/silk.h - * This file is silk board configuration. - * - * Copyright (C) 2015 Renesas Electronics Corporation - * Copyright (C) 2015 Cogent Embedded, Inc. - */ - -#ifndef __SILK_H -#define __SILK_H - -#include "rcar-gen2-common.h" - -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 -#define STACK_AREA_SIZE 0x00100000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) -#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -/* FLASH */ -#define CONFIG_SPI_FLASH_QUAD - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" - -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_CONS_SCIF2 -#define CONFIG_SH_SCIF_CLK_FREQ 65000000 -#endif - -#endif /* __SILK_H */ diff --git a/include/configs/sksimx6.h b/include/configs/sksimx6.h deleted file mode 100644 index 4f7ec2d..0000000 --- a/include/configs/sksimx6.h +++ /dev/null @@ -1,96 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic - */ - - -#ifndef __SKSIMX6_CONFIG_H -#define __SKSIMX6_CONFIG_H - -#include "mx6_common.h" -#include "imx6_spl.h" - -/* Thermal */ -#define CONFIG_IMX_THERMAL - -/* Serial */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M) - -/* Ethernet */ -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x01 - -#define CONFIG_PHY_MICREL_KSZ9021 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C2 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* Filesystem support */ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -/* Environment organization */ -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -/* Default environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addcons=setenv bootargs ${bootargs} " \ - "console=${console},${baudrate}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} ${miscargs}\0" \ - "bootcmd=run mmcboot\0" \ - "bootfile=uImage\0" \ - "bootimage=uImage\0" \ - "console=ttymxc0\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_file=imx6dl-sks-cts.dtb\0" \ - "fdt_high=0xffffffff\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "miscargs=quiet\0" \ - "mmcargs=setenv bootargs root=${mmcroot} rw rootwait\0" \ - "mmcboot=if run mmcload;then " \ - "run mmcargs addcons addmisc;" \ - "bootm;fi\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:${mmcpart} ${kernel_addr_r} boot/fitImage\0"\ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p1\0" \ - "net_nfs=tftp ${kernel_addr_r} ${board_name}/${bootfile};" \ - "tftp ${fdt_addr_r} ${board_name}/${fdt_file};" \ - "run nfsargs addip addcons addmisc;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "nfsargs=setenv bootargs root=/dev/nfs " \ - "nfsroot=${serverip}:${nfsroot},v3 panic=1\0" - -#endif diff --git a/include/configs/slimbootloader.h b/include/configs/slimbootloader.h deleted file mode 100644 index e0011ed..0000000 --- a/include/configs/slimbootloader.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 Intel Corporation - */ - -#ifndef __SLIMBOOTLOADER_CONFIG_H__ -#define __SLIMBOOTLOADER_CONFIG_H__ - -#include - -/* - * By default, CONFIG_SYS_NS16550_PORT_MAPPED is enabled for port io serial. - * To use mmio base serial, enable CONFIG_SYS_NS16550_MEM32 and disable - * CONFIG_SYS_NS16550_PORT_MAPPED until ns16550 driver supports serial port - * configuration in run-time. - * - * #define CONFIG_SYS_NS16550_MEM32 - * #undef CONFIG_SYS_NS16550_PORT_MAPPED - */ -#ifdef CONFIG_SYS_NS16550_MEM32 -#undef CONFIG_SYS_NS16550_PORT_MAPPED -#endif - -#define CONFIG_STD_DEVICES_SETTINGS \ - "stdin=serial,i8042-kbd,usbkbd\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -/* - * Override CONFIG_EXTRA_ENV_SETTINGS in x86-common.h - */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_STD_DEVICES_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=0x4000000\0" \ - "ramdiskfile=initrd\0" \ - "bootdev=usb\0" \ - "bootdevnum=0\0" \ - "bootdevpart=0\0" \ - "bootfsload=fatload\0" \ - "bootusb=setenv bootdev usb; boot\0" \ - "bootscsi=setenv bootdev scsi; boot\0" \ - "bootmmc=setenv bootdev mmc; boot\0" \ - "bootargs=console=ttyS0,115200 console=tty0\0" - -/* - * Override CONFIG_BOOTCOMMAND in x86-common.h - */ -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND \ - "if test ${bootdev} = \"usb\"; then ${bootdev} start; fi; " \ - "if test ${bootdev} = \"scsi\"; then ${bootdev} scan; fi; " \ - "${bootdev} info; " \ - "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \ - "${loadaddr} ${bootfile}; " \ - "${bootfsload} ${bootdev} ${bootdevnum}:${bootdevpart} " \ - "${ramdiskaddr} ${ramdiskfile}; " \ - "zboot ${loadaddr} 0 ${ramdiskaddr} ${filesize}" - -#endif /* __SLIMBOOTLOADER_CONFIG_H__ */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h deleted file mode 100644 index c1a43a5..0000000 --- a/include/configs/smartweb.h +++ /dev/null @@ -1,220 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - * - * (C) Copyright 2010 - * Achim Ehrlich - * taskit GmbH - * - * (C) Copyright 2012 - * Markus Hubig - * IMKO GmbH - * - * (C) Copyright 2014 - * Heiko Schocher - * DENX Software Engineering GmbH - * - * Configuation settings for the smartweb. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include -#include - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot - * program. Since the linker has to swallow that define, we must use a pure - * hex number here! - */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ - -/* misc settings */ -#define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ -#define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ -#define CONFIG_INITRD_TAG /* pass initrd param to kernel */ -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */ - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 32 - -/* setting board specific options */ -#define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB -#define CONFIG_ENV_OVERWRITE 1 /* Overwrite ethaddr / serial# */ -#define CONFIG_SYS_AUTOLOAD "yes" -#define CONFIG_RESET_TO_RETRY - -/* The LED PINs */ -#define CONFIG_RED_LED AT91_PIN_PA9 -#define CONFIG_GREEN_LED AT91_PIN_PA6 - -/* - * SDRAM: 1 bank, 64 MB, base address 0x20000000 - * Already initialized before u-boot gets started. - */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M) - -/* - * Perform a SDRAM Memtest from the start of SDRAM - * till the beginning of the U-Boot position in RAM. - */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000) - -/* NAND flash settings */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO /* enable the GPIO features */ -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* - * Ethernet configuration - * - */ -#define CONFIG_MACB -#define CONFIG_RMII /* use reduced MII inteface */ -#define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* BOOTP and DHCP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_NFSBOOTCOMMAND \ - "setenv autoload yes; setenv autoboot yes; " \ - "setenv bootargs ${basicargs} ${mtdparts} " \ - "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ - "dhcp" - -#if !defined(CONFIG_SPL_BUILD) -/* USB configuration */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -/* USB DFU support */ - -#define CONFIG_USB_GADGET_AT91 - -/* DFU class support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M -#define DFU_MANIFEST_POLL_TIMEOUT 25000 -#endif - -/* General Boot Parameter */ -#define CONFIG_BOOTCOMMAND "run flashboot" -#define CONFIG_SYS_CBSIZE 512 - -/* - * RAM Memory address where to put the - * Linux Kernel befor starting. - */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - -/* - * The NAND Flash partitions: - */ -#define CONFIG_ENV_OFFSET_REDUND (0x180000) -#define CONFIG_ENV_RANGE (SZ_512K) - -/* - * Predefined environment variables. - * Usefull to define some easy to use boot commands. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - \ - "basicargs=console=ttyS0,115200\0" \ - \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x301000 -#define CONFIG_SPL_STACK_R -#define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE -#else -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above that - * address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) -#endif - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SZ_4K) - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE -#define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN - -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) -#define CONFIG_SYS_USE_NANDFLASH 1 -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - -#define CONFIG_SYS_NAND_SIZE (SZ_256M) -#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K -#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK (198656000/2) -#define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x2060bf09 -#define CONFIG_SYS_MCKR 0x100 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10483f0e - -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - -#endif /* __CONFIG_H */ diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h deleted file mode 100644 index 82251b3..0000000 --- a/include/configs/smdk5250.h +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Samsung Electronics - * - * Configuration settings for the SAMSUNG SMDK5250 board. - */ - -#ifndef __CONFIG_SMDK_H -#define __CONFIG_SMDK_H - -#include -#include -#include - -#undef CONFIG_EXYNOS_FB -#undef CONFIG_EXYNOS_DP -#undef CONFIG_KEYBOARD - -#define CONFIG_BOARD_COMMON - -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -#endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h deleted file mode 100644 index 14ec099..0000000 --- a/include/configs/smdk5420.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG SMDK5420 board. - */ - -#ifndef __CONFIG_SMDK5420_H -#define __CONFIG_SMDK5420_H - -#include -#include -#include - -#undef CONFIG_EXYNOS_FB -#undef CONFIG_EXYNOS_DP - -#undef CONFIG_KEYBOARD - -#define CONFIG_BOARD_COMMON - -#define CONFIG_SMDK5420 /* which is in a SMDK5420 */ - -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800) - -/* select serial console configuration */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -/* USB */ -#define CONFIG_USB_XHCI_EXYNOS - -/* DRAM Memory Banks */ -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ - -#endif /* __CONFIG_SMDK5420_H */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h deleted file mode 100644 index 1d09792..0000000 --- a/include/configs/smdkc100.h +++ /dev/null @@ -1,159 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Samsung Electronics - * Minkyu Kang - * HeungJun Kim - * Inki Dae - * - * Configuation settings for the SAMSUNG SMDKC100 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* which is in a S5P Family */ -#define CONFIG_S5PC100 1 /* which is in a S5PC100 */ - -#include /* get chip and board defs */ - -/* input clock of PLL: SMDKC100 has 12MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 12000000 - -/* DRAM Base */ -#define CONFIG_SYS_SDRAM_BASE 0x30000000 - -/* Text Base */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - * 1MB = 0x100000, 0x100000 = 1024 * 1024 - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - -/* - * select serial console configuration - */ - -/* PWM */ -#define CONFIG_PWM 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BOOTCOMMAND "run ubifsboot" - -#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \ - " console=ttySAC0,115200n8" \ - " mem=128M" - -#define CONFIG_COMMON_BOOT "console=ttySAC0,115200n8" \ - " mem=128M " \ - " " CONFIG_MTDPARTS_DEFAULT - -#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \ - " onenand write 0x32008000 0x0 0x40000\0" - -#define CONFIG_ENV_OVERWRITE -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_UPDATEB \ - "updatek=" \ - "onenand erase 0x60000 0x300000;" \ - "onenand write 0x31008000 0x60000 0x300000\0" \ - "updateu=" \ - "onenand erase block 147-4095;" \ - "onenand write 0x32000000 0x1260000 0x8C0000\0" \ - "bootk=" \ - "onenand read 0x30007FC0 0x60000 0x300000;" \ - "bootm 0x30007FC0\0" \ - "flashboot=" \ - "set bootargs root=/dev/mtdblock${bootblock} " \ - "rootfstype=${rootfstype} " \ - "ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \ - "run bootk\0" \ - "ubifsboot=" \ - "set bootargs root=ubi0!rootfs rootfstype=ubifs " \ - " ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \ - "run bootk\0" \ - "boottrace=setenv opts initcall_debug; run bootcmd\0" \ - "android=" \ - "set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \ - "rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \ - "run bootk\0" \ - "nfsboot=" \ - "set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \ - "nfsroot=${nfsroot},nolock " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \ - "run bootk\0" \ - "ramboot=" \ - "set bootargs " CONFIG_RAMDISK_BOOT \ - " initrd=0x33000000,8M ramdisk=8192\0" \ - "rootfstype=cramfs\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "meminfo=mem=128M\0" \ - "nfsroot=/nfsroot/arm\0" \ - "bootblock=5\0" \ - "ubiblock=4\0" \ - "ubi=enabled" - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000) -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ - -#if !defined(CONFIG_NAND_SPL) && (CONFIG_SYS_TEXT_BASE >= 0xc0000000) -#define CONFIG_ENABLE_MMU -#endif - -#ifdef CONFIG_ENABLE_MMU -#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000 -#else -#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE -#endif - -/*----------------------------------------------------------------------- - * Boot configuration - */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128KiB, 0x20000 */ -#define CONFIG_ENV_ADDR (256 << 10) /* 256KiB, 0x40000 */ -#define CONFIG_ENV_OFFSET (256 << 10) /* 256KiB, 0x40000 */ - -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SAMSUNG_ONENAND 1 -#define CONFIG_SYS_ONENAND_BASE 0xE7100000 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - 0x1000000) - -/* - * Ethernet Contoller driver - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ -#endif /* CONFIG_CMD_NET */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h deleted file mode 100644 index 68af0ef..0000000 --- a/include/configs/smdkv310.h +++ /dev/null @@ -1,87 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Samsung Electronics - * - * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "exynos4-common.h" - -#undef CONFIG_BOARD_COMMON -#undef CONFIG_USB_GADGET_DWC2_OTG_PHY -#undef CONFIG_REVISION_TAG - -/* High Level Configuration Options */ -#define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ - -/* Mach Type */ -#define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 - -/* Handling Sleep Mode*/ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* select serial console configuration */ -#define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* MMC SPL */ -#define CONFIG_SKIP_LOWLEVEL_INIT -#define COPY_BL2_FNPTR_ADDR 0x00002488 - -#define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" - -/* Miscellaneous configurable options */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -/* SMDKV310 has 4 bank of DRAM */ -#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE - -/* FLASH and environment organization */ - -#define CONFIG_CLK_1000_400_200 - -/* MIU (Memory Interleaving Unit) */ -#define CONFIG_MIU_2BIT_INTERLEAVED - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ -#define RESERVE_BLOCK_SIZE (512) -#define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) - -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_SYS_INIT_SP_ADDR 0x02040000 - -/* U-Boot copy size from boot Media to DRAM.*/ -#define COPY_BL2_SIZE 0x80000 -#define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) -#define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) - -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h deleted file mode 100644 index b0408a5..0000000 --- a/include/configs/snapper9260.h +++ /dev/null @@ -1,120 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Bluewater Systems Snapper 9260 and 9G20 modules - * - * (C) Copyright 2011 Bluewater Systems - * Author: Andre Renaud - * Author: Ryan Mallon - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SoC type is defined in boards.cfg */ -#include -#include - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -/* CPU */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) - -/* Mem test settings */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) - -/* NAND Flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_TFTP_PORT -#define CONFIG_TFTP_TSIZE - -/* USB */ -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -/* GPIOs and IO expander */ -#define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } - -/* UARTs/Serial console */ -#define CONFIG_ATMEL_USART -#ifndef CONFIG_DM_SERIAL -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS -#endif - -/* I2C - Bit-bashed */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 100000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define CONFIG_SOFT_I2C_READ_REPEATED_START -#define I2C_INIT do { \ - at91_set_gpio_output(AT91_PIN_PA23, 1); \ - at91_set_gpio_output(AT91_PIN_PA24, 1); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ - at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ - } while (0) -#define I2C_SOFT_DECLARATIONS -#define I2C_ACTIVE -#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); -#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); -#define I2C_SDA(bit) do { \ - if (bit) { \ - at91_set_gpio_input(AT91_PIN_PA23, 1); \ - } else { \ - at91_set_gpio_output(AT91_PIN_PA23, 1); \ - at91_set_gpio_value(AT91_PIN_PA23, bit); \ - } \ - } while (0) -#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) -#define I2C_DELAY udelay(2) - -/* Boot options */ -#define CONFIG_SYS_LOAD_ADDR 0x23000000 - -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Environment settings */ -#define CONFIG_ENV_OVERWRITE - -/* Console settings */ - -/* U-Boot memory settings */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - -#endif /* __CONFIG_H */ diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h deleted file mode 100644 index ffcfdca..0000000 --- a/include/configs/snapper9g45.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Bluewater Systems Snapper 9G45 module - * - * (C) Copyright 2011 Bluewater Systems - * Author: Andre Renaud - * Author: Ryan Mallon - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* SoC type is defined in boards.cfg */ -#include -#include - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -/* CPU */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 64MB */ -#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \ - GENERATED_GBL_DATA_SIZE) - -/* Mem test settings */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) - -/* NAND Flash */ -#define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_RESET_PHY_R -#define CONFIG_AT91_WANTS_COMMON_PHY -#define CONFIG_TFTP_PORT -#define CONFIG_TFTP_TSIZE - -/* MMC */ -#define CONFIG_GENERIC_ATMEL_MCI - -/* LCD */ -#define CONFIG_ATMEL_LCD -#define CONFIG_GURNARD_SPLASH - -/* GPIOs and IO expander */ -#define CONFIG_ATMEL_LEGACY -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 - -/* UARTs/Serial console */ -#define CONFIG_ATMEL_USART - -/* Boot options */ -#define CONFIG_SYS_LOAD_ADDR 0x23000000 - -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Environment settings */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethaddr=00:00:00:00:00:00\0" \ - "serial=0\0" \ - "stdout=serial_atmel\0" \ - "stderr=serial_atmel\0" \ - "stdin=serial_atmel\0" \ - "bootlimit=3\0" \ - "loadaddr=0x71000000\0" \ - "board_rev=2\0" \ - "bootfile=/tftpboot/uImage\0" \ - "bootargs_def=console=ttyS0,115200 panic=5 quiet lpj=997376\0" \ - "nfsroot=/export/root\0" \ - "boot_working=setenv bootargs $bootargs_def; nboot $loadaddr 0 0x20c0000 && bootm\0" \ - "boot_safe=setenv bootargs $bootargs_def; nboot $loadaddr 0 0xc0000 && bootm\0" \ - "boot_tftp=setenv bootargs $bootargs_def ip=any nfsroot=$nfsroot; setenv autoload y && bootp && bootm\0" \ - "boot_usb=setenv bootargs $bootargs_def; usb start && usb storage && fatload usb 0:1 $loadaddr dds-xm200.bin && bootm\0" \ - "boot_mmc=setenv bootargs $bootargs_def; mmc rescan && fatload mmc 0:1 $loadaddr dds-xm200.bin && bootm\0" \ - "bootcmd=run boot_mmc ; run boot_usb ; run boot_working ; run boot_safe\0" \ - "altbootcmd=run boot_mmc ; run boot_usb ; run boot_safe ; run boot_working\0" - -/* Console settings */ - -/* U-Boot memory settings */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - -/* Command line configuration */ -#define CONFIG_CMD_MII -#define CONFIG_CMD_MMC -#define CONFIG_CMD_CACHE - -#endif /* __CONFIG_H */ diff --git a/include/configs/sniper.h b/include/configs/sniper.h deleted file mode 100644 index 0e2fcc3..0000000 --- a/include/configs/sniper.h +++ /dev/null @@ -1,151 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * LG Optimus Black codename sniper config - * - * Copyright (C) 2015 Paul Kocialkowski - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include - -/* - * CPU - */ - -#define CONFIG_ARM_ARCH_CP15_ERRATA - -/* - * Board - */ - -/* - * Clocks - */ - -#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 -#define CONFIG_SYS_PTV 2 - -#define V_NS16550_CLK 48000000 -#define V_OSCK 26000000 -#define V_SCLK (V_OSCK >> 1) - -/* - * DRAM - */ - -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * Memory - */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024 + CONFIG_ENV_SIZE) - -/* - * I2C - */ - -#define CONFIG_SYS_I2C -#define CONFIG_I2C_MULTI_BUS - -/* - * Input - */ - -/* - * SPL - */ - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE (512 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE (1024 * 1024) -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SYS_CBSIZE 512 - -/* - * Serial - */ - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -#define CONFIG_SYS_BAUDRATE_TABLE { 4800, 9600, 19200, 38400, 57600, \ - 115200 } - -/* - * Environment - */ - -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x82000000\0" \ - "loadaddr=0x82000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "fdtaddr=0x88000000\0" \ - "ramdisk_addr_r=0x88080000\0" \ - "pxefile_addr_r=0x80100000\0" \ - "scriptaddr=0x80000000\0" \ - "bootm_size=0x10000000\0" \ - "boot_mmc_dev=0\0" \ - "kernel_mmc_part=3\0" \ - "recovery_mmc_part=4\0" \ - "fdtfile=omap3-sniper.dtb\0" \ - "bootfile=/boot/extlinux/extlinux.conf\0" \ - "bootargs=console=ttyO2,115200 vram=5M,0x9FA00000 omapfb.vram=0:5M\0" - -/* - * ATAGs - */ - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG -#define CONFIG_SERIAL_TAG - -/* - * Boot - */ - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -#define CONFIG_BOOTCOMMAND \ - "setenv boot_mmc_part ${kernel_mmc_part}; " \ - "if test reboot-${reboot-mode} = reboot-r; then " \ - "echo recovery; setenv boot_mmc_part ${recovery_mmc_part}; fi; " \ - "if test reboot-${reboot-mode} = reboot-b; then " \ - "echo fastboot; fastboot 0; fi; " \ - "part start mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_start; " \ - "part size mmc ${boot_mmc_dev} ${boot_mmc_part} boot_mmc_size; " \ - "mmc dev ${boot_mmc_dev}; " \ - "mmc read ${kernel_addr_r} ${boot_mmc_start} ${boot_mmc_size} && " \ - "bootm ${kernel_addr_r};" - -/* - * Defaults - */ - -#include - -#endif diff --git a/include/configs/snow.h b/include/configs/snow.h deleted file mode 100644 index c546a5a..0000000 --- a/include/configs/snow.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * - * Configuration settings for the SAMSUNG EXYNOS5 Snow board. - */ - -#ifndef __CONFIG_SNOW_H -#define __CONFIG_SNOW_H - -#define EXYNOS_FDTFILE_SETTING \ - "fdtfile=exynos5250-snow.dtb\0" - -#include -#include -#include - -#define CONFIG_BOARD_COMMON - -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -#endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/socfpga_arria10_socdk.h b/include/configs/socfpga_arria10_socdk.h deleted file mode 100644 index 645e66e..0000000 --- a/include/configs/socfpga_arria10_socdk.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2015-2019 Altera Corporation - */ - -#ifndef __CONFIG_SOCFGPA_ARRIA10_H__ -#define __CONFIG_SOCFGPA_ARRIA10_H__ - -#include - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * U-Boot general configurations - */ - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 - -/* - * Serial / UART configurations - */ -#define CONFIG_SYS_NS16550_MEM32 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200} - -/* - * L4 OSC1 Timer 0 - */ -/* reload value when timer count to zero */ -#define TIMER_LOAD_VAL 0xFFFFFFFF - -/* - * Flash configurations - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -/* SPL memory allocation configuration, this is for FAT implementation */ -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000 - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */ diff --git a/include/configs/socfpga_arria5_socdk.h b/include/configs/socfpga_arria5_socdk.h deleted file mode 100644 index af6137a..0000000 --- a/include/configs/socfpga_arria5_socdk.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Marek Vasut - */ -#ifndef __CONFIG_SOCFPGA_ARRIA5_H__ -#define __CONFIG_SOCFPGA_ARRIA5_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h deleted file mode 100644 index 94268ed..0000000 --- a/include/configs/socfpga_common.h +++ /dev/null @@ -1,268 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Altera Corporation - */ -#ifndef __CONFIG_SOCFPGA_COMMON_H__ -#define __CONFIG_SOCFPGA_COMMON_H__ - -/* - * High level configuration - */ -#define CONFIG_CLOCKS - -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * Memory configurations - */ -#define PHYS_SDRAM_1 0x0 -#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -/* SPL memory allocation configuration, this is for FAT implementation */ -#ifndef CONFIG_SYS_SPL_MALLOC_SIZE -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 -#endif -#define CONFIG_SYS_INIT_RAM_SIZE (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE) -#endif - -/* - * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal - * SRAM as bootcounter storage. Make sure to not put the stack directly - * at this address to not overwrite the bootcounter by checking, if the - * bootcounter address is located in the internal SRAM. - */ -#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ - (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE))) -#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR -#else -#define CONFIG_SPL_STACK \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) -#endif - -/* - * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc - * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage - * in U-Boot pre-reloc is higher than in SPL. - */ -#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR -#else -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK -#endif - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ - /* Print buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* - * Cache - */ -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS - -/* - * Ethernet on SoC (EMAC) - */ -#ifdef CONFIG_CMD_NET -#define CONFIG_DW_ALTDESCRIPTOR -#endif - -/* - * FPGA Driver - */ -#ifdef CONFIG_CMD_FPGA -#define CONFIG_FPGA_COUNT 1 -#endif - -/* - * L4 OSC1 Timer 0 - */ -#ifndef CONFIG_TIMER -/* This timer uses eosc1, whose clock frequency is fixed at any condition. */ -#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) -#define CONFIG_SYS_TIMER_RATE 25000000 -#endif - -/* - * L4 Watchdog - */ -#ifdef CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS -#define CONFIG_DW_WDT_CLOCK_KHZ 25000 -#endif - -/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -/* FIXME */ -/* using smaller max blk cnt to avoid flooding the limited stack we have */ -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ -#endif - -/* - * NAND Support - */ -#ifdef CONFIG_NAND_DENALI -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS -#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS -#endif - -/* - * QSPI support - */ -/* Enable multiple SPI NOR flash manufacturers */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SPI_FLASH_MTD -#endif -/* QSPI reference clock */ -#ifndef __ASSEMBLY__ -unsigned int cm_get_qspi_controller_clk_hz(void); -#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() -#endif - -/* - * USB - */ - -/* - * USB Gadget (DFU, UMS) - */ -#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024) -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB IDs */ -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 -#endif - -/* - * U-Boot environment - */ -#if !defined(CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE (8 * 1024) -#endif - -/* Environment for SDMMC boot */ -#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET) -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */ -#endif - -/* Environment for QSPI boot */ -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) -#define CONFIG_ENV_OFFSET 0x00100000 -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#endif - -/* - * SPL - * - * SRAM Memory layout for gen 5: - * - * 0xFFFF_0000 ...... Start of SRAM - * 0xFFFF_xxxx ...... Top of stack (grows down) - * 0xFFFF_yyyy ...... Global Data - * 0xFFFF_zzzz ...... Malloc area - * 0xFFFF_FFFF ...... End of SRAM - * - * SRAM Memory layout for Arria 10: - * 0xFFE0_0000 ...... Start of SRAM (bottom) - * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) - * 0xFFEy_yyyy ...... Global Data - * 0xFFEz_zzzz ...... Malloc area (grows up to top) - * 0xFFE3_FFFF ...... End of SRAM (top) - */ -#ifndef CONFIG_SPL_TEXT_BASE -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE -#endif - -/* SPL SDMMC boot support */ -#ifdef CONFIG_SPL_MMC_SUPPORT -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#endif -#else -#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 -#endif -#endif - -/* SPL QSPI boot support */ - -/* SPL NAND boot support */ -#ifdef CONFIG_SPL_NAND_SUPPORT -#if defined(CONFIG_TARGET_SOCFPGA_GEN5) -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 -#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x100000 -#endif -#endif - -/* Extra Environment */ -#ifndef CONFIG_SPL_BUILD - -#ifdef CONFIG_CMD_DHCP -#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) -#else -#define BOOT_TARGET_DEVICES_DHCP(func) -#endif - -#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) -#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) -#else -#define BOOT_TARGET_DEVICES_PXE(func) -#endif - -#ifdef CONFIG_CMD_MMC -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) -#else -#define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_PXE(func) \ - BOOT_TARGET_DEVICES_DHCP(func) - -#include - -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "bootm_size=0xa000000\0" \ - "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ - "fdt_addr_r=0x02000000\0" \ - "scriptaddr=0x02100000\0" \ - "pxefile_addr_r=0x02200000\0" \ - "ramdisk_addr_r=0x02300000\0" \ - "socfpga_legacy_reset_compat=1\0" \ - BOOTENV - -#endif -#endif - -#endif /* __CONFIG_SOCFPGA_COMMON_H__ */ diff --git a/include/configs/socfpga_cyclone5_socdk.h b/include/configs/socfpga_cyclone5_socdk.h deleted file mode 100644 index 028db2a..0000000 --- a/include/configs/socfpga_cyclone5_socdk.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Marek Vasut - */ -#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__ -#define __CONFIG_SOCFPGA_CYCLONE5_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */ diff --git a/include/configs/socfpga_dbm_soc1.h b/include/configs/socfpga_dbm_soc1.h deleted file mode 100644 index befaeaa..0000000 --- a/include/configs/socfpga_dbm_soc1.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Marek Vasut - */ -#ifndef __CONFIG_DEVBOARDS_DBM_SOC1_H__ -#define __CONFIG_DEVBOARDS_DBM_SOC1_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Environment is in MMC */ -#define CONFIG_ENV_OVERWRITE - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttyS0\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "bootdev=/dev/mmcblk0p2\0" \ - "rootdev=/dev/mmcblk0p3\0" \ - "netdev=eth0\0" \ - "hostname=dbm_soc1\0" \ - "kernel_addr_r=0x10000000\0" \ - "dfu_alt_info=mmc raw 0 3867148288\0" \ - "update_filename=u-boot-with-spl.sfp\0" \ - "update_sd_offset=0x800\0" \ - "update_sd=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "fpga_filename=output_file.rbf\0" \ - "load_fpga=" /* Load FPGA bitstream */ \ - "if tftp ${fpga_filename} ; then " \ - "fpga load 0 $loadaddr $filesize ; " \ - "bridge enable ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=${rootdev} rw rootwait\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:2 ${bootscript} ; then " \ - "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" \ - "socfpga_legacy_reset_compat=1\0" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_DEVBOARDS_DBM_SOC1_H__ */ diff --git a/include/configs/socfpga_de0_nano_soc.h b/include/configs/socfpga_de0_nano_soc.h deleted file mode 100644 index 21108e3..0000000 --- a/include/configs/socfpga_de0_nano_soc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Marek Vasut - */ -#ifndef __CONFIG_TERASIC_DE0_H__ -#define __CONFIG_TERASIC_DE0_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_TERASIC_DE0_H__ */ diff --git a/include/configs/socfpga_de10_nano.h b/include/configs/socfpga_de10_nano.h deleted file mode 100644 index d85f98f..0000000 --- a/include/configs/socfpga_de10_nano.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, Intel Corporation - */ -#ifndef __CONFIG_TERASIC_DE10_H__ -#define __CONFIG_TERASIC_DE10_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_TERASIC_DE10_H__ */ diff --git a/include/configs/socfpga_de1_soc.h b/include/configs/socfpga_de1_soc.h deleted file mode 100644 index 9919d29..0000000 --- a/include/configs/socfpga_de1_soc.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Marek Vasut - */ -#ifndef __CONFIG_TERASIC_DE1_SOC_H__ -#define __CONFIG_TERASIC_DE1_SOC_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB */ - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_TERASIC_DE1_SOC_H__ */ diff --git a/include/configs/socfpga_is1.h b/include/configs/socfpga_is1.h deleted file mode 100644 index c4da594..0000000 --- a/include/configs/socfpga_is1.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Marek Vasut - * Copyright (C) 2016 Pavel Machek - */ -#ifndef __CONFIG_SOCFPGA_IS1_H__ -#define __CONFIG_SOCFPGA_IS1_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x10000000 - -/* Booting Linux */ -#define CONFIG_BOOTFILE "zImage" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_ARP_TIMEOUT 500UL -#endif - -/* The rest of the configuration is shared */ -#include - -/* - * Bootcounter - */ -#define CONFIG_SYS_BOOTCOUNT_BE - -#endif /* __CONFIG_SOCFPGA_IS1_H__ */ diff --git a/include/configs/socfpga_mcvevk.h b/include/configs/socfpga_mcvevk.h deleted file mode 100644 index 590a9af..0000000 --- a/include/configs/socfpga_mcvevk.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Marek Vasut - */ -#ifndef __CONFIG_ARIES_MCVEVK_H__ -#define __CONFIG_ARIES_MCVEVK_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on MCV */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_BOOTCOMMAND "run mmc_mmc" -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Environment is in MMC */ -#define CONFIG_ENV_OVERWRITE - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "consdev=ttyS0\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "setuuid=part uuid mmc 0:3 uuid\0" \ - "netdev=eth0\0" \ - "hostname=mcvevk\0" \ - "kernel_addr_r=0x10000000\0" \ - "socfpga_legacy_reset_compat=1\0" \ - "bootm_size=0xa000000\0" \ - "dfu_alt_info=mmc raw 0 3867148288\0" \ - "update_filename=u-boot-with-spl.sfp\0" \ - "update_sd_offset=0x800\0" \ - "update_sd=" /* Update the SD firmware partition */ \ - "if mmc rescan ; then " \ - "if tftp ${update_filename} ; then " \ - "setexpr fw_sz ${filesize} / 0x200 ; " /* SD block size */ \ - "setexpr fw_sz ${fw_sz} + 1 ; " \ - "mmc write ${loadaddr} ${update_sd_offset} ${fw_sz} ; " \ - "fi ; " \ - "fi\0" \ - "update_qspi_offset=0x0\0" \ - "update_qspi=" /* Update the QSPI firmware */ \ - "if sf probe ; then " \ - "if tftp ${update_filename} ; then " \ - "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ - "fi ; " \ - "fi\0" \ - "fpga_filename=output_file.rbf\0" \ - "load_fpga=" /* Load FPGA bitstream */ \ - "if tftp ${fpga_filename} ; then " \ - "fpga load 0 $loadaddr $filesize ; " \ - "bridge enable ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addargs=run addcons addmisc\0" \ - "mmcload=" \ - "mmc rescan ; " \ - "load mmc 0:2 ${kernel_addr_r} ${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "mmcargs=setenv bootargs root=PARTUUID=${uuid} rw rootwait\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "mmc_mmc=" \ - "run mmcload setuuid mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "mmc_nfs=" \ - "run mmcload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_mmc=" \ - "run netload setuuid mmcargs addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs ; " \ - "bootm ${kernel_addr_r}\0" \ - "try_bootscript=" \ - "mmc rescan;" \ - "if test -e mmc 0:2 ${bootscript} ; then " \ - "if load mmc 0:2 ${kernel_addr_r} ${bootscript};" \ - "then ; " \ - "echo Running bootscript... ; " \ - "source ${kernel_addr_r} ; " \ - "fi ; " \ - "fi\0" - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_ARIES_MCVEVK_H__ */ diff --git a/include/configs/socfpga_sockit.h b/include/configs/socfpga_sockit.h deleted file mode 100644 index 9729999..0000000 --- a/include/configs/socfpga_sockit.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Marek Vasut - */ -#ifndef __CONFIG_TERASIC_SOCKIT_H__ -#define __CONFIG_TERASIC_SOCKIT_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_TERASIC_SOCKIT_H__ */ diff --git a/include/configs/socfpga_socrates.h b/include/configs/socfpga_socrates.h deleted file mode 100644 index 7faea15..0000000 --- a/include/configs/socfpga_socrates.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Marek Vasut - */ -#ifndef __CONFIG_SOCFPGA_SOCRATES_H__ -#define __CONFIG_SOCFPGA_SOCRATES_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCrates */ - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFPGA_SOCRATES_H__ */ diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h deleted file mode 100644 index 3a8ccc3..0000000 --- a/include/configs/socfpga_sr1500.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Stefan Roese - */ -#ifndef __CONFIG_SOCFPGA_SR1500_H__ -#define __CONFIG_SOCFPGA_SR1500_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ - -/* Booting Linux */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Ethernet on SoC (EMAC) */ -#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII -/* The PHY is autodetected, so no MII PHY address is needed here */ -#define PHY_ANEG_TIMEOUT 8000 - -/* Enable SPI NOR flash reset, needed for SPI booting */ -#define CONFIG_SPI_N25Q256A_RESET - -/* - * Bootcounter - */ -#define CONFIG_SYS_BOOTCOUNT_BE - -/* Environment setting for SPI flash */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_OFFSET 0x000e0000 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOCFPGA_SR1500_H__ */ diff --git a/include/configs/socfpga_stratix10_socdk.h b/include/configs/socfpga_stratix10_socdk.h deleted file mode 100644 index 8e6ecf4..0000000 --- a/include/configs/socfpga_stratix10_socdk.h +++ /dev/null @@ -1,208 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2017-2018 Intel Corporation - * - */ - -#ifndef __CONFIG_SOCFGPA_STRATIX10_H__ -#define __CONFIG_SOCFGPA_STRATIX10_H__ - -#include -#include - -/* - * U-Boot general configurations - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_LOADADDR 0x2000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_REMAKE_ELF -/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ -#define CPU_RELEASE_ADDR 0xFFD12210 -#define CONFIG_SYS_CACHELINE_SIZE 64 -#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ - -/* - * U-Boot console configurations - */ -#define CONFIG_SYS_MAXARGS 64 -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) - -/* - * U-Boot run time memory configurations - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ - + CONFIG_SYS_INIT_RAM_SIZE \ - - S10_HANDOFF_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) -#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) - -/* - * U-Boot environment configurations - */ -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ -#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ - -/* - * QSPI support - */ - #ifdef CONFIG_CADENCE_QSPI -/* Enable it if you want to use dual-stacked mode */ -/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ - -/* Flash device info */ - -/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ -#ifdef CONFIG_ENV_IS_IN_SPI_FLASH -#undef CONFIG_ENV_OFFSET -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET 0x710000 -#define CONFIG_ENV_SIZE (4 * 1024) -#define CONFIG_ENV_SECT_SIZE (4 * 1024) -#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_MTD_DEVICE -#define CONFIG_MTD_PARTITIONS -#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" -#endif /* CONFIG_SPL_BUILD */ - -#ifndef __ASSEMBLY__ -unsigned int cm_get_qspi_controller_clk_hz(void); -#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() -#endif - -#endif /* CONFIG_CADENCE_QSPI */ - -/* - * Boot arguments passed to the boot command. The value of - * CONFIG_BOOTARGS goes into the environment value "bootargs". - * Do note the value will override also the chosen node in FDT blob. - */ -#define CONFIG_BOOTARGS "earlycon" -#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ - "run mmcboot" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "bootfile=Image\0" \ - "fdt_addr=8000000\0" \ - "fdtimage=socfpga_stratix10_socdk.dtb\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ - " root=${mmcroot} rw rootwait;" \ - "booti ${loadaddr} - ${fdt_addr}\0" \ - "mmcload=mmc rescan;" \ - "load mmc 0:1 ${loadaddr} ${bootfile};" \ - "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ - "linux_qspi_enable=if sf probe; then " \ - "echo Enabling QSPI at Linux DTB...;" \ - "fdt addr ${fdt_addr}; fdt resize;" \ - "fdt set /soc/spi@ff8d2000 status okay;" \ - "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ - " ${qspi_clock}; fi; \0" \ - "scriptaddr=0x02100000\0" \ - "scriptfile=u-boot.scr\0" \ - "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ - "then source ${scriptaddr}; fi\0" \ - "socfpga_legacy_reset_compat=1\0" - -/* - * Generic Interrupt Controller Definitions - */ -#define CONFIG_GICV2 - -/* - * External memory configurations - */ -#define PHYS_SDRAM_1 0x0 -#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) -#define CONFIG_SYS_SDRAM_BASE 0 -#define CONFIG_SYS_MEMTEST_START 0 -#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 - -/* - * Serial / UART configurations - */ -#define CONFIG_SYS_NS16550_CLK 100000000 -#define CONFIG_SYS_NS16550_MEM32 - -/* - * Timer & watchdog configurations - */ -#define COUNTER_FREQUENCY 400000000 - -/* - * SDMMC configurations - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 -#endif -/* - * Flash configurations - */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_DW_ALTDESCRIPTOR -#endif /* CONFIG_CMD_NET */ - -/* - * L4 Watchdog - */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_HW_WATCHDOG -#define CONFIG_DESIGNWARE_WATCHDOG -#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS -#ifndef __ASSEMBLY__ -unsigned int cm_get_l4_sys_free_clk_hz(void); -#define CONFIG_DW_WDT_CLOCK_KHZ (cm_get_l4_sys_free_clk_hz() / 1000) -#endif -#endif - -/* - * SPL memory layout - * - * On chip RAM - * 0xFFE0_0000 ...... Start of OCRAM - * SPL code, rwdata - * empty space - * 0xFFEx_xxxx ...... Top of stack (grows down) - * 0xFFEy_yyyy ...... Global Data - * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) - * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) - * 0xFFE3_FFFF ...... End of OCRAM - * - * SDRAM - * 0x0000_0000 ...... Start of SDRAM_1 - * unused / empty space for image loading - * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) - * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) - * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) - * - */ -#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" -#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ - - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ - - CONFIG_SYS_SPL_MALLOC_SIZE) - -/* SPL SDMMC boot support */ -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#endif /* __CONFIG_H */ diff --git a/include/configs/socfpga_vining_fpga.h b/include/configs/socfpga_vining_fpga.h deleted file mode 100644 index debf3ea..0000000 --- a/include/configs/socfpga_vining_fpga.h +++ /dev/null @@ -1,211 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2019 Marek Vasut - */ -#ifndef __CONFIG_SOFTING_VINING_FPGA_H__ -#define __CONFIG_SOFTING_VINING_FPGA_H__ - -#include - -/* Memory configurations */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on VINING_FPGA */ - -/* Booting Linux */ -#define CONFIG_BOOTFILE "fitImage" -#define CONFIG_BOOTCOMMAND "run selboot" -#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MiB */ -#define CONFIG_LOADADDR 0x01000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Ethernet on SoC (EMAC) */ -#if defined(CONFIG_CMD_NET) -#define CONFIG_BOOTP_SEND_HOSTNAME -#endif - -/* Extra Environment */ -#define CONFIG_HOSTNAME "socfpga_vining_fpga" - -/* - * Active LOW GPIO buttons: - * A: GPIO 77 ... the button between USB B and ethernet - * B: GPIO 78 ... the button between USB A ports - * - * The logic: - * if button B is pressed, boot recovery system after 10 seconds - * if force_boottype is set, boot system depending on the value in the - * $force_boottype variable after 1 second - * if button B is not pressed and force_boottype is not set, boot normal - * Linux system after 5 seconds - */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "verify=n\0" \ - "consdev=ttyS0\0" \ - "baudrate=115200\0" \ - "bootscript=boot.scr\0" \ - "ubimtdnr=5\0" \ - "ubimtd=rootfs\0" \ - "ubipart=ubi0:vining-fpga-rootfs\0" \ - "ubisfcs=1\0" /* Default is flash at CS#1 */ \ - "netdev=eth0\0" \ - "hostname=vining_fpga\0" \ - "kernel_addr_r=0x10000000\0" \ - "fdt_addr_r=0x20000000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "dfu_alt_info=qspi0 sf 0:0;qspi1 sf 0:1\0" \ - "mtdparts_0_16m=ff705000.spi.0:" /* 16MiB+128MiB SF config */ \ - "1m(u-boot)," \ - "64k(env1)," \ - "64k(env2)," \ - "256k(softing1)," \ - "256k(softing2)," \ - "-(rcvrfs)\0" /* Recovery */ \ - "mtdparts_0_256m=ff705000.spi.0:" /* 256MiB(+256MiB) config */ \ - "1m(u-boot)," \ - "64k(env1)," \ - "64k(env2)," \ - "256k(softing1)," \ - "256k(softing2)," \ - "14720k(rcvrfs)," /* Recovery */ \ - "64m(rootfs)," /* Root */ \ - "-(userfs)\0" /* User */ \ - "mtdparts_1_128m=ff705000.spi.1:" /* 16MiB+128MiB SF config */ \ - "64m(rootfs)," \ - "-(userfs)\0" \ - "mtdparts_1_256m=ff705000.spi.1:" /* 256MiB+256MiB SF config */ \ - "-(userfs2)\0" \ - "update_filename=u-boot-with-spl-dtb.sfp\0" \ - "update_qspi_offset=0x0\0" \ - "update_qspi=" /* Update the QSPI firmware */ \ - "if sf probe ; then " \ - "if tftp ${update_filename} ; then " \ - "sf update ${loadaddr} ${update_qspi_offset} ${filesize} ; " \ - "fi ; " \ - "fi\0" \ - "sf_identify=" \ - "setenv sf_size_0 ; setenv sf_size_1 ; " \ - "sf probe 0:0 && setenv sf_size_0 ${sf_size} ; " \ - "sf probe 0:1 && setenv sf_size_1 ${sf_size} ; " \ - "if test -z \"${sf_size_1}\" ; then " \ - /* 1x256MiB SF */ \ - "setenv mtdparts_0 ${mtdparts_0_256m} ; " \ - "setenv mtdparts_1 ; " \ - "elif test \"${sf_size_0}\" = \"1000000\" ; then " \ - /* 16MiB+128MiB SF */ \ - "setenv mtdparts_0 ${mtdparts_0_16m} ; " \ - "setenv mtdparts_1 ${mtdparts_1_128m} ; " \ - "else " \ - /* 256MiB+256MiB SF */ \ - "setenv mtdparts_0 ${mtdparts_0_256m} ; " \ - "setenv mtdparts_1 ${mtdparts_1_256m} ; " \ - "fi\0" \ - "fpga_filename=output_file.rbf\0" \ - "load_fpga=" /* Load FPGA bitstream */ \ - "if tftp ${fpga_filename} ; then " \ - "fpga load 0 $loadaddr $filesize ; " \ - "bridge enable ; " \ - "fi\0" \ - "addcons=" \ - "setenv bootargs ${bootargs} " \ - "console=${consdev},${baudrate}\0" \ - "addip=" \ - "setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=" \ - "setenv bootargs ${bootargs} ${miscargs}\0" \ - "addmtd=" \ - "if test -z \"${sf_size_1}\" ; then " \ - "setenv mtdparts \"${mtdparts_0}\" ; " \ - "else " \ - "setenv mtdparts \"${mtdparts_0};${mtdparts_1}\" ; " \ - "fi ; " \ - "setenv bootargs ${bootargs} mtdparts=${mtdparts}\0" \ - "addargs=run addcons addmtd addmisc\0" \ - "ubiload=" \ - "ubi part ${ubimtd} ; ubifsmount ${ubipart} ; " \ - "ubifsload ${kernel_addr_r} /boot/${bootfile}\0" \ - "netload=" \ - "tftp ${kernel_addr_r} ${hostname}/${bootfile}\0" \ - "miscargs=nohlt panic=1\0" \ - "ubiargs=" \ - "setenv bootargs ubi.mtd=${ubimtdnr} " \ - "root=${ubipart} rootfstype=ubifs\0" \ - "nfsargs=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp\0" \ - "ubi_sfsel=" \ - "if test \"${boottype}\" = \"rcvr\" ; then " \ - "setenv ubisfcs 0 ; " \ - "setenv ubimtd rcvrfs ; " \ - "setenv ubimtdnr 5 ; " \ - "setenv mtdparts mtdparts=${mtdparts_0} ; " \ - "setenv mtdids nor0=ff705000.spi.0 ; " \ - "setenv ubipart ubi0:vining-fpga-rootfs ; " \ - "else " \ - "if test \"${sf_size_0}\" = \"1000000\" ; then "\ - /* 16MiB+128MiB SF */ \ - "setenv ubisfcs 1 ; " \ - "setenv ubimtd rootfs ; " \ - "setenv ubimtdnr 6 ; " \ - "setenv mtdparts mtdparts=${mtdparts_1} ; " \ - "setenv mtdids nor0=ff705000.spi.1 ; " \ - "setenv ubipart ubi0:vining-fpga-rootfs ; " \ - "else " \ - /* 256MiB(+256MiB) SF */ \ - "setenv ubisfcs 0 ; " \ - "setenv ubimtd rootfs ; " \ - "setenv ubimtdnr 6 ; " \ - "setenv mtdparts mtdparts=${mtdparts_0} ; " \ - "setenv mtdids nor0=ff705000.spi.0 ; " \ - "setenv ubipart ubi0:vining-fpga-rootfs ; " \ - "fi ; " \ - "fi ; " \ - "sf probe 0:${ubisfcs}\0" \ - "boot_kernel=" \ - "if test -z \"${sf_size_1}\" ; then " /* 1x256MiB SF */ \ - "imxtract ${kernel_addr_r} fdt@1 ${fdt_addr_r} && " \ - "fdt addr ${fdt_addr_r} && " \ - "fdt resize && " \ - "fdt set /soc/spi@ff705000/n25q00@1 status disabled && " \ - "bootm ${kernel_addr_r}:kernel@1 - ${fdt_addr_r} ; " \ - "else " \ - "bootm ${kernel_addr_r} ; " \ - "fi\0" \ - "ubi_ubi=" \ - "run ubi_sfsel ubiload ubiargs addargs boot_kernel\0" \ - "ubi_nfs=" \ - "run ubiload nfsargs addip addargs boot_kernel\0" \ - "net_ubi=" \ - "run netload ubiargs addargs boot_kernel\0" \ - "net_nfs=" \ - "run netload nfsargs addip addargs boot_kernel\0" \ - "selboot=" /* Select from where to boot. */ \ - "run sf_identify ; " \ - "if test \"${bootmode}\" = \"qspi\" ; then " \ - "led all off ; " \ - "if test \"${boottype}\" = \"rcvr\" ; then " \ - "echo \"Booting recovery system\" ; " \ - "led 3 on ; " /* Bottom RED */ \ - "fi ; " \ - "led 1 on ; " /* Top RED */ \ - "run ubi_ubi ; " \ - "else echo \"Unsupported boot mode: \"${bootmode} ; " \ - "fi\0" \ - "socfpga_legacy_reset_compat=1\0" - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_SECT_SIZE (64 * 1024) -#define CONFIG_ENV_OFFSET 0x100000 -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) - -/* Support changing the prompt string */ -#define CONFIG_CMDLINE_PS_SUPPORT - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIG_SOFTING_VINING_FPGA_H__ */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h deleted file mode 100644 index c7c30d3..0000000 --- a/include/configs/socrates.h +++ /dev/null @@ -1,342 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 - * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. - * - * Wolfgang Denk - * Copyright 2004 Freescale Semiconductor. - * (C) Copyright 2002,2003 Motorola,Inc. - * Xianghua Xiao - */ - -/* - * Socrates - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_SOCRATES 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -/* - * sysclk for MPC85xx - * - * Two valid values are: - * 33000000 - * 66000000 - * - * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz - * is likely the desired value here, so that is now the default. - * The board, however, can run at 66MHz. In any event, this value - * must match the settings of some switches. Details can be found - * in the README.mpc85xxads. - */ - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ 66666666 -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00400000 -#define CONFIG_SYS_MEMTEST_END 0x00C00000 - -#define CONFIG_SYS_CCSRBAR 0xE0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD - -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */ - -#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ - -/* Hardcoded values, to use instead of SPD */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935D322 -#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 -#define CONFIG_SYS_DDR_MODE 0x00480432 -#define CONFIG_SYS_DDR_INTERVAL 0x030C0100 -#define CONFIG_SYS_DDR_CONFIG_2 0x04400000 -#define CONFIG_SYS_DDR_CONFIG 0xC3008000 -#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000 -#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */ - -/* - * Flash on the LocalBus - */ -#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ - -#define CONFIG_SYS_FLASH0 0xFE000000 -#define CONFIG_SYS_FLASH1 0xFC000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } - -#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */ -#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */ - -#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */ -#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */ -#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */ -#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */ -#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ -#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */ - -/* FPGA and NAND */ -#define CONFIG_SYS_FPGA_BASE 0xc0000000 -#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ -#define CONFIG_SYS_HMI_BASE 0xc0010000 -#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ -#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */ - -#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* LIME GDC */ -#define CONFIG_SYS_LIME_BASE 0xc8000000 -#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */ -#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */ -#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */ - -#define CONFIG_VIDEO_MB862xx -#define CONFIG_VIDEO_MB862xx_ACCEL -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define VIDEO_FB_16BPP_PIXEL_SWAP -#define VIDEO_FB_16BPP_WORD_SWAP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */ - -/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */ -#define CONFIG_SYS_MB862xx_CCF 0x10000 -/* SDRAM parameter */ -#define CONFIG_SYS_MB862xx_MMR 0x4157BA63 - -/* Serial Port */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 102124 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 102124 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */ - -/* I2C W83782G HW-Monitoring IC */ -#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */ - -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 - -/* - * General PCI - * Memory space is mapped 1-1. - */ -#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - -/* PCI is clocked by the external source at 33 MHz */ -#define CONFIG_PCI_CLK_FREQ 33000000 -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#if defined(CONFIG_PCI) -#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "TSEC1" -#undef CONFIG_MPC85XX_FEC - -#define TSEC1_PHY_ADDR 0 -#define TSEC3_PHY_ADDR 1 - -#define TSEC1_PHYIDX 0 -#define TSEC3_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC3_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0,1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 - -/* - * Environment - */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE 0x4000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -#define CONFIG_TIMESTAMP /* Print image info with ts */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ -#endif - -#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consdev=ttyS0\0" \ - "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \ - "bootfile=/home/tftp/syscon3/uImage\0" \ - "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \ - "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \ - "uboot_addr=FFFA0000\0" \ - "kernel_addr=FE000000\0" \ - "fdt_addr=FE1E0000\0" \ - "ramdisk_addr=FE200000\0" \ - "fdt_addr_r=B00000\0" \ - "kernel_addr_r=200000\0" \ - "ramdisk_addr_r=400000\0" \ - "rootpath=/opt/eldk/ppc_85xxDP\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath\0" \ - "addcons=setenv bootargs $bootargs " \ - "console=$consdev,$baudrate\0" \ - "addip=setenv bootargs $bootargs " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ - ":$hostname:$netdev:off panic=1\0" \ - "boot_nor=run ramargs addcons;" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "tftp ${fdt_addr_r} ${fdt_file}; " \ - "run nfsargs addip addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ - "update_uboot=tftp 100000 ${uboot_file};" \ - "protect off fffa0000 ffffffff;" \ - "era fffa0000 ffffffff;" \ - "cp.b 100000 fffa0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_kernel=tftp 100000 ${bootfile};" \ - "era fe000000 fe1dffff;" \ - "cp.b 100000 fe000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_fdt=tftp 100000 ${fdt_file};" \ - "era fe1e0000 fe1fffff;" \ - "cp.b 100000 fe1e0000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "update_initrd=tftp 100000 ${initrd_file};" \ - "era fe200000 fe9fffff;" \ - "cp.b 100000 fe200000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "clean_data=era fea00000 fff5ffff\0" \ - "usbargs=setenv bootargs root=/dev/sda1 rw\0" \ - "load_usb=usb start;" \ - "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \ - "boot_usb=run load_usb usbargs addcons;" \ - "bootm ${kernel_addr_r} - ${fdt_addr};" \ - "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ - "" -#define CONFIG_BOOTCOMMAND "run boot_nor" - -/* pass open firmware flat tree */ - -/* USB support */ -#define CONFIG_USB_OHCI_NEW 1 -#define CONFIG_PCI_OHCI 1 -#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ -#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2) -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" -#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h deleted file mode 100644 index cfcc9c8..0000000 --- a/include/configs/som-db5800-som-6867.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Google, Inc - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x006ef000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h deleted file mode 100644 index d21ff97..0000000 --- a/include/configs/spear-common.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, - */ - -#ifndef _SPEAR_COMMON_H -#define _SPEAR_COMMON_H -/* - * Common configurations used for both spear3xx as well as spear6xx - */ - -/* U-Boot Load Address */ - -/* Ethernet driver configuration */ -#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ - -/* USBD driver configuration */ -#if defined(CONFIG_SPEAR_USBTTY) -#define CONFIG_DW_UDC -#define CONFIG_USB_DEVICE -#define CONFIG_USBD_HS -#define CONFIG_USB_TTY - -#define CONFIG_USBD_PRODUCT_NAME "SPEAr SoC" -#define CONFIG_USBD_MANUFACTURER "ST Microelectronics" - -#endif - -#define CONFIG_EXTRA_ENV_USBTTY "usbtty=cdc_acm\0" - -/* I2C driver configuration */ -#define CONFIG_SYS_I2C -#if defined(CONFIG_SPEAR600) -#define CONFIG_SYS_I2C_BASE 0xD0200000 -#elif defined(CONFIG_SPEAR300) -#define CONFIG_SYS_I2C_BASE 0xD0180000 -#elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_I2C_BASE 0xD0180000 -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_I2C_BASE 0xD0180000 -#endif -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x02 - -#define CONFIG_I2C_CHIPADDRESS 0x50 - -/* Timer, HZ specific defines */ - -/* Flash configuration */ -#if defined(CONFIG_FLASH_PNOR) -#define CONFIG_SPEAR_EMI -#else -#define CONFIG_ST_SMI -#endif - -#if defined(CONFIG_ST_SMI) - -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BASE 0xF8000000 -#define CONFIG_SYS_CS1_FLASH_BASE 0xF9000000 -#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_ADDR_BASE {CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_CS1_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_SECT 128 - -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) - -#endif - -/* - * Serial Configuration (PL011) - * CONFIG_PL01x_PORTS is defined in specific files - */ -#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ - 57600, 115200 } - -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* NAND FLASH Configuration */ -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_NAND_FSMC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* - * Default Environment Varible definitions - */ -#define CONFIG_ENV_OVERWRITE - -/* - * U-Boot Environment placing definitions. - */ -#if defined(CONFIG_ENV_IS_IN_FLASH) -#ifdef CONFIG_ST_SMI -/* - * Environment is in serial NOR flash - */ -#define CONFIG_SYS_MONITOR_LEN 0x00040000 -#define CONFIG_ENV_SECT_SIZE 0x00010000 -#define CONFIG_FSMTDBLK "/dev/mtdblock3 " - -#define CONFIG_BOOTCOMMAND "bootm 0xf8050000" - -#elif defined(CONFIG_SPEAR_EMI) -/* - * Environment is in parallel NOR flash - */ -#define CONFIG_SYS_MONITOR_LEN 0x00060000 -#define CONFIG_ENV_SECT_SIZE 0x00020000 -#define CONFIG_FSMTDBLK "/dev/mtdblock3 " - -#define CONFIG_BOOTCOMMAND "cp.b 0x50080000 0x1600000 " \ - "0x4C0000; bootm 0x1600000" -#endif - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#elif defined(CONFIG_ENV_IS_IN_NAND) -/* - * Environment is in NAND - */ - -#define CONFIG_ENV_OFFSET 0x60000 -#define CONFIG_ENV_RANGE 0x10000 -#define CONFIG_FSMTDBLK "/dev/mtdblock7 " - -#define CONFIG_BOOTCOMMAND "nand read.jffs2 0x1600000 " \ - "0x80000 0x4C0000; " \ - "bootm 0x1600000" -#endif - -#define CONFIG_NFSBOOTCOMMAND \ - "bootp; " \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):" \ - "$(netmask):$(hostname):$(netdev):off " \ - "console=ttyAMA0,115200 $(othbootargs);" \ - "bootm; " - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=ttyAMA0,115200 $(othbootargs);" \ - CONFIG_BOOTCOMMAND - -#define CONFIG_ENV_SIZE 0x02000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -/* Miscellaneous configurable options */ -#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x04000000 -#define CONFIG_SYS_MALLOC_LEN (1024*1024) -#define CONFIG_SYS_LOAD_ADDR 0x00800000 - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_1_MAXSIZE 0x40000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#endif diff --git a/include/configs/spear3xx_evb.h b/include/configs/spear3xx_evb.h deleted file mode 100644 index 2f642b1..0000000 --- a/include/configs/spear3xx_evb.h +++ /dev/null @@ -1,141 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#if defined(CONFIG_SPEAR300) -#define CONFIG_SPEAR3XX -#elif defined(CONFIG_SPEAR310) -#define CONFIG_SPEAR3XX -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SPEAR3XX -#endif - -#if defined(CONFIG_USBTTY) -#define CONFIG_SPEAR_USBTTY -#endif - -#include - -/* Ethernet driver configuration */ -#define CONFIG_DW_ALTDESCRIPTOR - -#if defined(CONFIG_SPEAR310) -#define CONFIG_MACB -#define CONFIG_MACB0_PHY 0x01 -#define CONFIG_MACB1_PHY 0x03 -#define CONFIG_MACB2_PHY 0x05 -#define CONFIG_MACB3_PHY 0x07 - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_MACB -#define CONFIG_MACB0_PHY 0x01 - -#endif - -/* Serial Configuration (PL011) */ -#define CONFIG_SYS_SERIAL0 0xD0000000 - -#if defined(CONFIG_SPEAR300) -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0} - -#elif defined(CONFIG_SPEAR310) - -#if (CONFIG_CONS_INDEX) -#undef CONFIG_PL011_CLOCK -#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) -#endif - -#define CONFIG_SYS_SERIAL1 0xB2000000 -#define CONFIG_SYS_SERIAL2 0xB2080000 -#define CONFIG_SYS_SERIAL3 0xB2100000 -#define CONFIG_SYS_SERIAL4 0xB2180000 -#define CONFIG_SYS_SERIAL5 0xB2200000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2, \ - (void *)CONFIG_SYS_SERIAL3, \ - (void *)CONFIG_SYS_SERIAL4, \ - (void *)CONFIG_SYS_SERIAL5 } -#elif defined(CONFIG_SPEAR320) - -#if (CONFIG_CONS_INDEX) -#undef CONFIG_PL011_CLOCK -#define CONFIG_PL011_CLOCK (83 * 1000 * 1000) -#endif - -#define CONFIG_SYS_SERIAL1 0xA3000000 -#define CONFIG_SYS_SERIAL2 0xA4000000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1, \ - (void *)CONFIG_SYS_SERIAL2 } -#endif - -#if defined(CONFIG_SPEAR_EMI) -#if defined(CONFIG_SPEAR310) -#define CONFIG_SYS_FLASH_BASE 0x50000000 -#define CONFIG_SYS_CS1_FLASH_BASE 0x60000000 -#define CONFIG_SYS_CS2_FLASH_BASE 0x70000000 -#define CONFIG_SYS_CS3_FLASH_BASE 0x80000000 -#define CONFIG_SYS_CS4_FLASH_BASE 0x90000000 -#define CONFIG_SYS_CS5_FLASH_BASE 0xA0000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_CS1_FLASH_BASE, \ - CONFIG_SYS_CS2_FLASH_BASE, \ - CONFIG_SYS_CS3_FLASH_BASE, \ - CONFIG_SYS_CS4_FLASH_BASE, \ - CONFIG_SYS_CS5_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 6 - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_FLASH_BASE 0x44000000 -#define CONFIG_SYS_CS1_FLASH_BASE 0x45000000 -#define CONFIG_SYS_CS2_FLASH_BASE 0x46000000 -#define CONFIG_SYS_CS3_FLASH_BASE 0x47000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, \ - CONFIG_SYS_CS1_FLASH_BASE, \ - CONFIG_SYS_CS2_FLASH_BASE, \ - CONFIG_SYS_CS3_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 4 - -#endif - -#define CONFIG_SYS_MAX_FLASH_SECT (127 + 8) -#define CONFIG_SYS_FLASH_QUIET_TEST - -#endif - -/* NAND flash configuration */ -#define CONFIG_SYS_FSMC_NAND_SP -#define CONFIG_SYS_FSMC_NAND_8BIT - -#if defined(CONFIG_SPEAR300) -#define CONFIG_SYS_NAND_BASE 0x80000000 - -#elif defined(CONFIG_SPEAR310) -#define CONFIG_SYS_NAND_BASE 0x40000000 - -#elif defined(CONFIG_SPEAR320) -#define CONFIG_SYS_NAND_BASE 0x50000000 - -#endif - -/* Environment Settings */ -#if defined(CONFIG_SPEAR300) -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY - -#elif defined(CONFIG_SPEAR310) || defined(CONFIG_SPEAR320) -#define CONFIG_EXTRA_ENV_UNLOCK "unlock=yes\0" -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY \ - CONFIG_EXTRA_ENV_UNLOCK -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/spear6xx_evb.h b/include/configs/spear6xx_evb.h deleted file mode 100644 index cfadfc8..0000000 --- a/include/configs/spear6xx_evb.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 - * Vipin Kumar, STMicroelectronics, - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#if defined(CONFIG_USBTTY) -#define CONFIG_SPEAR_USBTTY -#endif - -#include - -/* Serial Configuration (PL011) */ -#define CONFIG_SYS_SERIAL0 0xD0000000 -#define CONFIG_SYS_SERIAL1 0xD0080000 -#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1 } - -/* NAND flash configuration */ -#define CONFIG_SYS_FSMC_NAND_SP -#define CONFIG_SYS_FSMC_NAND_8BIT -#define CONFIG_SYS_NAND_BASE 0xD2000000 - -/* Ethernet PHY configuration */ -#define CONFIG_PHY_NATSEMI - -/* Environment Settings */ -#define CONFIG_EXTRA_ENV_SETTINGS CONFIG_EXTRA_ENV_USBTTY - -#endif /* __CONFIG_H */ diff --git a/include/configs/spring.h b/include/configs/spring.h deleted file mode 100644 index 272622a..0000000 --- a/include/configs/spring.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Google, Inc - */ - -#ifndef __CONFIG_SPRING_H -#define __CONFIG_SPRING_H - -#include -#include -#include - -#define CONFIG_BOARD_COMMON - -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" - -#endif /* __CONFIG_SPRING_H */ diff --git a/include/configs/stih410-b2260.h b/include/configs/stih410-b2260.h deleted file mode 100644 index b67efbb..0000000 --- a/include/configs/stih410-b2260.h +++ /dev/null @@ -1,75 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* ram memory-related information */ -#define PHYS_SDRAM_1 0x40000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define PHYS_SDRAM_1_SIZE 0x3E000000 -#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 /* default load addr */ - -#define CONFIG_SYS_HZ_CLOCK 1000000000 /* 1 GHz */ - -/* Environment */ - -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR -#define CONFIG_SYS_BOOTM_LEN SZ_16M - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(DHCP, dhcp, na) -#include -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x40000000\0" \ - "fdtfile=stih410-b2260.dtb\0" \ - "fdt_addr_r=0x47000000\0" \ - "scriptaddr=0x50000000\0" \ - "pxefile_addr_r=0x50100000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "ramdisk_addr_r=0x48000000\0" \ - BOOTENV - - -#define CONFIG_ENV_SIZE 0x4000 - -/* Extra Commands */ -#define CONFIG_CMD_ASKENV - -#define CONFIG_SETUP_MEMORY_TAGS - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN 0x1800000 -#define CONFIG_SYS_GBL_DATA_SIZE 1024 /* Global data structures */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN - \ - CONFIG_SYS_GBL_DATA_SIZE) - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* USB Configs */ -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_USB_ETHER_MCS7830 -#define CONFIG_USB_ETHER_SMSC95XX - -/* NET Configs */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h deleted file mode 100644 index 31c17d0..0000000 --- a/include/configs/stm32f429-discovery.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Kamil Lulko, - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_FLASH_BASE 0x08000000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0x90400000 -#define CONFIG_LOADADDR 0x90400000 - -#define CONFIG_SYS_MAX_FLASH_SECT 12 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 - -#define CONFIG_ENV_OFFSET (256 << 10) -#define CONFIG_ENV_SECT_SIZE (128 << 10) -#define CONFIG_ENV_SIZE (8 << 10) - -#define CONFIG_RED_LED 110 -#define CONFIG_GREEN_LED 109 - -#define CONFIG_STM32_FLASH - -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_SYS_MALLOC_LEN (2 << 20) - -#define CONFIG_BOOTCOMMAND \ - "run bootcmd_romfs" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_romfs=uclinux.physaddr=0x08180000 root=/dev/mtdblock0\0" \ - "bootcmd_romfs=setenv bootargs ${bootargs} ${bootargs_romfs};" \ - "bootm 0x08044000 - 0x08042000\0" - -/* - * Command line configuration. - */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h deleted file mode 100644 index a5390f8..0000000 --- a/include/configs/stm32f429-evaluation.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_FLASH_BASE 0x08000000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 -#define CONFIG_LOADADDR 0x00400000 - -#define CONFIG_SYS_MAX_FLASH_SECT 12 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 - -#define CONFIG_ENV_OFFSET (256 << 10) -#define CONFIG_ENV_SECT_SIZE (128 << 10) -#define CONFIG_ENV_SIZE (8 << 10) - -#define CONFIG_STM32_FLASH - -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00008000\0" \ - "fdtfile=stm32429i-eval.dtb\0" \ - "fdt_addr_r=0x00700000\0" \ - "scriptaddr=0x00800000\0" \ - "pxefile_addr_r=0x00800000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "ramdisk_addr_r=0x00900000\0" \ - BOOTENV - -/* - * Command line configuration. - */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h deleted file mode 100644 index 1c7efd1..0000000 --- a/include/configs/stm32f469-discovery.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) STMicroelectronics SA 2017 - * Author(s): Patrice CHOTARD, for STMicroelectronics. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_FLASH_BASE 0x08000000 - -#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 - -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0x00400000 -#define CONFIG_LOADADDR 0x00400000 - -#define CONFIG_SYS_MAX_FLASH_SECT 12 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 - -#define CONFIG_ENV_OFFSET (256 << 10) -#define CONFIG_ENV_SECT_SIZE (128 << 10) -#define CONFIG_ENV_SIZE (8 << 10) - -#define CONFIG_STM32_FLASH - -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00008000\0" \ - "fdtfile=stm32f469-disco.dtb\0" \ - "fdt_addr_r=0x00700000\0" \ - "scriptaddr=0x00800000\0" \ - "pxefile_addr_r=0x00800000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "ramdisk_addr_r=0x00900000\0" \ - BOOTENV - -/* - * Command line configuration. - */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h deleted file mode 100644 index cc26f83..0000000 --- a/include/configs/stm32f746-disco.h +++ /dev/null @@ -1,92 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, for STMicroelectronics. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x20050000 - -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SYS_LOAD_ADDR 0x08008000 -#else -#define CONFIG_SYS_LOAD_ADDR 0xC0400000 -#define CONFIG_LOADADDR 0xC0400000 -#endif - -/* - * Configuration of the external SDRAM memory - */ - -#define CONFIG_SYS_MAX_FLASH_SECT 8 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_ENV_SIZE (8 << 10) - -#define CONFIG_STM32_FLASH - -#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL (8) -#define CONFIG_DW_ALTDESCRIPTOR -#define CONFIG_PHY_SMSC - -#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_CBSIZE 1024 - -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0xC0008000\0" \ - "fdtfile=stm32f746-disco.dtb\0" \ - "fdt_addr_r=0xC0500000\0" \ - "scriptaddr=0xC0008000\0" \ - "pxefile_addr_r=0xC0008000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "ramdisk_addr_r=0xC0600000\0" \ - BOOTENV - -/* - * Command line configuration. - */ -#define CONFIG_BOARD_LATE_INIT -#define CONFIG_DISPLAY_BOARDINFO - -/* For SPL */ -#ifdef CONFIG_SUPPORT_SPL -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) -#define CONFIG_SYS_SPL_LEN 0x00008000 -#define CONFIG_SYS_UBOOT_START 0x080083FD -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_SPL_LEN) - -/* DT blob (fdt) address */ -#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \ - 0x1C0000) -#endif -/* For SPL ends */ - -/* For splashcreen */ -#ifdef CONFIG_DM_VIDEO -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_BMP_16BPP -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/stm32h743-disco.h b/include/configs/stm32h743-disco.h deleted file mode 100644 index f110e29..0000000 --- a/include/configs/stm32h743-disco.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 - -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0xD0400000 -#define CONFIG_LOADADDR 0xD0400000 - -#define CONFIG_ENV_SIZE (8 << 10) - -#define CONFIG_SYS_HZ_CLOCK 1000000 - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0xD0008000\0" \ - "fdtfile=stm32h743i-disco.dtb\0" \ - "fdt_addr_r=0xD0700000\0" \ - "scriptaddr=0xD0800000\0" \ - "pxefile_addr_r=0xD0800000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "ramdisk_addr_r=0xD0900000\0" \ - BOOTENV - -/* - * Command line configuration. - */ -#define CONFIG_BOARD_LATE_INIT - -#endif /* __CONFIG_H */ diff --git a/include/configs/stm32h743-eval.h b/include/configs/stm32h743-eval.h deleted file mode 100644 index e3bf5b2..0000000 --- a/include/configs/stm32h743-eval.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017, STMicroelectronics - All Rights Reserved - * Author(s): Patrice Chotard, for STMicroelectronics. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_FLASH_BASE 0x08000000 -#define CONFIG_SYS_INIT_SP_ADDR 0x24040000 - -/* - * Configuration of the external SDRAM memory - */ -#define CONFIG_SYS_LOAD_ADDR 0xD0400000 -#define CONFIG_LOADADDR 0xD0400000 - -#define CONFIG_ENV_SIZE (8 << 10) - -#define CONFIG_SYS_HZ_CLOCK 1000000 - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) - -#include -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0xD0008000\0" \ - "fdtfile=stm32h743i-eval.dtb\0" \ - "fdt_addr_r=0xD0700000\0" \ - "scriptaddr=0xD0800000\0" \ - "pxefile_addr_r=0xD0800000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "ramdisk_addr_r=0xD0900000\0" \ - BOOTENV - -/* - * Command line configuration. - */ -#define CONFIG_BOARD_LATE_INIT - -#endif /* __CONFIG_H */ diff --git a/include/configs/stm32mp1.h b/include/configs/stm32mp1.h deleted file mode 100644 index 988992b..0000000 --- a/include/configs/stm32mp1.h +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ -/* - * Copyright (C) 2018, STMicroelectronics - All Rights Reserved - * - * Configuration settings for the STM32MP15x CPU - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -#include -#include - -#ifndef CONFIG_STM32MP1_TRUSTED -/* PSCI support */ -#define CONFIG_ARMV7_PSCI_1_0 -#define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE -#define CONFIG_ARMV7_SECURE_MAX_SIZE STM32_SYSRAM_SIZE -#endif - -/* - * Configuration of the external SRAM memory used by U-Boot - */ -#define CONFIG_SYS_SDRAM_BASE STM32_DDR_BASE -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -#ifdef CONFIG_STM32MP1_OPTEE -#define CONFIG_SYS_MEM_TOP_HIDE SZ_32M -#endif /* CONFIG_STM32MP1_OPTEE */ - -/* - * Console I/O buffer size - */ -#define CONFIG_SYS_CBSIZE SZ_1K - -/* - * Needed by "loadb" - */ -#define CONFIG_SYS_LOAD_ADDR STM32_DDR_BASE - -/* ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN SZ_32M - -/* SPL support */ -#ifdef CONFIG_SPL -/* SPL use DDR */ -#define CONFIG_SPL_BSS_START_ADDR 0xC0200000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000 -#define CONFIG_SYS_SPL_MALLOC_START 0xC0300000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 - -/* limit SYSRAM usage to first 128 KB */ -#define CONFIG_SPL_MAX_SIZE 0x00020000 -#define CONFIG_SPL_STACK (STM32_SYSRAM_BASE + \ - STM32_SYSRAM_SIZE) -#endif /* #ifdef CONFIG_SPL */ - -#define CONFIG_SYS_MEMTEST_START STM32_DDR_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_64M) -#define CONFIG_SYS_MEMTEST_SCRATCH (CONFIG_SYS_MEMTEST_END + 4) - -/*MMC SD*/ -#define CONFIG_SYS_MMC_MAX_DEVICE 3 - -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Ethernet need */ -#ifdef CONFIG_DWC_ETH_QOS -#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_BOOTP_SERVERIP -#define CONFIG_SYS_AUTOLOAD "no" -#endif - -/* Dynamic MTD partition support */ -#if defined(CONFIG_STM32_QSPI) || defined(CONFIG_NAND_STM32_FMC2) -#define CONFIG_SYS_MTDPARTS_RUNTIME -#endif - -#ifdef CONFIG_DM_VIDEO -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_BMP_16BPP -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP -#endif - -/*****************************************************************************/ -#ifdef CONFIG_DISTRO_DEFAULTS -/*****************************************************************************/ - -#if !defined(CONFIG_SPL_BUILD) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(UBIFS, ubifs, 0) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 2) \ - func(PXE, pxe, na) - -/* - * bootcmd for stm32mp1: - * for serial/usb: execute the stm32prog command - * for mmc boot (eMMC, SD card), boot only on the same device - * for nand boot, boot with on ubifs partition on nand - * for nor boot, use the default order - */ -#define STM32MP_BOOTCMD "bootcmd_stm32mp=" \ - "echo \"Boot over ${boot_device}${boot_instance}!\";" \ - "if test ${boot_device} = serial || test ${boot_device} = usb;" \ - "then stm32prog ${boot_device} ${boot_instance}; " \ - "else " \ - "run env_check;" \ - "if test ${boot_device} = mmc;" \ - "then env set boot_targets \"mmc${boot_instance}\"; fi;" \ - "if test ${boot_device} = nand;" \ - "then env set boot_targets ubifs0; fi;" \ - "run distro_bootcmd;" \ - "fi;\0" - -#include - -#ifdef CONFIG_STM32MP1_OPTEE -/* with OPTEE: define specific MTD partitions = teeh, teed, teex */ -#define STM32MP_MTDPARTS \ - "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),256k(teeh),256k(teed),256k(teex),-(nor_user)\0" \ - "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),512k(teeh),512k(teed),512k(teex),-(UBI)\0" - -#else /* CONFIG_STM32MP1_OPTEE */ -#define STM32MP_MTDPARTS \ - "mtdparts_nor0=256k(fsbl1),256k(fsbl2),2m(ssbl),256k(u-boot-env),-(nor_user)\0" \ - "mtdparts_nand0=2m(fsbl),2m(ssbl1),2m(ssbl2),-(UBI)\0" - -#endif /* CONFIG_STM32MP1_OPTEE */ - -#ifndef CONFIG_SYS_MTDPARTS_RUNTIME -#undef STM32MP_MTDPARTS -#define STM32MP_MTDPARTS -#endif - -/* - * memory layout for 32M uncompressed/compressed kernel, - * 1M fdt, 1M script, 1M pxe and 1M for splashimage - * and the ramdisk at the end. - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootdelay=1\0" \ - "kernel_addr_r=0xc2000000\0" \ - "fdt_addr_r=0xc4000000\0" \ - "scriptaddr=0xc4100000\0" \ - "pxefile_addr_r=0xc4200000\0" \ - "splashimage=0xc4300000\0" \ - "ramdisk_addr_r=0xc4400000\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "altbootcmd=run bootcmd\0" \ - "env_default=1\0" \ - "env_check=if test $env_default -eq 1;"\ - " then env set env_default 0;env save;fi\0" \ - STM32MP_BOOTCMD \ - STM32MP_MTDPARTS \ - BOOTENV \ - "boot_net_usb_start=true\0" - -#endif /* ifndef CONFIG_SPL_BUILD */ -#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/ - -#endif /* __CONFIG_H */ diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h deleted file mode 100644 index 3596658..0000000 --- a/include/configs/stmark2.h +++ /dev/null @@ -1,169 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Sysam stmark2 board configuration - * - * (C) Copyright 2017 Angelo Dureghello - */ - -#ifndef __STMARK2_CONFIG_H -#define __STMARK2_CONFIG_H - -#define CONFIG_HOSTNAME "stmark2" - -#define CONFIG_MCFUART -#define CONFIG_SYS_UART_PORT 0 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } - -#define LDS_BOARD_TEXT \ - board/sysam/stmark2/sbf_dram_init.o (.text*) - -#define CONFIG_TIMESTAMP - -#define CONFIG_BOOTARGS \ - "console=ttyS0,115200 root=/dev/ram0 rw " \ - "rootfstype=ramfs " \ - "rdinit=/bin/init " \ - "devtmpfs.mount=1" - -#define CONFIG_BOOTCOMMAND \ - "sf probe 0:1 50000000; " \ - "sf read ${loadaddr} 0x100000 ${kern_size}; " \ - "bootm ${loadaddr}" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kern_size=0x700000\0" \ - "loadaddr=0x40001000\0" \ - "-(rootfs)\0" \ - "update_uboot=loady ${loadaddr}; " \ - "sf probe 0:1 50000000; " \ - "sf erase 0 0x80000; " \ - "sf write ${loadaddr} 0 ${filesize}\0" \ - "update_kernel=loady ${loadaddr}; " \ - "setenv kern_size ${filesize}; saveenv; " \ - "sf probe 0:1 50000000; " \ - "sf erase 0x100000 0x700000; " \ - "sf write ${loadaddr} 0x100000 ${filesize}\0" \ - "update_rootfs=loady ${loadaddr}; " \ - "sf probe 0:1 50000000; " \ - "sf erase 0x00800000 0x100000; " \ - "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ - "" - -/* Realtime clock */ -#undef CONFIG_MCFRTC -#define CONFIG_RTC_MCFRRTC -#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 - -/* spi not partitions */ -#define CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" - -/* Timer */ -#define CONFIG_MCFTMR -#undef CONFIG_MCFPIT - -/* DSPI and Serial Flash */ -#define CONFIG_CF_DSPI -#define CONFIG_SERIAL_FLASH - -#define CONFIG_SYS_SBFHDR_SIZE 0x7 - -/* Input, PCI, Flexbus, and VCO */ -#define CONFIG_EXTRA_CLOCK - -#define CONFIG_PRAM 2048 /* 2048 KB */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) -#define CONFIG_SYS_MBAR 0xFC000000 - -/* - * Definitions for initial stack pointer and data area (in internal SRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 -/* End of used area in internal SRAM */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 -#define CONFIG_SYS_INIT_RAM_CTRL 0x221 -#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - 32) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) - -/* - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ - -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) -#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) -#define CONFIG_SYS_DRAM_TEST - -#if defined(CONFIG_CF_SBF) -#define CONFIG_SERIAL_BOOT -#endif - -#if defined(CONFIG_SERIAL_BOOT) -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) -#else -#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) -#endif - -#define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) -/* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -/* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization ?? - */ -/* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ - (CONFIG_SYS_SDRAM_SIZE << 20)) - -/* Configuration for environment - * Environment is embedded in u-boot in the second sector of the flash - */ - -#if defined(CONFIG_CF_SBF) -#define CONFIG_ENV_IS_IN_SPI_FLASH 1 -#define CONFIG_ENV_OFFSET 0x40000 -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x10000 -#endif - -#undef CONFIG_ENV_OVERWRITE - -/* Cache Configuration */ -#define CONFIG_SYS_CACHELINE_SIZE 16 -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 8) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 4) -#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) -#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) -#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ - CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ - CF_ACR_EN | CF_ACR_SM_ALL) -#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ - CF_CACR_ICINVA | CF_CACR_EUSP) -#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ - CF_CACR_DEC | CF_CACR_DDCM_P | \ - CF_CACR_DCINVA) & ~CF_CACR_ICINVA) - -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - 12) - -#endif /* __STMARK2_CONFIG_H */ diff --git a/include/configs/stout.h b/include/configs/stout.h deleted file mode 100644 index 6734595..0000000 --- a/include/configs/stout.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * include/configs/stout.h - * This file is Stout board configuration. - * - * Copyright (C) 2015 Renesas Electronics Europe GmbH - * Copyright (C) 2015 Renesas Electronics Corporation - * Copyright (C) 2015 Cogent Embedded, Inc. - */ - -#ifndef __STOUT_H -#define __STOUT_H - -#include "rcar-gen2-common.h" - -#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000 -#define STACK_AREA_SIZE 0x00100000 -#define LOW_LEVEL_MERAM_STACK \ - (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) - -/* MEMORY */ -#define RCAR_GEN2_SDRAM_BASE 0x40000000 -#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) -#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) - -/* SCIF */ -#define CONFIG_SCIF_A - -/* SPI */ -#define CONFIG_SPI_FLASH_QUAD - -/* SH Ether */ -#define CONFIG_SH_ETHER_USE_PORT 0 -#define CONFIG_SH_ETHER_PHY_ADDR 0x1 -#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII -#define CONFIG_SH_ETHER_CACHE_WRITEBACK -#define CONFIG_SH_ETHER_CACHE_INVALIDATE -#define CONFIG_SH_ETHER_ALIGNE_SIZE 64 -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Board Clock */ -#define RMOBILE_XTAL_CLK 20000000u -#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootm_size=0x10000000\0" - -/* SPL support */ -#define CONFIG_SPL_STACK 0xe6340000 -#define CONFIG_SPL_MAX_SIZE 0x4000 -#ifdef CONFIG_SPL_BUILD -#define CONFIG_CONS_SCIFA0 -#define CONFIG_SH_SCIF_CLK_FREQ 52000000 -#endif - -#endif /* __STOUT_H */ diff --git a/include/configs/strider.h b/include/configs/strider.h deleted file mode 100644 index e3d64e5..0000000 --- a/include/configs/strider.h +++ /dev/null @@ -1,471 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc - * - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 family */ - -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR - -/* - * SERDES - */ -#define CONFIG_FSL_SERDES -#define CONFIG_FSL_SERDES1 0xe3000 - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_LOZ \ - | DDRCDR_NZ_LOZ \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x7b880001 */ -/* - * Manually set up DDR parameters - * consist of one chip NT5TU64M16HG from NANYA - */ - -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ - -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ONLY_CURRENT \ - | CSCONFIG_BANK_BIT_3 \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ -#define CONFIG_SYS_DDR_TIMING_3 0 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (0 << TIMING_CFG0_RRT_SHIFT) \ - | (0 << TIMING_CFG0_WWT_SHIFT) \ - | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00260802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (7 << TIMING_CFG1_CASLAT_SHIFT) \ - | (9 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26279222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (4 << TIMING_CFG2_CPO_SHIFT) \ - | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x021848c5 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x08240100 */ -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_16) - /* 0x43100000 */ - -#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0242 << SDRAM_MODE_SD_SHIFT)) - /* ODT 150ohm CL=4, AL=0 on SDRAM */ -#define CONFIG_SYS_DDR_MODE2 0x00000000 - -/* - * Memory test - */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x07f00000 - -/* - * The reserved memory - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ - -/* - * Initial RAM Base Address Setup - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CONFIG_FLASH_CFI_LEGACY -#define CONFIG_SYS_FLASH_LEGACY_512Kx16 - -#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 135 - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_FPGA_DONE(k) 0x0010 - -#define CONFIG_SYS_FPGA_COUNT 1 - -#define CONFIG_SYS_MCLINK_MAX 3 - -#define CONFIG_SYS_FPGA_PTR \ - { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } - -#define CONFIG_SYS_FPGA_NO_RFL_HI - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* Pass open firmware flat tree */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 - -#define CONFIG_PCA953X /* NXP PCA9554 */ -#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ - {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } - -#define CONFIG_PCA9698 /* NXP PCA9698 */ - -#define CONFIG_SYS_I2C_IHS -#define CONFIG_SYS_I2C_IHS_CH0 -#define CONFIG_SYS_I2C_IHS_SPEED_0 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F -#define CONFIG_SYS_I2C_IHS_CH1 -#define CONFIG_SYS_I2C_IHS_SPEED_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2 -#define CONFIG_SYS_I2C_IHS_SPEED_2 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F -#define CONFIG_SYS_I2C_IHS_CH3 -#define CONFIG_SYS_I2C_IHS_SPEED_3 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F - -#ifdef CONFIG_STRIDER_CON_DP -#define CONFIG_SYS_I2C_IHS_DUAL -#define CONFIG_SYS_I2C_IHS_CH0_1 -#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH1_1 -#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH2_1 -#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F -#define CONFIG_SYS_I2C_IHS_CH3_1 -#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 -#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F -#endif - -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SOFT_I2C_READ_REPEATED_START -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F -#define I2C_SOFT_DECLARATIONS2 -#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F -#define I2C_SOFT_DECLARATIONS3 -#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F -#define I2C_SOFT_DECLARATIONS4 -#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F -#if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) -#define I2C_SOFT_DECLARATIONS5 -#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F -#define I2C_SOFT_DECLARATIONS6 -#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F -#define I2C_SOFT_DECLARATIONS7 -#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F -#define I2C_SOFT_DECLARATIONS8 -#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F -#endif -#ifdef CONFIG_STRIDER_CON_DP -#define I2C_SOFT_DECLARATIONS9 -#define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F -#define I2C_SOFT_DECLARATIONS10 -#define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F -#define I2C_SOFT_DECLARATIONS11 -#define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F -#define I2C_SOFT_DECLARATIONS12 -#define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F -#endif - -#ifdef CONFIG_STRIDER_CON -#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} -#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} -#define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#elif defined(CONFIG_STRIDER_CON_DP) -#define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} -#define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} -#define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} -#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} -#define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ - {12, 0x4c} } -#elif defined(CONFIG_STRIDER_CPU_DP) -#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} -#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ - {8, 0x4c} } -#else -#define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} -#define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} -#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} -#define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ - {4, 0x18} } -#endif - -#ifndef __ASSEMBLY__ -void fpga_gpio_set(unsigned int bus, int pin); -void fpga_gpio_clear(unsigned int bus, int pin); -int fpga_gpio_get(unsigned int bus, int pin); -void fpga_control_set(unsigned int bus, int pin); -void fpga_control_clear(unsigned int bus, int pin); -#endif - -#ifdef CONFIG_STRIDER_CON -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) -#define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ - (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) -#elif defined(CONFIG_STRIDER_CON_DP) -#define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) -#define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) -#define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) -#else -#define I2C_SDA_GPIO 0x0040 -#define I2C_SCL_GPIO 0x0020 -#define I2C_FPGA_IDX I2C_ADAP_HWNR -#endif - -#ifdef CONFIG_STRIDER_CON_DP -#define I2C_ACTIVE \ - do { \ - if (I2C_ADAP_HWNR > 7) \ - fpga_control_set(I2C_FPGA_IDX, 0x0004); \ - else \ - fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ - } while (0) -#else -#define I2C_ACTIVE { } -#endif - -#define I2C_TRISTATE { } -#define I2C_READ \ - (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) -#define I2C_SDA(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ - } while (0) -#define I2C_SCL(bit) \ - do { \ - if (bit) \ - fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - else \ - fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ - } while (0) -#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ - -/* - * Software (bit-bang) MII driver configuration - */ -#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ -#define CONFIG_BITBANGMII_MULTI - -/* - * OSD Setup - */ -#define CONFIG_SYS_OSD_SCREENS 1 -#define CONFIG_SYS_DP501_DIFFERENTIAL -#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ - -#ifdef CONFIG_STRIDER_CON_DP -#define CONFIG_SYS_OSD_DH -#endif - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCIE1_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 -#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 - -/* enable PCIE clock */ -#define CONFIG_SYS_SCCR_PCIEXP1CM 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCIE - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 - -/* - * TSEC - */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) - -/* - * TSEC ethernet configuration - */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "eTSEC0" -#define TSEC1_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define TSEC1_FLAGS 0 - -/* Options are: eTSEC[0-1] */ -#define CONFIG_ETHPRIME "eTSEC0" - -/* - * Environment - */ -#if 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#else -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ -#endif - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ - -/* - * Environment Configuration - */ - -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#endif - -#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ - - -#define CONFIG_HOSTNAME "hrcon" -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS1\0" \ - "u-boot=u-boot.bin\0" \ - "kernel_addr=1000000\0" \ - "fdt_addr=C00000\0" \ - "fdtfile=hrcon.dtb\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ - " +${filesize};cp.b ${fileaddr} " \ - __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ - "upd=run load update\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp ${kernel_addr} $bootfile;" \ - "tftp ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_MMCBOOTCOMMAND \ - "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ - "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ - "bootm ${kernel_addr} - ${fdt_addr}" - -#define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND - -#endif /* __CONFIG_H */ diff --git a/include/configs/stv0991.h b/include/configs/stv0991.h deleted file mode 100644 index e526208..0000000 --- a/include/configs/stv0991.h +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, STMicroelectronics - All Rights Reserved - * Author(s): Vikas Manocha, for STMicroelectronics. - */ - -#ifndef __CONFIG_STV0991_H -#define __CONFIG_STV0991_H -#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH - -/* ram memory-related information */ -#define PHYS_SDRAM_1 0x00000000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define PHYS_SDRAM_1_SIZE 0x00198000 - -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET 0x30000 -#define CONFIG_ENV_ADDR \ - (PHYS_SDRAM_1_SIZE - CONFIG_ENV_SIZE) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024) - -/* user interface */ -#define CONFIG_SYS_CBSIZE 1024 - -/* MISC */ -#define CONFIG_SYS_LOAD_ADDR 0x00000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_RAM_ADDR 0x00190000 -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -/* U-Boot Load Address */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* GMAC related configs */ - -#define CONFIG_DW_ALTDESCRIPTOR - -/* Command support defines */ -#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ - -#define CONFIG_SYS_MEMTEST_START 0x0000 -#define CONFIG_SYS_MEMTEST_END 1024*1024 - -/* Misc configuration */ - -#define CONFIG_BOOTCOMMAND "go 0x40040000" - -/* -+ * QSPI support -+ */ -#ifdef CONFIG_OF_CONTROL /* QSPI is controlled via DT */ -#define CONFIG_CQSPI_REF_CLK ((30/4)/2)*1000*1000 - -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h deleted file mode 100644 index 6033760..0000000 --- a/include/configs/sun4i.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012-2013 Henrik Nordstrom - * - * Configuration settings for the Allwinner A10 (sun4i) CPU - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * A10 specific configuration - */ - -/* - * Include common sunxi configuration where most the settings are - */ -#include - -#define CONFIG_MACH_TYPE (4104 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - -#endif /* __CONFIG_H */ diff --git a/include/configs/sun50i.h b/include/configs/sun50i.h deleted file mode 100644 index e050a52..0000000 --- a/include/configs/sun50i.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the Allwinner A64 (sun50i) CPU - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * A64 specific configuration - */ - -#ifndef CONFIG_MACH_SUN50I_H6 -#define GICD_BASE 0x1c81000 -#define GICC_BASE 0x1c82000 -#else -#define GICD_BASE 0x3021000 -#define GICC_BASE 0x3022000 -#endif - -/* - * Include common sunxi configuration where most the settings are - */ -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h deleted file mode 100644 index ee42af8..0000000 --- a/include/configs/sun5i.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012-2013 Henrik Nordstrom - * - * Configuration settings for the Allwinner A13 (sun5i) CPU - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -/* - * Include common sunxi configuration where most the settings are - */ -#include - -#define CONFIG_MACH_TYPE (4138 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - -#endif /* __CONFIG_H */ diff --git a/include/configs/sun6i.h b/include/configs/sun6i.h deleted file mode 100644 index 1e490da..0000000 --- a/include/configs/sun6i.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012-2013 Henrik Nordstrom - * (C) Copyright 2013 Luke Kenneth Casson Leighton - * (C) Copyright 2013 Maxime Ripard - * - * Configuration settings for the Allwinner A31 (sun6i) CPU - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * A31 specific configuration - */ - -#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE -#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ - -/* - * Include common sunxi configuration where most the settings are - */ -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/sun7i.h b/include/configs/sun7i.h deleted file mode 100644 index d2fd586..0000000 --- a/include/configs/sun7i.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012-2013 Henrik Nordstrom - * (C) Copyright 2013 Luke Kenneth Casson Leighton - * - * Configuration settings for the Allwinner A20 (sun7i) CPU - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * A20 specific configuration - */ - -#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE -#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */ - -/* - * Include common sunxi configuration where most the settings are - */ -#include - -#define CONFIG_MACH_TYPE (4283 | ((CONFIG_MACH_TYPE_COMPAT_REV) << 28)) - -#endif /* __CONFIG_H */ diff --git a/include/configs/sun8i.h b/include/configs/sun8i.h deleted file mode 100644 index 9b4675e..0000000 --- a/include/configs/sun8i.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 Chen-Yu Tsai - * - * Configuration settings for the Allwinner A23 (sun8i) CPU - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * A23 specific configuration - */ - -/* - * Include common sunxi configuration where most the settings are - */ -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/sun9i.h b/include/configs/sun9i.h deleted file mode 100644 index 6ee08cf..0000000 --- a/include/configs/sun9i.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Hans de Goede - * - * Configuration settings for the Allwinner A80 (sun9i) CPU - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * A80 specific configuration - */ - -/* - * Include common sunxi configuration where most the settings are - */ -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h deleted file mode 100644 index 0ef289f..0000000 --- a/include/configs/sunxi-common.h +++ /dev/null @@ -1,509 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012-2012 Henrik Nordstrom - * - * (C) Copyright 2007-2011 - * Allwinner Technology Co., Ltd. - * Tom Cubie - * - * Configuration settings for the Allwinner sunxi series of boards. - */ - -#ifndef _SUNXI_COMMON_CONFIG_H -#define _SUNXI_COMMON_CONFIG_H - -#include -#include - -#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT -/* - * The U-Boot workarounds bugs in the outdated buggy sunxi-3.4 kernels at the - * expense of restricting some features, so the regular machine id values can - * be used. - */ -# define CONFIG_MACH_TYPE_COMPAT_REV 0 -#else -/* - * A compatibility guard to prevent loading outdated buggy sunxi-3.4 kernels. - * Only sunxi-3.4 kernels with appropriate fixes applied are able to pass - * beyond the machine id check. - */ -# define CONFIG_MACH_TYPE_COMPAT_REV 1 -#endif - -#ifdef CONFIG_ARM64 -#define CONFIG_SYS_BOOTM_LEN (32 << 20) -#endif - -/* Serial & console */ -#define CONFIG_SYS_NS16550_SERIAL -/* ns16550 reg in the low bits of cpu reg */ -#define CONFIG_SYS_NS16550_CLK 24000000 -#ifndef CONFIG_DM_SERIAL -# define CONFIG_SYS_NS16550_REG_SIZE -4 -# define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE -# define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE -# define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE -# define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE -# define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE -#endif - -/* CPU */ -#define COUNTER_FREQUENCY 24000000 - -/* - * The DRAM Base differs between some models. We cannot use macros for the - * CONFIG_FOO defines which contain the DRAM base address since they end - * up unexpanded in include/autoconf.mk . - * - * So we have to have this #ifdef #else #endif block for these. - */ -#ifdef CONFIG_MACH_SUN9I -#define SDRAM_OFFSET(x) 0x2##x -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* default load address */ -/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here - * since it needs to fit in with the other values. By also #defining it - * we get warnings if the Kconfig value mismatches. */ -#define CONFIG_SPL_STACK_R_ADDR 0x2fe00000 -#define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 -#else -#define SDRAM_OFFSET(x) 0x4##x -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_LOAD_ADDR 0x42000000 /* default load address */ -/* V3s do not have enough memory to place code at 0x4a000000 */ -/* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here - * since it needs to fit in with the other values. By also #defining it - * we get warnings if the Kconfig value mismatches. */ -#define CONFIG_SPL_STACK_R_ADDR 0x4fe00000 -#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 -#endif - -#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ - -/* - * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is - * slightly bigger. Note that it is possible to map the first 32 KiB of the - * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the - * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and - * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. - * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register - * is known yet. - * H6 has SRAM A1 at 0x00020000. - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS -/* FIXME: this may be larger on some SoCs */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ - -#ifdef CONFIG_AHCI -#define CONFIG_SYS_64BIT_LBA -#endif - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_SERIAL_TAG - -#ifdef CONFIG_NAND_SUNXI -#define CONFIG_SYS_NAND_MAX_ECCPOS 1664 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MAX_NAND_DEVICE 8 -#endif - -/* mmc config */ -#ifdef CONFIG_MMC -#define CONFIG_MMC_SUNXI_SLOT 0 -#endif - -#if defined(CONFIG_ENV_IS_IN_MMC) - -#ifdef CONFIG_ARM64 -/* - * This is actually (CONFIG_ENV_OFFSET - - * (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used - * directly in a makefile, without the preprocessor expansion. - */ -#define CONFIG_BOARD_SIZE_LIMIT 0x7e000 -#endif - -#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 -/* If we have two devices (most likely eMMC + MMC), favour the eMMC */ -#define CONFIG_SYS_MMC_ENV_DEV 1 -#else -/* Otherwise, use the only device we have */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif -#define CONFIG_SYS_MMC_MAX_DEVICE 4 -#endif - -#ifndef CONFIG_MACH_SUN8I_V3S -/* 64MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (64 << 20)) -#else -/* 2MB of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (2 << 20)) -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ - -/* standalone support */ -#define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR - -/* FLASH and environment organization */ - -#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ - -#ifndef CONFIG_ARM64 /* AArch64 FEL support is not ready yet */ -#define CONFIG_SPL_BOARD_LOAD_IMAGE -#endif - -/* - * We cannot use expressions here, because expressions won't be evaluated in - * autoconf.mk. - */ -#if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ -#ifdef CONFIG_ARM64 -/* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ -#define LOW_LEVEL_SRAM_STACK 0x00054000 -#else -#define LOW_LEVEL_SRAM_STACK 0x00018000 -#endif /* !CONFIG_ARM64 */ -#elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 -#define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ -/* end of SRAM A2 on H6 for now */ -#define LOW_LEVEL_SRAM_STACK 0x00118000 -#else -#define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */ -#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ -#endif - -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ - - -/* I2C */ -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_SY8106A_POWER -#endif - -#if defined CONFIG_I2C0_ENABLE || defined CONFIG_I2C1_ENABLE || \ - defined CONFIG_I2C2_ENABLE || defined CONFIG_I2C3_ENABLE || \ - defined CONFIG_I2C4_ENABLE || defined CONFIG_R_I2C_ENABLE -#define CONFIG_SYS_I2C_MVTWSI -#ifndef CONFIG_DM_I2C -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x7f -#endif -#endif - -#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) -#define CONFIG_SYS_I2C_SOFT -#define CONFIG_SYS_I2C_SOFT_SPEED 50000 -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 -/* We use pin names in Kconfig and sunxi_name_to_gpio() */ -#define CONFIG_SOFT_I2C_GPIO_SDA soft_i2c_gpio_sda -#define CONFIG_SOFT_I2C_GPIO_SCL soft_i2c_gpio_scl -#ifndef __ASSEMBLY__ -extern int soft_i2c_gpio_sda; -extern int soft_i2c_gpio_scl; -#endif -#define CONFIG_VIDEO_LCD_I2C_BUS 0 /* The lcd panel soft i2c is bus 0 */ -#define CONFIG_SYS_SPD_BUS_NUM 1 /* And the axp209 i2c bus is bus 1 */ -#else -#define CONFIG_SYS_SPD_BUS_NUM 0 /* The axp209 i2c bus is bus 0 */ -#define CONFIG_VIDEO_LCD_I2C_BUS -1 /* NA, but necessary to compile */ -#endif - -/* PMU */ -#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \ - defined CONFIG_AXP221_POWER || defined CONFIG_AXP818_POWER || \ - defined CONFIG_SY8106A_POWER -#endif - -#ifdef CONFIG_REQUIRE_SERIAL_CONSOLE -#if CONFIG_CONS_INDEX == 1 -#ifdef CONFIG_MACH_SUN9I -#define OF_STDOUT_PATH "/soc/serial@07000000:115200" -#else -#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28000:115200" -#endif -#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I) -#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200" -#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I) -#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200" -#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I) -#define OF_STDOUT_PATH "/soc@01c00000/serial@01f02800:115200" -#else -#error Unsupported console port nr. Please fix stdout-path in sunxi-common.h. -#endif -#endif /* ifdef CONFIG_REQUIRE_SERIAL_CONSOLE */ - -#ifdef CONFIG_VIDEO_SUNXI -/* - * The amount of RAM to keep free at the top of RAM when relocating u-boot, - * to use as framebuffer. This must be a multiple of 4096. - */ -#define CONFIG_SUNXI_MAX_FB_SIZE (16 << 20) - -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_STD_TIMINGS -#define CONFIG_I2C_EDID -#define VIDEO_LINE_LEN (pGD->plnSizeX) - -/* allow both serial and cfb console. */ -/* stop x86 thinking in cfbconsole from trying to init a pc keyboard */ - -#endif /* CONFIG_VIDEO_SUNXI */ - -/* Ethernet support */ - -#ifdef CONFIG_SUN7I_GMAC -#define CONFIG_PHY_REALTEK -#endif - -#ifdef CONFIG_USB_EHCI_HCD -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 -#endif - -#ifndef CONFIG_SPL_BUILD - -#ifdef CONFIG_ARM64 -/* - * Boards seem to come with at least 512MB of DRAM. - * The kernel should go at 512K, which is the default text offset (that will - * be adjusted at runtime if needed). - * There is no compression for arm64 kernels (yet), so leave some space - * for really big kernels, say 256MB for now. - * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. - * Align the initrd to a 2MB page. - */ -#define BOOTM_SIZE __stringify(0xa000000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) - -#else -/* - * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. - * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, - * 1M script, 1M pxe and the ramdisk at the end. - */ -#ifndef CONFIG_MACH_SUN8I_V3S -#define BOOTM_SIZE __stringify(0xa000000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3300000)) -#else -/* - * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. - * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, - * 1M script, 1M pxe and the ramdisk at the end. - */ -#define BOOTM_SIZE __stringify(0x2e00000) -#define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) -#define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000)) -#define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000)) -#define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000)) -#define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) -#endif -#endif - -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=" BOOTM_SIZE "\0" \ - "kernel_addr_r=" KERNEL_ADDR_R "\0" \ - "fdt_addr_r=" FDT_ADDR_R "\0" \ - "scriptaddr=" SCRIPT_ADDR_R "\0" \ - "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ - "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" - -#define DFU_ALT_INFO_RAM \ - "dfu_alt_info_ram=" \ - "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ - "fdt ram " FDT_ADDR_R " 0x100000;" \ - "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" - -#ifdef CONFIG_MMC -#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 -#define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ - BOOTENV_DEV_MMC(MMC, mmc, 0) \ - BOOTENV_DEV_MMC(MMC, mmc, 1) \ - "bootcmd_mmc_auto=" \ - "if test ${mmc_bootdev} -eq 1; then " \ - "run bootcmd_mmc1; " \ - "run bootcmd_mmc0; " \ - "elif test ${mmc_bootdev} -eq 0; then " \ - "run bootcmd_mmc0; " \ - "run bootcmd_mmc1; " \ - "fi\0" - -#define BOOTENV_DEV_NAME_MMC_AUTO(devtypeu, devtypel, instance) \ - "mmc_auto " - -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC_AUTO, mmc_auto, na) -#else -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) -#endif -#else -#define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#ifdef CONFIG_AHCI -#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) -#else -#define BOOT_TARGET_DEVICES_SCSI(func) -#endif - -#ifdef CONFIG_USB_STORAGE -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_DEVICES_USB(func) -#endif - -#ifdef CONFIG_CMD_PXE -#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) -#else -#define BOOT_TARGET_DEVICES_PXE(func) -#endif - -#ifdef CONFIG_CMD_DHCP -#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) -#else -#define BOOT_TARGET_DEVICES_DHCP(func) -#endif - -/* FEL boot support, auto-execute boot.scr if a script address was provided */ -#define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ - "bootcmd_fel=" \ - "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ - "echo '(FEL boot)'; " \ - "source ${fel_scriptaddr}; " \ - "fi\0" -#define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ - "fel " - -#define BOOT_TARGET_DEVICES(func) \ - func(FEL, fel, na) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_SCSI(func) \ - BOOT_TARGET_DEVICES_USB(func) \ - BOOT_TARGET_DEVICES_PXE(func) \ - BOOT_TARGET_DEVICES_DHCP(func) - -#ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT -#define BOOTCMD_SUNXI_COMPAT \ - "bootcmd_sunxi_compat=" \ - "setenv root /dev/mmcblk0p3 rootwait; " \ - "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ - "echo Loaded environment from uEnv.txt; " \ - "env import -t 0x44000000 ${filesize}; " \ - "fi; " \ - "setenv bootargs console=${console} root=${root} ${extraargs}; " \ - "ext2load mmc 0 0x43000000 script.bin && " \ - "ext2load mmc 0 0x48000000 uImage && " \ - "bootm 0x48000000\0" -#else -#define BOOTCMD_SUNXI_COMPAT -#endif - -#include - -#ifdef CONFIG_USB_KEYBOARD -#define CONSOLE_STDIN_SETTINGS \ - "preboot=usb start\0" \ - "stdin=serial,usbkbd\0" -#else -#define CONSOLE_STDIN_SETTINGS \ - "stdin=serial\0" -#endif - -#ifdef CONFIG_VIDEO -#define CONSOLE_STDOUT_SETTINGS \ - "stdout=serial,vga\0" \ - "stderr=serial,vga\0" -#elif CONFIG_DM_VIDEO -#define CONSOLE_STDOUT_SETTINGS \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" -#else -#define CONSOLE_STDOUT_SETTINGS \ - "stdout=serial\0" \ - "stderr=serial\0" -#endif - -#ifdef CONFIG_MTDIDS_DEFAULT -#define SUNXI_MTDIDS_DEFAULT \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" -#else -#define SUNXI_MTDIDS_DEFAULT -#endif - -#ifdef CONFIG_MTDPARTS_DEFAULT -#define SUNXI_MTDPARTS_DEFAULT \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" -#else -#define SUNXI_MTDPARTS_DEFAULT -#endif - -#define PARTS_DEFAULT \ - "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ - "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ - "name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \ - "name=system,size=-,uuid=${uuid_gpt_system};" - -#define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b" - -#ifdef CONFIG_ARM64 -#define UUID_GPT_SYSTEM "b921b045-1df0-41c3-af44-4c6f280d3fae" -#else -#define UUID_GPT_SYSTEM "69dad710-2ce4-4e3c-b16c-21a1d49abed3" -#endif - -#define CONSOLE_ENV_SETTINGS \ - CONSOLE_STDIN_SETTINGS \ - CONSOLE_STDOUT_SETTINGS - -#ifdef CONFIG_ARM64 -#define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" -#else -#define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONSOLE_ENV_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ - DFU_ALT_INFO_RAM \ - "fdtfile=" FDTFILE "\0" \ - "console=ttyS0,115200\0" \ - SUNXI_MTDIDS_DEFAULT \ - SUNXI_MTDPARTS_DEFAULT \ - "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ - "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ - "partitions=" PARTS_DEFAULT "\0" \ - BOOTCMD_SUNXI_COMPAT \ - BOOTENV - -#else /* ifndef CONFIG_SPL_BUILD */ -#define CONFIG_EXTRA_ENV_SETTINGS -#endif - -#endif /* _SUNXI_COMMON_CONFIG_H */ diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h deleted file mode 100644 index 1705f9c..0000000 --- a/include/configs/suvd3.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#define CONFIG_HOSTNAME "suvd3" -#define CONFIG_KM_BOARD_NAME "suvd3" - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ - 0x0000c000 | \ - MxMR_WLFx_2X) -#endif /* __CONFIG_H */ diff --git a/include/configs/syzygy_hub.h b/include/configs/syzygy_hub.h deleted file mode 100644 index e31b77c..0000000 --- a/include/configs/syzygy_hub.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 Xilinx - * (C) Copyright 2017 Opal Kelly Inc. - * - * Configuration settings for the SYZYGY Hub development board - * See zynq-common.h for Zynq common configs - */ - -#ifndef __CONFIG_SYZYGY_HUB_H -#define __CONFIG_SYZYGY_HUB_H - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fit_image=fit.itb\0" \ - "bitstream_image=download.bit\0" \ - "loadbit_addr=0x1000000\0" \ - "load_addr=0x2000000\0" \ - "fit_size=0x800000\0" \ - "flash_off=0x100000\0" \ - "nor_flash_off=0xE2100000\0" \ - "fdt_high=0x20000000\0" \ - "initrd_high=0x20000000\0" \ - "loadbootenv_addr=0x2000000\0" \ - "fdt_addr_r=0x1f00000\0" \ - "pxefile_addr_r=0x2000000\0" \ - "kernel_addr_r=0x2000000\0" \ - "scriptaddr=0x3000000\0" \ - "ramdisk_addr_r=0x3100000\0" \ - "bootenv=uEnv.txt\0" \ - "bootenv_dev=mmc\0" \ - "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \ - "env import -t ${loadbootenv_addr} $filesize\0" \ - "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \ - "setbootenv=if env run bootenv_existence_test; then " \ - "if env run loadbootenv; then " \ - "env run importbootenv; " \ - "fi; " \ - "fi; \0" \ - "sd_loadbootenv=set bootenv_dev mmc && " \ - "run setbootenv \0" \ - "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv\0" \ - "preboot=if test $modeboot = sdboot; then " \ - "run sd_loadbootenv; " \ - "echo Checking if uenvcmd is set ...; " \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...; " \ - "run uenvcmd; " \ - "fi; " \ - "fi; \0" \ - "sdboot=echo Copying FPGA Bitstream from SD to RAM... && " \ - "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ - "echo Programming FPGA... && " \ - "fpga loadb 0 ${loadbit_addr} ${filesize} && " \ - "echo Copying FIT from SD to RAM... && " \ - "load mmc 0 ${load_addr} ${fit_image} && " \ - "bootm ${load_addr}\0" \ - "jtagboot=echo TFTPing FIT to RAM... && " \ - "tftpboot ${load_addr} ${fit_image} && " \ - "bootm ${load_addr}\0" \ - DFU_ALT_INFO \ - BOOTENV - -#include - -#endif /* __CONFIG_SYZYGY_HUB_H */ diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h deleted file mode 100644 index bf37501..0000000 --- a/include/configs/t4qds.h +++ /dev/null @@ -1,254 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2011-2012 Freescale Semiconductor, Inc. - */ - -/* - * Corenet DS style board configuration file - */ -#ifndef __T4QDS_H -#define __T4QDS_H - -/* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ - -#ifndef CONFIG_RESET_VECTOR_ADDRESS -#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc -#endif - -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_SRIO2 /* SRIO port 2 */ - -#define CONFIG_ENV_OVERWRITE - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_SYS_CACHE_STASHING -#define CONFIG_BTB /* toggle branch predition */ -#ifdef CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#endif - -#define CONFIG_ENABLE_36BIT_PHYS - -#define CONFIG_ADDR_MAP -#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L3 Cache as L3 SRAM - */ -#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (512 << 10) -#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024) -#ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024) -#endif -#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024) -#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10) -#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024) - -#define CONFIG_SYS_DCSRBAR 0xf0000000 -#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull - -/* - * DDR Setup - */ -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 2 -#define CONFIG_CHIP_SELECTS_PER_CTRL 4 - -#define CONFIG_DDR_SPD - -/* - * IFC Definitions - */ -#define CONFIG_SYS_FLASH_BASE 0xe0000000 -#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE -#else -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -#define CONFIG_HWCONFIG - -/* define to use L1 as initial stack */ -#define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK -#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 -/* The assembler doesn't like typecast */ -#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ - ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ - CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -/* Serial Port - controlled on board with jumper J8 - * open - index 2 - * shorted - index 1 - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) -#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) -#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 - -/* - * RapidIO - */ -#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ - -#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ - -/* controller 1, direct to uli, tgtid 3, Base address 20000 */ -#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ - -/* controller 2, Slot 2, tgtid 2, Base address 201000 */ -#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ - -/* controller 3, Slot 1, tgtid 1, Base address 202000 */ -#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ - -/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif - -#ifdef CONFIG_FMAN_ENET -#define CONFIG_ETHPRIME "FM1@DTSEC1" -#endif - -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 64 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -#ifdef CONFIG_CMD_KGDB -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/ - -/* default location for tftp and bootm */ -#define CONFIG_LOADADDR 1000000 - -#define CONFIG_HVBOOT \ - "setenv bootargs config-addr=0x60000000; " \ - "bootm 0x01000000 - 0x00f00000" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tao3530.h b/include/configs/tao3530.h deleted file mode 100644 index 7a54fe3..0000000 --- a/include/configs/tao3530.h +++ /dev/null @@ -1,234 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the TechNexion TAO-3530 SOM - * equipped on Thunder baseboard. - * - * Edward Lin - * Tapani Utriainen - * - * Copyright (C) 2013 Stefan Roese - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ - -#include /* get chip and board defs */ -#include - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) - -/* - * Hardware drivers - */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* commands to include */ - -#define CONFIG_SYS_I2C -#define CONFIG_I2C_MULTI_BUS - -/* - * TWL4030 - */ - -/* - * Board NAND Info. - */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -/* Environment information */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=ttyO2,115200n8\0" \ - "mpurate=600\0" \ - "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ - "tv_mode=omapfb.mode=tv:ntsc\0" \ - "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ - "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ - "extra_options= \0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 rw\0" \ - "mmcrootfstype=ext3 rootwait\0" \ - "nandroot=ubi0:rootfs ubi.mtd=4\0" \ - "nandrootfstype=ubifs\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "${video_mode} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype} " \ - "${extra_options}\0" \ - "nandargs=setenv bootargs console=${console} " \ - "mpurate=${mpurate} " \ - "${video_mode} " \ - "${network_setting} " \ - "root=${nandroot} " \ - "rootfstype=${nandrootfstype} "\ - "${extra_options}\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "nand read ${loadaddr} 280000 400000; " \ - "bootm ${loadaddr}\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi" - -/* - * Miscellaneous configurable options - */ - -/* turn on command-line edit/hist/auto */ - -#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ - /* defaults */ -#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ -#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ - /* load address */ - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * FLASH and environment organization - */ - -/* **** PISMO SUPPORT *** */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE NAND_BASE - -/* Monitor at start of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP - -#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ - -#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* - * USB - * - * Currently only EHCI is enabled, the MUSB OTG controller - * is not enabled. - */ - -/* USB EHCI */ -#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 - -/* Defines for SPL */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -/* - * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: - * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT - */ -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13 } -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -/* - * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the - * older x-loader implementations. And move the BSS area so that it - * doesn't overlap with TEXT_BASE. - */ -#define CONFIG_SPL_BSS_START_ADDR 0x80100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h deleted file mode 100644 index fdd1c52..0000000 --- a/include/configs/taurus.h +++ /dev/null @@ -1,216 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common board functions for Siemens TAURUS (AT91SAM9G20) based boards - * (C) Copyright 2013 Siemens AG - * - * Based on: - * U-Boot file: include/configs/at91sam9260ek.h - * - * (C) Copyright 2007-2008 - * Stelian Pop - * Lead Tech Design - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * SoC must be defined first, before hardware.h is included. - * In this case SoC is defined in boards.cfg. - */ -#include -#include - -/* - * Warning: changing CONFIG_SYS_TEXT_BASE requires - * adapting the initial boot program. - * Since the linker has to swallow that define, we must use a pure - * hex number here! - */ - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* main clock xtal */ - -/* Misc CPU related */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO -#define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ - -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* - * SDRAM: 1 bank, min 32, max 128 MB - * Initialized before u-boot gets started. - */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) - -/* - * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, - * leaving the correct space for initial global data structure above - * that address while providing maximum stack area below. - */ -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -#define CONFIG_SYS_NAND_DBW_8 -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* USB */ -#if defined(CONFIG_BOARD_TAURUS) -#define CONFIG_USB_ATMEL -#define CONFIG_USB_ATMEL_CLK_SEL_PLLB -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 - -/* USB DFU support */ - -#define CONFIG_USB_GADGET_AT91 - -/* DFU class support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE (SZ_1M) -#define DFU_MANIFEST_POLL_TIMEOUT 25000 -#endif - -/* SPI EEPROM */ -#define TAURUS_SPI_MASK (1 << 4) - -#if defined(CONFIG_SPL_BUILD) -/* SPL related */ -#endif - -/* load address */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - -/* bootstrap in spi flash , u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET_REDUND 0x180000 - -#ifndef CONFIG_SPL_BUILD -#if defined(CONFIG_BOARD_AXM) -#define CONFIG_EXTRA_ENV_SETTINGS \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ - "${gatewayip}:${netmask}:${hostname}:${netdev}::off\0" \ - "addtest=setenv bootargs ${bootargs} loglevel=4 test\0" \ - "boot_file=setenv bootfile /${project_dir}/kernel/uImage\0" \ - "boot_retries=0\0" \ - "ethact=macb0\0" \ - "flash_nfs=run nand_kernel;run nfsargs;run addip;" \ - "upgrade_available;bootm ${kernel_ram};reset\0" \ - "flash_self=run nand_kernel;run setbootargs;upgrade_available;" \ - "bootm ${kernel_ram};reset\0" \ - "flash_self_test=run nand_kernel;run setbootargs addtest;" \ - "upgrade_available;bootm ${kernel_ram};reset\0" \ - "hostname=systemone\0" \ - "kernel_Off=0x00200000\0" \ - "kernel_Off_fallback=0x03800000\0" \ - "kernel_ram=0x21500000\0" \ - "kernel_size=0x00400000\0" \ - "kernel_size_fallback=0x00400000\0" \ - "loads_echo=1\0" \ - "nand_kernel=nand read.e ${kernel_ram} ${kernel_Off} " \ - "${kernel_size}\0" \ - "net_nfs=run boot_file;tftp ${kernel_ram} ${bootfile};" \ - "run nfsargs;run addip;upgrade_available;" \ - "bootm ${kernel_ram};reset\0" \ - "netdev=eth0\0" \ - "nfsargs=run root_path;setenv bootargs ${bootargs} root=/dev/nfs " \ - "rw nfsroot=${serverip}:${rootpath} " \ - "at91sam9_wdt.wdt_timeout=16\0" \ - "partitionset_active=A\0" \ - "preboot=echo;echo Type 'run flash_self' to use kernel and root " \ - "filesystem on memory;echo Type 'run flash_nfs' to use " \ - "kernel from memory and root filesystem over NFS;echo Type " \ - "'run net_nfs' to get Kernel over TFTP and mount root " \ - "filesystem over NFS;echo\0" \ - "project_dir=systemone\0" \ - "root_path=setenv rootpath /home/projects/${project_dir}/rootfs\0" \ - "rootfs=/dev/mtdblock5\0" \ - "rootfs_fallback=/dev/mtdblock7\0" \ - "setbootargs=setenv bootargs ${bootargs} console=ttyMTD,mtdoops " \ - "root=${rootfs} rootfstype=jffs2 panic=7 " \ - "at91sam9_wdt.wdt_timeout=16\0" \ - "stderr=serial\0" \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "upgrade_available=0\0" -#endif -#endif /* #ifndef CONFIG_SPL_BUILD */ -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN \ - ROUND(3 * CONFIG_ENV_SIZE + SZ_4M, 0x1000) - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (31 * SZ_512) -#define CONFIG_SPL_STACK (ATMEL_BASE_SRAM1 + SZ_16K) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SYS_MALLOC_LEN) -#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN - -#define CONFIG_SPL_BSS_START_ADDR CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_BSS_MAX_SIZE (3 * SZ_512) - -#define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) -#define CONFIG_SYS_USE_NANDFLASH 1 -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_NAND_RAW_ONLY -#define CONFIG_SPL_NAND_SOFTECC -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_5_ADDR_CYCLE - -#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M) -#define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K -#define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCSIZE 256 -#define CONFIG_SYS_NAND_ECCBYTES 3 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ - 48, 49, 50, 51, 52, 53, 54, 55, \ - 56, 57, 58, 59, 60, 61, 62, 63, } - -#define CONFIG_SPL_ATMEL_SIZE -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define AT91_PLL_LOCK_TIMEOUT 1000000 -#define CONFIG_SYS_AT91_PLLA 0x202A3F01 -#define CONFIG_SYS_MCKR 0x1300 -#define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) -#define CONFIG_SYS_AT91_PLLB 0x10193F05 - -#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO - -#endif diff --git a/include/configs/tb100.h b/include/configs/tb100.h deleted file mode 100644 index a761c37..0000000 --- a/include/configs/tb100.h +++ /dev/null @@ -1,65 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011-2014 Pierrick Hascoet, Abilis Systems - */ - -#ifndef _CONFIG_TB100_H_ -#define _CONFIG_TB100_H_ - -#include - -/* - * Memory configuration - */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MALLOC_LEN SZ_128K -#define CONFIG_SYS_BOOTM_LEN SZ_32M -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -/* - * UART configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK 166666666 - -/* - * Even though the board houses Realtek RTL8211E PHY - * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly. - * In particular "parse_status" reports link is down. - * - * Until Realtek PHY driver is fixed fall back to generic PHY driver - * which implements all required functionality and behaves much more stable. - * - * #define CONFIG_PHY_REALTEK - * - */ - -/* - * Ethernet configuration - */ -#define ETH0_BASE_ADDRESS 0xFE100000 -#define ETH1_BASE_ADDRESS 0xFE110000 - -/* - * Command line configuration - */ - -/* - * Environment configuration - */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -/* - * Console configuration - */ - -#endif /* _CONFIG_TB100_H_ */ diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h deleted file mode 100644 index 46d67a7..0000000 --- a/include/configs/tbs2910.h +++ /dev/null @@ -1,117 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 Soeren Moch - * - * Configuration settings for the TBS2910 MatrixARM board. - */ - -#ifndef __TBS2910_CONFIG_H -#define __TBS2910_CONFIG_H - -#include "mx6_common.h" - -/* General configuration */ - -#define CONFIG_MACH_TYPE 3980 - -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_IMX_THERMAL - -/* Physical Memory Map */ -#define CONFIG_SYS_SDRAM_BASE MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END \ - (CONFIG_SYS_MEMTEST_START + 500 * 1024 * 1024) - -#define CONFIG_SYS_BOOTMAPSZ 0x10000000 - -/* Serial console */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE /* select UART1/UART2 */ - -/* Framebuffer */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP -#endif - -/* PCI */ -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) -#endif - -/* SATA */ -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#ifdef CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USBD_HS -#endif /* CONFIG_CMD_USB_MASS_STORAGE */ -#endif /* CONFIG_CMD_USB */ - -/* Environment organization */ -#define CONFIG_SYS_MMC_ENV_DEV 2 /* overwritten on SD boot */ -#define CONFIG_SYS_MMC_ENV_PART 1 /* overwritten on SD boot */ -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_OFFSET (384 * 1024) -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_BOARD_SIZE_LIMIT 392192 /* (CONFIG_ENV_OFFSET - 1024) */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_mmc1=console=ttymxc0,115200 di0_primary console=tty1\0" \ - "bootargs_mmc2=video=mxcfb0:dev=hdmi,1920x1080M@60 " \ - "video=mxcfb1:off video=mxcfb2:off fbmem=28M\0" \ - "bootargs_mmc3=root=/dev/mmcblk0p1 rootwait consoleblank=0 quiet\0" \ - "bootargs_mmc=setenv bootargs ${bootargs_mmc1} ${bootargs_mmc2} " \ - "${bootargs_mmc3}\0" \ - "bootargs_upd=setenv bootargs console=ttymxc0,115200 " \ - "rdinit=/sbin/init enable_wait_mode=off\0" \ - "bootcmd_mmc=run bootargs_mmc; mmc dev 2; " \ - "mmc read 0x10800000 0x800 0x4000; bootm 0x10800000\0" \ - "bootcmd_up1=load mmc 1 0x10800000 uImage\0" \ - "bootcmd_up2=load mmc 1 0x10d00000 uramdisk.img; " \ - "run bootargs_upd; " \ - "bootm 0x10800000 0x10d00000\0" \ - "console=ttymxc0\0" \ - "fan=gpio set 92\0" \ - "set_con_serial=setenv stdout serial; " \ - "setenv stderr serial\0" \ - "set_con_hdmi=setenv stdout serial,vga; " \ - "setenv stderr serial,vga\0" \ - "stderr=serial,vga\0" \ - "stdin=serial,usbkbd\0" \ - "stdout=serial,vga\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "if run bootcmd_up1; then " \ - "run bootcmd_up2; " \ - "else " \ - "run bootcmd_mmc; " \ - "fi" - -#endif /* __TBS2910_CONFIG_H * */ diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h deleted file mode 100644 index b637832..0000000 --- a/include/configs/tec-ng.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra30-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten™ NG Evaluation Carrier" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -/* SPI */ -#define CONFIG_TEGRA_SLINK_CTRLS 6 -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -/* Tag support */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tec.h b/include/configs/tec.h deleted file mode 100644 index 907c8d5..0000000 --- a/include/configs/tec.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - * (C) Copyright 2011-2012 - * Avionic Design GmbH - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Tamonten Evaluation Carrier" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */ -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -/* NAND support */ -#define CONFIG_TEGRA_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* Environment in NAND, aligned to start of last sector */ -#define CONFIG_ENV_OFFSET (SZ_512M - SZ_128K) /* 128K sectors */ - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h deleted file mode 100644 index fae0e76..0000000 --- a/include/configs/tegra-common-post.h +++ /dev/null @@ -1,121 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef __TEGRA_COMMON_POST_H -#define __TEGRA_COMMON_POST_H - -/* - * Size of malloc() pool - */ -#ifdef CONFIG_DFU_OVER_USB -#define CONFIG_SYS_MALLOC_LEN (SZ_4M + \ - CONFIG_SYS_DFU_DATA_BUF_SIZE + \ - CONFIG_SYS_DFU_MAX_FILE_SIZE) -#else -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ -#endif - -#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ - -#ifndef CONFIG_SPL_BUILD -#ifndef BOOT_TARGET_DEVICES -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -#endif -#include -#else -#define BOOTENV -#endif - -#ifdef CONFIG_TEGRA_KEYBOARD -#define STDIN_KBD_KBC ",tegra-kbc" -#else -#define STDIN_KBD_KBC "" -#endif - -#ifdef CONFIG_USB_KEYBOARD -#define STDIN_KBD_USB ",usbkbd" -#else -#define STDIN_KBD_USB "" -#endif - -#ifdef CONFIG_LCD -#define STDOUT_LCD ",lcd" -#else -#define STDOUT_LCD "" -#endif - -#ifdef CONFIG_DM_VIDEO -#define STDOUT_VIDEO ",vidconsole" -#else -#define STDOUT_VIDEO "" -#endif - -#ifdef CONFIG_CROS_EC_KEYB -#define STDOUT_CROS_EC ",cros-ec-keyb" -#else -#define STDOUT_CROS_EC "" -#endif - -#define TEGRA_DEVICE_SETTINGS \ - "stdin=serial" STDIN_KBD_KBC STDIN_KBD_USB STDOUT_CROS_EC "\0" \ - "stdout=serial" STDOUT_LCD STDOUT_VIDEO "\0" \ - "stderr=serial" STDOUT_LCD STDOUT_VIDEO "\0" \ - "" - -#ifndef BOARD_EXTRA_ENV_SETTINGS -#define BOARD_EXTRA_ENV_SETTINGS -#endif - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#ifndef CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS -#define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS -#endif - -#ifdef CONFIG_ARM64 -#define FDT_HIGH "ffffffffffffffff" -#define INITRD_HIGH "ffffffffffffffff" -#else -#define FDT_HIGH "ffffffff" -#define INITRD_HIGH "ffffffff" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - TEGRA_DEVICE_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ - "fdt_high=" FDT_HIGH "\0" \ - "initrd_high=" INITRD_HIGH "\0" \ - BOOTENV \ - BOARD_EXTRA_ENV_SETTINGS \ - CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS - -#if defined(CONFIG_TEGRA20_SFLASH) || defined(CONFIG_TEGRA20_SLINK) || defined(CONFIG_TEGRA114_SPI) -#define CONFIG_TEGRA_SPI -#endif - -/* overrides for SPL build here */ -#ifdef CONFIG_SPL_BUILD - -#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY - -/* remove I2C support */ -#ifdef CONFIG_SYS_I2C_TEGRA -#undef CONFIG_SYS_I2C_TEGRA -#endif - -/* remove USB */ -#ifdef CONFIG_USB_EHCI_TEGRA -#undef CONFIG_USB_EHCI_TEGRA -#endif - -#endif /* CONFIG_SPL_BUILD */ - -#endif /* __TEGRA_COMMON_POST_H */ diff --git a/include/configs/tegra-common-usb-gadget.h b/include/configs/tegra-common-usb-gadget.h deleted file mode 100644 index e6b61c4..0000000 --- a/include/configs/tegra-common-usb-gadget.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2014 - * NVIDIA Corporation - */ - -#ifndef _TEGRA_COMMON_USB_GADGET_H_ -#define _TEGRA_COMMON_USB_GADGET_H_ - -#ifndef CONFIG_SPL_BUILD -/* USB gadget mode support*/ -#ifndef CONFIG_TEGRA20 -#define CONFIG_CI_UDC_HAS_HOSTPC -#endif -/* DFU protocol */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M -#define CONFIG_SYS_DFU_MAX_FILE_SIZE SZ_32M -#endif - -#endif /* _TEGRA_COMMON_USB_GADGET_H_ */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h deleted file mode 100644 index 84f671d..0000000 --- a/include/configs/tegra-common.h +++ /dev/null @@ -1,85 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef _TEGRA_COMMON_H_ -#define _TEGRA_COMMON_H_ -#include -#include - -/* - * High Level Configuration Options - */ -#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ - -#include /* get chip and board defs */ - -/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ -#ifndef CONFIG_ARM64 -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE -#endif - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ - -/* Environment */ -#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * Common HW configuration. - * If this varies between SoCs later, move to tegraNN-common.h - * Note: This is number of devices, not max device ID. - */ -#define CONFIG_SYS_MMC_MAX_DEVICE 4 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * Increasing the size of the IO buffer as default nfsargs size is more - * than 256 and so it is not possible to edit it - */ -#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max number of command args */ - -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ - -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ - -#ifndef CONFIG_ARM64 -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#endif - -#ifndef CONFIG_ARM64 -/* Defines for SPL */ -#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ - CONFIG_SPL_TEXT_BASE) -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 -#endif - -#endif /* _TEGRA_COMMON_H_ */ diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h deleted file mode 100644 index d3a7045..0000000 --- a/include/configs/tegra114-common.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. - */ - -#ifndef _TEGRA114_COMMON_H_ -#define _TEGRA114_COMMON_H_ -#include "tegra-common.h" - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * pxefile_addr_r can be pretty much anywhere that doesn't conflict with - * something else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 32M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for - * the compressed kernel to be up to 32M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define CONFIG_LOADADDR 0x81000000 -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x83000000\0" \ - "ramdisk_addr_r=0x83100000\0" - -/* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -#endif /* _TEGRA114_COMMON_H_ */ diff --git a/include/configs/tegra124-common.h b/include/configs/tegra124-common.h deleted file mode 100644 index 522993b..0000000 --- a/include/configs/tegra124-common.h +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * NVIDIA Corporation - */ - -#ifndef _TEGRA124_COMMON_H_ -#define _TEGRA124_COMMON_H_ - -#include "tegra-common.h" - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * pxefile_addr_r can be pretty much anywhere that doesn't conflict with - * something else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 32M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for - * the compressed kernel to be up to 32M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define CONFIG_LOADADDR 0x81000000 -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x83000000\0" \ - "ramdisk_addr_r=0x83100000\0" - -/* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -/* GPU needs setup */ -#define CONFIG_TEGRA_GPU - -#endif /* _TEGRA124_COMMON_H_ */ diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h deleted file mode 100644 index b4936cc..0000000 --- a/include/configs/tegra186-common.h +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright 2013-2016, NVIDIA CORPORATION. - */ - -#ifndef _TEGRA186_COMMON_H_ -#define _TEGRA186_COMMON_H_ - -#include "tegra-common.h" - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -/* Generic Interrupt Controller */ -#define CONFIG_GICV2 - -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * pxefile_addr_r can be pretty much anywhere that doesn't conflict with - * something else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 16M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for - * the compressed kernel to be up to 16M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define CONFIG_LOADADDR 0x80080000 -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" - -#endif diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h deleted file mode 100644 index 1e31d82..0000000 --- a/include/configs/tegra20-common.h +++ /dev/null @@ -1,86 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef _TEGRA20_COMMON_H_ -#define _TEGRA20_COMMON_H_ -#include "tegra-common.h" - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_STACKBASE 0x03800000 /* 56MB */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ - -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * pxefile_addr_r can be pretty much anywhere that doesn't conflict with - * something else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 32M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for - * the compressed kernel to be up to 32M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define CONFIG_LOADADDR 0x01000000 -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x10000000\0" \ - "pxefile_addr_r=0x10100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x03000000\0" \ - "ramdisk_addr_r=0x03100000\0" - -/* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 -#define CONFIG_SPL_STACK 0x000ffffc - -/* Align LCD to 1MB boundary */ -#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE - -#ifdef CONFIG_TEGRA_LP0 -#define TEGRA_LP0_ADDR 0x1C406000 -#define TEGRA_LP0_SIZE 0x2000 -#define TEGRA_LP0_VEC \ - "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ - "@" __stringify(TEGRA_LP0_ADDR) " " -#else -#define TEGRA_LP0_VEC -#endif - -/* - * This parameter affects a TXFILLTUNING field that controls how much data is - * sent to the latency fifo before it is sent to the wire. Without this - * parameter, the default (2) causes occasional Data Buffer Errors in OUT - * packets depending on the buffer address and size. - */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 -#define CONFIG_EHCI_IS_TDI - -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#endif /* _TEGRA20_COMMON_H_ */ diff --git a/include/configs/tegra210-common.h b/include/configs/tegra210-common.h deleted file mode 100644 index 1c53311..0000000 --- a/include/configs/tegra210-common.h +++ /dev/null @@ -1,59 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2015 - * NVIDIA Corporation - */ - -#ifndef _TEGRA210_COMMON_H_ -#define _TEGRA210_COMMON_H_ - -#include "tegra-common.h" - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ - -/* Generic Interrupt Controller */ -#define CONFIG_GICV2 - -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * pxefile_addr_r can be pretty much anywhere that doesn't conflict with - * something else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 16M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for - * the compressed kernel to be up to 16M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define CONFIG_LOADADDR 0x80080000 -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x82000000\0" \ - "ramdisk_addr_r=0x82100000\0" - -/* For USB EHCI controller */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -/* GPU needs setup */ -#define CONFIG_TEGRA_GPU - -#endif /* _TEGRA210_COMMON_H_ */ diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h deleted file mode 100644 index 54bc675..0000000 --- a/include/configs/tegra30-common.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef _TEGRA30_COMMON_H_ -#define _TEGRA30_COMMON_H_ -#include "tegra-common.h" - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_STACKBASE 0x83800000 /* 56MB */ - -/* - * Memory layout for where various images get loaded by boot scripts: - * - * scriptaddr can be pretty much anywhere that doesn't conflict with something - * else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * pxefile_addr_r can be pretty much anywhere that doesn't conflict with - * something else. Put it above BOOTMAPSZ to eliminate conflicts. - * - * kernel_addr_r must be within the first 128M of RAM in order for the - * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will - * decompress itself to 0x8000 after the start of RAM, kernel_addr_r - * should not overlap that area, or the kernel will have to copy itself - * somewhere else before decompression. Similarly, the address of any other - * data passed to the kernel shouldn't overlap the start of RAM. Pushing - * this up to 32M allows for a sizable kernel to be decompressed below the - * compressed load address. - * - * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for - * the compressed kernel to be up to 32M too. - * - * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows - * for the FDT/DTB to be up to 1M, which is hopefully plenty. - */ -#define CONFIG_LOADADDR 0x81000000 -#define MEM_LAYOUT_ENV_SETTINGS \ - "scriptaddr=0x90000000\0" \ - "pxefile_addr_r=0x90100000\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdt_addr_r=0x83000000\0" \ - "ramdisk_addr_r=0x83100000\0" - -/* Defines for SPL */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80090000 -#define CONFIG_SPL_STACK 0x800ffffc - -/* For USB EHCI controller */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 - -#endif /* _TEGRA30_COMMON_H_ */ diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h deleted file mode 100644 index 0c563e7..0000000 --- a/include/configs/theadorable-x86-common.h +++ /dev/null @@ -1,152 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Stefan Roese - */ - -/* - * Common options, macros and default environment for all - * theadorable x86 based boards - */ - -#ifndef __THEADORABLE_X86_COMMON_H -#define __THEADORABLE_X86_COMMON_H - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO -#define CONFIG_CMD_BMP -#define CONFIG_BMP_16BPP - -/* Environment settings */ -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x006ec000 -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) - -#undef CONFIG_BOOTCOMMAND -#undef CONFIG_EXTRA_ENV_SETTINGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "tftpdir=" DEF_ENV_TFTPDIR "\0" \ - "eth_init=" DEF_ENV_ETH_INIT "\0" \ - "ubuntu_part=" __stringify(DEF_ENV_UBUNTU_PART) "\0" \ - "yocto_part=" __stringify(DEF_ENV_YOCTO_PART) "\0" \ - "ubuntu_tty=" __stringify(DEF_ENV_UBUNTU_TTY) "\0" \ - "yocto_tty=" __stringify(DEF_ENV_YOCTO_TTY) "\0" \ - "start_eth=if test -n \"${eth_init}\";" \ - "then run eth_init;else sleep 0;fi\0" \ - "kernel-ver=4.8.0-54-generic\0" \ - "boot=zboot 03000000 0 04000000 ${filesize}\0" \ - "mtdparts=mtdparts=intel-spi:4k(descriptor),7084k(me)," \ - "8k(env1),8k(env2),64k(mrc),640k(u-boot)," \ - "64k(vga),-(fsp)\0" \ - "addtty_ubuntu=setenv bootargs ${bootargs} " \ - "console=ttyS${ubuntu_tty},${baudrate}\0" \ - "addtty_yocto=setenv bootargs ${bootargs} " \ - "console=ttyS${yocto_tty},${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addmisc=setenv bootargs ${bootargs} " \ - "intel-spi.writeable=1 vmalloc=300M " \ - "pci=realloc=on,hpmemsize=0,hpiosize=0\0" \ - "bootcmd=if env exists recovery_status;" \ - "then run swupdate;" \ - "else run yocto_boot;run swupdate;" \ - "fi\0" \ - "setroot=part uuid scsi 0:${partnr} uuid;" \ - "setenv root PARTUUID=${uuid}\0" \ - "setroot_ubuntu=setenv partnr ${ubuntu_part};run setroot\0" \ - "setroot_yocto=setenv partnr ${yocto_part};run setroot\0" \ - "ubuntu_args=setenv bootargs " \ - "root=${root} ro\0" \ - "ubuntu_args_quiet=setenv bootargs " \ - "root=${root} ro quiet\0" \ - "ubuntu_load=load scsi 0:${ubuntu_part} 03000000 " \ - "/boot/vmlinuz-${kernel-ver};" \ - "load scsi 0:${ubuntu_part} 04000000 " \ - "/boot/initrd.img-${kernel-ver}\0" \ - "ubuntu_boot=run setroot_ubuntu ubuntu_args_quiet " \ - "addmtd addmisc ubuntu_load boot\0" \ - "ubuntu_boot_console=run setroot_ubuntu ubuntu_args " \ - "addtty_ubuntu addmtd addmisc ubuntu_load boot\0" \ - "net_args=setenv bootargs root=${root} ro\0" \ - "net_boot=run start_eth setroot_ubuntu net_args " \ - "addtty_ubuntu addmtd addmisc;" \ - "tftp 03000000 ${tftpdir}/bzImage;" \ - "load scsi 0:${ubuntu_part} 04000000 " \ - "/boot/initrd.img-${kernel-ver};" \ - "run boot\0" \ - "yocto_args=setenv bootargs root=${root} " \ - "panic=1\0" \ - "yocto_args_fast=setenv bootargs root=${root} " \ - "quiet panic=1\0" \ - "yocto_boot=run setroot_yocto yocto_args addmtd addmisc " \ - "addtty_yocto;" \ - "if run yocto_load;then zboot 03000000;fi\0" \ - "yocto_boot_fast=run setroot_yocto yocto_args_fast addmtd " \ - "addmisc addtty_yocto yocto_load;zboot 03000000\0" \ - "yocto_boot_tftp=run setroot_yocto yocto_args addmtd " \ - "addmisc addtty_yocto " \ - "start_eth yocto_load_tftp;zboot 03000000\0" \ - "yocto_kernel=bzImage\0" \ - "yocto_load=load scsi 0:${yocto_part} 03000000 " \ - "/boot/${yocto_kernel}\0" \ - "yocto_load_tftp=tftp 03000000 dfi/bzImage\0" \ - "swupdate=if env exists swupdate_factory;" \ - "then run swupdate_usb;run swupdate_run;" \ - "else setenv swupdate_part 2;run swupdate_mmc;" \ - "run swupdate_run;setenv swupdate_part 1;" \ - "run swupdate_mmc;run swupdate_usb;" \ - "run swupdate_run;" \ - "fi\0" \ - "swupdate-initrd=/boot/swupdate-image-theadorable.ext4.gz\0" \ - "swupdate-kernel=/boot/bzImage\0" \ - "swupdate_args=setenv bootargs root=/dev/ram rw panic=1\0" \ - "swupdate_dev=0\0" \ - "swupdate_factory=0\0" \ - "swupdate_interface=usb\0" \ - "swupdate_kernel=vmlinuz-4.4.0-28-generic\0" \ - "swupdate_load=load ${swupdate_interface} ${swupdate_dev}:" \ - "${swupdate_part} 03000000 ${swupdate-kernel}" \ - " && load ${swupdate_interface} ${swupdate_dev}:" \ - "${swupdate_part} 04000000 ${swupdate-initrd}\0" \ - "swupdate_mmc=setenv swupdate_interface mmc;" \ - "setenv swupdate_dev ${swupdate_mmcdev};" \ - "setenv swupdate_part 1;" \ - "mmc dev ${swupdate_dev};mmc rescan\0" \ - "swupdate_mmcdev=0\0" \ - "swupdate_part=1\0" \ - "swupdate_run=run swupdate_args addtty_yocto addmtd addmisc;" \ - "if run swupdate_load;then run boot;" \ - "else echo SWUpdate cannot be started from " \ - "${swupdate_interface};" \ - "fi\0" \ - "swupdate_usb=setenv swupdate_interface usb;" \ - "setenv swupdate_dev 0;setenv swupdate_part 1;" \ - "usb start\0" \ - "logo_tftp=tftp ${loadaddr} ${tftpdir}/logo.bmp;" \ - "bmp display ${loadaddr}\0" \ - "preboot=scsi scan;load scsi 0:${ubuntu_part} ${loadaddr} " \ - "/boot/logo/logo.bmp;bmp display ${loadaddr}\0" \ - "rootpath=/tftpboot/theadorable-x86-conga/work/" \ - "rootfs-yocto-swupdate-2017-03-29\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:" \ - "${gatewayip}:${netmask}:${hostname}:eth0:off\0" \ - "set_bootargs_nfs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},tcp,nfsvers=3\0" \ - "net_nfs=run start_eth set_bootargs_nfs addtty_yocto addip " \ - "addmtd addmisc;tftp 03000000 ${tftpdir}/bzImage;" \ - "zboot 03000000\0" \ - "load_uboot=tftp ${loadaddr} ${tftpdir}/u-boot.rom\0" \ - "update_uboot=sf probe;" \ - "sf update ${loadaddr} 0 800000;saveenv\0" \ - "upd_uboot=run start_eth load_uboot update_uboot\0" - -#endif /* __THEADORABLE_X86_COMMON_H */ diff --git a/include/configs/theadorable-x86-conga-qa3-e3845.h b/include/configs/theadorable-x86-conga-qa3-e3845.h deleted file mode 100644 index 1c4362d..0000000 --- a/include/configs/theadorable-x86-conga-qa3-e3845.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Stefan Roese - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* Set the board specific parameters */ -#define DEF_ENV_TFTPDIR "theadorable-x86-conga" -#define DEF_ENV_ETH_INIT "" -#define DEF_ENV_UBUNTU_PART 2 -#define DEF_ENV_UBUNTU_TTY 0 /* Use ttyS0 */ -#define DEF_ENV_YOCTO_PART 3 -#define DEF_ENV_YOCTO_TTY 0 /* Use ttyS0 */ - -/* - * Include the theadorable-x86 common options, macros and default - * environment - */ -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/theadorable-x86-dfi-bt700.h b/include/configs/theadorable-x86-dfi-bt700.h deleted file mode 100644 index bb3186e..0000000 --- a/include/configs/theadorable-x86-dfi-bt700.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Stefan Roese - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* Use BayTrail internal HS UART which is memory-mapped */ -#undef CONFIG_SYS_NS16550_PORT_MAPPED - -/* Set the board specific parameters */ -#define DEF_ENV_TFTPDIR "theadorable-x86-dfi" -#define DEF_ENV_ETH_INIT "usb reset" -#define DEF_ENV_UBUNTU_PART 1 -#define DEF_ENV_UBUNTU_TTY 4 /* Use ttyS4 */ -#define DEF_ENV_YOCTO_PART 2 -#define DEF_ENV_YOCTO_TTY 1 /* Use ttyS1 */ - -/* - * Include the theadorable-x86 common options, macros and default - * environment - */ -#include - -#endif /* __CONFIG_H */ diff --git a/include/configs/theadorable.h b/include/configs/theadorable.h deleted file mode 100644 index 45cd7e2..0000000 --- a/include/configs/theadorable.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015-2016 Stefan Roese - */ - -#ifndef _CONFIG_THEADORABLE_H -#define _CONFIG_THEADORABLE_H - -/* - * High Level Configuration Options (easy to change) - */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* - * Commands configuration - */ - -/* - * The debugging version enables USB support via defconfig. - * This version should also enable all other non-production - * interfaces / features. - */ - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MVTWSI -#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE -#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_MAX_CONTROLLER_COUNT 3 - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ -#define CONFIG_ENV_OVERWRITE - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -/* SATA support */ -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_LBA48 - -/* Enable LCD and reserve 512KB from top of memory*/ -#define CONFIG_SYS_MEM_TOP_HIDE 0x80000 - -#define CONFIG_BMP_16BPP -#define CONFIG_BMP_24BPP -#define CONFIG_BMP_32BPP - -/* FPGA programming support */ -#define CONFIG_FPGA_STRATIX_V - -/* - * Bootcounter - */ -/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ -#define BOOTCOUNT_ADDR 0x1000 - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* - * Memory layout while starting into the bin_hdr via the - * BootROM: - * - * 0x4000.4000 - 0x4003.4000 headers space (192KiB) - * 0x4000.4030 bin_hdr start address - * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) - * 0x4007.fffc BootROM stack top - * - * The address space between 0x4007.fffc and 0x400f.fff is not locked in - * L2 cache thus cannot be used. - */ - -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS - -/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ -#define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ - -#endif /* _CONFIG_THEADORABLE_H */ diff --git a/include/configs/thuban.h b/include/configs/thuban.h deleted file mode 100644 index 569df9e..0000000 --- a/include/configs/thuban.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Siemens Schweiz AG - * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * U-Boot file:/include/configs/am335x_evm.h - * - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - */ - -#ifndef __CONFIG_THUBAN_H -#define __CONFIG_THUBAN_H - -#include "siemens-am33x-common.h" - -#define DDR_PLL_FREQ 303 - -#define BOARD_DFU_BUTTON_GPIO 27 /* Use as default */ -#define GPIO_LAN9303_NRST 88 /* GPIO2_24 = gpio88 */ - -#define CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - "button_dfu0=27\0" \ - "led0=103,1,0\0" \ - "led1=64,0,1\0" - - /* Physical Memory Map */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ - -/* I2C Configuration */ -#define CONFIG_SYS_I2C_SPEED 100000 - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define EEPROM_ADDR_DDR3 0x90 -#define EEPROM_ADDR_CHIP 0x120 - -#define CONFIG_PHY_SMSC - -#define CONFIG_FACTORYSET - -/* Define own nand partitions */ -#define CONFIG_ENV_OFFSET_REDUND 0x2E0000 -#define CONFIG_ENV_SIZE_REDUND 0x2000 -#define CONFIG_ENV_RANGE (4 * CONFIG_SYS_ENV_SECT_SIZE) - -#ifndef CONFIG_SPL_BUILD - -/* Default env settings */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "hostname=thuban\0" \ - "ubi_off=2048\0"\ - "nand_img_size=0x400000\0" \ - "optargs=\0" \ - "preboot=draco_led 0\0" \ - CONFIG_ENV_SETTINGS_BUTTONS_AND_LEDS \ - CONFIG_ENV_SETTINGS_V2 \ - CONFIG_ENV_SETTINGS_NAND_V2 - -#ifndef CONFIG_RESTORE_FLASH -/* set to negative value for no autoboot */ - -#define CONFIG_BOOTCOMMAND \ -"if dfubutton; then " \ - "run dfu_start; " \ - "reset; " \ -"fi;" \ -"run nand_boot;" \ -"run nand_boot_backup;" \ -"reset;" - -#else - -#define CONFIG_BOOTCOMMAND \ - "setenv autoload no; " \ - "dhcp; " \ - "if tftp 80000000 debrick.scr; then " \ - "source 80000000; " \ - "fi" -#endif -#endif /* CONFIG_SPL_BUILD */ -#endif /* ! __CONFIG_THUBAN_H */ diff --git a/include/configs/thunderx_88xx.h b/include/configs/thunderx_88xx.h deleted file mode 100644 index 619571d..0000000 --- a/include/configs/thunderx_88xx.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/** - * (C) Copyright 2014, Cavium Inc. -**/ - -#ifndef __THUNDERX_88XX_H__ -#define __THUNDERX_88XX_H__ - -#define CONFIG_REMAKE_ELF - -#define CONFIG_THUNDERX - -#define CONFIG_SYS_64BIT - -#define MEM_BASE 0x00500000 - -#define CONFIG_SYS_LOWMEM_BASE MEM_BASE - -/* Link Definitions */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -/* SMP Spin Table Definitions */ -#define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ - -#define CONFIG_SYS_MEMTEST_START MEM_BASE -#define CONFIG_SYS_MEMTEST_END (MEM_BASE + PHYS_SDRAM_1_SIZE) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* PL011 Serial Configuration */ - -#define CONFIG_PL011_CLOCK 24000000 - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE (0x801000000000) -#define GICR_BASE (0x801000002000) -#define CONFIG_SYS_SERIAL0 0x87e024000000 -#define CONFIG_SYS_SERIAL1 0x87e025000000 - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (MEM_BASE) - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 (MEM_BASE) /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE (0x80000000-MEM_BASE) /* 2048 MB */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Initial environment variables */ -#define UBOOT_IMG_HEAD_SIZE 0x40 -/* C80000 - 0x40 */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_addr=08007ffc0\0" \ - "fdt_addr=0x94C00000\0" \ - "fdt_high=0x9fffffff\0" - -/* Do not preserve environment */ -#define CONFIG_ENV_SIZE 0x1000 - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ -#define CONFIG_NO_RELOCATION 1 -#define PLL_REF_CLK 50000000 /* 50 MHz */ -#define NS_PER_REF_CLK_TICK (1000000000/PLL_REF_CLK) - -#endif /* __THUNDERX_88XX_H__ */ diff --git a/include/configs/ti814x_evm.h b/include/configs/ti814x_evm.h deleted file mode 100644 index 46b1b41..0000000 --- a/include/configs/ti814x_evm.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * ti814x_evm.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __CONFIG_TI814X_EVM_H -#define __CONFIG_TI814X_EVM_H - -#include - -#define CONFIG_SYS_MALLOC_LEN (1024 << 10) -#define CONFIG_MACH_TYPE MACH_TYPE_TI8148EVM - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG /* for ramdisk support */ - -/* commands to include */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x80200000\0" \ - "fdtaddr=0x80F80000\0" \ - "rdaddr=0x81000000\0" \ - "bootfile=/boot/uImage\0" \ - "fdtfile=\0" \ - "console=ttyO0,115200n8\0" \ - "optargs=\0" \ - "mmcdev=0\0" \ - "mmcroot=/dev/mmcblk0p2 ro\0" \ - "mmcrootfstype=ext4 rootwait\0" \ - "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ - "ramrootfstype=ext2\0" \ - "mmcargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${mmcroot} " \ - "rootfstype=${mmcrootfstype}\0" \ - "bootenv=uEnv.txt\0" \ - "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \ - "importbootenv=echo Importing environment from mmc ...; " \ - "env import -t $loadaddr $filesize\0" \ - "ramargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=${ramroot} " \ - "rootfstype=${ramrootfstype}\0" \ - "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ - "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \ - "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "ramboot=echo Booting from ramdisk ...; " \ - "run ramargs; " \ - "bootm ${loadaddr}\0" \ - "fdtfile=ti814x-evm.dtb\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "echo SD/MMC found on device ${mmcdev};" \ - "if run loadbootenv; then " \ - "echo Loaded environment from ${bootenv};" \ - "run importbootenv;" \ - "fi;" \ - "if test -n $uenvcmd; then " \ - "echo Running uenvcmd ...;" \ - "run uenvcmd;" \ - "fi;" \ - "if run loaduimage; then " \ - "run mmcboot;" \ - "fi;" \ - "fi;" \ - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 512 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START \ - + PHYS_DRAM_1_SIZE - (8 << 12)) - -#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default */ - -/** - * Physical Memory Map - */ -#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */ -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */ - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -/** - * Platform/Board specific defs - */ -#define CONFIG_SYS_TIMERBASE 0x4802E000 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */ - -/* CPU */ - -#define CONFIG_ENV_OVERWRITE - -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ - -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000 - -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80800000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* Ethernet */ -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#define CONFIG_PHY_ET1011C -#define CONFIG_PHY_ET1011C_TX_CLK_FIX - -#endif /* ! __CONFIG_TI814X_EVM_H */ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h deleted file mode 100644 index fc5608b..0000000 --- a/include/configs/ti816x_evm.h +++ /dev/null @@ -1,115 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ti816x_evm.h - * - * Copyright (C) 2013, Adeneo Embedded - * Antoine Tenart, - */ - -#ifndef __CONFIG_TI816X_EVM_H -#define __CONFIG_TI816X_EVM_H - -#include -#include - -#define CONFIG_ENV_SIZE 0x2000 -#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan;" \ - "fatload mmc 0 ${loadaddr} uImage;" \ - "bootm ${loadaddr}" \ - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMD_ASKENV - -#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -/** - * Platform/Board specific defs - */ -#define CONFIG_SYS_CLK_FREQ 27000000 -#define CONFIG_SYS_TIMERBASE 0x4802E000 -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK (48000000) -#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ - -/* allow overwriting serial config and ethaddr */ -#define CONFIG_ENV_OVERWRITE - - -/* - * GPMC NAND block. We support 1 device and the physical address to - * access CS0 at is 0x8000000. - */ -#define CONFIG_SYS_NAND_BASE 0x8000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -/* NAND: SPL related configs */ - -/* NAND: device related configs */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ - CONFIG_SYS_NAND_PAGE_SIZE) -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -/* NAND: driver related configs */ -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 14 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x000c0000 -#define CONFIG_ENV_OFFSET 0x001c0000 -#define CONFIG_ENV_OFFSET_REDUND 0x001e0000 -#define CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE - -/* SPL */ -/* Defines for SPL */ -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 - -/* Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * Disable MMC DM for SPL build and can be re-enabled after adding - * DM support in SPL - */ -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_MMC -#undef CONFIG_TIMER -#endif -#endif diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h deleted file mode 100644 index 19e1e22..0000000 --- a/include/configs/ti_am335x_common.h +++ /dev/null @@ -1,64 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ti_am335x_common.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * For more details, please see the technical documents listed at - * http://www.ti.com/product/am3359#technicaldocuments - */ - -#ifndef __CONFIG_TI_AM335X_COMMON_H__ -#define __CONFIG_TI_AM335X_COMMON_H__ - -#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ -#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ - -#include - -/* NS16550 Configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_SERIAL -#ifndef CONFIG_DM_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif -#endif -#define CONFIG_SYS_NS16550_CLK 48000000 - -#ifndef CONFIG_SPL_BUILD -/* Network defines. */ -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 10 -#endif - -/* - * SPL related defines. The Public RAM memory map the ROM defines the - * area between 0x402F0400 and 0x4030B800 as a download area and - * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also - * supports X-MODEM loading via UART, and we leverage this and then use - * Y-MODEM to load u-boot.img, when booted over UART. - */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) - -/* Enable the watchdog inside of SPL */ - -/* - * Since SPL did pll and ddr initialization for us, - * we don't need to do it twice. - */ -#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * When building U-Boot such that there is no previous loader - * we need to call board_early_init_f. This is taken care of in - * s_init when we have SPL used. - */ - -/* Now bring in the rest of the common code. */ -#include - -#endif /* __CONFIG_TI_AM335X_COMMON_H__ */ diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h deleted file mode 100644 index 6d15304..0000000 --- a/include/configs/ti_armv7_common.h +++ /dev/null @@ -1,211 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ti_armv7_common.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * The various ARMv7 SoCs from TI all share a number of IP blocks when - * implementing a given feature. Rather than define these in every - * board or even SoC common file, we define a common file to be re-used - * in all cases. While technically true that some of these details are - * configurable at the board design, they are common throughout SoC - * reference platforms as well as custom designs and become de facto - * standards. - */ - -#ifndef __CONFIG_TI_ARMV7_COMMON_H__ -#define __CONFIG_TI_ARMV7_COMMON_H__ - -/* Support both device trees and ATAGs. */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Our DDR memory always starts at 0x80000000 and U-Boot shall have - * relocated itself to higher in memory by the time this value is used. - * However, set this to a 32MB offset to allow for easier Linux kernel - * booting as the default is often used as the kernel load address. - */ -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -/* - * We setup defaults based on constraints from the Linux kernel, which should - * also be safe elsewhere. We have the default load at 32MB into DDR (for - * the kernel), FDT above 128MB (the maximum location for the end of the - * kernel), and the ramdisk 512KB above that (allowing for hopefully never - * seen large trees). We say all of this must be within the first 256MB - * as that will normally be within the kernel lowmem and thus visible via - * bootm_size and we only run on platforms with 256MB or more of memory. - */ -#define DEFAULT_LINUX_BOOT_ENV \ - "loadaddr=0x82000000\0" \ - "kernel_addr_r=0x82000000\0" \ - "fdtaddr=0x88000000\0" \ - "fdt_addr_r=0x88000000\0" \ - "rdaddr=0x88080000\0" \ - "ramdisk_addr_r=0x88080000\0" \ - "scriptaddr=0x80000000\0" \ - "pxefile_addr_r=0x80100000\0" \ - "bootm_size=0x10000000\0" \ - "boot_fdt=try\0" - -#define DEFAULT_FIT_TI_ARGS \ - "boot_fit=0\0" \ - "addr_fit=0x90000000\0" \ - "name_fit=fitImage\0" \ - "update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit}\0" \ - "get_overlaystring=" \ - "for overlay in $overlay_files;" \ - "do;" \ - "setenv overlaystring ${overlaystring}'#'${overlay};" \ - "done;\0" \ - "run_fit=bootm ${addr_fit}#${fdtfile}${overlaystring}\0" \ - "loadfit=run args_mmc; run run_fit;\0" \ - -/* - * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined, - * we say (for simplicity) that we have 1 bank, always, even when - * we have more. We always start at 0x80000000, and we place the - * initial stack pointer in our SRAM. Otherwise, we can define - * CONFIG_NR_DRAM_BANKS before including this file. - */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 - -#ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) -#endif - -/* Timer information. */ -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* If DM_I2C, enable non-DM I2C support */ -#if !defined(CONFIG_DM_I2C) -#define CONFIG_I2C -#define CONFIG_SYS_I2C -#endif - -/* - * The following are general good-enough settings for U-Boot. We set a - * large malloc pool as we generally have a lot of DDR, and we opt for - * function over binary size in the main portion of U-Boot as this is - * generally easily constrained later if needed. We enable the config - * options that give us information in the environment about what board - * we are on so we do not need to rely on the command prompt. We set a - * console baudrate of 115200 and use the default baud rate table. - */ -#define CONFIG_SYS_MALLOC_LEN SZ_32M -#define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ - -/* As stated above, the following choices are optional. */ - -/* We set the max number of command args high to avoid HUSH bugs. */ -#define CONFIG_SYS_MAXARGS 64 - -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * When we have SPI, NOR or NAND flash we expect to be making use of - * mtdparts, both for ease of use in U-Boot and for passing information - * on to the Linux kernel. - */ - -/* - * Our platforms make use of SPL to initalize the hardware (primarily - * memory) enough for full U-Boot to be loaded. We make use of the general - * SPL framework found under common/spl/. Given our generally common memory - * map, we set a number of related defaults and sizes here. - */ -#if !defined(CONFIG_NOR_BOOT) && \ - !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX)) - -/* - * We also support Falcon Mode so that the Linux kernel can be booted - * directly from SPL. This is not currently available on HS devices. - */ - -/* - * Place the image at the start of the ROM defined image space (per - * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined - * downloaded image area minus 1KiB for scratch space. We initalize DRAM as - * soon as we can so that we can place stack, malloc and BSS there. We load - * U-Boot itself into memory at 0x80800000 for legacy reasons (to not conflict - * with older SPLs). We have our BSS be placed 2MiB after this, to allow for - * the default Linux kernel address of 0x80008000 to work with most sized - * kernels, in the Falcon Mode case. We have the SPL malloc pool at the end - * of the BSS area. We suggest that the stack be placed at 32MiB after the - * start of DRAM to allow room for all of the above (handled in Kconfig). - */ -#ifndef CONFIG_SPL_BSS_START_ADDR -#define CONFIG_SPL_BSS_START_ADDR 0x80a00000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ -#endif -#ifndef CONFIG_SYS_SPL_MALLOC_START -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M -#endif -#ifndef CONFIG_SPL_MAX_SIZE -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) -#endif - - -/* FAT sd card locations. */ -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#ifndef CONFIG_SPL_FS_LOAD_PAYLOAD_NAME -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - -#ifdef CONFIG_SPL_OS_BOOT -/* FAT */ -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" - -/* RAW SD card / eMMC */ -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1700 /* address 0x2E0000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500 /* address 0x2A0000 */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200 /* 256KiB */ -#endif - -/* General parts of the framework, required. */ - -#ifdef CONFIG_NAND -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#endif -#endif /* !CONFIG_NOR_BOOT */ - -/* Generic Environment Variables */ - -#ifdef CONFIG_CMD_NET -#define NETARGS \ - "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ - "::off\0" \ - "nfsopts=nolock\0" \ - "rootpath=/export/rootfs\0" \ - "netloadimage=tftp ${loadaddr} ${bootfile}\0" \ - "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \ - "netargs=setenv bootargs console=${console} " \ - "${optargs} " \ - "root=/dev/nfs " \ - "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ - "ip=dhcp\0" \ - "netboot=echo Booting from network ...; " \ - "setenv autoload no; " \ - "dhcp; " \ - "run netloadimage; " \ - "run netloadfdt; " \ - "run netargs; " \ - "bootz ${loadaddr} - ${fdtaddr}\0" -#else -#define NETARGS "" -#endif - -#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */ diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h deleted file mode 100644 index ba12428..0000000 --- a/include/configs/ti_armv7_keystone2.h +++ /dev/null @@ -1,302 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Common configuration header file for all Keystone II EVM platforms - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, - */ - -#ifndef __CONFIG_KS2_EVM_H -#define __CONFIG_KS2_EVM_H - -#define CONFIG_SOC_KEYSTONE - -/* U-Boot Build Configuration */ -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage loader */ - -/* SoC Configuration */ -#define CONFIG_SPL_TARGET "u-boot-spi.gph" - -/* Memory Configuration */ -#define CONFIG_SYS_LPAE_SDRAM_BASE 0x800000000 -#define CONFIG_MAX_RAM_BANK_SIZE (2 << 30) /* 2GB */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_ISW_ENTRY_ADDR - \ - GENERATED_GBL_DATA_SIZE) - -#ifdef CONFIG_SYS_MALLOC_F_LEN -#define SPL_MALLOC_F_SIZE CONFIG_SYS_MALLOC_F_LEN -#else -#define SPL_MALLOC_F_SIZE 0 -#endif - -/* SPL SPI Loader Configuration */ -#define CONFIG_SPL_PAD_TO 65536 -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_PAD_TO - 8) -#define CONFIG_SPL_BSS_START_ADDR (CONFIG_ISW_ENTRY_ADDR + \ - CONFIG_SPL_MAX_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (32 * 1024) -#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ - CONFIG_SPL_BSS_MAX_SIZE) -#define CONFIG_SYS_SPL_MALLOC_SIZE (32 * 1024) -#define KEYSTONE_SPL_STACK_SIZE (8 * 1024) -#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START + \ - CONFIG_SYS_SPL_MALLOC_SIZE + \ - SPL_MALLOC_F_SIZE + \ - KEYSTONE_SPL_STACK_SIZE - 4) - -/* SRAM scratch space entries */ -#define SRAM_SCRATCH_SPACE_ADDR CONFIG_SPL_STACK + 0x8 - -#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR) -#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200) -#define KEYSTONE_SRAM_SCRATCH_SPACE_END (TI_SRAM_SCRATCH_BOARD_EEPROM_END) - -/* UART Configuration */ -#define CONFIG_SYS_NS16550_MEM32 -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#endif -#define CONFIG_SYS_NS16550_COM1 KS2_UART0_BASE -#define CONFIG_SYS_NS16550_COM2 KS2_UART1_BASE - -#ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(KS2_CLK1_6) -#else -#define CONFIG_SYS_NS16550_CLK ks_clk_get_rate(uart_pll_clk) / 2 -#endif - -/* SPI Configuration */ -#define CONFIG_SYS_SPI_CLK ks_clk_get_rate(KS2_CLK1_6) -#define CONFIG_SYS_SPI0 -#define CONFIG_SYS_SPI_BASE KS2_SPI0_BASE -#define CONFIG_SYS_SPI0_NUM_CS 4 -#define CONFIG_SYS_SPI1 -#define CONFIG_SYS_SPI1_BASE KS2_SPI1_BASE -#define CONFIG_SYS_SPI1_NUM_CS 4 -#define CONFIG_SYS_SPI2 -#define CONFIG_SYS_SPI2_BASE KS2_SPI2_BASE -#define CONFIG_SYS_SPI2_NUM_CS 4 -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH -#endif - -/* Network Configuration */ -#define CONFIG_BOOTP_DEFAULT -#define CONFIG_BOOTP_DNS2 -#define CONFIG_BOOTP_SEND_HOSTNAME -#define CONFIG_NET_RETRY_COUNT 32 -#define CONFIG_SYS_SGMII_REFCLK_MHZ 312 -#define CONFIG_SYS_SGMII_LINERATE_MHZ 1250 -#define CONFIG_SYS_SGMII_RATESCALE 2 - -/* Keyston Navigator Configuration */ -#define CONFIG_TI_KSNAV -#define CONFIG_KSNAV_QM_BASE_ADDRESS KS2_QM_BASE_ADDRESS -#define CONFIG_KSNAV_QM_CONF_BASE KS2_QM_CONF_BASE -#define CONFIG_KSNAV_QM_DESC_SETUP_BASE KS2_QM_DESC_SETUP_BASE -#define CONFIG_KSNAV_QM_STATUS_RAM_BASE KS2_QM_STATUS_RAM_BASE -#define CONFIG_KSNAV_QM_INTD_CONF_BASE KS2_QM_INTD_CONF_BASE -#define CONFIG_KSNAV_QM_PDSP1_CMD_BASE KS2_QM_PDSP1_CMD_BASE -#define CONFIG_KSNAV_QM_PDSP1_CTRL_BASE KS2_QM_PDSP1_CTRL_BASE -#define CONFIG_KSNAV_QM_PDSP1_IRAM_BASE KS2_QM_PDSP1_IRAM_BASE -#define CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE KS2_QM_MANAGER_QUEUES_BASE -#define CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE KS2_QM_MANAGER_Q_PROXY_BASE -#define CONFIG_KSNAV_QM_QUEUE_STATUS_BASE KS2_QM_QUEUE_STATUS_BASE -#define CONFIG_KSNAV_QM_LINK_RAM_BASE KS2_QM_LINK_RAM_BASE -#define CONFIG_KSNAV_QM_REGION_NUM KS2_QM_REGION_NUM -#define CONFIG_KSNAV_QM_QPOOL_NUM KS2_QM_QPOOL_NUM - -/* NETCP pktdma */ -#define CONFIG_KSNAV_PKTDMA_NETCP -#define CONFIG_KSNAV_NETCP_PDMA_CTRL_BASE KS2_NETCP_PDMA_CTRL_BASE -#define CONFIG_KSNAV_NETCP_PDMA_TX_BASE KS2_NETCP_PDMA_TX_BASE -#define CONFIG_KSNAV_NETCP_PDMA_TX_CH_NUM KS2_NETCP_PDMA_TX_CH_NUM -#define CONFIG_KSNAV_NETCP_PDMA_RX_BASE KS2_NETCP_PDMA_RX_BASE -#define CONFIG_KSNAV_NETCP_PDMA_RX_CH_NUM KS2_NETCP_PDMA_RX_CH_NUM -#define CONFIG_KSNAV_NETCP_PDMA_SCHED_BASE KS2_NETCP_PDMA_SCHED_BASE -#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_BASE KS2_NETCP_PDMA_RX_FLOW_BASE -#define CONFIG_KSNAV_NETCP_PDMA_RX_FLOW_NUM KS2_NETCP_PDMA_RX_FLOW_NUM -#define CONFIG_KSNAV_NETCP_PDMA_RX_FREE_QUEUE KS2_NETCP_PDMA_RX_FREE_QUEUE -#define CONFIG_KSNAV_NETCP_PDMA_RX_RCV_QUEUE KS2_NETCP_PDMA_RX_RCV_QUEUE -#define CONFIG_KSNAV_NETCP_PDMA_TX_SND_QUEUE KS2_NETCP_PDMA_TX_SND_QUEUE - -/* Keystone net */ -#define CONFIG_KSNET_MAC_ID_BASE KS2_MAC_ID_BASE_ADDR -#define CONFIG_KSNET_NETCP_BASE KS2_NETCP_BASE -#define CONFIG_KSNET_SERDES_SGMII_BASE KS2_SGMII_SERDES_BASE -#define CONFIG_KSNET_SERDES_SGMII2_BASE KS2_SGMII_SERDES2_BASE -#define CONFIG_KSNET_SERDES_LANES_PER_SGMII KS2_LANES_PER_SGMII_SERDES - -#define CONFIG_AEMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE - -/* I2C Configuration */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED1 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE1 0x10 /* SMBus host address */ -#define CONFIG_SYS_DAVINCI_I2C_SPEED2 100000 -#define CONFIG_SYS_DAVINCI_I2C_SLAVE2 0x10 /* SMBus host address */ - -/* EEPROM definitions */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CONFIG_ENV_EEPROM_IS_ON_I2C - -/* NAND Configuration */ -#define CONFIG_KEYSTONE_RBL_NAND -#define CONFIG_KEYSTONE_NAND_MAX_RBL_SIZE CONFIG_ENV_OFFSET -#define CONFIG_SYS_NAND_MASK_CLE 0x4000 -#define CONFIG_SYS_NAND_MASK_ALE 0x2000 -#define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST - -#define CONFIG_SYS_NAND_LARGEPAGE -#define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_MAX_CHIPS 1 -#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE - -#define DFU_ALT_INFO_MMC \ - "dfu_alt_info_mmc=" \ - "MLO fat 0 1;" \ - "u-boot.img fat 0 1;" \ - "uEnv.txt fat 0 1\0" - -/* DFU settings */ -#define DFUARGS \ - "dfu_bufsiz=0x10000\0" \ - DFU_ALT_INFO_MMC \ - -/* U-Boot general configuration */ -#define CONFIG_TIMESTAMP - -/* EDMA3 */ -#define CONFIG_TI_EDMA3 - -#define KERNEL_MTD_PARTS \ - "mtdparts=" \ - SPI_MTD_PARTS - -#define DEFAULT_FW_INITRAMFS_BOOT_ENV \ - "name_fw_rd=k2-fw-initrd.cpio.gz\0" \ - "set_rd_spec=setenv rd_spec ${rdaddr}:${filesize}\0" \ - "init_fw_rd_net=dhcp ${rdaddr} ${tftp_root}/${name_fw_rd}; " \ - "run set_rd_spec\0" \ - "init_fw_rd_nfs=nfs ${rdaddr} ${nfs_root}/boot/${name_fw_rd}; " \ - "run set_rd_spec\0" \ - "init_fw_rd_ramfs=setenv rd_spec -\0" \ - "init_fw_rd_ubi=ubifsload ${rdaddr} ${bootdir}/${name_fw_rd}; " \ - "run set_rd_spec\0" \ - -#define DEFAULT_PMMC_BOOT_ENV \ - "set_name_pmmc=setenv name_pmmc ti-sci-firmware-${soc_variant}.bin\0" \ - "dev_pmmc=0\0" \ - "get_pmmc_net=dhcp ${loadaddr} ${tftp_root}/${name_pmmc}\0" \ - "get_pmmc_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_pmmc}\0" \ - "get_pmmc_ramfs=run get_pmmc_net\0" \ - "get_pmmc_mmc=load mmc ${bootpart} ${loadaddr} " \ - "${bootdir}/${name_pmmc}\0" \ - "get_pmmc_ubi=ubifsload ${loadaddr} ${bootdir}/${name_pmmc}\0" \ - "run_pmmc=rproc init; rproc list; " \ - "rproc load ${dev_pmmc} ${loadaddr} 0x${filesize}; " \ - "rproc start ${dev_pmmc}\0" \ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - CONFIG_EXTRA_ENV_KS2_BOARD_SETTINGS \ - DFUARGS \ - "bootdir=/boot\0" \ - "tftp_root=/\0" \ - "nfs_root=/export\0" \ - "mem_lpae=1\0" \ - "addr_ubi=0x82000000\0" \ - "addr_secdb_key=0xc000000\0" \ - "name_kern=zImage\0" \ - "addr_mon=0x87000000\0" \ - "addr_non_sec_mon=0x0c097fc0\0" \ - "addr_load_sec_bm=0x0c09c000\0" \ - "run_mon=mon_install ${addr_mon}\0" \ - "run_mon_hs=mon_install ${addr_non_sec_mon} " \ - "${addr_load_sec_bm}\0" \ - "run_kern=bootz ${loadaddr} ${rd_spec} ${fdtaddr}\0" \ - "init_net=run args_all args_net\0" \ - "init_nfs=setenv autoload no; dhcp; run args_all args_net\0" \ - "init_ubi=run args_all args_ubi; " \ - "ubi part ubifs; ubifsmount ubi:rootfs;\0" \ - "get_fdt_net=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ - "get_fdt_nfs=nfs ${fdtaddr} ${nfs_root}/boot/${name_fdt}\0" \ - "get_fdt_ubi=ubifsload ${fdtaddr} ${bootdir}/${name_fdt}\0" \ - "get_kern_net=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ - "get_kern_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_kern}\0" \ - "get_kern_ubi=ubifsload ${loadaddr} ${bootdir}/${name_kern}\0" \ - "get_mon_net=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_mon_nfs=nfs ${addr_mon} ${nfs_root}/boot/${name_mon}\0" \ - "get_mon_ubi=ubifsload ${addr_mon} ${bootdir}/${name_mon}\0" \ - "get_fit_net=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0" \ - "get_fit_nfs=nfs ${addr_fit} ${nfs_root}/boot/${name_fit}\0" \ - "get_fit_ubi=ubifsload ${addr_fit} ${bootdir}/${name_fit}\0" \ - "get_fit_mmc=load mmc ${bootpart} ${addr_fit} ${bootdir}/${name_fit}\0" \ - "get_uboot_net=dhcp ${loadaddr} ${tftp_root}/${name_uboot}\0" \ - "get_uboot_nfs=nfs ${loadaddr} ${nfs_root}/boot/${name_uboot}\0" \ - "burn_uboot_spi=sf probe; sf erase 0 0x100000; " \ - "sf write ${loadaddr} 0 ${filesize}\0" \ - "burn_uboot_nand=nand erase 0 0x100000; " \ - "nand write ${loadaddr} 0 ${filesize}\0" \ - "args_all=setenv bootargs console=ttyS0,115200n8 rootwait=1 " \ - KERNEL_MTD_PARTS \ - "args_net=setenv bootargs ${bootargs} rootfstype=nfs " \ - "root=/dev/nfs rw nfsroot=${serverip}:${nfs_root}," \ - "${nfs_options} ip=dhcp\0" \ - "nfs_options=v3,tcp,rsize=4096,wsize=4096\0" \ - "get_fdt_ramfs=dhcp ${fdtaddr} ${tftp_root}/${name_fdt}\0" \ - "get_kern_ramfs=dhcp ${loadaddr} ${tftp_root}/${name_kern}\0" \ - "get_mon_ramfs=dhcp ${addr_mon} ${tftp_root}/${name_mon}\0" \ - "get_fit_ramfs=dhcp ${addr_fit} ${tftp_root}/${name_fit}\0" \ - "get_fs_ramfs=dhcp ${rdaddr} ${tftp_root}/${name_fs}\0" \ - "get_ubi_net=dhcp ${addr_ubi} ${tftp_root}/${name_ubi}\0" \ - "get_ubi_nfs=nfs ${addr_ubi} ${nfs_root}/boot/${name_ubi}\0" \ - "burn_ubi=nand erase.part ubifs; " \ - "nand write ${addr_ubi} ubifs ${filesize}\0" \ - "init_ramfs=run args_all args_ramfs get_fs_ramfs\0" \ - "args_ramfs=setenv bootargs ${bootargs} " \ - "rdinit=/sbin/init rw root=/dev/ram0 " \ - "initrd=0x808080000,80M\0" \ - "no_post=1\0" \ - "mtdparts=mtdparts=davinci_nand.0:" \ - "1024k(bootloader)ro,512k(params)ro,-(ubifs)\0" - -#ifndef CONFIG_BOOTCOMMAND -#ifndef CONFIG_TI_SECURE_DEVICE -#define CONFIG_BOOTCOMMAND \ - "run init_${boot}; " \ - "run get_mon_${boot} run_mon; " \ - "run get_kern_${boot}; " \ - "run init_fw_rd_${boot}; " \ - "run get_fdt_${boot}; " \ - "run run_kern" -#else -#define CONFIG_BOOTCOMMAND \ - "run run_mon_hs; " \ - "run init_${boot}; " \ - "run get_fit_${boot}; " \ - "bootm ${addr_fit}#${name_fdt}" -#endif -#endif - -/* Now for the remaining common defines */ -#include - -/* we may include files below only after all above definitions */ -#include -#include -#ifndef CONFIG_SOC_K2G -#define CONFIG_SYS_HZ_CLOCK ks_clk_get_rate(KS2_CLK1_6) -#else -#define CONFIG_SYS_HZ_CLOCK get_external_clk(sys_clk) -#endif - -#endif /* __CONFIG_KS2_EVM_H */ diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h deleted file mode 100644 index 98b5839..0000000 --- a/include/configs/ti_armv7_omap.h +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ti_armv7_omap.h - * - * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ - * - * The various ARMv7 SoCs from TI all share a number of IP blocks when - * implementing a given feature. This is meant to isolate the features - * that are based on OMAP architecture. - */ -#ifndef __CONFIG_TI_ARMV7_OMAP_H__ -#define __CONFIG_TI_ARMV7_OMAP_H__ - -/* - * GPMC NAND block. We support 1 device and the physical address to - * access CS0 at is 0x8000000. - */ -#ifdef CONFIG_NAND -#ifndef CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_BASE 0x8000000 -#endif -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - -/* Now for the remaining common defines */ -#include - -#endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h deleted file mode 100644 index 5d9c8ef..0000000 --- a/include/configs/ti_omap3_common.h +++ /dev/null @@ -1,68 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ti_omap3_common.h - * - * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ - * - * For more details, please see the technical documents listed at - * http://www.ti.com/product/omap3530 - * http://www.ti.com/product/omap3630 - * http://www.ti.com/product/dm3730 - */ - -#ifndef __CONFIG_TI_OMAP3_COMMON_H__ -#define __CONFIG_TI_OMAP3_COMMON_H__ - -/* - * High Level Configuration Options - */ - -#include -#include - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -/* NS16550 Configuration */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif /* !CONFIG_DM_SERIAL */ -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ - 115200} - -/* Select serial console configuration */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 -#define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#endif - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) - -#define CONFIG_SYS_MONITOR_LEN (256 << 10) - -/* SPL */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (64 << 20)) - -#ifdef CONFIG_NAND -#define CONFIG_SYS_NAND_BASE 0x30000000 -#endif - -/* Now bring in the rest of the common code. */ -#include - -#endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ diff --git a/include/configs/ti_omap4_common.h b/include/configs/ti_omap4_common.h deleted file mode 100644 index 1e31622..0000000 --- a/include/configs/ti_omap4_common.h +++ /dev/null @@ -1,130 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Texas Instruments Incorporated. - * Aneesh V - * Steve Sakoman - * - * TI OMAP4 common configuration settings - */ - -#ifndef __CONFIG_TI_OMAP4_COMMON_H -#define __CONFIG_TI_OMAP4_COMMON_H - -#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 1 -#define CONFIG_SYS_PL310_BASE 0x48242000 -#endif - -/* Get CPU defs */ -#include -#include - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE - -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#include - -/* - * Hardware drivers - */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_COM3 UART3_BASE -#endif - -/* TWL6030 */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_TWL6030_POWER 1 -#endif - -/* USB */ - -/* USB device configuration */ -#define CONFIG_USB_DEVICE 1 -#define CONFIG_USB_TTY 1 - -/* - * Environment setup - */ -#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=" \ - "setenv mmcdev " #instance"; "\ - "setenv bootpart " #instance":2 ; "\ - "run mmcboot\0" - -#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(LEGACY_MMC, legacy_mmc, 0) \ - func(MMC, mmc, 1) \ - func(LEGACY_MMC, legacy_mmc, 1) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - DEFAULT_FIT_TI_ARGS \ - "console=ttyO2,115200n8\0" \ - "fdtfile=undefined\0" \ - "bootpart=0:2\0" \ - "bootdir=/boot\0" \ - "bootfile=zImage\0" \ - "usbtty=cdc_acm\0" \ - "vram=16M\0" \ - "loaduimage=load mmc ${mmcdev} ${loadaddr} uImage\0" \ - "uimageboot=echo Booting from mmc${mmcdev} ...; " \ - "run args_mmc; " \ - "bootm ${loadaddr}\0" \ - "findfdt="\ - "if test $board_name = sdp4430; then " \ - "setenv fdtfile omap4-sdp.dtb; fi; " \ - "if test $board_name = panda; then " \ - "setenv fdtfile omap4-panda.dtb; fi;" \ - "if test $board_name = panda-a4; then " \ - "setenv fdtfile omap4-panda-a4.dtb; fi;" \ - "if test $board_name = panda-es; then " \ - "setenv fdtfile omap4-panda-es.dtb; fi;" \ - "if test $board_name = duovero; then " \ - "setenv fdtfile omap4-duovero-parlor.dtb; fi;" \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine device tree to use; fi; \0" \ - BOOTENV - -/* - * Defines for SPL - * It is known that this will break HS devices. Since the current size of - * SPL is overlapped with public stack and breaking non HS devices to boot. - * So moving TEXT_BASE down to non-HS limit. - */ -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) - -#ifdef CONFIG_SPL_BUILD -/* No need for i2c in SPL mode as we will use SRI2C for PMIC access on OMAP4 */ -#undef CONFIG_SYS_I2C -#endif - -#endif /* __CONFIG_TI_OMAP4_COMMON_H */ diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h deleted file mode 100644 index de0a6af..0000000 --- a/include/configs/ti_omap5_common.h +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - * Texas Instruments Incorporated. - * Sricharan R - * - * Derived from OMAP4 done by: - * Aneesh V - * - * TI OMAP5 AND DRA7XX common configuration settings - * - * For more details, please see the technical documents listed at - * http://www.ti.com/product/omap5432 - */ - -#ifndef __CONFIG_TI_OMAP5_COMMON_H -#define __CONFIG_TI_OMAP5_COMMON_H - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE - -/* - * For the DDR timing information we can either dynamically determine - * the timings to use or use pre-determined timings (based on using the - * dynamic method. Default to the static timing infomation. - */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - -#define CONFIG_PALMAS_POWER - -#include -#include - -#include - -/* - * Hardware drivers - */ -#define CONFIG_SYS_NS16550_CLK 48000000 -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#endif - -/* - * Environment setup - */ - -#ifndef DFUARGS -#define DFUARGS -#endif - -#include -#include -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV \ - DEFAULT_MMC_TI_ARGS \ - DEFAULT_FIT_TI_ARGS \ - DEFAULT_COMMON_BOOT_TI_ARGS \ - DEFAULT_FDT_TI_ARGS \ - DFUARGS \ - NETARGS \ - NANDARGS \ - -/* - * SPL related defines. The Public RAM memory map the ROM defines the - * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. - * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. - * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and - * print some information. - */ -#ifdef CONFIG_TI_SECURE_DEVICE -/* - * For memory booting on HS parts, the first 4KB of the internal RAM is - * reserved for secure world use and the flash loader image is - * preceded by a secure certificate. The SPL will therefore run in internal - * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). - */ -#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 -/* If no specific start address is specified then the secure EMIF - * region will be placed at the end of the DDR space. In order to prevent - * the main u-boot relocation from clobbering that memory and causing a - * firewall violation, we tell u-boot that memory is protected RAM (PRAM) - */ -#if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) -#define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 -#endif -#else -/* - * For all booting on GP parts, the flash loader image is - * downloaded into internal RAM at address 0x40300000. - */ -#endif - -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ - (128 << 20)) -#ifdef CONFIG_SPL_BUILD -#undef CONFIG_TIMER -#endif - -#endif /* __CONFIG_TI_OMAP5_COMMON_H */ diff --git a/include/configs/tinker_rk3288.h b/include/configs/tinker_rk3288.h deleted file mode 100644 index 5adae68..0000000 --- a/include/configs/tinker_rk3288.h +++ /dev/null @@ -1,22 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Rockchip Electronics Co., Ltd - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include - -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dchp, na) - -#define CONFIG_SYS_MMC_ENV_DEV 1 - -#endif diff --git a/include/configs/titanium.h b/include/configs/titanium.h deleted file mode 100644 index c24d657..0000000 --- a/include/configs/titanium.h +++ /dev/null @@ -1,165 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Stefan Roese - * - * Configuration settings for the ProjectionDesign / Barco - * Titanium board. - * - * Based on mx6qsabrelite.h which is: - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_MX6Q - -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 3769 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_FEC_MXC_PHYADDR 4 - -/* USB Configs */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (500 << 20)) - -#define CONFIG_HOSTNAME "titanium" -#define CONFIG_UBI_PART ubi -#define CONFIG_UBIFS_VOLUME rootfs0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel=" CONFIG_HOSTNAME "/uImage\0" \ - "kernel_fs=/boot/uImage\0" \ - "kernel_addr=11000000\0" \ - "dtb=" CONFIG_HOSTNAME "/" \ - CONFIG_HOSTNAME ".dtb\0" \ - "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \ - "dtb_addr=12800000\0" \ - "script=boot.scr\0" \ - "uimage=uImage\0" \ - "console=ttymxc0\0" \ - "baudrate=115200\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "uimage=uImage\0" \ - "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ - " ${script}\0" \ - "bootscript=echo Running bootscript from mmc ...; source\0" \ - "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ - "mmcroot=/dev/mmcblk0p2\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot} rootwait rw\0" \ - "bootmmc=run mmcargs; fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}" \ - " ${uimage}; bootm\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcon=setenv bootargs ${bootargs} console=ttymxc0," \ - "${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "rootpath=/opt/eldk-5.3/armv7a/rootfs-minimal-mtdutils\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \ - "part=" __stringify(CONFIG_UBI_PART) "\0" \ - "boot_vol=0\0" \ - "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ - "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ - "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ - " ${filesize}\0" \ - "upd_ubifs=run load_ubifs update_ubifs\0" \ - "init_ubi=nand erase.part ubi;ubi part ${part};" \ - "ubi create ${vol} c800000\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ - " addcon addmtd;" \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "ubifsargs=set bootargs ubi.mtd=ubi " \ - "root=ubi:rootfs${boot_vol} rootfstype=ubifs\0" \ - "ubifs_mount=ubi part ubi;ubifsmount ubi:rootfs${boot_vol}\0" \ - "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ - "ubifsload ${dtb_addr} ${dtb_fs};\0" \ - "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ - "addmtd;bootm ${kernel_addr} - ${dtb_addr}\0" \ - "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ - "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ - "net_nfs=run load_dtb load_kernel; " \ - "run nfsargs addip addcon addmtd;" \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "delenv=env default -a -f; saveenv; reset\0" - -#define CONFIG_BOOTCOMMAND "run nand_ubifs" - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (512 << 20) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Enable NAND support */ -#ifdef CONFIG_CMD_NAND - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* Environment in NAND */ -#define CONFIG_ENV_OFFSET (16 << 20) -#define CONFIG_ENV_SECT_SIZE (128 << 10) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + (512 << 10)) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#else /* CONFIG_CMD_NAND */ - -/* Environment in MMC */ -#define CONFIG_ENV_SIZE (8 << 10) -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif /* CONFIG_CMD_NAND */ - -/* UBI/UBIFS config options */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/topic_miami.h b/include/configs/topic_miami.h deleted file mode 100644 index b98656d..0000000 --- a/include/configs/topic_miami.h +++ /dev/null @@ -1,123 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 Topic Embedded Products - * - * Configuration for Zynq Evaluation and Development Board - Miami - * See zynq-common.h for Zynq common configs - */ - -#ifndef __CONFIG_TOPIC_MIAMI_H -#define __CONFIG_TOPIC_MIAMI_H - - -/* Speed up boot time by ignoring the environment which we never used */ - -#include "zynq-common.h" - -/* Fixup settings */ -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x8000 -#undef CONFIG_ENV_OFFSET -#define CONFIG_ENV_OFFSET 0x80000 - -/* SPL settings */ -#undef CONFIG_SPL_ETH_SUPPORT -#undef CONFIG_SPL_MAX_FOOTPRINT -#define CONFIG_SPL_MAX_FOOTPRINT CONFIG_SYS_SPI_U_BOOT_OFFS -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" - -/* sspi command isn't useful */ -#undef CONFIG_CMD_SPI - -/* No useful gpio */ -#undef CONFIG_ZYNQ_GPIO -#undef CONFIG_CMD_GPIO - -/* No falcon support */ -#undef CONFIG_SPL_OS_BOOT -#undef CONFIG_SPL_FPGA_SUPPORT - -/* FPGA commands that we don't use */ - -/* Extras */ -#undef CONFIG_SYS_MEMTEST_START -#define CONFIG_SYS_MEMTEST_START 0 -#undef CONFIG_SYS_MEMTEST_END -#define CONFIG_SYS_MEMTEST_END 0x18000000 - -/* Faster flash, ours may run at 108 MHz */ -#undef CONFIG_SPI_FLASH_WINBOND - -/* Setup proper boot sequences for Miami boards */ - -#if defined(CONFIG_USB) -# define EXTRA_ENV_USB \ - "usbreset=i2c dev 1 && i2c mw 41 1 ff && i2c mw 41 3 fe && "\ - "i2c mw 41 1 fe && i2c mw 41 1 ff\0" \ - "usbboot=run usbreset && if usb start; then " \ - "echo Booting from USB... && " \ - "if load usb 0 0x1900000 ${bootscript}; then "\ - "source 0x1900000; fi; " \ - "load usb 0 ${kernel_addr} ${kernel_image} && " \ - "load usb 0 ${devicetree_addr} ${devicetree_image} && " \ - "load usb 0 ${ramdisk_load_address} ${ramdisk_image} && " \ - "bootm ${kernel_addr} ${ramdisk_load_address} "\ - "${devicetree_addr}; " \ - "fi\0" - /* Note that addresses here should match the addresses in the env */ -# undef DFU_ALT_INFO -# define DFU_ALT_INFO \ - "dfu_alt_info=" \ - "uImage ram 0x2080000 0x500000;" \ - "devicetree.dtb ram 0x2000000 0x20000;" \ - "uramdisk.image.gz ram 0x4000000 0x10000000\0" \ - "dfu_ram=run usbreset && dfu 0 ram 0\0" \ - "thor_ram=run usbreset && thordown 0 ram 0\0" -#else -# define EXTRA_ENV_USB -#endif - -#undef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_image=uImage\0" \ - "kernel_addr=0x2080000\0" \ - "ramdisk_image=uramdisk.image.gz\0" \ - "ramdisk_load_address=0x4000000\0" \ - "devicetree_image=devicetree.dtb\0" \ - "devicetree_addr=0x2000000\0" \ - "bitstream_image=fpga.bin\0" \ - "bootscript=autorun.scr\0" \ - "loadbit_addr=0x100000\0" \ - "loadbootenv_addr=0x2000000\0" \ - "kernel_size=0x440000\0" \ - "devicetree_size=0x10000\0" \ - "boot_size=0xF00000\0" \ - "fdt_high=0x20000000\0" \ - "initrd_high=0x20000000\0" \ - "mmc_loadbit=echo Loading bitstream from SD/MMC/eMMC to RAM.. && " \ - "mmcinfo && " \ - "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \ - "fpga load 0 ${loadbit_addr} ${filesize}\0" \ - "qspiboot=echo Booting from QSPI flash... && " \ - "sf probe && " \ - "sf read ${devicetree_addr} 0xA0000 ${devicetree_size} && " \ - "sf read ${kernel_addr} 0xC0000 ${kernel_size} && " \ - "bootm ${kernel_addr} - ${devicetree_addr}\0" \ - "sdboot=if mmcinfo; then " \ - "setenv bootargs console=ttyPS0,115200 " \ - "root=/dev/mmcblk0p2 rw rootfstype=ext4 " \ - "rootwait quiet ; " \ - "load mmc 0 ${kernel_addr} ${kernel_image}&& " \ - "load mmc 0 ${devicetree_addr} ${devicetree_image}&& " \ - "bootm ${kernel_addr} - ${devicetree_addr}; " \ - "fi\0" \ - EXTRA_ENV_USB \ - DFU_ALT_INFO - -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "if mmcinfo; then " \ - "if fatload mmc 0 0x1900000 ${bootscript}; then source 0x1900000; " \ - "fi; fi; run $modeboot" -#undef CONFIG_DISPLAY_BOARDINFO - -#endif /* __CONFIG_TOPIC_MIAMI_H */ diff --git a/include/configs/tplink_wdr4300.h b/include/configs/tplink_wdr4300.h deleted file mode 100644 index 4367158..0000000 --- a/include/configs/tplink_wdr4300.h +++ /dev/null @@ -1,61 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 Marek Vasut - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_SYS_MHZ 280 -#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MALLOC_LEN 0x40000 -#define CONFIG_SYS_BOOTPARAMS_LEN 0x20000 - -#define CONFIG_SYS_SDRAM_BASE 0xa0000000 -#define CONFIG_SYS_LOAD_ADDR 0xa1000000 -#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR - -#define CONFIG_SYS_INIT_RAM_ADDR 0xbd000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_CLK 40000000 -#define CONFIG_SYS_BAUDRATE_TABLE \ - {9600, 19200, 38400, 57600, 115200} - -#define CONFIG_BOOTCOMMAND \ - "dhcp 192.168.1.1:wdr4300.fit && bootm $loadaddr" - -#define CONFIG_ENV_SIZE 0x10000 - -/* - * Command - */ -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ -#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - /* Boot argument buffer size */ - -/* USB, USB storage, USB ethernet */ -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_IS_TDI - -/* - * Diagnostics - */ -#define CONFIG_SYS_MEMTEST_START 0x80100000 -#define CONFIG_SYS_MEMTEST_END 0x83f00000 - -#define CONFIG_CMD_MII - -#endif /* __CONFIG_H */ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h deleted file mode 100644 index 13e3d60..0000000 --- a/include/configs/tqma6.h +++ /dev/null @@ -1,341 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013, 2014, 2017 Markus Niebel - * - * Configuration settings for the TQ Systems TQMa6 module. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -/* SPL */ -/* #if defined(CONFIG_SPL_BUILD) */ -/* common IMX6 SPL configuration */ -#include "imx6_spl.h" - -/* #endif */ - -/* place code in last 4 MiB of RAM */ - -#include "mx6_common.h" - -#if defined(CONFIG_TQMA6S) -#define PHYS_SDRAM_SIZE (512u * SZ_1M) -#elif defined(CONFIG_TQMA6DL) -#define PHYS_SDRAM_SIZE (SZ_1G) -#elif defined(CONFIG_TQMA6Q) -#define PHYS_SDRAM_SIZE (SZ_1G) -#endif - -#define CONFIG_MXC_UART - -/* SPI Flash */ - -#define TQMA6_SPI_FLASH_SECTOR_SIZE SZ_64K - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 100000 - -/* I2C EEPROM (M24C64) */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */ -#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20 - -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 -#define TQMA6_PFUZE100_I2C_BUS 2 - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_ENV_SIZE (SZ_8K) -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * SZ_1M) - -#if defined(CONFIG_TQMA6X_MMC_BOOT) - -#define TQMA6_UBOOT_OFFSET SZ_1K -#define TQMA6_UBOOT_SECTOR_START 0x2 -#define TQMA6_UBOOT_SECTOR_COUNT 0x7fe - -#define CONFIG_ENV_OFFSET SZ_1M -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#define TQMA6_FDT_OFFSET (2 * SZ_1M) -#define TQMA6_FDT_SECTOR_START 0x1000 -#define TQMA6_FDT_SECTOR_COUNT 0x800 - -#define TQMA6_KERNEL_SECTOR_START 0x2000 -#define TQMA6_KERNEL_SECTOR_COUNT 0x2000 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "uboot_start="__stringify(TQMA6_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_size="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_size="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "loadimage=mmc dev ${mmcdev}; " \ - "mmc read ${loadaddr} ${kernel_start} ${kernel_size};\0" \ - "loadfdt=mmc dev ${mmcdev}; " \ - "mmc read ${fdt_addr} ${fdt_start} ${fdt_size};\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${uboot_size}; then " \ - "mmc write ${loadaddr} ${uboot_start} " \ - "${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_kernel=run kernel_name; " \ - "if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${kernel_size}; then " \ - "mmc write ${loadaddr} " \ - "${kernel_start} ${blkc}; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "setenv filesize; setenv blkc \0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "setexpr blkc ${filesize} + 0x1ff; " \ - "setexpr blkc ${blkc} / 0x200; " \ - "if itest ${blkc} <= ${fdt_size}; then " \ - "mmc write ${loadaddr} ${fdt_start} ${blkc}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize; setenv blkc \0" \ - -#define CONFIG_BOOTCOMMAND \ - "run mmcboot; run netboot; run panicboot" - -#elif defined(CONFIG_TQMA6X_SPI_BOOT) - -#define TQMA6_UBOOT_OFFSET 0x400 -#define TQMA6_UBOOT_SECTOR_START 0x0 -/* max u-boot size: 512k */ -#define TQMA6_UBOOT_SECTOR_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE -#define TQMA6_UBOOT_SECTOR_COUNT 0x8 -#define TQMA6_UBOOT_SIZE (TQMA6_UBOOT_SECTOR_SIZE * \ - TQMA6_UBOOT_SECTOR_COUNT) - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_OFFSET (TQMA6_UBOOT_SIZE) -#define CONFIG_ENV_SECT_SIZE TQMA6_SPI_FLASH_SECTOR_SIZE -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \ - CONFIG_ENV_SECT_SIZE) - -#define TQMA6_FDT_OFFSET (CONFIG_ENV_OFFSET_REDUND + \ - CONFIG_ENV_SECT_SIZE) -#define TQMA6_FDT_SECT_SIZE (TQMA6_SPI_FLASH_SECTOR_SIZE) - -#define TQMA6_FDT_SECTOR_START 0x0a /* 8 Sector u-boot, 2 Sector env */ -#define TQMA6_FDT_SECTOR_COUNT 0x01 - -#define TQMA6_KERNEL_SECTOR_START 0x10 -#define TQMA6_KERNEL_SECTOR_COUNT 0x60 - -#define TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - "mmcblkdev=0\0" \ - "uboot_offset="__stringify(TQMA6_UBOOT_OFFSET)"\0" \ - "uboot_sectors="__stringify(TQMA6_UBOOT_SECTOR_COUNT)"\0" \ - "fdt_start="__stringify(TQMA6_FDT_SECTOR_START)"\0" \ - "fdt_sectors="__stringify(TQMA6_FDT_SECTOR_COUNT)"\0" \ - "kernel_start="__stringify(TQMA6_KERNEL_SECTOR_START)"\0" \ - "kernel_sectors="__stringify(TQMA6_KERNEL_SECTOR_COUNT)"\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr blkc ${filesize} + " \ - __stringify(TQMA6_UBOOT_OFFSET) "; " \ - "setexpr size ${uboot_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${blkc} <= ${size}; then " \ - "sf probe; " \ - "sf erase 0 ${size}; " \ - "sf write ${loadaddr} ${uboot_offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv blkc; setenv size \0" \ - "update_kernel=run kernel_name; if tftp ${kernel}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "update_fdt=if tftp ${fdt_file}; then " \ - "if itest ${filesize} > 0; then " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "if itest ${filesize} <= ${size}; then " \ - "sf probe; " \ - "sf erase ${offset} ${size}; " \ - "sf write ${loadaddr} ${offset} " \ - "${filesize}; " \ - "fi; " \ - "fi; fi; " \ - "setenv filesize 0; setenv size ; setenv offset\0" \ - "loadimage=sf probe; " \ - "setexpr size ${kernel_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${kernel_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${loadaddr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" \ - "loadfdt=sf probe; " \ - "setexpr size ${fdt_sectors} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "setexpr offset ${fdt_start} * " \ - __stringify(TQMA6_SPI_FLASH_SECTOR_SIZE)"; " \ - "sf read ${fdt_addr} ${offset} ${size}; " \ - "setenv size ; setenv offset\0" \ - -#define CONFIG_BOOTCOMMAND \ - "sf probe; run mmcboot; run netboot; run panicboot" \ - -#else - -#error "need to define boot source" - -#endif - -/* 128 MiB offset as in ARM related docu for linux suggested */ -#define TQMA6_FDT_ADDRESS 0x18000000 - -/* set to a resonable value, changeable by user */ -#define TQMA6_CMA_SIZE 160M - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "board=tqma6\0" \ - "uimage=uImage\0" \ - "zimage=zImage\0" \ - "boot_type=bootz\0" \ - "kernel_name=if test \"${boot_type}\" != bootz; then " \ - "setenv kernel ${uimage}; " \ - "else setenv kernel ${zimage}; fi\0" \ - "uboot=u-boot.imx\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "fdt_addr="__stringify(TQMA6_FDT_ADDRESS)"\0" \ - "console=" CONSOLE_DEV "\0" \ - "cma_size="__stringify(TQMA6_CMA_SIZE)"\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "rootfsmode=ro\0" \ - "addcma=setenv bootargs ${bootargs} cma=${cma_size}\0" \ - "addtty=setenv bootargs ${bootargs} console=${console},${baudrate}\0" \ - "addfb=setenv bootargs ${bootargs} " \ - "imx-fbdev.legacyfb_depth=32 consoleblank=0\0" \ - "mmcpart=2\0" \ - "mmcblkdev=0\0" \ - "mmcargs=run addmmc addtty addfb addcma\0" \ - "addmmc=setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk${mmcblkdev}p${mmcpart} ${rootfsmode} " \ - "rootwait\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "setenv bootargs; " \ - "run mmcargs; " \ - "run loadimage; " \ - "if run loadfdt; then " \ - "echo boot device tree kernel ...; " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "${boot_type}; " \ - "fi;\0" \ - "setenv bootargs \0" \ - "netdev=eth0\0" \ - "rootpath=/srv/nfs/tqma6\0" \ - "ipmode=static\0" \ - "netargs=run addnfs addip addtty addfb addcma\0" \ - "addnfs=setenv bootargs ${bootargs} " \ - "root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath},v3,tcp;\0" \ - "addip_static=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:" \ - "${hostname}:${netdev}:off\0" \ - "addip_dynamic=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test \"${ipmode}\" != static; then " \ - "run addip_dynamic; else run addip_static; fi\0" \ - "set_getcmd=if test \"${ipmode}\" != static; then " \ - "setenv getcmd dhcp; setenv autoload yes; " \ - "else setenv getcmd tftp; setenv autoload no; fi\0" \ - "netboot=echo Booting from net ...; " \ - "run kernel_name; " \ - "run set_getcmd; " \ - "setenv bootargs; " \ - "run netargs; " \ - "if ${getcmd} ${kernel}; then " \ - "if ${getcmd} ${fdt_addr} ${fdt_file}; then " \ - "${boot_type} ${loadaddr} - ${fdt_addr}; " \ - "fi; " \ - "fi; " \ - "echo ... failed\0" \ - "panicboot=echo No boot device !!! reset\0" \ - TQMA6_EXTRA_BOOTDEV_ENV_SETTINGS \ - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * All the defines above are for the TQMa6 SoM - * - * Now include the baseboard specific configuration - */ -#ifdef CONFIG_MBA6 -#include "tqma6_mba6.h" -#elif CONFIG_WRU4 -#include "tqma6_wru4.h" -#else -#error "No baseboard for the TQMa6 defined!" -#endif - -/* Support at least the sensor on TQMa6 SOM */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/tqma6_mba6.h b/include/configs/tqma6_mba6.h deleted file mode 100644 index bee6d2f..0000000 --- a/include/configs/tqma6_mba6.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 - 2017 Markus Niebel - * - * Configuration settings for the TQ Systems TQMa6 module on - * MBa6 starter kit - */ - -#ifndef __CONFIG_TQMA6_MBA6_H -#define __CONFIG_TQMA6_MBA6_H - -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" - -#define CONFIG_FEC_MXC_PHYADDR 0x03 - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" - -#endif /* __CONFIG_TQMA6_MBA6_H */ diff --git a/include/configs/tqma6_wru4.h b/include/configs/tqma6_wru4.h deleted file mode 100644 index 0af52e5..0000000 --- a/include/configs/tqma6_wru4.h +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015 Stefan Roese - */ - -#ifndef __CONFIG_TQMA6_WRU4_H -#define __CONFIG_TQMA6_WRU4_H - -/* Ethernet */ -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x01 -#define CONFIG_PHY_SMSC - -/* UART */ -#define CONFIG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" - -/* Watchdog */ - -/* Config on-board RTC */ -#define CONFIG_RTC_DS1337 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -/* Turn off RTC square-wave output to save battery */ -#define CONFIG_RTC_DS1337_NOOSC - -/* LED */ - -/* Bootcounter */ -#define CONFIG_SYS_BOOTCOUNT_BE - -#endif /* __CONFIG_TQMA6_WRU4_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h deleted file mode 100644 index af8e8ce..0000000 --- a/include/configs/trats.h +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Samsung Electronics - * Heungjun Kim - * - * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. - */ - -#ifndef __CONFIG_TRATS_H -#define __CONFIG_TRATS_H - -#include - -#define CONFIG_TRATS - -#define CONFIG_TIZEN /* TIZEN lib */ - -#define CONFIG_SYS_L2CACHE_OFF -#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE 0x10502000 -#endif - -/* TRATS has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ - -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) - -/* select serial console configuration */ - -#define CONFIG_MACH_TYPE MACH_TYPE_TRATS - -#define CONFIG_BOOTCOMMAND "run autoboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -#define CONFIG_BOOTBLOCK "10" -#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" - -#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ - -#define CONFIG_ENV_OVERWRITE - -/* Tizen - partitions definitions */ -#define PARTS_CSA "csa-mmc" -#define PARTS_BOOT "boot" -#define PARTS_QBOOT "qboot" -#define PARTS_CSC "csc" -#define PARTS_ROOT "platform" -#define PARTS_DATA "data" -#define PARTS_UMS "ums" - -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ - "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ - "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ - "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ - "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ - "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ - "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ - -#define CONFIG_DFU_ALT \ - "u-boot raw 0x80 0x400;" \ - "/uImage ext4 0 2;" \ - "/modem.bin ext4 0 2;" \ - "/exynos4210-trats.dtb ext4 0 2;" \ - ""PARTS_CSA" part 0 1;" \ - ""PARTS_BOOT" part 0 2;" \ - ""PARTS_QBOOT" part 0 3;" \ - ""PARTS_CSC" part 0 4;" \ - ""PARTS_ROOT" part 0 5;" \ - ""PARTS_DATA" part 0 6;" \ - ""PARTS_UMS" part 0 7;" \ - "params.bin raw 0x38 0x8;" \ - "/Image.itb ext4 0 2\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootk=" \ - "run loaduimage;" \ - "if run loaddtb; then " \ - "bootm 0x40007FC0 - ${fdtaddr};" \ - "fi;" \ - "bootm 0x40007FC0;\0" \ - "updatebackup=" \ - "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ - "mmc dev 0 0\0" \ - "updatebootb=" \ - "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ - "lpj=lpj=3981312\0" \ - "nfsboot=" \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${nfsroot},nolock,tcp " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:" \ - "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ - "; run bootk\0" \ - "ramfsboot=" \ - "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ - "${console} ${meminfo} " \ - "initrd=0x43000000,8M ramdisk=8192\0" \ - "mmcboot=" \ - "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ - "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run bootk\0" \ - "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ - "boottrace=setenv opts initcall_debug; run bootcmd\0" \ - "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ - "verify=n\0" \ - "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE \ - "meminfo=crashkernel=32M@0x50000000\0" \ - "nfsroot=/nfsroot/arm\0" \ - "bootblock=" CONFIG_BOOTBLOCK "\0" \ - "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ - "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ - "${fdtfile}\0" \ - "mmcdev=0\0" \ - "mmcbootpart=2\0" \ - "mmcrootpart=5\0" \ - "opts=always_resume=1\0" \ - "partitions=" PARTS_DEFAULT \ - "dfu_alt_info=" CONFIG_DFU_ALT \ - "spladdr=0x40000100\0" \ - "splsize=0x200\0" \ - "splfile=falcon.bin\0" \ - "spl_export=" \ - "setexpr spl_imgsize ${splsize} + 8 ;" \ - "setenv spl_imgsize 0x${spl_imgsize};" \ - "setexpr spl_imgaddr ${spladdr} - 8 ;" \ - "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ - "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ - "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ - "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ - "spl export atags 0x40007FC0;" \ - "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ - "mw.l ${spl_addr_tmp} ${splsize};" \ - "ext4write mmc ${mmcdev}:${mmcbootpart}" \ - " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ - "setenv spl_imgsize;" \ - "setenv spl_imgaddr;" \ - "setenv spl_addr_tmp;\0" \ - CONFIG_EXTRA_ENV_ITB \ - "fdtaddr=40800000\0" \ - -/* Falcon mode definitions */ -#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 - -/* GPT */ - -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - -/* Download menu - Samsung common */ -#define CONFIG_LCD_MENU - -/* Download menu - definitions for check keys */ -#ifndef __ASSEMBLY__ - -#define KEY_PWR_PMIC_NAME "MAX8997_PMIC" -#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 -#define KEY_PWR_STATUS_MASK (1 << 0) -#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 -#define KEY_PWR_INTERRUPT_MASK (1 << 0) - -#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 -#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 -#endif /* __ASSEMBLY__ */ - -/* LCD console */ -#define LCD_BPP LCD_COLOR16 - -/* LCD */ -#define CONFIG_BMP_16BPP -#define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_EXYNOS_MIPI_DSIM -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) - -#endif /* __CONFIG_H */ diff --git a/include/configs/trats2.h b/include/configs/trats2.h deleted file mode 100644 index 9c6b2bb..0000000 --- a/include/configs/trats2.h +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Samsung Electronics - * Sanghee Kim - * Piotr Wilczek - * - * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. - */ - -#ifndef __CONFIG_TRATS2_H -#define __CONFIG_TRATS2_H - -#include - -#define CONFIG_TIZEN /* TIZEN lib */ - -#define CONFIG_SYS_L2CACHE_OFF -#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 -#define CONFIG_SYS_PL310_BASE 0x10502000 -#endif - -/* TRATS2 has 4 banks of DRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -/* select serial console configuration */ - -/* Console configuration */ - -#define CONFIG_BOOTCOMMAND "run autoboot" -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ - - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ - -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV -#define CONFIG_ENV_SIZE 4096 -#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ - -#define CONFIG_ENV_OVERWRITE - -/* Tizen - partitions definitions */ -#define PARTS_CSA "csa-mmc" -#define PARTS_BOOT "boot" -#define PARTS_QBOOT "qboot" -#define PARTS_CSC "csc" -#define PARTS_ROOT "platform" -#define PARTS_DATA "data" -#define PARTS_UMS "ums" - -#define PARTS_DEFAULT \ - "uuid_disk=${uuid_gpt_disk};" \ - "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ - "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ - "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ - "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ - "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ - "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ - "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ - -#define CONFIG_DFU_ALT \ - "u-boot raw 0x80 0x800;" \ - "/uImage ext4 0 2;" \ - "/modem.bin ext4 0 2;" \ - "/exynos4412-trats2.dtb ext4 0 2;" \ - ""PARTS_CSA" part 0 1;" \ - ""PARTS_BOOT" part 0 2;" \ - ""PARTS_QBOOT" part 0 3;" \ - ""PARTS_CSC" part 0 4;" \ - ""PARTS_ROOT" part 0 5;" \ - ""PARTS_DATA" part 0 6;" \ - ""PARTS_UMS" part 0 7;" \ - "params.bin raw 0x38 0x8;" \ - "/Image.itb ext4 0 2\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "bootk=" \ - "run loaduimage;" \ - "if run loaddtb; then " \ - "bootm 0x40007FC0 - ${fdtaddr};" \ - "fi;" \ - "bootm 0x40007FC0;\0" \ - "updatebackup=" \ - "mmc dev 0 2; mmc write 0x51000000 0 0x800;" \ - " mmc dev 0 0\0" \ - "updatebootb=" \ - "mmc read 0x51000000 0x80 0x800; run updatebackup\0" \ - "mmcboot=" \ - "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ - "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ - "run bootk\0" \ - "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ - "boottrace=setenv opts initcall_debug; run bootcmd\0" \ - "verify=n\0" \ - "rootfstype=ext4\0" \ - "console=" CONFIG_DEFAULT_CONSOLE \ - "kernelname=uImage\0" \ - "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ - "${kernelname}\0" \ - "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ - "${fdtfile}\0" \ - "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ - "mmcbootpart=2\0" \ - "mmcrootpart=5\0" \ - "opts=always_resume=1\0" \ - "partitions=" PARTS_DEFAULT \ - "dfu_alt_info=" CONFIG_DFU_ALT \ - "uartpath=ap\0" \ - "usbpath=ap\0" \ - "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ - "consoleoff=set console console=ram; save; reset\0" \ - "spladdr=0x40000100\0" \ - "splsize=0x200\0" \ - "splfile=falcon.bin\0" \ - "spl_export=" \ - "setexpr spl_imgsize ${splsize} + 8 ;" \ - "setenv spl_imgsize 0x${spl_imgsize};" \ - "setexpr spl_imgaddr ${spladdr} - 8 ;" \ - "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ - "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ - "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ - "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ - "spl export atags 0x40007FC0;" \ - "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ - "mw.l ${spl_addr_tmp} ${splsize};" \ - "ext4write mmc ${mmcdev}:${mmcbootpart}" \ - " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ - "setenv spl_imgsize;" \ - "setenv spl_imgaddr;" \ - "setenv spl_addr_tmp;\0" \ - CONFIG_EXTRA_ENV_ITB \ - "fdtaddr=40800000\0" \ - -/* GPT */ - -/* Security subsystem - enable hw_rand() */ -#define CONFIG_EXYNOS_ACE_SHA - -/* Common misc for Samsung */ -#define CONFIG_MISC_COMMON - -/* Download menu - Samsung common */ -#define CONFIG_LCD_MENU - -/* Download menu - definitions for check keys */ -#ifndef __ASSEMBLY__ - -#define KEY_PWR_PMIC_NAME "MAX77686_PMIC" -#define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 -#define KEY_PWR_STATUS_MASK (1 << 0) -#define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 -#define KEY_PWR_INTERRUPT_MASK (1 << 1) - -#define KEY_VOL_UP_GPIO EXYNOS4X12_GPIO_X22 -#define KEY_VOL_DOWN_GPIO EXYNOS4X12_GPIO_X33 -#endif /* __ASSEMBLY__ */ - -/* LCD console */ -#define LCD_BPP LCD_COLOR16 - -/* LCD */ -#define CONFIG_BMP_16BPP -#define CONFIG_FB_ADDR 0x52504000 -#define CONFIG_EXYNOS_MIPI_DSIM -#define CONFIG_VIDEO_BMP_GZIP -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) - -#endif /* __CONFIG_H */ diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h deleted file mode 100644 index 2106f4e..0000000 --- a/include/configs/tricorder.h +++ /dev/null @@ -1,253 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2006-2008 - * Texas Instruments. - * Richard Woodruff - * Syed Mohammed Khasim - * - * (C) Copyright 2012 - * Corscience GmbH & Co. KG - * Thomas Weber - * - * Configuration settings for the Tricorder board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_MACH_TYPE MACH_TYPE_TRICORDER -/* - * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 0x800FFFC0--0x80100000 should not be used for any - * other needs. - */ - -#include /* get chip and board defs */ -#include - -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (1024*1024) - -/* Hardware drivers */ - -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -/* select serial console configuration */ -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* I2C */ -#define CONFIG_SYS_I2C - - -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_BUS_NUM 1 - -/* TWL4030 */ - -/* Board NAND Info */ -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ - /* devices */ -#define CONFIG_SYS_NAND_MAX_OOBFREE 2 -#define CONFIG_SYS_NAND_MAX_ECCPOS 56 - -/* needed for ubi */ - -/* Environment information (this is the common part) */ - - -/* hang() the board on panic() */ - -/* environment placement (for NAND), is different for FLASHCARD but does not - * harm there */ -#define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ -#define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ - -/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend - * value can not be used here! */ -#define CONFIG_LOADADDR 0x82000000 - -#define CONFIG_COMMON_ENV_SETTINGS \ - "console=ttyO2,115200n8\0" \ - "mmcdev=0\0" \ - "vram=3M\0" \ - "defaultdisplay=lcd\0" \ - "kernelopts=mtdoops.mtddev=3\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "commonargs=" \ - "setenv bootargs console=${console} " \ - "${mtdparts} " \ - "${kernelopts} " \ - "vt.global_cursor_default=0 " \ - "vram=${vram} " \ - "omapdss.def_disp=${defaultdisplay}\0" - -#define CONFIG_BOOTCOMMAND "run autoboot" - -/* specific environment settings for different use cases - * FLASHCARD: used to run a rdimage from sdcard to program the device - * 'NORMAL': used to boot kernel from sdcard, nand, ... - * - * The main aim for the FLASHCARD skin is to have an embedded environment - * which will not be influenced by any data already on the device. - */ -#ifdef CONFIG_FLASHCARD -/* the rdaddr is 16 MiB before the loadaddr */ -#define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_COMMON_ENV_SETTINGS \ - CONFIG_ENV_RDADDR \ - "autoboot=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ - "rdinit=/sbin/init; " \ - "mmc dev ${mmcdev}; mmc rescan; " \ - "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ - "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ - "bootm ${loadaddr} ${rdaddr}\0" - -#else /* CONFIG_FLASHCARD */ - -#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_COMMON_ENV_SETTINGS \ - "mmcargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "root=/dev/mmcblk0p2 " \ - "rootwait " \ - "rw\0" \ - "nandargs=" \ - "run commonargs; " \ - "setenv bootargs ${bootargs} " \ - "root=ubi0:root " \ - "ubi.mtd=7 " \ - "rootfstype=ubifs " \ - "ro\0" \ - "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source ${loadaddr}\0" \ - "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "bootm ${loadaddr}\0" \ - "loaduimage_ubi=ubi part ubi; " \ - "ubifsmount ubi:root; " \ - "ubifsload ${loadaddr} /boot/uImage\0" \ - "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ - "nandboot=echo Booting from nand ...; " \ - "run nandargs; " \ - "run loaduimage_nand; " \ - "bootm ${loadaddr}\0" \ - "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loaduimage; then " \ - "run mmcboot; " \ - "else run nandboot; " \ - "fi; " \ - "fi; " \ - "else run nandboot; fi\0" - -#endif /* CONFIG_FLASHCARD */ - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 0x07000000) /* 112 MB */ - -#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) - -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -/* NAND and environment organization */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 -#define CONFIG_SYS_INIT_RAM_SIZE 0x800 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* SRAM config */ -#define CONFIG_SYS_SRAM_START 0x40200000 -#define CONFIG_SYS_SRAM_SIZE 0x10000 - -/* Defines for SPL */ - -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_ECC -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 - -#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ - CONFIG_SPL_TEXT_BASE) - -#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -/* NAND boot config */ -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_PAGE_SIZE 2048 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) -#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS -#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ - 13, 14, 16, 17, 18, 19, 20, 21, 22, \ - 23, 24, 25, 26, 27, 28, 30, 31, 32, \ - 33, 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 44, 45, 46, 47, 48, 49, 50, 51, \ - 52, 53, 54, 55, 56} - -#define CONFIG_SYS_NAND_ECCSIZE 512 -#define CONFIG_SYS_NAND_ECCBYTES 13 -#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW - -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 - -#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 -#endif /* __CONFIG_H */ diff --git a/include/configs/trimslice.h b/include/configs/trimslice.h deleted file mode 100644 index 93db175..0000000 --- a/include/configs/trimslice.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010-2012 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_TEGRA_UARTA_GPU -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_TRIMSLICE - -/* SPI */ - -/* Environment in SPI */ -#define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE -/* 1MiB flash, environment located as high as possible */ -#define CONFIG_ENV_OFFSET (SZ_1M - CONFIG_ENV_SIZE) - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ts4600.h b/include/configs/ts4600.h deleted file mode 100644 index a107e96..0000000 --- a/include/configs/ts4600.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2016 Savoir-faire Linux Inc. - * - * Author: Sebastien Bourdelin - * - * Derived from MX28EVK code by - * Fabio Estevam - * Freescale Semiconductor, Inc. - * - * Configuration settings for the TS4600 Board - */ -#ifndef __CONFIGS_TS4600_H__ -#define __CONFIGS_TS4600_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_SIZE (8 * 1024) - -/* Environment is in MMC */ -#if defined(CONFIG_CMD_MMC) && defined(CONFIG_ENV_IS_IN_MMC) -#define CONFIG_ENV_OFFSET (256 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -/* Boot Linux */ -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Extra Environment */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr=0x41000000\0" \ - "loadkernel=load mmc ${mmcdev}:${mmcpart} ${loadaddr} zImage\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} imx28-ts4600.dtb\0" \ - "loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot.ub\0" \ - "bootscript=echo Running bootscript from mmc...; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "run loadbootscript && source ${loadaddr}; \0" \ - "sdboot=echo Booting from SD card ...; " \ - "setenv mmcdev 0; " \ - "setenv mmcpart 2; " \ - "setenv root /dev/mmcblk0p3; " \ - "run loadkernel && run loadfdt; \0" \ - "startbootsequence=run bootscript || run sdboot \0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc rescan; " \ - "run startbootsequence; " \ - "setenv cmdline_append console=ttyAMA0,115200; " \ - "setenv bootargs root=${root} rootwait rw ${cmdline_append}; " \ - "bootz ${loadaddr} - ${fdt_addr}; " - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_TS4600_H__ */ diff --git a/include/configs/ts4800.h b/include/configs/ts4800.h deleted file mode 100644 index 4e274bd..0000000 --- a/include/configs/ts4800.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2015, Savoir-faire Linux Inc. - * - * Derived from MX51EVK code by - * Guennadi Liakhovetski - * Freescale Semiconductor, Inc. - * - * Configuration settings for the TS4800 Board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ - -#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 2nd stage bootloader */ - -#define CONFIG_HW_WATCHDOG - -#define CONFIG_MACH_TYPE MACH_TYPE_TS48XX - -/* text base address used when linking */ - -#include - -/* enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_REVISION_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -/* - * Hardware drivers - */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* - * MMC Configs - * */ -#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR - -/* - * Eth Configs - */ -#define CONFIG_PHY_SMSC - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE /* disable vendor parameters protection (serial#, ethaddr) */ - -/*********************************************************** - * Command definition - ***********************************************************/ - -/* Environment variables */ - - -#define CONFIG_LOADADDR 0x91000000 /* loadaddr env var */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdt_file=imx51-ts4800.dtb\0" \ - "fdt_addr=0x90fe0000\0" \ - "mmcdev=0\0" \ - "mmcpart=2\0" \ - "mmcroot=/dev/mmcblk0p3 rootwait rw\0" \ - "mmcargs=setenv bootargs root=${mmcroot}\0" \ - "addtty=setenv bootargs ${bootargs} console=ttymxc0,${baudrate}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image};\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addtty; " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "echo ERR: cannot load FDT; " \ - "fi; " - - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi; " - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Low level init */ -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35100 -#define CONFIG_SYS_MAIN_PWR_ON - -/*----------------------------------------------------------------------- - * Environment organization - */ - -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif diff --git a/include/configs/tuge1.h b/include/configs/tuge1.h deleted file mode 100644 index 808538e..0000000 --- a/include/configs/tuge1.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_KM_BOARD_NAME "tuge1" -#define CONFIG_HOSTNAME "tuge1" - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/turris_mox.h b/include/configs/turris_mox.h deleted file mode 100644 index 16a49c7..0000000 --- a/include/configs/turris_mox.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Marek Behun - * - * Based on mvebu_armada-37xx.h by Stefan Roese - */ - -#ifndef _CONFIG_TURRIS_MOX_H -#define _CONFIG_TURRIS_MOX_H - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) - -#define CONFIG_LAST_STAGE_INIT - -/* - * High Level Configuration Options (easy to change) - */ -#define CONFIG_DISPLAY_BOARDINFO_LATE - -/* additions for new ARM relocation support */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 - -/* auto boot */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ - 115200, 230400, 460800, 921600 } - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_INITRD_TAG /* enable INITRD tag */ -#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MiB for malloc() */ - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */ -#define CONFIG_SYS_MEMTEST_START 0x00800000 /* 8M */ -#define CONFIG_SYS_MEMTEST_END 0x00ffffff /*(_16M -1) */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_ALT_MEMTEST - -/* End of 16M scrubbed by training in bootrom */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0xFF0000) - -/* - * I2C - */ -#define CONFIG_I2C_MV -#define CONFIG_SYS_I2C_SLAVE 0x0 - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET 0x180000 /* as Marvell U-Boot version */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ - -/* - * Ethernet Driver configuration - */ -#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */ -#define CONFIG_ARP_TIMEOUT 200 -#define CONFIG_NET_RETRY_COUNT 50 -#define CONFIG_PHY_MARVELL - -#define CONFIG_USB_MAX_CONTROLLER_COUNT (3 + 3) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "scriptaddr=0x4d00000\0" \ - "pxefile_addr_r=0x4e00000\0" \ - "fdt_addr_r=0x4f00000\0" \ - "kernel_addr_r=0x5000000\0" \ - "ramdisk_addr_r=0x8000000\0" \ - BOOTENV - -#endif /* _CONFIG_TURRIS_MOX_H */ diff --git a/include/configs/turris_omnia.h b/include/configs/turris_omnia.h deleted file mode 100644 index abe1e99..0000000 --- a/include/configs/turris_omnia.h +++ /dev/null @@ -1,124 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Marek Behun - * Copyright (C) 2016 Tomas Hlavacek - */ - -#ifndef _CONFIG_TURRIS_OMNIA_H -#define _CONFIG_TURRIS_OMNIA_H - -/* - * High Level Configuration Options (easy to change) - */ - -/* - * TEXT_BASE needs to be below 16MiB, since this area is scrubbed - * for DDR ECC byte filling in the SPL before loading the main - * U-Boot into it. - */ -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_OFFSET ((1 << 20) - CONFIG_ENV_SIZE) -#define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB */ - -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* Keep device tree and initrd in lower memory so the kernel can access them */ -#define RELOCATION_LIMITS_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) -#define CONFIG_SPL_DRIVERS_MISC_SUPPORT - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_SPI -/* SPL related SPI defines */ -# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS -#endif - -#ifdef CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC -/* SPL related MMC defines */ -# define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) -# define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS -# ifdef CONFIG_SPL_BUILD -# define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ -# endif -#endif - -/* - * mv-common.h should be defined after CMD configs since it used them - * to enable certain macros - */ -#include "mv-common.h" - -/* Include the common distro boot environment */ -#ifndef CONFIG_SPL_BUILD - -#ifdef CONFIG_MMC -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) -#else -#define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#ifdef CONFIG_USB_STORAGE -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_DEVICES_USB(func) -#endif - -#ifdef CONFIG_SCSI -#define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) -#else -#define BOOT_TARGET_DEVICES_SCSI(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_SCSI(func) \ - BOOT_TARGET_DEVICES_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#define KERNEL_ADDR_R __stringify(0x1000000) -#define FDT_ADDR_R __stringify(0x2000000) -#define RAMDISK_ADDR_R __stringify(0x2200000) -#define SCRIPT_ADDR_R __stringify(0x1800000) -#define PXEFILE_ADDR_R __stringify(0x1900000) - -#define LOAD_ADDRESS_ENV_SETTINGS \ - "kernel_addr_r=" KERNEL_ADDR_R "\0" \ - "fdt_addr_r=" FDT_ADDR_R "\0" \ - "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" \ - "scriptaddr=" SCRIPT_ADDR_R "\0" \ - "pxefile_addr_r=" PXEFILE_ADDR_R "\0" - -#include - -#define CONFIG_EXTRA_ENV_SETTINGS \ - RELOCATION_LIMITS_ENV_SETTINGS \ - LOAD_ADDRESS_ENV_SETTINGS \ - "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ - "console=ttyS0,115200\0" \ - "ethact=ethernet@34000\0" \ - BOOTENV - -#endif /* CONFIG_SPL_BUILD */ - -#endif /* _CONFIG_TURRIS_OMNIA_H */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h deleted file mode 100644 index 0eb673a..0000000 --- a/include/configs/tuxx1.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2006 Freescale Semiconductor, Inc. - * Dave Liu - * - * Copyright (C) 2007 Logic Product Development, Inc. - * Peter Barada - * - * Copyright (C) 2007 MontaVista Software, Inc. - * Anton Vorontsov - * - * (C) Copyright 2008 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * (C) Copyright 2010-2013 - * Lukas Roggli, KEYMILE Ltd, lukas.roggli@keymile.com - * Holger Brunck, Keymile GmbH, holger.bruncl@keymile.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_KM_BOARD_NAME "tuxx1" -#define CONFIG_HOSTNAME "tuxx1" - -/* include common defines/options for all Keymile boards */ -#include "km/keymile-common.h" -#include "km/km-powerpc.h" -#include "km/km-mpc83xx.h" -#include "km/km-mpc832x.h" - -#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ - 0x0000c000 | \ - MxMR_WLFx_2X) - -#endif /* __CONFIG_H */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h deleted file mode 100644 index 3378b4a..0000000 --- a/include/configs/udoo.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * Configuration settings for Udoo board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#include "imx6_spl.h" - -/* Provide the MACH_TYPE value that the vendor kernel requires. */ -#define CONFIG_MACH_TYPE 4800 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* SATA Configs */ - -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -/* Network support */ - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 6 - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc1,115200\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdtfile=undefined\0" \ - "fdt_addr=0x18000000\0" \ - "fdt_addr_r=0x18000000\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcrootfstype=ext4\0" \ - "findfdt="\ - "if test ${board_rev} = MX6Q; then " \ - "setenv fdtfile imx6q-udoo.dtb; fi; " \ - "if test ${board_rev} = MX6DL; then " \ - "setenv fdtfile imx6dl-udoo.dtb; fi; " \ - "if test ${fdtfile} = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(SATA, sata, 0) \ - func(DHCP, dhcp, na) - -#include - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif /* __CONFIG_H * */ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h deleted file mode 100644 index 6ba4270..0000000 --- a/include/configs/udoo_neo.h +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014-2015 Freescale Semiconductor, Inc. - * Copyright Jasbir Matharu - * Copyright 2015 UDOO Team - * - * Configuration settings for the UDOO NEO board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#include "imx6_spl.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) -#define CONFIG_MXC_UART - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* Command definition */ -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_SYS_MMC_ENV_DEV 0 /*USDHC2*/ - -/* Linux only */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0,115200\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdtfile=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_addr_r=0x83000000\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcrootfstype=ext4\0" \ - "findfdt="\ - "if test $board_name = BASIC; then " \ - "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \ - "if test $board_name = BASICKS; then " \ - "setenv fdtfile imx6sx-udoo-neo-basic.dtb; fi; " \ - "if test $board_name = FULL; then " \ - "setenv fdtfile imx6sx-udoo-neo-full.dtb; fi; " \ - "if test $board_name = EXTENDED; then " \ - "setenv fdtfile imx6sx-udoo-neo-extended.dtb; fi; " \ - "if test $fdtfile = UNDEFINED; then " \ - "echo WARNING: Could not determine dtb to use; fi\0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x84000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(DHCP, dhcp, na) - -#include - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#define CONFIG_ENV_SIZE SZ_8K - -#define CONFIG_IMX_THERMAL - -/* I2C configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE3000 -#define CONFIG_POWER_PFUZE3000_I2C_ADDR 0x08 -#define PFUZE3000_I2C_BUS 0 - -/* Network */ -#define CONFIG_FEC_MXC - -#define CONFIG_FEC_ENET_DEV 0 -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 - -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ulcb.h b/include/configs/ulcb.h deleted file mode 100644 index 6f2a0cc..0000000 --- a/include/configs/ulcb.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/ulcb.h - * This file is ULCB board configuration. - * - * Copyright (C) 2017 Renesas Electronics Corporation - */ - -#ifndef __ULCB_H -#define __ULCB_H - -#include "rcar-gen3-common.h" - -/* Ethernet RAVB */ -#define CONFIG_BITBANGMII -#define CONFIG_BITBANGMII_MULTI - -/* Generic Timer Definitions (use in assembler source) */ -#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 1 -#define CONFIG_SYS_MMC_ENV_PART 2 - -#endif /* __ULCB_H */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h deleted file mode 100644 index 68568f4..0000000 --- a/include/configs/uniphier.h +++ /dev/null @@ -1,231 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012-2015 Panasonic Corporation - * Copyright (C) 2015-2016 Socionext Inc. - * Author: Masahiro Yamada - */ - -/* U-Boot - Common settings for UniPhier Family */ - -#ifndef __CONFIG_UNIPHIER_COMMON_H__ -#define __CONFIG_UNIPHIER_COMMON_H__ - -#ifndef CONFIG_SPL_BUILD -#include - -#ifdef CONFIG_CMD_MMC -#define BOOT_TARGET_DEVICE_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) -#else -#define BOOT_TARGET_DEVICE_MMC(func) -#endif - -#ifdef CONFIG_CMD_UBIFS -#define BOOT_TARGET_DEVICE_UBIFS(func) func(UBIFS, ubifs, 0) -#else -#define BOOT_TARGET_DEVICE_UBIFS(func) -#endif - -#ifdef CONFIG_CMD_USB -#define BOOT_TARGET_DEVICE_USB(func) func(USB, usb, 0) -#else -#define BOOT_TARGET_DEVICE_USB(func) -#endif - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICE_MMC(func) \ - BOOT_TARGET_DEVICE_UBIFS(func) \ - BOOT_TARGET_DEVICE_USB(func) -#else -#define BOOTENV -#endif - -#define CONFIG_ARMV7_PSCI_1_0 - -/*----------------------------------------------------------------------- - * MMU and Cache Setting - *----------------------------------------------------------------------*/ - -#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) - -#define CONFIG_TIMESTAMP - -/* FLASH related */ - -#define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_MONITOR_BASE 0 -#define CONFIG_SYS_MONITOR_LEN 0x000d0000 /* 832KB */ -#define CONFIG_SYS_FLASH_BASE 0 - -/* - * flash_toggle does not work for our support card. - * We need to use flash_status_poll. - */ -#define CONFIG_SYS_CFI_FLASH_STATUS_POLL - -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 - -/* serial console configuration */ - -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_ENV_OFFSET 0x100000 -#define CONFIG_ENV_SIZE 0x2000 -/* #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */ - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 1 - -#if !defined(CONFIG_ARM64) -/* Time clock 1MHz */ -#define CONFIG_SYS_TIMER_RATE 1000000 -#endif - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_NAND_REGS_BASE 0x68100000 -#define CONFIG_SYS_NAND_DATA_BASE 0x68000000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 - -/* - * Network Configuration - */ -#define CONFIG_SERVERIP 192.168.11.1 -#define CONFIG_IPADDR 192.168.11.10 -#define CONFIG_GATEWAYIP 192.168.11.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_SYS_LOAD_ADDR 0x85000000 -#define CONFIG_SYS_BOOTM_LEN (32 << 20) - -#if defined(CONFIG_ARM64) -/* ARM Trusted Firmware */ -#define BOOT_IMAGES \ - "second_image=unph_bl.bin\0" \ - "third_image=fip.bin\0" -#else -#define BOOT_IMAGES \ - "second_image=u-boot-spl.bin\0" \ - "third_image=u-boot.bin\0" -#endif - -#define CONFIG_ROOTPATH "/nfs/root/path" -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs $bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off;" \ - "run __nfsboot" - -#ifdef CONFIG_FIT -#define CONFIG_BOOTFILE "fitImage" -#define KERNEL_ADDR_R_OFFSET "0x05100000" -#define LINUXBOOT_ENV_SETTINGS \ - "tftpboot=tftpboot $kernel_addr_r $bootfile &&" \ - "bootm $kernel_addr_r\0" \ - "__nfsboot=run tftpboot\0" -#else -#ifdef CONFIG_ARM64 -#define CONFIG_BOOTFILE "Image" -#define LINUXBOOT_CMD "booti" -#define KERNEL_ADDR_R_OFFSET "0x02080000" -#else -#define CONFIG_BOOTFILE "zImage" -#define LINUXBOOT_CMD "bootz" -#define KERNEL_ADDR_R_OFFSET "0x00208000" -#endif -#define LINUXBOOT_ENV_SETTINGS \ - "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \ - LINUXBOOT_CMD " $kernel_addr_r $ramdisk_addr_r $fdt_addr_r\0" \ - "tftpboot=tftpboot $kernel_addr_r $bootfile && " \ - "tftpboot $fdt_addr_r $fdtfile &&" \ - "tftpboot $ramdisk_addr_r $ramdisk_file &&" \ - "setenv ramdisk_addr_r $ramdisk_addr_r:$filesize &&" \ - "run boot_common\0" \ - "__nfsboot=tftpboot $kernel_addr_load $bootfile && " \ - "tftpboot $fdt_addr_r $fdtfile &&" \ - "setenv ramdisk_addr_r - &&" \ - "run boot_common\0" -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_addr_r_offset=0x05100000\0" \ - "kernel_addr_r_offset=" KERNEL_ADDR_R_OFFSET "\0" \ - "ramdisk_addr_r_offset=0x06000000\0" \ - "ramdisk_file=rootfs.cpio.gz\0" \ - "netdev=eth0\0" \ - "initrd_high=0xffffffffffffffff\0" \ - "loadaddr_offset=0x05000000\0" \ - "script=boot.scr\0" \ - "scriptaddr=0x85000000\0" \ - "nor_base=0x42000000\0" \ - "emmcboot=mmcsetn && run bootcmd_mmc${mmc_first_dev}\0" \ - "nandboot=run bootcmd_ubifs0\0" \ - "norboot=run tftpboot\0" \ - "usbboot=run bootcmd_usb0\0" \ - "emmcscript=setenv devtype mmc && " \ - "mmcsetn && " \ - "setenv devnum ${mmc_first_dev} && " \ - "run loadscript_fat\0" \ - "nandscript=echo Running ${script} from ubi ... && " \ - "ubi part UBI && " \ - "ubifsmount ubi0:boot && " \ - "ubifsload ${loadaddr} ${script} && " \ - "source\0" \ - "norscript=echo Running ${script} from tftp ... && " \ - "tftpboot ${script} &&" \ - "source\0" \ - "usbscript=usb start && " \ - "setenv devtype usb && " \ - "setenv devnum 0 && " \ - "run loadscript_fat\0" \ - "loadscript_fat=echo Running ${script} from ${devtype}${devnum} ... && " \ - "load ${devtype} ${devnum}:1 ${loadaddr} ${script} && " \ - "source\0" \ - "sramupdate=setexpr tmp_addr $nor_base + 0x50000 &&" \ - "tftpboot $tmp_addr $second_image && " \ - "setexpr tmp_addr $nor_base + 0x70000 && " \ - "tftpboot $tmp_addr $third_image\0" \ - "emmcupdate=mmcsetn &&" \ - "mmc dev $mmc_first_dev &&" \ - "mmc partconf $mmc_first_dev 0 1 1 &&" \ - "tftpboot $second_image && " \ - "mmc write $loadaddr 0 100 && " \ - "tftpboot $third_image && " \ - "mmc write $loadaddr 100 f00\0" \ - "nandupdate=nand erase 0 0x00100000 &&" \ - "tftpboot $second_image && " \ - "nand write $loadaddr 0 0x00020000 && " \ - "tftpboot $third_image && " \ - "nand write $loadaddr 0x00020000 0x001e0000\0" \ - "usbupdate=usb start &&" \ - "tftpboot $second_image && " \ - "usb write $loadaddr 0 100 && " \ - "tftpboot $third_image && " \ - "usb write $loadaddr 100 f00\0" \ - BOOT_IMAGES \ - LINUXBOOT_ENV_SETTINGS \ - BOOTENV - -#define CONFIG_SYS_BOOTMAPSZ 0x20000000 - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE) - -/* only for SPL */ -#define CONFIG_SPL_STACK (0x00200000) - -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 - -/* subtract sizeof(struct image_header) */ -#define CONFIG_SYS_UBOOT_BASE (0x130000 - 0x40) - -#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SPL_MAX_FOOTPRINT 0x10000 -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 - -#define CONFIG_SPL_PAD_TO 0x20000 - -#endif /* __CONFIG_UNIPHIER_COMMON_H__ */ diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h deleted file mode 100644 index c0ba647..0000000 --- a/include/configs/usb_a9263.h +++ /dev/null @@ -1,89 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2007-2013 - * Stelian Pop - * Lead Tech Design - * Thomas Petazzoni, Free Electrons, - * Mateusz Kulikowski - * - * Settings for Calao USB-A9263 board - * - * U-Boot image has to be less than 200704 bytes, otherwise at91bootstrap - * installed on board will not be able to load it properly. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H -#include - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 - -#define CONFIG_MACH_TYPE MACH_TYPE_USB_A9263 - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* - * Hardware drivers - */ -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (ATMEL_BASE_SRAM1 + 16 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15) -#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22) -#endif - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_AT91_WANTS_COMMON_PHY - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_ATMEL -#define CONFIG_USB_OHCI_NEW -#define CONFIG_SYS_USB_OHCI_CPU_INIT -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 -#endif - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -/* bootstrap + u-boot + env + linux in dataflash on CS0 */ -#define CONFIG_BOOTCOMMAND "nboot 21000000 0" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) - -#endif diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h deleted file mode 100644 index 128f02d..0000000 --- a/include/configs/usbarmory.h +++ /dev/null @@ -1,101 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * USB armory MkI board configuration settings - * http://inversepath.com/usbarmory - * - * Copyright (C) 2015, Inverse Path - * Andrej Rosano - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_FSL_CLK - -#include - -/* U-Boot environment */ -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -/* U-Boot general configurations */ -#define CONFIG_SYS_CBSIZE 512 - -/* UART */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* SD/MMC */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/* USB */ -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ - -/* Fuse */ -#define CONFIG_FSL_IIM - -/* U-Boot memory offsets */ -#define CONFIG_LOADADDR 0x72000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* Linux boot */ -#define CONFIG_HOSTNAME "usbarmory" -#define CONFIG_BOOTCOMMAND \ - "run distro_bootcmd; " \ - "setenv bootargs console=${console} ${bootargs_default}; " \ - "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \ - "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \ - "bootz ${kernel_addr_r} - ${fdt_addr_r}" - -#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0) - -#include - -#define MEM_LAYOUT_ENV_SETTINGS \ - "kernel_addr_r=0x70800000\0" \ - "fdt_addr_r=0x71000000\0" \ - "scriptaddr=0x70800000\0" \ - "pxefile_addr_r=0x70800000\0" \ - "ramdisk_addr_r=0x73000000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ - "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \ - "fdtfile=imx53-usbarmory.dtb\0" \ - "console=ttymxc0,115200\0" \ - BOOTENV - -#ifndef CONFIG_CMDLINE -#define USBARMORY_FIT_PATH "/boot/usbarmory.itb" -#define USBARMORY_FIT_ADDR "0x70800000" -#endif - -/* Physical Memory Map */ -#define PHYS_SDRAM CSD0_BASE_ADDR -#define PHYS_SDRAM_SIZE (gd->ram_size) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_MEMTEST_START 0x70000000 -#define CONFIG_SYS_MEMTEST_END 0x90000000 - -#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) - -#endif /* __CONFIG_H */ diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h deleted file mode 100644 index 8c68372..0000000 --- a/include/configs/vcoreiii.h +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* - * Copyright (c) 2018 Microsemi Corporation - */ - -#ifndef __VCOREIII_H -#define __VCOREIII_H - -#include - -/* Onboard devices */ - -#define CONFIG_SYS_MALLOC_LEN 0x1F0000 -#define CONFIG_SYS_LOAD_ADDR 0x00100000 -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#if defined(CONFIG_SOC_LUTON) || defined(CONFIG_SOC_SERVAL) -#define CPU_CLOCK_RATE 416666666 /* Clock for the MIPS core */ -#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333 -#else -#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS core */ -#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) -#endif -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ - -#define CONFIG_BOARD_TYPES - -#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) -#define CONFIG_ENV_OFFSET (1024 * 1024) -#define CONFIG_ENV_SIZE (8 * 1024) -#define CONFIG_ENV_SECT_SIZE (256 * 1024) - -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) - -#endif - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || defined(CONFIG_DDRTYPE_MT47H128M8HQ) -#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) -#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || defined(CONFIG_DDRTYPE_MT41K128M16JT) -#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) -#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || defined(CONFIG_DDRTYPE_MT41K256M16) -#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) -#else -#error Unknown DDR size - please add! -#endif - -#define CONFIG_CONS_INDEX 1 - -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_SDRAM_SIZE - SZ_1M) - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE - -#define CONFIG_BOARD_EARLY_INIT_R -#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) -#define VCOREIII_DEFAULT_MTD_ENV \ - "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \ - "mtdids="CONFIG_MTDIDS_DEFAULT"\0" -#else -#define VCOREIII_DEFAULT_MTD_ENV /* Go away */ -#endif - -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - VCOREIII_DEFAULT_MTD_ENV \ - "loadaddr=0x81000000\0" \ - "spi_image_off=0x00100000\0" \ - "console=ttyS0,115200\0" \ - "setup=setenv bootargs console=${console} ${mtdparts}" \ - "${bootargs_extra}\0" \ - "spiboot=run setup; sf probe; sf read ${loadaddr}" \ - "${spi_image_off} 0x600000; bootm ${loadaddr}\0" \ - "ubootfile=u-boot.bin\0" \ - "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \ - "sf erase UBoot 0x100000;" \ - "sf write ${loadaddr} UBoot ${filesize}\0" \ - "bootcmd=run spiboot\0" \ - "" -#endif /* __VCOREIII_H */ diff --git a/include/configs/vct.h b/include/configs/vct.h deleted file mode 100644 index 5710715..0000000 --- a/include/configs/vct.h +++ /dev/null @@ -1,202 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2008 Stefan Roese , DENX Software Engineering - */ - -/* - * This file contains the configuration parameters for the VCT board - * family: - * - * vct_premium - * vct_premium_small - * vct_premium_onenand - * vct_premium_onenand_small - * vct_platinum - * vct_platinum_small - * vct_platinum_onenand - * vct_platinum_onenand_small - * vct_platinumavc - * vct_platinumavc_small - * vct_platinumavc_onenand - * vct_platinumavc_onenand_small - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CPU_CLOCK_RATE 324000000 /* Clock for the MIPS core */ -#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) - -#define CONFIG_SKIP_LOWLEVEL_INIT /* SDRAM is initialized by the bootstrap code */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 << 10) -#define CONFIG_SYS_MALLOC_LEN (1 << 20) -#define CONFIG_SYS_BOOTPARAMS_LEN (128 << 10) -#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 - -#if !defined(CONFIG_VCT_NAND) && !defined(CONFIG_VCT_ONENAND) -#define CONFIG_VCT_NOR -#endif - -/* - * UART - */ -#ifdef CONFIG_VCT_PLATINUMAVC -#define UART_1_BASE 0xBDC30000 -#else -#define UART_1_BASE 0xBF89C000 -#endif - -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE -4 -#define CONFIG_SYS_NS16550_COM1 UART_1_BASE -#define CONFIG_SYS_NS16550_CLK 921600 - -/* - * SDRAM - */ -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_MBYTES_SDRAM 128 -#define CONFIG_SYS_MEMTEST_START 0x80200000 -#define CONFIG_SYS_MEMTEST_END 0x80400000 -#define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ - -#if defined(CONFIG_VCT_PREMIUM) || defined(CONFIG_VCT_PLATINUM) -#define CONFIG_NET_RETRY_COUNT 20 -#endif - -/* - * Commands - */ -#if defined(CONFIG_CMD_USB) - -/* - * USB/EHCI - */ -#define CONFIG_USB_EHCI_VCT /* on VCT platform */ -#define CONFIG_EHCI_MMIO_BIG_ENDIAN -#define CONFIG_EHCI_DESC_BIG_ENDIAN -#define CONFIG_EHCI_IS_TDI -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */ -#endif /* CONFIG_CMD_USB */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ - -/* - * FLASH and environment organization - */ -#if defined(CONFIG_VCT_NOR) -#define CONFIG_FLASH_NOT_MEM_MAPPED - -/* - * We need special accessor functions for the CFI FLASH driver. This - * can be enabled via the CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS option. - */ -#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS - -/* - * For the non-memory-mapped NOR FLASH, we need to define the - * NOR FLASH area. This can't be detected via the addr2info() - * function, since we check for flash access in the very early - * U-Boot code, before the NOR FLASH is detected. - */ -#define CONFIG_FLASH_BASE 0xb0000000 -#define CONFIG_FLASH_END 0xbfffffff - -/* - * CFI driver settings - */ -#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ - -#define CONFIG_SYS_FLASH_BASE 0xb0000000 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ - -#ifdef CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif /* CONFIG_ENV_IS_IN_FLASH */ -#endif /* CONFIG_VCT_NOR */ - -#if defined(CONFIG_VCT_ONENAND) -#define CONFIG_USE_ONENAND_BOARD_INIT -#define CONFIG_SYS_ONENAND_BASE 0x00000000 /* this is not real address */ -#define CONFIG_SYS_FLASH_BASE 0x00000000 -#define CONFIG_ENV_ADDR (128 << 10) /* after compr. U-Boot image */ -#define CONFIG_ENV_SIZE (128 << 10) /* erase size */ -#endif /* CONFIG_VCT_ONENAND */ - -/* - * I2C/EEPROM - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7f - -/* - * Software (bit-bang) I2C driver configuration - */ -#define CONFIG_SYS_GPIO_I2C_SCL 11 -#define CONFIG_SYS_GPIO_I2C_SDA 10 - -#ifndef __ASSEMBLY__ -int vct_gpio_dir(int pin, int dir); -void vct_gpio_set(int pin, int val); -int vct_gpio_get(int pin); -#endif - -#define I2C_INIT vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SCL, 1) -#define I2C_ACTIVE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 1) -#define I2C_TRISTATE vct_gpio_dir(CONFIG_SYS_GPIO_I2C_SDA, 0) -#define I2C_READ vct_gpio_get(CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_SDA(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SDA, bit) -#define I2C_SCL(bit) vct_gpio_set(CONFIG_SYS_GPIO_I2C_SCL, bit) -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -/* CAT24WC32 */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */ - /* 32 byte page write mode using*/ - /* last 5 bits of the address */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ - -#define CONFIG_BOOTCOMMAND "run test3" - -/* - * UBI configuration - */ - -/* - * We need a small, stripped down image to fit into the first 128k OneNAND - * erase block (gzipped). This image only needs basic commands for FLASH - * (NOR/OneNAND) usage and Linux kernel booting. - */ -#if defined(CONFIG_VCT_SMALL_IMAGE) -#undef CONFIG_SYS_I2C_SOFT -#undef CONFIG_SOURCE -#undef CONFIG_TIMESTAMP -#endif /* CONFIG_VCT_SMALL_IMAGE */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h deleted file mode 100644 index 66f771d..0000000 --- a/include/configs/ve8313.h +++ /dev/null @@ -1,272 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Freescale Semiconductor, Inc. 2006. - * - * (C) Copyright 2010 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -/* - * ve8313 board configuration file - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 - -#define CONFIG_PCI_INDIRECT_BRIDGE 1 -#define CONFIG_FSL_ELBC 1 - -/* - * On-board devices - * - */ -#define CONFIG_SYS_MEMTEST_START 0x00001000 -#define CONFIG_SYS_MEMTEST_END 0x07000000 - -/* - * Device configurations - */ - -/* - * DDR Setup - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory*/ - -/* - * Manually set up DDR parameters, as this board does not - * have the SPD connected to I2C. - */ -#define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | CSCONFIG_AP \ - | CSCONFIG_ODT_RD_NEVER \ - | CSCONFIG_ODT_WR_ALL \ - | CSCONFIG_ROW_BIT_13 \ - | CSCONFIG_COL_BIT_10) - /* 0x80840102 */ - -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ - | (0 << TIMING_CFG0_WRT_SHIFT) \ - | (3 << TIMING_CFG0_RRT_SHIFT) \ - | (2 << TIMING_CFG0_WWT_SHIFT) \ - | (7 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ - | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ - | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x0e720802 */ -#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ - | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ - | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ - | (5 << TIMING_CFG1_CASLAT_SHIFT) \ - | (6 << TIMING_CFG1_REFREC_SHIFT) \ - | (2 << TIMING_CFG1_WRREC_SHIFT) \ - | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ - | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x26256222 */ -#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ - | (5 << TIMING_CFG2_CPO_SHIFT) \ - | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ - | (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ - | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ - | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ - | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) - /* 0x029028c7 */ -#define CONFIG_SYS_DDR_INTERVAL ((0x320 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (0x2000 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) - /* 0x03202000 */ -#define CONFIG_SYS_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_DBW_32) - /* 0x43080000 */ -#define CONFIG_SYS_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0232 << SDRAM_MODE_SD_SHIFT)) - /* 0x44400232 */ -#define CONFIG_SYS_DDR_MODE_2 0x8000C000 - -#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - /*0x02000000*/ -#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ - | DDRCDR_PZ_NOMZ \ - | DDRCDR_NZ_NOMZ \ - | DDRCDR_M_ODR) - /* 0x73000002 */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xFE000000 -#define CONFIG_SYS_FLASH_SIZE 32 /* size in MB */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ - -#define CONFIG_SYS_GBL_DATA_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) -#define CONFIG_SYS_MALLOC_LEN (512 * 1024) - -/* - * NAND settings - */ -#define CONFIG_SYS_NAND_BASE 0x61000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 - - - -/* Still needed for spl_minimal.c */ -#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR1_PRELIM -#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR1_PRELIM - - - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) - -#if defined(CONFIG_PCI) -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ -#endif - -/* - * TSEC - */ - -#define CONFIG_TSEC1 -#ifdef CONFIG_TSEC1 -#define CONFIG_HAS_ETH0 -#define CONFIG_TSEC1_NAME "TSEC1" -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define TSEC1_PHY_ADDR 0x01 -#define TSEC1_FLAGS 0 -#define TSEC1_PHYIDX 0 -#endif - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC1" - -/* - * Environment - */ -#define CONFIG_ENV_ADDR \ - (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x4000 -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND \ - (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg Buffer size */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ - /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) - -/* System IO Config */ -#define CONFIG_SYS_SICRH (0x01000000 | \ - SICRH_ETSEC2_B | \ - SICRH_ETSEC2_C | \ - SICRH_ETSEC2_D | \ - SICRH_ETSEC2_E | \ - SICRH_ETSEC2_F | \ - SICRH_ETSEC2_G | \ - SICRH_TSOBI1 | \ - SICRH_TSOBI2) - /* 0x010fff03 */ -#define CONFIG_SYS_SICRL (SICRL_LBC | \ - SICRL_SPI_A | \ - SICRL_SPI_B | \ - SICRL_SPI_C | \ - SICRL_SPI_D | \ - SICRL_ETSEC2_A) - /* 0x33fc0003) */ - -#define CONFIG_NETDEV eth0 - -#define CONFIG_HOSTNAME "ve8313" -#define CONFIG_UBOOTPATH ve8313/u-boot.bin - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=" __stringify(CONFIG_NETDEV) "\0" \ - "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \ - "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "u-boot_addr_r=100000\0" \ - "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \ - " +${filesize};" \ - "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \ - "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \ - " ${filesize};" \ - "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \ - -#endif /* __CONFIG_H */ diff --git a/include/configs/venice2.h b/include/configs/venice2.h deleted file mode 100644 index 8ad872d..0000000 --- a/include/configs/venice2.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013-2014 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#include "tegra124-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Venice2" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTA -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) - -/* SPI */ -#define CONFIG_SPI_FLASH_SIZE (4 << 20) - -#include "tegra-common-usb-gadget.h" -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/ventana.h b/include/configs/ventana.h deleted file mode 100644 index 09f90db..0000000 --- a/include/configs/ventana.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010,2011 - * NVIDIA Corporation - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "tegra20-common.h" - -/* High-level configuration options */ -#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana" - -/* Board-specific serial config */ -#define CONFIG_TEGRA_ENABLE_UARTD -#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE - -#define CONFIG_MACH_TYPE MACH_TYPE_VENTANA - -/* Environment in eMMC, at the end of 2nd "boot sector" */ -#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 2 - -#include "tegra-common-post.h" - -#endif /* __CONFIG_H */ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h deleted file mode 100644 index b2c14f9..0000000 --- a/include/configs/vexpress_aemv8a.h +++ /dev/null @@ -1,222 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_AEMV8A_H -#define __VEXPRESS_AEMV8A_H - -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -#ifndef CONFIG_SEMIHOSTING -#error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING -#endif -#endif - -#define CONFIG_REMAKE_ELF - -/* Link Definitions */ -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -/* ATF loads u-boot here for BASE_FVP model */ -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000) -#elif CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0) -#endif - -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ - -/* CS register bases for the original memory map. */ -#define V2M_PA_CS0 0x00000000 -#define V2M_PA_CS1 0x14000000 -#define V2M_PA_CS2 0x18000000 -#define V2M_PA_CS3 0x1c000000 -#define V2M_PA_CS4 0x0c000000 -#define V2M_PA_CS5 0x10000000 - -#define V2M_PERIPH_OFFSET(x) (x << 16) -#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1)) -#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2)) -#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3)) - -#define V2M_BASE 0x80000000 - -/* Common peripherals relative to CS7. */ -#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4)) -#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5)) -#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6)) -#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7)) - -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define V2M_UART0 0x7ff80000 -#define V2M_UART1 0x7ff70000 -#else /* Not Juno */ -#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9)) -#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10)) -#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11)) -#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12)) -#endif - -#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15)) - -#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17)) -#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18)) - -#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22)) -#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23)) - -#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26)) - -#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31)) - -/* System register offsets. */ -#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) -#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) -#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) - -/* Generic Timer Definitions */ -#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */ - -/* Generic Interrupt Controller Definitions */ -#ifdef CONFIG_GICV3 -#define GICD_BASE (0x2f000000) -#define GICR_BASE (0x2f100000) -#else - -#ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP -#define GICD_BASE (0x2f000000) -#define GICC_BASE (0x2c000000) -#elif CONFIG_TARGET_VEXPRESS64_JUNO -#define GICD_BASE (0x2C010000) -#define GICC_BASE (0x2C02f000) -#endif -#endif /* !CONFIG_GICV3 */ - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20)) - -#ifndef CONFIG_TARGET_VEXPRESS64_JUNO -/* The Vexpress64 simulators use SMSC91C111 */ -#define CONFIG_SMC91111 1 -#define CONFIG_SMC91111_BASE (0x01A000000) -#endif - -/* PL011 Serial Configuration */ -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_PL011_CLOCK 7273800 -#else -#define CONFIG_PL011_CLOCK 24000000 -#endif - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ -/* Top 16MB reserved for secure world use */ -#define DRAM_SEC_SIZE 0x01000000 -#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define PHYS_SDRAM_2 (0x880000000) -#define PHYS_SDRAM_2_SIZE 0x180000000 -#endif - -/* Enable memtest */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) - -/* Initial environment variables */ -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -/* - * Defines where the kernel and FDT exist in NOR flash and where it will - * be copied into DRAM - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=norkern\0" \ - "kernel_alt_name=Image\0" \ - "kernel_addr=0x80080000\0" \ - "initrd_name=ramdisk.img\0" \ - "initrd_addr=0x84000000\0" \ - "fdtfile=board.dtb\0" \ - "fdt_alt_name=juno\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" \ - -/* Copy the kernel and FDT to DRAM memory and boot */ -#define CONFIG_BOOTCOMMAND "afs load ${kernel_name} ${kernel_addr} ; " \ - "if test $? -eq 1; then "\ - " echo Loading ${kernel_alt_name} instead of "\ - "${kernel_name}; "\ - " afs load ${kernel_alt_name} ${kernel_addr};"\ - "fi ; "\ - "afs load ${fdtfile} ${fdt_addr} ; " \ - "if test $? -eq 1; then "\ - " echo Loading ${fdt_alt_name} instead of "\ - "${fdtfile}; "\ - " afs load ${fdt_alt_name} ${fdt_addr}; "\ - "fi ; "\ - "fdt addr ${fdt_addr}; fdt resize; " \ - "if afs load ${initrd_name} ${initrd_addr} ; "\ - "then "\ - " setenv initrd_param ${initrd_addr}; "\ - " else setenv initrd_param -; "\ - "fi ; " \ - "booti ${kernel_addr} ${initrd_param} ${fdt_addr}" - - -#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_name=Image\0" \ - "kernel_addr=0x80080000\0" \ - "initrd_name=ramdisk.img\0" \ - "initrd_addr=0x88000000\0" \ - "fdtfile=devtree.dtb\0" \ - "fdt_addr=0x83000000\0" \ - "fdt_high=0xffffffffffffffff\0" \ - "initrd_high=0xffffffffffffffff\0" - -#define CONFIG_BOOTCOMMAND "smhload ${kernel_name} ${kernel_addr}; " \ - "smhload ${fdtfile} ${fdt_addr}; " \ - "smhload ${initrd_name} ${initrd_addr} "\ - "initrd_end; " \ - "fdt addr ${fdt_addr}; fdt resize; " \ - "fdt chosen ${initrd_addr} ${initrd_end}; " \ - "booti $kernel_addr - $fdt_addr" - - -#endif - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ -#define CONFIG_SYS_MAXARGS 64 /* max command args */ - -#ifdef CONFIG_TARGET_VEXPRESS64_JUNO -#define CONFIG_SYS_FLASH_BASE 0x08000000 -/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 -/* Store environment at top of flash in the same location as blank.img */ -/* in the Juno firmware. */ -#define CONFIG_ENV_ADDR 0x0BFC0000 -#define CONFIG_ENV_SECT_SIZE 0x00010000 -#else -#define CONFIG_SYS_FLASH_BASE 0x0C000000 -/* 256 x 256KiB sectors */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 -/* Store environment at top of flash */ -#define CONFIG_ENV_ADDR 0x0FFC0000 -#define CONFIG_ENV_SECT_SIZE 0x00040000 -#endif - -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT -#define CONFIG_SYS_MAX_FLASH_BANKS 1 - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ -#define FLASH_MAX_SECTOR_SIZE 0x00040000 -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - -#endif /* __VEXPRESS_AEMV8A_H */ diff --git a/include/configs/vexpress_ca15_tc2.h b/include/configs/vexpress_ca15_tc2.h deleted file mode 100644 index 4f8e635..0000000 --- a/include/configs/vexpress_ca15_tc2.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 Linaro - * Andre Przywara, - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA15X2_TC2_h -#define __VEXPRESS_CA15X2_TC2_h - -#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#include "vexpress_common.h" - -#define CONFIG_SYSFLAGS_ADDR 0x1c010030 -#define CONFIG_SMP_PEN_ADDR CONFIG_SYSFLAGS_ADDR - -#endif diff --git a/include/configs/vexpress_ca5x2.h b/include/configs/vexpress_ca5x2.h deleted file mode 100644 index b8079e6..0000000 --- a/include/configs/vexpress_ca5x2.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Linaro - * Ryan Harkin, - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA5X2_h -#define __VEXPRESS_CA5X2_h - -#define CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP -#include "vexpress_common.h" - -#endif /* __VEXPRESS_CA5X2_h */ diff --git a/include/configs/vexpress_ca9x4.h b/include/configs/vexpress_ca9x4.h deleted file mode 100644 index 8157a58..0000000 --- a/include/configs/vexpress_ca9x4.h +++ /dev/null @@ -1,16 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Linaro - * Ryan Harkin, - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_CA9X4_H -#define __VEXPRESS_CA9X4_H - -#define CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#include "vexpress_common.h" - -#endif /* VEXPRESS_CA9X4_H */ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h deleted file mode 100644 index 47ea89d..0000000 --- a/include/configs/vexpress_common.h +++ /dev/null @@ -1,251 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 ARM Limited - * (C) Copyright 2010 Linaro - * Matt Waddel, - * - * Configuration for Versatile Express. Parts were derived from other ARM - * configurations. - */ - -#ifndef __VEXPRESS_COMMON_H -#define __VEXPRESS_COMMON_H - -/* - * Definitions copied from linux kernel: - * arch/arm/mach-vexpress/include/mach/motherboard.h - */ -#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -/* CS register bases for the original memory map. */ -#define V2M_PA_CS0 0x40000000 -#define V2M_PA_CS1 0x44000000 -#define V2M_PA_CS2 0x48000000 -#define V2M_PA_CS3 0x4c000000 -#define V2M_PA_CS7 0x10000000 - -#define V2M_PERIPH_OFFSET(x) (x << 12) -#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0)) -#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) -#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) - -#define V2M_BASE 0x60000000 -#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) -/* CS register bases for the extended memory map. */ -#define V2M_PA_CS0 0x08000000 -#define V2M_PA_CS1 0x0c000000 -#define V2M_PA_CS2 0x14000000 -#define V2M_PA_CS3 0x18000000 -#define V2M_PA_CS7 0x1c000000 - -#define V2M_PERIPH_OFFSET(x) (x << 16) -#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1)) -#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2)) -#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3)) - -#define V2M_BASE 0x80000000 -#endif - -/* - * Physical addresses, offset from V2M_PA_CS0-3 - */ -#define V2M_NOR0 (V2M_PA_CS0) -#define V2M_NOR1 (V2M_PA_CS1) -#define V2M_SRAM (V2M_PA_CS2) -#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000) -#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000) - -/* Common peripherals relative to CS7. */ -#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4)) -#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5)) -#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6)) -#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7)) - -#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9)) -#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10)) -#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11)) -#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12)) - -#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15)) - -#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17)) -#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18)) - -#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22)) -#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23)) - -#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26)) - -#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31)) -#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32) - -/* System register offsets. */ -#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0) -#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4) -#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8) - -/* - * Configuration - */ -#define SYS_CFG_START (1 << 31) -#define SYS_CFG_WRITE (1 << 30) -#define SYS_CFG_OSC (1 << 20) -#define SYS_CFG_VOLT (2 << 20) -#define SYS_CFG_AMP (3 << 20) -#define SYS_CFG_TEMP (4 << 20) -#define SYS_CFG_RESET (5 << 20) -#define SYS_CFG_SCC (6 << 20) -#define SYS_CFG_MUXFPGA (7 << 20) -#define SYS_CFG_SHUTDOWN (8 << 20) -#define SYS_CFG_REBOOT (9 << 20) -#define SYS_CFG_DVIMODE (11 << 20) -#define SYS_CFG_POWER (12 << 20) -#define SYS_CFG_SITE_MB (0 << 16) -#define SYS_CFG_SITE_DB1 (1 << 16) -#define SYS_CFG_SITE_DB2 (2 << 16) -#define SYS_CFG_STACK(n) ((n) << 12) - -#define SYS_CFG_ERR (1 << 1) -#define SYS_CFG_COMPLETE (1 << 0) - -/* Board info register */ -#define SYS_ID V2M_SYSREGS -#define CONFIG_REVISION_TAG 1 - -#define CONFIG_SYS_MEMTEST_START V2M_BASE -#define CONFIG_SYS_MEMTEST_END 0x20000000 - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_SYS_L2CACHE_OFF 1 -#define CONFIG_INITRD_TAG 1 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */ - -#define SCTL_BASE V2M_SYSCTL -#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0) - -#define CONFIG_SYS_TIMER_RATE 1000000 -#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4) -#define CONFIG_SYS_TIMER_COUNTS_DOWN - -/* PL011 Serial Configuration */ -#define CONFIG_PL011_CLOCK 24000000 -#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1} - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CONFIG_SYS_SERIAL0 V2M_UART0 -#define CONFIG_SYS_SERIAL1 V2M_UART1 - -#define CONFIG_ARM_PL180_MMCI -#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 -#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000 - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000) -#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000) - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ -#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \ - ((unsigned int)0x20000000)) -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ -#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */ - -/* additions for new relocation code */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET - -/* Basic environment settings */ -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -#include - -#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP -#define CONFIG_PLATFORM_ENV_SETTINGS \ - "loadaddr=0x80008000\0" \ - "ramdisk_addr_r=0x61000000\0" \ - "kernel_addr=0x44100000\0" \ - "ramdisk_addr=0x44800000\0" \ - "maxramdisk=0x1800000\0" \ - "pxefile_addr_r=0x88000000\0" \ - "scriptaddr=0x88000000\0" \ - "kernel_addr_r=0x80008000\0" -#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP) -#define CONFIG_PLATFORM_ENV_SETTINGS \ - "loadaddr=0xa0008000\0" \ - "ramdisk_addr_r=0x81000000\0" \ - "kernel_addr=0x0c100000\0" \ - "ramdisk_addr=0x0c800000\0" \ - "maxramdisk=0x1800000\0" \ - "pxefile_addr_r=0xa8000000\0" \ - "scriptaddr=0xa8000000\0" \ - "kernel_addr_r=0xa0008000\0" -#endif -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_PLATFORM_ENV_SETTINGS \ - BOOTENV \ - "console=ttyAMA0,38400n8\0" \ - "dram=1024M\0" \ - "root=/dev/sda1 rw\0" \ - "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \ - "24M@0x2000000(initrd)\0" \ - "flashargs=setenv bootargs root=${root} console=${console} " \ - "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \ - "devtmpfs.mount=0 vmalloc=256M\0" \ - "bootflash=run flashargs; " \ - "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \ - "bootm ${kernel_addr} ${ramdisk_addr_r}\0" - -/* FLASH and environment organization */ -#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */ -#define CONFIG_SYS_FLASH_SIZE 0x04000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 -#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0 -#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0 - -/* Timeout values in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */ - -/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */ -#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */ -#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */ - -/* Room required on the stack for the environment data */ -#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE - -/* - * Amount of flash used for environment: - * We don't know which end has the small erase blocks so we use the penultimate - * sector location for the environment - */ -#define CONFIG_ENV_SECT_SIZE FLASH_MAX_SECTOR_SIZE -#define CONFIG_ENV_OVERWRITE 1 - -/* Store environment at top of flash */ -#define CONFIG_ENV_OFFSET (PHYS_FLASH_SIZE - \ - (2 * CONFIG_ENV_SECT_SIZE)) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE1 + \ - CONFIG_ENV_OFFSET) -#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \ - CONFIG_SYS_FLASH_BASE1 } - -/* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ - -#endif /* VEXPRESS_COMMON_H */ diff --git a/include/configs/veyron.h b/include/configs/veyron.h deleted file mode 100644 index 2ab6d6c..0000000 --- a/include/configs/veyron.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 Google, Inc - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,vidconsole\0" \ - "stderr=serial,vidconsole\0" - -#include - -#define CONFIG_KEYBOARD - -#endif diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h deleted file mode 100644 index ba85bc9..0000000 --- a/include/configs/vf610twr.h +++ /dev/null @@ -1,203 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale Vybrid vf610twr board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_MACH_TYPE 4146 - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* Enable passing of ATAGs */ -#define CONFIG_CMDLINE_TAG - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* NAND support */ -#define CONFIG_SYS_NAND_ONFI_DETECTION - -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR - -/* Dynamic MTD partition support */ -#endif - -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_FEC_MXC_PHYADDR 0 - -/* QSPI Configs*/ - -#ifdef CONFIG_FSL_QSPI -#define FSL_QSPI_FLASH_SIZE (1 << 24) -#define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_SYS_FSL_QSPI_LE -#endif - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - - -#define CONFIG_SYS_LOAD_ADDR 0x82000000 - -/* We boot from the gfxRAM area of the OCRAM. */ -#define CONFIG_BOARD_SIZE_LIMIT 520192 - -/* - * We do have 128MB of memory on the Vybrid Tower board. Leave the last - * 16MB alone to avoid conflicts with Cortex-M4 firmwares running from - * DDR3. Hence, limit the memory range for image processing to 112MB - * using bootm_size. All of the following must be within this range. - * We have the default load at 32MB into DDR (for the kernel), FDT at - * 64MB and the ramdisk 512KB above that (allowing for hopefully never - * seen large trees). This allows a reasonable split between ramdisk - * and kernel size, where the ram disk can be a bit larger. - */ -#define MEM_LAYOUT_ENV_SETTINGS \ - "bootm_size=0x07000000\0" \ - "loadaddr=0x82000000\0" \ - "kernel_addr_r=0x82000000\0" \ - "fdt_addr=0x84000000\0" \ - "fdt_addr_r=0x84000000\0" \ - "rdaddr=0x84080000\0" \ - "ramdisk_addr_r=0x84080000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - MEM_LAYOUT_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttyLP1\0" \ - "fdt_file=vf610-twr.dtb\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -/* Miscellaneous configurable options */ - -#define CONFIG_SYS_MEMTEST_START 0x80010000 -#define CONFIG_SYS_MEMTEST_END 0x87C00000 - -/* Physical memory map */ -#define PHYS_SDRAM (0x80000000) -#define PHYS_SDRAM_SIZE (128 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_ENV_OFFSET (12 * 64 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 -#endif - -#ifdef CONFIG_ENV_IS_IN_NAND -#define CONFIG_ENV_SIZE (64 * 2048) -#define CONFIG_ENV_SECT_SIZE (64 * 2048) -#define CONFIG_ENV_RANGE (512 * 1024) -#define CONFIG_ENV_OFFSET 0x180000 -#endif - -#endif diff --git a/include/configs/vinco.h b/include/configs/vinco.h deleted file mode 100644 index eebb3f7..0000000 --- a/include/configs/vinco.h +++ /dev/null @@ -1,109 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration settings for the VInCo platform. - * - * Based on the settings for the SAMA5-EK board - * Copyright (C) 2014 Atmel - * Bo Shen - * Copyright (C) 2015 Free Electrons - * Gregory CLEMENT gregory.clement@free-electrons.com - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "at91-sama5_common.h" - -/* The value in the common file is too far away for the VInCo platform */ - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE 0xfc00c000 -#define CONFIG_USART_ID 30 - -/* Timer */ -#define CONFIG_SYS_TIMER_COUNTER 0xfc06863c - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x4000000 - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -/* SerialFlash */ - -#ifdef CONFIG_CMD_SF -#define CONFIG_ATMEL_SPI0 -#define CONFIG_SPI_FLASH_STMICRO -#endif - -/* MMC */ - -#ifdef CONFIG_CMD_MMC -#define CONFIG_GENERIC_ATMEL_MCI -#define ATMEL_BASE_MMCI 0xfc000000 -#define CONFIG_SYS_MMC_CLK_OD 500000 - -/* For generating MMC partitions */ - -#endif - -/* USB device */ - -/* Ethernet Hardware */ -#define CONFIG_PHY_SMSC -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY - -#ifdef CONFIG_SPI_BOOT -/* bootstrap + u-boot + env + linux in serial flash */ -/* Use our own mapping for the VInCo platform */ -#undef CONFIG_ENV_OFFSET -#undef CONFIG_ENV_SIZE - -#define CONFIG_ENV_OFFSET 0x10000 -#define CONFIG_ENV_SIZE 0x10000 - -/* Update the bootcommand according to our mapping for the VInCo platform */ -#undef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND "mmc dev 0 0;" \ - "mmc read ${loadaddr} ${k_offset} ${k_blksize};" \ - "mmc read ${oftaddr} ${dtb_offset} ${dtb_blksize};" \ - "bootz ${loadaddr} - ${oftaddr}" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "kernel_start=0x20000\0" \ - "kernel_size=0x800000\0" \ - "mmcblksize=0x200\0" \ - "oftaddr=0x21000000\0" \ - "loadaddr=0x22000000\0" \ - "update_uboot=tftp ${loadaddr} u-boot.bin;sf probe 0;" \ - "sf erase 0x20000 0x4B000; sf write ${loadaddr} 0x20000 0x4B000\0" \ - "create_partition=setexpr dtb_start ${kernel_start} + 0x400000;" \ - "setexpr rootfs_start ${kernel_start} + ${kernel_size};" \ - "setenv partitions 'name=kernel,size=${kernel_size}," \ - "start=${kernel_start};name=rootfs,size=-';" \ - "gpt write mmc 0 ${partitions} \0"\ - "f2blk_size=setexpr fileblksize ${filesize} / ${mmcblksize};" \ - "setexpr fileblksize ${fileblksize} + 1\0" \ - "store_kernel=tftp ${loadaddr} zImage; run f2blk_size;" \ - "setexpr k_blksize ${fileblksize};" \ - "setexpr k_offset ${kernel_start} / ${mmcblksize};" \ - "mmc write ${fileaddr} ${k_offset} ${fileblksize}\0" \ - "store_dtb=tftp ${loadaddr} at91-vinco.dtb; run f2blk_size;" \ - "setexpr dtb_blksize ${fileblksize};" \ - "setexpr dtb_offset ${dtb_start} / ${mmcblksize};" \ - "mmc write ${fileaddr} ${dtb_offset} ${fileblksize}\0" \ - "store_rootfs=tftp ${loadaddr} vinco-gateway-image-vinco.ext4;" \ - "setexpr rootfs_offset ${rootfs_start} / ${mmcblksize};" \ - "mmc write ${fileaddr} ${rootfs_offset} ${fileblksize}\0" \ - "bootdelay=0\0" - -#endif - -#endif diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h deleted file mode 100644 index 33f06c0..0000000 --- a/include/configs/vining_2000.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 samtec automotive software & electronics gmbh - * - * Configuration settings for the Samtec VIN|ING 2000 board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#ifdef CONFIG_SPL -#include "imx6_spl.h" -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M) - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) -#include - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_PFUZE100 -#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 - -/* Network */ -#define CONFIG_FEC_MXC - -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 - -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" - -#define CONFIG_PHY_ATHEROS - -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#endif - -#ifdef CONFIG_CMD_PCI -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX -#define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(4, 6) -#endif - -#define CONFIG_IMX_THERMAL - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_ENV_OFFSET_REDUND (9 * SZ_64K) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#ifdef CONFIG_ENV_IS_IN_MMC -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC4 eMMC */ -/* 0=user, 1=boot0, 2=boot1, * 4..7=general0..3. */ -#define CONFIG_SYS_MMC_ENV_PART 1 /* boot0 */ -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h deleted file mode 100644 index a4f2af4..0000000 --- a/include/configs/vme8349.h +++ /dev/null @@ -1,333 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * esd vme8349 U-Boot configuration file - * Copyright (c) 2008, 2009 esd gmbh Hannover Germany - * - * (C) Copyright 2006-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * reinhard.arlt@esd-electronics.de - * Based on the MPC8349EMDS config. - */ - -/* - * vme8349 board configuration file. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_E300 1 /* E300 Family */ - -/* Don't enable PCI2 on vme834x - it doesn't exist physically. */ -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ - -#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x00100000 - -/* - * DDR Setup - */ -#define CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ -#define CONFIG_SPD_EEPROM -#define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_SYS_READ_SPD vme8349_read_spd -#define CONFIG_SYS_83XX_DDR_USES_CS0 /* esd; Fsl board uses CS2/CS3 */ - -/* - * 32-bit data path mode. - * - * Please note that using this mode for devices with the real density of 64-bit - * effectively reduces the amount of available memory due to the effect of - * wrapping around while translating address to row/columns, for example in the - * 256MB module the upper 128MB get aliased with contents of the lower - * 128MB); normally this define should be used for devices with real 32-bit - * data path. - */ -#undef CONFIG_DDR_32BIT - -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is sys memory*/ -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ - | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) -#define CONFIG_DDR_2T_TIMING -#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN \ - | DDRCDR_ODT \ - | DDRCDR_Q_DRN) - /* 0x80080001 */ - -/* - * FLASH on the Local Bus - */ -#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ -#define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ - - -#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 - - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ - -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase TO (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write TO (ms) */ - -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xF7000000 /* Initial RAM addr */ -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* size */ - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Malloc size */ - -#undef CONFIG_SYS_LB_SDRAM /* if board has SDRAM on local bus */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) - -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} - -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } -/* could also use CONFIG_I2C_MULTI_BUS and CONFIG_SYS_SPD_BUS_NUM... */ - -#define CONFIG_SYS_I2C_8574_ADDR2 0x20 /* I2C1, PCF8574 */ - -/* TSEC */ -#define CONFIG_SYS_TSEC1_OFFSET 0x24000 -#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) -#define CONFIG_SYS_TSEC2_OFFSET 0x25000 -#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC2_OFFSET) - -/* - * General PCI - * Addresses are mapped 1-1. - */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 -#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE -#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 -#define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE -#define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ - -#if defined(CONFIG_PCI) - -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP - -#if !defined(CONFIG_PCI_PNP) - #define PCI_ENET0_IOADDR 0xFIXME - #define PCI_ENET0_MEMADDR 0xFIXME - #define PCI_IDSEL_NUMBER 0xFIXME -#endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ - -#endif /* CONFIG_PCI */ - -/* - * TSEC configuration - */ - -#if defined(CONFIG_TSEC_ENET) - -#define CONFIG_GMII /* MII PHY management */ -#define CONFIG_TSEC1 -#define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 -#define CONFIG_TSEC2_NAME "TSEC1" -#define CONFIG_PHY_M88E1111 -#define TSEC1_PHY_ADDR 0x08 -#define TSEC2_PHY_ADDR 0x10 -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT - -/* Options are: TSEC[0-1] */ -#define CONFIG_ETHPRIME "TSEC0" - -#endif /* CONFIG_TSEC_ENET */ - -/* - * Environment - */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0xc0000) - #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ - #define CONFIG_ENV_SIZE 0x2000 - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ -#define CONFIG_SYS_RTC_BUS_NUM 0x01 -#define CONFIG_SYS_I2C_RTC_ADDR 0x32 - -/* Pass Ethernet MAC to VxWorks */ -#define CONFIG_SYS_VXWORKS_MAC_PTR 0x000043f0 - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 256 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ - -#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ - -/* System IO Config */ -#define CONFIG_SYS_SICRH 0 -#define CONFIG_SYS_SICRL SICRL_LDP_A - -#define CONFIG_SYS_GPIO1_PRELIM -#define CONFIG_SYS_GPIO1_DIR 0x00100000 -#define CONFIG_SYS_GPIO1_DAT 0x00100000 - -#define CONFIG_SYS_GPIO2_PRELIM -#define CONFIG_SYS_GPIO2_DIR 0x78900000 -#define CONFIG_SYS_GPIO2_DAT 0x70100000 - -#ifdef CONFIG_PCI -#define CONFIG_PCI_INDIRECT_BRIDGE -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#endif - -/* - * Environment Configuration - */ -#define CONFIG_ENV_OVERWRITE - -#if defined(CONFIG_TSEC_ENET) -#define CONFIG_HAS_ETH0 -#define CONFIG_HAS_ETH1 -#endif - -#define CONFIG_HOSTNAME "VME8349" -#define CONFIG_ROOTPATH "/tftpboot/rootfs" -#define CONFIG_BOOTFILE "uImage" - -#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=vme8349\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "load=tftp 100000 /tftpboot/bdi2000/vme8349.bin\0" \ - "update=protect off fff00000 fff3ffff; " \ - "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ - "upd=run load update\0" \ - "fdtaddr=780000\0" \ - "fdtfile=vme8349.dtb\0" \ - "" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ - "$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr $ramdiskaddr $fdtaddr" - -#define CONFIG_BOOTCOMMAND "run flash_self" - -#ifndef __ASSEMBLY__ -int vme8349_read_spd(unsigned char chip, unsigned int addr, int alen, - unsigned char *buffer, int len); -#endif - -#endif /* __CONFIG_H */ diff --git a/include/configs/vyasa-rk3288.h b/include/configs/vyasa-rk3288.h deleted file mode 100644 index 3574a3b..0000000 --- a/include/configs/vyasa-rk3288.h +++ /dev/null @@ -1,38 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Amarula Solutions - * - * Configuration settings for Amarula Vyasa RK3288. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define ROCKCHIP_DEVICE_SETTINGS -#include - -#undef BOOT_TARGET_DEVICES - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 1) \ - -#define CONFIG_SYS_MMC_ENV_DEV 1 - -#ifndef CONFIG_TPL_BUILD - -#define CONFIG_SPL_OS_BOOT - -/* Falcon Mode */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" -#define CONFIG_CMD_SPL -#define CONFIG_SYS_SPL_ARGS_ADDR 0x0ffe5000 -#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K) - -/* Falcon Mode - MMC support: args@16MB kernel@17MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8000 /* 16MB */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512) -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x8800 /* 17MB */ -#endif - -#endif diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h deleted file mode 100644 index a0a78ea..0000000 --- a/include/configs/wandboard.h +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Freescale Semiconductor, Inc. - * - * Configuration settings for the Wandboard. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -#include "imx6_spl.h" - -#define CONFIG_MACH_TYPE MACH_TYPE_WANDBOARD_IMX6 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* SATA Configs */ - -#ifdef CONFIG_CMD_SATA -#define CONFIG_SYS_SATA_MAX_DEVICE 1 -#define CONFIG_DWC_AHSATA_PORT_ID 0 -#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR -#define CONFIG_LBA48 -#endif - -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) - -/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -/* USB Configs */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* Framebuffer */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_HDMI -#define CONFIG_IMX_VIDEO_SKIP - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "console=ttymxc0\0" \ - "splashpos=m,m\0" \ - "splashimage=" __stringify(CONFIG_LOADADDR) "\0" \ - "fdtfile=undefined\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr_r=0x18000000\0" \ - "fdt_addr=0x18000000\0" \ - "ip_dyn=yes\0" \ - "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ - "finduuid=part uuid mmc 0:1 uuid\0" \ - "update_sd_firmware_filename=u-boot.imx\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - "findfdt="\ - "if test $board_name = D1 && test $board_rev = MX6QP ; then " \ - "setenv fdtfile imx6qp-wandboard-revd1.dtb; fi; " \ - "if test $board_name = D1 && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-wandboard-revd1.dtb; fi; " \ - "if test $board_name = D1 && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-wandboard-revd1.dtb; fi; " \ - "if test $board_name = C1 && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-wandboard.dtb; fi; " \ - "if test $board_name = C1 && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-wandboard.dtb; fi; " \ - "if test $board_name = B1 && test $board_rev = MX6Q ; then " \ - "setenv fdtfile imx6q-wandboard-revb1.dtb; fi; " \ - "if test $board_name = B1 && test $board_rev = MX6DL ; then " \ - "setenv fdtfile imx6dl-wandboard-revb1.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; \0" \ - "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ - "ramdisk_addr_r=0x13000000\0" \ - "ramdiskaddr=0x13000000\0" \ - "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ - BOOTENV - -#define BOOT_TARGET_DEVICES(func) \ - func(MMC, mmc, 0) \ - func(MMC, mmc, 1) \ - func(MMC, mmc, 2) \ - func(SATA, sata, 0) \ - func(USB, usb, 0) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ -#define CONFIG_ENV_SIZE (8 * 1024) - -#define CONFIG_ENV_OFFSET (768 * 1024) -#define CONFIG_SYS_MMC_ENV_DEV 0 - -#endif /* __CONFIG_H * */ diff --git a/include/configs/warp.h b/include/configs/warp.h deleted file mode 100644 index 41fd6c7..0000000 --- a/include/configs/warp.h +++ /dev/null @@ -1,153 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014 O.S. Systems Software LTDA. - * Copyright (C) 2014 Kynetics LLC. - * Copyright (C) 2014 Revolution Robotics, Inc. - * - * Author: Otavio Salvador - * - * Configuration settings for the WaRP Board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include "mx6_common.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) /* Increase due to DFU */ - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE - -/* Watchdog */ - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_256M) - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_ENV_OFFSET (6 * SZ_64K) -#define CONFIG_ENV_SIZE SZ_8K -#define CONFIG_SYS_MMC_ENV_DEV 0 - -/* VDD voltage 1.65 - 1.95 */ -#define CONFIG_SYS_SD_VOLTAGE 0x00000080 - -/* USB Configs */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG2 port enabled */ -#endif - -#define CONFIG_USBD_HS - -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* I2C Configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_MAX77696 - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx6sl-warp.dtb\0" \ - "fdt_addr=0x88000000\0" \ - "initrd_addr=0x83800000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev=0\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc 0:2 uuid\0" \ - "dfu_alt_info=boot raw 0x2 0x400 mmcpart 1\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else run netboot; " \ - "fi; " \ - "fi; " \ - "else run netboot; fi" - -#endif /* __CONFIG_H */ diff --git a/include/configs/warp7.h b/include/configs/warp7.h deleted file mode 100644 index 73541fe..0000000 --- a/include/configs/warp7.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2016 NXP Semiconductors - * - * Configuration settings for the i.MX7S Warp board. - */ - -#ifndef __WARP7_CONFIG_H -#define __WARP7_CONFIG_H - -#include "mx7_common.h" -#include - -#define PHYS_SDRAM_SIZE SZ_512M - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (35 * SZ_1M) - -/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR -#define CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -/* Switch on SERIAL_TAG */ -#define CONFIG_SERIAL_TAG - -#define CONFIG_DFU_ENV_SETTINGS \ - "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ - -/* When booting with FIT specify the node entry containing boot.scr */ -#if defined(CONFIG_FIT) -#define BOOT_SCR_STRING "source ${bootscriptaddr}:${bootscr_fitimage_name}\0" -#else -#define BOOT_SCR_STRING "source ${bootscriptaddr}\0" -#endif - -#ifndef CONFIG_OPTEE_LOAD_ADDR -#define CONFIG_OPTEE_LOAD_ADDR 0 -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - CONFIG_DFU_ENV_SETTINGS \ - "script=boot.scr\0" \ - "bootscr_fitimage_name=bootscr\0" \ - "script_signed=boot.scr.imx-signed\0" \ - "bootscriptaddr=0x83200000\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "ethact=usb_ether\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx7s-warp.dtb\0" \ - "fdt_addr=" __stringify(CONFIG_SYS_FDT_ADDR)"\0" \ - "fdtovaddr=0x83100000\0" \ - "optee_addr=" __stringify(CONFIG_OPTEE_LOAD_ADDR)"\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "rootpart=" __stringify(CONFIG_WARP7_ROOT_PART) "\0" \ - "finduuid=part uuid mmc 0:${rootpart} uuid\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "ivt_offset=" __stringify(BOOTROM_IVT_HDR_OFFSET)"\0"\ - "warp7_auth_or_fail=hab_auth_img_or_fail ${hab_ivt_addr} ${filesize} 0;\0" \ - "do_bootscript_hab=" \ - "if test ${hab_enabled} -eq 1; then " \ - "setexpr hab_ivt_addr ${bootscriptaddr} - ${ivt_offset}; " \ - "setenv script ${script_signed}; " \ - "load mmc ${mmcdev}:${mmcpart} ${hab_ivt_addr} ${script}; " \ - "run warp7_auth_or_fail; " \ - "run bootscript; "\ - "fi;\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${bootscriptaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - BOOT_SCR_STRING \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "run do_bootscript_hab;" \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "fi; " \ - "fi; " \ - "fi" - -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* I2C configs */ -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_SPEED 100000 - -/* environment organization */ -#define CONFIG_ENV_SIZE SZ_8K - -#define CONFIG_ENV_OFFSET (8 * SZ_64K) -#define CONFIG_SYS_FSL_USDHC_NUM 1 - -#define CONFIG_SYS_MMC_ENV_DEV 0 -#define CONFIG_SYS_MMC_ENV_PART 0 - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET - -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 /* Only OTG1 port enabled */ - -#define CONFIG_IMX_THERMAL - -#define CONFIG_USBD_HS - -/* USB Device Firmware Update support */ -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -#define CONFIG_USBNET_DEV_ADDR "de:ad:be:af:00:01" - -/* Environment variable name to represent HAB enable state */ -#define HAB_ENABLED_ENVNAME "hab_enabled" - -#endif diff --git a/include/configs/wb45n.h b/include/configs/wb45n.h deleted file mode 100644 index 43de2e1..0000000 --- a/include/configs/wb45n.h +++ /dev/null @@ -1,138 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the WB45N CPU Module. - */ - -#ifndef __CONFIG_H__ -#define __CONFIG_H__ - -#include - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* general purpose I/O */ -#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ -#define CONFIG_AT91_GPIO - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_SYS - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE 0x20000000 -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */ - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 - -#define CONFIG_RBTREE -#define CONFIG_LZO - -/* Ethernet */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_ETHADDR C0:EE:40:00:00:00 -#define CONFIG_ENV_OVERWRITE 1 - -/* System */ -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END 0x23e00000 - -#ifdef CONFIG_SYS_USE_NANDFLASH -/* bootstrap + u-boot + env + linux in nandflash */ -#define CONFIG_ENV_OFFSET 0xa0000 -#define CONFIG_ENV_OFFSET_REDUND 0xc0000 -#define CONFIG_ENV_SIZE 0x20000 /* 1 block = 128 kB */ - -#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xe0000 0x280000; " \ - "run _mtd; bootm" - -#define MTDIDS_DEFAULT "nand0=atmel_nand" -#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:" \ - "128K(at91bs)," \ - "512K(u-boot)," \ - "128K(u-boot-env)," \ - "128K(redund-env)," \ - "2560K(kernel-a)," \ - "2560K(kernel-b)," \ - "38912K(rootfs-a)," \ - "38912K(rootfs-b)," \ - "46208K(user)," \ - "512K(logs)" - -#else -#error No boot method selected, please select 'CONFIG_SYS_USE_NANDFLASH' -#endif - -#define CONFIG_BOOTARGS "console=ttyS0,115200 earlyprintk " \ - "rw noinitrd mem=64M " \ - "rootfstype=ubifs root=ubi0:rootfs ubi.mtd=6" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "_mtd=mtdparts default; setenv bootargs ${bootargs} ${mtdparts}\0" \ - "autoload=no\0" \ - "autostart=no\0" \ - "ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \ - "\0" - -#define CONFIG_SYS_CBSIZE 256 -#define CONFIG_SYS_MAXARGS 16 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x6000 -#define CONFIG_SPL_STACK 0x308000 - -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SYS_MASTER_CLOCK 132096000 -#define CONFIG_SYS_AT91_PLLA 0x20c73f03 -#define CONFIG_SYS_MCKR 0x1301 -#define CONFIG_SYS_MCKR_CSS 0x1302 - -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif /* __CONFIG_H__ */ diff --git a/include/configs/wb50n.h b/include/configs/wb50n.h deleted file mode 100644 index 6e471f6..0000000 --- a/include/configs/wb50n.h +++ /dev/null @@ -1,112 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the WB50N CPU Module. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -/* ARM asynchronous clock */ -#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 -#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#ifndef CONFIG_SPL_BUILD -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* general purpose I/O */ -#define CONFIG_AT91_GPIO - -/* serial console */ -#define CONFIG_ATMEL_USART -#define CONFIG_USART_BASE ATMEL_BASE_DBGU -#define CONFIG_USART_ID ATMEL_ID_DBGU - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* SDRAM */ -#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS -#define CONFIG_SYS_SDRAM_SIZE 0x04000000 - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_INIT_SP_ADDR 0x310000 -#else -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) -#endif - -#define CONFIG_SYS_MEMTEST_START 0x21000000 -#define CONFIG_SYS_MEMTEST_END 0x22000000 - -/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 -/* our ALE is AD21 */ -#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) -/* our CLE is AD22 */ -#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* Ethernet Hardware */ -#define CONFIG_MACB -#define CONFIG_RMII -#define CONFIG_NET_RETRY_COUNT 20 -#define CONFIG_MACB_SEARCH_PHY -#define CONFIG_RGMII -#define CONFIG_ETHADDR C0:EE:40:00:00:00 -#define CONFIG_ENV_OVERWRITE 1 - -#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=no\0" \ - "autostart=no\0" - -/* bootstrap + u-boot + env in nandflash */ -#define CONFIG_ENV_OFFSET_REDUND 0xC0000 -#define CONFIG_BOOTCOMMAND \ - "nand read 0x22000000 0x000e0000 0x500000; " \ - "bootm" - -#define CONFIG_BOOTARGS \ - "rw rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs" - -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_MAXARGS 16 -#define CONFIG_SYS_PBSIZE \ - (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) - -/* SPL */ -#define CONFIG_SPL_MAX_SIZE 0x10000 -#define CONFIG_SPL_BSS_START_ADDR 0x20000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 - -#define CONFIG_SYS_MONITOR_LEN (512 << 10) - -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_PAGE_SIZE 0x800 -#define CONFIG_SYS_NAND_PAGE_COUNT 64 -#define CONFIG_SYS_NAND_OOBSIZE 64 -#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 -#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 - -#endif diff --git a/include/configs/woodburn.h b/include/configs/woodburn.h deleted file mode 100644 index 7f9ddb5..0000000 --- a/include/configs/woodburn.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Configuration for the woodburn board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "woodburn_common.h" - -/* Set TEXT at the beginning of the NOR flash */ - -#endif /* __CONFIG_H */ diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h deleted file mode 100644 index 5ad3dab..0000000 --- a/include/configs/woodburn_common.h +++ /dev/null @@ -1,203 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Configuration for the woodburn board. - */ - -#ifndef __WOODBURN_COMMON_CONFIG_H -#define __WOODBURN_COMMON_CONFIG_H - -#include - - /* High Level Configuration Options */ -#define CONFIG_MX35 -#define CONFIG_MX35_HCLK_FREQ 24000000 -#define CONFIG_SYS_FSL_CLK - -#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3 - -/* This is required to setup the ESDC controller */ - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024) - -/* - * Hardware drivers - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ -#define CONFIG_SYS_SPD_BUS_NUM 0 - -/* PMIC Controller */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_FSL -#define CONFIG_POWER_FSL_MC13892 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 -#define CONFIG_RTC_MC13XXX - -/* mmc driver */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 1 - -/* - * UART (console) - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* - * Command definition - */ - -#define CONFIG_NET_RETRY_COUNT 100 - - -#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ - -/* - * Ethernet on SOC (FEC) - */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE FEC_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x1 - -#define CONFIG_DISCOVER_PHY - -#define CONFIG_ARP_TIMEOUT 200UL - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x10000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* - * Physical Memory Map - */ -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR - -#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \ - IRAM_BASE_ADDR - \ - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \ - CONFIG_SYS_GBL_DATA_OFFSET) - -/* - * MTD Command for mtdparts - */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ -/* Monitor at beginning of flash */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE - -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) - -/* - * CFI FLASH driver setup - */ - -/* A non-standard buffered write algorithm */ - -/* - * NAND FLASH driver setup - */ -#define CONFIG_NAND_MXC_V1_1 -#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR) -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR) -#define CONFIG_MXC_NAND_HWECC -#define CONFIG_SYS_NAND_LARGEPAGE - -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* - * Default environment and default scripts - * to update uboot and load kernel - */ - -#define CONFIG_HOSTNAME "woodburn" -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip_sta=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \ - "addip=if test -n ${ipdyn};then run addip_dyn;" \ - "else run addip_sta;fi\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "addtty=setenv bootargs ${bootargs}" \ - " console=ttymxc0,${baudrate}\0" \ - "addmisc=setenv bootargs ${bootargs} ${misc}\0" \ - "loadaddr=80800000\0" \ - "kernel_addr_r=80800000\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - "bootfile=" CONFIG_HOSTNAME "/uImage\0" \ - "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \ - "flash_self=run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ - "run nfsargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r}\0" \ - "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \ - "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \ - "net_self=if run net_self_load;then " \ - "run ramargs addip addtty addmtd addmisc;" \ - "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \ - "else echo Images not loades;fi\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \ - "load=tftp ${loadaddr} ${u-boot}\0" \ - "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ - "update=protect off ${uboot_addr} +80000;" \ - "erase ${uboot_addr} +80000;" \ - "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \ - "upd=if run load;then echo Updating u-boot;if run update;" \ - "then echo U-Boot updated;" \ - "else echo Error updating u-boot !;" \ - "echo Board without bootloader !!;" \ - "fi;" \ - "else echo U-Boot not downloaded..exiting;fi\0" \ - "bootcmd=run net_nfs\0" - -#endif /* __CONFIG_H */ diff --git a/include/configs/woodburn_sd.h b/include/configs/woodburn_sd.h deleted file mode 100644 index 60d8a4b..0000000 --- a/include/configs/woodburn_sd.h +++ /dev/null @@ -1,30 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011, Stefano Babic - * - * (C) Copyright 2008-2010 Freescale Semiconductor, Inc. - * - * Configuration for the woodburn board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include "woodburn_common.h" - -/* Set TEXT in RAM */ - -/* - * SPL - */ - -#define CONFIG_SPL_MAX_SIZE (64 * 1024) /* 8 KB for stack */ -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK - -#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 -#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */ -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h deleted file mode 100644 index e260a63..0000000 --- a/include/configs/work_92105.h +++ /dev/null @@ -1,158 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * WORK Microwave work_92105 board configuration file - * - * (C) Copyright 2014 DENX Software Engineering GmbH - * Written-by: Albert ARIBAUD - */ - -#ifndef __CONFIG_WORK_92105_H__ -#define __CONFIG_WORK_92105_H__ - -/* SoC and board defines */ -#include -#include - -/* - * Define work_92105 machine type by hand -- done only for compatibility - * with original board code - */ -#define CONFIG_MACH_TYPE 736 - -#if !defined(CONFIG_SPL_BUILD) -#define CONFIG_SKIP_LOWLEVEL_INIT -#endif - -/* - * Memory configurations - */ -#define CONFIG_SYS_MALLOC_LEN SZ_1M -#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE -#define CONFIG_SYS_SDRAM_SIZE SZ_128M -#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) - -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ - - GENERATED_GBL_DATA_SIZE) - -/* - * Serial Driver - */ -#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ - -/* - * Ethernet Driver - */ - -#define CONFIG_PHY_SMSC -#define CONFIG_LPC32XX_ETH -#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ - -/* - * I2C driver - */ - -#define CONFIG_SYS_I2C_LPC32XX -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SPEED 350000 - -/* - * I2C EEPROM - */ - -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 - -/* - * I2C RTC - */ - -#define CONFIG_RTC_DS1374 - -/* - * U-Boot General Configurations - */ -#define CONFIG_SYS_CBSIZE 1024 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/* - * NAND chip timings for FIXME: which one? - */ - -#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 -#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 -#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 -#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 -#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 -#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 -#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 - -/* - * NAND - */ - -/* driver configuration */ -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_MAX_NAND_CHIPS 1 -#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE -#define CONFIG_NAND_LPC32XX_MLC - -/* - * GPIO - */ - -#define CONFIG_LPC32XX_GPIO - -/* - * SSP/SPI/DISPLAY - */ - -#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 -/* - * Environment - */ - -#define CONFIG_ENV_SIZE 0x00020000 -#define CONFIG_ENV_OFFSET 0x00100000 -#define CONFIG_ENV_OFFSET_REDUND 0x00120000 -#define CONFIG_ENV_ADDR 0x80000100 - -/* - * Boot Linux - */ -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x80008000 - -/* - * SPL - */ - -/* SPL will be executed at offset 0 */ -/* SPL will use SRAM as stack */ -#define CONFIG_SPL_STACK 0x0000FFF8 -/* Use the framework and generic lib */ -/* SPL will use serial */ -/* SPL will load U-Boot from NAND offset 0x40000 */ -#define CONFIG_SPL_NAND_DRIVERS -#define CONFIG_SPL_NAND_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 -#define CONFIG_SPL_PAD_TO 0x20000 -/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE - -/* - * Include SoC specific configuration - */ -#include - -#endif /* __CONFIG_WORK_92105_H__*/ diff --git a/include/configs/x530.h b/include/configs/x530.h deleted file mode 100644 index 2269d1e..0000000 --- a/include/configs/x530.h +++ /dev/null @@ -1,122 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2018 Allied Telesis Labs - */ - -#ifndef _CONFIG_X530_H -#define _CONFIG_X530_H - -/* - * High Level Configuration Options (easy to change) - */ - -#define CONFIG_DISPLAY_BOARDINFO_LATE - -#define CONFIG_SYS_TCLK 250000000 /* 250MHz */ - -/* - * NS16550 Configuration - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK -#if !defined(CONFIG_DM_SERIAL) -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_COM1 MV_UART_CONSOLE_BASE -#endif - -/* - * Serial Port configuration - * The following definitions let you select what serial you want to use - * for your console driver. - */ - -#define CONFIG_CONS_INDEX 1 /*Console on UART0 */ - -/* - * Commands configuration - */ -#define CONFIG_CMD_PCI - -/* NAND */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BBT_CUSTOM_SCAN -#define BBT_CUSTOM_SCAN_PAGE 0 -#define BBT_CUSTOM_SCAN_POSITION 2048 - -/* SPI NOR flash default params, used by sf commands */ - -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:240M(user),8M(errlog),8M(nand-bbt)" -#define MTDPARTS_MTDOOPS "errlog" - -/* Partition support */ - -/* Additional FS support/configuration */ - -/* USB/EHCI configuration */ -#define CONFIG_EHCI_IS_TDI - -/* Environment in SPI NOR flash */ -#define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ -#define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ -#define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ -#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET - -#define CONFIG_PHY_MARVELL /* there is a marvell phy */ -#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ - -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_SCAN_SHOW -#endif - -/* NAND */ -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_CMD_UBI -#define CONFIG_CMD_UBIFS -#define CONFIG_LZO -#define CONFIG_MTD_DEVICE -#define CONFIG_CMD_MTDPARTS - -#define CONFIG_SYS_MALLOC_LEN (4 << 20) - -#include - -/* - * Other required minimal configurations - */ -#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */ - -#define CONFIG_SYS_ALT_MEMTEST - -/* Keep device tree and initrd in low memory so the kernel can access them */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x10000000\0" \ - "initrd_high=0x10000000\0" - -#define CONFIG_SYS_LOAD_ADDR 0x1000000 -#define CONFIG_UBI_PART user -#define CONFIG_UBIFS_VOLUME user - -/* SPL */ - -/* Defines for SPL */ -#define CONFIG_SPL_SIZE (140 << 10) -#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) - -#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) -#define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) - -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MALLOC_SIMPLE -#endif - -#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) -#define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) - -/* SPL related SPI defines */ -#define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS - -#endif /* _CONFIG_X530_H */ diff --git a/include/configs/x600.h b/include/configs/x600.h deleted file mode 100644 index d4bbdcd..0000000 --- a/include/configs/x600.h +++ /dev/null @@ -1,238 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009, STMicroelectronics - All Rights Reserved - * Author(s): Vipin Kumar, for STMicroelectronics. - * - * Copyright (C) 2012, 2015 Stefan Roese - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_SPEAR600 /* SPEAr600 SoC */ -#define CONFIG_X600 /* on X600 board */ - -#include - -/* Timer, HZ specific defines */ -#define CONFIG_SYS_HZ_CLOCK 8300000 - -#define CONFIG_SYS_FLASH_BASE 0xf8000000 -/* Reserve 8KiB for SPL */ -#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ -#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO -#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ - CONFIG_SYS_SPL_LEN) -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MONITOR_LEN 0x60000 - -/* Serial Configuration (PL011) */ -#define CONFIG_SYS_SERIAL0 0xD0000000 -#define CONFIG_SYS_SERIAL1 0xD0080000 -#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ - (void *)CONFIG_SYS_SERIAL1 } -#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ - 57600, 115200 } -#define CONFIG_SYS_LOADS_BAUD_CHANGE - -/* NOR FLASH config options */ -#define CONFIG_ST_SMI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 -#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_MAX_FLASH_SECT 128 -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) - -/* NAND FLASH config options */ -#define CONFIG_NAND_FSMC -#define CONFIG_SYS_NAND_SELF_INIT -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE -#define CONFIG_MTD_ECC_SOFT -#define CONFIG_SYS_FSMC_NAND_8BIT -#define CONFIG_SYS_NAND_ONFI_DETECTION -#define CONFIG_NAND_ECC_BCH - -/* UBI/UBI config options */ - -/* Ethernet config options */ -#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ - -#define CONFIG_SPEAR_GPIO - -/* I2C config options */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_BASE 0xD0200000 -#define CONFIG_SYS_I2C_SPEED 400000 -#define CONFIG_SYS_I2C_SLAVE 0x02 -#define CONFIG_I2C_CHIPADDRESS 0x50 - -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 - -/* FPGA config options */ -#define CONFIG_FPGA_COUNT 1 - -/* USB EHCI options */ -#define CONFIG_USB_EHCI_SPEAR -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -/* - * U-Boot Environment placing definitions. - */ -#define CONFIG_ENV_SECT_SIZE 0x00010000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ - CONFIG_SYS_MONITOR_LEN) -#define CONFIG_ENV_SIZE 0x02000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* Miscellaneous configurable options */ -#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 -#define CONFIG_CMDLINE_TAG -#define CONFIG_SETUP_MEMORY_TAGS - -#define CONFIG_SYS_MEMTEST_START 0x00800000 -#define CONFIG_SYS_MEMTEST_END 0x04000000 -#define CONFIG_SYS_MALLOC_LEN (8 << 20) -#define CONFIG_SYS_LOAD_ADDR 0x00800000 - -#define CONFIG_HOSTNAME "x600" -#define CONFIG_UBI_PART ubi0 -#define CONFIG_UBIFS_VOLUME rootfs - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "u-boot_addr=1000000\0" \ - "u-boot=" CONFIG_HOSTNAME "/u-boot.spr\0" \ - "load=tftp ${u-boot_addr} ${u-boot}\0" \ - "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize};" \ - "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ - "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " ${filesize};" \ - "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \ - " +${filesize}\0" \ - "upd=run load update\0" \ - "ubifs=" CONFIG_HOSTNAME "/ubifs.img\0" \ - "part=" __stringify(CONFIG_UBI_PART) "\0" \ - "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \ - "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ - "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ - " ${filesize}\0" \ - "upd_ubifs=run load_ubifs update_ubifs\0" \ - "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ - "ubi create ${vol} 4000000\0" \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk-4.2/arm\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "boot_part=0\0" \ - "altbootcmd=if test $boot_part -eq 0;then " \ - "echo Switching to partition 1!;" \ - "setenv boot_part 1;" \ - "else; " \ - "echo Switching to partition 0!;" \ - "setenv boot_part 0;" \ - "fi;" \ - "saveenv;boot\0" \ - "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ - "root=ubi0:rootfs rootfstype=ubifs\0" \ - "kernel=" CONFIG_HOSTNAME "/uImage\0" \ - "kernel_fs=/boot/uImage \0" \ - "kernel_addr=1000000\0" \ - "dtb=" CONFIG_HOSTNAME "/" \ - CONFIG_HOSTNAME ".dtb\0" \ - "dtb_fs=/boot/" CONFIG_HOSTNAME ".dtb\0" \ - "dtb_addr=1800000\0" \ - "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ - "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ - "${baudrate}\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "net_nfs=run load_dtb load_kernel; " \ - "run nfsargs addip addcon addmtd addmisc;" \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ - "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ - "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ - " addcon addmisc addmtd;" \ - "bootm ${kernel_addr} - ${dtb_addr}\0" \ - "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \ - "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ - "ubifsload ${dtb_addr} ${dtb_fs};\0" \ - "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ - "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ - "bootcmd=run nand_ubifs\0" \ - "\0" - -/* Physical Memory Map */ -#define PHYS_SDRAM_1 0x00000000 -#define PHYS_SDRAM_1_MAXSIZE 0x40000000 - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 -#define CONFIG_SRAM_BASE 0xd2800000 -/* Preserve the last 2 lwords for the boot-counter */ -#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8) -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* - * SPL related defines - */ -#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00) -#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" - -/* - * Please select/define only one of the following - * Each definition corresponds to a supported DDR chip. - * DDR configuration is based on the following selection - */ -#define CONFIG_DDR_MT47H64M16 1 -#define CONFIG_DDR_MT47H32M16 0 -#define CONFIG_DDR_MT47H128M8 0 - -/* - * Synchronous/Asynchronous operation of DDR - * - * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation - * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation - * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation - */ -#define CONFIG_DDR_2HCLK 1 -#define CONFIG_DDR_HCLK 0 -#define CONFIG_DDR_PLL2 0 - -/* - * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported - * or not. Modify/Add to only these macros to define new boot types - */ -#define USB_BOOT_SUPPORTED 0 -#define PCIE_BOOT_SUPPORTED 0 -#define SNOR_BOOT_SUPPORTED 1 -#define NAND_BOOT_SUPPORTED 1 -#define PNOR_BOOT_SUPPORTED 0 -#define TFTP_BOOT_SUPPORTED 0 -#define UART_BOOT_SUPPORTED 0 -#define SPI_BOOT_SUPPORTED 0 -#define I2C_BOOT_SUPPORTED 0 -#define MMC_BOOT_SUPPORTED 0 - -#endif /* __CONFIG_H */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h deleted file mode 100644 index 5a33223..0000000 --- a/include/configs/x86-chromebook.h +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2015 Google, Inc - */ - -#ifndef _X86_CHROMEBOOK_H -#define _X86_CHROMEBOOK_H - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_X86_REFCODE_ADDR 0xffea0000 -#define CONFIG_X86_REFCODE_RUN_ADDR 0 - -#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff - -#define CONFIG_BIOSEMU -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_OFFSET 0x003f8000 - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \ - "stdout=vidconsole,serial\0" \ - "stderr=vidconsole,serial\0" - -#endif diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h deleted file mode 100644 index 54214f9..0000000 --- a/include/configs/x86-common.h +++ /dev/null @@ -1,144 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - */ - -#include - -#ifndef __CONFIG_X86_COMMON_H -#define __CONFIG_X86_COMMON_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_PHYSMEM - -#define CONFIG_LMB - -#undef CONFIG_ZLIB -#undef CONFIG_GZIP -#define CONFIG_SYS_BOOTM_LEN (16 << 20) - -/* SATA AHCI storage */ -#ifdef CONFIG_SCSI_AHCI -#define CONFIG_LBA48 -#define CONFIG_SYS_64BIT_LBA - -#endif - -/* Generic TPM interfaced through LPC bus */ -#define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000 - -/*----------------------------------------------------------------------- - * Real Time Clock Configuration - */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS - -/*----------------------------------------------------------------------- - * Serial Configuration - */ -#define CONFIG_SYS_NS16550_PORT_MAPPED - -/*----------------------------------------------------------------------- - * Command line configuration. - */ - -#ifndef CONFIG_BOOTCOMMAND -#define CONFIG_BOOTCOMMAND \ - "ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_CBSIZE 512 - -#define CONFIG_SYS_MEMTEST_START 0x00100000 -#define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x20000000 - -/*----------------------------------------------------------------------- - * CPU Features - */ - -#define CONFIG_SYS_STACK_SIZE (32 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x200000 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/*----------------------------------------------------------------------- - * Environment configuration - */ -#define CONFIG_ENV_SIZE 0x01000 - -/*----------------------------------------------------------------------- - * PCI configuration - */ -#define CONFIG_PCI_CONFIG_HOST_BRIDGE - -/*----------------------------------------------------------------------- - * USB configuration - */ - -#define CONFIG_TFTP_TSIZE -#define CONFIG_BOOTP_BOOTFILESIZE - -/* Default environment */ -#define CONFIG_ROOTPATH "/opt/nfsroot" -#define CONFIG_HOSTNAME "x86" -#define CONFIG_BOOTFILE "bzImage" -#define CONFIG_LOADADDR 0x1000000 -#define CONFIG_RAMDISK_ADDR 0x4000000 -#if defined(CONFIG_GENERATE_ACPI_TABLE) || defined(CONFIG_EFI_STUB) -#define CONFIG_OTHBOOTARGS "othbootargs=\0" -#else -#define CONFIG_OTHBOOTARGS "othbootargs=acpi=off\0" -#endif - -#if defined(CONFIG_DISTRO_DEFAULTS) -#define DISTRO_BOOTENV BOOTENV -#else -#define DISTRO_BOOTENV -#endif - -#define CONFIG_EXTRA_ENV_SETTINGS \ - DISTRO_BOOTENV \ - CONFIG_STD_DEVICES_SETTINGS \ - "pciconfighost=1\0" \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - CONFIG_OTHBOOTARGS \ - "scriptaddr=0x7000000\0" \ - "kernel_addr_r=0x1000000\0" \ - "ramdisk_addr_r=0x4000000\0" \ - "ramdiskfile=initramfs.gz\0" - - -#define CONFIG_RAMBOOTCOMMAND \ - "setenv bootargs root=/dev/ram rw " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftpboot $kernel_addr_r $bootfile;" \ - "tftpboot $ramdisk_addr_r $ramdiskfile;" \ - "zboot $kernel_addr_r 0 $ramdisk_addr_r $filesize" - -#define CONFIG_NFSBOOTCOMMAND \ - "setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs;" \ - "tftpboot $kernel_addr_r $bootfile;" \ - "zboot $kernel_addr_r" - - -#endif /* __CONFIG_H */ diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h deleted file mode 100644 index afc4b82..0000000 --- a/include/configs/xfi3.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Marek Vasut - */ -#ifndef __CONFIGS_XFI3_H__ -#define __CONFIGS_XFI3_H__ - -/* U-Boot Commands */ - -/* Memory configuration */ -#define PHYS_SDRAM_1 0x40000000 /* Base address */ -#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */ -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -/* Environment */ -#define CONFIG_ENV_SIZE (16 * 1024) -#define CONFIG_ENV_OVERWRITE - -/* Booting Linux */ -#define CONFIG_BOOTFILE "uImage" -#define CONFIG_LOADADDR 0x42000000 -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -/* LCD */ -#ifdef CONFIG_VIDEO -#define CONFIG_VIDEO_FONT_4X6 -#define CONFIG_VIDEO_MXS_MODE_SYSTEM -#define CONFIG_SYS_BLACK_IN_WRITE -#define LCD_BPP LCD_COLOR16 -#endif - -/* USB */ -#ifdef CONFIG_CMD_USB -#define CONFIG_EHCI_MXS_PORT0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 - -#define CONFIG_NETCONSOLE -#endif - -/* The rest of the configuration is shared */ -#include - -#endif /* __CONFIGS_XFI3_H__ */ diff --git a/include/configs/xilinx_versal.h b/include/configs/xilinx_versal.h deleted file mode 100644 index f426127..0000000 --- a/include/configs/xilinx_versal.h +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx Versal - * (C) Copyright 2016 - 2018 Xilinx, Inc. - * Michal Simek - * - * Based on Configuration for Xilinx ZynqMP - */ - -#ifndef __XILINX_VERSAL_H -#define __XILINX_VERSAL_H - -#define CONFIG_REMAKE_ELF - -/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ - -/* Generic Interrupt Controller Definitions */ -#define GICD_BASE 0xF9000000 -#define GICR_BASE 0xF9080000 - -#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 - -#define CONFIG_SYS_MEMTEST_START 0 -#define CONFIG_SYS_MEMTEST_END 1000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ -#if CONFIG_COUNTER_FREQUENCY -# define COUNTER_FREQUENCY CONFIG_COUNTER_FREQUENCY -#endif - -/* Serial setup */ -#define CONFIG_ARM_DCC -#define CONFIG_CPU_ARMV8 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 4800, 9600, 19200, 38400, 57600, 115200 } - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_MAY_FAIL - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 - -/* Monitor Command Prompt */ -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_MAXARGS 64 - -#if defined(CONFIG_CMD_DFU) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_THOR_RESET_OFF -#define DFU_ALT_INFO_RAM \ - "dfu_ram_info=" \ - "setenv dfu_alt_info " \ - "Image ram $kernel_addr_r $kernel_size_r\\\\;" \ - "system.dtb ram $fdt_addr_r $fdt_size_r\0" \ - "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ - "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" - -#define DFU_ALT_INFO \ - DFU_ALT_INFO_RAM -#endif - -#if !defined(DFU_ALT_INFO) -# define DFU_ALT_INFO -#endif - -/* Ethernet driver */ -#if defined(CONFIG_ZYNQ_GEM) -# define CONFIG_NET_MULTI -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define PHY_ANEG_TIMEOUT 20000 -#endif - -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) - -#define CONFIG_CLOCKS - -#define ENV_MEM_LAYOUT_SETTINGS \ - "fdt_high=10000000\0" \ - "fdt_addr_r=0x40000000\0" \ - "fdt_size_r=0x400000\0" \ - "pxefile_addr_r=0x10000000\0" \ - "kernel_addr_r=0x18000000\0" \ - "kernel_size_r=0x10000000\0" \ - "scriptaddr=0x20000000\0" \ - "ramdisk_addr_r=0x02100000\0" \ - "script_offset_f=0x7F80000\0" \ - "script_size_f=0x80000\0" - -#if defined(CONFIG_MMC_SDHCI_ZYNQ) -# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) -#else -# define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#if defined(CONFIG_ZYNQMP_GQSPI) || defined(CONFIG_CADENCE_OSPI_VERSAL) -# define BOOT_TARGET_DEVICES_XSPI(func) func(XSPI, xspi, 0) -#else -# define BOOT_TARGET_DEVICES_XSPI(func) -#endif - -#define BOOTENV_DEV_XSPI(devtypeu, devtypel, instance) \ - "bootcmd_xspi0=sf probe 0 0 0 && " \ - "sf read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_XSPI(devtypeu, devtypel, instance) \ - "xspi " - -#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) - -#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ - "jtag " - -#define BOOT_TARGET_DEVICES_DFU_USB(func) func(DFU_USB, dfu_usb, 0) - -#define BOOTENV_DEV_DFU_USB(devtypeu, devtypel, instance) \ - "bootcmd_dfu_usb=setenv dfu_alt_info boot.scr ram $scriptaddr " \ - "$script_size_f; dfu 0 ram 0 && source $scriptaddr; " \ - "echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_DFU_USB(devtypeu, devtypel, instance) \ - "dfu_usb " - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICES_JTAG(func) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_XSPI(func) \ - BOOT_TARGET_DEVICES_DFU_USB(func) \ - func(PXE, pxe, na) \ - func(DHCP, dhcp, na) - -#include - -/* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV \ - DFU_ALT_INFO -#endif - -#endif /* __XILINX_VERSAL_H */ diff --git a/include/configs/xilinx_versal_mini.h b/include/configs/xilinx_versal_mini.h deleted file mode 100644 index ee305e0..0000000 --- a/include/configs/xilinx_versal_mini.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Configuration for Xilinx Versal MINI configuration - * - * (C) Copyright 2018-2019 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_VERSAL_MINI_H -#define __CONFIG_VERSAL_MINI_H - -#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 - -#define CONFIG_EXTRA_ENV_SETTINGS - -#include - -/* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_ZLIB -#undef CONFIG_GZIP -#undef CONFIG_CMD_ENV - -/* BOOTP options */ -#undef CONFIG_BOOTP_BOOTFILESIZE -#undef CONFIG_BOOTP_MAY_FAIL - -#undef CONFIG_SYS_CBSIZE -#define CONFIG_SYS_CBSIZE 1024 - -#endif /* __CONFIG_VERSAL_MINI_H */ diff --git a/include/configs/xilinx_versal_mini_qspi.h b/include/configs/xilinx_versal_mini_qspi.h deleted file mode 100644 index 8572b8b..0000000 --- a/include/configs/xilinx_versal_mini_qspi.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Configuration for Xilinx Versal QSPI Flash utility - * - * (C) Copyright 2018-2019 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_VERSAL_MINI_QSPI_H -#define __CONFIG_VERSAL_MINI_QSPI_H - -#include - -#undef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) - -#endif /* __CONFIG_VERSAL_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h deleted file mode 100644 index ee1ceeb..0000000 --- a/include/configs/xilinx_zynqmp.h +++ /dev/null @@ -1,265 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP - * (C) Copyright 2014 - 2015 Xilinx, Inc. - * Michal Simek - * - * Based on Configuration for Versatile Express - */ - -#ifndef __XILINX_ZYNQMP_H -#define __XILINX_ZYNQMP_H - -#define CONFIG_REMAKE_ELF - -/* #define CONFIG_ARMV8_SWITCH_TO_EL1 */ - -/* Generic Interrupt Controller Definitions */ -#define CONFIG_GICV2 -#define GICD_BASE 0xF9010000 -#define GICC_BASE 0xF9020000 - -#ifndef CONFIG_SYS_MEMTEST_SCRATCH -# define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 -#endif - -#define CONFIG_SYS_MEMTEST_START 0 -#define CONFIG_SYS_MEMTEST_END 1000 - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE - -/* Generic Timer Definitions - setup in EL3. Setup by ATF for other cases */ -#if !defined(COUNTER_FREQUENCY) -# define COUNTER_FREQUENCY 100000000 -#endif - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x2000000) - -/* Serial setup */ -#define CONFIG_ARM_DCC -#define CONFIG_CPU_ARMV8 - -#define CONFIG_SYS_BAUDRATE_TABLE \ - { 4800, 9600, 19200, 38400, 57600, 115200 } - -/* BOOTP options */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_MAY_FAIL - -#ifdef CONFIG_NAND_ARASAN -# define CONFIG_SYS_MAX_NAND_DEVICE 1 -# define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -#if defined(CONFIG_SPL_BUILD) -#define CONFIG_ZYNQMP_PSU_INIT_ENABLED -#endif - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LOAD_ADDR 0x8000000 - -#if defined(CONFIG_ZYNQMP_USB) -#define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x1800000 -#define DFU_DEFAULT_POLL_TIMEOUT 300 -#define CONFIG_THOR_RESET_OFF -#define DFU_ALT_INFO_RAM \ - "dfu_ram_info=" \ - "setenv dfu_alt_info " \ - "Image ram $kernel_addr $kernel_size\\\\;" \ - "system.dtb ram $fdt_addr $fdt_size\0" \ - "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ - "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" - -#define DFU_ALT_INFO \ - DFU_ALT_INFO_RAM - -#ifndef CONFIG_SPL_BUILD -# define PARTS_DEFAULT \ - "partitions=uuid_disk=${uuid_gpt_disk};" \ - "name=""boot"",size=16M,uuid=${uuid_gpt_boot};" \ - "name=""Linux"",size=-M,uuid=${uuid_gpt_Linux}\0" -#endif -#endif - -#if !defined(DFU_ALT_INFO) -# define DFU_ALT_INFO -#endif - -#if !defined(PARTS_DEFAULT) -# define PARTS_DEFAULT -#endif - -/* Monitor Command Prompt */ -/* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 2048 -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_PANIC_HANG -#define CONFIG_SYS_MAXARGS 64 - -/* Ethernet driver */ -#if defined(CONFIG_ZYNQ_GEM) -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define PHY_ANEG_TIMEOUT 20000 -#endif - -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) - -#define CONFIG_CLOCKS - -#define ENV_MEM_LAYOUT_SETTINGS \ - "fdt_high=10000000\0" \ - "fdt_addr_r=0x40000000\0" \ - "pxefile_addr_r=0x10000000\0" \ - "kernel_addr_r=0x18000000\0" \ - "scriptaddr=0x20000000\0" \ - "ramdisk_addr_r=0x02100000\0" \ - "script_offset_f=0x3e80000\0" \ - "script_size_f=0x80000\0" \ - -#if defined(CONFIG_MMC_SDHCI_ZYNQ) -# define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) -#else -# define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#if defined(CONFIG_SATA_CEVA) -# define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) -#else -# define BOOT_TARGET_DEVICES_SCSI(func) -#endif - -#if defined(CONFIG_ZYNQMP_USB) -# define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) -#else -# define BOOT_TARGET_DEVICES_USB(func) -#endif - -#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) -# define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) -#else -# define BOOT_TARGET_DEVICES_PXE(func) -#endif - -#if defined(CONFIG_CMD_DHCP) -# define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) -#else -# define BOOT_TARGET_DEVICES_DHCP(func) -#endif - -#if defined(CONFIG_ZYNQMP_GQSPI) -# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, 0) -#else -# define BOOT_TARGET_DEVICES_QSPI(func) -#endif - -#if defined(CONFIG_NAND_ARASAN) -# define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, 0) -#else -# define BOOT_TARGET_DEVICES_NAND(func) -#endif - -#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "=sf probe " #instance " 0 0 && " \ - "sf read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_" #devtypel #instance "= nand info && " \ - "nand read $scriptaddr $script_offset_f $script_size_f && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - #devtypel #instance " " - -#define BOOT_TARGET_DEVICES_JTAG(func) func(JTAG, jtag, na) - -#define BOOTENV_DEV_JTAG(devtypeu, devtypel, instance) \ - "bootcmd_jtag=source $scriptaddr; echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_JTAG(devtypeu, devtypel, instance) \ - "jtag " - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICES_JTAG(func) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_QSPI(func) \ - BOOT_TARGET_DEVICES_NAND(func) \ - BOOT_TARGET_DEVICES_USB(func) \ - BOOT_TARGET_DEVICES_SCSI(func) \ - BOOT_TARGET_DEVICES_PXE(func) \ - BOOT_TARGET_DEVICES_DHCP(func) - -#include - -/* Initial environment variables */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV \ - DFU_ALT_INFO -#endif - -/* SPL can't handle all huge variables - define just DFU */ -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) -#undef CONFIG_EXTRA_ENV_SETTINGS -# define CONFIG_EXTRA_ENV_SETTINGS \ - "dfu_alt_info_ram=uboot.bin ram 0x8000000 0x1000000;" \ - "atf-uboot.ub ram 0x10000000 0x1000000;" \ - "Image ram 0x80000 0x3f80000;" \ - "system.dtb ram 0x4000000 0x100000\0" \ - "dfu_bufsiz=0x1000\0" -#endif - -#define CONFIG_SPL_STACK 0xfffffffc -#define CONFIG_SPL_MAX_SIZE 0x40000 - -/* Just random location in OCM */ -#define CONFIG_SPL_BSS_START_ADDR 0x0 -#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 - -#if defined(CONFIG_SPL_SPI_FLASH_SUPPORT) -# define CONFIG_SYS_SPI_KERNEL_OFFS 0x80000 -# define CONFIG_SYS_SPI_ARGS_OFFS 0xa0000 -# define CONFIG_SYS_SPI_ARGS_SIZE 0xa0000 -#endif - -/* u-boot is like dtb */ -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "u-boot.bin" -#define CONFIG_SYS_SPL_ARGS_ADDR 0x8000000 - -/* ATF is my kernel image */ -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "atf-uboot.ub" - -/* FIT load address for RAM boot */ -#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 - -/* MMC support */ -#ifdef CONFIG_MMC_SDHCI_ZYNQ -# define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 /* unused */ -# define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 /* unused */ -# define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 /* unused */ -# define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_DFU) -# undef CONFIG_CMD_BOOTD -# define CONFIG_SPL_ENV_SUPPORT -# define CONFIG_SPL_HASH_SUPPORT -# define CONFIG_ENV_MAX_ENTRIES 10 -#endif - -#define CONFIG_SYS_SPL_MALLOC_START 0x20000000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 - -#ifdef CONFIG_SPL_SYS_MALLOC_SIMPLE -# error "Disable CONFIG_SPL_SYS_MALLOC_SIMPLE. Full malloc needs to be used" -#endif - -#define CONFIG_BOARD_EARLY_INIT_F - -#endif /* __XILINX_ZYNQMP_H */ diff --git a/include/configs/xilinx_zynqmp_mini.h b/include/configs/xilinx_zynqmp_mini.h deleted file mode 100644 index a692289..0000000 --- a/include/configs/xilinx_zynqmp_mini.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP Flash utility - * - * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_ZYNQMP_MINI_H -#define __CONFIG_ZYNQMP_MINI_H - -#define CONFIG_SYS_MEMTEST_SCRATCH 0xfffc0000 - -#define CONFIG_EXTRA_ENV_SETTINGS - -#include - -/* Undef unneeded configs */ -#undef CONFIG_BOOTCOMMAND -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_SYS_MALLOC_LEN -#undef CONFIG_ZLIB -#undef CONFIG_GZIP -#undef CONFIG_CMD_ENV -#undef CONFIG_SYS_INIT_SP_ADDR - -/* BOOTP options */ -#undef CONFIG_BOOTP_BOOTFILESIZE -#undef CONFIG_BOOTP_MAY_FAIL - -#endif /* __CONFIG_ZYNQMP_MINI_H */ diff --git a/include/configs/xilinx_zynqmp_mini_emmc.h b/include/configs/xilinx_zynqmp_mini_emmc.h deleted file mode 100644 index a7ae30d..0000000 --- a/include/configs/xilinx_zynqmp_mini_emmc.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP eMMC Flash utility - * - * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_ZYNQMP_MINI_EMMC_H -#define __CONFIG_ZYNQMP_MINI_EMMC_H - -#include - -#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MALLOC_LEN 0x800000 - -#endif /* __CONFIG_ZYNQMP_MINI_EMMC_H */ diff --git a/include/configs/xilinx_zynqmp_mini_nand.h b/include/configs/xilinx_zynqmp_mini_nand.h deleted file mode 100644 index 692f6e5..0000000 --- a/include/configs/xilinx_zynqmp_mini_nand.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP Nand Flash utility - * - * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_ZYNQMP_MINI_NAND_H -#define __CONFIG_ZYNQMP_MINI_NAND_H - -#include - -#define CONFIG_SYS_SDRAM_SIZE 0x1000000 -#define CONFIG_SYS_SDRAM_BASE 0x0 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x40000) -#define CONFIG_SYS_MALLOC_LEN 0x800000 - -#endif /* __CONFIG_ZYNQMP_MINI_NAND_H */ diff --git a/include/configs/xilinx_zynqmp_mini_qspi.h b/include/configs/xilinx_zynqmp_mini_qspi.h deleted file mode 100644 index 129af6e..0000000 --- a/include/configs/xilinx_zynqmp_mini_qspi.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuration for Xilinx ZynqMP QSPI Flash utility - * - * (C) Copyright 2018 Xilinx, Inc. - * Michal Simek - * Siva Durga Prasad Paladugu - */ - -#ifndef __CONFIG_ZYNQMP_MINI_QSPI_H -#define __CONFIG_ZYNQMP_MINI_QSPI_H - -#include - -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x20000) -#define CONFIG_SYS_MALLOC_LEN 0x2000 - -#endif /* __CONFIG_ZYNQMP_MINI_QSPI_H */ diff --git a/include/configs/xilinx_zynqmp_r5.h b/include/configs/xilinx_zynqmp_r5.h deleted file mode 100644 index 4eb3312..0000000 --- a/include/configs/xilinx_zynqmp_r5.h +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * (C) Copyright 2018 Xilinx, Inc. (Michal Simek) - */ - -#ifndef __CONFIG_ZYNQMP_R5_H -#define __CONFIG_ZYNQMP_R5_H - -#define CONFIG_EXTRA_ENV_SETTINGS - -/* CPU clock */ -#define CONFIG_CPU_FREQ_HZ 500000000 - -/* Serial drivers */ -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -# define CONFIG_ENV_SIZE (128 << 10) - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Boot configuration */ -#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ - -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ - -#define CONFIG_SYS_MALLOC_LEN 0x1400000 - -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -/* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) - -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* 0x0 - 0x40 is used for placing exception vectors */ -#define CONFIG_SYS_MEMTEST_START 0x40 -#define CONFIG_SYS_MEMTEST_END 0x100 -#define CONFIG_SYS_MEMTEST_SCRATCH 0 - -#endif /* __CONFIG_ZYNQ_ZYNQMP_R5_H */ diff --git a/include/configs/xpedite517x.h b/include/configs/xpedite517x.h deleted file mode 100644 index 23f0389..0000000 --- a/include/configs/xpedite517x.h +++ /dev/null @@ -1,650 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009 Extreme Engineering Solutions, Inc. - * Copyright 2007-2008 Freescale Semiconductor, Inc. - */ - -/* - * xpedite517x board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_SYS_BOARD_NAME "XPedite5170" -#define CONFIG_SYS_FORM_3U_VPX 1 -#define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ -#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ -#define CONFIG_ALTIVEC 1 - -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CONFIG_PCIE1 1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -/* - * DDR config - */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ -#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ -#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ - -/* - * virtual address to be used for temporary mappings. There - * should be 128k free at this VA. - */ -#define CONFIG_SYS_SCRATCH_VA 0xe0000000 - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC86xx */ - -/* - * L2CR setup - */ -#define CONFIG_SYS_L2 -#define L2_INIT 0 -#define L2_ENABLE (L2CR_L2E) - -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR -#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - -/* - * Diagnostics - */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY |\ - CONFIG_SYS_POST_I2C) -/* The XPedite5170 can host an XMC which has an EEPROM at address 0x50 */ -#define I2C_ADDR_IGNORE_LIST {0x50} - -/* - * Memory map - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable - * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable - * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable - * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable - * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable - * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable - * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable - * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable - * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable - */ - -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_4 | LCRR_EADC_3) - -/* - * NAND flash configuration - */ -#define CONFIG_SYS_NAND_BASE 0xef800000 -#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE2} -#define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_NAND_ACTL -#define CONFIG_SYS_NAND_ACTL_ALE (1 << 14) /* C_LA14 */ -#define CONFIG_SYS_NAND_ACTL_CLE (1 << 15) /* C_LA15 */ -#define CONFIG_SYS_NAND_ACTL_NCE 0 /* NCE not controlled by ADDR */ -#define CONFIG_SYS_NAND_ACTL_DELAY 25 -#define CONFIG_JFFS2_NAND - -/* - * NOR flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xf8000000 -#define CONFIG_SYS_FLASH_BASE2 0xf0000000 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff00000, 0xc0000}, \ - {0xf7f00000, 0xc0000} } -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ - -/* - * Chip select configuration - */ -/* NOR Flash 0 on CS0 */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE |\ - BR_PS_16 |\ - BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB |\ - OR_GPCM_CSNT |\ - OR_GPCM_XACS |\ - OR_GPCM_ACS_DIV2 |\ - OR_GPCM_SCY_8 |\ - OR_GPCM_TRLX |\ - OR_GPCM_EHTR |\ - OR_GPCM_EAD) - -/* NOR Flash 1 on CS1 */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 |\ - BR_PS_16 |\ - BR_V) -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM - -/* NAND flash on CS2 */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE |\ - BR_PS_8 |\ - BR_V) -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB |\ - OR_GPCM_BCTLD |\ - OR_GPCM_CSNT |\ - OR_GPCM_ACS_DIV4 |\ - OR_GPCM_SCY_4 |\ - OR_GPCM_TRLX |\ - OR_GPCM_EHTR) - -/* Optional NAND flash on CS3 */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 |\ - BR_PS_8 |\ - BR_V) -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM - -/* - * Use L1 as initial stack - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 100000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 100000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* PEX8518 slave I2C interface */ -#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70 - -/* I2C DS1631 temperature sensor */ -#define CONFIG_SYS_I2C_LM90_ADDR 0x4c - -/* I2C EEPROM - AT24C128B */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ - -/* I2C RTC */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 - -/* GPIO */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 -#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c -#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e -#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f -#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 -#define CONFIG_SYS_I2C_PCA9553_ADDR 0x62 - -/* - * PU = pulled high, PD = pulled low - * I = input, O = output, IO = input/output - */ -/* PCA9557 @ 0x18*/ -#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */ -#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */ -#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */ -#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */ -#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */ -#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */ - -/* PCA9557 @ 0x1c*/ -#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */ -#define CONFIG_SYS_PCA953X_PLUG_GPIO0 0x02 /* Samtec connector GPIO */ -#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */ -#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */ -#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */ -#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */ -#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */ -#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */ - -/* PCA9557 @ 0x1e*/ -#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */ -#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */ -#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */ -#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */ -#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */ -#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; VPX Geographical address parity */ -#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; VPX P1 SYSCON */ - -/* PCA9557 @ 0x1f */ -#define CONFIG_SYS_PCA953X_VPX_GPIO0 0x01 /* PU; VPX P15 GPIO */ -#define CONFIG_SYS_PCA953X_VPX_GPIO1 0x02 /* PU; VPX P15 GPIO */ -#define CONFIG_SYS_PCA953X_VPX_GPIO2 0x04 /* PU; VPX P15 GPIO */ -#define CONFIG_SYS_PCA953X_VPX_GPIO3 0x08 /* PU; VPX P15 GPIO */ - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -/* PCIE1 - PEX8518 */ -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */ -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ - -/* PCIE2 - VPX P1 */ -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */ - -/* - * Networking options - */ -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC1_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define CONFIG_HAS_ETH0 - -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) -#define TSEC2_PHY_ADDR 2 -#define TSEC2_PHYIDX 0 -#define CONFIG_HAS_ETH1 - -/* - * BAT mappings - */ -#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) -#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT |\ - BATU_BL_1M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT) -#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU -#endif - -/* - * BAT0 2G Cacheable, non-guarded - * 0x0000_0000 2G DDR - */ -#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U - -/* - * BAT1 1G Cache-inhibited, guarded - * 0x8000_0000 1G PCI-Express 1 Memory - */ -#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCIE1_MEM_PHYS |\ - BATU_BL_1G |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCIE1_MEM_PHYS |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U - -/* - * BAT2 512M Cache-inhibited, guarded - * 0xc000_0000 512M PCI-Express 2 Memory - */ -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE2_MEM_PHYS |\ - BATU_BL_512M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCIE2_MEM_PHYS |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U - -/* - * BAT3 1M Cache-inhibited, guarded - * 0xe000_0000 1M CCSR - */ -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR |\ - BATU_BL_1M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U - -/* - * BAT4 32M Cache-inhibited, guarded - * 0xe200_0000 16M PCI-Express 1 I/O - * 0xe300_0000 16M PCI-Express 2 I/0 - */ -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_PHYS |\ - BATU_BL_32M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE1_IO_PHYS |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U - -/* - * BAT5 128K Cacheable, non-guarded - * 0xe400_1000 128K Init RAM for stack in the CPU DCache (no backing memory) - */ -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR |\ - BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR |\ - BATU_BL_128K |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L -#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U - -/* - * BAT6 256M Cache-inhibited, guarded - * 0xf000_0000 256M FLASH - */ -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE2 |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE |\ - BATU_BL_256M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE |\ - BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U - -/* Map the last 1M of flash where we're running from reset */ -#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE |\ - BATU_BL_1M |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY |\ - BATL_PP_RW |\ - BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY - -/* - * BAT7 64M Cache-inhibited, guarded - * 0xe800_0000 64K NAND FLASH - * 0xe804_0000 128K DUART Registers - */ -#define CONFIG_SYS_DBAT7L (CONFIG_SYS_NAND_BASE |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT |\ - BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT7U (CONFIG_SYS_NAND_BASE |\ - BATU_BL_512K |\ - BATU_VS |\ - BATU_VP) -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_NAND_BASE |\ - BATL_PP_RW |\ - BATL_CACHEINHIBIT) -#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) - -/* - * Flash memory map: - * fffc0000 - ffffffff Pri FDT (256KB) - * fff80000 - fffbffff Pri U-Boot Environment (256 KB) - * fff00000 - fff7ffff Pri U-Boot (512 KB) - * fef00000 - ffefffff Pri OS image (16MB) - * f8000000 - feefffff Pri OS Use/Filesystem (111MB) - * - * f7fc0000 - f7ffffff Sec FDT (256KB) - * f7f80000 - f7fbffff Sec U-Boot Environment (256 KB) - * f7f00000 - f7f7ffff Sec U-Boot (512 KB) - * f6f00000 - f7efffff Sec OS image (16MB) - * f0000000 - f6efffff Sec OS Use/Filesystem (111MB) - */ -#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000) -#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000) -#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000) -#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000) -#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) -#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000) - -#define CONFIG_PROG_UBOOT1 \ - "$download_cmd $loadaddr $ubootfile; " \ - "if test $? -eq 0; then " \ - "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ - "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ - "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ - "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ - "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ - "if test $? -ne 0; then " \ - "echo PROGRAM FAILED; " \ - "else; " \ - "echo PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_UBOOT2 \ - "$download_cmd $loadaddr $ubootfile; " \ - "if test $? -eq 0; then " \ - "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ - "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ - "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ - "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ - "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ - "if test $? -ne 0; then " \ - "echo PROGRAM FAILED; " \ - "else; " \ - "echo PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_BOOT_OS_NET \ - "$download_cmd $osaddr $osfile; " \ - "if test $? -eq 0; then " \ - "if test -n $fdtaddr; then " \ - "$download_cmd $fdtaddr $fdtfile; " \ - "if test $? -eq 0; then " \ - "bootm $osaddr - $fdtaddr; " \ - "else; " \ - "echo FDT DOWNLOAD FAILED; " \ - "fi; " \ - "else; " \ - "bootm $osaddr; " \ - "fi; " \ - "else; " \ - "echo OS DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_OS1 \ - "$download_cmd $osaddr $osfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ - "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ - "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo OS PROGRAM FAILED; " \ - "else; " \ - "echo OS PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo OS DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_OS2 \ - "$download_cmd $osaddr $osfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ - "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ - "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo OS PROGRAM FAILED; " \ - "else; " \ - "echo OS PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo OS DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_FDT1 \ - "$download_cmd $fdtaddr $fdtfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ - "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ - "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo FDT PROGRAM FAILED; " \ - "else; " \ - "echo FDT PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo FDT DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_FDT2 \ - "$download_cmd $fdtaddr $fdtfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ - "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ - "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo FDT PROGRAM FAILED; " \ - "else; " \ - "echo FDT PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo FDT DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=yes\0" \ - "download_cmd=tftp\0" \ - "console_args=console=ttyS0,115200\0" \ - "root_args=root=/dev/nfs rw\0" \ - "misc_args=ip=on\0" \ - "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ - "bootfile=/home/user/file\0" \ - "osfile=/home/user/board.uImage\0" \ - "fdtfile=/home/user/board.dtb\0" \ - "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=0x1e00000\0" \ - "osaddr=0x1000000\0" \ - "loadaddr=0x1000000\0" \ - "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ - "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ - "prog_os1="CONFIG_PROG_OS1"\0" \ - "prog_os2="CONFIG_PROG_OS2"\0" \ - "prog_fdt1="CONFIG_PROG_FDT1"\0" \ - "prog_fdt2="CONFIG_PROG_FDT2"\0" \ - "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ - "bootcmd_flash1=run set_bootargs; " \ - "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ - "bootcmd_flash2=run set_bootargs; " \ - "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ - "bootcmd=run bootcmd_flash1\0" -#endif /* __CONFIG_H */ diff --git a/include/configs/xpedite520x.h b/include/configs/xpedite520x.h deleted file mode 100644 index 21e91ee..0000000 --- a/include/configs/xpedite520x.h +++ /dev/null @@ -1,450 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * Copyright 2004-2008 Freescale Semiconductor, Inc. - */ - -/* - * xpedite520x board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_SYS_BOARD_NAME "XPedite5200" -#define CONFIG_SYS_FORM_PMC_XMC 1 - -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CONFIG_PCI1 1 /* PCI controller 1 */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -/* - * DDR config - */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS 0x54 -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 2 -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#define CONFIG_SYS_CLK_FREQ 66666666 - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_SYS_CCSRBAR 0xef000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* - * Diagnostics - */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_I2C) -#define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \ - CONFIG_SYS_I2C_EEPROM_ADDR, \ - CONFIG_SYS_I2C_PCA953X_ADDR0, \ - CONFIG_SYS_I2C_PCA953X_ADDR1, \ - CONFIG_SYS_I2C_RTC_ADDR} - -/* - * Memory map - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable - * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable - * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable - * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable - * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable - * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable - * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable - */ - -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) - -/* - * NAND flash configuration - */ -#define CONFIG_SYS_NAND_BASE 0xef800000 -#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_ACTL -#define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */ -#define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */ -#define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */ -#define CONFIG_SYS_NAND_ACTL_DELAY 25 - -/* - * NOR flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xfc000000 -#define CONFIG_SYS_FLASH_BASE2 0xf8000000 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ - {0xfbf40000, 0xc0000} } -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -/* - * Chip select configuration - */ -/* NOR Flash 0 on CS0 */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | \ - BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_8) - -/* NOR Flash 1 on CS1 */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ - BR_PS_16 | \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM - -/* NAND flash on CS2 */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ - BR_PS_8 | \ - BR_V) - -/* NAND flash on CS2 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \ - OR_GPCM_BCTLD | \ - OR_GPCM_CSNT | \ - OR_GPCM_ACS_DIV4 | \ - OR_GPCM_SCY_4 | \ - OR_GPCM_TRLX | \ - OR_GPCM_EHTR) - -/* NAND flash on CS3 */ -#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \ - BR_PS_8 | \ - BR_V) -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM - -/* - * Use L1 as initial stack - */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 -#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 - -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ - -/* - * Serial Port - */ -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) -#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) -#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - -/* - * I2C - */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 -#define CONFIG_SYS_FSL_I2C2_SPEED 400000 -#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 - -/* I2C EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */ - -/* I2C RTC */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 - -/* GPIO */ -#define CONFIG_PCA953X -#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18 -#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19 -#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0 - -/* PCA957 @ 0x18 */ -#define CONFIG_SYS_PCA953X_BRD_CFG0 0x01 -#define CONFIG_SYS_PCA953X_BRD_CFG1 0x02 -#define CONFIG_SYS_PCA953X_BRD_CFG2 0x04 -#define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08 -#define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10 -#define CONFIG_SYS_PCA953X_NVM_WP 0x20 -#define CONFIG_SYS_PCA953X_MONARCH 0x40 -#define CONFIG_SYS_PCA953X_EREADY 0x80 - -/* PCA957 @ 0x19 */ -#define CONFIG_SYS_PCA953X_P14_IO0 0x01 -#define CONFIG_SYS_PCA953X_P14_IO1 0x02 -#define CONFIG_SYS_PCA953X_P14_IO2 0x04 -#define CONFIG_SYS_PCA953X_P14_IO3 0x08 -#define CONFIG_SYS_PCA953X_P14_IO4 0x10 -#define CONFIG_SYS_PCA953X_P14_IO5 0x20 -#define CONFIG_SYS_PCA953X_P14_IO6 0x40 -#define CONFIG_SYS_PCA953X_P14_IO7 0x80 - -/* 12-bit ADC used to measure CPU diode */ -#define CONFIG_SYS_I2C_MAX1237_ADDR 0x34 - -/* - * General PCI - * Memory space is mapped 1-1, but I/O space must start from 0. - */ -#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS -#define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */ -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */ - -/* - * Networking options - */ -#define CONFIG_ETHPRIME "eTSEC1" - -#define CONFIG_TSEC1 1 -#define CONFIG_TSEC1_NAME "eTSEC1" -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC1_PHY_ADDR 1 -#define TSEC1_PHYIDX 0 -#define CONFIG_HAS_ETH0 - -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "eTSEC2" -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC2_PHY_ADDR 2 -#define TSEC2_PHYIDX 0 -#define CONFIG_HAS_ETH1 - -#define CONFIG_TSEC3 1 -#define CONFIG_TSEC3_NAME "eTSEC3" -#define TSEC3_FLAGS TSEC_GIGABIT -#define TSEC3_PHY_ADDR 3 -#define TSEC3_PHYIDX 0 -#define CONFIG_HAS_ETH2 - -#define CONFIG_TSEC4 1 -#define CONFIG_TSEC4_NAME "eTSEC4" -#define TSEC4_FLAGS TSEC_GIGABIT -#define TSEC4_PHY_ADDR 4 -#define TSEC4_PHYIDX 0 -#define CONFIG_HAS_ETH3 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */ -#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */ -#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ -#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ - -/* - * Environment Configuration - */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */ -#define CONFIG_ENV_SIZE 0x8000 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024)) - -/* - * Flash memory map: - * fff80000 - ffffffff Pri U-Boot (512 KB) - * fff40000 - fff7ffff Pri U-Boot Environment (256 KB) - * fff00000 - fff3ffff Pri FDT (256KB) - * fef00000 - ffefffff Pri OS image (16MB) - * fc000000 - feefffff Pri OS Use/Filesystem (47MB) - * - * fbf80000 - fbffffff Sec U-Boot (512 KB) - * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB) - * fbf00000 - fbf3ffff Sec FDT (256KB) - * faf00000 - fbefffff Sec OS image (16MB) - * f8000000 - faefffff Sec OS Use/Filesystem (47MB) - */ -#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000) -#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000) -#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000) -#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000) -#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000) -#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000) - -#define CONFIG_PROG_UBOOT1 \ - "$download_cmd $loadaddr $ubootfile; " \ - "if test $? -eq 0; then " \ - "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ - "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ - "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \ - "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \ - "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \ - "if test $? -ne 0; then " \ - "echo PROGRAM FAILED; " \ - "else; " \ - "echo PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_UBOOT2 \ - "$download_cmd $loadaddr $ubootfile; " \ - "if test $? -eq 0; then " \ - "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ - "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ - "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \ - "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \ - "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \ - "if test $? -ne 0; then " \ - "echo PROGRAM FAILED; " \ - "else; " \ - "echo PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_BOOT_OS_NET \ - "$download_cmd $osaddr $osfile; " \ - "if test $? -eq 0; then " \ - "if test -n $fdtaddr; then " \ - "$download_cmd $fdtaddr $fdtfile; " \ - "if test $? -eq 0; then " \ - "bootm $osaddr - $fdtaddr; " \ - "else; " \ - "echo FDT DOWNLOAD FAILED; " \ - "fi; " \ - "else; " \ - "bootm $osaddr; " \ - "fi; " \ - "else; " \ - "echo OS DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_OS1 \ - "$download_cmd $osaddr $osfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \ - "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ - "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo OS PROGRAM FAILED; " \ - "else; " \ - "echo OS PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo OS DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_OS2 \ - "$download_cmd $osaddr $osfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \ - "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ - "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo OS PROGRAM FAILED; " \ - "else; " \ - "echo OS PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo OS DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_FDT1 \ - "$download_cmd $fdtaddr $fdtfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \ - "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ - "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo FDT PROGRAM FAILED; " \ - "else; " \ - "echo FDT PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo FDT DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_PROG_FDT2 \ - "$download_cmd $fdtaddr $fdtfile; " \ - "if test $? -eq 0; then " \ - "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \ - "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ - "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \ - "if test $? -ne 0; then " \ - "echo FDT PROGRAM FAILED; " \ - "else; " \ - "echo FDT PROGRAM SUCCEEDED; " \ - "fi; " \ - "else; " \ - "echo FDT DOWNLOAD FAILED; " \ - "fi;" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "autoload=yes\0" \ - "download_cmd=tftp\0" \ - "console_args=console=ttyS0,115200\0" \ - "root_args=root=/dev/nfs rw\0" \ - "misc_args=ip=on\0" \ - "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \ - "bootfile=/home/user/file\0" \ - "osfile=/home/user/board.uImage\0" \ - "fdtfile=/home/user/board.dtb\0" \ - "ubootfile=/home/user/u-boot.bin\0" \ - "fdtaddr=0x1e00000\0" \ - "osaddr=0x1000000\0" \ - "loadaddr=0x1000000\0" \ - "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \ - "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \ - "prog_os1="CONFIG_PROG_OS1"\0" \ - "prog_os2="CONFIG_PROG_OS2"\0" \ - "prog_fdt1="CONFIG_PROG_FDT1"\0" \ - "prog_fdt2="CONFIG_PROG_FDT2"\0" \ - "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \ - "bootcmd_flash1=run set_bootargs; " \ - "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\ - "bootcmd_flash2=run set_bootargs; " \ - "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\ - "bootcmd=run bootcmd_flash1\0" -#endif /* __CONFIG_H */ diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h deleted file mode 100644 index 73e1fa3..0000000 --- a/include/configs/xpedite537x.h +++ /dev/null @@ -1,500 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * Copyright 2007-2008 Freescale Semiconductor, Inc. - */ - -/* - * xpedite537x board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - */ -#define CONFIG_SYS_BOARD_NAME "XPedite5370" -#define CONFIG_SYS_FORM_3U_VPX 1 - -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ -#define CONFIG_PCIE1 1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 1 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ - -/* - * Multicore config - */ -#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */ -#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */ - -/* - * DDR config - */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#define CONFIG_DDR_SPD -#define CONFIG_MEM_INIT_VALUE 0xdeadbeef -#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */ -#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */ -#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */ -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -#define CONFIG_DDR_ECC -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_VERY_BIG_RAM - -#ifndef __ASSEMBLY__ -extern unsigned long get_board_sys_clk(unsigned long dummy); -extern unsigned long get_board_ddr_clk(unsigned long dummy); -#endif - -#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_SYS_CCSRBAR 0xef000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -/* - * Diagnostics - */ -#define CONFIG_SYS_MEMTEST_START 0x10000000 -#define CONFIG_SYS_MEMTEST_END 0x20000000 -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_I2C) -/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */ -#define I2C_ADDR_IGNORE_LIST {0x50} - -/* - * Memory map - * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable - * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable - * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable - * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable - * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable - * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable - * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable - * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable - * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable - * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable - * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable - */ - -#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3) - -/* - * NAND flash configuration - */ -#define CONFIG_SYS_NAND_BASE 0xef800000 -#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */ -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ - CONFIG_SYS_NAND_BASE2} -#define CONFIG_SYS_MAX_NAND_DEVICE 2 -#define CONFIG_NAND_FSL_ELBC - -/* - * NOR flash configuration - */ -#define CONFIG_SYS_FLASH_BASE 0xf8000000 -#define CONFIG_SYS_FLASH_BASE2 0xf0000000 -#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \ - {0xf7f40000, 0xc0000} } -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ - -/* - * Chip select configuration - */ -/* NOR Flash 0 on CS0 */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - BR_PS_16 | \ - BR_V) -#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \ - OR_GPCM_CSNT | \ - OR_GPCM_XACS | \ - OR_GPCM_ACS_DIV2 | \ - OR_GPCM_SCY_8 | \ - OR_GPCM_TRLX | \ - OR_GPCM_EHTR | \ - OR_GPCM_EAD) - -/* NOR Flash 1 on CS1 */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \ - BR_PS_16 | \ - BR_V) -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM - -/* NAND flash on CS2 */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \ - (2< - * - * Configuration settings for the CCV xPress board - */ -#ifndef __XPRESS_CONFIG_H -#define __XPRESS_CONFIG_H - -#include "mx6_common.h" -#include - -/* SPL options */ -#include "imx6_spl.h" - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (16 << 20) - -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR - -/* I2C configs */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ -#define CONFIG_SYS_I2C_SPEED 100000 - -/* Miscellaneous configurable options */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000) - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_SYS_HZ 1000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR -#define PHYS_SDRAM_SIZE (128 << 20) - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment is in stored in the eMMC boot partition */ -#define CONFIG_ENV_SIZE (16 << 10) -#define CONFIG_ENV_OFFSET (512 << 10) -#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC2 */ -#define CONFIG_SYS_MMC_ENV_PART 1 /* boot parition */ -#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC2 */ - -/* USB Configs */ -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 - -#define CONFIG_FEC_MXC -#define CONFIG_FEC_ENET_DEV 0 -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_MXC_PHYADDR 0x0 -#define CONFIG_FEC_XCV_TYPE RMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_PHY_SMSC - -#define CONFIG_IMX_THERMAL - -#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 - -#define CONFIG_UBOOT_SECTOR_START 0x2 -#define CONFIG_UBOOT_SECTOR_COUNT 0x3fe - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc6\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ - "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "uboot=ccv/u-boot.imx\0" \ - "uboot_start="__stringify(CONFIG_UBOOT_SECTOR_START)"\0" \ - "uboot_size="__stringify(CONFIG_UBOOT_SECTOR_COUNT)"\0" \ - "update_uboot=if tftp ${uboot}; then " \ - "if itest ${filesize} > 0; then " \ - "mmc dev 0 1;" \ - "setexpr blkc ${filesize} / 0x200;" \ - "setexpr blkc ${blkc} + 1;" \ - "if itest ${blkc} <= ${uboot_size}; then " \ - "mmc write ${loadaddr} ${uboot_start} " \ - "${blkc};" \ - "fi;" \ - "fi; fi;" \ - "setenv filesize; setenv blkc\0" \ - "update_bootpart=mmc bootbus 0 2 1 2;mmc partconf 0 1 1 0\0" - -#endif /* __XPRESS_CONFIG_H */ diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h deleted file mode 100644 index 2f20273..0000000 --- a/include/configs/xtfpga.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2007-2013 Tensilica, Inc. - * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include -#include -#include - -/* - * The 'xtfpga' board describes a set of very similar boards with only minimal - * differences. - */ - -/*=====================*/ -/* Board and Processor */ -/*=====================*/ - -#define CONFIG_XTFPGA - -/* FPGA CPU freq after init */ -#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk) - -/*===================*/ -/* RAM Layout */ -/*===================*/ - -#if XCHAL_HAVE_PTP_MMU -#define CONFIG_SYS_MEMORY_BASE \ - (XCHAL_VECBASE_RESET_VADDR - XCHAL_VECBASE_RESET_PADDR) -#define CONFIG_SYS_IO_BASE 0xf0000000 -#else -#define CONFIG_SYS_MEMORY_BASE 0x60000000 -#define CONFIG_SYS_IO_BASE 0x90000000 -#define CONFIG_MAX_MEM_MAPPED 0x10000000 -#endif - -/* Onboard RAM sizes: - * - * LX60 0x04000000 64 MB - * LX110 0x03000000 48 MB - * LX200 0x06000000 96 MB - * ML605 0x18000000 384 MB - * KC705 0x38000000 896 MB - * - * noMMU configurations can only see first 256MB of onboard memory. - */ - -#if XCHAL_HAVE_PTP_MMU || CONFIG_BOARD_SDRAM_SIZE < 0x10000000 -#define CONFIG_SYS_SDRAM_SIZE CONFIG_BOARD_SDRAM_SIZE -#else -#define CONFIG_SYS_SDRAM_SIZE 0x10000000 -#endif - -#define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000) - -/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ -#ifdef CONFIG_XTFPGA_LX60 -# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ -#else -# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ -#endif - -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* heap 256KB */ - -/* Linux boot param area in RAM (used only when booting linux) */ -#define CONFIG_SYS_BOOTPARAMS_LEN (64 << 10) - -/* Memory test is destructive so default must not overlap vectors or U-Boot*/ -#define CONFIG_SYS_MEMTEST_START MEMADDR(0x01000000) -#define CONFIG_SYS_MEMTEST_END MEMADDR(0x02000000) - -/* Load address for stand-alone applications. - * MEMADDR cannot be used here, because the definition needs to be - * a plain number as it's used as -Ttext argument for ld in standalone - * example makefile. - * Handle noMMU vs MMUv2 vs MMUv3 distinction here manually. - */ -#if XCHAL_HAVE_PTP_MMU -#if XCHAL_VECBASE_RESET_VADDR == XCHAL_VECBASE_RESET_PADDR -#define CONFIG_STANDALONE_LOAD_ADDR 0x00800000 -#else -#define CONFIG_STANDALONE_LOAD_ADDR 0xd0800000 -#endif -#else -#define CONFIG_STANDALONE_LOAD_ADDR 0x60800000 -#endif - -#if defined(CONFIG_MAX_MEM_MAPPED) && \ - CONFIG_MAX_MEM_MAPPED < CONFIG_SYS_SDRAM_SIZE -#define CONFIG_SYS_MEMORY_SIZE CONFIG_MAX_MEM_MAPPED -#else -#define CONFIG_SYS_MEMORY_SIZE CONFIG_SYS_SDRAM_SIZE -#endif - -#define XTENSA_SYS_TEXT_ADDR \ - (MEMADDR(CONFIG_SYS_MEMORY_SIZE) - CONFIG_SYS_MONITOR_LEN) - -/* Used by tftpboot; env var 'loadaddr' */ -#define CONFIG_SYS_LOAD_ADDR MEMADDR(0x02000000) - -/*==============================*/ -/* U-Boot general configuration */ -/*==============================*/ - -#define CONFIG_BOARD_POSTCLK_INIT - -#define CONFIG_BOOTFILE "uImage" - /* Console I/O Buffer Size */ -#define CONFIG_SYS_CBSIZE 1024 - /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE - -/*==============================*/ -/* U-Boot autoboot configuration */ -/*==============================*/ - - -/*=========================================*/ -/* FPGA Registers (board info and control) */ -/*=========================================*/ - -/* - * These assume FPGA bitstreams from Tensilica release RB and up. Earlier - * releases may not provide any/all of these registers or at these offsets. - * Some of the FPGA registers are broken down into bitfields described by - * SHIFT left amount and field WIDTH (bits), and also by a bitMASK. - */ - -/* Date of FPGA bitstream build in binary coded decimal (BCD) */ -#define CONFIG_SYS_FPGAREG_DATE IOADDR(0x0D020000) -#define FPGAREG_MTH_SHIFT 24 /* BCD month 1..12 */ -#define FPGAREG_MTH_WIDTH 8 -#define FPGAREG_MTH_MASK 0xFF000000 -#define FPGAREG_DAY_SHIFT 16 /* BCD day 1..31 */ -#define FPGAREG_DAY_WIDTH 8 -#define FPGAREG_DAY_MASK 0x00FF0000 -#define FPGAREG_YEAR_SHIFT 0 /* BCD year 2001..9999*/ -#define FPGAREG_YEAR_WIDTH 16 -#define FPGAREG_YEAR_MASK 0x0000FFFF - -/* FPGA core clock frequency in Hz (also input to UART) */ -#define CONFIG_SYS_FPGAREG_FREQ IOADDR(0x0D020004) /* CPU clock frequency*/ - -/* - * DIP switch (left=sw1=lsb=bit0, right=sw8=msb=bit7; off=0, on=1): - * Bits 0..5 set the lower 6 bits of the default ethernet MAC. - * Bit 6 is reserved for future use by Tensilica. - * Bit 7 maps the first 128KB of ROM address space at CONFIG_SYS_ROM_BASE to - * the base of flash * (when on/1) or to the base of RAM (when off/0). - */ -#define CONFIG_SYS_FPGAREG_DIPSW IOADDR(0x0D02000C) -#define FPGAREG_MAC_SHIFT 0 /* Ethernet MAC bits 0..5 */ -#define FPGAREG_MAC_WIDTH 6 -#define FPGAREG_MAC_MASK 0x3f -#define FPGAREG_BOOT_SHIFT 7 /* Boot ROM addr mapping */ -#define FPGAREG_BOOT_WIDTH 1 -#define FPGAREG_BOOT_MASK 0x80 -#define FPGAREG_BOOT_RAM 0 -#define FPGAREG_BOOT_FLASH (1< - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL_ZC5202_H -#define __EL_ZC5202_H - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p2" - -#include "el6x_common.h" - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE MII100 -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 -#define CONFIG_MV88E6352_SWITCH - -#define CONFIG_PCI_SCAN_SHOW -#define CONFIG_PCIE_IMX - -#endif /*__EL6Q_CONFIG_H */ diff --git a/include/configs/zc5601.h b/include/configs/zc5601.h deleted file mode 100644 index e4fe7a4..0000000 --- a/include/configs/zc5601.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) Stefano Babic - * - * Configuration settings for the E+L i.MX6Q DO82 board. - */ - -#ifndef __EL_ZC5601_H -#define __EL_ZC5601_H - - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" -#define CONFIG_MMCROOT "/dev/mmcblk0p1" - -#include "el6x_common.h" - -/* Ethernet */ -#define CONFIG_FEC_MXC -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_FEC_XCV_TYPE RGMII -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0x10 -#define CONFIG_FEC_FIXED_SPEED 1000 /* No autoneg, fix Gb */ - -#endif /*__EL6Q_CONFIG_H */ diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h deleted file mode 100644 index 9d68376..0000000 --- a/include/configs/zmx25.h +++ /dev/null @@ -1,107 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2011 Graf-Syteco, Matthias Weisser - * - * - * Configuation settings for the zmx25 board - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include - -#define CONFIG_SYS_TIMER_RATE 32768 -#define CONFIG_SYS_TIMER_COUNTER \ - (&((struct gpt_regs *)IMX_GPT1_BASE)->counter) - -#define CONFIG_MACH_TYPE MACH_TYPE_ZMX25 -/* - * Environment settings - */ -#define CONFIG_EXTRA_ENV_SETTINGS \ - "gs_fast_boot=setenv bootdelay 5\0" \ - "gs_slow_boot=setenv bootdelay 10\0" \ - "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ - "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ - "bootm 0x81000000; bootelf 0x81000000\0" - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -/* - * Hardware drivers - */ - -/* - * Serial - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART2_BASE - -/* - * Ethernet - */ -#define CONFIG_FEC_MXC -#define CONFIG_FEC_MXC_PHYADDR 0x00 - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE - -/* - * Command line configuration. - */ - -/* - * Additional command - */ - -/* - * USB - */ -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI_MXC -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_MXC_USB_PORT 1 -#define CONFIG_MXC_USB_PORTSC MXC_EHCI_MODE_SERIAL -#define CONFIG_MXC_USB_FLAGS (MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN) -#define CONFIG_EHCI_IS_TDI -#endif /* CONFIG_CMD_USB */ - -/* SDRAM */ -#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ - -/* - * FLASH and environment organization - */ -#define CONFIG_SYS_FLASH_BASE 0xA0000000 -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 256 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (128 * 1024) - -/* - * CFI FLASH driver setup - */ - -#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE - -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) - - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) - -#endif /* __CONFIG_H */ diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h deleted file mode 100644 index 274cc19..0000000 --- a/include/configs/zynq-common.h +++ /dev/null @@ -1,279 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 Michal Simek - * (C) Copyright 2013 - 2018 Xilinx, Inc. - * - * Common configuration options for all Zynq boards. - */ - -#ifndef __CONFIG_ZYNQ_COMMON_H -#define __CONFIG_ZYNQ_COMMON_H - -/* CPU clock */ -#ifndef CONFIG_CPU_FREQ_HZ -# define CONFIG_CPU_FREQ_HZ 800000000 -#endif - -#define CONFIG_REMAKE_ELF - -/* Cache options */ -#define CONFIG_SYS_L2CACHE_OFF -#ifndef CONFIG_SYS_L2CACHE_OFF -# define CONFIG_SYS_L2_PL310 -# define CONFIG_SYS_PL310_BASE 0xf8f02000 -#endif - -#define ZYNQ_SCUTIMER_BASEADDR 0xF8F00600 -#define CONFIG_SYS_TIMERBASE ZYNQ_SCUTIMER_BASEADDR -#define CONFIG_SYS_TIMER_COUNTS_DOWN -#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) - -/* Serial drivers */ -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} - -#define CONFIG_ARM_DCC - -/* Ethernet driver */ -#if defined(CONFIG_ZYNQ_GEM) -# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN -# define CONFIG_BOOTP_MAY_FAIL -#endif - -/* QSPI */ - -/* NOR */ -#ifdef CONFIG_MTD_NOR_FLASH -# define CONFIG_SYS_FLASH_BASE 0xE2000000 -# define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024) -# define CONFIG_SYS_MAX_FLASH_BANKS 1 -# define CONFIG_SYS_MAX_FLASH_SECT 512 -# define CONFIG_SYS_FLASH_ERASE_TOUT 1000 -# define CONFIG_SYS_FLASH_WRITE_TOUT 5000 -# define CONFIG_FLASH_SHOW_PROGRESS 10 -# undef CONFIG_SYS_FLASH_EMPTY_INFO -#endif - -#ifdef CONFIG_NAND_ZYNQ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_ONFI_DETECTION -#endif - -#ifdef CONFIG_USB_EHCI_ZYNQ -# define CONFIG_EHCI_IS_TDI - -# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000 -# define DFU_DEFAULT_POLL_TIMEOUT 300 -# define CONFIG_THOR_RESET_OFF -# define DFU_ALT_INFO_RAM \ - "dfu_ram_info=" \ - "setenv dfu_alt_info " \ - "${kernel_image} ram 0x3000000 0x500000\\\\;" \ - "${devicetree_image} ram 0x2A00000 0x20000\\\\;" \ - "${ramdisk_image} ram 0x2000000 0x600000\0" \ - "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \ - "thor_ram=run dfu_ram_info && thordown 0 ram 0\0" - -# if defined(CONFIG_MMC_SDHCI_ZYNQ) -# define DFU_ALT_INFO_MMC \ - "dfu_mmc_info=" \ - "setenv dfu_alt_info " \ - "${kernel_image} fat 0 1\\\\;" \ - "${devicetree_image} fat 0 1\\\\;" \ - "${ramdisk_image} fat 0 1\0" \ - "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \ - "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0" - -# define DFU_ALT_INFO \ - DFU_ALT_INFO_RAM \ - DFU_ALT_INFO_MMC -# else -# define DFU_ALT_INFO \ - DFU_ALT_INFO_RAM -# endif -#endif - -#if !defined(DFU_ALT_INFO) -# define DFU_ALT_INFO -#endif - -/* Allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* enable preboot to be loaded before CONFIG_BOOTDELAY */ - -/* Boot configuration */ -#define CONFIG_SYS_LOAD_ADDR 0 /* default? */ - -#ifdef CONFIG_SPL_BUILD -#define BOOTENV -#else - -#ifdef CONFIG_CMD_MMC -#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) -#else -#define BOOT_TARGET_DEVICES_MMC(func) -#endif - -#ifdef CONFIG_CMD_USB -#define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) func(USB, usb, 1) -#else -#define BOOT_TARGET_DEVICES_USB(func) -#endif - -#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) -#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) -#else -#define BOOT_TARGET_DEVICES_PXE(func) -#endif - -#if defined(CONFIG_CMD_DHCP) -#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) -#else -#define BOOT_TARGET_DEVICES_DHCP(func) -#endif - -#if defined(CONFIG_ZYNQ_QSPI) -# define BOOT_TARGET_DEVICES_QSPI(func) func(QSPI, qspi, na) -#else -# define BOOT_TARGET_DEVICES_QSPI(func) -#endif - -#if defined(CONFIG_NAND_ZYNQ) -# define BOOT_TARGET_DEVICES_NAND(func) func(NAND, nand, na) -#else -# define BOOT_TARGET_DEVICES_NAND(func) -#endif - -#if defined(CONFIG_MTD_NOR_FLASH) -# define BOOT_TARGET_DEVICES_NOR(func) func(NOR, nor, na) -#else -# define BOOT_TARGET_DEVICES_NOR(func) -#endif - -#define BOOTENV_DEV_QSPI(devtypeu, devtypel, instance) \ - "bootcmd_qspi=sf probe 0 0 0 && " \ - "sf read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_QSPI(devtypeu, devtypel, instance) \ - "qspi " - -#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ - "bootcmd_nand=nand info && " \ - "nand read ${scriptaddr} ${script_offset_f} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ - "nand " - -#define BOOTENV_DEV_NOR(devtypeu, devtypel, instance) \ - "script_offset_nor=0xE2FC0000\0" \ - "bootcmd_nor=cp.b ${script_offset_nor} ${scriptaddr} ${script_size_f} && " \ - "source ${scriptaddr}; echo SCRIPT FAILED: continuing...;\0" - -#define BOOTENV_DEV_NAME_NOR(devtypeu, devtypel, instance) \ - "nor " - -#define BOOT_TARGET_DEVICES(func) \ - BOOT_TARGET_DEVICES_MMC(func) \ - BOOT_TARGET_DEVICES_QSPI(func) \ - BOOT_TARGET_DEVICES_NAND(func) \ - BOOT_TARGET_DEVICES_NOR(func) \ - BOOT_TARGET_DEVICES_USB(func) \ - BOOT_TARGET_DEVICES_PXE(func) \ - BOOT_TARGET_DEVICES_DHCP(func) - -#include -#endif /* CONFIG_SPL_BUILD */ - -/* Default environment */ -#ifndef CONFIG_EXTRA_ENV_SETTINGS -#define CONFIG_EXTRA_ENV_SETTINGS \ - "fdt_high=0x20000000\0" \ - "initrd_high=0x20000000\0" \ - "scriptaddr=0x20000\0" \ - "script_offset_f=0xFC0000\0" \ - "script_size_f=0x40000\0" \ - "fdt_addr_r=0x1f00000\0" \ - "pxefile_addr_r=0x2000000\0" \ - "kernel_addr_r=0x2000000\0" \ - "scriptaddr=0x3000000\0" \ - "ramdisk_addr_r=0x3100000\0" \ - DFU_ALT_INFO \ - BOOTENV -#endif - -/* Miscellaneous configurable options */ - -#define CONFIG_CLOCKS -#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ -#define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0 -#define CONFIG_SYS_MEMTEST_END 0x1000 - -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - - -/* Extend size of kernel image for uncompression */ -#define CONFIG_SYS_BOOTM_LEN (60 * 1024 * 1024) - -/* Boot FreeBSD/vxWorks from an ELF image */ -#define CONFIG_SYS_MMC_MAX_DEVICE 1 - -/* MMC support */ -#ifdef CONFIG_MMC_SDHCI_ZYNQ -#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 -#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" -#endif - -/* Address in RAM where the parameters must be copied by SPL. */ -#define CONFIG_SYS_SPL_ARGS_ADDR 0x10000000 - -#define CONFIG_SPL_FS_LOAD_ARGS_NAME "system.dtb" -#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage" - -/* Not using MMC raw mode - just for compilation purpose */ -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0 -#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0 -#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0 - -/* qspi mode is working fine */ -#ifdef CONFIG_ZYNQ_QSPI -#define CONFIG_SYS_SPI_ARGS_OFFS 0x200000 -#define CONFIG_SYS_SPI_ARGS_SIZE 0x80000 -#define CONFIG_SYS_SPI_KERNEL_OFFS (CONFIG_SYS_SPI_ARGS_OFFS + \ - CONFIG_SYS_SPI_ARGS_SIZE) -#endif - -/* SP location before relocation, must use scratch RAM */ - -/* 3 * 64kB blocks of OCM - one is on the top because of bootrom */ -#define CONFIG_SPL_MAX_SIZE 0x30000 - -/* On the top of OCM space */ -#define CONFIG_SYS_SPL_MALLOC_START CONFIG_SPL_STACK_R_ADDR -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x2000000 - -/* - * SPL stack position - and stack goes down - * 0xfffffe00 is used for putting wfi loop. - * Set it up as limit for now. - */ -#define CONFIG_SPL_STACK 0xfffffe00 - -/* BSS setup */ -#define CONFIG_SPL_BSS_START_ADDR 0x100000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 - -#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000 - -#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE - -#endif /* __CONFIG_ZYNQ_COMMON_H */ diff --git a/include/configs/zynq_cse.h b/include/configs/zynq_cse.h deleted file mode 100644 index 917f35b..0000000 --- a/include/configs/zynq_cse.h +++ /dev/null @@ -1,34 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2013 - 2017 Xilinx. - * - * Configuration settings for the Xilinx Zynq CSE board. - * See zynq-common.h for Zynq common configs - */ - -#ifndef __CONFIG_ZYNQ_CSE_H -#define __CONFIG_ZYNQ_CSE_H - -#define CONFIG_SKIP_LOWLEVEL_INIT - -#include - -/* Undef unneeded configs */ -#undef CONFIG_EXTRA_ENV_SETTINGS -#undef CONFIG_ZLIB -#undef CONFIG_GZIP - -#undef CONFIG_SYS_CBSIZE - -#define CONFIG_SYS_CBSIZE 1024 - -#undef CONFIG_SYS_INIT_RAM_ADDR -#undef CONFIG_SYS_INIT_RAM_SIZE -#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000 -#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 -#undef CONFIG_SPL_BSS_START_ADDR -#undef CONFIG_SPL_BSS_MAX_SIZE -#define CONFIG_SPL_BSS_START_ADDR 0x20000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x8000 - -#endif /* __CONFIG_ZYNQ_CSE_H */ -- cgit v1.2.3