From 08dd4564b1f5c3258caf6bfc4bdc77ead1b042d6 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Wed, 30 Oct 2019 15:38:10 +0800 Subject: fix ARCH_DMA_MINALIGN mess --- arch/arm/include/asm/cache.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm/include/asm/cache.h') diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 950ec1e..57e2149 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -47,6 +47,10 @@ void dram_bank_mmu_setup(int bank); * value than found in the L1 cache but this is OK to use in terms of * alignment. */ +#ifdef CONFIG_SYS_CACHELINE_SIZE #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE +#else +#define ARCH_DMA_MINALIGN 64 /* should be enough */ +#endif #endif /* _ASM_CACHE_H */ -- cgit v1.2.3