From ae51f41d14f548d494ac41e0d21137c5a4c3f59c Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Wed, 30 Oct 2019 14:21:52 +0800 Subject: import the U-Boot code and make it compile --- arch/x86/include/asm/cache.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 arch/x86/include/asm/cache.h (limited to 'arch/x86/include/asm/cache.h') diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h new file mode 100644 index 0000000..145b878 --- /dev/null +++ b/arch/x86/include/asm/cache.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2011 The Chromium OS Authors. + */ + +#ifndef __X86_CACHE_H__ +#define __X86_CACHE_H__ + +/* + * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment. Otherwise + * use 64-bytes, a safe default for x86. + */ +#ifndef CONFIG_SYS_CACHELINE_SIZE +#define CONFIG_SYS_CACHELINE_SIZE 64 +#endif + +#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE + +static inline void wbinvd(void) +{ + asm volatile ("wbinvd" : : : "memory"); +} + +static inline void invd(void) +{ + asm volatile("invd" : : : "memory"); +} + +/* Enable caches and write buffer */ +void enable_caches(void); + +/* Disable caches and write buffer */ +void disable_caches(void); + +#endif /* __X86_CACHE_H__ */ -- cgit v1.2.3