From ae51f41d14f548d494ac41e0d21137c5a4c3f59c Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Wed, 30 Oct 2019 14:21:52 +0800 Subject: import the U-Boot code and make it compile --- arch/x86/include/asm/interrupt.h | 64 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 arch/x86/include/asm/interrupt.h (limited to 'arch/x86/include/asm/interrupt.h') diff --git a/arch/x86/include/asm/interrupt.h b/arch/x86/include/asm/interrupt.h new file mode 100644 index 0000000..fdeb857 --- /dev/null +++ b/arch/x86/include/asm/interrupt.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2009 + * Graeme Russ, graeme.russ@gmail.com + * + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + */ + +#ifndef __ASM_INTERRUPT_H_ +#define __ASM_INTERRUPT_H_ 1 + +#include + +#define SYS_NUM_IRQS 16 + +/* Architecture defined exceptions */ +enum x86_exception { + EXC_DE = 0, + EXC_DB, + EXC_NMI, + EXC_BP, + EXC_OF, + EXC_BR, + EXC_UD, + EXC_NM, + EXC_DF, + EXC_CSO, + EXC_TS, + EXC_NP, + EXC_SS, + EXC_GP, + EXC_PF, + EXC_MF = 16, + EXC_AC, + EXC_MC, + EXC_XM, + EXC_VE +}; + +/* arch/x86/cpu/interrupts.c */ +void set_vector(u8 intnum, void *routine); + +/* Architecture specific functions */ +void mask_irq(int irq); +void unmask_irq(int irq); +void specific_eoi(int irq); + +extern char exception_stack[]; + +/** + * configure_irq_trigger() - Configure IRQ triggering + * + * Switch the given interrupt to be level / edge triggered + * + * @param int_num legacy interrupt number (3-7, 9-15) + * @param is_level_triggered true for level triggered interrupt, false for + * edge triggered interrupt + */ +void configure_irq_trigger(int int_num, bool is_level_triggered); + +void *x86_get_idt(void); + +#endif -- cgit v1.2.3