From 1a691f101632955a994a0198fc5498b108e97fbc Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Wed, 30 Oct 2019 15:42:15 +0800 Subject: rm include/configs --- include/configs/MPC8569MDS.h | 503 ------------------------------------------- 1 file changed, 503 deletions(-) delete mode 100644 include/configs/MPC8569MDS.h (limited to 'include/configs/MPC8569MDS.h') diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h deleted file mode 100644 index de187bf..0000000 --- a/include/configs/MPC8569MDS.h +++ /dev/null @@ -1,503 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009-2011 Freescale Semiconductor, Inc. - */ - -/* - * mpc8569mds board configuration file - */ -#ifndef __CONFIG_H -#define __CONFIG_H - -#define CONFIG_SYS_SRIO -#define CONFIG_SRIO1 /* SRIO port 1 */ - -#define CONFIG_PCIE1 1 /* PCIE controller */ -#define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_ENV_OVERWRITE - -#ifndef __ASSEMBLY__ -extern unsigned long get_clock_freq(void); -#endif -/* Replace a call to get_clock_freq (after it is implemented)*/ -#define CONFIG_SYS_CLK_FREQ 66666666 -#define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#ifdef CONFIG_ATM -#define CONFIG_PQ_MDS_PIB -#define CONFIG_PQ_MDS_PIB_ATM -#endif - -/* - * These can be toggled for performance analysis, otherwise use default. - */ -#define CONFIG_L2_CACHE /* toggle L2 cache */ -#define CONFIG_BTB /* toggle branch predition */ - -#ifndef CONFIG_SYS_MONITOR_BASE -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#endif - -/* - * Only possible on E500 Version 2 or newer cores. - */ -#define CONFIG_ENABLE_36BIT_PHYS 1 - -#define CONFIG_HWCONFIG - -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - -/* - * Config the L2 Cache as L2 SRAM - */ -#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 -#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (512 << 10) -#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) - -#define CONFIG_SYS_CCSRBAR 0xe0000000 -#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR - -#if defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE -#endif - -/* DDR Setup */ -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ -#define CONFIG_DDR_SPD -#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ - -#define CONFIG_MEM_INIT_VALUE 0xDeadBeef - -#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 - /* DDR is system memory*/ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE - -#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) - -/* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ - -/* These are used when DDR doesn't use SPD. */ -#define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_TIMING_3 0x00020000 -#define CONFIG_SYS_DDR_TIMING_0 0x00330004 -#define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 -#define CONFIG_SYS_DDR_TIMING_2 0x002888D0 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 -#define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 -#define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 -#define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 -#define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 -#define CONFIG_SYS_DDR_TIMING_4 0x00220001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 -#define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 -#define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 -#define CONFIG_SYS_DDR_CDR_1 0x80040000 -#define CONFIG_SYS_DDR_CDR_2 0x00000000 -#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 -#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL2 0x24400000 - -#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d -#define CONFIG_SYS_DDR_ERR_DIS 0x00000000 -#define CONFIG_SYS_DDR_SBE 0x00010000 - -#undef CONFIG_CLOCKS_IN_MHZ - -/* - * Local Bus Definitions - */ - -#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ -#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE - -#define CONFIG_SYS_BCSR_BASE 0xf8000000 -#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE - -/*Chip select 0 - Flash*/ -#define CONFIG_FLASH_BR_PRELIM 0xfe000801 -#define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 - -/*Chip select 1 - BCSR*/ -#define CONFIG_SYS_BR1_PRELIM 0xf8000801 -#define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 - -/*Chip select 4 - PIB*/ -#define CONFIG_SYS_BR4_PRELIM 0xf8008801 -#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 - -/*Chip select 5 - PIB*/ -#define CONFIG_SYS_BR5_PRELIM 0xf8010801 -#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - -#undef CONFIG_SYS_RAMBOOT - -#define CONFIG_SYS_FLASH_EMPTY_INFO - -/* Chip select 3 - NAND */ -#ifndef CONFIG_NAND_SPL -#define CONFIG_SYS_NAND_BASE 0xFC000000 -#else -#define CONFIG_SYS_NAND_BASE 0xFFF00000 -#endif - -/* NAND boot: 4K NAND loader config */ -#define CONFIG_SYS_NAND_SPL_SIZE 0x1000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) -#define CONFIG_SYS_NAND_U_BOOT_START \ - (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) -#define CONFIG_SYS_NAND_U_BOOT_OFFS (0) -#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) -#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) - -#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ - | (2<