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| author | raywu <raywu@aaeon.com> | 2018-06-28 16:35:44 +0800 |
|---|---|---|
| committer | raywu <raywu@aaeon.com> | 2018-06-28 16:35:44 +0800 |
| commit | fc887e4a3296ceea8ce6bc15999f03059760a495 (patch) | |
| tree | f20995f9a0ea6c0e0418f26efa883fbc116e0d4e /8168EL.CFG | |
| parent | 97b7ec0be98ebb8ae381f9d7e0110da22e8bfd7a (diff) | |
| download | zprj-fc887e4a3296ceea8ce6bc15999f03059760a495.tar.xz | |
Added RTL8111E EEPROM Files
Diffstat (limited to '8168EL.CFG')
| -rw-r--r-- | 8168EL.CFG | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/8168EL.CFG b/8168EL.CFG new file mode 100644 index 0000000..5081024 --- /dev/null +++ b/8168EL.CFG @@ -0,0 +1,48 @@ +NODEID = 00 E0 4C 68 00 01 +;ENDID = 00 E0 4C 68 FF FF +VID = 10 EC +DID = 81 68 +SVID = 10 EC +SMID = 01 23 + +;Do not change following parameters without Realtek approval +CONFIG0 = 00 +CONFIG1 = CF +CONFIGx = 3C +CONFIG3 = 60 +CONFIG4 = 14 +CONFIG5 = 82 +;If PXE is enabled, set spi_en (IO reg offset 0x56 bit 3 set to 1) to 1 +;CONFIG5 = 8A +PMC = C3 FF +ROMBAR = 00 +;LEDCFG = High-Byte(19H) Low-Byte(18H) +;LEDCFG = 0C A9 +;Prefetchable memory access. Non-Prefetchable set to 04H, Prefetchable set to 0CH +PREFETCHABLE = 04 +ROMCONF = 3F +;Bit 7-6 Boot Protocol +; 00 ==> PXE protocol +; 01 ==> RPL protocol +;Bit 5-4 Boot order (method) +; 00 ==> ROM disable +; 01 ==> Int 18h +; 10 ==> Int 19h +; 11 ==> PnP/BEV(BBS) +;Bit 3 Show Config Message +; 0 ==> Enable +; 1 ==> Disable +;Bit 2 Shift+F10 Menu Entry +; 0 ==> Enable +; 1 ==> Disable +;Bit 1-0 Show Config Time +; 00 ==> 3 Seconds +; 01 ==> 5 Seconds +; 10 ==> 1 Seconds +; 11 ==> 0 Second + +;Serial Number in PCI Config Space +SN = 00 E0 4C 68 00 00 00 01 +VERSION = 1.010 + + |