diff options
| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /Board/CPU | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'Board/CPU')
162 files changed, 12776 insertions, 0 deletions
diff --git a/Board/CPU/CPU.EQU b/Board/CPU/CPU.EQU new file mode 100644 index 0000000..34423e6 --- /dev/null +++ b/Board/CPU/CPU.EQU @@ -0,0 +1,158 @@ +;************************************************************************* +;************************************************************************* +;** ** +;** (C)Copyright 1987-2013, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone: (770)-246-8600 ** +;** ** +;************************************************************************* +;************************************************************************* + +;********************************************************************** +; $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CPU.EQU 1 2/07/12 3:57a Davidhsieh $ +; +; $Revision: 1 $ +; +; $Date: 2/07/12 3:57a $ +;********************************************************************** +; Revision History +; ---------------- +; $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CPU.EQU $ +; +; 1 2/07/12 3:57a Davidhsieh + +; +;********************************************************************** + +;<AMI_FHDR_START> +;---------------------------------------------------------------------------- +; +; Name: CPU.EQU +; +; Description: Equates used by the CPU module. +; +;---------------------------------------------------------------------------- +;<AMI_FHDR_END> + +include token.equ + +; Miscellanous equates +; Must be alligned properly. 1G stack +CAR_PhysBase EQU MKF_CAR_BASE_ADDRESS +CAR_PhysSize EQU MKF_CAR_TOTAL_SIZE +CAR_PhysMask EQU (NOT (CAR_PhysSize - 1)) + +CAR_PEISize EQU (CAR_PhysSize - MKF_CAR_SEC_SIZE) + +BSP_STACK_OFFSET EQU (CAR_PhysBase + CAR_PEISize - 4) +AP_STACK_OFFSET EQU (CAR_PhysBase + CAR_PhysSize - 4) + + +; Define the equates here +MSR_XAPIC_BASE EQU 01Bh + XAPIC_BASE_ENABLE_BIT EQU 011d + XAPIC_BASE_BSP_BIT EQU 008d + + XAPIC_ENABLE_BIT EQU 8d ; SVR SW APIC Enable/Disable Bit + APIC_PRESENT_BIT EQU 9d ; APIC Present bit in Feature Flags + +MASK_ICR_CLEAR EQU 0FFF33000h ; AND mask for ICR reserved bit +OR_MASK_INIT_IPI EQU 000004500h ; OR mask to send INIT IPI +OR_MASK_USE_DEST_FIELD EQU 000000000h ; OR mask to set dest field = "Dest Field" + +;----------------------------------------------------------------------------- +; Local APIC Register Equates +;----------------------------------------------------------------------------- +LOCAL_APIC_ID equ 0020h +LOCAL_APIC_VERSION equ 0030h +LOCAL_APIC_TASK_PRI equ 0080h +LOCAL_APIC_ARB_PRI equ 0090h +LOCAL_APIC_PROC_PRI equ 00A0h +LOCAL_APIC_EOI equ 00B0h +LOCAL_APIC_LDR equ 00D0h +LOCAL_APIC_DEST_FORMAT equ 00E0h +LOCAL_APIC_SVR equ 00F0h +LOCAL_APIC_ISR0 equ 0100h +LOCAL_APIC_TMR0 equ 0180h +LOCAL_APIC_IRR0 equ 0200h +LOCAL_APIC_ERR_STAT equ 0280h +LOCAL_APIC_ICR_LO equ 0300h +LOCAL_APIC_ICR_HI equ 0310h +LOCAL_APIC_LVT equ 0320h +LOCAL_APIC_PERF equ 0340h +LOCAL_APIC_LVT_LINT0 equ 0350h +LOCAL_APIC_LVT_LINT1 equ 0360h +LOCAL_APIC_LVT_ERR equ 0370h +LOCAL_APIC_ITC equ 0380h +LOCAL_APIC_TIMER equ 0390h +LOCAL_APIC_TMR_DIV equ 03E0h + + + +; Generic MTRR equates +MTRR_PHYS_BASE_0 EQU 0200h +MTRR_PHYS_MASK_0 EQU 0201h +MTRR_PHYS_BASE_1 EQU 0202h +MTRR_PHYS_MASK_1 EQU 0203h +MTRR_PHYS_BASE_2 EQU 0204h +MTRR_PHYS_MASK_2 EQU 0205h +MTRR_PHYS_BASE_3 EQU 0206h +MTRR_PHYS_MASK_3 EQU 0207h +MTRR_PHYS_BASE_4 EQU 0208h +MTRR_PHYS_MASK_4 EQU 0209h +MTRR_PHYS_BASE_5 EQU 020Ah +MTRR_PHYS_MASK_5 EQU 020Bh +MTRR_PHYS_BASE_6 EQU 020Ch +MTRR_PHYS_MASK_6 EQU 020Dh +MTRR_PHYS_BASE_7 EQU 020Eh +MTRR_PHYS_MASK_7 EQU 020Fh +MTRR_FIX_64K_00000 EQU 0250h +MTRR_FIX_16K_80000 EQU 0258h +MTRR_FIX_16K_A0000 EQU 0259h +MTRR_FIX_4K_C0000 EQU 0268h +MTRR_FIX_4K_C8000 EQU 0269h +MTRR_FIX_4K_D0000 EQU 026Ah +MTRR_FIX_4K_D8000 EQU 026Bh +MTRR_FIX_4K_E0000 EQU 026Ch +MTRR_FIX_4K_E8000 EQU 026Dh +MTRR_FIX_4K_F0000 EQU 026Eh +MTRR_FIX_4K_F8000 EQU 026Fh +MTRR_DEF_TYPE EQU 02FFh + +EFI_SEC_PEI_HAND_OFF STRUCT + DataSize dw ? ; Size of the data structure + Reserved1 dw ? ; Reserved to match allignment of C code + BootFirmwareVolumeBase dd ? ; Base Address of the boot firmware volume + BootFirmwareVolumeSize dd ? ; Size of the boot firmware volume + TemporaryRamBase dd ? ; Base Address CAR + TemporaryRamSize dd ? ; Size of CAR + PeiTemporaryRamBase dd ? ; Base Address of CAR for PEI + PeiTemporaryRamSize dd ? ; Size of CAR for PEI + StackBase dd ? ; Base Address of CAR Stack + StackSize dd ? ; Size of CAR Stack +EFI_SEC_PEI_HAND_OFF ENDS + +EFI_PEI_SERVICES_DOUBLE_POINTER_SIZE EQU 4 + +IDTR32 STRUCT + Limit dw ? + BaseAddress dd ? +IDTR32 ENDS +;************************************************************************* +;************************************************************************* +;** ** +;** (C)Copyright 1987-2013, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone: (770)-246-8600 ** +;** ** +;************************************************************************* +;************************************************************************* + diff --git a/Board/CPU/CPU.cif b/Board/CPU/CPU.cif new file mode 100644 index 0000000..8498992 --- /dev/null +++ b/Board/CPU/CPU.cif @@ -0,0 +1,13 @@ +<component> + name = "AMI Cpu PKG" + category = ModulePart + LocalRoot = "Board\CPU" + RefName = "AMI Cpu PKG" +[parts] +"CPU Board" +"CPU Core" +"CpuSpSMI" +"AmiTxtDxe" +"AmiTxtPei" +"AmiCpuS3Pei" +<endComponent> diff --git a/Board/CPU/CPU.mak b/Board/CPU/CPU.mak new file mode 100644 index 0000000..21fcdd7 --- /dev/null +++ b/Board/CPU/CPU.mak @@ -0,0 +1,298 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CPU.mak 2 6/15/12 3:29a Davidhsieh $ +# +# $Revision: 2 $ +# +# $Date: 6/15/12 3:29a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CPU.mak $ +# +# 2 6/15/12 3:29a Davidhsieh +# [TAG] None +# [Category] New Feature +# [Description] For FIT module support +# +# 1 2/07/12 3:57a Davidhsieh +# +# +#********************************************************************** + +#<AMI_FHDR_START> +#--------------------------------------------------------------------------- +# Name: CPU.mak +# +# Description: Make file for the CPU component. +# +#--------------------------------------------------------------------------- +#<AMI_FHDR_END> + + +#--------------------------------------------------------------------------- +# Global Build Dependency List +#--------------------------------------------------------------------------- +all : $(BUILD_DIR)\equates.equ CPUMODULE + +CPUMODULE : STARTUP_DIR SECCORE CPU_PEI_BEFORE_MEM CPUPEI CPUDXE + +$(BUILD_DIR)\Cpu.mak : $(CPU_BOARD_DIR)\CPU.mak $(CPU_CORE_DIR)\CPUCore.cif $(BUILD_RULES) $(CPU_BOARD_DIR)\CPUBSP.cif + $(CIF2MAK) $(CPU_CORE_DIR)\CPUCore.cif $(CIF2MAK_DEFAULTS) $(CPU_BOARD_DIR)\CPUBSP.cif + +$(BUILD_DIR)\equates.equ : + @copy << $(BUILD_DIR)\equates.equ + +<< + @copy << $(BUILD_DIR)\mbiosequ.equ + +<< + +STARTUP_DIR: CREATE_BUILD_DIR CREATE_CPU_CORE_BUILD_DIR CREATE_CPU_BOARD_BUILD_DIR CREATE_NB_SEC CREATE_SB_SEC + +CREATE_BUILD_DIR: + if not exist $(BUILD_DIR) mkdir $(BUILD_DIR) + +CREATE_CPU_CORE_BUILD_DIR: + if not exist $(BUILD_DIR)\$(CPU_CORE_DIR) mkdir $(BUILD_DIR)\$(CPU_CORE_DIR) + +CREATE_CPU_BOARD_BUILD_DIR: + if not exist $(BUILD_DIR)\$(CPU_BOARD_DIR) mkdir $(BUILD_DIR)\$(CPU_BOARD_DIR) + + +#--------------------------------------------------------------------------- + +#--------------------------------------------------------------------------- +# Add files into CSP Library +#--------------------------------------------------------------------------- +AMI_CSP_LIB_LIBRARY_PATH = $(PROJECT_DIR)\$(AMI_CSP_LIB_LIBRARY_PATH);$(PROJECT_DIR)\$(CPU_BOARD_DIR);$(PROJECT_DIR)\$(CPU_CORE_DIR) + +AMI_CSP_LIB_INCLUDE_FILES = \ +"$(CPU_CORE_DIR)\CpuCspLib.h" + \ +$(AMI_CSP_LIB_INCLUDE_FILES) + +AMI_CSP_LIB_OBJS = $(AMI_CSP_LIB_OBJS) \ +$(BUILD_DIR)\CpuCspLib.obj \ + +{$(CPU_CORE_DIR)}.c{$(BUILD_DIR)}.obj:: + $(CC) $(CFLAGS) /I $(CPU_BOARD_DIR) /I $(CPU_CORE_DIR) /Fo$(BUILD_DIR)\ $< + +{$(CPU_BOARD_DIR)}.c{$(BUILD_DIR)\$(CPU_BOARD_DIR)}.obj:: + $(CC) $(CFLAGS) /I $(CPU_BOARD_DIR) /I $(CPU_CORE_DIR) /Fo$(BUILD_DIR)\$(CPU_BOARD_DIR)\ $< + +$(BUILD_DIR)\CpuCspLibAsm.obj: $(PROJECT_DIR)\$(CPU_CORE_DIR)\CpuCspLibAsm.asm + $(ASM_TARGET) $(AFLAGS) /I $(CPU_BOARD_DIR) /Fo$(BUILD_DIR)\ $** + +#--------------------------------------------------------------------------- + + +#--------------------------------------------------------------------------- +# Making STARTUP Module +#--------------------------------------------------------------------------- +TOP_FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + +SECCORE: $(BUILD_DIR)\Cpu.mak $(BUILD_DIR)\SecCore.ffs + +$(BUILD_DIR)\ResVec.bin : $(BUILD_DIR)\ResVec.exe + exe2bin $? $@ + +$(BUILD_DIR)\ResVec.exe : $(BUILD_DIR)\ResVec.obj + $(ASMLINK) /m /ONERROR:NOEXE $?,$@,$(BUILD_DIR)\ResVec.map,,, + +$(BUILD_DIR)\ResVec.obj : $(CPU_CORE_DIR)\ResetVector.asm + $(ASM) $(AFLAGS) /c /nologo /Fo$@ $? + +SEC_CORE_OBJ_FILES = \ +$(BUILD_DIR)\$(CPU_CORE_DIR)\Startup32.obj + +$(BUILD_DIR)\Startup.efi : $(ADDON_SEC_CORE_OBJ_FILES) $(BUILD_DIR)\$(CPU_CORE_DIR)\SecCoreSdl.obj + @set INCLUDE=%%INCLUDE%%;$(CPU_BOARD_DIR) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\Cpu.mak efi\ + NAME=Startup MAKEFILE=$(BUILD_DIR)\Cpu.mak\ + "OBJECTS=$(SEC_CORE_OBJ_FILES)" \ + ENTRY_POINT=CPU_START\ + TYPE=PEIM + + +$(BUILD_DIR)\$(CPU_CORE_DIR)\SecCoreSdl.obj : $(BUILD_DIR)\SECCoreL.ASM $(BUILD_DIR)\equates.equ + $(ASM) $(AFLAGS) /coff /I$(CPU_CORE_DIR) /I$(CPU_BOARD_DIR) /Fo$@ $(BUILD_DIR)\SECCoreL.asm + +$(BUILD_DIR)\SecCoreHdr.txt : + @copy << $(BUILD_DIR)\SecCoreHdr.txt + +.586p +.XMM + +<< + +$(BUILD_DIR)\SECCoreL.ASM : $(BUILD_DIR)\SECCore.ASM $(BUILD_DIR)\SecCoreHdr.txt + copy /b $(BUILD_DIR)\SecCoreHdr.txt+$(BUILD_DIR)\SECCore.ASM $@ + + +$(BUILD_DIR)\ApResetVec.bin : $(CPU_BOARD_DIR)\Cpu.mak + @copy << $(BUILD_DIR)\StartupMerge.ini +output + SEC_CORE($(BUILD_DIR)\ApResetVec.bin) +end +group SEC_CORE + size = 0x10 + lower = 0 + components + const(0xff, 0xff, 0xff) + const(0xea, 0xd0, 0xff, 0x00, 0xf0) + end +end +<< + $(MERGE) $(BUILD_DIR)\StartupMerge.ini + +$(BUILD_DIR)\SecCore.ffs : $(BUILD_DIR)\ResVec.bin $(BUILD_DIR)\Startup.efi $(BUILD_DIR)\ApResetVec.bin $(CPU_BOARD_DIR)\Cpu.mak + $(CPU_TOOLS_DIR)\SecFixup $(BUILD_DIR)\Startup.efi $(BUILD_DIR)\ResVec.bin $(BUILD_DIR)\ResVec.fixup +!IF "$(SEC_CAN_START_APS)"=="1" + $(CPU_TOOLS_DIR)\CreateSecFfs $(BUILD_DIR)\ApResetVec.bin 4096 $(BUILD_DIR)\Startup.efi $(BUILD_DIR)\ResVec.fixup $(BUILD_DIR)\SecCore.ffs +!ELSE + $(CPU_TOOLS_DIR)\CreateSecFfs $(BUILD_DIR)\Startup.efi $(BUILD_DIR)\ResVec.fixup $(BUILD_DIR)\SecCore.ffs +!ENDIF + +#--------------------------------------------------------------------------- + + +#--------------------------------------------------------------------------- +# Making CPU PEI Module +#--------------------------------------------------------------------------- +CPU_INCLUDE_DIR = $(CPU_BOARD_DIR) + +CPU_BEFOREMEM_INCLUDE = \ + $(CPU_BOARD_DIR)\ + $(PROJECT_CPU_INCLUDES) + +CPU_PEI_BEFORE_MEM : $(BUILD_DIR)\Cpu.mak CPU_PEI_BEFORE_MEM_BIN + +CPU_PEI_BEFORE_MEM_OBJECTS = \ + $(BUILD_DIR)\$(CPU_CORE_DIR)\CpuPeiBeforeMem.obj + +CPU_PEI_BEFORE_MEM_BIN : $(AMICSPLib) $(AMIPEILIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\Cpu.mak all\ + NAME=CpuPeiBeforeMem MAKEFILE=$(BUILD_DIR)\Cpu.mak\ + "MY_INCLUDES=$(CPU_BEFOREMEM_INCLUDE)" \ + GUID=1555ACF3-BD07-4685-B668-A86945A4124D \ + "OBJECTS=$(CPU_PEI_BEFORE_MEM_OBJECTS)" \ + ENTRY_POINT=CpuPeiBeforeMemEntry\ + TYPE=PEIM \ + DEPEX1=\ + COMPRESS=0 + +CPU_PEI_OBJECTS = \ +$(BUILD_DIR)\$(CPU_CORE_DIR)\CpuPei.obj \ +$(BUILD_DIR)\$(CPU_CORE_DIR)\CpuPeiFuncs.obj \ + +CPUPEI : $(BUILD_DIR)\Cpu.mak CpuPeiBin + +CpuPeiBin : $(AMIPEILIB) $(AMICSPLib) + @set INCLUDE=%%INCLUDE%%;$(CPU_INCLUDE_DIR) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\Cpu.mak all\ + NAME=CpuPei MAKEFILE=$(BUILD_DIR)\Cpu.mak\ + GUID=2BB5AFA9-FF33-417b-8497-CB773C2B93BF \ + "OBJECTS=$(CPU_PEI_OBJECTS)" \ + ENTRY_POINT=CpuPeiEntry\ + TYPE=PEIM \ + DEPEX1=$(CPU_CORE_DIR)\CpuPei.dxs DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \ + COMPRESS=0 +#--------------------------------------------------------------------------- + +#--------------------------------------------------------------------------- +# Making CPU DXE Module +#--------------------------------------------------------------------------- +CpuDxe : $(BUILD_DIR)\Cpu.mak CpuDxeBin + +CPU_DXE_OBJECTS = \ +$(BUILD_DIR)\$(CPU_CORE_DIR)\CpuDxe.obj \ +$(BUILD_DIR)\$(CPU_CORE_DIR)\CpuDxeFuncs.obj \ +!if "$(CPU_MODULE_CREATE_SMBIOS_TABLES)"=="1" +$(BUILD_DIR)\$(CPU_CORE_DIR)\CpuSmbios.obj \ +!endif + +DXE_PLATFORM_CPU_LIB = $(BUILD_DIR)\$(CPU_BOARD_DIR)\PlatformCpuLibDxe.obj + +$(BUILD_DIR)\$(CPU_BOARD_DIR)\PlatformCpuLibDxe.obj : $(CPU_BOARD_DIR)\PlatformCpuLib.c + $(CC) $(CFLAGS) /I$(CPU_CORE_DIR) /Fo$@ $(CPU_BOARD_DIR)\PlatformCpuLib.c + +CpuDxeBin : $(DXE_PLATFORM_CPU_LIB) $(AMIDXELIB) $(AMICSPLib) + @set INCLUDE=%%INCLUDE%%;$(CPU_INCLUDE_DIR) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\Cpu.mak all\ + NAME=CpuDxe MAKEFILE=$(BUILD_DIR)\Cpu.mak\ + OBJECTS="$(CPU_DXE_OBJECTS)" \ + GUID=E03ABADF-E536-4e88-B3A0-B77F78EB34FE \ + ENTRY_POINT=DxeInitializeCpu\ + TYPE=RT_DRIVER \ + DEPEX1=$(CPU_CORE_DIR)\CpuDxe.dxs DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1 +#--------------------------------------------------------------------------- + +#-#--------------------------------------------------------------------------- +#-# Making CPU EIST ASL Module +#-#--------------------------------------------------------------------------- +#-#----------------------------------------------------------------------- +#-# ASL compiler definition +#-#----------------------------------------------------------------------- +#-MASL = asl.exe # Microsoft ASL compiler +#-IASL = iasl.exe # Intel ASL compiler. Supports extended ACPI 2.0 asl objects +#-#----------------------------------------------------------------------- +#-ASL_COMPILER = MASL # Default ASL compiler. Can be 'IASL' for Intel ASL and 'MASL' for Microsoft ASL compiler. +#-# Note. Msft. ASL compiler of version 1.0.14NT correctly process ACPI 2.0 extended ASL objects. +#-#----------------------------------------------------------------------- + + + +#--------------------------------------------------------------------------- +# Create CPU Setup Screens +#--------------------------------------------------------------------------- +SetupSdbs : $(BUILD_DIR)\CPU.mak CPUSDB +SetupBin : $(BUILD_DIR)\CpuSetup.obj $(AMICSPLib) + +CPUSDB : + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\CPU.mak all\ + TYPE=SDB NAME=CPU MAKEFILE=$(BUILD_DIR)\CPU.mak "STRING_CONSUMERS=$(CPU_BOARD_DIR)\CPU.sd $(CPU_BOARD_DIR)\CpuSetup.c" + +$(BUILD_DIR)\CPUSetup.obj : $(PROJECT_DIR)\$(CPU_BOARD_DIR)\CPUSetup.c $(BUILD_DIR)\SetupStrTokens.h + $(CC) $(CFLAGS) /Fo$@ $(PROJECT_DIR)\$(CPU_BOARD_DIR)\CPUSetup.c + +#--------------------------------------------------------------------------- +# CPU Debugger Initialization +#--------------------------------------------------------------------------- + +$(BUILD_DIR)\$(CPU_BOARD_DIR)\CpuPeiDebugger.obj : $(PROJECT_DIR)\$(CPU_BOARD_DIR)\CpuPeiDebugger.c + $(CC) $(CFLAGS) /I $(CPU_CORE_DIR) /Fo$@ $(PROJECT_DIR)\$(CPU_BOARD_DIR)\CpuPeiDebugger.c + +PeiDbgPortBin : $(BUILD_DIR)\$(CPU_BOARD_DIR)\CpuPeiDebugger.obj + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/CPU/CPU.sd b/Board/CPU/CPU.sd new file mode 100644 index 0000000..f3da96f --- /dev/null +++ b/Board/CPU/CPU.sd @@ -0,0 +1,1525 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CPU.sd 26 6/11/15 10:34p Crystallee $ +// +// $Revision: 26 $ +// +// $Date: 6/11/15 10:34p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CPU.sd $ +// +// 26 6/11/15 10:34p Crystallee +// [TAG] EIP207854 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Txt test fail with TCG2 module +// [RootCause] Tokne TCG_SUPPORT was removed. +// [Solution] Add TCG2Support token. +// +// 25 11/07/13 1:08a Crystallee +// +// 24 8/28/13 5:59a Crystallee +// [TAG] EIP134339 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] [Sharkbay]Build error after update Haswell Cpu module +// [RootCause] If token TCG_SUPPORT is disabled, TpmSupport setup data +// will not define, then cause built error. +// [Solution] Add token TCG_SUPPORT condition when use TpmSupport setup +// data. +// +// 23 7/23/13 7:41a Crystallee +// [TAG] EIP128089 +// [Category] Improvement +// [Description] TXT will be disabled and grayed out in Setup when TPM +// Support is disabled. +// +// 22 5/09/13 10:54p Crystallee +// [TAG] EIP123326 +// [Category] Improvement +// [Description] Show "Processor family" and "FSB speed" on CPU +// Configuration in BIOS setup menu. +// +// 21 4/03/13 4:56a Crystallee +// [TAG] EIP119880 +// [Category] Improvement +// [Description] Provide setup items which is related to PowerLimit3. +// +// 20 3/20/13 2:57a Crystallee +// [TAG] None +// [Category] Improvement +// [Description] Change TurboPowerLimitLock default value to enable. +// +// 19 3/06/13 2:15a Crystallee +// [TAG] None +// [Category] Improvement +// [Description] Change numeric step value to 1. +// +// 18 3/05/13 1:35a Davidhsieh +// [TAG] EIP116207 +// [Category] Improvement +// [Description] Change VrCurrentLimit from UINT8 to UINT16 +// +// 17 2/26/13 3:19a Crystallee +// [TAG] None +// [Category] Improvement +// [Description] Keep the same variable size. +// +// 16 2/22/13 2:00a Crystallee +// [TAG] EIP112238 +// [Category] Improvement +// [Description] Refer Intel BIOS and provide setup items for Intel +// Haswell RC policy. +// +// 15 1/24/13 5:13a Crystallee +// [TAG] None +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Change C state limit to C10, the system will hang. +// [RootCause] BIOS doesn't limit the C state to CPU support. +// [Solution] According to the CPU C state support, add C state limit to +// prevent system hanging and limit the setup item choice. +// +// 14 1/23/13 2:49a Crystallee +// [TAG] None +// [Category] Improvement +// [Description] Create setup item for BootInLfm +// +// 13 12/26/12 2:59a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Change Iout Slope default value +// +// 12 12/13/12 4:14a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Extend setup item C state package to C10 +// +// 11 12/12/12 1:26a Davidhsieh +// [TAG] EIP108401 +// [Category] Improvement +// [Description] Create setup item for VrMiscIoutOffsetSign +// +// 10 12/03/12 9:49p Davidhsieh +// [TAG] EIP108401 +// [Category] Improvement +// [Description] Create setup items for VrMiscIoutOffset, +// VrMiscIoutSlope and LakeTiny +// +// 9 11/18/12 9:34p Davidhsieh +// [TAG] EIP195980 +// [Category] Improvement +// [Description] Setup items for Package C State Limit and Energy +// Performance +// +// 8 10/28/12 11:36p Davidhsieh +// [TAG] EIP105017 +// [Category] Improvement +// [Description] Implement Setup Options for Debug Interface Enable/Lock +// +// 7 10/19/12 7:07a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Setup items CTDP BIOS, C8, C9 and C10 created +// +// 6 9/13/12 3:29a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Add DTS setup item +// +// 5 7/19/12 2:20a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Change VT default value to enable +// +// 4 6/15/12 3:30a Davidhsieh +// [TAG] EIP89941 +// [Category] Improvement +// [Description] Add Intel TXT setup item +// [Files] CPU.sd +// CPU.uni +// CPUBSP.cif +// +// 3 5/22/12 2:59a Davidhsieh +// Setup page layout change +// +// 2 3/16/12 3:34a Davidhsieh +// Setup items create for CPU RC policy +// +// 1 2/07/12 3:57a Davidhsieh +// +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// Name: CPU.sd +// +// Description: Setup definition for CPU. +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#ifdef SETUP_DATA_DEFINITION +/***********************************************************/ +/* Put NVRAM data definitions here. +/* For example: UINT8 Data1; +/* These definitions will be converted by the build process +/* to a definitions of SETUP_DATA fields. +/***********************************************************/ +#if CPU_SETUP_SET_MAX_RATIO + UINT8 CpuMaxRatio; +#endif +#if CPU_SETUP_SET_BOOT_RATIO + UINT8 CpuSetBootRatio; +#endif + UINT8 XDBit; + UINT8 HTD; + UINT8 ActiveCoreCount; + UINT8 OverclockingLock; + UINT8 LimitCpuid; + UINT8 VT; + UINT8 LocalX2Apic; + UINT8 CpuTccActOffset; + UINT8 TurboPowerLimitLock; + UINT8 Cpu1CoreRatioLimit; + UINT8 Cpu2CoreRatioLimit; + UINT8 Cpu3CoreRatioLimit; + UINT8 Cpu4CoreRatioLimit; + UINT8 VrCurrentLimitLock; + UINT16 VrCurrentLimit; + UINT8 PR1CurrentLimit; + UINT8 MlcStreamerPrefetcher; + UINT8 MlcSpatialPrefetcher; + UINT8 AesEnable; + UINT8 BootInLfm; + UINT8 EIST; + UINT8 TurboMode; + UINT8 PowerLimit1; + UINT8 PowerLimit2; + UINT8 PowerLimit1Time; + UINT8 DdrPowerLimit1; + UINT8 DdrPowerLimit2; + UINT8 DdrPowerLimit1Time; + UINT8 CxEnable; + UINT8 C3Enable; + UINT8 C6Enable; + UINT8 C7Enable; + UINT8 cTDPLevel; + UINT8 cTDPLock; + UINT8 CpuTstate; + UINT8 C1E; + UINT8 C1AutoDemotion; + UINT8 C3AutoDemotion; + UINT8 C1UnDemotion; + UINT8 C3UnDemotion; + UINT8 PkgCStateDemotion; + UINT8 PkgCStateUnDemotion; + UINT8 C6Latency; + UINT8 C7Latency; + UINT8 CxPreWake; + UINT8 TxtSupport; + UINT8 DtsEnable; + UINT8 CtdpBios; + UINT8 C8Enable; + UINT8 C9Enable; + UINT8 C10Enable; + UINT8 DebugInterfaceEnable; + UINT8 DebugInterfaceLock; + UINT8 PmgCstCfgCtrlLock; + UINT8 PackageCState; + UINT8 CpuEngPerfBias; + UINT8 LakeTiny; + UINT16 IoutOffset; + UINT16 IoutSlope; + UINT8 IoutOffsetSign; + UINT8 CstateLatencyControl0TimeUnit; + UINT8 CstateLatencyControl1TimeUnit; + UINT8 CstateLatencyControl2TimeUnit; + UINT8 CstateLatencyControl0Irtl; + UINT8 CstateLatencyControl1Irtl; + UINT8 CstateLatencyControl2Irtl; + UINT8 PowerLimit3Lock; + UINT8 PowerLimit3; + UINT8 PowerLimit3Time; + UINT8 PowerLimit3DutyCycle; +#endif + +//--------------------------------------------------------------------------- +#if defined(VFRCOMPILE) && !defined(CONTROLS_ARE_DEFINED) +#define CONTROL_DEFINITION +#endif +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +#ifdef CONTROL_DEFINITION +#if CPU_SETUP_SET_MAX_RATIO +#define CPU_ONEOF_CPUMAXRATIO\ + numeric varid = SETUP_DATA.CpuMaxRatio,\ + prompt = STRING_TOKEN(STR_CPU_MAX_RATIO),\ + help = STRING_TOKEN(STR_CPU_MAX_RATIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 255,\ + endnumeric; +#endif +#if CPU_SETUP_SET_BOOT_RATIO +#define CPU_ONEOF_CPUBOOTRATIO\ + numeric varid = SETUP_DATA.CpuSetBootRatio,\ + prompt = STRING_TOKEN(STR_CPU_SET_BOOT_RATIO),\ + help = STRING_TOKEN(STR_CPU_SET_BOOT_RATIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 255,\ + endnumeric; +#endif +#define CPU_ONEOF_CPUHTD\ + oneof varid = SETUP_DATA.HTD,\ + prompt = STRING_TOKEN(STR_CPU_HTD_PROMPT),\ + help = STRING_TOKEN(STR_CPU_HTD_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUACTIVECORECOUNTGUP2\ + oneof varid = SETUP_DATA.ActiveCoreCount,\ + prompt = STRING_TOKEN(STR_CPU_ACTIVE_CORE_COUNT_PROMPT),\ + help = STRING_TOKEN(STR_CPU_ACTIVE_CORE_COUNT_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_ALL), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_2), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_3), value = 3, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUACTIVECORECOUNTGUP5\ + oneof varid = SETUP_DATA.ActiveCoreCount,\ + prompt = STRING_TOKEN(STR_CPU_ACTIVE_CORE_COUNT_PROMPT),\ + help = STRING_TOKEN(STR_CPU_ACTIVE_CORE_COUNT_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_ALL), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_1), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUACTIVECORECOUNTGUP3\ + oneof varid = SETUP_DATA.ActiveCoreCount,\ + prompt = STRING_TOKEN(STR_CPU_ACTIVE_CORE_COUNT_PROMPT),\ + help = STRING_TOKEN(STR_CPU_ACTIVE_CORE_COUNT_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_ALL), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_2), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_3), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_4), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_5), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_OVERCLOCKING_LOCK\ + oneof varid = SETUP_DATA.OverclockingLock,\ + prompt = STRING_TOKEN(STR_CPU_OVERCLOCKING_LOCK),\ + help = STRING_TOKEN(STR_CPU_OVERCLOCKING_LOCK_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPULIMITCPUID\ + oneof varid = SETUP_DATA.LimitCpuid,\ + prompt = STRING_TOKEN(STR_CPU_LIMIT_CPUID_MAX_PROMPT),\ + help = STRING_TOKEN(STR_CPU_LIMIT_CPUID_MAX_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUXDBIT\ + oneof varid = SETUP_DATA.XDBit,\ + prompt = STRING_TOKEN(STR_CPU_XD_BIT_PROMPT),\ + help = STRING_TOKEN(STR_CPU_XD_BIT_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUVT\ + oneof varid = SETUP_DATA.VT,\ + prompt = STRING_TOKEN(STR_CPU_VT_PROMPT),\ + help = STRING_TOKEN(STR_CPU_VT_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUMLCSTREAMER\ + oneof varid = SETUP_DATA.MlcStreamerPrefetcher,\ + prompt = STRING_TOKEN(STR_PROC_HW_PREFETCH_PROMPT),\ + help = STRING_TOKEN(STR_PROC_HW_PREFETCH_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUMLCSPATIAL\ + oneof varid = SETUP_DATA.MlcSpatialPrefetcher,\ + prompt = STRING_TOKEN(STR_PROC_ADJ_CACHE_LINE_PROMPT),\ + help = STRING_TOKEN(STR_PROC_ADJ_CACHE_LINE_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_AES\ + oneof varid = SETUP_DATA.AesEnable,\ + prompt = STRING_TOKEN(STR_CPU_AES_PROMPT),\ + help = STRING_TOKEN(STR_CPU_AES_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_BOOTPERFORMANCEMODE\ + oneof varid = SETUP_DATA.BootInLfm,\ + prompt = STRING_TOKEN(STR_CPU_BOOT_PERFORMANCE_PROMPT),\ + help = STRING_TOKEN(STR_CPU_BOOT_PERFORMANCE_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_BOOT_PERFORMANCE_MAX_NONTURBO), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_BOOT_PERFORMANCE_MAX_BATTERY), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_BOOT_PERFORMANCE_TURBO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_EIST\ + oneof varid = SETUP_DATA.EIST,\ + prompt = STRING_TOKEN(STR_CPU_EIST_PROMPT),\ + help = STRING_TOKEN(STR_CPU_EIST_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_TURBOMODE\ + oneof varid = SETUP_DATA.TurboMode,\ + prompt = STRING_TOKEN(STR_CPU_TURBO_MODE_PROMPT),\ + help = STRING_TOKEN(STR_CPU_TURBO_MODE_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUENGPERFBIAS\ + oneof varid = SETUP_DATA.CpuEngPerfBias,\ + prompt = STRING_TOKEN(STR_CPU_ENG_PERF_BIAS_PROMPT),\ + help = STRING_TOKEN(STR_CPU_ENG_PERF_BIAS_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_ENG_PERF_BIAS_PERFORM), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENG_PERF_BIAS_BAL_PERFORM), value = 7, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENG_PERF_BIAS_BAL_ENRGY), value = 11, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENG_PERF_BIAS_ERGY_EFFIC), value = 15, flags = RESET_REQUIRED, key = 0;\ + endoneof; + + #define CPU_ONEOF_TURBOPOWERLIMITLOCK\ + oneof varid = SETUP_DATA.TurboPowerLimitLock,\ + prompt = STRING_TOKEN(STR_CPU_POWER_LIMIT_LOCK),\ + help = STRING_TOKEN(STR_CPU_POWER_LIMIT_LOCK_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_NUMERIC_CPUPWRLIMIT1\ + numeric varid = SETUP_DATA.PowerLimit1,\ + prompt = STRING_TOKEN(STR_CPU_LONG_DUR_PWR),\ + help = STRING_TOKEN(STR_CPU_LONG_DUR_PWR_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_LONG_DUR_PWR), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_NUMERIC_CPUPWRLIMIT1TIME\ + numeric varid = SETUP_DATA.PowerLimit1Time,\ + prompt = STRING_TOKEN(STR_CPU_LONG_DUR_TIME),\ + help = STRING_TOKEN(STR_CPU_LONG_DUR_TIME_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_LONG_DUR_TIME), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_NUMERIC_CPUPWRLIMIT2\ + numeric varid = SETUP_DATA.PowerLimit2,\ + prompt = STRING_TOKEN(STR_CPU_SHRT_DUR_PWR),\ + help = STRING_TOKEN(STR_CPU_SHRT_DUR_PWR_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_SHRT_DUR_PWR), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_PLATFORMPOWERLIMITLOCK\ + oneof varid = SETUP_DATA.PowerLimit3Lock,\ + prompt = STRING_TOKEN(STR_CPU_PLATFORM_POWER_LIMIT_LOCK),\ + help = STRING_TOKEN(STR_CPU_PLATFORM_POWER_LIMIT_LOCK_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_NUMERIC_CPUPWRLIMIT3\ + numeric varid = SETUP_DATA.PowerLimit3,\ + prompt = STRING_TOKEN(STR_CPU_POWER_LIMIT3),\ + help = STRING_TOKEN(STR_CPU_POWER_LIMIT3_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_POWER_LIMIT3), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_NUMERIC_CPUPWRLIMIT3TIME\ + numeric varid = SETUP_DATA.PowerLimit3Time,\ + prompt = STRING_TOKEN(STR_CPU_PL3_TIME),\ + help = STRING_TOKEN(STR_CPU_PL3_TIME_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_PL3_TIME), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_NUMERIC_CPUPWRLIMIT3DUTYCYCLE\ + numeric varid = SETUP_DATA.PowerLimit3DutyCycle,\ + prompt = STRING_TOKEN(STR_CPU_PL3_DUTY_CYCLE),\ + help = STRING_TOKEN(STR_CPU_PL3_DUTY_CYCLE_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 100,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_PL3_DUTY_CYCLE), value = 100, flags = MANUFACTURING; \ + endnumeric; + +#define DDR_NUMERIC_DDRPWRLIMIT1\ + numeric varid = SETUP_DATA.DdrPowerLimit1,\ + prompt = STRING_TOKEN(STR_DDR_PWR_LIMIT1),\ + help = STRING_TOKEN(STR_DDR_PWR_LIMIT1_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_LONG_DUR_PWR), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define DDR_NUMERIC_DDRPWRLIMIT1TIME\ + numeric varid = SETUP_DATA.DdrPowerLimit1Time,\ + prompt = STRING_TOKEN(STR_DDR_PWR_LIMIT1_TIME),\ + help = STRING_TOKEN(STR_DDR_PWR_LIMIT1_TIME_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_LONG_DUR_TIME), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define DDR_NUMERIC_DDRPWRLIMIT2\ + numeric varid = SETUP_DATA.DdrPowerLimit2,\ + prompt = STRING_TOKEN(STR_DDR_PWR_LIMIT2),\ + help = STRING_TOKEN(STR_DDR_PWR_LIMIT2_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_SHRT_DUR_PWR), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_CXENABLE\ + oneof varid = SETUP_DATA.CxEnable,\ + prompt = STRING_TOKEN(STR_CPU_CTATES_PROMPT),\ + help = STRING_TOKEN(STR_CPU_CTATES_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_C1EENABLE\ + oneof varid = SETUP_DATA.C1E,\ + prompt = STRING_TOKEN(STR_CPU_C1E_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C1E_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_C3ENABLE\ + oneof varid = SETUP_DATA.C3Enable,\ + prompt = STRING_TOKEN(STR_CPU_C3_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C3_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_C6ENABLE\ + oneof varid = SETUP_DATA.C6Enable,\ + prompt = STRING_TOKEN(STR_CPU_C6_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C6_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + endoneof; + +#define CPU_LONGSHORT_C6LATENCY\ + oneof varid = SETUP_DATA.C6Latency,\ + prompt = STRING_TOKEN(STR_CPU_C6_LATENCY_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C6_LATENCY_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_SHORT_LATENCY), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_LONG_LATENCY), value = 1, flags = RESET_REQUIRED;\ + endoneof; + +#define CPU_ONEOF_C7ENABLE\ + oneof varid = SETUP_DATA.C7Enable,\ + prompt = STRING_TOKEN(STR_CPU_C7_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C7_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C7), value = 1, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C7S), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + endoneof; + +#define CPU_LONGSHORT_C7LATENCY\ + oneof varid = SETUP_DATA.C7Latency,\ + prompt = STRING_TOKEN(STR_CPU_C7_LATENCY_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C7_LATENCY_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_SHORT_LATENCY), value = 0, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_LONG_LATENCY), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + endoneof; + +#define CPU_ONEOF_C8ENABLE\ + oneof varid = SETUP_DATA.C8Enable,\ + prompt = STRING_TOKEN(STR_CPU_C8_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C8_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + endoneof; + +#define CPU_ONEOF_C9ENABLE\ + oneof varid = SETUP_DATA.C9Enable,\ + prompt = STRING_TOKEN(STR_CPU_C9_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C9_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + endoneof; + +#define CPU_ONEOF_C10ENABLE\ + oneof varid = SETUP_DATA.C10Enable,\ + prompt = STRING_TOKEN(STR_CPU_C10_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C10_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + endoneof; + +#define CPU_ONEOF_C1AUTODEMOTIONENABLE\ + oneof varid = SETUP_DATA.C1AutoDemotion,\ + prompt = STRING_TOKEN(STR_CPU_C1DEMOTION_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C1DEMOTION_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_C3AUTODEMOTIONENABLE\ + oneof varid = SETUP_DATA.C3UnDemotion,\ + prompt = STRING_TOKEN(STR_CPU_C3DEMOTION_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C3DEMOTION_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_C1UNDEMOTIONENABLE\ + oneof varid = SETUP_DATA.C1UnDemotion,\ + prompt = STRING_TOKEN(STR_CPU_C1UNDEMOTION_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C1UNDEMOTION_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_C3UNDEMOTIONENABLE\ + oneof varid = SETUP_DATA.C3AutoDemotion,\ + prompt = STRING_TOKEN(STR_CPU_C3UNDEMOTION_PROMPT),\ + help = STRING_TOKEN(STR_CPU_C1UNDEMOTION_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_PACKAGECDEMOTIONENABLE\ + oneof varid = SETUP_DATA.PkgCStateDemotion,\ + prompt = STRING_TOKEN(STR_CPU_PACKAGECDEMOTION_PROMPT),\ + help = STRING_TOKEN(STR_CPU_PACKAGECDEMOTION_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_PACKAGECUNDEMOTIONENABLE\ + oneof varid = SETUP_DATA.PkgCStateUnDemotion,\ + prompt = STRING_TOKEN(STR_CPU_PACKAGECUNDEMOTION_PROMPT),\ + help = STRING_TOKEN(STR_CPU_PACKAGECUNDEMOTION_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CXPREWAKEENABLE\ + oneof varid = SETUP_DATA.CxPreWake,\ + prompt = STRING_TOKEN(STR_CPU_CX_PREWAKE_PROMPT),\ + help = STRING_TOKEN(STR_CPU_CX_PREWAKE_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#if CPU_SETUP_SET_LATENCY_CONTROL +#define CPU_ONEOF_C3LATENCYCONTROLTIMEUNIT\ + oneof varid = SETUP_DATA.CstateLatencyControl0TimeUnit,\ + prompt = STRING_TOKEN(STR_CPU_C3_LATENCY_CONTROL_TIME_UNIT),\ + help = STRING_TOKEN(STR_CPU_C3_LATENCY_CONTROL_TIME_UNIT_HELP),\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_32NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1024NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_32768NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1048576NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_33554432NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_NUMERIC_C3LATENCYCONTROLLATENCY\ + numeric varid = SETUP_DATA.CstateLatencyControl0Irtl,\ + prompt = STRING_TOKEN(STR_CPU_C3_LATENCY_CONTROL_LATENCY),\ + help = STRING_TOKEN(STR_CPU_C3_LATENCY_CONTROL_LATENCY_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 0x42,\ + endnumeric; + +#define CPU_ONEOF_C6C7SHORTLATENCYCONTROLTIMEUNIT\ + oneof varid = SETUP_DATA.CstateLatencyControl1TimeUnit,\ + prompt = STRING_TOKEN(STR_CPU_C6C7_SHORT_LATENCY_CONTROL_TIME_UNIT),\ + help = STRING_TOKEN(STR_CPU_C6C7_SHORT_LATENCY_CONTROL_TIME_UNIT_HELP),\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_32NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1024NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_32768NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1048576NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_33554432NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_NUMERIC_C6C7SHORTLATENCYCONTROLLATENCY\ + numeric varid = SETUP_DATA.CstateLatencyControl1Irtl,\ + prompt = STRING_TOKEN(STR_CPU_C6C7_SHORT_LATENCY_CONTROL_LATENCY),\ + help = STRING_TOKEN(STR_CPU_C6C7_SHORT_LATENCY_CONTROL_LATENCY_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 0x6A,\ + endnumeric; + +#define CPU_ONEOF_C6C7LONGLATENCYCONTROLTIMEUNIT\ + oneof varid = SETUP_DATA.CstateLatencyControl2TimeUnit,\ + prompt = STRING_TOKEN(STR_CPU_C6C7_LONG_LATENCY_CONTROL_TIME_UNIT),\ + help = STRING_TOKEN(STR_CPU_C6C7_LONG_LATENCY_CONTROL_TIME_UNIT_HELP),\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_32NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1024NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_32768NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_1048576NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_LATENCY_CONTROL_TIME_UNIT_33554432NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_NUMERIC_C6C7LONGLATENCYCONTROLLATENCY\ + numeric varid = SETUP_DATA.CstateLatencyControl2Irtl,\ + prompt = STRING_TOKEN(STR_CPU_C6C7_LONG_LATENCY_CONTROL_LATENCY),\ + help = STRING_TOKEN(STR_CPU_C6C7_LONG_LATENCY_CONTROL_LATENCY_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 0x91,\ + endnumeric; +#endif + +#define CPU_ONEOF_PACKAGECSTATELOCK\ + oneof varid = SETUP_DATA.PmgCstCfgCtrlLock,\ + prompt = STRING_TOKEN(STR_CPU_PACKAGE_CSTATE_REPORT_LOCK),\ + help = STRING_TOKEN(STR_CPU_PACKAGE_CSTATE_REPORT_LOCK_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_PACKAGECSTATEUPTOC7\ + oneof varid = SETUP_DATA.PackageCState,\ + prompt = STRING_TOKEN(STR_CPU_PACKAGE_CSTATE_REPORT),\ + help = STRING_TOKEN(STR_CPU_PACKAGE_CSTATE_REPORT_HELP),\ + option text = STRING_TOKEN(STR_CPU_C0SUPPORT), value = 0, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C2SUPPORT), value = 1, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C3SUPPORT), value = 2, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C6SUPPORT), value = 3, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C7SUPPORT), value = 4, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C7SSUPPORT), value = 5, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_AUTO), value = 0xff, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + endoneof; + +#define CPU_ONEOF_PACKAGECSTATEUPTOC10\ + oneof varid = SETUP_DATA.PackageCState,\ + prompt = STRING_TOKEN(STR_CPU_PACKAGE_CSTATE_REPORT),\ + help = STRING_TOKEN(STR_CPU_PACKAGE_CSTATE_REPORT_HELP),\ + option text = STRING_TOKEN(STR_CPU_C0SUPPORT), value = 0, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C2SUPPORT), value = 1, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C3SUPPORT), value = 2, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C6SUPPORT), value = 3, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C7SUPPORT), value = 4, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C7SSUPPORT), value = 5, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C8SUPPORT), value = 6, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C9SUPPORT), value = 7, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_C10SUPPORT), value = 8, flags = RESET_REQUIRED;\ + option text = STRING_TOKEN(STR_CPU_AUTO), value = 0xff, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;\ + endoneof; + +#define CPU_ONEOF_CPULAKETINY\ + oneof varid = SETUP_DATA.LakeTiny,\ + prompt = STRING_TOKEN(STR_CPU_LAKETINY_PROMPT),\ + help = STRING_TOKEN(STR_CPU_LAKETINY_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUCTDPBIOS\ + oneof varid = SETUP_DATA.CtdpBios,\ + prompt = STRING_TOKEN(STR_CPU_CTDP_BIOS_PROMPT),\ + help = STRING_TOKEN(STR_CPU_CTDP_BIOS_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUCONFIGTDPLEVEL\ + oneof varid = SETUP_DATA.cTDPLevel,\ + prompt = STRING_TOKEN(STR_CPUTDP_LEVEL_PROMPT),\ + help = STRING_TOKEN(STR_CPUTDP_LEVEL_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPUTDP_LEVEL_NOMINAL), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPUTDP_LEVEL_DOWN), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPUTDP_LEVEL_UP), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0xff, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUCTDPLOCK\ + oneof varid = SETUP_DATA.cTDPLock,\ + prompt = STRING_TOKEN(STR_CPUTDP_LOCK_PROMPT),\ + help = STRING_TOKEN(STR_CPUTDP_LOCK_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_NUMERIC_CPUTCCACTIVEOFFSET\ + numeric varid = SETUP_DATA.CpuTccActOffset,\ + prompt = STRING_TOKEN(STR_CPU_TCC_ACTIVATION_OFFSET),\ + help = STRING_TOKEN(STR_CPU_TCC_ACTIVATION_OFFSET_HELP),\ + flags = RESET_REQUIRED, \ + minimum = 0,\ + maximum = 50,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_TCC_ACTIVATION_OFFSET), value = 50, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_CPU1CORERATIOLIMIT\ + numeric varid = SETUP_DATA.Cpu1CoreRatioLimit,\ + prompt = STRING_TOKEN(STR_CPU_1_CORE_RATIO_LIMIT),\ + help = STRING_TOKEN(STR_CPU_1_CORE_RATIO_LIMIT_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_1_CORE_RATIO_LIMIT), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_CPU2CORERATIOLIMIT\ + numeric varid = SETUP_DATA.Cpu2CoreRatioLimit,\ + prompt = STRING_TOKEN(STR_CPU_2_CORE_RATIO_LIMIT),\ + help = STRING_TOKEN(STR_CPU_2_CORE_RATIO_LIMIT_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_2_CORE_RATIO_LIMIT), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_CPU3CORERATIOLIMIT\ + numeric varid = SETUP_DATA.Cpu3CoreRatioLimit,\ + prompt = STRING_TOKEN(STR_CPU_3_CORE_RATIO_LIMIT),\ + help = STRING_TOKEN(STR_CPU_3_CORE_RATIO_LIMIT_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_3_CORE_RATIO_LIMIT), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_CPU4CORERATIOLIMIT\ + numeric varid = SETUP_DATA.Cpu4CoreRatioLimit,\ + prompt = STRING_TOKEN(STR_CPU_4_CORE_RATIO_LIMIT),\ + help = STRING_TOKEN(STR_CPU_4_CORE_RATIO_LIMIT_HELP),\ + flags = RESET_REQUIRED ,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_4_CORE_RATIO_LIMIT), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_CPUVRCURRENTLIMITLOCK\ + oneof varid = SETUP_DATA.VrCurrentLimitLock,\ + prompt = STRING_TOKEN(STR_PRIMARY_PLANE_CURRENT_LOCK),\ + help = STRING_TOKEN(STR_PRIMARY_PLANE_CURRENT_LOCK_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUVRCURRENTLIMIT\ + numeric varid = SETUP_DATA.VrCurrentLimit,\ + prompt = STRING_TOKEN(STR_PRIMARY_PLANE_CURRENT),\ + help = STRING_TOKEN(STR_PRIMARY_PLANE_CURRENT_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 8191,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PRIMARY_PLANE_CURRENT), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_CPUPR1CURRENTLIMIT\ + numeric varid = SETUP_DATA.PR1CurrentLimit,\ + prompt = STRING_TOKEN(STR_SECONDARY_PLANE_CURRENT),\ + help = STRING_TOKEN(STR_SECONDARY_PLANE_CURRENT_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 255,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_SECONDARY_PLANE_CURRENT), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define CPU_ONEOF_ITXT\ + oneof varid = SETUP_DATA.TxtSupport,\ + prompt = STRING_TOKEN(STR_ITXT_PROMPT),\ + help = STRING_TOKEN(STR_ITXT_SUPPORT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_CPUTSTATEENABLE\ + oneof varid = SETUP_DATA.CpuTstate,\ + prompt = STRING_TOKEN(STR_CPU_TSTATE_PROMPT),\ + help = STRING_TOKEN(STR_CPU_TSTATE_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_DTS\ + oneof varid = SETUP_DATA.DtsEnable,\ + prompt = STRING_TOKEN(STR_DTS_PROMPT),\ + help = STRING_TOKEN(STR_DTS_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_DEBUG_INTERFACE\ + oneof varid = SETUP_DATA.DebugInterfaceEnable,\ + prompt = STRING_TOKEN(STR_DEBUG_INTERFACE_PROMPT),\ + help = STRING_TOKEN(STR_DEBUG_INTERFACE_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define CPU_ONEOF_DEBUG_INTERFACE_LOCK\ + oneof varid = SETUP_DATA.DebugInterfaceLock,\ + prompt = STRING_TOKEN(STR_DEBUG_INTERFACE_LOCK_PROMPT),\ + help = STRING_TOKEN(STR_DEBUG_INTERFACE_LOCK_PROMPT_HELP),\ + option text = STRING_TOKEN(STR_CPU_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_CPU_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define VR_NUMERIC_IOUT_OFFSET_SIGN\ + numeric varid = SETUP_DATA.IoutOffsetSign,\ + prompt = STRING_TOKEN(STR_CPU_IOUT_OFFSET_SIGN_PROMPT),\ + help = STRING_TOKEN(STR_CPU_IOUT_OFFSET_SIGN_PROMPT_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_IOUT_OFFSET_PROMPT), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define VR_NUMERIC_IOUT_OFFSET\ + numeric varid = SETUP_DATA.IoutOffset,\ + prompt = STRING_TOKEN(STR_CPU_IOUT_OFFSET_PROMPT),\ + help = STRING_TOKEN(STR_CPU_IOUT_OFFSET_PROMPT_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 625,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_CPU_IOUT_OFFSET_PROMPT), value = 255, flags = MANUFACTURING; \ + endnumeric; + +#define VR_NUMERIC_IOUT_SLOPE\ + numeric varid = SETUP_DATA.IoutSlope,\ + prompt = STRING_TOKEN(STR_CPU_IOUT_SLOPE_PROMPT),\ + help = STRING_TOKEN(STR_CPU_IOUT_SLOPE_PROMPT_HELP),\ + flags = 0 | RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 512,\ + option text = STRING_TOKEN (STR_CPU_IOUT_SLOPE_PROMPT), value = 1023, flags = MANUFACTURING; \ + endnumeric; +#endif //#ifdef CONTROL_DEFINITION + +#ifdef CONTROLS_WITH_DEFAULTS +#if CPU_SETUP_SET_MAX_RATIO + CPU_ONEOF_CPUMAXRATIO +#endif +#if CPU_SETUP_SET_BOOT_RATIO + CPU_ONEOF_CPUBOOTRATIO +#endif + CPU_ONEOF_CPUHTD + CPU_ONEOF_CPUACTIVECORECOUNTGUP2 + CPU_ONEOF_CPUACTIVECORECOUNTGUP5 + CPU_ONEOF_CPUACTIVECORECOUNTGUP3 + CPU_ONEOF_OVERCLOCKING_LOCK + CPU_ONEOF_CPULIMITCPUID + CPU_ONEOF_CPUXDBIT + CPU_ONEOF_CPUVT + CPU_ONEOF_CPUMLCSTREAMER + CPU_ONEOF_CPUMLCSPATIAL + CPU_ONEOF_AES + CPU_ONEOF_BOOTPERFORMANCEMODE + CPU_ONEOF_EIST + CPU_ONEOF_TURBOMODE + CPU_ONEOF_CPUENGPERFBIAS + CPU_ONEOF_TURBOPOWERLIMITLOCK + CPU_NUMERIC_CPUPWRLIMIT1 + CPU_NUMERIC_CPUPWRLIMIT1TIME + CPU_NUMERIC_CPUPWRLIMIT2 + CPU_ONEOF_PLATFORMPOWERLIMITLOCK + CPU_NUMERIC_CPUPWRLIMIT3 + CPU_NUMERIC_CPUPWRLIMIT3TIME + CPU_NUMERIC_CPUPWRLIMIT3DUTYCYCLE + CPU_ONEOF_CXENABLE + CPU_ONEOF_C1EENABLE + CPU_ONEOF_C3ENABLE + CPU_ONEOF_C6ENABLE + CPU_LONGSHORT_C6LATENCY + CPU_ONEOF_C7ENABLE + CPU_LONGSHORT_C7LATENCY + CPU_ONEOF_C8ENABLE + CPU_ONEOF_C9ENABLE + CPU_ONEOF_C10ENABLE + CPU_ONEOF_C1AUTODEMOTIONENABLE + CPU_ONEOF_C3AUTODEMOTIONENABLE + CPU_ONEOF_C1UNDEMOTIONENABLE + CPU_ONEOF_C3UNDEMOTIONENABLE + CPU_ONEOF_PACKAGECDEMOTIONENABLE + CPU_ONEOF_PACKAGECUNDEMOTIONENABLE + CPU_ONEOF_CXPREWAKEENABLE +#if CPU_SETUP_SET_LATENCY_CONTROL + CPU_ONEOF_C3LATENCYCONTROLTIMEUNIT + CPU_NUMERIC_C3LATENCYCONTROLLATENCY + CPU_ONEOF_C6C7SHORTLATENCYCONTROLTIMEUNIT + CPU_NUMERIC_C6C7SHORTLATENCYCONTROLLATENCY + CPU_ONEOF_C6C7LONGLATENCYCONTROLTIMEUNIT + CPU_NUMERIC_C6C7LONGLATENCYCONTROLLATENCY +#endif + CPU_ONEOF_PACKAGECSTATELOCK + CPU_ONEOF_PACKAGECSTATEUPTOC7 + CPU_ONEOF_PACKAGECSTATEUPTOC10 + CPU_ONEOF_CPULAKETINY + CPU_ONEOF_CPUCTDPBIOS + CPU_ONEOF_CPUCONFIGTDPLEVEL + CPU_ONEOF_CPUCTDPLOCK + CPU_NUMERIC_CPUTCCACTIVEOFFSET + CPU_ONEOF_CPU1CORERATIOLIMIT + CPU_ONEOF_CPU2CORERATIOLIMIT + CPU_ONEOF_CPU3CORERATIOLIMIT + CPU_ONEOF_CPU4CORERATIOLIMIT + CPU_ONEOF_CPUVRCURRENTLIMITLOCK + CPU_ONEOF_CPUVRCURRENTLIMIT + CPU_ONEOF_ITXT + CPU_ONEOF_CPUTSTATEENABLE + CPU_ONEOF_DTS + CPU_ONEOF_DEBUG_INTERFACE + CPU_ONEOF_DEBUG_INTERFACE_LOCK + VR_NUMERIC_IOUT_OFFSET_SIGN + VR_NUMERIC_IOUT_OFFSET + VR_NUMERIC_IOUT_SLOPE +#endif //#ifdef CONTROLS_WITH_DEFAULTS + +#ifdef ADVANCED_FORM_SET + + #ifndef SUPPRESS_GRAYOUT_ENDIF + #define SUPPRESS_GRAYOUT_ENDIF endif; + #endif + + #ifdef FORM_SET_TYPEDEF + #include <PlatformCpuLib.h> + #endif + + #ifdef FORM_SET_VARSTORE + varstore SETUP_CPU_FEATURES, + key = AUTO_ID(CPU_FEATURES_ID), + name = SetupCpuFeatures, + guid = SETUP_GUID; + #endif + + #ifdef FORM_SET_ITEM + // Define controls to be added to the main page of the formset + #endif + + #ifdef FORM_SET_GOTO + // Define goto commands for the forms defined in this file + goto CPU_FORM_ID, + prompt = STRING_TOKEN(STR_CPU_FORM), + help = STRING_TOKEN(STR_CPU_FORM_HELP); + #endif + + #ifdef FORM_SET_FORM + #ifndef CPU_FORM_SETUP + #define CPU_FORM_SETUP + + // Define forms + form formid = AUTO_ID(CPU_FORM_ID), + title = STRING_TOKEN(STR_CPU_FORM); + + SUBTITLE(STRING_TOKEN(STR_CPU_FORM)) + SEPARATOR + + SUBTITLE(STRING_TOKEN(STR_CPU_SKT0_VERSION_VALUE)) + + text + help = STRING_TOKEN(STR_CPU_SKT_CPUID_HELP), + text = STRING_TOKEN(STR_CPU_SKT_CPUID_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_CPUID_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_PROCESSOR_FAMILY_HELP), + text = STRING_TOKEN(STR_PROCESSOR_FAMILY_STRING), + text = STRING_TOKEN(STR_PROCESSOR_FAMILY_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_MICROCODE_HELP), + text = STRING_TOKEN(STR_CPU_SKT_MICROCODE_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_MICROCODE_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_FSBSPEED_HELP), + text = STRING_TOKEN(STR_CPU_SKT_FSBSPEED_STRING), + text = STRING_TOKEN(STR_CPU_SKT_FSBSPEED_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_MAXSPEED_HELP), + text = STRING_TOKEN(STR_CPU_SKT_MAXSPEED_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_MAXSPEED_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_MINSPEED_HELP), + text = STRING_TOKEN(STR_CPU_SKT_MINSPEED_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_MINSPEED_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_PROCESSOR_SPEED_HELP), + text = STRING_TOKEN(STR_PROCESSOR_SPEED_STRING), + text = STRING_TOKEN(STR_PROCESSOR_SPEED_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_NUMCORE_HELP), + text = STRING_TOKEN(STR_CPU_SKT_NUMCORE_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_NUMCORE_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_HT_HELP), + text = STRING_TOKEN(STR_CPU_SKT_HT_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_HT_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_VTX_HELP), + text = STRING_TOKEN(STR_CPU_SKT_VTX_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_VTX_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_SMX_HELP), + text = STRING_TOKEN(STR_CPU_SKT_SMX_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_SMX_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_EMT64_HELP), + text = STRING_TOKEN(STR_CPU_EMT64_STRING), + text = STRING_TOKEN(STR_CPU_EMT64_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_EIST_HELP), + text = STRING_TOKEN(STR_CPU_SKT_EIST_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_EIST_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_C3_HELP), + text = STRING_TOKEN(STR_CPU_SKT_C3_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_C3_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_C6_HELP), + text = STRING_TOKEN(STR_CPU_SKT_C6_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_C6_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_C7_HELP), + text = STRING_TOKEN(STR_CPU_SKT_C7_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_C7_VALUE), + flags = 0, key = 0; + + SEPARATOR + + text + help = STRING_TOKEN(STR_CPU_SKT_L1_DATA_CACHE_HELP), + text = STRING_TOKEN(STR_CPU_SKT_L1_DATA_CACHE_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_L1_DATA_CACHE_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_L1_CODE_CACHE_HELP), + text = STRING_TOKEN(STR_CPU_SKT_L1_CODE_CACHE_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_L1_CODE_CACHE_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_L2_CACHE_HELP), + text = STRING_TOKEN(STR_CPU_SKT_L2_CACHE_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_L2_CACHE_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN(STR_CPU_SKT_L3_CACHE_HELP), + text = STRING_TOKEN(STR_CPU_SKT_L3_CACHE_STRING), + text = STRING_TOKEN(STR_CPU_SKT0_L3_CACHE_VALUE), + flags = 0, key = 0; + + SEPARATOR + + suppressif ideqval SETUP_CPU_FEATURES.CpuMismatch == 0; + text + help = STRING_TOKEN(STR_CPU_MISMATCH_VALUE), + text = STRING_TOKEN(STR_CPU_MISMATCH_STRING), + text = STRING_TOKEN(STR_CPU_MISMATCH_VALUE), + flags = 0, key = 0; + endif; + +#if CPU_SETUP_SET_MAX_RATIO + CPU_ONEOF_CPUMAXRATIO +#endif + +#if CPU_SETUP_SET_BOOT_RATIO + CPU_ONEOF_CPUBOOTRATIO +#endif + + suppressif ideqval SETUP_CPU_FEATURES.HTAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUHTD + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.MultiCoreAvailable == 0 OR NOT ideqval SETUP_CPU_FEATURES.CpuGroup == 2; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUACTIVECORECOUNTGUP2 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.MultiCoreAvailable == 0 OR NOT ideqval SETUP_CPU_FEATURES.CpuGroup == 5; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUACTIVECORECOUNTGUP5 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.MultiCoreAvailable == 0 OR NOT ideqval SETUP_CPU_FEATURES.CpuGroup == 3; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUACTIVECORECOUNTGUP3 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_OVERCLOCKING_LOCK + endif; + + suppressif ideqval SETUP_CPU_FEATURES.LimitCpuidAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPULIMITCPUID + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.XDBitAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUXDBIT + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.VTAvailable == 0 OR ideqval SETUP_DATA.TxtSupport == 1; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUVT + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUMLCSTREAMER + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUMLCSPATIAL + endif; + + suppressif ideqval SETUP_CPU_FEATURES.AesAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_AES + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_BOOTPERFORMANCEMODE + endif; + + suppressif ideqval SETUP_CPU_FEATURES.EistAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_EIST + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.TurboModeAvailable == 0 OR ideqval SETUP_DATA.EIST == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_TURBOMODE + CPU_ONEOF_CPUENGPERFBIAS + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.PwrLimitAvailable == 0 + OR ideqval SETUP_DATA.TurboMode == 0 + OR ideqval SETUP_DATA.EIST == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_TURBOPOWERLIMITLOCK + CPU_NUMERIC_CPUPWRLIMIT1 + CPU_NUMERIC_CPUPWRLIMIT1TIME + CPU_NUMERIC_CPUPWRLIMIT2 + CPU_ONEOF_PLATFORMPOWERLIMITLOCK + CPU_NUMERIC_CPUPWRLIMIT3 + CPU_NUMERIC_CPUPWRLIMIT3TIME + CPU_NUMERIC_CPUPWRLIMIT3DUTYCYCLE + DDR_NUMERIC_DDRPWRLIMIT1 + DDR_NUMERIC_DDRPWRLIMIT1TIME + DDR_NUMERIC_DDRPWRLIMIT2 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.XECoreRatioLimitAvailable == 0 + OR ideqval SETUP_DATA.TurboMode == 0 + OR ideqval SETUP_DATA.EIST == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPU1CORERATIOLIMIT + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.XECoreRatioLimitAvailable == 0 OR ideqval SETUP_CPU_FEATURES.NumCores == 1 + OR ideqval SETUP_DATA.TurboMode == 0 + OR ideqval SETUP_DATA.EIST == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPU2CORERATIOLIMIT + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.XECoreRatioLimitAvailable == 0 OR ideqval SETUP_CPU_FEATURES.NumCores == 1 + OR ideqval SETUP_CPU_FEATURES.NumCores == 2 + OR ideqval SETUP_DATA.TurboMode == 0 + OR ideqval SETUP_DATA.EIST == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPU3CORERATIOLIMIT + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.XECoreRatioLimitAvailable == 0 OR ideqval SETUP_CPU_FEATURES.NumCores == 1 + OR ideqval SETUP_CPU_FEATURES.NumCores == 2 OR ideqval SETUP_CPU_FEATURES.NumCores == 3 + OR ideqval SETUP_DATA.TurboMode == 0 OR ideqval SETUP_DATA.EIST == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPU4CORERATIOLIMIT + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.CurrentLimitAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUVRCURRENTLIMITLOCK + CPU_ONEOF_CPUVRCURRENTLIMIT + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CXENABLE + endif; + + suppressif ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C1EENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.C3Available == 0 + OR ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C3ENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.C6Available == 0 + OR ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C6ENABLE + CPU_LONGSHORT_C6LATENCY + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.C7Available == 0 + OR ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C7ENABLE + CPU_LONGSHORT_C7LATENCY + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.C8Available == 0 + OR ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C8ENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.C9Available == 0 + OR ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C9ENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.C10Available == 0 + OR ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C10ENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C1AUTODEMOTIONENABLE + CPU_ONEOF_C3AUTODEMOTIONENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_DATA.CxEnable == 0 + OR ideqval SETUP_CPU_FEATURES.PkgCStateDemotionAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_PACKAGECDEMOTIONENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_C1UNDEMOTIONENABLE + CPU_ONEOF_C3UNDEMOTIONENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_DATA.CxEnable == 0 + OR ideqval SETUP_CPU_FEATURES.PkgCStateDemotionAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_PACKAGECUNDEMOTIONENABLE + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CXPREWAKEENABLE +#if CPU_SETUP_SET_LATENCY_CONTROL + CPU_ONEOF_C3LATENCYCONTROLTIMEUNIT + CPU_NUMERIC_C3LATENCYCONTROLLATENCY + CPU_ONEOF_C6C7SHORTLATENCYCONTROLTIMEUNIT + CPU_NUMERIC_C6C7SHORTLATENCYCONTROLLATENCY + CPU_ONEOF_C6C7LONGLATENCYCONTROLTIMEUNIT + CPU_NUMERIC_C6C7LONGLATENCYCONTROLLATENCY +#endif + CPU_ONEOF_PACKAGECSTATELOCK + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_DATA.CxEnable == 0 + OR ideqval SETUP_CPU_FEATURES.C10Available == 1; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_PACKAGECSTATEUPTOC7 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_DATA.CxEnable == 0 + OR ideqval SETUP_CPU_FEATURES.C10Available == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_PACKAGECSTATEUPTOC10 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_DATA.CxEnable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPULAKETINY + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.cTDPAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUCTDPBIOS + CPU_ONEOF_CPUCONFIGTDPLEVEL + CPU_ONEOF_CPUCTDPLOCK + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SETUP_CPU_FEATURES.TccActivationAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_NUMERIC_CPUTCCACTIVEOFFSET + SUPPRESS_GRAYOUT_ENDIF + + + suppressif ideqval SETUP_CPU_FEATURES.SmxAvailable == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER +#if TCG_SUPPORT || TCG2Support + OR ideqval SETUP_DATA.TpmSupport == 0 +#endif + OR ideqval SETUP_CPU_FEATURES.TpmDeviceAvailable == 0; + CPU_ONEOF_ITXT + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + CPU_ONEOF_CPUTSTATEENABLE + CPU_ONEOF_DTS + CPU_ONEOF_DEBUG_INTERFACE + CPU_ONEOF_DEBUG_INTERFACE_LOCK + VR_NUMERIC_IOUT_OFFSET_SIGN + VR_NUMERIC_IOUT_OFFSET + VR_NUMERIC_IOUT_SLOPE + endif; + endform; + #endif + #endif +#endif + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Board/CPU/CPU.sdl b/Board/CPU/CPU.sdl new file mode 100644 index 0000000..78c159f --- /dev/null +++ b/Board/CPU/CPU.sdl @@ -0,0 +1,470 @@ +TOKEN + Name = "NUMBER_CPU_SOCKETS" + Value = "1" + Help = "Number CPU Sockets on the board. Fixed on 1 for this CPU module" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "CPU_SETUP_SET_MAX_RATIO" + Value = "0" + Help = "Enable setup question force max ratio." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "CPU_SETUP_SET_BOOT_RATIO" + Value = "0" + Help = "Enable setup question to set boot ratio." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "CPU_SETUP_SET_LATENCY_CONTROL" + Value = "0" + Help = "Enable setup question to set latency control." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "CPU_DISPLAY_SETUP_SMX" + Value = "1" + Help = "Enables display CPU SMX supported." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "RC_POLICY_POWER_UNIT" + Value = "0" + Help = "This is used for Intel Haswell RC policy. 0 - in Watts, 1 - in 125 Milli Watts" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "NCPU" + Value = "16" + Help = "Maximum number of processor threads." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "MTRR_POLICY" + Value = "1" + Help = "Maximum number of processor threads." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "CPU_MAX_MEMORY_SIZE" + Value = "0x100000000" + Help = "Maximum memory size addressable by the CPU" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "CPU_MAX_IO_SIZE" + Value = "0x10000" + Help = "Maximum I/O size addressable by the CPU" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SW_SMI_PSTATE_CNT" + Value = "0" + Help = "VALUE to write into SMI CMD register to enter\CPU performance state control mode (if any)" + TokenType = Integer + TargetH = Yes + Range = "0-0xff 0 = not supported" + Token = "ACPI_BUILD_TABLES_2_0" "=" "1" +End + +TOKEN + Name = "SW_SMI_CST_CNT" + Value = "0" + Help = "Value to write in SMI_CMD reg to support _CST object and change state notification" + TokenType = Integer + TargetH = Yes + Range = "0-0xff" + Token = "ACPI_BUILD_TABLES_2_0" "=" "1" +End + +TOKEN + Name = "NEHALEM_CPU_MODULE" + Value = "1" + Help = "Nehalem CPU module is present" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Lock = Yes +End + +TOKEN + Name = "LOCAL_APIC_BASE" + Value = "0xfee00000" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "APIC_ID_REGISTER" + Value = "0x20" + Help = "APIC Identification Register Index" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "APIC_VERSION_REGISTER" + Value = "0x30" + Help = "APIC Version Register Index" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "APIC_SPURIOUS_VECTOR_REGISTER" + Value = "0xf0" + Help = "APIC Spurious Interrupt Vector Register Index" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "APIC_ICR_LOW_REGISTER" + Value = "0x300" + Help = "APIC Interrupt Control Register Low Index" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "APIC_ICR_HIGH_REGISTER" + Value = "0x310" + Help = "APIC Interrupt Control Register High Index" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "APIC_LVT_LINT0_REGISTER" + Value = "0x350" + Help = "APIC LVT LINT0 Register Index" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "APIC_LVT_LINT1_REGISTER" + Value = "0x360" + Help = "APIC LVT LINT1 Register Index" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SEC_CREATE_PE32" + Value = "1" + Help = "Create SEC Core PE32 Image." + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes +End + +TOKEN + Name = "CAR_BASE_ADDRESS" + Value = "(0xffffffff - $(FLASH_SIZE) + 1 - 0x100000) & 0xfff00000" + Help = "DO NOT CHANGE THIS VALUE.\Cache-as-RAM physical base location" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "CAR_TOTAL_SIZE" + Value = "0x20000" + Help = "Total Cache-as-RAM size available (in bytes)" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "PEI_CACHE_FLASH_ENABLED" + Value = "1" + Help = "Enable caching the flash during PEI." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "CODE_CACHE_BASE_ADDRESS" + Value = "0xffffffff - 0x100000 + 1" + Help = "Code Cache Base Address." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "CODE_CACHE_SIZE" + Value = "100000h" + Help = "Code Cache Size.\Max 40000h. Size must match aligment of base." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "CODE_CACHE_PART2_BASE" + Value = "0" + Help = "Code Cache PART 2 Base Address. 0 = No PART 2" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "CODE_CACHE_PART2_SIZE" + Value = "10000h" + Help = "Code Cache PART 2 Size ." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "WDB_REGION_BASE_ADDRESS" + Value = "0" + Help = "Write-Combined Cache Base Address. 0 = No WDB" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "WDB_REGION_BASE_SIZE" + Value = "1000h" + Help = "Write-Combined Cache Size ." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SMM_FROM_SMBASE_DRIVER" + Value = "0x55" + Help = "SWSMI number used in CPU RC" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "SMM_BASE_SAVE_STATE_OFFSET" + Value = "0fef8h" + Help = "Offset in the CPU SMM save state area where the SMM Base value is stored. \This offset is used to change the SMM Base location during next SMI." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "MAX_SMM_SAVE_STATE_SIZE" + Value = "0x400" + Help = "Largest SMM save state size of any CPU that can be placed on the board.\Currently, Intel 64-bit CPUs use 0x300 for its save state size.\" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "IED_SAVESTATE_OFFSET" + Value = "0xfeec" + Help = "Intel Enhanced Debug Save" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "ACPI_INFO2_PROTOCOL_PUBLISHED" + Value = "1" + Help = "ACPI INFO2 PROTOCOL is published by this module." + TokenType = Boolean + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "PERF_TUNE_SUPPORT" + Value = "0" + Help = "This token is for performance tunning support.\The major function of performnce tunning is not done in CPU module, it's in performance tunning module.\Do not change this token directly." + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "I3_CPU_NON_TURBO" + Value = "1" + Help = "Force i3 Cpu turbo mode not available" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "BRAND_STRING_WORKAROUND" + Value = "0" + Help = "This sample code is a workaround for prevent Windows displays 2 different frequencies brand string within the My Computer -> Properties.It will configure custom tdp table. And if use this workaround, the parameter in the custom ctdp settings shoule vary with platform." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "MPDTable_CREATED" + Value = "1" + Help = "Create MPDT Table." + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes +End + + +TOKEN + Name = "SMM_ACCESS_CHECK_ENABLE" + Value = "0" + Help = "Enable or disable Smm Access Check Feature of Cpu" + TokenType = Boolean + TargetH = Yes +End + +PATH + Name = "CPU_BOARD_DIR" + Path = "Board\CPU" +End + +PATH + Name = "CPU_CORE_DIR" + Path = "Core\CPU" +End + +MODULE + Help = "Includes CPU.mak to Project" + File = "CPU.mak" +End + +ELINK + Name = "$(BUILD_DIR)\CpuDxe.ffs" + Parent = "FV_MAIN" + Priority = 0 + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\CPU.sdb" + Parent = "SETUP_SDBS" + Priority = 10 + InvokeOrder = AfterParent +End + +ELINK + Name = "$(CPU_BOARD_DIR)\CPU.sd" + Parent = "SETUP_DEFINITIONS" + Priority = 10 + InvokeOrder = AfterParent +End + +ELINK + Name = "CPUPEIDBG_Initialize," + Parent = "PeiDebuggerInitialize" + Priority = 100 + Token = "PeiDebugger_SUPPORT" "!=" "0" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SecCore.ffs" + Parent = "FV_BB" + Help = "SEC Core" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\CpuPeiBeforeMem.ffs" + Parent = "FV_BB" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\CPUPEI.ffs" + Parent = "FV_BB" + InvokeOrder = AfterParent +End + +ELINK + Name = "InitCPUStrings," + Parent = "SetupStringInit" + InvokeOrder = AfterParent +End + +ELINK + Name = "-i $(CPU_BOARD_DIR)" + Parent = "SETUP_VFR_INCLUDES" + InvokeOrder = AfterParent +End + +ELINK + Name = "SECCoreAtPowerOn" + Segment = "STARTUP_SEG" + Help = "SEC Core Init after power-on and before memory detection." + mSTART = "mSTART_PROC_NEAR32" + mBODY = "mBODY_JMP_PROC_NEAR32" + mEND = "mEND_PROC_WITH_JMP_NEAR32" + mEXTERN = "mEXTERN_NEAR32" + SrcFile = "$(BUILD_DIR)\SECCore.ASM" + InvokeOrder = TableFunction + OutBOOT = Yes +End + +ELINK + Name = "ADDON_SEC_CORE_OBJ_FILES" + InvokeOrder = ReplaceParent +End + +OUTPUTREGISTER + Name = "EKERNEL_BOOT" + Path = "BUILD\" + File = "SECCore.ASM" +End + +SEGMENT + Name = "STARTUP_SEG" + Format = "SEGMENT PARA PUBLIC 'CODE' USE32" +End + diff --git a/Board/CPU/CPU.uni b/Board/CPU/CPU.uni Binary files differnew file mode 100644 index 0000000..97f25ed --- /dev/null +++ b/Board/CPU/CPU.uni diff --git a/Board/CPU/CPUBSP.cif b/Board/CPU/CPUBSP.cif new file mode 100644 index 0000000..3017eca --- /dev/null +++ b/Board/CPU/CPUBSP.cif @@ -0,0 +1,20 @@ +<component> + name = "CPU Board" + category = ModulePart + LocalRoot = "Board\CPU" + RefName = "CPU Board" +[files] +"CPU.sdl" +"CPU.mak" +"CPU.EQU" +"CPU.sd" +"CPU.uni" +"CPUPwrMgt.uni" +"CPUSetup.c" +"CpuSmbios.sdl" +"PlatformCpuLib.h" +"PlatformCpuLib.c" +"CpuPeiDebugger.c" +[parts] +"CpuRcPolicyWrap" +<endComponent> diff --git a/Board/CPU/CPUPwrMgt.uni b/Board/CPU/CPUPwrMgt.uni Binary files differnew file mode 100644 index 0000000..4d24035 --- /dev/null +++ b/Board/CPU/CPUPwrMgt.uni diff --git a/Board/CPU/CPUSetup.c b/Board/CPU/CPUSetup.c new file mode 100644 index 0000000..81572d2 --- /dev/null +++ b/Board/CPU/CPUSetup.c @@ -0,0 +1,750 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CPUSetup.c 6 4/10/15 2:37a Crystallee $ +// +// $Revision: 6 $ +// +// $Date: 4/10/15 2:37a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CPUSetup.c $ +// +// 6 4/10/15 2:37a Crystallee +// +// 5 5/09/13 10:54p Crystallee +// [TAG] EIP123326 +// [Category] Improvement +// [Description] Show "Processor family" and "FSB speed" on CPU +// Configuration in BIOS setup menu. +// +// 4 11/07/12 4:37a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] L4 Cache support improve +// +// 3 10/17/12 1:57a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] L4 cache support +// +// 2 3/16/12 3:35a Davidhsieh +// Setup items create for CPU RC policy +// +// 1 2/07/12 3:57a Davidhsieh +// +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: CPUSetup.c +// +// Description: CPU Setup Rountines +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <Setup.h> +#include "AmiCspLibInc.h" +#include <SetupStrTokens.h> +#include <AmiDxeLib.h> +#include <Protocol\AmiCpuInfo.h> +#include <Protocol\AmiCpuInfo2.h> +#include <AmiHobs.h> +#include "token.h" + +#define SANDY_BRIDGE 0x206a0 +#define JAKETOWN 0x206d0 +#define PlatformInfoMsr 0xce + +typedef struct { + STRING_REF Ver; + STRING_REF Id; + STRING_REF Family; + STRING_REF Microcode; + STRING_REF MaxSpeed; + STRING_REF MinSpeed; + STRING_REF L1DataSize; + STRING_REF L1CodeSize; + STRING_REF L2Size; + STRING_REF L3Size; + STRING_REF NumCores; + STRING_REF HyperThreading; + STRING_REF Vtx; + STRING_REF Smx; + STRING_REF Eist; + STRING_REF CpuC3; + STRING_REF CpuC6; + STRING_REF CpuC7; +} SKT_STR_TOK; + +static SKT_STR_TOK gSktStrTok[] = { +{ STRING_TOKEN(STR_CPU_SKT0_VERSION_VALUE), + STRING_TOKEN(STR_CPU_SKT0_CPUID_VALUE), + STRING_TOKEN(STR_PROCESSOR_FAMILY_VALUE), + STRING_TOKEN(STR_CPU_SKT0_MICROCODE_VALUE), + STRING_TOKEN(STR_CPU_SKT0_MAXSPEED_VALUE), + STRING_TOKEN(STR_CPU_SKT0_MINSPEED_VALUE), + STRING_TOKEN(STR_CPU_SKT0_L1_DATA_CACHE_VALUE), + STRING_TOKEN(STR_CPU_SKT0_L1_CODE_CACHE_VALUE), + STRING_TOKEN(STR_CPU_SKT0_L2_CACHE_VALUE), + STRING_TOKEN(STR_CPU_SKT0_L3_CACHE_VALUE), + STRING_TOKEN(STR_CPU_SKT0_NUMCORE_VALUE), + STRING_TOKEN(STR_CPU_SKT0_HT_VALUE), + STRING_TOKEN(STR_CPU_SKT0_VTX_VALUE), + STRING_TOKEN(STR_CPU_SKT0_SMX_VALUE), + STRING_TOKEN(STR_CPU_SKT0_EIST_VALUE), + STRING_TOKEN(STR_CPU_SKT0_C3_VALUE), + STRING_TOKEN(STR_CPU_SKT0_C6_VALUE), + STRING_TOKEN(STR_CPU_SKT0_C7_VALUE) +}}; + +static UINT32 gL1DataCacheSize; +static UINT32 gL1CodeCacheSize; +static UINT32 gL2CacheSize; +static UINT32 gL3CacheSize; +static UINT32 gL4CacheSize; + +static BOOLEAN gL1Shared; +static BOOLEAN gL2Shared; +static BOOLEAN gL3Shared; +static BOOLEAN gL4Shared; + +static EFI_GUID gAmiSetupGuid = SETUP_GUID; +static EFI_GUID gAmiCpuInfoProtocolGuid = AMI_CPU_INFO_PROTOCOL_GUID; +static EFI_GUID gAmiCpuInfo2ProtocolGuid = AMI_CPU_INFO_2_PROTOCOL_GUID; +static EFI_GUID gHobListGuid = HOB_LIST_GUID; +//static EFI_GUID gAmiInternalFactoryTdcTdpHobGuid = AMI_INTERNAL_FACTORY_TDC_TDP_HOB_GUID; +//static EFI_GUID gSetupNvramUpdateGuid = { \ +// 0xd84beff0, 0x159a, 0x4b60, 0x9a, 0xb9, 0xac, 0x5c, 0x47, 0x4b, 0xd3, 0xb1 +//}; +static EFI_GUID gCpuInfoHobGuid = AMI_CPUINFO_HOB_GUID; +static EFI_HII_HANDLE gHiiHandle; +static CPUINFO_HOB *gCpuInfoHob; +//static AMI_INTERNAL_FACTORY_TDC_TDP_HOB *gTdcTdpHob; //May not be present. + +static AMI_CPU_INFO_PROTOCOL *gCpuInfoProt; +static AMI_CPU_INFO_2_PROTOCOL *gCpuInfo2Prot; + +static VOID InitCpuInfo(); + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Procedure: GetBoardSocketNumber +// +// Description: Get socket number from Apic ID. +// +// Input: +// IN UINT32 ApicId +// +// Output: UINT32 - Physical Socket Id +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +static UINT32 GetBoardSocketNumber(IN UINT32 ApicId) +{ + UINT32 RegEax, RegEbx, RegEcx, RegEdx; + UINT8 MaxThreadsPackage; + + CPULib_CpuID(1, &RegEax, &RegEbx, &RegEcx, &RegEdx); + + MaxThreadsPackage = (UINT8)(RegEbx >> 16); + + return ApicId / MaxThreadsPackage; +} + + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Procedure: GetMaxSpeedFromBrandString +// +// Description: Get the max speed from the brand string. +// +// Input: +// IN CHAR8 *CpuBrandString - Pointer to CPU brand string. +// OUT CHAR8 *CpuMaxSpeedString -Pointer to string with format "9999 MHz"; 9999 can be any 4 digit number. +// +// Output: BOOLEAN - TRUE if frequency found. +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetMaxSpeedFromBrandString(IN CHAR8 *CpuBrandString, OUT CHAR8 *CpuMaxSpeedString) +{ + UINT32 i; + UINT8 CharCount; + BOOLEAN TransToMHz = FALSE; + BOOLEAN FreqStringFound; + + while (*CpuBrandString != 0) { + if (*CpuBrandString == 'G' && *(CpuBrandString + 1) == 'H' && *(CpuBrandString + 2) == 'z') { + FreqStringFound = TRUE; + TransToMHz = TRUE; + break; + } else if (*CpuBrandString == 'M' && *(CpuBrandString+1) == 'H' && *(CpuBrandString + 2) == 'z') { + FreqStringFound = TRUE; + break; + } else ++CpuBrandString; + } + + --CpuBrandString; //first numeric char + + //search numeric char + CharCount = 0; + for(i = 0 ; i < 4; ++i) { + if (*CpuBrandString >= '0' && *CpuBrandString <= '9') { + --CpuBrandString; + ++CharCount; + } else if (*CpuBrandString == '.') { + --CpuBrandString; + ++CharCount; + } else break; + } + + ++CpuBrandString; //first numeric char + + if (FreqStringFound && CharCount > 0) { + for(i = 0; i < CharCount; ++i) { + if (TransToMHz && *CpuBrandString == '.') CpuBrandString++; + + CpuMaxSpeedString[i] = *CpuBrandString; + ++CpuBrandString; + } + if (TransToMHz) CpuMaxSpeedString[3] = '0'; + } else FreqStringFound = FALSE; + + return FreqStringFound; +} +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Procedure: FillCacheData +// +// Description: Init global cache data varilable +// +// Input: +// IN AMI_CPU_INFO_2_CACHE_DESCR *CacheDesc +// IN UINT32 NumCacheEntries +// +// Output: VOID +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID FillCacheData(IN AMI_CPU_INFO_2_CACHE_DESCR *CacheDesc, IN UINT32 NumCacheEntries) +{ + AMI_CPU_INFO_2_CACHE_DESCR *ptr = CacheDesc; + while (NumCacheEntries--) { + switch(ptr->Level) { + case 1: + switch(ptr->Type) { + case AMI_CPU_INFO_2_CACHE_TYPE_DATA: gL1DataCacheSize = ptr->Size; break; + case AMI_CPU_INFO_2_CACHE_TYPE_CODE: gL1CodeCacheSize = ptr->Size; break; + default: ASSERT(FALSE); // Not valid cache for setup display. + } + gL1Shared = ptr->Shared != AMI_CPU_INFO_2_CACHE_SHARED_CORE; + break; + case 2: + switch(ptr->Type) { + case AMI_CPU_INFO_2_CACHE_TYPE_UNIFIED: gL2CacheSize = ptr->Size; break; + default: ASSERT(FALSE); //Not valid cache for setup display. + } + gL2Shared = ptr->Shared != AMI_CPU_INFO_2_CACHE_SHARED_CORE; + break; + case 3: + switch(ptr->Type) { + case AMI_CPU_INFO_2_CACHE_TYPE_UNIFIED: gL3CacheSize = ptr->Size; break; + default: ASSERT(FALSE); //Not valid cache for setup display. + } + gL3Shared = ptr->Shared != AMI_CPU_INFO_2_CACHE_SHARED_CORE; + break; + case 4: + switch(ptr->Type) { + case AMI_CPU_INFO_2_CACHE_TYPE_UNIFIED: gL4CacheSize = ptr->Size; break; + default: ASSERT(FALSE); //Not valid cache for setup display. + } + gL4Shared = ptr->Shared != AMI_CPU_INFO_2_CACHE_SHARED_CORE; + break; + default: + ASSERT(FALSE); //Invalid entry; + } + + ptr = (AMI_CPU_INFO_2_CACHE_DESCR*)((UINT8*)ptr + ptr->LengthDesc); + } +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Procedure: LocateCpuInfoProt +// +// Description: Callback on AMI CPU INFO protocol. Then call to init strings. +// +// Input: +// IN EFI_EVENT Event - Not used +// IN VOID *Context - Not Used +// +// Output: VOID +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID LocateCpuInfoProt(IN EFI_EVENT Event, IN VOID *Context) +{ + pBS->LocateProtocol (&gAmiCpuInfoProtocolGuid, NULL, &gCpuInfoProt); + InitCpuInfo(); +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// +// Procedure: LocateCpuInfoProt +// +// Description: Callback on AMI CPU INFO 2 protocol. Then call to init strings. +// +// Input: +// IN EFI_EVENT Event - Not used +// IN VOID *Context - Not Used +// +// Output: VOID +// +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID LocateCpuInfo2Prot(IN EFI_EVENT Event, IN VOID *Context) +{ + pBS->LocateProtocol (&gAmiCpuInfo2ProtocolGuid, NULL, &gCpuInfo2Prot); + InitCpuInfo(); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InitCpuInfo +// +// Description: Initialize CPU strings. +// +// Input: VOID +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +static VOID InitCpuInfo() +{ + UINTN CpuNumber = 0; + AMI_CPU_INFO *GetCpuInfo = NULL; + CHAR8 CpuMaxSpeedString[] = "9999 MHz"; + OUT AMI_CPU_INFO_2_CACHE_DESCR *CacheDesc; + OUT UINT32 NumCacheEntries; + UINT32 Bclk; + UINT32 i = 0; + BOOLEAN FreqStringFound = FALSE; + UINT32 RegEax, RegEbx, RegEcx, RegEdx; + BOOLEAN EistSupported = FALSE; + BOOLEAN C3Supported = FALSE; + BOOLEAN C6Supported = FALSE; + BOOLEAN C7Supported = FALSE; + EFI_STATUS Status; + + if (gCpuInfoProt == NULL) return; + if (gCpuInfo2Prot == NULL) return; + + Bclk = 100; //Bclk = 100 for SandyBridge and IvyBridge + + CPULib_CpuID(1, &RegEax, &RegEbx, &RegEcx, &RegEdx); + if (RegEcx & 0x80) EistSupported = TRUE; + CPULib_CpuID(5, &RegEax, &RegEbx, &RegEcx, &RegEdx); + if ((RegEdx >> 8) & 0xf) C3Supported = TRUE; + if ((RegEdx >> 12) & 0xf) C6Supported = TRUE; + if ((RegEdx >> 16) & 0xf) C7Supported = TRUE; + + gCpuInfoProt->GetCpuInfo(gCpuInfoProt, CpuNumber, &GetCpuInfo); + +#if CPU_SETUP_SET_MAX_RATIO +{ + BOOLEAN HasTurbo; + + CPULib_CpuID(6, &RegEax, &RegEbx, &RegEcx, &RegEdx); + HasTurbo = !!(RegEax & 2); + + if (HasTurbo) { + InitString( + gHiiHandle, + STRING_TOKEN(STR_CPU_MAX_RATIO_HELP), + L"Non Turbo Range: %d - %d. Turbo ratio: %d. If out of range ratio, maximum or minimum ratio is used. This sets the maximum ratio.", + Shr64(ReadMsr(PlatformInfoMsr),40) & 0xff, //Get Max and Min ratio from MSR + Shr64(ReadMsr(PlatformInfoMsr),8) & 0xff, + (Shr64(ReadMsr(PlatformInfoMsr),8) & 0xff )+ 1 + ); + } else { + InitString( + gHiiHandle, + STRING_TOKEN(STR_CPU_MAX_RATIO_HELP), + L"Range: %d - %d. If out of range ratio, maximum or minimum ratio is used. This sets the maximum ratio.", + Shr64(ReadMsr(PlatformInfoMsr),40) & 0xff, + Shr64(ReadMsr(PlatformInfoMsr),8) & 0xff + ); + } +} +#endif +#if CPU_SETUP_SET_BOOT_RATIO + InitString( + gHiiHandle, + STRING_TOKEN(STR_CPU_SET_BOOT_RATIO_HELP), + L"Range: %d - %d. If out of range ratio, maximum ratio is used. This sets the boot ratio. Non-ACPI OSes will use this ratio.", + Shr64(ReadMsr(PlatformInfoMsr),40) & 0xff, + Shr64(ReadMsr(PlatformInfoMsr),8) & 0xff + ); +#endif + + if (GetCpuInfo->X64Supported == 0) { + InitString( + gHiiHandle, + STRING_TOKEN(STR_CPU_EMT64_VALUE), + L"%a", + "Not Supported" + ); + } + + InitString( + gHiiHandle, + STRING_TOKEN(STR_PROCESSOR_SPEED_VALUE), + L"%d MHz", + (Shr64(ReadMsr(0x198),8) & 0xff) * Bclk + ); + + { + UINT32 PhysSocket; + UINT32 NumCores; + UINT32 NumThreads; + CHAR8 *CpuBrandString; + + PhysSocket = 0; + + Status = gCpuInfo2Prot->GetNumCoresThreads(gCpuInfo2Prot, i, + &NumCores, &NumThreads, NULL, NULL + ); + ASSERT_EFI_ERROR(Status); + + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].Ver, + L"%a", + GetCpuInfo->BrandString + ); + + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].Id, + L"%x", + GetCpuInfo->Version + ); + + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].Family, + L"%x", + ((GetCpuInfo->Version >> 8) & 0xf) + ); + + if(GetCpuInfo->MicroCodeVers != 0) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].Microcode, + L"%x", + GetCpuInfo->MicroCodeVers + ); + } + + CpuBrandString = GetCpuInfo->BrandString; + FreqStringFound = GetMaxSpeedFromBrandString(CpuBrandString, CpuMaxSpeedString); + + if (FreqStringFound) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].MaxSpeed, + L"%a", + CpuMaxSpeedString + ); + } else { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].MaxSpeed, + L"%d MHz", + (Shr64(ReadMsr(PlatformInfoMsr),8) & 0xff )* Bclk + ); + } + + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].MinSpeed, + L"%d MHz", + (Shr64(ReadMsr(PlatformInfoMsr),40) & 0xff )* Bclk //Get MinRatio from MSR + ); + + gL1DataCacheSize = 0; + gL1CodeCacheSize = 0; + gL2CacheSize = 0; + gL3CacheSize = 0; + + //Get cache data + Status = gCpuInfo2Prot->GetCoreCacheDesc(gCpuInfo2Prot, i, 0, &CacheDesc, &NumCacheEntries); + ASSERT_EFI_ERROR(Status); + + //Fill cache data + if (!EFI_ERROR(Status)) { + FillCacheData(CacheDesc, NumCacheEntries); + } + + if (gL1DataCacheSize) { + if (gL1Shared) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].L1DataSize, + L"%d kB", + gL1DataCacheSize + ); + } else { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].L1DataSize, + L"%d kB x %i", + gL1DataCacheSize, + NumCores + ); + } + } + + if (gL1CodeCacheSize) { + if (gL1Shared) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].L1CodeSize, + L"%d kB", + gL1CodeCacheSize + ); + } else { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].L1CodeSize, + L"%d kB x %i", + gL1CodeCacheSize, + NumCores + ); + } + } + + if (gL2CacheSize) { + if (gL2Shared) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].L2Size, + L"%d kB", + gL2CacheSize + ); + } else { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].L2Size, + L"%d kB x %i", + gL2CacheSize, + NumCores + ); + } + } + + if (gL3CacheSize) { + if (gL3Shared) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].L3Size, + L"%d kB", + gL3CacheSize + ); + } else { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].L3Size, + L"%d kB x %i", + gL3CacheSize, + NumCores + ); + } + } + + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].NumCores, + L"%i", + GetCpuInfo->NumCores + ); + + if(GetCpuInfo->NumHts > 1) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].HyperThreading, + L"%a", + "Supported" + ); + } + + if (GetCpuInfo->Features & (UINT64)1 << (32 + 5)) { //CPUID eax=1 ecx[5] + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].Vtx, + L"%a", + "Supported" + ); + } + + if (GetCpuInfo->Features & (UINT64)1 << (32 + 6)) { //CPUID eax=1 ecx[6] + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].Smx, + L"%a", + "Supported" + ); + } + + if (EistSupported) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].Eist, + L"%a", + "Supported" + ); + } + + if (C3Supported) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].CpuC3, + L"%a", + "Supported" + ); + } + + if (C6Supported) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].CpuC6, + L"%a", + "Supported" + ); + } + + if (C7Supported) { + InitString( + gHiiHandle, + gSktStrTok[PhysSocket].CpuC7, + L"%a", + "Supported" + ); + } + + CpuNumber += GetCpuInfo->NumCores * (GetCpuInfo->NumHts == 0 ? 1 : 2); + gCpuInfoProt->GetCpuInfo(gCpuInfoProt, CpuNumber, &GetCpuInfo); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InitCpuInfo +// +// Description: Initialize CPU strings. +// +// Input: +// IN EFI_HII_HANDLE HiiHandle +// IN UINT16 Class +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitCPUStrings(EFI_HII_HANDLE HiiHandle, UINT16 Class) +{ + EFI_EVENT AmiCpuInfoEvt; + EFI_STATUS Status; + VOID *CpuNotifyReg; + VOID *FirstHob; + + if (Class != ADVANCED_FORM_SET_CLASS) return; + gHiiHandle = HiiHandle; + + FirstHob = GetEfiConfigurationTable(pST, &gHobListGuid); + ASSERT(FirstHob); + if (FirstHob == NULL) return; + + gCpuInfoHob = (CPUINFO_HOB*)FirstHob; + //Find CpuInfo Info Hob. + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &gCpuInfoHob))) { + if (guidcmp(&gCpuInfoHob->EfiHobGuidType.Name, &gCpuInfoHobGuid) == 0) break; + } + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + Status = pBS->LocateProtocol (&gAmiCpuInfoProtocolGuid, NULL, &gCpuInfoProt); + if (EFI_ERROR(Status)) gCpuInfoProt = NULL; + + Status = pBS->LocateProtocol (&gAmiCpuInfo2ProtocolGuid, NULL, &gCpuInfo2Prot); + if (EFI_ERROR(Status)) gCpuInfo2Prot = NULL; + + + InitCpuInfo(); + + if (gCpuInfoProt == NULL) { + Status = RegisterProtocolCallback( + &gAmiCpuInfoProtocolGuid, + LocateCpuInfoProt, + NULL, + &AmiCpuInfoEvt, + &CpuNotifyReg + ); + ASSERT_EFI_ERROR(Status); + } + if (gCpuInfoProt == NULL) { + Status = RegisterProtocolCallback( + &gAmiCpuInfo2ProtocolGuid, + LocateCpuInfo2Prot, + NULL, + &AmiCpuInfoEvt, + &CpuNotifyReg + ); + ASSERT_EFI_ERROR(Status); + } +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/CpuPeiDebugger.c b/Board/CPU/CpuPeiDebugger.c new file mode 100644 index 0000000..de14bfe --- /dev/null +++ b/Board/CPU/CpuPeiDebugger.c @@ -0,0 +1,99 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuPeiDebugger.c 1 2/07/12 3:57a Davidhsieh $ +// +// $Revision: 1 $ +// +// $Date: 2/07/12 3:57a $ +// +//***************************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuPeiDebugger.c $ +// +// 1 2/07/12 3:57a Davidhsieh +// +//***************************************************************************** + +//<AMI_FHDR_START> +//---------------------------------------------------------------------------- +// +// Name: CpuPeiDebugger.C +// +// Description: +// This file contains PEI stage board component code for Template CPU module +// +//---------------------------------------------------------------------------- +//<AMI_FHDR_END> +#include <Efi.h> +#include <AmiLib.h> +#include <Token.h> +#include "AmiDebugPort.h" +#include "CpuCspLib.h" + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: CPUPEIDBG_Initialize +// +// Description: +// This eLink function is used to initialize CPU for PEI debugger support +// +// Input: DbgXportIfStruc Debug transport interface structure +// +// Output: EFI_STATUS +// +// Notes: PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +CPUPEIDBG_Initialize ( + PEI_DBG_PORT_INFO *DebugPort +) +{ + MemReadWrite32((UINT32*)(UINTN)(LOCAL_APIC_BASE + APIC_SPURIOUS_VECTOR_REGISTER), 1 << 8, 0xffffffff); + + //-------------------------- + //Program Virtual Wire Mode. + //-------------------------- + + //Program LINT0 vector as ExtInt + MemReadWrite32((UINT32*)(UINTN)(LOCAL_APIC_BASE + APIC_LVT_LINT0_REGISTER), + 0x700, 0xfffe00ff + ); + + //Program the LINT1 vector entry as NMI + MemReadWrite32((UINT32*)(UINTN)(LOCAL_APIC_BASE + APIC_LVT_LINT1_REGISTER), + 0x10400, 0xfffe00ff + ); + + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyDxe.c b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyDxe.c new file mode 100644 index 0000000..033ed88 --- /dev/null +++ b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyDxe.c @@ -0,0 +1,742 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuRcPolicyWrap/CpuRcPolicyDxe.c 26 4/10/15 4:08a Crystallee $ +// +// $Revision: 26 $ +// +// $Date: 4/10/15 4:08a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuRcPolicyWrap/CpuRcPolicyDxe.c $ +// +// 26 4/10/15 4:08a Crystallee +// +// 25 1/22/15 4:34a Crystallee +// +// 24 12/19/13 3:38a Crystallee +// +// 23 12/18/13 10:23p Crystallee +// [TAG] EIP145605 +// [Category] Improvement +// [Description] Intel Workaround - custom TDP table implementation. Add +// a workaround for prevent Windows displays 2 different frequencies brand +// string within the My Computer -> Properties. +// +// 22 8/28/13 5:45a Crystallee +// +// 21 8/14/13 4:56a Davidhsieh +// [TAG] EIP131295 +// [Category] Improvement +// [Description] Add token to force turbo mode is not supported for i3 +// Cpu +// +// 20 6/03/13 2:38a Hsingyingchung +// [TAG] EIP123835 +// [Category] Spec Update +// [Severity] Important +// [Description] SBY Performance Tuning Guid rev. 1.1 update. +// +// 19 4/07/13 11:52p Hsingyingchung +// [TAG] EIPNone +// [Category] Improvement +// [Description] Modify CustomPowerUnit of Haswell RC if add XTU +// +// 18 4/03/13 4:58a Crystallee +// [TAG] EIP119880 +// [Category] Improvement +// [Description] Provide setup items which is related to PowerLimit3. +// +// 17 3/28/13 4:01a Davidhsieh +// [TAG] None +// [Category] Bug Fix +// [Severity] Important +// [Symptom] ACPI T state table is not reported +// [RootCause] T state function enable policy in Haswell RC is not +// correct. +// [Solution] Correct the T state function policy +// +// 16 3/05/13 6:55a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Token RC_POLICY_POWER_UNIT create for Haswell RC +// CustomPowerUnit +// +// 15 2/22/13 1:54a Crystallee +// [TAG] EIP112238 +// [Category] Improvement +// [Description] Refer Intel BIOS and provide setup items for Intel +// Haswell RC policy. +// +// 14 2/07/13 3:54a Hsingyingchung +// [TAG] EIP112631 +// [Category] Improvement +// [Description] update for 4.6.5.0_XtuHswSetup_004 +// +// 13 1/24/13 5:18a Crystallee +// [TAG] None +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Change C state limit to C10, the system will hang. +// [RootCause] BIOS doesn't limit the C state to CPU support. +// [Solution] According to the CPU C state support, add C state limit to +// prevent system hanging and limit the setup item choice. +// +// 12 1/15/13 1:56a Crystallee +// [TAG] EIP103130 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] SHB MB: Passive Trip Point is not Active +// [RootCause] BIOS doesn't correct to disable "AutoThermalReporting" +// variable in the CPU DXE Platform Policy. +// [Solution] Correct the "AutoThermalReporting" variable in +// ThermalFuncEnables in POWER_MGMT_CONFIG +// +// 11 12/03/12 9:50p Davidhsieh +// [TAG] EIP108401 +// [Category] Improvement +// [Description] Create setup items for VrMiscIoutOffset, +// VrMiscIoutSlope and LakeTiny +// +// 10 11/23/12 2:04a Hsingyingchung +// +// 9 11/18/12 9:36p Davidhsieh +// [TAG] EIP105980 +// [Category] Improvement +// [Description] Setup items for Package C State Limit and Energy +// Performance +// +// 8 10/28/12 11:37p Davidhsieh +// [TAG] EIP105017 +// [Category] Improvement +// [Description] Implement Setup Options for Debug Interface Enable/Lock +// +// 7 10/17/12 2:21a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Setup items CTDP BIOS, C8, C9 and C10 created +// +// 6 9/13/12 3:33a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Add DTS setup item +// +// 5 8/06/12 10:48p Davidhsieh +// [TAG] EIP95485 +// [Category] Improvement +// [Description] Configure TXT Feature via setup option +// +// 4 7/19/12 2:22a Davidhsieh +// [TAG] EIP95485 +// [Category] Improvement +// [Description] Enable VT when TXT is enabled +// +// 3 5/22/12 3:00a Davidhsieh +// Setup page layout change +// +// 2 3/16/12 3:45a Davidhsieh +// Setup items create for CPU RC policy +// +// 1 2/07/12 3:57a Davidhsieh +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: CpuRcPolicyDxe.c +// +// Description: DxeCpuPolicyInitList eLink interface & its default child procedure +// for setting up DXE_CPU_PLATFORM_POLICY_PROTOCOL. +// +//<AMI_FHDR_END> +//********************************************************************** + +#include "token.h" + +#include "EdkIIGlueDxe.h" +//#include EFI_PROTOCOL_DEFINITION (CpuInfo) +#include "CpuPolicyInitDxe.h" + +#define VFRCOMPILE +#include "Include\Setup.h" +#undef VFRCOMPILE + +#if PERF_TUNE_SUPPORT == 1 +#define AMI_PERF_TUNE_DATA_HOB_GUID \ + {0x4d6c0496, 0x8de4, 0x4af2, 0x9a, 0x2e, 0x9b, 0xe5, 0xb9, 0x15, 0x6a, 0xc5} +#include <PerfTuneSetup.h> +typedef struct _PERF_TUNE_DATA_HOB2{ + EFI_HOB_GUID_TYPE EfiHobGuidType; + OC_SETUP_DATA PerfTuneDataHob; + BOOLEAN IsRunDefault; + BOOLEAN IsCpuChanged; + BOOLEAN IsWdtTimeOut; +}PERF_TUNE_DATA_HOB2; +#endif + +#define AMI_INTERNAL_UCODE_HOB_GUID \ + {0x94567c6f, 0xf7a9, 0x4229, 0x13, 0x30, 0xfe, 0x11, 0xcc, 0xab, 0x3a, 0x11} + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + UINT32 uCodeAddr; +} AMI_INTERNAL_UCODE_HOB; + +// Type Definition(s) +typedef VOID (CPU_POLICY_INIT_FUNC) ( + IN EFI_SYSTEM_TABLE *SystemTable, + IN SETUP_DATA *SetupData, + IN OUT DXE_CPU_PLATFORM_POLICY_PROTOCOL *mCpuPolicyDataPtr); + +VOID DxeCpuPolicyInit ( + IN EFI_SYSTEM_TABLE *SystemTable, + IN SETUP_DATA *SetupData, + IN OUT DXE_CPU_PLATFORM_POLICY_PROTOCOL *mCpuPolicyDataPtr); + +VOID CallDxeCpuPolicyInitList( + IN EFI_SYSTEM_TABLE *SystemTable, + IN OUT DXE_CPU_PLATFORM_POLICY_PROTOCOL *mCpuPolicyDataPtr); + +// External Declaration(s) +extern CPU_POLICY_INIT_FUNC DXE_CPU_POLICY_INIT_LIST EndOfList; + +CPU_POLICY_INIT_FUNC* DxeCpuPolicyInitListTable[] = \ + {DXE_CPU_POLICY_INIT_LIST NULL}; + +EFI_GUID gAmiInternaluCodeHobGuid = AMI_INTERNAL_UCODE_HOB_GUID; +UINT32 gMicrocodeStart = 0; + +//Cstate +#define C3_SUB_STATES_MASK 0x00000f00 +#define C6_SUB_STATES_MASK 0x0000f000 +#define C7_SUB_STATES_MASK 0x000f0000 +#define C8_SUB_STATES_MASK 0x00f00000 +#define C9_SUB_STATES_MASK 0x0f000000 +#define C10_SUB_STATES_MASK 0xf0000000 + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CallDxeCpuPolicyInitList +// +// Description: Get the microcode patch. +// +// +// Input: +// IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This +// IN UINT8 **MicrocodeData +// +// Output: +// EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +AmiPlatformCpuRetrieveMicrocode ( + IN DXE_CPU_PLATFORM_POLICY_PROTOCOL *This, + OUT UINT8 **MicrocodeData + ) +/*++ + +Routine Description: + + Get the microcode patch. + +Arguments: + + This - Driver context. + MicrocodeData - Retrieved image of the microcode. + +Returns: + + EFI_SUCCESS - Image found. + +--*/ + +// +// GC_TODO: EFI_NOT_FOUND - add return value to function comment +// GC_TODO: EFI_NOT_FOUND - add return value to function comment +// +{ + + if (*MicrocodeData == NULL && gMicrocodeStart != 0) { + *MicrocodeData = (UINT8 *) (UINTN) gMicrocodeStart; + } else{ + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CallDxeCpuPolicyInitList +// +// Description: This function orderly calls functions in DxeCpuPolicyOemInitList +// for OEM or Custom to override PEI_CPU_PLATFORM_POLICY_PPI. +// +// +// Input: +// IN EFI_SYSTEM_TABLE *SystemTable +// IN OUT DXE_CPU_PLATFORM_POLICY_PROTOCOL *mCpuPolicyDataPtr +// +// Output: +// None + +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CallDxeCpuPolicyInitList ( + IN EFI_SYSTEM_TABLE *SystemTable, + IN OUT DXE_CPU_PLATFORM_POLICY_PROTOCOL *mCpuPolicyDataPtr) +{ + + EFI_STATUS Status; + + EFI_GUID guidSetup = SETUP_GUID; + SETUP_DATA SetupData; + SETUP_DATA *SetupDataPtr = NULL; + UINTN Size = sizeof(SETUP_DATA); + UINTN i; + + Status = gRT->GetVariable(L"Setup",&guidSetup, NULL, &Size, &SetupData); + +//SetupData variable is always exist in Aptio BIOS even it's the 1st time boot. +// ASSERT_EFI_ERROR (Status); + if(!EFI_ERROR(Status)) SetupDataPtr = &SetupData; + +// Call DxeCpuPolicyInitListTable(eLink:DxeCpuPolicyInitList) + for (i = 0; DxeCpuPolicyInitListTable[i] != NULL; i++) + DxeCpuPolicyInitListTable[i](SystemTable, SetupDataPtr, mCpuPolicyDataPtr); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CallDxeCpuPolicyInitList +// +// Description: This function overrides DXE_CPU_PLATFORM_POLICY_PROTOCOL. +// +// +// Input: +// IN EFI_SYSTEM_TABLE *SystemTable +// IN SETUP_DATA *SetupData +// IN OUT DXE_CPU_PLATFORM_POLICY_PROTOCOL *mCpuPolicyDataPtr +// +// Output: +// None + +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID DxeCpuPolicyInit ( + IN EFI_SYSTEM_TABLE *SystemTable, + IN SETUP_DATA *SetupData, + IN OUT DXE_CPU_PLATFORM_POLICY_PROTOCOL *mCpuPolicyData) +{ + + EFI_STATUS Status; + CPU_CONFIG *CpuConfig = mCpuPolicyData->CpuConfig; + POWER_MGMT_CONFIG *CpuPmConfig = mCpuPolicyData->PowerMgmtConfig; + + UINT32 RegEax, RegEbx, RegEcx, RegEdx; + UINT8 CStateSupport = 0; + VOID *HobList; + AMI_INTERNAL_UCODE_HOB *uCodeHob = NULL; + +#if BRAND_STRING_WORKAROUND == 1 + PPM_CUSTOM_CTDP_TABLE *CustomConfigTdpTable; + UINT16 CustomPowerLimit1; + UINT8 mPowerUnitPowerOfTwo; + UINT8 mPowerUnit; + UINT16 mCustomPowerUnit; + UINT16 mPackageTdp; + UINTN PackageTdp; + UINTN NoOfOverrides = 0; + UINTN Index; + UINT64 PakagePowerLimitMsr = 0; + UINTN mHswUltPpmCtdpOverideTable[] = { + /// TDP Icc MSR PL1 MSR PL2 TdpUp TdpUp TdpNominal TdpNominal TdpDown TdpDown + /// Max PL1 PL2 PL1 PL2 PL1 PL2 + 5700, 0, 6700, 8375, 0, 8375, 0, 8375, 0, 8375 , /// 57W Sku Overrides + 1500, 0, 2500, 2500, 0, 2500, 0, 2500, 0, 2500 , /// 15W Sku Overrides + 1150, 0, 0, 2500, 0, 2500, 0, 2500, 0, 2500 , /// 11.5W Sku Overrides + 2800, 40, 0, 3500, 0, 3500, 0, 3500, 0, 3500 /// 28W 40A Sku Overrides + }; +#endif + +#if PERF_TUNE_SUPPORT == 1 + EFI_GUID gAmiPerfTuneDataHobGuid = AMI_PERF_TUNE_DATA_HOB_GUID; + PERF_TUNE_DATA_HOB2 *XtuPerfTuneDataHob; + OC_SETUP_DATA *SettingData; +#endif + +#if defined(I3_CPU_NON_TURBO) && (I3_CPU_NON_TURBO == 1) + + BOOLEAN IsI3Cpu = FALSE; +{ + CHAR8 BrandStrBuff[49]; + CHAR8 *BrandString = BrandStrBuff; + + AsmCpuid(0x80000002, &RegEax, &RegEbx, &RegEcx, &RegEdx); + *(UINT32*)BrandString = RegEax; BrandString +=4; + *(UINT32*)BrandString = RegEbx; BrandString +=4; + *(UINT32*)BrandString = RegEcx; BrandString +=4; + *(UINT32*)BrandString = RegEdx; BrandString +=4; + + AsmCpuid(0x80000003, &RegEax, &RegEbx, &RegEcx, &RegEdx); + *(UINT32*)BrandString = RegEax; BrandString +=4; + *(UINT32*)BrandString = RegEbx; BrandString +=4; + *(UINT32*)BrandString = RegEcx; BrandString +=4; + *(UINT32*)BrandString = RegEdx; BrandString +=4; + + AsmCpuid(0x80000004, &RegEax, &RegEbx, &RegEcx, &RegEdx); + *(UINT32*)BrandString = RegEax; BrandString +=4; + *(UINT32*)BrandString = RegEbx; BrandString +=4; + *(UINT32*)BrandString = RegEcx; BrandString +=4; + *(UINT32*)BrandString = RegEdx; BrandString +=4; + *BrandString = '\0';\ + + BrandString = BrandStrBuff; + + while(*BrandString) { + if ( *((CHAR16*)BrandString) == '3i') { + IsI3Cpu = TRUE; + break; + } + ++BrandString; + } + + +} +#endif + + // + // Get the start of the HOBs. + // + Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, &HobList); + // + // Get the Compatible BIOS structure BDAT from the HOB. + // + if (!EFI_ERROR(Status)){ + uCodeHob = GetNextGuidHob (&gAmiInternaluCodeHobGuid, HobList); + if (uCodeHob != NULL) { + gMicrocodeStart = uCodeHob->uCodeAddr; + DEBUG ((EFI_D_ERROR, "CPU ID in uCode = %x\n", ((EFI_CPU_MICROCODE_HEADER *)gMicrocodeStart)->ProcessorId)); + // uCode in memory is already found, change the RetriveveMicrocode funciton + mCpuPolicyData->CpuConfig->RetrieveMicrocode = AmiPlatformCpuRetrieveMicrocode; + } + } + + CpuConfig->RetrieveMicrocode = AmiPlatformCpuRetrieveMicrocode; + + CpuPmConfig->CustomPowerUnit = RC_POLICY_POWER_UNIT; + if(SetupData != NULL){ + // + //CPU config overwrite + // + CpuConfig->LimitCpuidMaximumValue = SetupData->LimitCpuid; + CpuConfig->HtState = SetupData->HTD; + CpuConfig->ExecuteDisableBit = SetupData->XDBit; + CpuConfig->VmxEnable = SetupData->VT; + + if (SetupData->TxtSupport) { + CpuConfig->VmxEnable = CPU_FEATURE_ENABLE; //Enable VMX when TXT enable + CpuConfig->SmxEnable = CPU_FEATURE_ENABLE; + } else { + CpuConfig->SmxEnable = CPU_FEATURE_DISABLE; + } + //CpuConfig->SmxEnable = CPU_FEATURE_ENABLE; + + CpuConfig->MlcStreamerPrefetcher = SetupData->MlcStreamerPrefetcher; + CpuConfig->MlcSpatialPrefetcher = SetupData->MlcSpatialPrefetcher; + CpuConfig->AesEnable = SetupData->AesEnable; + //CpuConfig->MachineCheckEnable = CPU_FEATURE_ENABLE; + CpuConfig->EnableDts = SetupData->DtsEnable; + CpuConfig->DebugInterfaceEnable = SetupData->DebugInterfaceEnable; + CpuConfig->DebugInterfaceLockEnable = SetupData->DebugInterfaceLock; + + // + //Power management config overwrite + // + CpuPmConfig->pFunctionEnables->Eist = SetupData->EIST; + CpuPmConfig->pFunctionEnables->TurboMode = SetupData->TurboMode; +#if defined(I3_CPU_NON_TURBO) && (I3_CPU_NON_TURBO == 1) + if (IsI3Cpu) + CpuPmConfig->pFunctionEnables->TurboMode = PPM_DISABLE; +#endif + //CpuPmConfig->pFunctionEnables->Cx = PPM_ENABLE; + if (SetupData->CxEnable){ + CpuPmConfig->pFunctionEnables->C1e = SetupData->C1E; + CpuPmConfig->pFunctionEnables->C3 = SetupData->C3Enable; + CpuPmConfig->pFunctionEnables->C6 = SetupData->C6Enable; + CpuPmConfig->pFunctionEnables->DeepCState = SetupData->C7Enable; + CpuPmConfig->pFunctionEnables->C1AutoDemotion = SetupData->C1AutoDemotion; + CpuPmConfig->pFunctionEnables->C3AutoDemotion = SetupData->C3AutoDemotion; + CpuPmConfig->pFunctionEnables->PkgCStateDemotion = SetupData->PkgCStateDemotion; + CpuPmConfig->pFunctionEnables->C1UnDemotion = SetupData->C1UnDemotion; + CpuPmConfig->pFunctionEnables->C3UnDemotion = SetupData->C3UnDemotion; + CpuPmConfig->pFunctionEnables->PkgCStateUnDemotion = SetupData->PkgCStateUnDemotion; + CpuPmConfig->pFunctionEnables->CStatePreWake = SetupData->CxPreWake; + CpuPmConfig->pFunctionEnables->LongLatencyC6 = SetupData->C6Latency; + CpuPmConfig->pFunctionEnables->LongLatencyC7 = SetupData->C7Latency; + CpuPmConfig->pFunctionEnables->LakeTiny = SetupData->LakeTiny; +#if ULT_SUPPORT + CpuPmConfig->pFunctionEnables->C8 = SetupData->C8Enable; + CpuPmConfig->pFunctionEnables->C9 = SetupData->C9Enable; + CpuPmConfig->pFunctionEnables->C10 = SetupData->C10Enable; +#endif + } else { + CpuPmConfig->pFunctionEnables->Cx = PPM_DISABLE; + CpuPmConfig->pFunctionEnables->C3 = PPM_DISABLE; + CpuPmConfig->pFunctionEnables->C6 = PPM_DISABLE; + CpuPmConfig->pFunctionEnables->DeepCState = PPM_DISABLE; +#if ULT_SUPPORT + CpuPmConfig->pFunctionEnables->C8 = PPM_DISABLE; + CpuPmConfig->pFunctionEnables->C9 = PPM_DISABLE; + CpuPmConfig->pFunctionEnables->C10 = PPM_DISABLE; +#endif + } + CpuPmConfig->ThermalFuncEnables->TStates = SetupData->CpuTstate; + //CpuPmConfig->pFunctionEnables->CStatePreWake = PPM_ENABLE; + //CpuPmConfig->pFunctionEnables->EnergyEfficientPState = PPM_ENABLE; + //CpuPmConfig->pFunctionEnables->CStatePreWake = PPM_ENABLE; +#if SB_SETUP_SUPPORT + CpuPmConfig->ThermalFuncEnables->AutoThermalReporting = SetupData->AutoThermalReport; +#endif + //CpuPmConfig->pFunctionEnables->LongLatencyC6 = PPM_DISABLE; + //CpuPmConfig->pFunctionEnables->LongLatencyC7 = PPM_ENABLE; + //CpuPmConfig->pFunctionEnables->ThermalMonitor = PPM_ENABLE; + //CpuPmConfig->pFunctionEnables->LakeTiny = PPM_DISABLE; + + if (SetupData->PowerLimit1) + CpuPmConfig->pTurboSettings->PowerLimit1 = SetupData->PowerLimit1; + if (SetupData->PowerLimit2) + CpuPmConfig->pTurboSettings->PowerLimit2 = SetupData->PowerLimit2; + if (SetupData->PowerLimit1Time) + CpuPmConfig->pTurboSettings->PowerLimit1Time = SetupData->PowerLimit1Time; + + CpuPmConfig->pTurboSettings->PowerLimit3Lock = SetupData->PowerLimit3Lock; + if (SetupData->PowerLimit3) + CpuPmConfig->pTurboSettings->PowerLimit3 = SetupData->PowerLimit3; + if (SetupData->PowerLimit3Time) + CpuPmConfig->pTurboSettings->PowerLimit3Time = SetupData->PowerLimit3Time; + if (SetupData->PowerLimit3DutyCycle) + CpuPmConfig->pTurboSettings->PowerLimit3DutyCycle = SetupData->PowerLimit3DutyCycle; + + if (SetupData->DdrPowerLimit1) + CpuPmConfig->pTurboSettings->DdrPowerLimit1 = SetupData->DdrPowerLimit1; + if (SetupData->DdrPowerLimit2) + CpuPmConfig->pTurboSettings->DdrPowerLimit2 = SetupData->DdrPowerLimit2; + if (SetupData->DdrPowerLimit1Time) + CpuPmConfig->pTurboSettings->DdrPowerLimit1Time = SetupData->DdrPowerLimit1Time; + + CpuPmConfig->pTurboSettings->ConfigTdpBios = SetupData->CtdpBios; + CpuPmConfig->pTurboSettings->ConfigTdpLevel = SetupData->cTDPLevel; + CpuPmConfig->pTurboSettings->ConfigTdpLock = SetupData->cTDPLock; + CpuPmConfig->pTurboSettings->EnergyPolicy = SetupData->CpuEngPerfBias; + + CpuPmConfig->pTurboSettings->TurboPowerLimitLock = SetupData->TurboPowerLimitLock; + +#if BRAND_STRING_WORKAROUND == 1 + //Configure custom cTdp table + CpuPmConfig->pCustomCtdpSettings->ConfigTdpCustom = PPM_ENABLE; + CpuPmConfig->pCustomCtdpSettings->CustomTdpCount = 2; + CpuPmConfig->pCustomCtdpSettings->CustomBootModeIndex = 0; + + CustomConfigTdpTable = CpuPmConfig->pCustomCtdpSettings->CustomConfigTdpTable; + mPowerUnitPowerOfTwo = (UINT8)(AsmReadMsr64 (MSR_PACKAGE_POWER_SKU_UNIT) & 0xf); + mPowerUnit = (UINT8) 1 << mPowerUnitPowerOfTwo; +#if RC_POLICY_POWER_UNIT == 0 + mCustomPowerUnit = 1; +#else + mCustomPowerUnit = (UINT8) 1 << mPowerUnitPowerOfTwo; +#endif + mPackageTdp = (UINT16)(AsmReadMsr64(MSR_PACKAGE_POWER_SKU) & 0x7fff); + +#if RC_POLICY_POWER_UNIT == 0 + CustomConfigTdpTable[0].CustomPowerLimit1 = mPackageTdp / mPowerUnit; + CustomConfigTdpTable[0].CustomPowerLimit2 = mPackageTdp * 125 / 100 / mPowerUnit; +#else + CustomConfigTdpTable[0].CustomPowerLimit1 = mPackageTdp; + CustomConfigTdpTable[0].CustomPowerLimit2 = mPackageTdp * 125 / 100; +#endif + CustomConfigTdpTable[0].CustomPowerLimit1Time = 0x1c; //MB_POWER_LIMIT1_TIME_DEFAULT + CustomConfigTdpTable[0].CustomTurboActivationRatio = (UINT8)(AsmReadMsr64 (MSR_CONFIG_TDP_NOMINAL) & 0xff) - 1; + CustomConfigTdpTable[0].CustomConfigTdpControl = 1; + + CustomPowerLimit1 = (UINT16)(AsmReadMsr64(MSR_CONFIG_TDP_LVL1) & 0x7fff); +#if RC_POLICY_POWER_UNIT == 0 + CustomConfigTdpTable[1].CustomPowerLimit1 = CustomPowerLimit1 / mPowerUnit; + CustomConfigTdpTable[1].CustomPowerLimit2 = CustomPowerLimit1 * 125 / 100 / mPowerUnit; +#else + CustomConfigTdpTable[1].CustomPowerLimit1 = CustomPowerLimit1; + CustomConfigTdpTable[1].CustomPowerLimit2 = CustomPowerLimit1 * 125 / 100; +#endif + CustomConfigTdpTable[1].CustomPowerLimit1Time = CustomConfigTdpTable[0].CustomPowerLimit1Time; + CustomConfigTdpTable[1].CustomTurboActivationRatio = (UINT8)((AsmReadMsr64(MSR_CONFIG_TDP_LVL1) >> 16) & 0xff) - 1; + CustomConfigTdpTable[1].CustomConfigTdpControl = 0; + + AsmCpuid(0x1, &RegEax, &RegEbx, &RegEcx, &RegEdx); + RegEax = RegEax & CPUID_FULL_FAMILY_MODEL; + if(RegEax == EnumCpuHswUlt) NoOfOverrides = 1; + PackageTdp = ((mPackageTdp / mPowerUnit) * 100); + if((mPackageTdp % mPowerUnit) !=0) + PackageTdp += ((mPackageTdp % mPowerUnit)* 100) / mPowerUnit; + + Index = 0; + while(NoOfOverrides != 0 && Index < sizeof(mHswUltPpmCtdpOverideTable)) { + if(mHswUltPpmCtdpOverideTable[0 + Index] == PackageTdp) { + PakagePowerLimitMsr = AsmReadMsr64(MSR_PACKAGE_POWER_LIMIT); + + if(mHswUltPpmCtdpOverideTable[2 + Index]) { + PakagePowerLimitMsr &= ~POWER_LIMIT_MASK; + PakagePowerLimitMsr |= ((mHswUltPpmCtdpOverideTable[2 + Index] * mPowerUnit)/100) & POWER_LIMIT_MASK; + } + + if(mHswUltPpmCtdpOverideTable[3 + Index]) { + PakagePowerLimitMsr &= ~(0x7FFF00000000); //MSR_PACKAGE_POWER_LIMIT[46:32] + PakagePowerLimitMsr |=((mHswUltPpmCtdpOverideTable[3 + Index] * mPowerUnit)/100) & 0x7FFF00000000; + } + AsmWriteMsr64 (MSR_PACKAGE_POWER_LIMIT, PakagePowerLimitMsr); + + if(mHswUltPpmCtdpOverideTable[6 + Index]) //CtdpNominalPowerLimit1 + CustomConfigTdpTable[0].CustomPowerLimit1 = \ + ((UINT16)(mHswUltPpmCtdpOverideTable[6 + Index]) / 100) * mCustomPowerUnit; + + if(mHswUltPpmCtdpOverideTable[7 + Index]) //CtdpNominalPowerLimit2 + CustomConfigTdpTable[0].CustomPowerLimit2 = \ + ((UINT16)(mHswUltPpmCtdpOverideTable[7 + Index]) / 100) * mCustomPowerUnit; + + if(mHswUltPpmCtdpOverideTable[8 + Index]) //CtdpDownPowerLimit1 + CustomConfigTdpTable[1].CustomPowerLimit1 = \ + ((UINT16)(mHswUltPpmCtdpOverideTable[8 + Index]) / 100) * mCustomPowerUnit; + + if(mHswUltPpmCtdpOverideTable[9 + Index]) //CtdpDownPowerLimit2 + CustomConfigTdpTable[1].CustomPowerLimit2 = \ + ((UINT16)(mHswUltPpmCtdpOverideTable[9 + Index]) / 100) * mCustomPowerUnit; + + break; + } + Index += 10; + } +#endif + + //if (RShiftU64(AsmReadMsr64(0xce), 33) & 0x03) + // CpuPmConfig->pTurboSettings->TurboPowerLimitLock = PPM_DISABLE; + //else + // CpuPmConfig->pTurboSettings->TurboPowerLimitLock = PPM_ENABLE; + //CpuPmConfig->pTurboSettings->DdrPowerLimitLock = PPM_DISABLE; + //CpuPmConfig->pTurboSettings->EnergyPolicy = 0; + // + CpuPmConfig->pPpmLockEnables->PmgCstCfgCtrlLock = SetupData->PmgCstCfgCtrlLock; + CpuPmConfig->pPpmLockEnables->OverclockingLock = SetupData->OverclockingLock; + //CpuPmConfig->pPpmLockEnables->ProcHotLock = PPM_DISABLE; + CpuPmConfig->S3RestoreMsrSwSmiNumber = SW_SMI_S3_RESTORE_MSR_FROM_SDL; + + AsmCpuid(5, &RegEax, &RegEbx, &RegEcx, &RegEdx); + if (!!(RegEdx & C10_SUB_STATES_MASK)) CStateSupport = 8; //C10 support + if (!!(RegEdx & C9_SUB_STATES_MASK) && (!CStateSupport)) CStateSupport = 7; //C9 support + if (!!(RegEdx & C8_SUB_STATES_MASK) && (!CStateSupport)) CStateSupport = 6; //C8 support + if (!!(RegEdx & C7_SUB_STATES_MASK) && (!CStateSupport)) CStateSupport = 5; //C7 support + if (!!(RegEdx & C6_SUB_STATES_MASK) && (!CStateSupport)) CStateSupport = 3; //C6 support + if (!!(RegEdx & C3_SUB_STATES_MASK) && (!CStateSupport)) CStateSupport = 2; //C3 support + + if (SetupData->PackageCState != 0xFF && SetupData->PackageCState > CStateSupport) + CpuPmConfig->PkgCStateLimit = CStateSupport; + else + CpuPmConfig->PkgCStateLimit = SetupData->PackageCState; + + //CpuPmConfig->PkgCStateLimit = PkgAuto; + // +#if CPU_SETUP_SET_LATENCY_CONTROL + CpuPmConfig->CstateLatencyControl0TimeUnit = SetupData->CstateLatencyControl0TimeUnit; + CpuPmConfig->CstateLatencyControl1TimeUnit = SetupData->CstateLatencyControl1TimeUnit; + CpuPmConfig->CstateLatencyControl2TimeUnit = SetupData->CstateLatencyControl2TimeUnit; + CpuPmConfig->CstateLatencyControl0Irtl = SetupData->CstateLatencyControl0Irtl; + CpuPmConfig->CstateLatencyControl1Irtl = SetupData->CstateLatencyControl1Irtl; + CpuPmConfig->CstateLatencyControl2Irtl = SetupData->CstateLatencyControl2Irtl; +#endif + //CpuPmConfig->RfiFreqTunningOffsetIsNegative = 0; + //CpuPmConfig->RfiFreqTunningOffset = 0; + +#if PERF_TUNE_SUPPORT == 1 + Status = EfiGetSystemConfigurationTable (&gEfiHobListGuid, &HobList); + if (!EFI_ERROR(Status)){ + XtuPerfTuneDataHob = GetNextGuidHob (&gAmiPerfTuneDataHobGuid, HobList); + if (XtuPerfTuneDataHob != NULL) { + SettingData = &XtuPerfTuneDataHob->PerfTuneDataHob; + } + } + SettingData = &XtuPerfTuneDataHob->PerfTuneDataHob; + + if (!(EFI_ERROR(Status) /*|| XtuPerfTuneDataHob->IsWdtTimeOut*/ || (XtuPerfTuneDataHob->IsCpuChanged && XtuPerfTuneDataHob->IsRunDefault))) + { + if (SettingData->EIST) + { + CpuPmConfig->pFunctionEnables->Eist = PPM_ENABLE; + + if (SettingData->TurboMode){ + CpuPmConfig->pFunctionEnables->TurboMode = PPM_ENABLE; + } + else + CpuPmConfig->pFunctionEnables->TurboMode = PPM_DISABLE; + + } + else{ + CpuPmConfig->pFunctionEnables->Eist = PPM_DISABLE; + CpuPmConfig->pFunctionEnables->TurboMode = PPM_DISABLE; + } + + if(!(SettingData->OverclockingEnable)) + CpuPmConfig->pPpmLockEnables->OverclockingLock = PPM_ENABLE; // 1, disable overclocking lock; 0, enable overclocking lock + + // Skus that support Config TDP are not able to change power limit(MSR 0x610) in real time, + // and don't lock cTDP CTC(MSR 0x64B) and cTDP TAR(MSR 0x64C). + if ((AsmReadMsr64(MSR_PLATFORM_INFO) & (BIT33 | BIT34))){ + CpuPmConfig->pTurboSettings->PowerLimit2 = AUTO; + CpuPmConfig->pTurboSettings->PowerLimit1 = AUTO; + CpuPmConfig->pTurboSettings->PowerLimit1Time = AUTO; + CpuPmConfig->pTurboSettings->TurboPowerLimitLock = PPM_DISABLE; + CpuPmConfig->pFunctionEnables->PowerLimit2 = PPM_ENABLE; + CpuPmConfig->pTurboSettings->ConfigTdpLock = PPM_DISABLE; + + }else{ + CpuPmConfig->pTurboSettings->PowerLimit2 = SettingData->ShortPowerLimit; + CpuPmConfig->pTurboSettings->PowerLimit1 = SettingData->ExtendedPowerLimit; + CpuPmConfig->pTurboSettings->PowerLimit1Time = SettingData->ExtendedTimeWindow; + CpuPmConfig->pTurboSettings->TurboPowerLimitLock = (UINT8)SettingData->PowerLockSwitch; + CpuPmConfig->pFunctionEnables->PowerLimit2 = (UINT8)SettingData->ShortPowerLockSwitch; + } + CpuPmConfig->CustomPowerUnit = PowerUnitWatts; + } +#endif + } +} + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyPei.c b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyPei.c new file mode 100644 index 0000000..9c596b9 --- /dev/null +++ b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyPei.c @@ -0,0 +1,400 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuRcPolicyWrap/CpuRcPolicyPei.c 16 6/11/15 10:30p Crystallee $ +// +// $Revision: 16 $ +// +// $Date: 6/11/15 10:30p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuRcPolicyWrap/CpuRcPolicyPei.c $ +// +// 16 6/11/15 10:30p Crystallee +// [TAG] EIP207854 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Txt test fail with TCG2 module +// [RootCause] Tokne TCG_SUPPORT was removed. +// [Solution] Add TCG2Support token. +// +// 15 4/10/15 3:15a Crystallee +// +// 14 1/22/15 3:59a Crystallee +// [TAG] EIPNone +// [Category] Bug Fix +// [Severity] Minor +// [Symptom] PowerConv and TimeConv parameters in +// AmiInternalFactoryTdcTdp Hob is incorrect. +// [RootCause] Read from wrong MSR. +// [Solution] The data should read from MSR 0x606. +// +// 13 8/28/13 5:54a Crystallee +// [TAG] EIP134339 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] [Sharkbay]Build error after update Haswell Cpu module +// [RootCause] If token TCG_SUPPORT is disabled, TpmSupport setup data +// will not define, then cause built error. +// [Solution] Add token TCG_SUPPORT condition when use TpmSupport setup +// data. +// +// 12 7/23/13 7:44a Crystallee +// [TAG] EIP128089 +// [Category] Improvement +// [Description] TXT will be disabled and grayed out in Setup when TPM +// Support is disabled. +// +// 11 2/22/13 1:54a Crystallee +// [TAG] EIP112238 +// [Category] Improvement +// [Description] Refer Intel BIOS and provide setup items for Intel +// Haswell RC policy. +// +// 10 1/23/13 2:58a Crystallee +// [TAG] None +// [Category] Improvement +// [Description] Create setup item for BootInLfm +// +// 9 12/12/12 1:23a Davidhsieh +// [TAG] EIP108401 +// [Category] Improvement +// [Description] Create setup item for VrMiscIoutOffsetSign +// +// 8 12/03/12 9:50p Davidhsieh +// [TAG] EIP108401 +// [Category] Improvement +// [Description] Create setup items for VrMiscIoutOffset, +// VrMiscIoutSlope and LakeTiny +// +// 7 11/23/12 2:05a Hsingyingchung +// [TAG] EIP99095 +// [Category] Improvement +// [Description] Update by XTU 4.X +// +// 6 7/19/12 2:22a Davidhsieh +// [TAG] EIP95485 +// [Category] Improvement +// [Description] Enable VT when TXT is enabled +// +// 5 7/02/12 8:23a Davidhsieh +// +// 4 6/19/12 8:25a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Only enable TXT while TCG also enable +// +// 3 6/15/12 3:34a Davidhsieh +// [TAG] EIP89941 +// [Category] Improvement +// [Description] Add Intel TXT setup item +// +// 2 3/16/12 3:45a Davidhsieh +// Setup items create for CPU RC policy +// +// 1 2/07/12 3:57a Davidhsieh +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: CpuPolicyInitPei.c +// +// Description: PeiCpuPolicyInitList eLink interface & its default child procedure +// for setting up PEI_CPU_PLATFORM_POLICY_PPI. +// +//<AMI_FHDR_END> +//********************************************************************** +#include "EdkIIGluePeim.h" +#include "CpuPlatformPolicy.h" + +#define VFRCOMPILE +#include "Include\Setup.h" +#undef VFRCOMPILE + +#include "token.h" + +#define MSR_FLEX_RATIO 0x194 +#define MSR_TURBO_RATIO_LIMIT 0x1AD +#define MSR_VR_CURRENT_CONFIG 0x601 +#define MSR_PACKAGE_POWER_SKU_UNIT 0x606 +#define MSR_PACKAGE_POWER_LIMIT 0x610 + +#pragma pack(push,1) +#define AMI_INTERNAL_FACTORY_TDC_TDP_HOB_GUID \ + {0x982d8c6f, 0xf6f6, 0x4135, 0xa3, 0x9, 0xa4, 0x59, 0x3e, 0xa5, 0x64, 0x17} + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + UINT8 Revision; + BOOLEAN IsSandyBridge; + BOOLEAN IsHasWell; + UINT64 Reserved0; + UINT8 PowerConv; + UINT8 CurConv; + UINT8 TimeConv; + UINT16 Tdc; + UINT16 Tdp; + UINT8 TdpLimitTime; + UINT8 Vid; +//Used for PERF_TUNE_SUPPORT Start + UINT8 OneCoreRatioLimit; + UINT8 TwoCoreRatioLimit; + UINT8 ThreeCoreRatioLimit; + UINT8 FourCoreRatioLimit; + UINT8 FiveCoreRatioLimit; + UINT8 SixCoreRatioLimit; + UINT16 IaCoreCurrentMax; + UINT16 IGfxCoreCurrentMax; + UINT8 OneCoreRatioMax; + UINT8 TwoCoreRatioMax; + UINT8 ThreeCoreRatioMax; + UINT8 FourCoreRatioMax; + UINT8 FiveCoreRatioMax; + UINT8 SixCoreRatioMax; +//Used for PERF_TUNE_SUPPORT End +} AMI_INTERNAL_FACTORY_TDC_TDP_HOB; +#pragma pack(pop) + +// Type Definition(s) +typedef VOID (CPU_POLICY_INIT_FUNC) ( + IN EFI_PEI_SERVICES **PeiServices, + IN SETUP_DATA *SetupData, + IN OUT PEI_CPU_PLATFORM_POLICY_PPI *PeiCpuPolicyPpi); + +//VOID PeiCpuPolicyInit ( +// IN EFI_PEI_SERVICES **PeiServices, +// IN SETUP_DATA *SetupData, +// IN OUT PEI_CPU_PLATFORM_POLICY_PPI *PeiCpuPolicyPpi ); + +VOID CallPeiCpuPolicyInitList( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT PEI_CPU_PLATFORM_POLICY_PPI *PeiCpuPolicyPpi); + +// External Declaration(s) +extern CPU_POLICY_INIT_FUNC PEI_CPU_POLICY_INIT_LIST EndOfList; + +CPU_POLICY_INIT_FUNC* PeiCpuPolicyInitListTable[] = \ + {PEI_CPU_POLICY_INIT_LIST NULL}; + +EFI_GUID gAmiInternalFactoryTdcTdpHobGuid = AMI_INTERNAL_FACTORY_TDC_TDP_HOB_GUID; +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CallPeiCpuPolicyInitList +// +// Description: This function orderly calls functions in PeiCpuPolicyInitListTable +// for OEM or Custom to override PEI_CPU_PLATFORM_POLICY_PPI. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CallPeiCpuPolicyInitList ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT PEI_CPU_PLATFORM_POLICY_PPI *PeiCpuPolicyPpi ) +{ + + EFI_PEI_READ_ONLY_VARIABLE_PPI *ReadOnlyVariable; + EFI_GUID gEfiSetupGuid = SETUP_GUID; + SETUP_DATA SetupData; + SETUP_DATA *SetupDataPtr = NULL; + UINTN VariableSize= sizeof (SETUP_DATA); + UINTN i; + EFI_STATUS Status; + + // + // Get AMI setup variable to setup PEI CPU Policy + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gPeiReadOnlyVariablePpiGuid, + 0, + NULL, + &ReadOnlyVariable + ); +// ASSERT_EFI_ERROR (Status); + + if (!EFI_ERROR(Status)) { + Status = ReadOnlyVariable->PeiGetVariable ( + PeiServices, + L"Setup", + &gEfiSetupGuid, + NULL, + &VariableSize, + &SetupData + ); + } +//SetupData variable is always exist in Aptio BIOS even it's the 1st time boot. +// ASSERT_EFI_ERROR (Status); + if(!EFI_ERROR(Status)) SetupDataPtr = &SetupData; + else return; +// Call PeiCpuPolicyInitListTable(eLink:PeiCpuPolicyInitList) + for (i = 0; PeiCpuPolicyInitListTable[i] != NULL; i++) + PeiCpuPolicyInitListTable[i](PeiServices, SetupDataPtr, PeiCpuPolicyPpi); + +} + +VOID PeiCpuPolicyInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN SETUP_DATA *SetupData, + IN OUT PEI_CPU_PLATFORM_POLICY_PPI *PeiCpuPolicyPpi ) +{ + + UINT32 RegEax, RegEbx, RegEcx, RegEdx; + UINT8 TotLogicalCpus = 0; + UINT8 LogicalCpusPerCore = 0; + UINT8 CpuSupportedCores = 0; + UINT64 TempMsr; + EFI_STATUS Status; + CPU_CONFIG_PPI *CpuConfig = PeiCpuPolicyPpi->CpuConfig; +// SECURITY_CONFIG_PPI *SecurityConfig = PeiCpuPolicyPpi->SecurityConfig; + POWER_MGMT_CONFIG_PPI *PowerMgmtConfig = PeiCpuPolicyPpi->PowerMgmtConfig; + TXT_CONFIG *TxtConfig = PeiCpuPolicyPpi->SecurityConfig->TxtConfig; + AMI_INTERNAL_FACTORY_TDC_TDP_HOB *TdcTdpHob; +#if TCG_SUPPORT || TCG2Support + UINT8 *TpmBaseAddr = (UINT8*)0xfed40000; +#endif + +// +// Create Cpu Tdc and Tdp HOB +// + Status = (*PeiServices)->CreateHob( + PeiServices, + EFI_HOB_TYPE_GUID_EXTENSION, + sizeof(AMI_INTERNAL_FACTORY_TDC_TDP_HOB), + &TdcTdpHob + ); + + if ( !EFI_ERROR(Status) ) { + TdcTdpHob->EfiHobGuidType.Name = gAmiInternalFactoryTdcTdpHobGuid; + TdcTdpHob->Revision = 1; + + TempMsr = AsmReadMsr64 (MSR_PACKAGE_POWER_LIMIT); + + TdcTdpHob->IsSandyBridge = FALSE; + TdcTdpHob->IsHasWell = TRUE; + TdcTdpHob->Tdc = (UINT16)(RShiftU64 (TempMsr, 32) & 0x7fff); + TdcTdpHob->Tdp = (UINT16)(TempMsr & 0x7fff); + TdcTdpHob->TdpLimitTime = (UINT8)(RShiftU64 (TempMsr, 17) & 0x7f); + + TempMsr = AsmReadMsr64 (MSR_PACKAGE_POWER_SKU_UNIT); + TdcTdpHob->PowerConv = 1 << ((UINT8)(TempMsr & 0xf)); + TdcTdpHob->TimeConv = RShiftU64(TempMsr, 16) & 0xf ; // 1 / (2 ^ TIME_UINT) + + TempMsr = AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT); + TdcTdpHob->OneCoreRatioLimit = (UINT8)TempMsr; + TdcTdpHob->TwoCoreRatioLimit = (UINT8)(RShiftU64 (TempMsr, 8)); + TdcTdpHob->ThreeCoreRatioLimit = (UINT8)(RShiftU64 (TempMsr, 16)); + TdcTdpHob->FourCoreRatioLimit = (UINT8)(RShiftU64 (TempMsr, 24)); + TdcTdpHob->FiveCoreRatioLimit = (UINT8)(RShiftU64 (TempMsr, 32)); + TdcTdpHob->SixCoreRatioLimit = (UINT8)(RShiftU64 (TempMsr, 40)); + + TdcTdpHob->Vid = (UINT8)(AsmReadMsr64(MSR_FLEX_RATIO)); + TdcTdpHob->IaCoreCurrentMax = (UINT16)(AsmReadMsr64(MSR_VR_CURRENT_CONFIG) & 0xfff); + } + // CPU policy configure by setup questions + if (SetupData != NULL) { +// +// CPU feature policyoverwrite +// +#if CPU_SETUP_SET_MAX_RATIO + CpuConfig->CpuRatioOverride = CPU_FEATURE_ENABLE; + CpuConfig->CpuRatio = SetupData->CpuMaxRatio;; +#endif + CpuConfig->HyperThreading = SetupData->HTD; + CpuConfig->VmxEnable = SetupData->VT; + CpuConfig->MlcStreamerPrefetcher = SetupData->MlcStreamerPrefetcher; + CpuConfig->MlcSpatialPrefetcher = SetupData->MlcSpatialPrefetcher; + + //Do not set ActiveCoreCount more than CPU supported Cores + AsmCpuidEx (0xb, 1, &RegEax, &RegEbx, &RegEcx, &RegEdx); + TotLogicalCpus = (UINT8)RegEbx; + + AsmCpuidEx (0xb, 0, &RegEax, &RegEbx, &RegEcx, &RegEdx); + LogicalCpusPerCore = (UINT8)RegEbx; + + CpuSupportedCores = TotLogicalCpus / LogicalCpusPerCore; + + if (SetupData->ActiveCoreCount != 0 && SetupData->ActiveCoreCount <= CpuSupportedCores) + CpuConfig->ActiveCoreCount = SetupData->ActiveCoreCount; + else + CpuConfig->ActiveCoreCount = 0; + +// +// Power Managment policy overwrite +// + + PowerMgmtConfig->VrCurrentLimitLock = SetupData->VrCurrentLimitLock; + + if(SetupData->CpuTccActOffset != 0) + PowerMgmtConfig->TccActivationOffset = SetupData->CpuTccActOffset; + + if(SetupData->Cpu1CoreRatioLimit != 0){ + PowerMgmtConfig->Xe = CPU_FEATURE_ENABLE; + PowerMgmtConfig->RatioLimit[0] = SetupData->Cpu1CoreRatioLimit; + } + + if(SetupData->Cpu2CoreRatioLimit != 0){ + PowerMgmtConfig->Xe = CPU_FEATURE_ENABLE; + PowerMgmtConfig->RatioLimit[1] = SetupData->Cpu2CoreRatioLimit; + } + + if(SetupData->Cpu3CoreRatioLimit != 0){ + PowerMgmtConfig->Xe = CPU_FEATURE_ENABLE; + PowerMgmtConfig->RatioLimit[2] = SetupData->Cpu3CoreRatioLimit; + } + + if(SetupData->Cpu4CoreRatioLimit != 0){ + PowerMgmtConfig->Xe = CPU_FEATURE_ENABLE; + PowerMgmtConfig->RatioLimit[3] = SetupData->Cpu4CoreRatioLimit; + } + + if (SetupData->VrCurrentLimit != 0) + PowerMgmtConfig->VrCurrentLimit = SetupData->VrCurrentLimit; + + PowerMgmtConfig->VrMiscIoutOffset = SetupData->IoutOffset; + PowerMgmtConfig->VrMiscIoutSlope = SetupData->IoutSlope; + PowerMgmtConfig->VrMiscIoutOffsetSign = SetupData->IoutOffsetSign; + + PowerMgmtConfig->BootInLfm = SetupData->BootInLfm; + +// +// TXT Policy overwrite +// +#if TCG_SUPPORT || TCG2Support + if (SetupData->TxtSupport && SetupData->TpmSupport && (*TpmBaseAddr != 0xff)) { + CpuConfig->Txt = CPU_FEATURE_ENABLE; + TxtConfig->TxtDprMemorySize = TXT_TOTAL_STOLEN_MEMORY_SIZE; + } +#else + CpuConfig->Txt = CPU_FEATURE_DISABLE; +#endif + if (SetupData->TxtSupport) + CpuConfig->VmxEnable = CPU_FEATURE_ENABLE; // VMX must enable when TXT enable + } +} +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.cif b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.cif new file mode 100644 index 0000000..0db72cc --- /dev/null +++ b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.cif @@ -0,0 +1,11 @@ +<component> + name = "CpuRcPolicyWrap" + category = ModulePart + LocalRoot = "Board\Cpu\CpuRcPolicyWrap" + RefName = "CpuRcPolicyWrap" +[files] +"CpuRcPolicyWrap.sdl" +"CpuRcPolicyWrap.mak" +"CpuRcPolicyPei.c" +"CpuRcPolicyDxe.c" +<endComponent> diff --git a/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.mak b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.mak new file mode 100644 index 0000000..7305ea9 --- /dev/null +++ b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.mak @@ -0,0 +1,76 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuRcPolicyWrap/CpuRcPolicyWrap.mak 1 2/07/12 3:57a Davidhsieh $ +# +# $Revision: 1 $ +# +# $Date: 2/07/12 3:57a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuRcPolicyWrap/CpuRcPolicyWrap.mak $ +# +# 1 2/07/12 3:57a Davidhsieh +# +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** + +#---------------------------------------------------------------------------- +# Link to CpuPolicyPeiBin (Pesudo target of CpuPolicyPei.ffs) +#---------------------------------------------------------------------------- +CpuPolicyPeiBin: $(BUILD_DIR)\CpuRcPolicyPei.obj + +MY_PEI_FLAGS =\ + $(CRC_PEI_POLICY_FLAGS)\ + /D\"PEI_CPU_POLICY_INIT_LIST=$(PeiCpuPolicyInitList)\" + +$(BUILD_DIR)\CpuRcPolicyPei.obj: $(CpuRcPolicyWrap_DIR)\CpuRcPolicyPei.c + $(CC) $(CFLAGS) $(MY_PEI_FLAGS) /I$(PROJECT_DIR)\include /I$(PROJECT_CPU_ROOT)\Include /Fo$(BUILD_DIR)\ $(CpuRcPolicyWrap_DIR)\CpuRcPolicyPei.c + +#---------------------------------------------------------------------------- +# Link to CpuPolicyPeiBin (Pesudo target of CpuPolicyPei.ffs) +#---------------------------------------------------------------------------- +CpuPolicyInitDxeBin: $(BUILD_DIR)\CpuRcPolicyDxe.obj + +MY_DXE_FLAGS =\ + $(CRC_DXE_POLICY_FLAGS)\ + /D\"DXE_CPU_POLICY_INIT_LIST=$(DxeCpuPolicyInitList)\" + +$(BUILD_DIR)\CpuRcPolicyDxe.obj: $(CpuRcPolicyWrap_DIR)\CpuRcPolicyDxe.c + $(CC) $(CFLAGS) $(MY_DXE_FLAGS) /I$(PROJECT_DIR)\include /I$(UefiEfiIfrSupportLib_DIR) /Fo$(BUILD_DIR)\ $(CpuRcPolicyWrap_DIR)\CpuRcPolicyDxe.c + +#--------------------------------------------------------------------------- +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.sdl b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.sdl new file mode 100644 index 0000000..eb6374f --- /dev/null +++ b/Board/CPU/CpuRcPolicyWrap/CpuRcPolicyWrap.sdl @@ -0,0 +1,154 @@ +#**************************************************************************** +#**************************************************************************** +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30071 ** +#** ** +#** Phone (770)-246-8600 ** +#** ** +#**************************************************************************** +#**************************************************************************** +#**************************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuRcPolicyWrap/CpuRcPolicyWrap.sdl 1 2/07/12 3:57a Davidhsieh $ +# +# $Revision: 1 $ +# +# $Date: 2/07/12 3:57a $ +# +#**************************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/CpuRcPolicyWrap/CpuRcPolicyWrap.sdl $ +# +# 1 2/07/12 3:57a Davidhsieh +# +# 2 9/26/11 3:49a Davidhsieh +# +# 1 5/06/11 6:07a Davidhsieh +# First release +# +# +#**************************************************************************** +PATH + Name = "CpuRcPolicyWrap_DIR" +End + +MODULE + Help = "Includes CpuPeiPolicy.mak to Project" + File = "CpuRcPolicyWrap.mak" +End + +ELINK + Name = "CRC_PEI_POLICY_FLAGS" + InvokeOrder = ReplaceParent + Help = "eLink for setting up extra flags to compile C files link to CpuPolicyPei PEIM" +End + +ELINK + Name = "/D TIANO_RELEASE_VERSION=$(TIANO_RELEASE_VERSION)" + Parent = "CRC_PEI_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(EDK_INCLUDES:x64=IA32)" + Parent = "CRC_PEI_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(EdkIIGlueLib_INCLUDES:x64=IA32)" + Parent = "CRC_PEI_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(PROJECT_DIR)" + Parent = "CRC_PEI_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(PROJECT_CPU_ROOT)\Ppi\CpuPlatformPolicy" + Parent = "CRC_PEI_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "PeiCpuPolicyInitList" + InvokeOrder = ReplaceParent + Help = "eLink for overriding CPU Reference Code PEI CPU Platform Policy." +End + +ELINK + Name = "PeiCpuPolicyInit," + Parent = "PeiCpuPolicyInitList" + InvokeOrder = AfterParent + Help = "CPU module default Cpu RC PEI CPU Platform Policy overriding eLink." +End + +ELINK + Name = "CRC_DXE_POLICY_FLAGS" + InvokeOrder = ReplaceParent + Help = "eLink for setting up extra flags to compile C files link to CpuPolicyPei PEIM" +End + +ELINK + Name = "/D TIANO_RELEASE_VERSION=$(TIANO_RELEASE_VERSION)" + Parent = "CRC_DXE_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(EDK_INCLUDES)" + Parent = "CRC_DXE_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(EdkIIGlueLib_INCLUDES)" + Parent = "CRC_DXE_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(PROJECT_CPU_ROOT)" + Parent = "CRC_DXE_POLICY_FLAGS" + InvokeOrder = AfterParent +End + + +ELINK + Name = "/I$(PROJECT_CPU_ROOT)\Include" + Parent = "CRC_DXE_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(CpuPolicyInitDxe_DIR)" + Parent = "CRC_DXE_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(PROJECT_DIR)" + Parent = "CRC_DXE_POLICY_FLAGS" + InvokeOrder = AfterParent +End + +ELINK + Name = "DxeCpuPolicyInitList" + InvokeOrder = ReplaceParent + Help = "eLink for overriding CPU Reference Code DXE CPU Platform Policy." +End + +ELINK + Name = "DxeCpuPolicyInit," + Parent = "DxeCpuPolicyInitList" + InvokeOrder = AfterParent + Help = "CPU module default Cpu RC DXE CPU Platform Policy overriding eLink." +End + diff --git a/Board/CPU/CpuS3Pei/AmiCpuS3Pei.c b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.c new file mode 100644 index 0000000..d8ae4d4 --- /dev/null +++ b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.c @@ -0,0 +1,192 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI CPU S3 Pei/AmiCpuS3Pei.c 2 9/28/12 5:40a Davidhsieh $ +// +// $Revision: 2 $ +// +// $Date: 9/28/12 5:40a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI CPU S3 Pei/AmiCpuS3Pei.c $ +// +// 2 9/28/12 5:40a Davidhsieh +// Wait APIC idle after sending SMM IPI +// +// 1 9/26/12 10:45a Davidhsieh +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: AmiCpuS3Pei.c +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +// +#include <PEI.h> +#include <AmiPeiLib.h> +#include <AmiCspLib.h> +#include <Ppi\Stall.h> +#include <Ppi\ReadOnlyVariable.h> +#include <Setup.h> +#include <token.h> +#include "Core/CPU/CPU.h" +#include "Core/CPU/CpuCspLib.h" + +EFI_GUID gSmmHobGuid = SMM_HOB_GUID; +EFI_GUID gPeiReadOnlyVariablePpiGuid = EFI_PEI_READ_ONLY_VARIABLE_PPI_GUID; +EFI_GUID gEfiPeiStallPpiGuid = EFI_PEI_STALL_PPI_GUID; +EFI_GUID gMpCpuApicIdDataGuid = MP_CPU_APIC_ID_DATA_GUID; + +#define SMM_ASM_FIXUP_SMM_BASE 0x38002 +#define SMM_ASM_FIXUP_IED_ZERO_MEM 0x38029 +#define SMM_ASM_BASE_CHANGE_FLAG 0x3808f +#define APIC_SMI (2 << 8) +#define APIC_DELIVERY_STATUS (1 << 12) +#define APIC_LEVEL_ASSERT (1 << 14) +#define APIC_NO_SHORT_HAND (0 << 18) + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AmiCpuS3PeiEntry +// +// Description: PEI Entry Point for Intel TXT Driver. +// +// Input: EFI_HANDLE - ImageHandle +// EFI_SYSTEM_TABLE* - SystemTable +// +// Output: None. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +AmiCpuS3PeiEntry ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices +) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + VOID *FirstHob; + SMM_HOB *SmmHob; + EFI_PEI_READ_ONLY_VARIABLE_PPI *ReadOnlyVariable; + EFI_PEI_STALL_PPI *PeiStall; + MP_CPU_APICID_DATA MpCpuApicIdData; + UINTN VariableSize = sizeof(MP_CPU_APICID_DATA); + BOOLEAN ApicIdFromVariable = FALSE; + VOID *SaveBuffer; + UINT8 ApicId; + UINT8 i, j=0; + + (*PeiServices)->GetBootMode(PeiServices, &BootMode); + + if (BootMode != BOOT_ON_S3_RESUME) + return EFI_SUCCESS; + + Status = (*PeiServices)->LocatePpi ( + PeiServices, &gPeiReadOnlyVariablePpiGuid, 0, NULL, &ReadOnlyVariable + ); + ASSERT_PEI_ERROR(PeiServices, Status); + + Status = (*PeiServices)->LocatePpi( + PeiServices, &gEfiPeiStallPpiGuid, 0, NULL, &PeiStall + ); + ASSERT_PEI_ERROR(PeiServices, Status); + + if(!EFI_ERROR(Status)){ + Status = ReadOnlyVariable->GetVariable ( + PeiServices, + L"CPUS3APICID", + &gMpCpuApicIdDataGuid, + NULL, + &VariableSize, + &MpCpuApicIdData + ); + if(Status == EFI_SUCCESS) + ApicIdFromVariable = TRUE; //If CPU S3 APIC ID data found, use local data as CPU APIC ID + } + + (*PeiServices)->GetHobList(PeiServices, &FirstHob); + SmmHob = (SMM_HOB*)FirstHob; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &SmmHob))) + { + if (guidcmp(&SmmHob->EfiHobGuidType.Name, &gSmmHobGuid) == 0) + break; + } + + if (!EFI_ERROR(Status)) + { + //Allocate memory for temporarly perserve the 3000:8000 data. + Status = (*PeiServices)->AllocatePool( + PeiServices, + SmmGetBaseSaveBufferSize(), + &SaveBuffer + ); + ASSERT_PEI_ERROR(PeiServices, Status); + + SmmSetupDefaultHandler(SaveBuffer, SmmHob); + + for (i = 0; i < SmmHob->NumCpus; ++i) + { + *(UINT32*)SMM_ASM_FIXUP_SMM_BASE = (UINT32)SmmHob->SmmBase[i]; + *(volatile UINT8*)SMM_ASM_BASE_CHANGE_FLAG = 0; //Initialize Flag + + if (ApicIdFromVariable) ApicId = MpCpuApicIdData.ApicId[i]; + else ApicId = j; + + MemReadWrite32((UINT32*)(LOCAL_APIC_BASE + APIC_ICR_HIGH_REGISTER), ApicId << 24, 0x00ffffff); + MemReadWrite32((UINT32*)(LOCAL_APIC_BASE + APIC_ICR_LOW_REGISTER), APIC_NO_SHORT_HAND + APIC_LEVEL_ASSERT + APIC_SMI, 0); + + while (!(*(volatile UINT8*)SMM_ASM_BASE_CHANGE_FLAG)) + { + CPULib_Pause(); //Wait on Flag + } + ++*(UINT16*)SMM_ASM_FIXUP_IED_ZERO_MEM; //Only 0, for first thread to clear IED memory. + PeiStall->Stall(PeiServices, PeiStall, 50); + //Wait until IPI is Idle + while( + MemRead32((UINT32*)(LOCAL_APIC_BASE + APIC_ICR_LOW_REGISTER)) & APIC_DELIVERY_STATUS + ); + + if (!ApicIdFromVariable){ + if (IsHtEnabled()) j++; + else j += 2; + } + } + + SmmRemoveDefaultHandler(SaveBuffer); + } + + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/CpuS3Pei/AmiCpuS3Pei.cif b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.cif new file mode 100644 index 0000000..ae15fb7 --- /dev/null +++ b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.cif @@ -0,0 +1,11 @@ +<component> + name = "AMI CPU S3 Pei" + category = ModulePart + LocalRoot = "Board\Cpu\CpuS3Pei" + RefName = "AmiCpuS3Pei" +[files] +"AmiCpuS3Pei.sdl" +"AmiCpuS3Pei.mak" +"AmiCpuS3Pei.c" +"AmiCpuS3Pei.dxs" +<endComponent> diff --git a/Board/CPU/CpuS3Pei/AmiCpuS3Pei.dxs b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.dxs new file mode 100644 index 0000000..1f0b684 --- /dev/null +++ b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.dxs @@ -0,0 +1,72 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI CPU S3 Pei/AmiCpuS3Pei.dxs 1 9/26/12 10:45a Davidhsieh $ +// +// $Revision: 1 $ +// +// $Date: 9/26/12 10:45a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI CPU S3 Pei/AmiCpuS3Pei.dxs $ +// +// 1 9/26/12 10:45a Davidhsieh +// +// 1 2/07/12 3:58a Davidhsieh +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// Name: CPUPEI.dxs +// +// Description: Dependency expression for CPU PEI component. +// Currently it is dependent on the CPU IO & PCI CFG PPI. +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <pei.h> +#include <ppi\CpuIo.h> +#include <ppi\PciCfg.h> +#include <Ppi\ReadOnlyVariable.h> +#define PEI_SMM_ACCESS_PPI_GUID \ + { \ + 0x268f33a9, 0xcccd, 0x48be, 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e, 0xd6 \ + } + +DEPENDENCY_START + EFI_PEI_PERMANENT_MEMORY_INSTALLED_PPI AND + EFI_PEI_MASTER_BOOT_MODE_PEIM_PPI AND + EFI_PEI_CPU_IO_PPI_INSTALLED_GUID AND + EFI_PEI_PCI_CFG_PPI_INSTALLED_GUID AND + PEI_SMM_ACCESS_PPI_GUID AND + EFI_PEI_READ_ONLY_VARIABLE_PPI_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/CpuS3Pei/AmiCpuS3Pei.mak b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.mak new file mode 100644 index 0000000..d628aa4 --- /dev/null +++ b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.mak @@ -0,0 +1,66 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI CPU S3 Pei/AmiCpuS3Pei.mak 1 9/26/12 10:45a Davidhsieh $ +# +# $Revision: 1 $ +# +# $Date: 9/26/12 10:45a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI CPU S3 Pei/AmiCpuS3Pei.mak $ +# +# 1 9/26/12 10:45a Davidhsieh +# +# +#********************************************************************** +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: AmiCpuS3Pei.mak +# +# Description: Makefile for AmiCpuS3Pei module. +# +#<AMI_FHDR_END> +#********************************************************************** + +all : AmiCpuS3Pei + +AmiCpuS3Pei: $(BUILD_DIR)\AmiCpuS3Pei.mak AmiCpuS3PeiBin + +$(BUILD_DIR)\AmiCpuS3Pei.mak : $(AmiCpuS3Pei_DIR)\$(@B).cif $(AmiCpuS3Pei_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(AmiCpuS3Pei_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +AmiCpuS3PeiBin : $(AMIPEILIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\AmiCpuS3Pei.mak all\ + MAKEFILE=$(BUILD_DIR)\AmiCpuS3Pei.mak \ + GUID=F7D22BCA-1BCA-5591-CC8B-1CA98F2890FE \ + ENTRY_POINT=AmiCpuS3PeiEntry\ + TYPE=PEIM \ + COMPRESS=0 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/CPU/CpuS3Pei/AmiCpuS3Pei.sdl b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.sdl new file mode 100644 index 0000000..32a8622 --- /dev/null +++ b/Board/CPU/CpuS3Pei/AmiCpuS3Pei.sdl @@ -0,0 +1,71 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI CPU S3 Pei/AmiCpuS3Pei.sdl 3 10/01/12 2:16a Davidhsieh $ +# +# $Revision: 3 $ +# +# $Date: 10/01/12 2:16a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI CPU S3 Pei/AmiCpuS3Pei.sdl $ +# +# 3 10/01/12 2:16a Davidhsieh +# +# 2 9/27/12 12:26a Davidhsieh +# +# 1 9/26/12 10:45a Davidhsieh +# +#********************************************************************** +TOKEN + Name = "AMI_CPU_S3_PEI_SUPPORT" + Value = "1" + Help = "Main switch to enable AMI CPU S3 PEI support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "AmiCpuS3Pei_DIR" +End + +MODULE + Help = "Includes AmiCpuS3Pei.mak to Project" + File = "AmiCpuS3Pei.mak" +End + +ELINK + Name = "$(BUILD_DIR)\AmiCpuS3Pei.ffs" + Parent = "FV_BB" + Help = "AMI CPU S3 PEI component" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/CPU/CpuSmbios.sdl b/Board/CPU/CpuSmbios.sdl new file mode 100644 index 0000000..3788da3 --- /dev/null +++ b/Board/CPU/CpuSmbios.sdl @@ -0,0 +1,95 @@ +TOKEN + Name = "CPU_MODULE_CREATE_SMBIOS_TABLES" + Value = "1" + Help = "Enable for CPU Module. Also, disable token PROCESSOR_INFO.\Disable for SMBIOS module.\\\" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "CPU_CACHE_L4_DISPLAY_IN_SMBIOS" + Value = "0" + Help = "The SMBIOS will display L4, if CPU support." + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "SMBIOS_TYPE_4_PROC_FAMILY" + Value = "0" + Help = "0 - Autodetect\0xce - Intel Core i3\0xcd - Intel Core i5\0xc6 - Intel Core i7\0xb3 - Intel Xeon" + TokenType = Integer + TargetH = Yes + Range = "0-ff" +End + +TOKEN + Name = "SMBIOS_TYPE_4_PROC_UPGRADE" + Value = "0x24" + Help = "0x21 - Mobile - Socket rPGA988B\0x22 - Mobile - Socket BGA1023\0x23 - Mobile - Socket LGA1224\0x24 - DT - Socket LGA1155 \0x25 - EN - Socket LGA1356\0x26 - EP - Socket LGA2011\" + TokenType = Integer + TargetH = Yes + Range = "0-ff" +End + +TOKEN + Name = "SMBIOS_TYPE_4_MAX_SPEED" + Value = "0" + Help = "Value in MHz." + TokenType = Integer + TargetH = Yes + Range = "0-ffff" +End + +TOKEN + Name = "SMBIOS_TYPE_4_ASSET_TAG" + Value = "Fill By OEM" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SMBIOS_TYPE_4_PART_NUMBER" + Value = "Fill By OEM" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SMBIOS_TYPE_4_SOCKET_DESIGINTATION_SOCKET_0" + Value = "SOCKET 0" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SMBIOS_TYPE_7_L1_SOCKET_DESIGNATION" + Value = "CPU Internal L1" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SMBIOS_TYPE_7_L2_SOCKET_DESIGNATION" + Value = "CPU Internal L2" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SMBIOS_TYPE_7_L3_SOCKET_DESIGNATION" + Value = "CPU Internal L3" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SMBIOS_TYPE_7_L4_SOCKET_DESIGNATION" + Value = "CPU Internal L4" + TokenType = Expression + TargetH = Yes + Token = "CPU_CACHE_L4_DISPLAY_IN_SMBIOS" "=" "1" +End + diff --git a/Board/CPU/Microcode/DESKTOP/DESKTOP.SDL b/Board/CPU/Microcode/DESKTOP/DESKTOP.SDL new file mode 100644 index 0000000..60e0b90 --- /dev/null +++ b/Board/CPU/Microcode/DESKTOP/DESKTOP.SDL @@ -0,0 +1,1260 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30071 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +#**************************************************************************** +# $Header: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/DESKTOP/DESKTOP.SDL 114 2/22/17 1:31a Davidhsieh $ +# +# $Revision: 114 $ +# +# $Date: 2/22/17 1:31a $ +# +#**************************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/DESKTOP/DESKTOP.SDL $ +# +# 114 2/22/17 1:31a Davidhsieh +# [TAG] EIP319448 +# [Category] Spec Update +# [Severity] Important +# [Description] Updated Intel(R) Haswell C-0 Stepping(306C3) version 22 +# +# Updated Intel(R) Broadwell-H G-0 Stepping(40671) version 17 +# +# Updated Intel(R) Haswell Perf Halo C-0 Stepping(40661) version 17 +# +# Update Intel(R) Sandy Bridge-E C-1, M-0 Stepping(206D6) version 619 +# +# Updated Intel(R) Broadwell-E R-0 Stepping(406F1) version 0B00001D +# +# Updated Intel(R) Haswell-E R-2 Stepping(306F2) version 38 +# +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 113 6/17/16 4:05p Artems +# [TAG] EIP275143 +# [Category] Improvement +# [Description] Updated Intel(R) Haswell Processor C-0 Stepping version +# 21 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 112 4/29/16 11:53a Artems +# [TAG] EIP266854 +# [Category] Improvement +# [Description] [Aptio 4_MCU] Intel DT microcode update DT_B_100 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 111 4/29/16 11:31a Artems +# [TAG] EIP265620 +# [Category] Improvement +# [Description] [Aptio 4_MCU] Iintel DT microcode update DT_P_106 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 110 2/19/16 2:46p Artems +# [TAG] EIP256973 +# [Category] Improvement +# [Description] [Aptio4_MCU]Intel DT Processors Microcode Update +# DT_P_103 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 109 8/14/15 5:30p Artems +# [TAG] EIP233803 +# [Description] Updated Clarkdale Processor C-2 Stepping version 0F +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 108 8/10/15 4:27p Artems +# [TAG] EIP232434 +# [Description] Updated Clarkdale Processor K-0 Stepping version 05 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 107 8/05/15 12:01p Artems +# [TAG] EIP231326 +# [Description] Updated Gulftown Processor B-1 Stepping version 1C +# Updated Lynnfield Processor B-1 Stepping version 08 +# Updated Bloomfield Processor D-0 Stepping version 1B +# Updated Bloomfield Processor C-0 Stepping version 13 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 106 7/17/15 6:06p Artems +# [TAG] EIP229101 +# [Category] Improvement +# [Description] Updated Broadwell-H Processor G-0 Stepping version 12 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 105 6/17/15 5:40p Artems +# [TAG] EIP223845 +# [Description] Updated Broadwell-H Processor G-0 Stepping version 11 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 104 5/18/15 4:48p Artems +# [TAG] EIP218685 +# [Category] Improvement +# [Description] Added Broadwell-E Processor L-0 Stepping version 10 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 103 5/14/15 5:08p Artems +# [TAG] EIP217911 +# [Category] Improvement +# [Description] Updated Broadwell-H Processor G-0 Stepping version 10 +# [Files] DESKTOP.SDL +# Desktop.CIF +# +# 102 5/07/15 3:06p Artems +# +# 101 3/17/15 5:32p Artems +# Updated IvyBridge Processor E-1, L-1 Stepping version 1C +# +# 100 1/12/15 6:23p Artems +# Desktop +# Updated Haswell processor( 306CX) C-0 stepping to version 1D +# +# 99 11/25/14 10:32a Markw +# +# 98 11/20/14 6:13p Markw +# Update dependency. +# +# 97 11/20/14 11:10a Mithunraghavs +# Added Broadwell-H (4067X) E-0 stepping version FFFF0003 +# +# 96 11/06/14 2:48p Markw +# Updated Haswell-E M-0, R2 (306F2) to version 29. +# +# 94 7/21/14 2:59p Craigv +# Updated Haswell C-0 (306C3) to version 1C. +# Updated Haswell Perf Halo C-0 (40661) to version 12. +# Updated Haswell-E M-0 (306F2) to version 23. +# +# 93 6/23/14 12:44p Craigv +# Updated Haswell Perf Halo C-0 (40661) to version 10. +# Updated Haswell C-0 (306C3) to version 1A. +# Updated Ivy Bridge E S-1 (306E4) to version 428. +# Updated Ivy Bridge E-1, L-1 (306A9) to version 1B. +# +# 92 5/29/14 1:17p Craigv +# Updated Haswell C-0 (306C3) to version 19. +# Updated Haswell-E (306F2) M-0 to version 1E. +# +# 91 1/30/14 1:46p Craigv +# Updated IvyBridge-E S-1 (306E4) to version 00000424. +# Updated to production status +# +# 90 1/23/14 5:31p Craigv +# Updated Ivy Bridge-E (306E2) L-1, R-1 to version 0000020D. +# Added Haswell-E (306F2) M-0 version 00000007. +# +# 89 10/23/13 10:02a Mithunraghavs +# The microcode for the Haswell-E processor (Haswell-E), Family 6 Model +# 3F Step 1 (L-0) has been updated from 80000011 to 80000013 +# +# 88 10/16/13 11:50a Markw +# Remove non-production from Haswell Perf C-0 (40661). +# +# 87 10/14/13 6:04p Craigv +# Updated Haswell C-0 (306C3) to version 00000017. +# Updated Haswell Perf Halo C-0 (40661) to version 0000000F. +# +# 86 9/23/13 3:10p Craigv +# Added Haswell-E Processor (306F1) version 80000011. +# +# 85 9/13/13 5:05p Markw +# Updated Intel Lynnfield Xeon B-1 (106E5) to version 7. +# +# 84 8/28/13 10:27a Markw +# Fix e-link 306C3 to point to correct microcode version. +# +# 83 8/27/13 11:38a Markw +# Remove non production from 306C3. +# +# 81 7/26/13 4:37p Craigv +# Updated Intel(R) Haswell Perf Halo Processor C-0 (40661) to version +# 0000000E. +# +# 80 7/18/13 12:22p Craigv +# Updated Intel Lynnfield B-1 (106E5) to version 00000006. +# Updated Intel Clarkdale K-0 (20655) to version 00000004. +# Updated Intel Clarkdale C-2 (20652) to version 0000000E. +# Updated Intel Bloomfield D-0 (106A5) to version 00000019. +# Updated Intel Bloomfield C-0 (106A4) to version 00000012. +# Updated Intel Haswell C-0 (306C3) to version 00000012. +# +# 79 7/15/13 11:37a Craigv +# Updated intel Ivy Bridge-E S-1 (306E4) to version 00000416. +# +# 78 7/02/13 1:50p Craigv +# Updated Gulftown B-1 (206C2) to version 0000001A. +# Updated Haswell C-0 (306C3) to version 00000010. +# +# 77 6/26/13 7:18p Craigv +# Updated Intel SandyBridge-E (206D7) C-2, M-1 to version 00000710. +# Updated Intel Sandy Bridge (206A7) Q-0, D-2 to version 00000029. +# Updated Intel Ivy Bridge (306A9) E-1, L-1 to version 00000019. +# +# 76 6/13/13 3:46p Craigv +# Added Intel Ivy Bridge-E S-1 (306E4) version 413. +# +# 75 5/20/13 3:16p Craigv +# Added Intel Haswell Perf Halo C-0 (40661) version 000A. +# +# 74 5/07/13 11:54a Craigv +# Update Haswell C-0 (306C3) to version 009. +# +# 73 3/22/13 11:25a Craigv +# Update Haswell C-0 (306C3) to version 008. +# +# 72 2/22/13 4:15p Craigv +# Updated Ivy Bridge-E (306E2) L-1 and R-1 to version 0000020C. +# +# 71 2/05/13 12:35p Craigv +# Update Haswell C-0 (306C3) to version 7. +# +# 70 1/28/13 11:38a Craigv +# Update Haswell C-0 (306C3) to version 6. +# +# 69 1/17/13 11:30a Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 17. +# +# 68 1/15/13 9:52p Craigv +# Added Ivy Bridge-E (306E2) version 00000209. +# +# 67 1/08/13 3:26p Markw +# Update Haswell C-0 (306C3) to version 3 +# +# 66 11/16/12 4:43p Craigv +# +# 65 11/16/12 4:40p Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 16 +# +# 64 10/30/12 10:20p Markw +# Update Haswell B-0 (306C2) to version FFFF_0006. +# +# 63 10/24/12 10:55a Craigv +# Added Haswell Perf Halo B-0 (40660) version FFFF_0011. +# Update Haswell B-0 (306C2) to version FFFF_0006. +# +# 62 9/19/12 6:03p Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 15. +# +# 61 7/20/12 2:59p Markw +# Update Haswell A-0 (306C1) to version FFFF0013. +# Update Haswell B-0 (306C2) to version FFFF0003. +# +# 60 5/31/12 11:33a Markw +# Updated help string to use tab instead of spaces for consistency. +# +# 59 5/22/12 5:18p Craigv +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 28. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 70C. +# +# 58 4/24/12 10:46a Markw +# Add NON_PRODUCTION_MICROCODE dependency to Haswell A-0. +# +# 57 4/23/12 10:52a Craigv +# Added Haswell processor A-0 Stepping version FFFF000D +# +# 56 4/17/12 3:02p Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 12. +# +# 55 3/26/12 3:52p Markw +# Place pack changes from version 53. +# +# 54 3/26/12 1:48p Craigv +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 26. +# +# 53 3/22/12 11:07a Markw +# Rearrange processor tokens to have the later CPUs earlier in the list. +# +# 52 3/19/12 2:29p Craigv +# Update Sandy Bridge-E C-1, M-0 (206D6) to version 616. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 70B. +# +# 51 2/29/12 11:01a Craigv +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version 10. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 10. +# +# 50 2/14/12 12:37p Craigv +# Update Sandy Bridge-E C-1, M-0 (206D6) to version 615. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 70A. +# +# 49 2/03/12 4:41p Craigv +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version C. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version C. +# +# 48 1/19/12 5:29p Markw +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version A. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version A. +# +# 47 1/19/12 12:33p Markw +# Update Sandy Bridge-E C-1, M-0 (206D6) to version 610. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 705. +# +# 46 1/17/12 1:45p Markw +# Update Intel(R) Ivy Bridge Processor E-0 (306A8) to version 8. +# +# 45 1/09/12 5:45p Markw +# Update Ivy Bridge E-1 (306A9) to Version 8. +# +# 44 12/06/11 4:08p Markw +# Update Sandy Bridge-E C-1 (206D6) to version 60F. +# Update Sandy Bridge-E C-2 (206D7) to version 704. +# Update Ivy Bridge E-0 (306A8) to Version 7. +# +# 43 11/09/11 12:55p Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 25. +# Update Sandy Bridge-E C-1 (206D6) to version 60D. +# Update Lynnfield B-1 (106E5) to version 5. +# +# 42 10/26/11 11:03a Markw +# Update Gulftown B-1 (206C2) to Version 15. +# Update Clarkdale C-2 (20652) to Version 0D. +# Update Clarkdale K-0 (20655) to Version 03. +# +# 41 10/11/11 3:50p Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 23. +# Update Sandybridge-E C-0 (206D5) to version 511. +# Update Sandy Bridge-E C-1 (206D6) to version 60C. +# +# 40 9/28/11 6:26p Markw +# Update Sandy Bridge-E C-0 (206D5) to version 511. +# Update Sandy Bridge-E C-0 (206D6) to version 60B. +# Update Intel(R) Ivy Bridge Processor C-0 (306A4) to version 7. +# Update Intel(R) Ivy Bridge Processor C-1 (306A5) to version 7. +# +# 39 8/29/11 2:55p Markw +# Update Sandy Bridge-E C-0 (206D5) to version 50D. +# Update Intel(R) Ivy Bridge Processor C-0 (306A4) to version 5. +# +# 38 8/10/11 7:07p Markw +# Update Sandybridge-E C-0 (206d5) to version 50B. +# +# 37 8/09/11 10:33a Markw +# Revert DESKTOP back to 0 as default as expected. +# +# 36 8/09/11 10:32a Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 1B. +# Update Sandybridge-E C-0 (206d5) to version 50A. +# +# 35 8/04/11 1:15p Markw +# Update Bloomfield D- 0 (106A5) to version 16. +# Update Sandybridge-E C-0 (206d5) to version 509. +# +# 34 7/27/11 1:33p Markw +# Update Sandy Bridge-E C-0 (206D5) to version 508. +# +# 33 7/12/11 11:46a Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 1A. +# +# 32 6/13/11 5:42p Markw +# Update Gulftown B1 (206C2) to Version 14. +# +# 31 6/03/11 12:23p Markw +# Update Intel(R) Ivy Bridge Processor B-0 (306A2) to version 8. +# +# 30 6/03/11 12:07p Markw +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 18. +# +# 29 5/12/11 5:21p Markw +# Update Bloomfield D-0 (106A5) to version 15. +# +# 28 4/27/11 6:29p Markw +# Update Sandy Bridge-E B-1 (206D3) to version 80000302. +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 17. +# +# 27 3/04/11 12:02p Markw +# Update Sandy Bridge-E B0 (206D1) to version 8000020A. +# +# 26 2/15/11 6:57p Markw +# Update Sandy Bridge-E A1 (206D0) to version 80000103. +# Update Sandy Bridge-E B0 (206D1) to version 80000207. +# +# 25 1/27/11 12:35p Markw +# Update Sandy Bridge D1, Q0 (206A7) to version 14. +# +# 24 1/04/11 10:33a Markw +# Update Sandy Bridge D1, Q0 (206A7) to version 12. +# +# 23 12/16/10 11:28a Markw +# Fixed dependency on M12206A7_0000000D.pdb. +# +# 22 11/30/10 10:22a Markw +# Update Sandy Bridge D1, Q0 (206A7) to version D. +# +# 21 10/15/10 4:41p Markw +# Update Sandy Bridge D1 (206A6) to version 28. +# +# 20 10/08/10 10:36a Markw +# Update Sandy Bridge D0 (206a5) to version 7. +# Add Sandy Bridge D2 (206a7) to version 6. +# +# 19 9/15/10 1:51p Markw +# Update Gulftown B1 (206C2) to Version 13. +# +# 18 9/02/10 5:04p Markw +# Update Gulftown B1 (206C2) to Version 10. +# +# 17 8/12/10 11:19a Markw +# +# 16 7/27/10 10:38a Hari +# Updated Microcode version for Clarkdale C2. +# +# 15 7/26/10 11:06a Hari +# Added Microcode for Sandy Bridge D0 +# +# 14 7/12/10 5:24p Hari +# Added M03206C2_0000000F for Westmere EP processor +# +# 13 6/08/10 6:44p Markw +# Update Sandy Bridge C0 stepping to version 8. +# +# 12 5/28/10 10:24a Markw +# Update Lynnfield B1 and add Clarkdale K0. +# +# 11 4/09/10 11:24a Markw +# Add Sandy Bridge B2. +# +# 10 3/04/10 5:07p Markw +# Add Sandy Bridge B0. +# +# 9 1/20/10 9:49a Markw +# Update Gulftown B0 +# +# 8 1/19/10 11:30p Markw +# Update Gulftown B1. +# +# 7 12/30/09 8:13p Markw +# Add Gulftown A1. +# +# 6 11/24/09 1:11p Markw +# Fix description. +# +# 5 11/24/09 1:07p Markw +# Fix filename. +# +# 4 11/24/09 12:37p Markw +# +# 3 11/24/09 12:30p Markw +# +# 2 10/16/09 9:50a Markw +# +# 1 9/29/09 2:51p Markw +#**************************************************************************** +TOKEN + Name = "DESKTOP" + Value = "0" + Help = "Master Desktop CPU uCode Enable" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Range = "On-Off" +End + +TOKEN + Name = "DESKTOP_406FX" + Value = "0" + Help = "Intel(R) Broadwell-E" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_4067X" + Value = "0" + Help = "Intel(R) Broadwell-H" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_4066X" + Value = "0" + Help = "Intel(R) Haswell Perf Halo" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_306FX" + Value = "0" + Help = "Intel(R) Haswell-E" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_306CX" + Value = "0" + Help = "Intel(R) Haswell" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_306EX" + Value = "0" + Help = "Intel(R) Ivy Bridge-E" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_306AX" + Value = "0" + Help = "Intel(R) Ivy Bridge" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_206DX" + Value = "0" + Help = "Intel(R) SandyBridge-E processors" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_206AX" + Value = "0" + Help = "Intel(R) Sandy Bridge" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_106FX" + Value = "0" + Help = "Intel(R) Havendale" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_2065X" + Value = "0" + Help = "Intel(R) Clarkdale" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_106EX" + Value = "0" + Help = "Intel(R) Clarksfield" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_206CX" + Value = "0" + Help = "Intel(R) Gulftown" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_106AX" + Value = "0" + Help = "Intel(R) Bloomfield" + TokenType = Boolean +End + +TOKEN + Name = "DESKTOP_M03106A4" + Value = "1" + Help = "Bloomfield C-0" + TokenType = Boolean + Token = "DESKTOP_106AX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M03106A5" + Value = "1" + Help = "Bloomfield D-0" + TokenType = Boolean + Token = "DESKTOP_106AX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13106E0" + Value = "1" + Help = "Intel(R) Clarksfield A-0" + TokenType = Boolean + Token = "DESKTOP_106EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13106E1" + Value = "1" + Help = "Intel(R) Clarksfield A-2 \CPU Signature 106E1" + TokenType = Boolean + Token = "DESKTOP_106EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13106E5" + Value = "1" + Help = "Intel(R) Lynnfield B-1" + TokenType = Boolean + Token = "DESKTOP_106EX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13206C0" + Value = "1" + Help = "Intel(R) Gulftown A-0" + TokenType = Boolean + Token = "DESKTOP_206CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M03206C1" + Value = "1" + Help = "Intel(R) Gulftown B-0" + TokenType = Boolean + Token = "DESKTOP_206CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M03206C2" + Value = "1" + Help = "Intel(R) Gulftown B-1" + TokenType = Boolean + Token = "DESKTOP_206CX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M1320651" + Value = "1" + Help = "Intel(R) Clarkdale C-0" + TokenType = Boolean + Token = "DESKTOP_2065X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M1220652" + Value = "1" + Help = "Intel(R) Clarkdale C-2" + TokenType = Boolean + Token = "DESKTOP_2065X" "=" "1" +End + +TOKEN + Name = "DESKTOP_M9220655" + Value = "1" + Help = "Intel(R) Clarkdale K-0" + TokenType = Boolean + Token = "DESKTOP_2065X" "=" "1" +End + +TOKEN + Name = "DESKTOP_M13106F1" + Value = "1" + Help = "Intel(R) Havendale B-0" + TokenType = Boolean + Token = "DESKTOP_106FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12206A1" + Value = "1" + Help = "Intel(R) Sandy Bridge B-0" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A2" + Value = "1" + Help = "Intel(R) Sandy Bridge B-2" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A3" + Value = "1" + Help = "Intel(R) Sandy Bridge C-0" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A5" + Value = "1" + Help = "Intel(R) Sandy Bridge D-0" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A6" + Value = "1" + Help = "Intel(R) Sandy Bridge D-1" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +END + +TOKEN + Name = "DESKTOP_M12206A7" + Value = "1" + Help = "Intel(R) Sandy Bridge D-2 and Q-0" + TokenType = Boolean + Token = "DESKTOP_206AX" "=" "1" +END + +TOKEN + Name = "DESKTOP_M07206D1" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor A-1 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M0F206D2" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor B-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M0F206D3" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor B-1 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M6D206D5" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor C-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M6D206D6" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor C-1 and M-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M6D206D7" + Value = "1" + Help = "Intel(R) SandyBridge-E Processor C-2 and M-1 Stepping" + TokenType = Boolean + Token = "DESKTOP_206DX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A2" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor B-0" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A4" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor C-0" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A5" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor C-1" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A8" + Value = "1" + Help = "Intel(R) Ivy Bridge E-0 and L-0" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M12306A9" + Value = "1" + Help = "Intel(R) Ivy Bridge E-1 and L-1" + TokenType = Boolean + Token = "DESKTOP_306AX" "=" "1" +End + +TOKEN + Name = "DESKTOP_MED306E2" + Value = "1" + Help = "Intel(R) Ivy Bridge-E L-1 R-1" + TokenType = Boolean + Token = "DESKTOP_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_MED306E4" + Value = "1" + Help = "Intel(R) Ivy Bridge-E S-1" + TokenType = Boolean + Token = "DESKTOP_306EX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M32306C1" + Value = "1" + Help = "Intel(R) Haswell Processor A-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M32306C2" + Value = "1" + Help = "Intel(R) Haswell Processor B-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M32306C3" + Value = "1" + Help = "Intel(R) Haswell C-0" + TokenType = Boolean + Token = "DESKTOP_306CX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M3240660" + Value = "1" + Help = "Intel(R) Haswell Perf Halo Processor B-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_4066X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_M3240661" + Value = "1" + Help = "Intel(R) Haswell Perf Halo Processor C-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_4066X" "=" "1" +End + +TOKEN + Name = "DESKTOP_MEF306F1" + Value = "1" + Help = "Intel(R) Haswell-E Processor L-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_306FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_MEF306F2" + Value = "1" + Help = "Intel(R) Haswell-E Processor M-0, R-2 Stepping" + TokenType = Boolean + Token = "DESKTOP_306FX" "=" "1" +End + +TOKEN + Name = "DESKTOP_M2240671" + Value = "1" + Help = "Intel(R) Broadwell-H Processor E-0, G-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_4067X" "=" "1" +End + +TOKEN + Name = "DESKTOP_MEF406F0" + Value = "1" + Help = "Intel(R) Broadwell-E Processor L-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_406FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "DESKTOP_MEF406F1" + Value = "1" + Help = "Intel(R) Broadwell-E Processor R-0 Stepping" + TokenType = Boolean + Token = "DESKTOP_406FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +PATH + Name = "MICROCODE_DESKTOP_DIR" +End + +ELINK + Name = "$(Intel_Desktop)" + Parent = "MICROCODE_FILES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M03106A4_00000013.PDB" + Parent = "$(Intel_Desktop)" + Help = "Bloomfield C0" + Token = "DESKTOP_M03106A4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M03106A5_0000001B.PDB" + Parent = "$(Intel_Desktop)" + Help = "Bloomfield D0" + Token = "DESKTOP_M03106A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13106E0_FFFF001F.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarksfield A0" + Token = "DESKTOP_M13106E0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13106E1_FFFF000D.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarksfield A2" + Token = "DESKTOP_M13106E1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13106E5_00000008.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Lynnfield B1" + Token = "DESKTOP_M13106E5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13206C0_FFFF0016.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Gulftown A0" + Token = "DESKTOP_M13206C0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M03206C1_00000006.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Gulftown B0" + Token = "DESKTOP_M03206C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M03206C2_0000001C.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Gulftown B1" + Token = "DESKTOP_M03206C2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M1320651_FFFF0012.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarkdale C0" + Token = "DESKTOP_M1320651" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M1220652_0000000F.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarkdale C2" + Token = "DESKTOP_M1220652" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M9220655_00000005.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Clarkdale K0" + Token = "DESKTOP_M9220655" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M13106F1_FFFF0007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Havendale B0" + Token = "DESKTOP_M13106F1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A1_00000007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge B0" + Token = "DESKTOP_M12206A1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A2_00000026.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge B2" + Token = "DESKTOP_M12206A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A3_00000008.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge C0" + Token = "DESKTOP_M12206A3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A5_00000007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge D0" + Token = "DESKTOP_M12206A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A6_00000028.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge D1" + Token = "DESKTOP_M12206A6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12206A7_00000029.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Sandy Bridge D2 and Q0" + Token = "DESKTOP_M12206A7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M07206D1_80000103.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor A1 Stepping" + Token = "DESKTOP_M07206D1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M0F206D2_8000020A.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor B0 Stepping" + Token = "DESKTOP_M0F206D2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M0F206D3_80000302.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor B1 Stepping" + Token = "DESKTOP_M0F206D3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M6D206D5_00000512.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor C-0 Stepping" + Token = "DESKTOP_M6D206D5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M6D206D6_00000619.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor C-1 and M-0 Stepping" + Token = "DESKTOP_M6D206D6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M6D206D7_00000710.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) SandyBridge-E Processor C-2 and M-1 Stepping" + Token = "DESKTOP_M6D206D7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A2_00000008.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge B-0" + Token = "DESKTOP_M12306A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A4_00000007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge C-0" + Token = "DESKTOP_M12306A4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A5_00000007.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge C-1" + Token = "DESKTOP_M12306A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A8_00000010.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge E-0 and L-0" + Token = "DESKTOP_M12306A8" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M12306A9_0000001C.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge E-1 and L-1" + Token = "DESKTOP_M12306A9" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MED306E2_0000020D.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge-E L-1 and R-1" + Token = "DESKTOP_MED306E2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MED306E4_00000428.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Ivy Bridge-E S-1" + Token = "DESKTOP_MED306E4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M32306C1_FFFF0013.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell Processor A-0" + Token = "DESKTOP_M32306C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M32306C2_FFFF0006.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell Processor B-0" + Token = "DESKTOP_M32306C2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M32306C3_00000022.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell C-0" + Token = "DESKTOP_M32306C3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M3240660_FFFF0011.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell Perf Halo Processor B-0 Stepping" + Token = "DESKTOP_M3240660" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M3240661_00000017.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell Perf Halo Processor C-0 Stepping" + Token = "DESKTOP_M3240661" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MEF306F1_80000013.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell-E Processor L-0 Stepping" + Token = "DESKTOP_MEF306F1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M6F306F2_00000038.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Haswell-E Processor M-0, R-2 Stepping" + Token = "DESKTOP_MEF306F2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\M2240671_00000017.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Broadwell-H Processor E-0, G-0 Stepping" + Token = "DESKTOP_M2240671" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MEF406F0_00000010.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Broadwell-E Processor L-0 Stepping" + Token = "DESKTOP_MEF406F0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_DESKTOP_DIR)\MEF406F1_0B00001D.PDB" + Parent = "$(Intel_Desktop)" + Help = "Intel(R) Broadwell-E Processor R-0 Stepping" + Token = "DESKTOP_MEF406F1" "=" "1" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/Board/CPU/Microcode/DESKTOP/Desktop.CIF b/Board/CPU/Microcode/DESKTOP/Desktop.CIF new file mode 100644 index 0000000..0d660fd --- /dev/null +++ b/Board/CPU/Microcode/DESKTOP/Desktop.CIF @@ -0,0 +1,49 @@ +<component> + name = "Desktop CPU uCode Patches" + category = ModulePart + LocalRoot = "Board\CPU\Microcode\DESKTOP" + RefName = "INTEL_DESKTOP" +[files] +"DESKTOP.SDL" = "SDL FILES" +"M03106A4_00000013.PDB" = "Desktop Microcode Update" +"M03106A5_0000001B.PDB" = "Desktop Microcode Update" +"M13106E0_FFFF001F.PDB" = "Desktop Microcode Update" +"M13106E1_FFFF000D.PDB" = "Desktop Microcode Update" +"M13106E5_00000008.PDB" = "Desktop Microcode Update" +"M13106F1_FFFF0007.PDB" = "Desktop Microcode Update" +"M1320651_FFFF0012.PDB" = "Desktop Microcode Update" +"M1220652_0000000F.PDB" = "Desktop Microcode Update" +"M9220655_00000005.PDB" = "Desktop Microcode Update" +"M12206A1_00000007.PDB" = "Desktop Microcode Update" +"M12206A2_00000026.PDB" = "Desktop Microcode Update" +"M12206A3_00000008.PDB" = "Desktop Microcode Update" +"M12206A5_00000007.PDB" = "Desktop Microcode Update" +"M12206A6_00000028.PDB" = "Desktop Microcode Update" +"M12206A7_00000029.PDB" = "Desktop Microcode Update" +"M13206C0_FFFF0016.PDB" = "Desktop Microcode Update" +"M03206C1_00000006.PDB" = "Desktop Microcode Update" +"M03206C2_0000001C.PDB" = "Desktop Microcode Update" +"M07206D1_80000103.PDB" = "Desktop Microcode Update" +"M0F206D2_8000020A.PDB" = "Desktop Microcode Update" +"M0F206D3_80000302.PDB" = "Desktop Microcode Update" +"M6D206D5_00000512.PDB" = "Desktop Microcode Update" +"M6D206D6_00000619.PDB" = "Desktop Microcode Update" +"M6D206D7_00000710.PDB" = "Desktop Microcode Update" +"M12306A2_00000008.PDB" = "Desktop Microcode Update" +"M12306A4_00000007.PDB" = "Desktop Microcode Update" +"M12306A5_00000007.PDB" = "Desktop Microcode Update" +"M12306A8_00000010.PDB" = "Desktop Microcode Update" +"M12306A9_0000001C.PDB" = "Desktop Microcode Update" +"M32306C1_FFFF0013.PDB" = "Desktop Microcode Update" +"M32306C2_FFFF0006.PDB" = "Desktop Microcode Update" +"M32306C3_00000022.PDB" = "Desktop Microcode Update" +"MED306E2_0000020D.PDB" = "Desktop Microcode Update" +"MED306E4_00000428.PDB" = "Desktop Microcode Update" +"MEF306F1_80000013.PDB" = "Desktop Microcode Update" +"M6F306F2_00000038.PDB" = "Desktop Microcode Update" +"M3240660_FFFF0011.PDB" = "Desktop Microcode Update" +"M3240661_00000017.PDB" = "Desktop Microcode Update" +"M2240671_00000017.PDB" = "Desktop Microcode Update" +"MEF406F0_00000010.PDB" = "Desktop Microcode Update" +"MEF406F1_0B00001D.PDB" = "Desktop Microcode Update" +<endComponent> diff --git a/Board/CPU/Microcode/DESKTOP/M03106A4_00000013.PDB b/Board/CPU/Microcode/DESKTOP/M03106A4_00000013.PDB Binary files differnew file mode 100644 index 0000000..073d1d6 --- /dev/null +++ b/Board/CPU/Microcode/DESKTOP/M03106A4_00000013.PDB diff --git a/Board/CPU/Microcode/DESKTOP/M03106A5_0000001B.PDB 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+#** ** +#************************************************************************* +#************************************************************************* +#**************************************************************************** +# $Header: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/MOBILE/MOBILE.SDL 80 2/22/17 3:05a Davidhsieh $ +# +# $Revision: 80 $ +# +# $Date: 2/22/17 3:05a $ +# +#**************************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/MOBILE/MOBILE.SDL $ +# +# 80 2/22/17 3:05a Davidhsieh +# [TAG] EIP319448 +# [Category] Spec Update +# [Severity] Important +# [Description] +# Updated Intel(R) Haswell C0 Stepping(306C3) version 22 +# Updated Intel(R) Broadwell-H G0 Stepping(40671) version 17 +# Updated Intel(R) Haswell Perf Halo C0 Stepping(40661) version 17 +# Updated Intel(R) Haswell ULT C0/D0 Stepping(40651) version 20 +# Updated Intel(R) Broadwell E0/F0 Stepping(306D4) version 25 +# +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 79 10/04/16 1:38p Artems +# [TAG] EIP295177 +# [Category] Improvement +# [Description] [Aptio4_MCU] Intel NB Processors Microcode Update +# MOB_P_77/MOB_B_90 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 78 6/17/16 4:09p Artems +# [TAG] EIP275143 +# [Category] Improvement +# [Description] Updated Intel(R) Haswell Processor C-0 Stepping version +# 21 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 77 5/17/16 2:17p Artems +# [TAG] EIP268478 +# [Category] Improvement +# [Description] M32306C3_00000020.TXT | Assembly format, Revision +# 00000020 | C-0 (Haswell) +# M7240651_0000001F.TXT | Assembly format, Revision 0000001F | C-0 +# (Haswell ULT) +# M7240651_0000001F.TXT | Assembly format, Revision 0000001F | D-0 +# (Haswell ULT) +# +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 76 2/26/16 2:01p Artems +# [TAG] EIP258108 +# [Category] Improvement +# [Description] [Aptio4_MCU]Intel DT Processors Microcode Update +# MOB_P_67 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 75 8/14/15 5:31p Artems +# [TAG] EIP233803 +# [Description] Updated Arrandale Processor C-2 Stepping version 0F +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 74 8/10/15 4:25p Artems +# [TAG] EIP232434 +# [Description] Updated Arrandale Processor K-0 Stepping version 05 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 73 8/05/15 11:57a Artems +# [TAG] EIP231326 +# [Description] Updated Clarksfield Processor B-1 Stepping version 08 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 72 7/17/15 6:07p Artems +# [TAG] EIP229101 +# [Description] Updated Broadwell-H Processor G-0 Stepping version 12 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 71 6/17/15 5:42p Artems +# [TAG] EIP223845 +# [Description] Updated Broadwell Processor E-0, F-0 Stepping version +# 21 +# Updated Broadwell-H Processor G-0 Stepping version 11 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 70 5/14/15 5:09p Artems +# [TAG] EIP217911 +# [Category] Improvement +# [Description] Updated Broadwell-H Processor G-0 Stepping version 10 +# [Files] MOBILE.SDL +# Mobile.CIF +# +# 69 5/07/15 3:54p Artems +# +# 68 5/07/15 3:22p Artems +# +# 67 3/17/15 5:29p Artems +# Updated IvyBridge Processor E-1, L-1 Stepping version 1C +# +# 66 1/12/15 6:22p Artems +# Mobile +# Updated Haswell processor( 306CX) C-0 stepping to version 1D +# +# 65 7/21/14 3:13p Craigv +# Updated Haswell ULT C-0, D-0 (40651) to version 1C. +# +# 64 7/21/14 2:49p Craigv +# Updated Haswell Perf Halo C-0 (30661) to version 12. +# Updated Haswell C-0 (306C3) to version 1C. +# +# 63 6/23/14 11:59a Craigv +# Updated Haswell Perf Halo (40661) to version 10. +# Updated Haswell ULT C-0, D-0 (40651) to version 18. +# Updated Haswell C-0 (306C3) to version 1A. +# Updated Ivy Bridge E-1, L-1 (306A9) to version 1B. +# +# 62 5/29/14 12:34p Craigv +# Updated Haswell C-0 (306C3) to version 19. +# +# 61 10/16/13 11:54a Markw +# Remove non-production from Haswell Perf Halo C-0 (40661). +# +# 60 10/14/13 4:00p Craigv +# Updated Haswell Processor C-0 (306C3) to version 00000017. +# Updated Haswell ULT C-0, D-0 (40651) to version 00000017. +# Updated Haswell Perf Halo C-0 (40661) to version 0000000F. +# +# 59 8/20/13 4:15p Craigv +# Updated Intel Haswell C-0 (306C3) to version 00000016. +# Updated Intel Haswell ULT C-0 (40651) to version 00000016. +# +# 58 7/26/13 4:36p Craigv +# Updated Intel Haswell Perf Halo Processor C-0 (40661) to version +# 0000000E. +# +# 56 7/18/13 11:30a Craigv +# Updated Intel Haswell C-0 (306C3) to version 00000012. +# Updated Intel Haswell ULT C-0 (40651) to version 00000015. +# +# 55 7/15/13 7:32p Markw +# Fix production settings for newly added microcode. +# +# 54 7/15/13 12:17p Craigv +# Updated Intel Clarksfield B-1 (106E5) to version 00000006. +# Added Intel Arrandale C-2 (20652) version 0000000E. +# Added Intel Arrandale K-0 (20655) version 00000004. +# +# 53 7/02/13 1:54p Craigv +# Updated Haswell C-0 (306C3) to version 00000010. +# Updated Haswell ULT C-0 (40651) to version 00000014. +# +# 52 6/26/13 7:36p Craigv +# Updated Ivy Bridge (306A9) E-1, L-1, N-0 to version 00000019. +# Updated Sandy Bridge (206A7) D-2, J-1 to version 00000029. +# +# 51 5/20/13 2:59p Craigv +# Added Intel Haswell Perf Halo C-0 Stepping (M3240661) version 000A. +# +# 50 5/07/13 12:02p Craigv +# Updated Intel(R) Haswell ULT C-0 (40651) to version 010. +# +# 49 4/17/13 5:39p Craigv +# Updated Intel(R) Haswell ULT C-0 (40651) to version 00A. +# +# 48 3/27/13 2:26p Markw +# Update Haswell ULT C-0 (40651) to version 8. +# +# 47 3/25/13 7:04p Craigv +# Updated Haswell ULT (40651) C-0 to version 006. +# +# 46 3/22/13 11:30a Craigv +# Update Haswell C-0 (306C3) to version 008. +# +# 45 2/06/13 11:30a Markw +# Update help string. +# +# 44 2/05/13 12:38p Craigv +# Update Haswell ULT C-0 (40651) to version 5. +# Update Haswell C-0 (306C3) to version 7. +# +# 43 1/28/13 11:41a Craigv +# Update Haswell C-0 (306C3) to version 6. +# +# 42 1/17/13 11:44a Craigv +# Update Intel(R) Ivy Bridge Processor E-1, L-1 (306A9) to version 17. +# +# 41 1/08/13 3:14p Markw +# Update Haswell ULT C-1 (40651) to version 2. +# Update Haswell C-0 (306C3) to version 4. +# +# 40 12/14/12 12:06p Craigv +# Update Haswell ULT B-0 (40650) to version FFFF_000B. +# +# 39 12/04/12 11:18a Craigv +# Update Haswell ULT B-0 (40650) to version FFFF_000A. +# +# 38 11/16/12 4:31p Craigv +# Update Intel(R) Ivy Bridge Processor E-1, L-1, N-0 (306A9) to version +# 16 +# +# 37 10/30/12 4:01p Craigv +# Update Haswell ULT B-0 (40650) to version FFFF_0009 +# +# 36 10/24/12 10:43a Craigv +# Update Haswell Perf Halo B-0 (40660) to version FFFF_0011. +# Update Haswell B-0 (306C2) to version FFFF_0006. +# +# 35 9/07/12 3:58p Craigv +# Update Intel(R) Ivy Bridge Processor E-1, L-1, N-0 (306A9) to version +# 15 +# +# 34 8/27/12 11:48a Craigv +# Update Haswell ULT B-0 (40650) to version FFFF_0007 +# +# 33 8/14/12 12:59p Craigv +# Update Haswell Perf Halo B-0 (40660) to version FFFF_000B. +# +# 32 8/13/12 7:31p Craigv +# Update Intel(R) Ivy Bridge Processor E-1, L-1, N-0 (306A9) to version +# 13 +# +# 31 7/20/12 11:19a Markw +# Update Haswell A-0 (306C1) to version FFFF_000D. +# Update Haswell B-0 (306C2) to version FFFF_0003. +# Update Haswell ULT B-0 (40650) to version FFFF_0004. +# +# 30 7/09/12 10:16a Markw +# Fix default of Haswell B-0 to be disabled. +# +# 29 7/06/12 5:56p Markw +# +# 28 7/06/12 5:22p Craigv +# Added Haswell processor B-0 Stepping version FFFF000A +# +# 27 5/22/12 12:30p Markw +# Add revision 25 changes back into file. +# +# 26 5/21/12 7:06p Craigv +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 28 +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 and N-0 (306A9) to +# version 12 +# +# 25 4/24/12 10:52a Markw +# Add NON_PRODUCTION_MICROCODE dependency to Haswell A-0. +# Rearrange processor tokens to have the later CPUs earlier in the list. +# +# 24 4/23/12 10:42a Craigv +# Added Haswell processor A-0 Stepping version FFFF000D +# +# 23 4/17/12 3:00p Craigv +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 12. +# +# 22 3/26/12 1:50p Craigv +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 26. +# +# 21 2/29/12 10:55a Craigv +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version 10. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version 10. +# +# 20 2/02/12 2:30p Markw +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version C. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version C. +# +# 19 1/19/12 5:24p Markw +# Update Intel(R) Ivy Bridge Processor E-0 and L-0 (306A8) to version A. +# Update Intel(R) Ivy Bridge Processor E-1 and L-1 (306A9) to version A. +# +# 18 1/17/12 1:44p Markw +# Update Intel(R) Ivy Bridge Processor E-0 (306A8) to version 8. +# +# 17 1/09/12 5:47p Markw +# Update Ivy Bridge E-1 (306A9) to Version 8. +# +# 16 12/06/11 4:20p Markw +# Update Intel(R) Ivy Bridge Processor E-0 (306A8) to version 7. +# +# 15 11/09/11 12:23p Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 25. +# +# 14 10/11/11 3:58p Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 23. +# +# 13 9/28/11 6:45p Markw +# Update Intel(R) Ivy Bridge Processor C-0 (306A4) to version 7. +# Update Intel(R) Ivy Bridge Processor K-0 (306A5) to version 7. +# +# 12 8/29/11 2:46p Markw +# Update Intel(R) Ivy Bridge Processor C-0 (306A4) to version 5. +# +# 11 8/09/11 10:34a Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 1B. +# +# 10 7/12/11 10:59a Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 1A. +# +# 9 6/03/11 11:58a Markw +# Update Intel(R) Sandy Bridge Processor D-2, J-1 (206A7) to version 18. +# Update Intel(R) Ivy Bridge Processor B-0 (306A2) to version 8. +# +# 8 4/27/11 6:35p Markw +# Update Intel(R) Sandy Bridge Processor D2, J1 (206A7) to version 17. +# +# 7 3/07/11 6:55p Markw +# Update Intel(R) Sandy Bridge Processor D2, J1 (206A7) to version 12. +# +# 6 1/03/11 7:10p Markw +# Update Intel(R) Sandy Bridge Processor D2, J1 (206A7) to version 12. +# +# 5 11/30/10 10:54a Markw +# Updated help string 206A3 is for both C0 and P0. +# +# 4 11/30/10 10:50a Markw +# Update Intel(R) Sandy Bridge Processor D0 (206A5) to version 7. +# Update Intel(R) Sandy Bridge Processor D1 (206A6) to version 28. +# Update Intel(R) Sandy Bridge Processor D2, J1 (206A7) to version D. +# +# 3 6/15/10 1:07p Fasihm +# Add Sandy Bridge stepping A0, B2, C0 (206AX) microcode. +# +# 2 11/24/09 1:02p Markw +# Remove incorrect dependency. +# +# 1 9/29/09 2:51p Markw +# +#**************************************************************************** + +TOKEN + Name = "MOBILE" + Value = "0" + Help = "Master Mobile CPU uCode Enable" + TokenType = Boolean + Master = Yes + Range = "On-Off" +End + +TOKEN + Name = "MOBILE_4067X" + Value = "0" + Help = "Intel(R) Broadwell-H" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_4066X" + Value = "0" + Help = "Intel(R) Haswell Perf Halo" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_4065X" + Value = "0" + Help = "Intel(R) Haswell ULT" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_306DX" + Value = "0" + Help = "Intel(R) Broadwell" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_306CX" + Value = "0" + Help = "Intel(R) Haswell" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_306AX" + Value = "0" + Help = "Intel(R) Ivy Bridge" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_206AX" + Value = "0" + Help = "Intel(R) Sandy Bridge" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_2065X" + Value = "0" + Help = "Intel(R) Arrandale Processor" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_106FX" + Value = "0" + Help = "Intel(R) Auburndale Processor" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_106EX" + Value = "0" + Help = "Intel(R) Clarksfield Processor" + TokenType = Boolean +End + +TOKEN + Name = "MOBILE_M1320650" + Value = "1" + Help = "Intel(R) Arrandale Processor A0." + TokenType = Boolean + Token = "MOBILE_2065X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M1320651" + Value = "1" + Help = "Intel(R) Arrandale Processor C0 Stepping." + TokenType = Boolean + Token = "MOBILE_2065X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M1220652" + Value = "1" + Help = "Intel(R) Arrandale Processor C-2 Stepping." + TokenType = Boolean + Token = "MOBILE_2065X" "=" "1" +End + +TOKEN + Name = "MOBILE_M9220655" + Value = "1" + Help = "Intel(R) Arrandale Processor K-0 Stepping." + TokenType = Boolean + Token = "MOBILE_2065X" "=" "1" +End + +TOKEN + Name = "MOBILE_M13106F1" + Value = "1" + Help = "Intel(R) Auburndale Processor." + TokenType = Boolean + Token = "MOBILE_106FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + + +TOKEN + Name = "MOBILE_M13106E5" + Value = "1" + Help = "Intel(R) Clarksfield Processor." + TokenType = Boolean + Token = "MOBILE_106EX" "=" "1" +End + +TOKEN + Name = "MOBILE_M13106E3" + Value = "1" + Help = "Intel(R) Clarksfield Processor." + TokenType = Boolean + Token = "MOBILE_106EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A0" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor A0" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A2" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor B2" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A3" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor C0, P0" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A5" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor D0" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A6" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor D1" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12206A7" + Value = "1" + Help = "Intel(R) Sandy Bridge Processor D2, J1" + TokenType = Boolean + Token = "MOBILE_206AX" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A2" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor B-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A4" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor C-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A5" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor K-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A8" + Value = "1" + Help = "Intel(R) Ivy Bridge E-0 and L-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M12306A9" + Value = "1" + Help = "Intel(R) Ivy Bridge E-1, L-1, and N-0" + TokenType = Boolean + Token = "MOBILE_306AX" "=" "1" +End + +TOKEN + Name = "MOBILE_M32306C1" + Value = "1" + Help = "Intel(R) Haswell Processor A-0 Stepping" + TokenType = Boolean + Token = "MOBILE_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M32306C2" + Value = "1" + Help = "Intel(R) Haswell Processor B-0 Stepping" + TokenType = Boolean + Token = "MOBILE_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_MF2306D2" + Value = "1" + Help = "Intel(R) Broadwell Processor C-0" + TokenType = Boolean + Token = "MOBILE_306DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_MC0306D3" + Value = "1" + Help = "Intel(R) Broadwell Processor D-0" + TokenType = Boolean + Token = "MOBILE_306DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_MC0306D4" + Value = "1" + Help = "Intel(R) Broadwell Processor E-0,F-0" + TokenType = Boolean + Token = "MOBILE_306DX" "=" "1" +End + +TOKEN + Name = "MOBILE_M32306C3" + Value = "1" + Help = "Intel(R) Haswell C-0" + TokenType = Boolean + Token = "MOBILE_306CX" "=" "1" +End + +TOKEN + Name = "MOBILE_M7240650" + Value = "1" + Help = "Intel(R) Haswell ULT B-0" + TokenType = Boolean + Token = "MOBILE_4065X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M7240651" + Value = "1" + Help = "Intel(R) Haswell ULT C-0" + TokenType = Boolean + Token = "MOBILE_4065X" "=" "1" +End + +TOKEN + Name = "MOBILE_M3240660" + Value = "1" + Help = "Intel(R) Haswell Perf Halo Processor B-0 Stepping" + TokenType = Boolean + Token = "MOBILE_4066X" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "MOBILE_M3240661" + Value = "1" + Help = "Intel(R) Haswell Perf Halo Processor C-0 Stepping" + TokenType = Boolean + Token = "MOBILE_4066X" "=" "1" +End + +TOKEN + Name = "MOBILE_M2240671" + Value = "1" + Help = "Intel(R) Broadwell-H Processor G-0" + TokenType = Boolean + Token = "MOBILE_4067X" "=" "1" +End + +PATH + Name = "MICROCODE_MOBILE_DIR" +End + +ELINK + Name = "$(Intel_Mobile)" + Parent = "MICROCODE_FILES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M1320650_FFFF0008.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Arrandale Processor" + Token = "MOBILE_M1320650" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M1320651_FFFF000F.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Arrandale Processor C0 Stepping" + Token = "MOBILE_M1320651" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M1220652_0000000F.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Arrandale Processor C-2 Stepping" + Token = "MOBILE_M1220652" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M9220655_00000005.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Arrandale Processor K-0 Stepping" + Token = "MOBILE_M9220655" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M13106F1_FFFF0007.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Auburndale Processor" + Token = "MOBILE_M13106F1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M13106E5_00000008.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Clarksfield Processor B-1" + Token = "MOBILE_M13106E5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M13106E3_FFFF0006.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Clarksfield Processor" + Token = "MOBILE_M13106E3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A0_00000024.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge A0" + Token = "MOBILE_M12206A0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A2_00000026.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge B2" + Token = "MOBILE_M12206A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A3_00000008.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge C0, P0" + Token = "MOBILE_M12206A3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A5_00000007.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge D0" + Token = "MOBILE_M12206A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A6_00000028.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge D-1" + Token = "MOBILE_M12206A6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12206A7_00000029.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Sandy Bridge D-2, J-1" + Token = "MOBILE_M12206A7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A2_00000008.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge B-0" + Token = "MOBILE_M12306A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A4_00000007.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge C-0" + Token = "MOBILE_M12306A4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A5_00000007.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge K-0" + Token = "MOBILE_M12306A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A8_00000010.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge E-0 and L-0" + Token = "MOBILE_M12306A8" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M12306A9_0000001C.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Ivy Bridge E-1, L-1, and N-0" + Token = "MOBILE_M12306A9" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M32306C1_FFFF0013.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell Processor A-0" + Token = "MOBILE_M32306C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M32306C2_FFFF0006.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell Processor B-0" + Token = "MOBILE_M32306C2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M32306C3_00000022.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell C-0" + Token = "MOBILE_M32306C3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M7240650_FFFF000B.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell ULT Processor B-0 Stepping" + Token = "MOBILE_M7240650" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M7240651_00000020.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell ULT C-0, D-0" + Token = "MOBILE_M7240651" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M3240660_FFFF0011.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell Perf Halo Processor B-0 Stepping" + Token = "MOBILE_M3240660" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M3240661_00000017.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Haswell Perf Halo Processor C-0 Stepping" + Token = "MOBILE_M3240661" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\MF2306D2_FFFF0009.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Broadwell C-0" + Token = "MOBILE_MF2306D2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\MC0306D3_FFFF0010.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Broadwell D-0" + Token = "MOBILE_MC0306D3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\MC0306D4_00000025.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Broadwell E-0,F-0" + Token = "MOBILE_MC0306D4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_MOBILE_DIR)\M2240671_00000017.PDB" + Parent = "$(Intel_Mobile)" + Help = "Intel(R) Broadwell-H Processor G-0" + Token = "MOBILE_M2240671" "=" "1" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/Board/CPU/Microcode/MOBILE/Mobile.CIF b/Board/CPU/Microcode/MOBILE/Mobile.CIF new file mode 100644 index 0000000..4dd59cf --- /dev/null +++ b/Board/CPU/Microcode/MOBILE/Mobile.CIF @@ -0,0 +1,41 @@ +<COMPONENT> + Name = "Mobile CPU uCode Patches" + Category = MODULEPART + RefName = "INTEL_MOBILE" + LocalRoot = "Board\CPU\Microcode\MOBILE" + +[PROPERTIES] + +[FILES] + "MOBILE.SDL" = "SDL FILES" + "M13106F1_FFFF0007.PDB" = "MOBILE MICROCODE UPDATES" + "M13106E5_00000008.PDB" = "MOBILE MICROCODE UPDATES" + "M13106E3_FFFF0006.PDB" = "MOBILE MICROCODE UPDATES" + "M1320650_FFFF0008.PDB" = "MOBILE MICROCODE UPDATES" + "M1320651_FFFF000F.PDB" = "MOBILE MICROCODE UPDATES" + "M1220652_0000000F.PDB" = "MOBILE MICROCODE UPDATES" + "M9220655_00000005.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A1_00000005.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A0_00000024.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A2_00000026.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A3_00000008.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A5_00000007.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A6_00000028.PDB" = "MOBILE MICROCODE UPDATES" + "M12206A7_00000029.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A2_00000008.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A4_00000007.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A5_00000007.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A8_00000010.PDB" = "MOBILE MICROCODE UPDATES" + "M12306A9_0000001C.PDB" = "MOBILE MICROCODE UPDATES" + "M32306C1_FFFF0013.PDB" = "MOBILE MICROCODE UPDATES" + "M32306C2_FFFF0006.PDB" = "MOBILE MICROCODE UPDATES" + "M32306C3_00000022.PDB" = "MOBILE MICROCODE UPDATES" + "MF2306D2_FFFF0009.PDB" = "MOBILE MICROCODE UPDATES" + "MC0306D3_FFFF0010.PDB" = "MOBILE MICROCODE UPDATES" + "MC0306D4_00000025.PDB" = "MOBILE MICROCODE UPDATES" + "M7240650_FFFF000B.PDB" = "MOBILE MICROCODE UPDATES" + "M7240651_00000020.PDB" = "MOBILE MICROCODE UPDATES" + "M3240660_FFFF0011.PDB" = "MOBILE MICROCODE UPDATES" + "M3240661_00000017.PDB" = "MOBILE MICROCODE UPDATES" + "M2240671_00000017.PDB" = "MOBILE MICROCODE UPDATES" +<ENDCOMPONENT> diff --git a/Board/CPU/Microcode/MPDTable.asm b/Board/CPU/Microcode/MPDTable.asm new file mode 100644 index 0000000..42bbef1 --- /dev/null +++ b/Board/CPU/Microcode/MPDTable.asm @@ -0,0 +1,16 @@ +include token.equ + +ifndef EFIx64 +.model small +endif + +.data + db 'MPDT' ;Microcode Patch Description Table + db 0 ;Revision + db 0 ;[0] = 0 Non boot block, [0] = 1 boot block + db 0 ;CPU Manufacture: 0 = Intel + db 0 ;Reserved + dd MKF_MICROCODE_ALIGNMENT ;Alignment - Include token .equ + dw 0 ;Reserved + dw 16 ;size of Table +END
\ No newline at end of file diff --git a/Board/CPU/Microcode/MPDTableBB.asm b/Board/CPU/Microcode/MPDTableBB.asm new file mode 100644 index 0000000..f143f6e --- /dev/null +++ b/Board/CPU/Microcode/MPDTableBB.asm @@ -0,0 +1,16 @@ +include token.equ + +ifndef EFIx64 +.model small +endif + +.data + db 'MPDT' ;Microcode Patch Description Table + db 0 ;Revision + db 1 ;[0] = 0 Non boot block, [0] = 1 boot block + db 0 ;CPU Manufacture: 0 = Intel + db 0 ;Reserved + dd MKF_MICROCODE_ALIGNMENT ;Alignment - Include token .equ + dw 0 ;Reserved + dw 16 ;size of Table +END
\ No newline at end of file diff --git a/Board/CPU/Microcode/Microcode.cif b/Board/CPU/Microcode/Microcode.cif new file mode 100644 index 0000000..c2975a4 --- /dev/null +++ b/Board/CPU/Microcode/Microcode.cif @@ -0,0 +1,15 @@ +<component> + name = "Intel Nehalem Microcode" + category = eModule + LocalRoot = "Board\CPU\Microcode\" + RefName = "Intel_Nehalem_Microcode" +[files] +"Microcode.sdl" +"Microcode.mak" +"MPDTable.asm" +"MPDTableBB.asm" +[parts] +"INTEL_MOBILE" +"INTEL_DESKTOP" +"INTEL_SERVWORK" +<endComponent> diff --git a/Board/CPU/Microcode/Microcode.mak b/Board/CPU/Microcode/Microcode.mak new file mode 100644 index 0000000..a9fd4a7 --- /dev/null +++ b/Board/CPU/Microcode/Microcode.mak @@ -0,0 +1,195 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/Microcode.mak 5 12/20/11 2:43p Markw $ +# +# $Revision: 5 $ +# +# $Date: 12/20/11 2:43p $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/Microcode.mak $ +# +# 5 12/20/11 2:43p Markw +# [TAG] EIPNone +# [Category] Improvement +# [Description] Don't build MPDT binary when SDL token MPDTable_CREATED +# is disable. +# Type binary is not supported by 4.6.3 and earlier, and most projects if +# any using 4.6.3 don't support MPDT. +# [Files] Microcode.mak +# +# 4 7/28/11 5:20p Markw +# [TAG] EIP65726 +# [Category] Improvement +# [Description] Support MPDT - Microcode Patch Description Table. This +# table provides a header for AMI utilities. +# +# [Files] Microcode.cif, Microcode.sdl, Microcode.mak, MPDTable.asm, +# MPDTableBB.asm, Startup32.asm, CpuCspLib.c , MicrocodeUpdate.c +# +# 3 8/27/10 10:49a Markw +# Update microcode to support pack microcode without padding, and support +# microcode in the bootblock and updates in main FV. +# +# 2 6/15/10 1:45p Markw +# Update the microcode.bin path in the build process. +# +# 1 9/29/09 2:51p Markw +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: MicroCode.mak +# +# Description: Build the microcode file. +# +#<AMI_FHDR_END> +#********************************************************************** + +MICROCODE_BUILD_DIR = $(BUILD_DIR)\$(MICROCODE_DIR) + +all : MICROCODE + +MICROCODE : MICROCODE_CREATE_BUILD_DIR $(BUILD_DIR)\Microcode.ffs \ +!if "$(MICROCODE_SPLIT_BB_UPDATE)"=="1" + $(BUILD_DIR)\Microcode_Blank.ffs +!ENDIF + + + +$(BUILD_DIR)\Microcode.mak : $(MICROCODE_DIR)\Microcode.mak $(MICROCODE_DIR)\Microcode.cif $(BUILD_RULES) + $(CIF2MAK) $(MICROCODE_DIR)\Microcode.cif $(CIF2MAK_DEFAULTS) + + +$(BUILD_DIR)\MPDTable.bin : $(MICROCODE_DIR)\MPDTable.asm $(BUILD_DIR)\Microcode.mak + $(MAKE) /$(MAKEFLAGS)\ + /f $(BUILD_DIR)\Microcode.mak bin\ + OBJECTS=$(BUILD_DIR)\$(MICROCODE_DIR)\MPDTable.obj\ + NAME=MPDTable\ + MAKEFILE=$(BUILD_DIR)\Microcode.mak \ + TYPE=BINARY + +$(BUILD_DIR)\MPDTableBB.bin : $(MICROCODE_DIR)\MPDTableBB.asm $(BUILD_DIR)\Microcode.mak + $(MAKE) /$(MAKEFLAGS)\ + /f $(BUILD_DIR)\Microcode.mak bin\ + OBJECTS=$(BUILD_DIR)\$(MICROCODE_DIR)\MPDTableBB.obj\ + NAME=MPDTableBB\ + MAKEFILE=$(BUILD_DIR)\Microcode.mak \ + TYPE=BINARY + +MICROCODE_GUID = 17088572-377F-44ef-8F4E-B09FFF46A070 + +MICROCODE_CREATE_BUILD_DIR: + if not exist $(MICROCODE_BUILD_DIR) md $(MICROCODE_BUILD_DIR) + +$(MICROCODE_BUILD_DIR)\Microcode.bin : $(MICROCODE_DIR)\Microcode.mak $(BUILD_DIR)\token.mak \ +!IF "$(MPDTable_CREATED)"=="1" + $(BUILD_DIR)\MPDTable.bin $(BUILD_DIR)\MPDTableBB.bin +!ELSE + #BLANK line for line continuation. +!ENDIF + copy << $(BUILD_DIR)\Microcode.ini +output + MICROCODE_FILES($(MICROCODE_BUILD_DIR)\Microcode.bin) +end +group MICROCODE_FILES + upper=0xffffffff +components +!IF "$(MPDTable_CREATED)"=="1" +!IF "$(MICROCODE_SPLIT_BB_UPDATE)"=="0" + file $(BUILD_DIR)\MPDTable.bin binfile=$(BUILD_DIR)\MPDTable.bin end +!ELSE + file $(BUILD_DIR)\MPDTableBB.bin binfile=$(BUILD_DIR)\MPDTableBB.bin end +!ENDIF +!ENDIF + +!IF "$(MICROCODE_SPLIT_BB_UPDATE)"=="0" +blank MICROCODE_PAD + size=$(MICROCODE_PAD_SIZE) +!IF "$(FLASH_ERASE_POLARITY)"=="0" + pattern=(0) +!ELSE + pattern=(0xFF) +!ENDIF +end +!ENDIF +<<KEEP + + for %%F IN ($(MICROCODE_FILES)) DO \ + echo file %%F binfile=%%F align=$(MICROCODE_ALIGNMENT) end >> $(BUILD_DIR)\Microcode.ini + echo end end >> $(BUILD_DIR)\Microcode.ini + $(MERGE) /s $(BUILD_DIR)\Microcode.ini + +$(BUILD_DIR)\Microcode.ffs : $(MICROCODE_BUILD_DIR)\microcode.bin + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=17088572-377F-44ef-8F4E-B09FFF46A070\ + TYPE=EFI_FV_FILETYPE_RAW \ + FFS_ALIGNMENT=1 FFS_CHECKSUM=1\ + RAWFILE=$** FFSFILE=$@ COMPRESS=0 NAME=$(**B) + +!if "$(MICROCODE_SPLIT_BB_UPDATE)"=="1" +$(MICROCODE_BUILD_DIR)\Microcode_Blank.bin : $(MICROCODE_DIR)\Microcode.mak $(BUILD_DIR)\token.mak + copy << $(BUILD_DIR)\Microcode_Blank.ini +output + MICROCODE_EMPTY($(MICROCODE_BUILD_DIR)\Microcode_Blank.bin) +end +group MICROCODE_EMPTY + upper=0xffffffff + +components + +!IF "$(MPDTable_CREATED)"=="1" + file $(BUILD_DIR)\MPDTable.bin binfile=$(BUILD_DIR)\MPDTable.bin end +!ENDIF + +blank MICROCODE_PAD + size=$(MICROCODE_PAD_SIZE) +!IF "$(FLASH_ERASE_POLARITY)"=="0" + pattern=(0) +!ELSE + pattern=(0xFF) +!ENDIF +end +end +end +<<KEEP + $(MERGE) /s $(BUILD_DIR)\Microcode_Blank.ini + + +$(BUILD_DIR)\Microcode_Blank.ffs : $(MICROCODE_BUILD_DIR)\Microcode_Blank.bin + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=17088572-377F-44ef-8F4E-B09FFF46A070\ + TYPE=EFI_FV_FILETYPE_RAW \ + FFS_ALIGNMENT=1 FFS_CHECKSUM=0 \ + RAWFILE=$** FFSFILE=$@ COMPRESS=0 NAME=$(**B) +!ENDIF + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2010, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/CPU/Microcode/Microcode.sdl b/Board/CPU/Microcode/Microcode.sdl new file mode 100644 index 0000000..5744c34 --- /dev/null +++ b/Board/CPU/Microcode/Microcode.sdl @@ -0,0 +1,150 @@ +TOKEN + Name = "Microcode_SUPPORT" + Value = "1" + Help = "Main switch to enable Microcode support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "NON_PRODUCTION_MICROCODE" + Value = "0" + Help = "Enable Non-production Microcode" + TokenType = Boolean +End + +TOKEN + Name = "MICROCODE_SPLIT_BB_UPDATE" + Value = "0" + Help = "If enabled, \ a) Microcode added at build time is stored in boot block.\ b) Microcode updates by INT15h are stored in the main firmware volume.\If disabled, all microcode is in the main firmware volume.\\If enabled, microcode is more fault tolerant, but requires more flash space.\" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes +End + + +TOKEN + Name = "MICROCODE_PAD_SIZE" + Value = "0x2000" + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "0" +End + +TOKEN + Name = "MICROCODE_PAD_SIZE" + Value = "0x5000" + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "1" +End + +TOKEN + Name = "MICROCODE_BLOCK_SIZE" + Value = "2048" + Help = "Do not change. This matches the INT15h Microcode update." + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "PACK_MICROCODE" + Value = "1" + Help = "This packs the microcode with no gaps.\If Split microcode is disabled, it is recommended for this to be disabled\for compatibility with earlier CPU modules.\The CPU module must support this. " + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "1" +End + +TOKEN + Name = "MICROCODE_ALIGNMENT" + Value = "$(MICROCODE_BLOCK_SIZE)" + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes +End + +TOKEN + Name = "MICROCODE_ALIGNMENT" + Value = "16" + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "1" +End + +TOKEN + Name = "FV_MICROCODE_BASE" + Value = "$(FV_MAIN_BASE)" + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "0" +End + +TOKEN + Name = "FV_MICROCODE_BASE" + Value = "$(FV_BB_BASE)" + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "1" +End + +TOKEN + Name = "FV_MICROCODE_UPDATE_BASE" + Value = "$(FV_MAIN_BASE)" + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "1" +End + +PATH + Name = "MICROCODE_DIR" +End + +MODULE + Help = "Includes Microcode.mak to Project" + File = "Microcode.mak" +End + +ELINK + Name = "MICROCODE_FILES" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "$(BUILD_DIR)\Microcode.ffs" + Parent = "FV_MAIN" + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "0" + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(BUILD_DIR)\Microcode.ffs" + Parent = "FV_BB" + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "1" + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(BUILD_DIR)\Microcode_Blank.ffs" + Parent = "FV_MAIN" + Token = "MICROCODE_SPLIT_BB_UPDATE" "=" "1" + InvokeOrder = BeforeParent +End + diff --git a/Board/CPU/Microcode/ServWork/M03106A2_FFFF0019.PDB b/Board/CPU/Microcode/ServWork/M03106A2_FFFF0019.PDB Binary files differnew file mode 100644 index 0000000..863eb45 --- /dev/null +++ b/Board/CPU/Microcode/ServWork/M03106A2_FFFF0019.PDB diff --git a/Board/CPU/Microcode/ServWork/M03106A4_00000011.PDB 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0000000..41b2d07 --- /dev/null +++ b/Board/CPU/Microcode/ServWork/MED306E6_00000600.PDB diff --git a/Board/CPU/Microcode/ServWork/MED306E7_0000070D.PDB b/Board/CPU/Microcode/ServWork/MED306E7_0000070D.PDB Binary files differnew file mode 100644 index 0000000..197d1a9 --- /dev/null +++ b/Board/CPU/Microcode/ServWork/MED306E7_0000070D.PDB diff --git a/Board/CPU/Microcode/ServWork/ServWork.CIF b/Board/CPU/Microcode/ServWork/ServWork.CIF new file mode 100644 index 0000000..b0dd960 --- /dev/null +++ b/Board/CPU/Microcode/ServWork/ServWork.CIF @@ -0,0 +1,42 @@ +<component> + name = "Server/Workstation CPU uCode Patches" + category = ModulePart + LocalRoot = "Board\CPU\Microcode\ServWork" + RefName = "INTEL_SERVWORK" +[files] +"ServWork.SDL" = "SDL FILES" +"M03106A2_FFFF0019.PDB" = "ServerWork Station Microcode Updates" +"M03106A4_00000011.PDB" = "ServerWork Station Microcode Updates" +"M03106A5_0000001B.PDB" = "ServerWork Station Microcode Updates" +"M13106E5_00000008.PDB" = "ServerWork Station Microcode Updates" +"M1220652_0000000F.PDB" = "ServerWork Station Microcode Updates" +"M12206A7_00000029.PDB" = "ServerWork Station Microcode Updates" +"M13206C0_FFFF0016.PDB" = "ServerWork Station Microcode Updates" +"M03206C1_00000006.PDB" = "ServerWork Station Microcode Updates" +"M03206C2_0000001D.PDB" = "ServerWork Station Microcode Updates" +"M07206D0_80000006.PDB" = "ServerWork Station Microcode Updates" +"M07206D1_80000106.PDB" = "ServerWork Station Microcode Updates" +"M0F206D2_8000020C.PDB" = "ServerWork Station Microcode Updates" +"M0F206D3_80000304.PDB" = "ServerWork Station Microcode Updates" +"M6D206D5_00000513.PDB" = "ServerWork Station Microcode Updates" +"M6D206D6_00000619.PDB" = "ServerWork Station Microcode Updates" +"M6D206D7_00000710.PDB" = "ServerWork Station Microcode Updates" +"M05206E0_FFFF0005.PDB" = "ServerWork Station Microcode Updates" +"M05206E1_FFFF0006.PDB" = "ServerWork Station Microcode Updates" +"M05206E2_FFFF0004.PDB" = "ServerWork Station Microcode Updates" +"M05206E3_FFFF000C.PDB" = "ServerWork Station Microcode Updates" +"M05206E5_FFFF0016.PDB" = "ServerWork Station Microcode Updates" +"M04206E6_0000000B.PDB" = "ServerWork Station Microcode Updates" +"M05206F0_FFFF0013.PDB" = "ServerWork Station Microcode Updates" +"M05206F1_00000008.PDB" = "ServerWork Station Microcode Updates" +"M05206F2_00000039.PDB" = "ServerWork Station Microcode Updates" +"M12306A9_0000001C.PDB" = "ServerWork Station Microcode Updates" +"M32306C1_FFFF000D.PDB" = "ServerWork Station Microcode Updates" +"M32306C3_0000001D.PDB" = "ServerWork Station Microcode Updates" +"MED306E0_00000008.PDB" = "ServerWork Station Microcode Updates" +"MED306E2_0000020D.PDB" = "ServerWork Station Microcode Updates" +"MED306E3_00000308.PDB" = "ServerWork Station Microcode Updates" +"MED306E4_00000428.PDB" = "ServerWork Station Microcode Updates" +"MED306E6_00000600.PDB" = "ServerWork Station Microcode Updates" +"MED306E7_0000070D.PDB" = "ServerWork Station Microcode Updates" +<endComponent> diff --git a/Board/CPU/Microcode/ServWork/ServWork.SDL b/Board/CPU/Microcode/ServWork/ServWork.SDL new file mode 100644 index 0000000..9ab793b --- /dev/null +++ b/Board/CPU/Microcode/ServWork/ServWork.SDL @@ -0,0 +1,1075 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30071 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +#**************************************************************************** +# $Header: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/SERVWORK/ServWork.SDL 112 8/14/15 5:28p Artems $ +# +# $Revision: 112 $ +# +# $Date: 8/14/15 5:28p $ +# +#**************************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/CPU/Intel/NehalemMicrocode/SERVWORK/ServWork.SDL $ +# +# 112 8/14/15 5:28p Artems +# [TAG] EIP233803 +# [Description] Updated Westmere -EX Processor A-2 Stepping version 39 +# Updated Westmere -EP -WS1S Processor B-1 Stepping version 1D +# Updated Nehalem -EX Processor D-0 Stepping version 0B +# Updated Clarkdale Xeon Processor C-2 Stepping version 0F +# [Files] ServWork.SDL +# ServWork.CIF +# +# 111 8/05/15 12:07p Artems +# [TAG] EIP231326 +# [Description] Updated Westmere -EP -WS1S Processor B-1 Stepping +# version 1C +# Updated Nehalem -EP -WS1S Processor D-0 Stepping version 1B +# Updated Lynnfield Xeon Processor B-1 Stepping version 08 +# [Files] ServWork.SDL +# ServWork.CIF +# +# 110 3/17/15 5:36p Artems +# Updated IvyBridge Processor E-1, L-1 Stepping version 1C +# +# 109 1/12/15 6:24p Artems +# Server +# Updated Haswell processor( 306CX) C-0 stepping to version 1D +# +# 108 7/21/14 3:07p Craigv +# Updated Haswell C-0 (306C3) to version 1C. +# +# 107 6/23/14 1:13p Craigv +# Updated Haswell C-0 (306C3) to version 1A. +# Updated Ivy Bridge E-1, L-1 (306A9) to version 1B. +# Updated Ivy Bridge M-1, S-1 (306E4) to version 428. +# Updated Ivy Bridge EX D-1 (306E7) to version 70D. +# +# 106 5/29/14 12:37p Craigv +# Updated Haswell C-0 (306C3) to version 19. +# Updated Ivy Bridge -EX D-1 (306E7) to version 70C. +# Updated IvyBridge -EX -EP -EN C-0, C-1, S-0, S-1, M-0, M-1 to version +# 427 +# +# 105 2/17/14 9:53a Craigv +# Updated IvyBridge EX (306E7) to version 00000709. +# +# 104 1/30/14 1:47p Craigv +# Updated Ivy Bridge-EP (306E4) to Production. +# Updated Ivy Bridge-EN (306E7) to Production. +# +# 103 1/10/14 3:09p Craigv +# Updated Intel Ivy Bridge -EX -EP =EN C-0, C-1, S-0, S-1, M-0, M-1 +# (306E4) to version 00000424. +# +# 102 10/23/13 10:20a Mithunraghavs +# The microcode update MED306E7_00000704.TXT for the Ivy Bridge-EX +# processor (Ivy Bridge-EX), Family 6 Model 3E Step 7 (D-1) has been +# updated from version 00000703 to 00000704 +# +# 101 10/14/13 6:11p Craigv +# Updated Haswell Processor C-0 (306C3) to version 00000017. +# +# 100 10/01/13 3:39p Craigv +# Updated Ivy Bridge -EX -EP -EN Processor C-0, C-1, S-0, S-1, M-0, M-1 +# to version 00000417 +# +# 99 9/13/13 4:56p Markw +# Updated Intel IvyBridge Processor -EX (306E7) D-1 version 700. +# Updated Intel Lynnfield Xeon B-1 (106E5) to version 7. +# +# 98 8/27/13 11:37a Markw +# Remove non production from 306C3. +# +# 97 8/26/13 1:47p Craigv +# Updated Intel Haswell C-0 (306C3) to version 00000016. +# +# 96 8/01/13 3:57p Craigv +# Added Intel IvyBridge Processor -EX (306E7) D-1 version 00000700. +# +# 95 7/18/13 4:27p Craigv +# Updated Intel(R) Ivy Bridge -EX -EP -EN Processor C-0, C-1, S-0, S-1, +# M-0, M-1 (306E4) to version 00000416. +# +# 94 7/18/13 3:54p Craigv +# Updated Intel Haswell C-0 (306C3) to version 00000012. +# +# 93 7/15/13 7:28p Markw +# Fix Production for 106A5. +# +# 92 7/15/13 12:29p Craigv +# Updated Intel Nehalem EP D-0 (106A5) to version 00000019. +# Updated Intel Lynnfield Xeon B-1 (106E5) to version 00000006. +# Updated Intel Clarkdale Xeon C-2 (20652) to version 0000000E. +# +# 91 7/12/13 5:46p Craigv +# Added Intel(R) Ivy Bridge -EX Processor D-0 Stepping (306E6) version +# 00000600. +# +# 90 7/03/13 11:17p Markw +# Add check-in 88 changes. +# +# 89 7/02/13 1:38p Craigv +# Updated Westmere WS 1S -EP (206C2) to version 0000001A. +# Updated Haswell C-0 (306C3) to version 00000010. +# +# 88 6/27/13 11:44a Markw +# Add TOKEN for SERVWORK_306AX. +# +# 87 6/26/13 7:58p Craigv +# Updated Sandy Bridge (206A7) D-2 to version 00000029. +# Updated Sandy Bridge -EN -EP (206D7) C-2 to version 00000710. +# Updated Westmere -EX (206F2) A-2 to version 00000037. +# Updated Nehalem -EX (206E6) D-0 to version 0000000A. +# Added Ivy Bridge (306A9) E-1, L-1 to version 00000019. +# +# 86 6/21/13 11:23a Craigv +# Updated Ivy Bridge -EX -EP -EN (306E4) C-0, C-1, S-0, S-1, M-0, M-1 to +# version 415. +# +# 85 6/13/13 3:52p Craigv +# Updated Intel Ivy Bridge -EP (306E4) C-0, C-1, M-0, S-0 to version 413. +# +# 84 5/30/13 5:21p Craigv +# Updated Ivy Bridge (306E4) C-0, S-0, M-0 to version 410. +# +# 83 5/30/13 4:43p Craigv +# Update Intel Ivy Bridge -EX Processor (306E4) C-0 to version 40F. +# +# 81 5/20/13 4:21p Craigv +# Added Intel Haswell Processor C-0 (306C3) version 0009. +# +# 80 5/10/13 11:06a Craigv +# Update IvyBridge C-0 (306E4) -EP-EX to version 40D. +# +# 79 4/17/13 5:37p Craigv +# Updated Ivy Bridge (306E4) help string to include -EX processors. +# +# 78 4/05/13 2:50p Craigv +# Update Ivy Bridge-EX -EP -EN Processor B-1, B-2, L-1, L-2, R-0, and R-1 +# (306E2) to version 20D. +# Updated Ivy Bridge-EP -EX Processor (306E3) B-3 to version 308. +# Updated Ivy Bridge-EP processor C-0 (306E4) Stepping Version 40C. +# +# 77 3/25/13 7:01p Craigv +# Updated Ivy Bridge-EP -EX Processor (306E3) B-3 to version 307. +# +# 76 3/21/13 3:22p Craigv +# Added Ivy Bridge-EP processor C-0 Stepping Version 40B. +# +# 75 1/25/13 4:05p Markw +# Update Ivy Bridge-EX -EP B-1, B-2, and L-1 (306E2) to version 20C. +# Update Ivy Bridge-EX -EP B-3 (306E3 to version 306. +# +# 74 12/04/12 11:27a Craigv +# Added Ivy Bridge-EX -EP processor B-1 and L-1 Stepping version +# 00000209. +# +# 73 10/30/12 3:58p Craigv +# Added Ivy Bridge-EX -EP processor B-1 and L-1 Stepping version 00000208 +# +# 72 8/15/12 11:08a Craigv +# Fix for Intel(R) Ivytown A-0 re-added. +# +# 71 8/08/12 12:18p Craigv +# Update IvyTown Processor A-0 (306E0) to version 00000008. +# +# 70 7/09/12 10:05a Markw +# Fix Intel(R) IvyTown Processor A-0 Stepping tokens. +# +# 69 7/06/12 5:25p Craigv +# Added IvyTown processor A-0 Stepping version 00000005. +# +# 68 6/18/12 1:57p Markw +# Update Sandybridge-EP C-1, M-0 (206d6) to version 619. +# Update Sandybridge-EP C-2, M-1 (206d7) to version 70D. +# +# 67 5/22/12 5:23p Craigv +# Update Sandy Bridge D-2 and Q-0 (206A7) to version 28. +# Update Sandy Bridge-E C-2, M-1 (206D7) to version 70C. +# +# 66 4/24/12 10:41a Markw +# Add NON_PRODUCTION_MICROCODE dependency to Haswell A-0. +# +# 65 4/23/12 10:55a Craigv +# Added Haswell processor A-0 Stepping version FFFF000D +# +# 64 4/19/12 11:08a Craigv +# Update Westmere-EX A-2 (206F2) to Version 36. +# Update Westmere EP D0 (206E6) to version 9. +# +# 63 3/19/12 2:26p Craigv +# Update Sandybridge-EP C-1, M-0 (206d6) to version 616. +# Update Sandybridge-EP C-2, M-1 (206d7) to version 70B. +# +# 62 2/14/12 12:35p Craigv +# Update Sandybridge-EP C-1, M-0 (206d6) to version 615. +# Update Sandybridge-EP C-2, M-1 (206d7) to version 70A. +# +# 61 1/31/12 4:20p Markw +# Update Sandybridge-EP C-1, M-0 (206d6) to version 613. +# Update Sandybridge-EP C-2, M-1 (206d7) to version 708. +# +# 60 1/20/12 11:07a Markw +# Update help strings for Sandy Bridge. C-1 microcode is also for M-0, +# and C-2 microcode is also for M-1. +# +# 59 12/23/11 1:12p Markw +# Update Sandybridge-EP C-1 (206d6) to version 610. +# Update Sandybridge-EP C-2 (206d7) to version 705. +# +# 58 12/07/11 10:41a Markw +# Fix SERVWORK_206AX. Default should be off. +# +# 57 12/06/11 3:19p Markw +# Update Sandybridge-EP C-1 (206d6) to version 60F. +# Update Sandybridge-EP C-2 (206d7) to version 704. +# Update Lynnfield B-1 (106e5) to version 5. +# +# 56 11/14/11 4:18p Markw +# Update Sandybridge D-2 (206A7) to version 25. +# +# 55 11/02/11 12:41p Markw +# Update Sandybridge-EP C-0 (206d5) to version 513. +# Update Sandybridge-EP C-1 (206d6) to version 60D. +# +# 54 10/26/11 11:38a Markw +# Update Westmere-EP B-1 (206C2) to Version 15. +# Update Clarkdale Xeon C-2 (20652) to Version 0D. +# Update Westmere-EX A-2 (206F2) to Version 34. +# +# +# 53 10/11/11 4:11p Markw +# Update Sandybridge-EP C-0 (206d5) to version 512. +# Update Sandybridge-EP C-1 (206d6) to version 60C. +# +# 52 9/22/11 2:23p Markw +# Update Sandybridge-EP C-0 (206d5) to version 511. +# Update Sandybridge-EP C-1 (206d6) to version 60B. +# +# 51 9/08/11 1:05p Markw +# Update Sandybridge-EP C-1 (206d6) to version 606. +# +# 50 8/29/11 3:00p Markw +# Update Sandybridge-EP C-0 (206d5) to version 50D. +# +# 49 8/10/11 7:01p Markw +# Update Sandybridge-EP C-0 (206d5) to version 50B. +# +# 48 8/09/11 10:24a Markw +# Update Westmere-EX A-2 (206F2) to version 32. +# Update Sandybridge-EP C-0 (206d5) to version 50A. +# +# 47 8/04/11 1:14p Markw +# Update Nehalem-EP D- 0 (106A5 to version 16. +# Update Sandybridge-EP C-0 (206d5) to version 509. +# Update Sandybridge-EP C-1 (206d6) to version 80000603. +# +# 46 7/13/11 11:27a Markw +# Update Sandybridge EP C0 (206d5) to version 00000508. +# +# 45 7/12/11 11:31a Markw +# Update Sandybridge EP C0 (206d5) to version 00000507. +# +# 44 7/12/11 11:10a Markw +# Update Sandybridge EP C0 (206d5) to version 80000507. +# +# 42 6/16/11 5:15p Markw +# Update Sandybridge EP C0 (206d5) to version 80000502. +# +# 41 6/13/11 5:50p Markw +# Update Westmere EP B1 (206C2) to Version 14. +# +# 40 6/03/11 12:30p Markw +# Update Westmere EX A-2 (206F2) to version 30. +# +# 39 5/12/11 5:32p Markw +# Update Sandybridge EP EN B-0 (206d2) to version 8000020C. +# +# 38 4/29/11 4:52p Markw +# Update Sandybridge EP EN B1 (206d3) to version 80000304. +# +# 37 4/01/11 11:57a Markw +# Update Sandybridge EP EN B0 (206d2) to version 8000020b. +# Update Sandybridge EP EN B1 (206d3) to version 80000302. +# +# 36 3/24/11 10:57a Markw +# Update Nehalem EP D0 (106A5) to version 15. +# +# 35 3/07/11 6:46p Markw +# Update Westmere EX A2 (206F2) to version 26. +# +# 34 3/03/11 3:45p Markw +# Update Sandy Bridge EN,EP, and EX B-0 (206D2) to Version 8000020A +# +# 33 2/14/11 11:57a Markw +# pdate Sandy Bridge EN,EP, and EX B-0 (206D2) to Version 80000206 +# +# 32 1/24/11 6:51p Markw +# Fix default SERVWORK_206DX. +# +# 31 1/24/11 6:50p Markw +# pdate Sandy Bridge EN,EP, and EX B-0 (206D2) to Version 80000206 +# +# 30 1/04/11 10:23a Markw +# Update Westmere EX A2 (206F2) to version 24. +# +# 29 12/14/10 4:47p Markw +# Update Sandy Bridge EN,EP, and EX A-1 (206D1) to Version 80000106. +# +# 28 11/22/10 9:11p Markw +# +# 27 11/22/10 9:07p Markw +# Update Sandy Bridge EP A-1 (206D1) to Version 80000105. +# +# 26 10/21/10 10:41a Markw +# Update Westmere EX A1 (206F1) to version 8. +# Update Westmere EX A2 (206F2) to version 22. +# +# 25 10/15/10 4:25p Markw +# Update Westmere EP D0 (206E6) to version 8. +# +# 24 10/14/10 3:21p Markw +# # 22 9/15/10 1:31p Markw +# Update Sandy Bridge EP 1a (206D1) to Version 80000103.. +# +# 23 9/15/10 2:29p Markw +# Update default token SERVWORK_206DX back to 0. +# +# 22 9/15/10 1:31p Markw +# Update Westmere EP B1 (206C2) to Version 13. +# +# 21 9/13/10 3:43p Markw +# Update SandyBridge EP A1 (206D1) to Version 80000101. +# +# 20 9/02/10 5:03p Markw +# Update Westmere EP B1 (206C2) to Version 10. +# Update SandyBridge EP A0 (206D0) to Version 80000006. +# +# 19 8/30/10 5:42p Markw +# Update Lynnfield B1 (106e5) and Westmere EX A1 (206f1). +# +# 18 8/19/10 10:49a Markw +# Fix build error for microcode Clarkdale 20652 and Westmere 206C2. +# +# 17 8/12/10 11:16a Markw +# +# 16 8/05/10 11:37a Markw +# Add +# Westmere-EX processor A0 Stepping version FFFF0013 +# +# 15 7/27/10 10:36a Hari +# Updated for Westmere EX A1 and clarksdale latest microcode +# +# 14 7/15/10 3:55p Bhimanadhunik +# +# 12 5/27/10 6:35p Markw +# Updated Nehalem-EX D0 to version 7 and Westmere-EX A0 to version +# 0xffff0010. +# +# 10 4/09/10 9:55a Markw +# Add M03206C2_0000000C.PDB +# +# 9 3/02/10 3:39p Markw +# Update Westmere EP B0 microcode to Rev A. +# Nehalem EX D0 to Rev 5. +# +# 8 1/19/10 11:17p Markw +# Add Westmere EP B-1 stepping. +# +# 7 1/19/10 11:03p Markw +# Add Westmere EP B0 Ver 6 +# +# 6 12/18/09 4:12p Markw +# Westmere-EP processor B1 +# +# 5 12/15/09 10:45p Markw +# Add Clarkdale Xeon C2 production and Nehalem EX D0 production. +# +# 4 11/17/09 2:39p Markw +# Added Nehalem EP B0 and Westmere EP B0. +# +# 3 11/05/09 5:32p Markw +# Nehalem EX D0 added. +# +# 2 10/16/09 10:27a Markw +# +# 1 9/29/09 2:51p Markw +# +#**************************************************************************** + +TOKEN + Name = "SERVWORK" + Value = "0" + Help = "Master Server/Workstation CPU uCode Enable" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Range = "On-Off" +End + +TOKEN + Name = "SERVWORK_306EX" + Value = "0" + Help = "Intel(R) IvyTown and Ivy Bridge-EP -EX" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_306CX" + Value = "0" + Help = "Intel(R) Haswell" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_206DX" + Value = "0" + Help = "Intel(R) SandyBridge-EN -EP and -EX processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_206AX" + Value = "0" + Help = "Intel(R) SandyBridge processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_306AX" + Value = "0" + Help = "Intel(R) IvyBridge processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_206FX" + Value = "0" + Help = "Intel(R) Westmere-EX processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_206EX" + Value = "0" + Help = "Intel(R) Nehalem-EX processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_2065X" + Value = "0" + Help = "Intel(R) Clarkdale Xeon processors" + TokenType = Boolean +End + + +TOKEN + Name = "SERVWORK_206CX" + Value = "0" + Help = "Intel(R) Westmere-EP processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_106AX" + Value = "0" + Help = "Intel(R) Nehalem-EP processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_106EX" + Value = "0" + Help = "Intel(R) Lynnfield processors" + TokenType = Boolean +End + +TOKEN + Name = "SERVWORK_M03106A2" + Value = "1" + Help = "Intel(R) Nehalem-EP processor B0 Stepping" + TokenType = Boolean + Token = "SERVWORK_106AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M03106A4" + Value = "1" + Help = "Intel(R) Nehalem-EP processor C0 Stepping" + TokenType = Boolean + Token = "SERVWORK_106AX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M03106A5" + Value = "1" + Help = "Intel(R) Nehalem-EP processor D0 Stepping" + TokenType = Boolean + Token = "SERVWORK_106AX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M1220652" + Value = "1" + Help = "Intel(R) Clarkdale Xeon processor C2 Stepping" + TokenType = Boolean + Token = "SERVWORK_2065X" "=" "1" +End + +TOKEN + Name = "SERVWORK_M13206C0" + Value = "1" + Help = "Intel(R) Westmere-EP processor A0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M03206C1" + Value = "1" + Help = "Intel(R) Westmere-EP processor B0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M03206C2" + Value = "1" + Help = "Intel(R) Westmere-EP and Westmere-WS 1S B1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206CX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E0" + Value = "1" + Help = "Intel(R) Nehalem-EX processor A1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E1" + Value = "1" + Help = "Intel(R) Nehalem-EX processor A2 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E2" + Value = "1" + Help = "Intel(R) Nehalem-EX processor" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E3" + Value = "1" + Help = "Intel(R) Nehalem-EX processor B0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206E5" + Value = "1" + Help = "Intel(R) Nehalem-EX processor C0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M04206E6" + Value = "1" + Help = "Intel(R) Nehalem-EX processor D0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206EX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M13106E5" + Value = "1" + Help = "Intel(R) Lynnfield Processor B1 Stepping" + TokenType = Boolean + Token = "SERVWORK_106EX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206F0" + Value = "1" + Help = "Intel(R) Westmere-EX Processor A0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206F1" + Value = "1" + Help = "Intel(R) Westmere-EX Processor A1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206FX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M05206F2" + Value = "1" + Help = "Intel(R) Westmere-EX Processor A2 Stepping" + TokenType = Boolean + Token = "SERVWORK_206FX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M07206D0" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor A0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M07206D1" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor A1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M0F206D2" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor B0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M0F206D3" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor B1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M6D206D5" + Value = "1" + Help = "Intel(R) SandyBridge-EP Processor C-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M6D206D6" + Value = "1" + Help = "Intel(R) SandyBridge-EP Processor C-1 and M-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M6D206D7" + Value = "1" + Help = "Intel(R) SandyBridge-EN -EP Processor C-2 and M-1 Stepping" + TokenType = Boolean + Token = "SERVWORK_206DX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M12206A7" + Value = "1" + Help = "Intel(R) SandyBridge Processor D-2 Stepping" + TokenType = Boolean + Token = "SERVWORK_206AX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M12306A9" + Value = "1" + Help = "Intel(R) Ivy Bridge Processor E-1, L-1 Stepping" + TokenType = Boolean + Token = "SERVWORK_306AX" "=" "1" +End + +TOKEN + Name = "SERVWORK_M32306C1" + Value = "1" + Help = "Intel(R) Haswell Processor A-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_306CX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_M32306C3" + Value = "1" + Help = "Intel(R) Haswell Processor C-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_306CX" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E0" + Value = "1" + Help = "Intel(R) IvyTown Processor A-0 Stepping" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E2" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP -EX Processor B-1, B-2, and L-1 Stepping" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E3" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP -EX Processor B-3" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E4" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP Processor C-0, M-0, S-0, C-1" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E6" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP Processor D-0" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" + Token = "NON_PRODUCTION_MICROCODE" "=" "1" +End + +TOKEN + Name = "SERVWORK_MED306E7" + Value = "1" + Help = "Intel(R) Ivy Bridge-EP Processor D-1" + TokenType = Boolean + Token = "SERVWORK_306EX" "=" "1" +End + +PATH + Name = "MICROCODE_SERVWORK_DIR" +End + +ELINK + Name = "$(Intel_ServWork)" + Parent = "MICROCODE_FILES" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03106A2_FFFF0019.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EP processor B0 Stepping" + Token = "SERVWORK_M03106A2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03106A4_00000011.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EP processor C0 Stepping" + Token = "SERVWORK_M03106A4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03106A5_0000001B.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EP processor D-0 & WS 1S Stepping" + Token = "SERVWORK_M03106A5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M1220652_0000000F.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Clarkdale Xeon processor C-2 Stepping" + Token = "SERVWORK_M1220652" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M13206C0_FFFF0016.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EP processor A0 Stepping" + Token = "SERVWORK_M13206C0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03206C1_00000006.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EP processor B0 Stepping" + Token = "SERVWORK_M03206C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M03206C2_0000001D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EP and Westmere-WS 1S B1 Stepping" + Token = "SERVWORK_M03206C2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E0_FFFF0005.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor A1 Stepping" + Token = "SERVWORK_M05206E0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E1_FFFF0006.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor A2 Stepping" + Token = "SERVWORK_M05206E1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E2_FFFF0004.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor" + Token = "SERVWORK_M05206E2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E3_FFFF000C.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor B0 Stepping" + Token = "SERVWORK_M05206E3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206E5_FFFF0016.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor C0 Stepping" + Token = "SERVWORK_M05206E5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M04206E6_0000000B.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Nehalem-EX processor D0 Stepping" + Token = "SERVWORK_M04206E6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206F0_FFFF0013.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EX processor A0 Stepping" + Token = "SERVWORK_M05206F0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206F1_00000008.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EX processor A1 Stepping" + Token = "SERVWORK_M05206F1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M05206F2_00000039.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Westmere-EX processor A2 Stepping" + Token = "SERVWORK_M05206F2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M13106E5_00000008.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Lynnfield Processor B-1 Stepping \CPU Signature 106E5" + Token = "SERVWORK_M13106E5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M12206A7_00000029.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge Processor D-2 Stepping" + Token = "SERVWORK_M12206A7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M12306A9_0000001C.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge Processor E-1, L-1 Stepping" + Token = "SERVWORK_M12306A9" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M07206D0_80000006.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge EP Processor A0 Stepping" + Token = "SERVWORK_M07206D0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M07206D1_80000106.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor A1 Stepping" + Token = "SERVWORK_M07206D1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M0F206D2_8000020C.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor B0 Stepping" + Token = "SERVWORK_M0F206D2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M0F206D3_80000304.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EN -EP and -EX Processor B1 Stepping" + Token = "SERVWORK_M0F206D3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M6D206D5_00000513.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EP Processor C-0 Stepping" + Token = "SERVWORK_M6D206D5" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M6D206D6_00000619.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EP Processor C-1 and M-0 Stepping" + Token = "SERVWORK_M6D206D6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M6D206D7_00000710.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) SandyBridge-EN -EP Processor C-2 and M-1 Stepping" + Token = "SERVWORK_M6D206D7" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M32306C1_FFFF000D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Haswell Processor A-0 Stepping" + Token = "SERVWORK_M32306C1" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\M32306C3_0000001D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Haswell Processor C-0 Stepping" + Token = "SERVWORK_M32306C3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E0_00000008.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) IvyTown Processor A-0 Stepping" + Token = "SERVWORK_MED306E0" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E2_0000020D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge-EP -EX -EN Processor B-1, B-2, L-1, L-2, R-0, and R-1 Stepping" + Token = "SERVWORK_MED306E2" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E3_00000308.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge-EP -EX Processor B-3 Stepping" + Token = "SERVWORK_MED306E3" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E4_00000428.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge -EX -EP -EN Processor C-0, C-1, S-0, S-1, M-0, M-1 Stepping" + Token = "SERVWORK_MED306E4" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E6_00000600.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge -EX Processor D-0 Stepping" + Token = "SERVWORK_MED306E6" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(MICROCODE_SERVWORK_DIR)\MED306E7_0000070D.PDB" + Parent = "$(Intel_ServWork)" + Help = "Intel(R) Ivy Bridge -EX Processor D-1 Stepping" + Token = "SERVWORK_MED306E7" "=" "1" + InvokeOrder = AfterParent +End
\ No newline at end of file diff --git a/Board/CPU/PlatformCpuLib.c b/Board/CPU/PlatformCpuLib.c new file mode 100644 index 0000000..66df0d5 --- /dev/null +++ b/Board/CPU/PlatformCpuLib.c @@ -0,0 +1,1046 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/PlatformCpuLib.c 7 4/10/15 2:37a Crystallee $ +// +// $Revision: 7 $ +// +// $Date: 4/10/15 2:37a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/PlatformCpuLib.c $ +// +// 7 4/10/15 2:37a Crystallee +// +// 6 7/23/13 7:41a Crystallee +// [TAG] EIP128089 +// [Category] Improvement +// [Description] TXT will be disabled and grayed out in Setup when TPM +// Support is disabled. +// +// 5 2/22/13 2:00a Crystallee +// [TAG] EIP112238 +// [Category] Improvement +// [Description] Refer Intel BIOS and provide setup items for Intel +// Haswell RC policy. +// +// 4 11/23/12 4:14a Davidhsieh +// [TAG] EIPNone +// [Category] Bug Fix +// [Severity] Minor +// [Symptom] Ctdp setup item is not displayed in setup menu +// [RootCause] The cTDPAvailable value is not initialzied +// [Solution] Initial cTDPAvailable value +// +// 3 10/17/12 2:23a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Setup items CTDP BIOS, C8, C9 and C10 created +// +// 2 3/16/12 3:35a Davidhsieh +// Setup items create for CPU RC policy +// +// 1 2/07/12 3:57a Davidhsieh +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// Name: PlatformCpuLib.c +// +// Description: Platform CPU Lib C source file +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <efi.h> +#include <Pei.h> +#include <Dxe.h> +#include <AmiLib.h> +#include <Setup.h> +#include <Ppi\ReadOnlyVariable.h> +#include <AmiCspLib.h> +#include "PlatformCpuLib.h" +#include "Cpu.h" + +static EFI_GUID gAmiSetupGuid = SETUP_GUID; +static EFI_GUID gEfiPeiReadOnlyVariablePpiGuid = EFI_PEI_READ_ONLY_VARIABLE_PPI_GUID; + +typedef struct { + SETUP_DATA *SetupData; +} PRIVATE_CPU_SETUP_LIB; + +//------------------------------------------------------------------------------- + +SETUP_CPU_FEATURES gSetupCpuFeatures; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformTpmDevicePresent +// +// Description: Set if Tpm device is present. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformTpmDevicePresent( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.TpmDeviceAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuCtdpSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuCtdpSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.cTDPAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuLimitCpuidSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuLimitCpuidSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.LimitCpuidAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuHtSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuHtSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.HTAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuMultiCoreSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuMultiCoreSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.MultiCoreAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuMultiSocketSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuMultiSocketSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.MultiSocketAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuMultiSocketPopulated +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Populated +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuMultiSocketPopulated( + IN VOID *Handle, + IN BOOLEAN Populated +) +{ + gSetupCpuFeatures.MultiSocketPopulated = Populated; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuXdSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuXdSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.XDBitAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuSmxSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuSmxSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.SmxAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuVtSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuVtSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.VTAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuLocalx2ApicSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuLocalx2ApicSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.LocalX2ApicAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuSocketSetPopulated +// +// Description: Set sockets populated. +// +// Input: +// IN VOID *Handle - Setup Handle +// IN UINT32 Socket - Socket (0-based) +// IN BOOLEAN Populated - TRUE if populated. Default: Not populated. +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuSocketSetPopulated( + IN VOID *Handle, + IN UINT32 Socket, + IN BOOLEAN Populated +) +{ + switch(Socket) { + case 0: gSetupCpuFeatures.Skt0Pop = TRUE; break; + case 1: gSetupCpuFeatures.Skt1Pop = TRUE; break; + case 2: gSetupCpuFeatures.Skt2Pop = TRUE; break; + case 3: gSetupCpuFeatures.Skt3Pop = TRUE; break; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuXeCoreRatioLimitSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuXeCoreRatioLimitSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.XECoreRatioLimitAvailable = Supported; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuCurrentLimitSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuCurrentLimitSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.CurrentLimitAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuPwrLimitConfigSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuPwrLimitConfigSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.PwrLimitAvailable = Supported; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuEistSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuEistSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.EistAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuTurboModeSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuTurboModeSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.TurboModeAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuPkgCStateDemotionSupport +// +// Description: Set if supported by platform. +// Available only in 4th Generation Intelr CoreT +// processors with signature greater than 000306C1h. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuPkgCStateDemotionSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.PkgCStateDemotionAvailable = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuC3Support +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuC3Support( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.C3Available = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuC6Support +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuC6Support( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.C6Available = Supported; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuC7Support +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuC7Support( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.C7Available = Supported; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuC8Support +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuC8Support( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.C8Available = Supported; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuC9Support +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuC9Support( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.C9Available = Supported; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuC10Support +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuC10Support( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.C10Available = Supported; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuAesSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuAesSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.AesAvailable = Supported; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuCurrentLimitSupport +// +// Description: Set if supported by platform. +// +// Input: +// IN VOID *Handle +// IN BOOLEAN Supported +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuTccActiveOffsetSupport( + IN VOID *Handle, + IN BOOLEAN Supported +) +{ + gSetupCpuFeatures.TccActivationAvailable = Supported; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PlatformCpuMismatch +// +// Description: Report is populated CPU combination is not supported. +// +// Input: +// IN VOID *Handle - Setup Handle +// IN BOOLEAN Mismatch - TRUE if CPU combination not supported. Default: Not populated. +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID PlatformCpuMismatch( + IN VOID *Handle, + IN BOOLEAN Mismatch +) +{ + gSetupCpuFeatures.CpuMismatch = Mismatch; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DxePlatformCpuSaveSupportedData +// +// Description: This functions saves the CPU supported data. +// +// Input: +// IN EFI_RUNTIME_SERVICES *Rs +// +// Output: EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS DxePlatformCpuSaveSupportedData( + IN EFI_RUNTIME_SERVICES *Rs +) +{ + return Rs->SetVariable( + L"SetupCpuFeatures", + &gAmiSetupGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof(SETUP_CPU_FEATURES), + &gSetupCpuFeatures + ); +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// Procedure: GetPlatformCpuGroup +// +// Description: Get the CPU group for the platform policy. +// +// Input: +// IN VOID *Handle +// +// Output: +// UINT32 Cpu Group +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 GetPlatformCpuGroup(IN VOID *Handle) { + UINT32 NumCores = NumSupportedCpuCores(); + + switch (NumCores) { + case 8: return 1; + case 4: return 2; + case 2: return 5; + default: return 2; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetPlatformNumCores +// +// Description: Get the maximum number of cores supported by processor. +// +// Input: +// IN VOID *Handle +// IN UINT32 Package - Package number. If question applies to all packages, use 0. +// +// Output: +// UINT8 - Number of cores +// Output may be CPU specific, since this is handled by CPU specific model. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 GetPlatformNumCores(IN VOID *Handle, UINT32 Package) +{ + SETUP_DATA *SetupData; + if (Handle == NULL) return 0xff; //No setup + + SetupData = ((PRIVATE_CPU_SETUP_LIB*)Handle)->SetupData; + return SetupData->ActiveCoreCount; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetPlatformCpuLimitCpuidEnable +// +// Description: Get the platform policy of limiting Cpuid. +// +// Input: +// IN VOID *Handle +// +// Output: +// BOOLEAN -- True Limit CPU ID. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetPlatformCpuLimitCpuidEnable(IN VOID *Handle) +{ + SETUP_DATA *SetupData; + if (Handle == NULL) return FALSE; //No setup + + SetupData = ((PRIVATE_CPU_SETUP_LIB*)Handle)->SetupData; + return (BOOLEAN) SetupData->LimitCpuid; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetPlatformCpux2ApicEnable +// +// Description: Get the platform policy of enable x2Apic. +// +// Input: +// IN VOID *Handle +// +// Output: +// BOOLEAN -- True Enable x2Apic +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetPlatformCpux2ApicEnable(IN VOID *Handle) +{ + SETUP_DATA *SetupData; + if (Handle == NULL) return FALSE; //No setup + + SetupData = ((PRIVATE_CPU_SETUP_LIB*)Handle)->SetupData; + return (BOOLEAN) SetupData->LocalX2Apic; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetPlatformCpuVtEnable +// +// Description: Get the platform policy of enable VT. +// +// Input: +// IN VOID *Handle +// +// Output: +// BOOLEAN -- True Enable VT +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetPlatformCpuVtEnable(IN VOID *Handle) +{ + SETUP_DATA *SetupData; + if (Handle == NULL) return FALSE; + + SetupData = ((PRIVATE_CPU_SETUP_LIB*)Handle)->SetupData; + return (BOOLEAN) SetupData->VT; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetPlatformCpuXdEnable +// +// Description: Get the platform policy of enable XD. +// +// Input: +// IN VOID *Handle +// +// Output: +// BOOLEAN -- True Enable XD. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetPlatformCpuXdEnable(IN VOID *Handle) +{ + SETUP_DATA *SetupData; + if (Handle == NULL) return FALSE; //No Setup + + SetupData = ((PRIVATE_CPU_SETUP_LIB*)Handle)->SetupData; + return (BOOLEAN) SetupData->XDBit; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetPlatformCpuBootRatio +// +// Description: Get the platform policy of for boot ratio. +// +// Input: +// IN VOID *Handle +// +// Output: +// UINT32 Boot Ratio +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 GetPlatformCpuBootRatio(IN VOID *Handle) +{ +#if CPU_SETUP_SET_BOOT_RATIO == 0 + return 0xffffffff; +#else + SETUP_DATA *SetupData; + if (Handle == NULL) return 0xffffffff; + + SetupData = ((PRIVATE_CPU_SETUP_LIB*)Handle)->SetupData; + return SetupData->CpuSetBootRatio; +#endif +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PeiInitPlatformCpuLib +// +// Description: Init platform policy in PEI. +// +// Input: +// IN EFI_PEI_SERVICES **PeiServices +// +// Output: +// VOID **Handle +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS PeiInitPlatformCpuLib(IN EFI_PEI_SERVICES **PeiServices, OUT VOID **Handle) +{ + EFI_PEI_READ_ONLY_VARIABLE_PPI *ReadOnlyVariable; + PRIVATE_CPU_SETUP_LIB *Private; + UINTN VariableSize; + EFI_STATUS Status; + + *Handle = NULL; + + Status = (*PeiServices)->LocatePpi( + PeiServices, + &gEfiPeiReadOnlyVariablePpiGuid, + 0, NULL, + &ReadOnlyVariable + ); + if (EFI_ERROR(Status)) return Status; + + + Status = (*PeiServices)->AllocatePool(PeiServices, + sizeof(PRIVATE_CPU_SETUP_LIB), + &Private + ); + if (EFI_ERROR(Status)) return Status; + + Status = (*PeiServices)->AllocatePool(PeiServices, + sizeof(SETUP_DATA), + &Private->SetupData + ); + if (EFI_ERROR(Status)) return Status; + + VariableSize = sizeof(SETUP_DATA); + Status = ReadOnlyVariable->GetVariable( + PeiServices, + L"Setup", &gAmiSetupGuid, + NULL, + &VariableSize, + Private->SetupData + ); + if (EFI_ERROR(Status)) return Status; + + *Handle = (VOID*)Private; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DxeInitPlatformCpuLib +// +// Description: Initialize DXE Init Platform Cpu Lib. +// +// Input: +// IN EFI_BOOT_SERVICES *Bs +// IN EFI_RUNTIME_SERVICES *Rs +// OUT VOID **Handle +// +// Output: +// EFI_STATUS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS DxeInitPlatformCpuLib( + IN EFI_BOOT_SERVICES *Bs, + IN EFI_RUNTIME_SERVICES *Rs, + OUT VOID **Handle +) +{ + UINTN VariableSize = sizeof(SETUP_DATA); + PRIVATE_CPU_SETUP_LIB *Private; + EFI_STATUS Status; + UINT32 CpuSignature = GetCpuSignature() & 0xfffffff0; + + //Only show as supported if all are supported. + MemSet(&gSetupCpuFeatures, sizeof(gSetupCpuFeatures), 0); //Initialize features to 0. + + gSetupCpuFeatures.CpuGroup = GetPlatformCpuGroup(NULL); + if (CpuSignature == SANDY_BRIDGE || CpuSignature == JAKETOWN ||CpuSignature == IVY_BRIDGE) + gSetupCpuFeatures.IsSandyBridge = TRUE; + + gSetupCpuFeatures.NumCores = NumCpuCores(); + + *Handle = NULL; + + Status = Bs->AllocatePool(EfiBootServicesData, sizeof(PRIVATE_CPU_SETUP_LIB), &Private); + if (EFI_ERROR(Status)) return Status; + + Status = Bs->AllocatePool(EfiBootServicesData, sizeof(SETUP_DATA), &Private->SetupData); + if (EFI_ERROR(Status)) return Status; + + VariableSize = sizeof(SETUP_DATA); + Status = Rs->GetVariable( + L"Setup", + &gAmiSetupGuid, + NULL, + &VariableSize, + Private->SetupData + ); + if (EFI_ERROR(Status)) return Status; + + *Handle = (VOID*)Private; + + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/PlatformCpuLib.h b/Board/CPU/PlatformCpuLib.h new file mode 100644 index 0000000..79ef296 --- /dev/null +++ b/Board/CPU/PlatformCpuLib.h @@ -0,0 +1,299 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/PlatformCpuLib.h 6 7/23/13 7:41a Crystallee $ +// +// $Revision: 6 $ +// +// $Date: 7/23/13 7:41a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/CPU Board/PlatformCpuLib.h $ +// +// 6 7/23/13 7:41a Crystallee +// [TAG] EIP128089 +// [Category] Improvement +// [Description] TXT will be disabled and grayed out in Setup when TPM +// Support is disabled. +// +// 5 2/22/13 2:00a Crystallee +// [TAG] EIP112238 +// [Category] Improvement +// [Description] Refer Intel BIOS and provide setup items for Intel +// Haswell RC policy. +// +// 4 11/23/12 4:14a Davidhsieh +// [TAG] EIPNone +// [Category] Bug Fix +// [Severity] Minor +// [Symptom] Ctdp setup item is not displayed in setup menu +// [RootCause] The cTDPAvailable value is not initialzied +// [Solution] Initial cTDPAvailable value +// +// 3 10/17/12 2:23a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Setup items CTDP BIOS, C8, C9 and C10 created +// +// 2 3/16/12 3:35a Davidhsieh +// Setup items create for CPU RC policy +// +// 1 2/07/12 3:57a Davidhsieh +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// Name: PlatformCpuLib.h +// +// Description: Platform CPU library. +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#ifndef __PLATFORM_CPU_LIB_H__ +#define __PLATFORM_CPU_LIB_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef VFRCOMPILE +#include <efi.h> +#include <Pei.h> + +EFI_STATUS PeiInitPlatformCpuLib(IN EFI_PEI_SERVICES **PeiServices, OUT VOID **Handle); +EFI_STATUS DxeInitPlatformCpuLib( + IN EFI_BOOT_SERVICES *Bs, + IN EFI_RUNTIME_SERVICES *Rs, + OUT VOID **Handle +); + +EFI_STATUS DxePlatformCpuSaveSupportedData( + IN EFI_RUNTIME_SERVICES *Rs +); + +UINT8 GetPlatformNumCores(IN VOID *Handle, UINT32 Package); +BOOLEAN GetPlatformCpuLimitCpuidEnable(IN VOID *Handle); +BOOLEAN GetPlatformCpux2ApicEnable(IN VOID *Handle); +BOOLEAN GetPlatformCpuVtEnable(IN VOID *Handle); +BOOLEAN GetPlatformCpuXdEnable(IN VOID *Handle); +UINT32 GetPlatformCpuGroup(IN VOID *Handle); +UINT32 GetPlatformCpuBootRatio(IN VOID *Handle); +///////////////////////////////////////////////////////////// +//These functions are currently only availabe in DXE not PEI. +///////////////////////////////////////////////////////////// + +VOID PlatformCpuCtdpSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuLimitCpuidSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuHtSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuMultiCoreSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuMultiSocketSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuMultiSocketPopulated( + IN VOID *Handle, + IN BOOLEAN Populated +); + +VOID PlatformCpuXdSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuVtSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuSmxSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuLocalx2ApicSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuSocketSetPopulated( + IN VOID *Handle, + IN UINT32 Socket, + IN BOOLEAN Populated +); + +VOID PlatformCpuMismatch( + IN VOID *Handle, + IN BOOLEAN Mismatch +); + +VOID PlatformCpuXeCoreRatioLimitSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuCurrentLimitSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuTccActiveOffsetSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuEistSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuTurboModeSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuC3Support( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuC6Support( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuC7Support( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuC8Support( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuC9Support( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuC10Support( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuAesSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuPkgCStateDemotionSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformCpuPwrLimitConfigSupport( + IN VOID *Handle, + IN BOOLEAN Supported +); + +VOID PlatformTpmDevicePresent( + IN VOID *Handle, + IN BOOLEAN Supported +); +#endif + +//////////////////////////////////////////////////////////////// +//This is a private structure that is used for setup by Cpu.Sd +//This structure can change any time. No drivers should refer +// directly to this structure. +//////////////////////////////////////////////////////////////// +typedef struct { + UINT8 XDBitAvailable; + UINT8 HTAvailable; + UINT8 MultiCoreAvailable; + UINT8 VTAvailable; + UINT8 LimitCpuidAvailable; + UINT8 MultiSocketAvailable; + UINT8 MultiSocketPopulated; + UINT8 LocalX2ApicAvailable; + UINT8 NumCores; + UINT8 CpuGroup; //Arbitrary number + UINT8 IsSandyBridge; + UINT8 IsHasWell; + UINT8 Skt0Pop; + UINT8 Skt1Pop; + UINT8 Skt2Pop; + UINT8 Skt3Pop; + UINT8 SmxAvailable; + UINT8 CpuMismatch; + UINT8 XECoreRatioLimitAvailable; + UINT8 CurrentLimitAvailable; + UINT8 PwrLimitAvailable; + UINT8 TccActivationAvailable; + UINT8 EistAvailable; + UINT8 TurboModeAvailable; + UINT8 C3Available; + UINT8 C6Available; + UINT8 C7Available; + UINT8 AesAvailable; + UINT8 cTDPAvailable; + UINT8 C8Available; + UINT8 C9Available; + UINT8 C10Available; + UINT8 PkgCStateDemotionAvailable; + UINT8 TpmDeviceAvailable; +} SETUP_CPU_FEATURES; + + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Board/CPU/TxtDxe/AmiTxtDxe.c b/Board/CPU/TxtDxe/AmiTxtDxe.c new file mode 100644 index 0000000..3db2503 --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtDxe.c @@ -0,0 +1,534 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.c 11 6/11/15 10:31p Crystallee $ +// +// $Revision: 11 $ +// +// $Date: 6/11/15 10:31p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.c $ +// +// 11 6/11/15 10:31p Crystallee +// [TAG] EIP207854 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Txt test fail with TCG2 module +// [RootCause] Tokne TCG_SUPPORT was removed. +// [Solution] Add TCG2Support token. +// +// 10 4/10/15 3:11a Crystallee +// +// 9 5/05/14 11:57p Hsingyingchung +// [TAG] EIP167029 +// [Category] Improvement +// [Description] Keep the original attribute of "Setup" variable when +// use SetVariable(). +// +// 8 1/17/14 4:08a Crystallee +// [TAG] None +// [Category] Improvement +// [Description] Show Txt information in setup->Advanced ->Intel Txt +// Information page. +// +// 7 8/28/13 5:57a Crystallee +// [TAG] EIP134339 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] [Sharkbay]Build error after update Haswell Cpu module +// [RootCause] If token TCG_SUPPORT is disabled, TpmSupport setup data +// will not define, then cause built error. +// [Solution] Add token TCG_SUPPORT condition when use TpmSupport setup +// data. +// +// 6 8/14/13 5:07a Davidhsieh +// +// 4 7/23/13 7:47a Crystallee +// [TAG] EIP128089 +// [Category] Improvement +// [Description] TXT will be disabled and grayed out in Setup when TPM +// Support is disabled. +// +// 3 9/13/12 4:13a Davidhsieh +// [TAG] None +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Desable TCG causes BIOS building error +// [RootCause] TCG setup data is used in TxtPei and the data is not +// exist when TCG disabled. +// [Solution] Do not use the TCG setup data when TCG disabled +// +// 2 9/05/12 1:36a Davidhsieh +// [TAG] EIP97350 +// [Category] Improvement +// [Description] Add AUX index define in TPM NVRAM to avoid system keep +// reset when TXT enabled +// +// 1 7/18/12 2:07a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] AMI TXT Dxe module part create +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: AmiTxtDxe.c +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +// +#include "AmiTxtDxe.h" +#include "Txt.h" + +AMI_TXT_INFO_PROTOCOL gAmiTxtInfoProtocol = {0}; +AMI_TXT_INFO_DATA gAmiTxtInfoData = {0}; + +EFI_GUID gHobListGuid = HOB_LIST_GUID; +EFI_GUID gAmiTxtInfoProtocolGuid = AMI_TXT_INFO_PROTOCOL_GUID; + +#if TCG_SUPPORT || TCG2Support +EFI_GUID gSetupGuid = SETUP_GUID; +EFI_GUID gEfiTcgProtocolGuid = EFI_TCG_PROTOCOL_GUID; +EFI_GUID gEfiTpmDeviceProtocolGuid = EFI_TPM_DEVICE_PROTOCOL_GUID; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: LtSendTpmCommand +// +// Description: Sends a command to the TPM +// +// Input: *EFI_TCG_PROTOCOL - Tcg Protocol type. +// UINT32 - Tcg Command ordinal. +// int - cmd datasize. +// VOID* - cmd data. +// +// Output: UINT32 - TPM_RESULT +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 +LtSendTpmCommand ( + IN EFI_TCG_PROTOCOL *tcg, + IN UINT32 ord, + IN int dataSize, + IN VOID *data +) +{ + EFI_STATUS Status; + static UINT8 result[0x400]; + TPM_1_2_RET_HEADER* tpmResult; + struct { + TPM_1_2_CMD_HEADER hdr; + UINT8 data[0x100]; + } cmd; + + cmd.hdr.Tag = TPM_H2NS (TPM_TAG_RQU_COMMAND); + cmd.hdr.ParamSize = TPM_H2NL (sizeof(TPM_1_2_RET_HEADER) + dataSize); + cmd.hdr.Ordinal = TPM_H2NL (ord); + pBS->CopyMem(cmd.data, data, dataSize); + Status = tcg->PassThroughToTpm ( tcg, \ + sizeof(TPM_1_2_CMD_HEADER) + dataSize, \ + (UINT8*)&cmd, \ + sizeof (result), \ + (UINT8*)&result ); + tpmResult = (TPM_1_2_RET_HEADER*)result; + if ( EFI_ERROR(Status) || (tpmResult->RetCode != 0)) + TRACE((TRACE_ALWAYS, "TXT (TPM Error) Status: %r; RetCode: %x.\n", \ + Status, \ + TPM_H2NL(tpmResult->RetCode) )); + return tpmResult->RetCode; +} + +#if defined SINIT_ACM_SUPPORT && SINIT_ACM_SUPPORT == 1 +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: EventUpdateSinitAcmToMemory +// +// Description: This routine copy SINIT ACM to SINIT meory for BIOS-Base SINI +// AC Module implementation. +// +// Input: IN EFI_EVENT Event +// IN VOID *Context +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +EventUpdateSinitAcmToMemory ( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_HANDLE *FvHandle; + UINTN Number, i, SinitacmSize = 0; + UINT32 Authentication, TxtMemBase; + VOID *pSinitacmPtr = NULL; + EFI_FIRMWARE_VOLUME_PROTOCOL *Fv; + EFI_GUID SinitAcmFfsGuid = \ + { 0x7fbfe0ea, 0x0e9d, 0x406b, 0xa2, 0x2, 0xca, 0x6a, 0x7d, 0x0e, 0x0f, 0x1e}; + EFI_GUID gEfiFirmwareVolume2ProtocolGuid = + { 0x220e73b6, 0x6bdb, 0x4413, 0x84, 0x5, 0xb9, 0x74, 0xb1, 0x8, 0x61, 0x9a }; + + pBS->CloseEvent (Event); + Status = pBS->LocateHandleBuffer (ByProtocol, \ + &gEfiFirmwareVolume2ProtocolGuid, \ + NULL, \ + &Number, \ + &FvHandle); + if (EFI_ERROR(Status)) return; + + for (i = 0; i < Number; i++) { + + Status = pBS->HandleProtocol (\ + FvHandle[i], &gEfiFirmwareVolume2ProtocolGuid, &Fv); + if (EFI_ERROR(Status)) continue; + + // Read SINIT AC module from Firmware Volume + SinitacmSize = 0; + pSinitacmPtr = NULL; + Status = Fv->ReadSection ( Fv, + &SinitAcmFfsGuid, + EFI_SECTION_RAW, + 0, + &pSinitacmPtr, + &SinitacmSize, + &Authentication ); + if (!EFI_ERROR(Status)) { + // SINIT Memory Base = TXT Public Space + 270h + TxtMemBase = *(UINT32*)0xfed30270; + // copy SINIT ACM to SINIT memory + pBS->CopyMem ((VOID*)TxtMemBase, pSinitacmPtr, SinitacmSize); + // BiosToOS Region Base = TXT Public Space + 300h + TxtMemBase = *(UINT32*)0xfed30300; + // Update SINIT ACM size to BiosToOS region + *(UINT32*)(TxtMemBase + 12) = (UINT32)SinitacmSize; + pBS->FreePool (pSinitacmPtr); + break; + } + } + pBS->FreePool (FvHandle); +} +#endif +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: LtDefineTpmNvramSpace +// +// Description: This routine for define the TPM Nvram space. +// +// Input: None. +// +// Output: TURE - Success. +// FALSE - Failed. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +LtDefineTpmNvramSpace ( + VOID +) +{ + EFI_STATUS Status; + EFI_TCG_PROTOCOL *tcg; + EFI_TPM_DEVICE_PROTOCOL *TpmDevice; + UINT32 CmdReadNvram[3] = { TPM_H2NL(0x50000002), + TPM_H2NL(0x00000000), + TPM_H2NL(0x40) }; + TPM_DEF_NV_DATA CmdDefineNvram [] = { \ + // TPM_NV_DATA_PUBLIC1 & TPM_NV_DATA_PUBLIC1.TPM_PCR_INFO_SHORT + TPM_H2NS(0x18), TPM_H2NL(0x50000003), TPM_H2NS(0x03), 0, 0, 0 , 0x1f, \ + // TPM_NV_DATA_PUBLIC1.TPM_PCR_INFO_SHORT.TCPA_DIGEST + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + // TPM_NV_DATA_PUBLIC2.TPM_PCR_INFO_SHORT + TPM_H2NS(0x3), 0, 0, 0 , 0x18, \ + // TPM_NV_DATA_PUBLIC2.TPM_PCR_INFO_SHORT.TCPA_DIGEST + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + // TPM_NV_DATA_PUBLIC2 + TPM_H2NS(0x17), TPM_H2NL(0), 0, 0, 0, TPM_H2NL(0x40), \ + // TCPA_DIGEST + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + // locate the TPM Device Protocol for sending TPM command. + Status = pBS->LocateProtocol ( &gEfiTpmDeviceProtocolGuid, \ + NULL, \ + &TpmDevice ); + if (EFI_ERROR(Status)) { + TRACE ((TRACE_ALWAYS, \ + "TXT (TPM Error) : failed to locate TPM Device protocol.\n")); + return FALSE; + } + // locate the TCG Protocol for sending TPM command. + Status = pBS->LocateProtocol ( &gEfiTcgProtocolGuid, NULL, &tcg ); + if (EFI_ERROR (Status)) { + TRACE ((TRACE_ALWAYS, \ + "TXT (TPM Error) : failed to locate TCG protocol.\n")); + return FALSE; + } +#if defined SINIT_ACM_SUPPORT && SINIT_ACM_SUPPORT == 1 +{ + // BIOS-Based SINIT AC module support. + EFI_EVENT SinitEvent; + + Status = CreateReadyToBootEvent(TPL_CALLBACK, \ + EventUpdateSinitAcmToMemory, \ + NULL, \ + &SinitEvent ); +} +#endif + TpmDevice->Init(TpmDevice); + // Send TPM command to read TPM NVRAM space. + Status = LtSendTpmCommand ( tcg, \ + TPM_ORD_NV_READVALUE, \ + sizeof(CmdReadNvram), \ + CmdReadNvram ); + // if TPM NVRAM isn't defined, Send TPM command to define TPM NVRAM space. + if (Status != 0) { + CmdReadNvram[0] = TPM_H2NL(0x50000003); + Status = LtSendTpmCommand ( tcg, \ + TPM_ORD_NV_READVALUE, \ + sizeof(CmdReadNvram), \ + CmdReadNvram ); + if (Status != 0) { + Status = LtSendTpmCommand ( tcg, \ + TPM_ORD_NV_DEFINESPACE, \ + sizeof(TPM_DEF_NV_DATA), \ + &CmdDefineNvram ); + } + } + Status = TpmDevice->Close(TpmDevice); + + if ( Status ) return FALSE; + return TRUE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TxtTpmNvRamDefine +// +// Description: +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID TxtTpmNvRamDefine() +{ + UINTN VariableSize; + SETUP_DATA SetupData; + EFI_STATUS Status; + + VariableSize = sizeof(SETUP_DATA); + Status = pRS->GetVariable ( L"Setup", \ + &gSetupGuid, \ + NULL, \ + &VariableSize, \ + &SetupData ); + if (EFI_ERROR(Status)) + return; + + if (SetupData.TxtSupport != 0) { + if (SetupData.TpmSupport != 0) LtDefineTpmNvramSpace(); + } +} +#else +VOID TxtTpmNvRamDefine() +{ + return; +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetTxtInfo +// +// Description: Get Txt information +// +// Input: None +// +// Output: None. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetTxtInfo ( + IN AMI_TXT_INFO_PROTOCOL *AMI_TXT_INFO_PROTOCOL, + OUT VOID **AmiTxtInfoData +){ + *AmiTxtInfoData = (VOID*)(&gAmiTxtInfoData); + return 0; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitAmiTxtInfo +// +// Description: Initialize Txt information +// +// Input: None +// +// Output: None. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID InitAmiTxtInfo() +{ + EFI_STATUS Status; + VOID *HobList; + TXT_INFO_HOB *TxtInfoHob; + UINT32 RegEax, RegEbx, RegEcx, RegEdx; + UINT32 *TxtErrCode = (UINT32*)(TXT_PUBLIC_BASE + 0x0030); + EFI_GUID gTxtInfoHobGuid = TXT_INFO_HOB_GUID; + + + HobList = GetEfiConfigurationTable(pST,&gHobListGuid); + if (!HobList) return; + + //Find RC Txt Info Hob. + TxtInfoHob = (TXT_INFO_HOB*)HobList; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &TxtInfoHob))) { + if (guidcmp(&TxtInfoHob->EfiHobGuidType.Name, &gTxtInfoHobGuid) == 0) break; + } + if (EFI_ERROR(Status)) return; + + //Initialize AmiTxtInfoProtocol + gAmiTxtInfoProtocol.ProtocolVer = AMI_TXT_INFO_PROTOCOL_VERSION; + gAmiTxtInfoProtocol.GetTxtInfo = GetTxtInfo; + + //Initialize AMI TXT info data from HOB created by Intel Txt RC + gAmiTxtInfoData.ChipsetIsTxtCapable = TxtInfoHob->Data.ChipsetIsTxtCapable; + gAmiTxtInfoData.TxtDprMemoryBase = TxtInfoHob->Data.TxtDprMemoryBase; + gAmiTxtInfoData.BiosAcmBase = TxtInfoHob->Data.BiosAcmBase; + gAmiTxtInfoData.McuUpdateDataAddr = TxtInfoHob->Data.McuUpdateDataAddr; + gAmiTxtInfoData.SinitAcmBase = TxtInfoHob->Data.SinitAcmBase; + + //Initializing ChipsetIsProduction default value + gAmiTxtInfoData.ChipsetIsProduction = (*(UINT32 *) (TXT_PUBLIC_BASE + 0x200) & BIT31) ? TRUE : FALSE; + + //Check ACM is production or not + gAmiTxtInfoData.BiosAcmIsProduction = (((ACM_HEADER*)(gAmiTxtInfoData.BiosAcmBase))->ModuleID & BIT31) ? FALSE : TRUE; + + //CPUID funciton 1 ECX[6], Secure Mode Extensions check + CPULib_CpuID(1, &RegEax, &RegEbx, &RegEcx, &RegEdx); + gAmiTxtInfoData.CpuIsTxtCapable = (RegEcx & BIT6) ? TRUE : FALSE; + + //TXT.CRASH register, TXT_PUBLIC_BASE + 0x30 + gAmiTxtInfoData.TxtErrCode = *TxtErrCode; + + Status = pBS->InstallProtocolInterface( + &TheImageHandle, + &gAmiTxtInfoProtocolGuid, + EFI_NATIVE_INTERFACE, + &gAmiTxtInfoProtocol + ); + + if (EFI_ERROR(Status)) + TRACE ((TRACE_ALWAYS, "AmiTXTDxe : Install Protocol error, Status = %x\n", Status)); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AmiTxtDxeEntry +// +// Description: DXE Entry Point for Intel TXT Driver. +// +// Input: EFI_HANDLE - ImageHandle +// EFI_SYSTEM_TABLE* - SystemTable +// +// Output: None. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +AmiTxtDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ +#if TCG_SUPPORT || TCG2Support + EFI_STATUS Status; + UINTN DataSize; + SETUP_DATA SetupData; + UINT8 *TpmBaseAddr = (UINT8*)0xfed40000; + UINT32 Attributes = 0; +#endif + + InitAmiLib(ImageHandle, SystemTable); + InitAmiTxtInfo(); + +#if TCG_SUPPORT || TCG2Support + DataSize = sizeof(SETUP_DATA); + + Status = pRS->GetVariable( + L"Setup", + &gSetupGuid, + &Attributes, + &DataSize, + &SetupData + ); + + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return EFI_SUCCESS; + //If TxtSupport on, but Tpm device is not present or TpmSupport off, + //then turn off TxtSupport. + if (SetupData.TxtSupport){ + if ((*TpmBaseAddr == 0xff) || (!SetupData.TpmSupport)){ + SetupData.TxtSupport = 0; + + Status = pRS->SetVariable( + L"Setup", + &gSetupGuid, + Attributes, + sizeof(SETUP_DATA), + &SetupData + ); + + ASSERT_EFI_ERROR(Status); + } + } +#endif + + TxtTpmNvRamDefine(); + + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/TxtDxe/AmiTxtDxe.cif b/Board/CPU/TxtDxe/AmiTxtDxe.cif new file mode 100644 index 0000000..6b9d1ea --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtDxe.cif @@ -0,0 +1,21 @@ +<component> + name = "AMI TXT Dxe" + category = ModulePart + LocalRoot = "Board\Cpu\TxtDxe" + RefName = "AmiTxtDxe" +[files] +"AmiTxtDxe.sdl" +"AmiTxtDxe.mak" +"AmiTxtDxe.c" +"AmiTxtDxe.dxs" +"TxtTcgService.h" +"TxtSetup.c" +"Include\Protocol\AmiTxtInfo.h" +"AmiTxtDxe.h" +"AmiTxtInfoSetup.c" +"AmiTxtInfoSetup.sd" +"AmiTxtInfoSetup.uni" +"AmiTxtInfoHook.c" +[parts] +"TxtSinitAcm" +<endComponent> diff --git a/Board/CPU/TxtDxe/AmiTxtDxe.dxs b/Board/CPU/TxtDxe/AmiTxtDxe.dxs new file mode 100644 index 0000000..4b2c032 --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtDxe.dxs @@ -0,0 +1,48 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.dxs 1 9/05/12 1:33a Davidhsieh $ +// +// $Revision: 1 $ +// +// $Date: 9/05/12 1:33a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.dxs $ +// +// 1 9/05/12 1:33a Davidhsieh +// +// +// +//********************************************************************** +#include <Protocol/SmmSwDispatch.h> + +DEPENDENCY_START + EFI_SMM_SW_DISPATCH_PROTOCOL_GUID +DEPENDENCY_END +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/TxtDxe/AmiTxtDxe.h b/Board/CPU/TxtDxe/AmiTxtDxe.h new file mode 100644 index 0000000..b92ad14 --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtDxe.h @@ -0,0 +1,112 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.h 1 1/17/14 3:45a Crystallee $ +// +// $Revision: 1 $ +// +// $Date: 1/17/14 3:45a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.h $ +// +// 1 1/17/14 3:45a Crystallee +// [TAG] None +// [Category] Improvement +// [Description] Show Txt information in setup->Advanced ->Intel Txt +// Information page. +// + +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: AmiTxtDxe.h +// +// Description: AmiTxt Dxe header file. +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#ifndef __AMI_TXT_DXE_H__ +#define __AMI_TXT_DXE_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include <token.h> +#include <AmiDxeLib.h> +#include "TxtTcgService.h" +#include <Setup.h> +#include <hob.h> +#include <Guid/TxtInfoHob/TxtInfoHob.h> +#include "Include/Protocol/AmiTxtInfo.h" +//#include <Protocol/CpuPlatformPolicy.h> + +VOID CPULib_CpuID(UINT32 CpuIDIndex, UINT32 * RegEAX, UINT32 * RegEBX, + UINT32 * RegECX, UINT32 * RegEDX); + +typedef struct _ACM_HEADER { + UINT32 ModuleType; ///< Module type + UINT32 HeaderLen; ///< 4 4 Header length (in multiples of four bytes) + /// (161 for version 0.0) + /// + UINT32 HeaderVersion; ///< 8 4 Module format version + UINT32 ModuleID; ///< 12 4 Module release identifier + UINT32 ModuleVendor; ///< 16 4 Module vendor identifier + UINT32 Date; ///< 20 4 Creation date (BCD format: + /// year.month.day) + /// + UINT32 Size; ///< 24 4 Module size (in multiples of four bytes) + UINT32 Reserved1; ///< 28 4 Reserved for future extensions + UINT32 CodeControl; ///< 32 4 Authenticated code control flags + UINT32 ErrorEntryPoint; ///< 36 4 Error response entry point offset (bytes) + UINT32 GDTLimit; ///< 40 4 GDT limit (defines last byte of GDT) + UINT32 GDTBasePtr; ///< 44 4 GDT base pointer offset (bytes) + UINT32 SegSel; ///< 48 4 Segment selector initializer + UINT32 EntryPoint; ///< 52 4 Authenticated code entry point offset (bytes) + UINT32 Reserved2; ///< 56 64 Reserved for future extensions + UINT32 KeySize; ///< 120 4 Module public key size less the exponent + /// (in multiples of four bytes + /// - 64 for version 0.0) + /// + UINT32 ScratchSize; ///< 124 4 Scratch field size (in multiples of four bytes) + /// (2 * KeySize + 15 for version 0.0) + /// + UINT8 RSAPubKey[65 * 4]; ///< 128 KeySize * 4 + 4 Module public key + UINT8 RSASig[256]; ///< 388 256 PKCS #1.5 RSA Signature. +} ACM_HEADER; +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/TxtDxe/AmiTxtDxe.mak b/Board/CPU/TxtDxe/AmiTxtDxe.mak new file mode 100644 index 0000000..f29aae9 --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtDxe.mak @@ -0,0 +1,132 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +#************************************************************************* +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.mak 5 1/17/14 4:08a Crystallee $ +# +# $Revision: 5 $ +# +# $Date: 1/17/14 4:08a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.mak $ +# +# 5 1/17/14 4:08a Crystallee +# [TAG] None +# [Category] Improvement +# [Description] Show Txt information in setup->Advanced ->Intel Txt +# Information page. +# +# 4 10/14/12 11:49p Davidhsieh +# [TAG] None +# [Category] Improvement +# [Description] Use SBLib_ExtResetSystem when pRS->ResetSystem does not +# support GlobaRest type in the project +# +# 3 9/05/12 1:36a Davidhsieh +# [TAG] EIP97350 +# [Category] Improvement +# [Description] Add AUX index define in TPM NVRAM to avoid system keep +# reset when TXT enabled +# +# 2 8/14/12 5:06a Davidhsieh +# [TAG] EIP97190 +# [Category] Improvement +# [Description] Changes in TXT Configuration require a Powercycle reset +# +# 1 7/18/12 2:07a Davidhsieh +# [TAG] None +# [Category] Improvement +# [Description] AMI TXT Dxe module part create +# +# +#********************************************************************** + +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: AmiTxtDxe.mak +# +# Description: Makefile for TxtWrapper. +# +#<AMI_FHDR_END> +#********************************************************************** + +all : AmiTxtDxe + +AmiTxtDxe: $(BUILD_DIR)\AmiTxtDxe.mak AmiTxtDxeBin + +$(BUILD_DIR)\AmiTxtDxe.mak : $(AmiTxtDxe_DIR)\$(@B).cif $(AmiTxtDxe_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(AmiTxtDxe_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +CPU_TXTDXE_INCLUDE = \ + $(PROJECT_CPU_INCLUDES) + +AmiTxtDxeBin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\AmiTxtDxe.mak all\ + MAKEFILE=$(BUILD_DIR)\AmiTxtDxe.mak \ + "MY_INCLUDES=$(CPU_TXTDXE_INCLUDE)" \ + OBJECTS=$(BUILD_DIR)\$(AmiTxtDxe_DIR)\AmiTxtDxe.obj\ + GUID=87D402CD-8B07-4B93-B38B-F8799F28B033 \ + ENTRY_POINT=AmiTxtDxeEntry\ + TYPE=BS_DRIVER \ + DEPEX1=$(AmiTxtDxe_DIR)\AmiTxtDxe.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ + COMPRESS=1 + +#--------------------------------------------------------------------------- +# TSE Elink component +#--------------------------------------------------------------------------- +TXTTSE_CFLAGS = \ +$(CFLAGS) \ +-I $(TSEBIN_DIR)\Inc \ +-I $(TSEBIN_DIR)\ \ +/D _TSE_HOOK_ + +AMITSEBin : $(BUILD_DIR)\TXTTseHook.obj $(BUILD_DIR)\AmiTxtInfoHook.obj + +$(BUILD_DIR)\TXTTseHook.obj : $(AmiTxtDxe_DIR)\TXTSetup.c + $(CC) $(TXTTSE_CFLAGS) /Fo$(BUILD_DIR)\TXTTseHook.obj $(AmiTxtDxe_DIR)\TXTSetup.c + +$(BUILD_DIR)\AmiTxtInfoHook.obj : $(AmiTxtDxe_DIR)\AmiTxtInfoHook.c + $(CC) $(TXTTSE_CFLAGS) /Fo$(BUILD_DIR)\AmiTxtInfoHook.obj $(AmiTxtDxe_DIR)\AmiTxtInfoHook.c + +#--------------------------------------------------------------------------- +# TSE Elink component +#--------------------------------------------------------------------------- +SetupSdbs : $(BUILD_DIR)\AmiTxtDxe.mak AmiTxtInfoSetupSDB +SetupBin : $(BUILD_DIR)\AmiTxtInfoSetup.obj + +AmiTxtInfoSetupSDB : + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\AmiTxtDxe.mak all\ + TYPE=SDB NAME=AmiTxtInfoSetup MAKEFILE=$(BUILD_DIR)\AmiTxtDxe.mak "STRING_CONSUMERS=$(AmiTxtDxe_DIR)\AmiTxtInfoSetup.sd $(AmiTxtDxe_DIR)\AmiTxtInfoSetup.c" + +$(BUILD_DIR)\AmiTxtInfoSetup.obj: $(PROJECT_DIR)\$(AmiTxtDxe_DIR)\AmiTxtInfoSetup.c $(BUILD_DIR)\SetupStrTokens.h + $(CC) $(CFLAGS) /Fo$@ $(PROJECT_DIR)\$(AmiTxtDxe_DIR)\AmiTxtInfoSetup.c + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/CPU/TxtDxe/AmiTxtDxe.sdl b/Board/CPU/TxtDxe/AmiTxtDxe.sdl new file mode 100644 index 0000000..d3cbb3a --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtDxe.sdl @@ -0,0 +1,133 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.sdl 3 1/17/14 4:08a Crystallee $ +# +# $Revision: 3 $ +# +# $Date: 1/17/14 4:08a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtDxe.sdl $ +# +# 3 1/17/14 4:08a Crystallee +# [TAG] None +# [Category] Improvement +# [Description] Show Txt information in setup->Advanced ->Intel Txt +# Information page. +# +# 2 8/14/12 5:06a Davidhsieh +# [TAG] EIP97190 +# [Category] Improvement +# [Description] Changes in TXT Configuration require a Powercycle reset +# +# 1 7/18/12 2:07a Davidhsieh +# [TAG] None +# [Category] Improvement +# [Description] AMI TXT Dxe module part create +# +# +#********************************************************************** +TOKEN + Name = "AMI_TXT_DXE_SUPPORT" + Value = "1" + Help = "Main switch to enable AMI TXT DXE support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "AMI_TXT_INFO_IN_SETUP" + Value = "1" + TokenType = Boolean +End + +TOKEN + Name = "AMI_POSE_SHOW_TXT_INFO" + Value = "0" + Help = "Show txt information in pose time when quiet boot disable." + TokenType = Integer + TargetH = Yes + Token = "AMI_TXT_INFO_IN_SETUP" "=" "1" +End + +PATH + Name = "AmiTxtDxe_DIR" +End + +MODULE + Help = "Includes TxtDxe.mak to Project" + File = "AmiTxtDxe.mak" +End + +ELINK + Name = "$(BUILD_DIR)\AmiTxtDxe.ffs" + Parent = "FV_MAIN" + Help = "Intel Txt DXE component" + InvokeOrder = AfterParent +End + +ELINK + Name = "TxtExitSetupEvent," + Parent = "PreSystemResetHook," + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(BUILD_DIR)\AmiTxtInfoSetup.sdb" + Parent = "SETUP_SDBS" + Priority = 50 + InvokeOrder = AfterParent +End + +ELINK + Name = "$(AmiTxtDxe_DIR)\AmiTxtInfoSetup.sd" + Parent = "SETUP_DEFINITIONS" + Priority = 50 + InvokeOrder = AfterParent + Token = "AMI_TXT_INFO_IN_SETUP" "=" "1" +End + +ELINK + Name = "InitAmiTxtInfoStrings," + Parent = "SetupStringInit" + InvokeOrder = AfterParent + Token = "AMI_TXT_INFO_IN_SETUP" "=" "1" +End + +ELINK + Name = "AmiTxtHook," + Parent = "ProcessConInAvailabilityHook," + InvokeOrder = AfterParent + Token = "AMI_TXT_INFO_IN_SETUP" "=" "1" + Token = "AMI_POSE_SHOW_TXT_INFO" "=" "1" +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/CPU/TxtDxe/AmiTxtInfoHook.c b/Board/CPU/TxtDxe/AmiTxtInfoHook.c new file mode 100644 index 0000000..a7fb7bc --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtInfoHook.c @@ -0,0 +1,167 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Cpu/TxtDxe/AmiTxtInfoHook.c 1 7/08/15 4:26a Chienhsieh $ +// +// $Revision: 1 $ +// +// $Date: 7/08/15 4:26a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: AmiTxtInfoHook.c +// +// Description: AmiTxtInfo Rountines +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <Setup.h> +#include <AmiDxeLib.h> +#include <AmiHobs.h> +#include <Protocol/SimpleTextIn.h> +#include <Protocol/AMIPostMgr.h> +#include "Include/Protocol/AmiTxtInfo.h" + +extern EFI_BOOT_SERVICES *gBS; +extern EFI_SYSTEM_TABLE *gST; +extern EFI_RUNTIME_SERVICES *gRT; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: AmiTxtHook +// +// Description: Initialize CPU strings. +// +// Input: +// IN EFI_HII_HANDLE HiiHandle +// IN UINT16 Class +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN AmiTxtHook (VOID) +{ + EFI_STATUS Status; + EFI_GUID AmiTseSetupguid = AMITSESETUP_GUID; + EFI_GUID gAmiTxtInfoProtocolGuid = AMI_TXT_INFO_PROTOCOL_GUID; + EFI_GUID gAmiPostManagerProtocolGuid = AMI_POST_MANAGER_PROTOCOL_GUID; + AMI_POST_MANAGER_PROTOCOL *gAmiPostMgr = NULL; + AMI_TXT_INFO_PROTOCOL *gAmiTxtInfoProt; + AMI_TXT_INFO_DATA *AmiTxtInfoData = NULL; + UINTN Index; + EFI_INPUT_KEY Key; + AMITSESETUP TSEVar; + UINTN Size; + CHAR16 Str[30]; + + Size = sizeof (AMITSESETUP); + + Status = gRT->GetVariable(L"AMITSESetup", \ + &AmiTseSetupguid, \ + NULL, \ + &Size, \ + &TSEVar ); + if (EFI_ERROR(Status)) return EFI_SUCCESS; + + Status = pBS->LocateProtocol( &gAmiPostManagerProtocolGuid, NULL, &gAmiPostMgr ); + if (EFI_ERROR(Status)) return EFI_SUCCESS; + + Status = pBS->LocateProtocol (&gAmiTxtInfoProtocolGuid, NULL, &gAmiTxtInfoProt); + if (EFI_ERROR(Status)) return EFI_SUCCESS; + + //Get AmiTxt info data + gAmiTxtInfoProt->GetTxtInfo(gAmiTxtInfoProt, &AmiTxtInfoData); + + //Only display txtinfor when error occur + if (!AmiTxtInfoData->TxtErrCode) return EFI_SUCCESS; + + //If it's silent boot, change to post screen + if(TSEVar.AMISilentBoot != 0) gAmiPostMgr->SwitchToPostScreen(); + + gAmiPostMgr->DisplayPostMessage(L"Intel Txt Information:"); + + if (AmiTxtInfoData->ChipsetIsProduction) + gAmiPostMgr->DisplayPostMessage(L"Chipset Production Fused"); + else + gAmiPostMgr->DisplayPostMessage(L"Chipset Debug Fused"); + + if (AmiTxtInfoData->ChipsetIsTxtCapable) + gAmiPostMgr->DisplayPostMessage(L"Chipset Txt Supported"); + else + gAmiPostMgr->DisplayPostMessage(L"Chipset Txt Don't Support"); + + if (AmiTxtInfoData->CpuIsTxtCapable) //CPUID eax=1 ecx[6] + gAmiPostMgr->DisplayPostMessage(L"Cpu Txt Supported"); + else + gAmiPostMgr->DisplayPostMessage(L"Cpu Txt don't Support"); + + if (AmiTxtInfoData->TxtErrCode) { + UINT32 ClassCode = (AmiTxtInfoData->TxtErrCode >> 4) & 0x3f; //ErrorCode[9:4] + UINT32 MajorCode = (AmiTxtInfoData->TxtErrCode >> 10) & 0x1f; //ErrorCode[14:10] + UINT32 MinorCode = (AmiTxtInfoData->TxtErrCode >> 16) & 0x1ff; //ErrorCode[24:16] + + Swprintf(Str,L"Error Code %x", AmiTxtInfoData->TxtErrCode); + gAmiPostMgr->DisplayPostMessage(Str); + + Swprintf(Str,L" Class Code %x", ClassCode); + gAmiPostMgr->DisplayPostMessage(Str); + + Swprintf(Str,L" Major Code %x", MajorCode); + gAmiPostMgr->DisplayPostMessage(Str); + + Swprintf(Str,L" Minor Code %x", MinorCode); + gAmiPostMgr->DisplayPostMessage(Str); + } else { + gAmiPostMgr->DisplayPostMessage(L"Error Code None"); + gAmiPostMgr->DisplayPostMessage(L" Class Code None"); + gAmiPostMgr->DisplayPostMessage(L" Major Code None"); + gAmiPostMgr->DisplayPostMessage(L" Minor Code None"); + } + + gAmiPostMgr->DisplayPostMessage(L"Press anykey to continue"); + + while(1){ + gBS->WaitForEvent(1, &(gST->ConIn->WaitForKey), &Index); + gST->ConIn->ReadKeyStroke(gST->ConIn, &Key); + if((Key.UnicodeChar != 0) || (Key.ScanCode != 0)) break; + } + + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/TxtDxe/AmiTxtInfoSetup.c b/Board/CPU/TxtDxe/AmiTxtInfoSetup.c new file mode 100644 index 0000000..302db9d --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtInfoSetup.c @@ -0,0 +1,176 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtInfoSetup.c 2 1/17/14 4:00a Crystallee $ +// +// $Revision: 2 $ +// +// $Date: 1/17/14 4:00a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtInfoSetup.c $ +// +// 2 1/17/14 4:00a Crystallee +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: HaswellSetup.c +// +// Description: CPU Setup Rountines +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <Setup.h> +#include <AmiDxeLib.h> +#include <AmiHobs.h> +#include "Include/Protocol/AmiTxtInfo.h" +#include <SetupStrTokens.h> + +AMI_TXT_INFO_PROTOCOL *gAmiTxtInfoProt; + + +#pragma pack(push, 1) + +typedef struct { + STRING_REF ChipsetFuse; + STRING_REF ChipsetTxtsupport; + STRING_REF CpuTxtsupport; + STRING_REF ErrorCode; + STRING_REF ClassCode; + STRING_REF MajorCode; + STRING_REF MinorCode; +} SKT_STR_TOK; + +static SKT_STR_TOK gSktStrTok[] = { +{ STRING_TOKEN(STR_CPUTXT_CHIP_FUSE_VALUE), + STRING_TOKEN(STR_CPUTXT_CHIP_SUPPORT_VALUE), + STRING_TOKEN(STR_CPUTXT_CPU_SUPPORT_VALUE), + STRING_TOKEN(STR_CPUTXT_ERROR_CODE_VALUE), + STRING_TOKEN(STR_CPUTXT_CLASS_CODE_VALUE), + STRING_TOKEN(STR_CPUTXT_MAJOR_CODE_VALUE), + STRING_TOKEN(STR_CPUTXT_MINOR_CODE_VALUE) +}}; + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InitAmiTxtInfoStrings +// +// Description: Initialize CPU strings. +// +// Input: +// IN EFI_HII_HANDLE HiiHandle +// IN UINT16 Class +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID InitAmiTxtInfoStrings(EFI_HII_HANDLE HiiHandle, UINT16 Class) +{ + EFI_STATUS Status; + AMI_TXT_INFO_DATA *AmiTxtInfoData = NULL; + EFI_GUID gAmiTxtInfoProtocolGuid = AMI_TXT_INFO_PROTOCOL_GUID; + + if (Class != ADVANCED_FORM_SET_CLASS) return; + + Status = pBS->LocateProtocol (&gAmiTxtInfoProtocolGuid, NULL, &gAmiTxtInfoProt); + if (EFI_ERROR(Status)) return; + + //Stop if protocl version incorrect + if (gAmiTxtInfoProt->ProtocolVer != AMI_TXT_INFO_PROTOCOL_VERSION) return; + + //Get AmiTxt info data + gAmiTxtInfoProt->GetTxtInfo(gAmiTxtInfoProt, &AmiTxtInfoData); + + //Update setup string + if (AmiTxtInfoData->ChipsetIsProduction) { + InitString( + HiiHandle, + gSktStrTok[0].ChipsetFuse, + L"%a", + "Production Fused" + ); + } + + if (AmiTxtInfoData->ChipsetIsTxtCapable) { + InitString( + HiiHandle, + gSktStrTok[0].ChipsetTxtsupport, + L"%a", + "Supported" + ); + } + + if (AmiTxtInfoData->CpuIsTxtCapable) { + InitString( + HiiHandle, + gSktStrTok[0].CpuTxtsupport, + L"%a", + "Supported" + ); + } + + if (AmiTxtInfoData->TxtErrCode) { + InitString( + HiiHandle, + gSktStrTok[0].ErrorCode, + L"%x", + AmiTxtInfoData->TxtErrCode + ); + + InitString( + HiiHandle, + gSktStrTok[0].ClassCode, + L"%x", + (AmiTxtInfoData->TxtErrCode >> 4) & 0x3f //ErrorCode[9:4] + ); + + InitString( + HiiHandle, + gSktStrTok[0].MajorCode, + L"%x", + (AmiTxtInfoData->TxtErrCode >> 10) & 0x1f //ErrorCode[14:10] + ); + + InitString( + HiiHandle, + gSktStrTok[0].MinorCode, + L"%x", + (AmiTxtInfoData->TxtErrCode >> 16) & 0x1ff //ErrorCode[24:16] + ); + } +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/TxtDxe/AmiTxtInfoSetup.sd b/Board/CPU/TxtDxe/AmiTxtInfoSetup.sd new file mode 100644 index 0000000..b42126e --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtInfoSetup.sd @@ -0,0 +1,149 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/AmiTxtInfoSetup.sd 2 1/17/14 4:02a Crystallee $ +// +// $Revision: 2 $ +// +// $Date: 1/17/14 4:02a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: +// +// +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// Name: AmiTxtInfoSetup.sd.sd +// +// Description: Setup definition for Intel Txt Info. +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#ifdef SETUP_DATA_DEFINITION +/***********************************************************/ +/* Put NVRAM data definitions here. +/* For example: UINT8 Data1; +/* These definitions will be converted by the build process +/* to a definitions of SETUP_DATA fields. +/***********************************************************/ +// UINT8 XDBit; +#endif + +//--------------------------------------------------------------------------- +#if defined(VFRCOMPILE) && !defined(CONTROLS_ARE_DEFINED) +#define CONTROL_DEFINITION +#endif +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +#ifdef CONTROL_DEFINITION + +#endif //#ifdef CONTROL_DEFINITION + +#ifdef CONTROLS_WITH_DEFAULTS + +#endif //#ifdef CONTROLS_WITH_DEFAULTS + +#ifdef ADVANCED_FORM_SET + + #ifndef SUPPRESS_GRAYOUT_ENDIF + #define SUPPRESS_GRAYOUT_ENDIF endif; + #endif + + #ifdef FORM_SET_TYPEDEF + + #endif + + #ifdef FORM_SET_VARSTORE + + #endif + + #ifdef FORM_SET_ITEM + // Define controls to be added to the main page of the formset + #endif + + #ifdef FORM_SET_GOTO + // Define goto commands for the forms defined in this file + goto CPUTXT_FORM_ID, + prompt = STRING_TOKEN(STR_CPUTXT_FORM), + help = STRING_TOKEN(STR_CPUTXT_HELP); + #endif + + #ifdef FORM_SET_FORM + + + // Define forms + form formid = AUTO_ID(CPUTXT_FORM_ID), + title = STRING_TOKEN(STR_CPUTXT_FORM); + + SUBTITLE(STRING_TOKEN(STR_CPUTXT_FORM)) + SEPARATOR + + text + help = STRING_TOKEN(STR_CPUTXT_CHIP_FUSE_HELP), + text = STRING_TOKEN(STR_CPUTXT_CHIP_FUSE_STRING), + text = STRING_TOKEN(STR_CPUTXT_CHIP_FUSE_VALUE); + + text + help = STRING_TOKEN(STR_CPUTXT_CHIP_SUPPORT_HELP), + text = STRING_TOKEN(STR_CPUTXT_CHIP_SUPPORT_STRING), + text = STRING_TOKEN(STR_CPUTXT_CHIP_SUPPORT_VALUE); + + text + help = STRING_TOKEN(STR_CPUTXT_CPU_SUPPORT_HELP), + text = STRING_TOKEN(STR_CPUTXT_CPU_SUPPORT_STRING), + text = STRING_TOKEN(STR_CPUTXT_CPU_SUPPORT_VALUE); + + text + help = STRING_TOKEN(STR_CPUTXT_ERROR_CODE_HELP), + text = STRING_TOKEN(STR_CPUTXT_ERROR_CODE_STRING), + text = STRING_TOKEN(STR_CPUTXT_ERROR_CODE_VALUE); + + text + help = STRING_TOKEN(STR_CPUTXT_CLASS_CODE_HELP), + text = STRING_TOKEN(STR_CPUTXT_CLASS_CODE_STRING), + text = STRING_TOKEN(STR_CPUTXT_CLASS_CODE_VALUE); + + text + help = STRING_TOKEN(STR_CPUTXT_MAJOR_CODE_HELP), + text = STRING_TOKEN(STR_CPUTXT_MAJOR_CODE_STRING), + text = STRING_TOKEN(STR_CPUTXT_MAJOR_CODE_VALUE); + + text + help = STRING_TOKEN(STR_CPUTXT_MINOR_CODE_HELP), + text = STRING_TOKEN(STR_CPUTXT_MINOR_CODE_STRING), + text = STRING_TOKEN(STR_CPUTXT_MINOR_CODE_VALUE); + + endform; + #endif +#endif + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Board/CPU/TxtDxe/AmiTxtInfoSetup.uni b/Board/CPU/TxtDxe/AmiTxtInfoSetup.uni Binary files differnew file mode 100644 index 0000000..98de491 --- /dev/null +++ b/Board/CPU/TxtDxe/AmiTxtInfoSetup.uni diff --git a/Board/CPU/TxtDxe/Include/Protocol/AmiTxtInfo.h b/Board/CPU/TxtDxe/Include/Protocol/AmiTxtInfo.h new file mode 100644 index 0000000..b9986de --- /dev/null +++ b/Board/CPU/TxtDxe/Include/Protocol/AmiTxtInfo.h @@ -0,0 +1,117 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/Include/Protocol/AmiTxtInfo.h 2 4/10/15 3:11a Crystallee $ +// +// $Revision: 2 $ +// +// $Date: 4/10/15 3:11a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/Include/Protocol/AmiTxtInfo.h $ +// +// 2 4/10/15 3:11a Crystallee +// +// 1 1/17/14 3:47a Crystallee +// [TAG] None +// [Category] Improvement +// [Description] Show Txt information in setup->Advanced ->Intel Txt +// Information page. +// + +//********************************************************************** + +//<AMI_FHDR_START> +//--------------------------------------------------------------------------- +// +// Name: AmiTxtInfo.h +// +// Description: +// +//--------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#ifndef __AMI_TXT_INFO_H__ +#define __AMI_TXT_INFO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#define AMI_TXT_INFO_PROTOCOL_GUID \ + {0x1c92f0ab, 0x3351, 0x1be5, 0xaf, 0xba, 0xc1, 0x25, 0x61, 0xbb, 0x32, 0xa3} + +#define AMI_TXT_INFO_PROTOCOL_VERSION 1 + + +typedef struct { + BOOLEAN ChipsetIsTxtCapable; ///< Value is set to 1 if chipset is Intel TXT capable. + UINT64 SinitMemorySize; ///< Size of memory reserved for placement of SINIT module. This memory is used by MLE. + UINT64 TxtHeapMemorySize; ///< Size of memory reserved for TXT Heap. This memory is used by MLE. + EFI_PHYSICAL_ADDRESS TxtDprMemoryBase; ///< Base address of DPR protected memory reserved for Intel TXT component. + UINT64 TxtDprMemorySize; ///< Size of DPR protected memory reserved for TXT component + EFI_PHYSICAL_ADDRESS BiosAcmBase; ///< Base address of BIOS ACM in system firmware. Intel TXT reference code would skip searching the BIOS ACM in PEI firmware volume if the field is not zero. + EFI_PHYSICAL_ADDRESS McuUpdateDataAddr; ///< Base address of CPU micro code patch loaded into BSP. Intel TXT reference code would skip searching the micro code path in PEI firmware volume if the field is not zero. + EFI_PHYSICAL_ADDRESS SinitAcmBase; ///< Base address of SINIT module if installed in system firmware. Zero otherwise. + UINT64 TgaSize; ///< Size of Trusted Graphics Aperture if supported by chipset. + EFI_PHYSICAL_ADDRESS TxtLcpPdBase; ///< Base address of Platform Default Launch Control Policy data if installed in system firmware. Zero otherwise. + UINT64 TxtLcpPdSize; ///< Size of Platform Default Launch Control Policy data if installed in system firmware. Zero otherwise. + /** + Flags passed from BIOS to OS or MRC + - BIT0: FLAGS0 for compatible definition + - BIT1: TXT_CPU_RESET_REQUIRED for MRC to issue reset if required + - BIT2: TPM_INIT_FAILED for indicate TPM initiate status. If the bit set, ResetEstablishmentBit is skipped in Dxe driver. + **/ + UINT64 Flags; + // + BOOLEAN ChipsetIsProduction; ///<TRUE Production Fuse, FALSE Debug Fuse> + BOOLEAN BiosAcmIsProduction; ///<TRUE Production Fuse, FALSE Debug Fuse> + BOOLEAN CpuIsTxtCapable; + UINT32 TxtErrCode; +} AMI_TXT_INFO_DATA; + +typedef struct _AMI_TXT_INFO_PROTOCOL AMI_TXT_INFO_PROTOCOL; + +typedef EFI_STATUS (*GET_TXT_INFO) ( + IN AMI_TXT_INFO_PROTOCOL *AMI_TXT_INFO_PROTOCOL, + OUT VOID **AmiTxtInfoData +); + +struct _AMI_TXT_INFO_PROTOCOL { + //Protocol Ver 0 + UINT32 ProtocolVer; + UINT64 Flags; + GET_TXT_INFO GetTxtInfo; +}; +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_DBG_Rev1_5.BIN b/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_DBG_Rev1_5.BIN Binary files differnew file mode 100644 index 0000000..62c0f10 --- /dev/null +++ b/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_DBG_Rev1_5.BIN diff --git a/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_PRO_NPW_Rev1_5.BIN b/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_PRO_NPW_Rev1_5.BIN Binary files differnew file mode 100644 index 0000000..86ee7d9 --- /dev/null +++ b/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_PRO_NPW_Rev1_5.BIN diff --git a/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_PRO_Rev1_5.BIN b/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_PRO_Rev1_5.BIN Binary files differnew file mode 100644 index 0000000..e271644 --- /dev/null +++ b/Board/CPU/TxtDxe/SinitAcm/HSW_SINITAC_PRO_Rev1_5.BIN diff --git a/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.cif b/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.cif new file mode 100644 index 0000000..0ae3772 --- /dev/null +++ b/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.cif @@ -0,0 +1,12 @@ +<component> + name = "TxtSinitAcm" + category = ModulePart + LocalRoot = "Board\Cpu\TxtDxe\SinitAcm" + RefName = "TxtSinitAcm" +[files] +"TxtSinitAcm.sdl" +"TxtSinitAcm.mak" +"HSW_SINITAC_PRO_Rev1_5.BIN" +"HSW_SINITAC_PRO_NPW_Rev1_5.BIN" +"HSW_SINITAC_DBG_Rev1_5.BIN" +<endComponent> diff --git a/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.mak b/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.mak new file mode 100644 index 0000000..7f8daa5 --- /dev/null +++ b/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.mak @@ -0,0 +1,69 @@ +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#********************************************************************** + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/TxtSinitAcm/TxtSinitAcm.mak 1 8/14/13 4:35a Davidhsieh $ +# +# $Revision: 1 $ +# +# $Date: 8/14/13 4:35a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/TxtSinitAcm/TxtSinitAcm.mak $ +# +# 1 8/14/13 4:35a Davidhsieh +# [TAG] None +# [Category] New Feature +# [Description] Txt Sinit ACM is included in BIOS +# +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: Sinitacm.mak +# +# Description: +# +# +#<AMI_FHDR_END> +#********************************************************************** +all : SinitAcmBin + +#--------------------------------------------------------------------------- +# SINIT ACM +#--------------------------------------------------------------------------- + +SinitAcmBin : $(BUILD_DIR)\SinitAcmBin.ffs + +$(BUILD_DIR)\SinitAcmBin.ffs : $(SINITACM_FILE) + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=7fbfe0ea-0e9d-406b-a202-ca6a7d0e0f1e \ + TYPE=EFI_FV_FILETYPE_FREEFORM \ + BINFILE=$** FFSFILE=$@ COMPRESS=1 NAME=$(**B) + +#********************************************************************** +#********************************************************************** +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#********************************************************************** +#**********************************************************************
\ No newline at end of file diff --git a/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.sdl b/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.sdl new file mode 100644 index 0000000..bdb35b7 --- /dev/null +++ b/Board/CPU/TxtDxe/SinitAcm/TxtSinitAcm.sdl @@ -0,0 +1,32 @@ +TOKEN + Name = "SINIT_ACM_SUPPORT" + Value = "0" + Help = "Main switch to enable TXT BIOS AC Module support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "SINITACM_FILE" + Value = "Board\CPU\TxtDxe\SinitAcm\HSW_SINITAC_PRO_Rev1_5.BIN" + TokenType = File + TargetMAK = Yes +End + +PATH + Name = "SinitAcm_DIR" +End + +MODULE + Help = "Includes TxtSinitAcm.mak to Project" + File = "TxtSinitAcm.mak" +End + +ELINK + Name = "$(BUILD_DIR)\SinitAcmBin.ffs" + Parent = "FV_MAIN" + Token = "SINIT_ACM_SUPPORT" "=" "1" + InvokeOrder = AfterParent +End + diff --git a/Board/CPU/TxtDxe/TxtSetup.c b/Board/CPU/TxtDxe/TxtSetup.c new file mode 100644 index 0000000..2565714 --- /dev/null +++ b/Board/CPU/TxtDxe/TxtSetup.c @@ -0,0 +1,135 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/TxtSetup.c 2 10/14/12 11:49p Davidhsieh $ +// +// $Revision: 2 $ +// +// $Date: 10/14/12 11:49p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/TxtSetup.c $ +// +// 2 10/14/12 11:49p Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Use SBLib_ExtResetSystem when pRS->ResetSystem does not +// support GlobaRest type in the project +// +// 1 8/14/12 5:05a Davidhsieh +// [TAG] EIP97190 +// [Category] Improvement +// [Description] Changes in TXT Configuration require a Powercycle reset +// +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: TXTSetup.c +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +//---------------------------------------------------------------------------- +// Includes +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <Setup.h> +#include <AmiCspLib.h> +#include <SetupStrTokens.h> + +#pragma pack (1) +typedef struct { + UINT8 SMXSupport; +} SETUP_TXT_FEATURES; +#pragma pack () + +//---------------------------------------------------------------------------- +// Local Variables + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: TxtExitSetupEvent +// +// Description: This routine for calling global reset if necessary. +// +// Input: EFI_EVENT - Efi event. +// VOID* - Image handle. +// +// Output: None. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +typedef enum { + mColdReset, + mWarmReset, + mShutdownReset, + mPowerCycleReset, + mGlobalReset, + mGlobalResetWithEc +} PCH_RESET_TYPE; + +EFI_STATUS +TxtExitSetupEvent (VOID) +{ + EFI_STATUS Status; + SETUP_DATA SetupData; + UINTN VariableSize; + EFI_GUID SetupGuid = SETUP_GUID; + // Get current Setup Data. + VariableSize = sizeof(SETUP_DATA); + Status = pRS->GetVariable ( L"Setup", \ + &SetupGuid, \ + NULL, \ + &VariableSize, \ + &SetupData ); + if (EFI_ERROR(Status)) return (Status); + + if ( SetupData.TxtSupport != 0 ) { + // Generate Global Reset System if TXT is enabled w/o SMX enabled + if ((UINT16)(ReadMsr(0x3A) & 0xFF03) == 0xFF03) return EFI_SUCCESS; + } else { + // Generate Global Reset System if TXT is disabled with SMX enabled. + if ((UINT16)(ReadMsr(0x3A) & 0xFF03) != 0xFF03) return EFI_SUCCESS; + } + // PlatformResetSystem() of ReferenceCode\ME\..\PlatformReset.c +#if defined(RESET_RUNTIME_SERVICES_SUPPORT) && (RESET_RUNTIME_SERVICES_SUPPORT == 0) + pRS->ResetSystem (mGlobalReset, EFI_SUCCESS, 0, NULL); +#else + SBLib_ExtResetSystem (SbResetGlobal); +#endif + EFI_DEADLOOP() + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Board/CPU/TxtDxe/TxtTcgService.h b/Board/CPU/TxtDxe/TxtTcgService.h new file mode 100644 index 0000000..8d6ad53 --- /dev/null +++ b/Board/CPU/TxtDxe/TxtTcgService.h @@ -0,0 +1,277 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2009, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/TxtTcgService.h 1 7/18/12 2:07a Davidhsieh $ +// +// $Revision: 1 $ +// +// $Date: 7/18/12 2:07a $ +// +//********************************************************************** +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT DXE/TxtTcgService.h $ +// +// 1 7/18/12 2:07a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] AMI TXT Dxe module part create +// +// 1 2/25/11 3:55a Hpbirdchen +// Initial 0.5 RC Check-in +// +// 1 12/01/10 11:11p Calvinchen +// +// 2 10/05/25 3:07p Calvinchen +// +// 4 7/27/09 7:12a Calvinchen +// TXT module uses internal TPM startup procedure instead of TCG +// library.(EIP#20424) +// +// 3 6/24/09 12:10a Calvinchen +// (EIP#22177)Updated for Aptio Source Enhancement. +// +// +//********************************************************************** +// +// Statements that include other header files. +// +typedef struct _EFI_TCG_PROTOCOL EFI_TCG_PROTOCOL; +typedef struct _EFI_TPM_DEVICE_PROTOCOL EFI_TPM_DEVICE_PROTOCOL; +typedef UINT16 TPM_STRUCTURE_TAG; +typedef UINT16 TPM_TAG; +typedef UINT32 TPM_COMMAND_CODE; +typedef UINT32 TPM_RESULT; +typedef UINT16 TPM_STARTUP_TYPE; + +// The TPM is starting up from a clean state +#define TPM_ST_CLEAR ((TPM_STARTUP_TYPE) 0x0001) +#define ST_CLEAR 0 +// The TPM is starting up from a saved state +#define TPM_ST_STATE ((TPM_STARTUP_TYPE) 0x0002) +#define ST_STATE 1 +#define TPM_ORD_Startup ((TPM_COMMAND_CODE) 0x00000099) +#define TPM_ORD_ContinueSelfTest ((TPM_COMMAND_CODE) 0x00000053) +#define TPM_ORD_NV_READVALUE ((TPM_COMMAND_CODE) 0x000000CF) // 207 +#define TPM_ORD_NV_WRITEVALUE ((TPM_COMMAND_CODE) 0x000000CD) // 205 +#define TPM_ORD_NV_DEFINESPACE ((TPM_COMMAND_CODE) 0x000000CC) // 204 +#define TPM_ORD_VERIFY 0x020000001 +#define TPM_NV_INDEX_LOCK 0x0FFFFFFFF +#define TPM_TAG_RQU_COMMAND ((TPM_STRUCTURE_TAG) 0x00C1) +#define TPM_TAG_RQU_AUTH1_COMMAND ((TPM_STRUCTURE_TAG) 0x00C2) +#define EFI_TCG_PROTOCOL_GUID \ + {0xf541796d, 0xa62e, 0x4954, 0xa7, 0x75, 0x95, 0x84, 0xf6, 0x1b, 0x9c, 0xdd} +#define EFI_TPM_DEVICE_PROTOCOL_GUID \ + { 0xde161cfe, 0x1e60, 0x42a1, 0x8c, 0xc3, 0xee, 0x7e, 0xf0, 0x73, 0x52, 0x12 } +#define TPM_H2NS(x) \ + (((UINT16)(x) << 8) | ((UINT16)(x) >> 8)) +#define TPM_H2NL(x) \ + (UINT32)((((UINT32)(x)) >> 24) | \ + (((x) >> 8) & 0xff00) | \ + ((x) << 24) | \ + (((x) & 0xff00) << 8)) +//---------------------------------------------------------------------------- +// NVram definition +//---------------------------------------------------------------------------- +#pragma pack (push) +#pragma pack (1) + +typedef struct _TCPA_DIGEST { + UINT8 digest[20]; +} TCPA_DIGEST; + +typedef struct _TPM_PCR_SELECTION { + UINT16 sizeOfSelect; + UINT8 pcrSelect[3]; +} TPM_PCR_SELECTION; + +typedef struct _TPM_PCR_INFO_SHORT { +//- TPM_PCR_SELECTION pcrSelection; + UINT16 sizeOfSelect; + UINT8 pcrSelect[3]; + UINT8 localityAtRelease; + TCPA_DIGEST digestAtRelease; +} TPM_PCR_INFO_SHORT; + +typedef struct _TPM_NV_ATTRIBUTES { + UINT16 tag; + UINT32 attributes; +} TPM_NV_ATTRIBUTES; + +typedef struct _TPM_NV_DATA_PUBLIC1 { + UINT16 Tag_; + UINT32 NvIndex; + TPM_PCR_INFO_SHORT PcrInfoRead; +} TPM_NV_DATA_PUBLIC1; + +typedef struct _TPM_NV_DATA_PUBLIC2 { + TPM_PCR_INFO_SHORT PcrInfoWrite; + TPM_NV_ATTRIBUTES PerMission; + UINT8 bReadSTClear; + UINT8 bWriteSTClear; + UINT8 bWriteDefine; + UINT32 DataSize; +} TPM_NV_DATA_PUBLIC2; + +typedef struct _TPM_DEF_NV_DATA { + TPM_NV_DATA_PUBLIC1 TpmDefineSpaceIn_pubinfo1; + TPM_NV_DATA_PUBLIC2 TpmDefineSpaceIn_pubinfo2; + TCPA_DIGEST TpmDefineSpaceIn_encAuth; +} TPM_DEF_NV_DATA; + +//---------------------------------------------------------------------------- +// TCG definition +//---------------------------------------------------------------------------- +typedef struct _TPM_1_2_CMD_HEADER { + TPM_TAG Tag; + UINT32 ParamSize; + TPM_COMMAND_CODE Ordinal; +} TPM_1_2_CMD_HEADER; + +typedef struct _TPM_1_2_RET_HEADER { + TPM_TAG Tag; + UINT32 ParamSize; + TPM_RESULT RetCode; +} TPM_1_2_RET_HEADER; + +typedef struct _TPM_1_2_CMD_STARTUP { + TPM_1_2_CMD_HEADER Header; + TPM_STARTUP_TYPE StartupType; +} TPM_1_2_CMD_STARTUP; + +typedef struct _TPM_1_2_REGISTERS { + UINT8 Access; // 0 + UINT8 Reserved1[7]; // 1 + UINT32 IntEnable; // 8 + UINT8 IntVector; // 0ch + UINT8 Reserved2[3]; // 0dh + UINT32 IntSts; // 10h + UINT32 IntfCapability; // 14h + UINT8 Sts; // 18h + UINT16 BurstCount; // 19h + UINT8 Reserved3[9]; + UINT32 DataFifo; // 24h + UINT8 Reserved4[0xed8]; // 28h + UINT16 Vid; // 0f00h + UINT16 Did; // 0f02h + UINT8 Rid; // 0f04h + UINT8 TcgDefined[0x7b]; // 0f05h + UINT32 LegacyAddress1; // 0f80h + UINT32 LegacyAddress1Ex; // 0f84h + UINT32 LegacyAddress2; // 0f88h + UINT32 LegacyAddress2Ex; // 0f8ch + UINT8 VendorDefined[0x70];// 0f90h +} TPM_1_2_REGISTERS; + +#pragma pack (pop) + +typedef EFI_STATUS (EFIAPI *EFI_TCG_STATUS_CHECK) ( +//- IN EFI_TCG_PROTOCOL *This, +//- OUT TCG_EFI_BOOT_SERVICE_CAPABILITY +//- *ProtocolCapability, +//- OUT UINT32 *TCGFeatureFlags, +//- OUT EFI_PHYSICAL_ADDRESS *EventLogLocation, +//- OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry +); + +typedef EFI_STATUS (EFIAPI *EFI_TCG_HASH_ALL) ( +//- IN EFI_TCG_PROTOCOL *This, +//- IN UINT8 *HashData, +//- IN UINT64 HashDataLen, +//- IN TCG_ALGORITHM_ID AlgorithmId, +//- IN OUT UINT64 *HashedDataLen, +//- IN OUT UINT8 **HashedDataResult +); + +typedef EFI_STATUS (EFIAPI *EFI_TCG_LOG_EVENT) ( +//- IN EFI_TCG_PROTOCOL *This, +//- IN TCG_PCR_EVENT *TCGLogData, +//- IN OUT UINT32 *EventNumber, +//- IN UINT32 Flags +); + +typedef EFI_STATUS (EFIAPI *EFI_TCG_PASS_THROUGH_TO_TPM) ( + IN EFI_TCG_PROTOCOL *This, + IN UINT32 TpmInputParamterBlockSize, + IN UINT8 *TpmInputParamterBlock, + IN UINT32 TpmOutputParameterBlockSize, + IN UINT8 *TpmOutputParameterBlock + ); + +typedef EFI_STATUS (EFIAPI *EFI_TCG_HASH_LOG_EXTEND_EVENT) ( +//- IN EFI_TCG_PROTOCOL *This, +//- IN UINT8 *HashData, +//- IN UINT64 HashDataLen, +//- IN TCG_ALGORITHM_ID AlgorithmId, +//- IN OUT TCG_PCR_EVENT *TCGLogData, +//- IN OUT UINT32 *EventNumber, +//- OUT EFI_PHYSICAL_ADDRESS *EventLogLastEntry +); + +typedef struct _EFI_TCG_PROTOCOL { + EFI_TCG_STATUS_CHECK StatusCheck; + EFI_TCG_HASH_ALL HashAll; + EFI_TCG_LOG_EVENT LogEvent; + EFI_TCG_PASS_THROUGH_TO_TPM PassThroughToTpm; + EFI_TCG_HASH_LOG_EXTEND_EVENT HashLogExtendEvent; +} EFI_TCG_PROTOCOL; + +typedef EFI_STATUS (EFIAPI *EFI_TPM_MP_INIT) ( + IN EFI_TPM_DEVICE_PROTOCOL *This + ); + +typedef EFI_STATUS (EFIAPI *EFI_TPM_MP_CLOSE) ( + IN EFI_TPM_DEVICE_PROTOCOL *This + ); + +typedef EFI_STATUS (EFIAPI *EFI_TPM_MP_GET_STATUS_INFO) ( + IN EFI_TPM_DEVICE_PROTOCOL *This + ); + +typedef EFI_STATUS (EFIAPI *EFI_TPM_MP_TRANSMIT) ( +//- IN EFI_TPM_DEVICE_PROTOCOL *This, +//- IN UINTN NoInBuffers, +//- IN TPM_TRANSMIT_BUFFER *InBuffers, +//- IN UINTN NoOutBuffers, +//- IN OUT TPM_TRANSMIT_BUFFER *OutBuffers + ); + +typedef struct _EFI_TPM_DEVICE_PROTOCOL { + EFI_TPM_MP_INIT Init; + EFI_TPM_MP_CLOSE Close; + EFI_TPM_MP_GET_STATUS_INFO GetStatusInfo; + EFI_TPM_MP_TRANSMIT Transmit; +} EFI_TPM_DEVICE_PROTOCOL; + +typedef struct _TPM_TRANSMIT_BUFFER { + VOID *Buffer; + UINTN Size; +} TPM_TRANSMIT_BUFFER; +typedef volatile TPM_1_2_REGISTERS *TPM_1_2_REGISTERS_PTR; + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2009, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/TxtPei/AmiTxtPei.c b/Board/CPU/TxtPei/AmiTxtPei.c new file mode 100644 index 0000000..5081caa --- /dev/null +++ b/Board/CPU/TxtPei/AmiTxtPei.c @@ -0,0 +1,164 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//********************************************************************** +// $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT PEI/AmiTxtPei.c 5 6/11/15 10:32p Crystallee $ +// +// $Revision: 5 $ +// +// $Date: 6/11/15 10:32p $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT PEI/AmiTxtPei.c $ +// +// 5 6/11/15 10:32p Crystallee +// [TAG] EIP207854 +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Txt test fail with TCG2 module +// [RootCause] Tokne TCG_SUPPORT was removed. +// [Solution] Add TCG2Support token. +// +// 4 4/10/15 3:17a Crystallee +// +// 3 9/13/12 4:15a Davidhsieh +// [TAG] None +// [Category] Bug Fix +// [Severity] Important +// [Symptom] Disable TCG support causes BIOS buiding error +// [RootCause] TCG setup data is used in TxtDxe and the data is not +// exist when TCG disabled. +// [Solution] Do not use TCG setup data when TCG disabled. +// +// 2 8/22/12 3:29a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] Install TPM_INITIALIZED_PPI when TPM device is present +// TPM enabled in setup +// +// 1 7/18/12 2:09a Davidhsieh +// [TAG] None +// [Category] Improvement +// [Description] AMI TXT PEI module part create +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: AmiTxtPei.c +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +// +#include <PEI.h> +#include <AmiPeiLib.h> +#include <AmiCspLib.h> +#include <ppi\ReadOnlyVariable.h> +#include <Setup.h> +#include <token.h> + +#define PEI_TPM_INITIALIZED_PPI_GUID \ + { \ + 0xe9db0d58, 0xd48d, 0x47f6, 0x9c, 0x6e, 0x6f, 0x40, 0xe8, 0x6c, 0x7b, 0x41 \ + } + +static EFI_GUID gPeiTpmInitializedPpiGuid = PEI_TPM_INITIALIZED_PPI_GUID; +static EFI_GUID gEfiPeiReadOnlyVariablePpiGuid = EFI_PEI_READ_ONLY_VARIABLE_PPI_GUID; +static EFI_GUID gEfiSetupGuid = SETUP_GUID; + +static EFI_PEI_PPI_DESCRIPTOR Tpm_Initialized[] = +{ + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gPeiTpmInitializedPpiGuid, NULL + } +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AmiTxtPeiEntry +// +// Description: PEI Entry Point for Intel TXT Driver. +// +// Input: EFI_HANDLE - ImageHandle +// EFI_SYSTEM_TABLE* - SystemTable +// +// Output: None. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +AmiTxtPeiEntry ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices +) +{ + + UINT8 *TpmBaseAddr = (UINT8*)0xfed40000; + EFI_PEI_READ_ONLY_VARIABLE_PPI *ReadOnlyVariable; + EFI_STATUS Status; + UINTN VariableSize; + + SETUP_DATA SetupData; + + if (*TpmBaseAddr != 0xff){ //If TPM device is present, check TPM setup data + Status = (*PeiServices)->LocatePpi( + PeiServices, + &gEfiPeiReadOnlyVariablePpiGuid, + 0, + NULL, + &ReadOnlyVariable + ); + + if (EFI_ERROR(Status)) return EFI_SUCCESS; + + VariableSize = sizeof(SETUP_DATA); + + Status = ReadOnlyVariable->GetVariable( + PeiServices, + L"Setup", + &gEfiSetupGuid, + NULL, + &VariableSize, + &SetupData + ); + + if ( EFI_ERROR(Status) ) return EFI_SUCCESS; + +#if TCG_SUPPORT || TCG2Support + if (SetupData.TpmSupport) + (*PeiServices)->InstallPpi(PeiServices, Tpm_Initialized); //Install PPI if TPM device detected and enable in setup +#endif + } + + return EFI_SUCCESS; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1987-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/CPU/TxtPei/AmiTxtPei.cif b/Board/CPU/TxtPei/AmiTxtPei.cif new file mode 100644 index 0000000..e790995 --- /dev/null +++ b/Board/CPU/TxtPei/AmiTxtPei.cif @@ -0,0 +1,10 @@ +<component> + name = "AMI TXT Pei" + category = ModulePart + LocalRoot = "Board\Cpu\TxtPei" + RefName = "AmiTxtPei" +[files] +"AmiTxtPei.sdl" +"AmiTxtPei.mak" +"AmiTxtPei.c" +<endComponent> diff --git a/Board/CPU/TxtPei/AmiTxtPei.mak b/Board/CPU/TxtPei/AmiTxtPei.mak new file mode 100644 index 0000000..7e65c25 --- /dev/null +++ b/Board/CPU/TxtPei/AmiTxtPei.mak @@ -0,0 +1,69 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT PEI/AmiTxtPei.mak 1 7/18/12 2:09a Davidhsieh $ +# +# $Revision: 1 $ +# +# $Date: 7/18/12 2:09a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT PEI/AmiTxtPei.mak $ +# +# 1 7/18/12 2:09a Davidhsieh +# [TAG] None +# [Category] Improvement +# [Description] AMI TXT PEI module part create +# +# +#********************************************************************** +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: AmiTxtPei.mak +# +# Description: Makefile for AmiTxtPei module. +# +#<AMI_FHDR_END> +#********************************************************************** + +all : AmiTxtPei + +AmiTxtPei: $(BUILD_DIR)\AmiTxtPei.mak AmiTxtPeiBin + +$(BUILD_DIR)\AmiTxtPei.mak : $(AmiTxtPei_DIR)\$(@B).cif $(AmiTxtPei_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(AmiTxtPei_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +AmiTxtPeiBin : $(AMIPEILIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\AmiTxtPei.mak all\ + MAKEFILE=$(BUILD_DIR)\AmiTxtPei.mak \ + GUID=C7D4BBCF-EB0A-4C91-BD8B-FCA99F28B011 \ + ENTRY_POINT=AmiTxtPeiEntry\ + TYPE=PEIM \ + COMPRESS=0 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/CPU/TxtPei/AmiTxtPei.sdl b/Board/CPU/TxtPei/AmiTxtPei.sdl new file mode 100644 index 0000000..7f6c65c --- /dev/null +++ b/Board/CPU/TxtPei/AmiTxtPei.sdl @@ -0,0 +1,71 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT PEI/AmiTxtPei.sdl 1 7/18/12 2:09a Davidhsieh $ +# +# $Revision: 1 $ +# +# $Date: 7/18/12 2:09a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/SOURCE/Modules/SharkBayRefCodes/Haswell/AMI Cpu PKG/AMI TXT PEI/AmiTxtPei.sdl $ +# +# 1 7/18/12 2:09a Davidhsieh +# [TAG] None +# [Category] Improvement +# [Description] AMI TXT PEI module part create +# +# +#********************************************************************** +TOKEN + Name = "AMI_TXT_PEI_SUPPORT" + Value = "1" + Help = "Main switch to enable AMI TXT PEI support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "AmiTxtPei_DIR" +End + +MODULE + Help = "Includes TxtDxe.mak to Project" + File = "AmiTxtPei.mak" +End + +ELINK + Name = "$(BUILD_DIR)\AmiTxtPei.ffs" + Parent = "FV_BB" + Help = "Intel Txt PEI component" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1987-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* |