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authorraywu <raywu0301@gmail.com>2018-06-15 00:00:50 +0800
committerraywu <raywu0301@gmail.com>2018-06-15 00:00:50 +0800
commitb7c51c9cf4864df6aabb99a1ae843becd577237c (patch)
treeeebe9b0d0ca03062955223097e57da84dd618b9a /Board/EM/Thunderbolt/TbtOemBoard
downloadzprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz
init. 1AQQW051HEADmaster
Diffstat (limited to 'Board/EM/Thunderbolt/TbtOemBoard')
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.c415
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.cif17
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs48
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.h328
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.mak95
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl495
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.c1298
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.h216
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtOemPorting.asl13
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c172
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.cif14
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h70
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak89
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd1456
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl386
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.unibin0 -> 29314 bytes
-rw-r--r--Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c243
17 files changed, 5355 insertions, 0 deletions
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.c b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.c
new file mode 100644
index 0000000..ce78068
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.c
@@ -0,0 +1,415 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.c 7 5/19/14 7:38a Barretlin $
+//
+// $Revision: 7 $
+//
+// $Date: 5/19/14 7:38a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.c $
+//
+// 7 5/19/14 7:38a Barretlin
+// [TAG] EIP165410
+// [Category] New Feature
+// [Description] Support Thunderbolt AIC at NB PCIE slot
+// [Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+//
+// 6 5/19/14 7:15a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Using setup item choose return value of _RMV method in
+// ASL code
+// [Files] TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+//
+// 5 2/18/14 2:12a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Release PCIE root port control when Thunderbolt
+// function disable in run time
+// [Files] TbtOemBoard.c
+//
+// 4 2/10/14 1:26p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] remove useless policy item and setup item
+// [Files] TbtOemBoard.h TbtOemBoard.c TbSetup.sdl TbtSetup.sd
+// TbtSetup.uni TbtSmm.c
+//
+// 3 1/05/14 2:06p Barretlin
+// [TAG] EIP N/A
+// [Category] New Feature
+// [Description] Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files] TbtOemBoard.h TbtOemBoard.c TbtOemLib.c TbtOemLib.h
+//
+// 2 6/17/13 2:18a Barretlin
+// [TAG] EIP126581
+// [Category] Improvement
+// [Description] add new AIC support setup item and change
+// TBWakeupSupport name
+// [Files] TbtOemBoard.h TbtOemBoard.c
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 12 12/12/12 4:14a Barretlin
+// [TAG] EIP108272
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Update to Spec 1.4 to support Redwood Ridge chip
+// [Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 11 10/28/12 11:50p Barretlin
+// [TAG] EIP104870
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files] TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+//
+// 10 10/28/12 11:21p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Create new setup item for thunderbolt POC handling
+// [Files] TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl TbtSetup.sd
+// TbtSetup.uni
+//
+// 9 9/22/12 9:59a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Use token to defien thunderbolt chip pins and update
+// sample code
+// [Files] TbtOemBoard.c TbtOemBoard.sdl
+//
+// 8 8/20/12 5:12a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix IO resource workaround broken in 4C 2port case
+// [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+//
+// 7 8/17/12 8:44a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Add IO resource workaround for Thunderbolt Spec1.1
+// Because new spec has removed IO resource for Thunderbolt device
+// [Files] TbtSmm.c TbtOemBoard.h TbtOemBoard.c TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+//
+// 6 7/31/12 4:07a Barretlin
+// [TAG] EIP96350
+// [Category] Spec Update
+// [Severity] Critical
+// [Description] Updated Thunderbolt specification to version 1.00
+// [Files] TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+//
+// 5 7/31/12 3:15a Barretlin
+// [TAG] EIP91119
+// [Category] Improvement
+// [Description] Resolution for enable/disable Thunderbolt device option
+// rom at POST time
+// [Files] TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 4 5/22/12 10:00a Barretlin
+// [TAG] EIP90650
+// [Category] Spec Update
+// [Description] Specificatoin Update 0.94 - The default value of
+// OPTIONAL workaround for devices that don't support surprise-removal
+// should be disable.
+// [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 3 5/07/12 7:00a Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Add three setup items for debug
+// [Files] TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+//
+// 2 2/20/12 12:01a Wesleychen
+// - Add new policy "SmiNotifyEnabled".
+// - Move OemProgramTbtSecurityLevel() to TbtDxe.c.
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//*************************************************************************
+#include <Efi.h>
+#include <token.h>
+#include <Setup.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+#include <TbtOemLib.h>
+#include <TbtOemBoard.h>
+
+// GUID Definition(s)
+EFI_GUID AmiTbtPlatformPpolicyGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+EFI_GUID TbtHRStatusGuid = AMI_TBT_HR_STATUS_GUID;
+EFI_GUID SetupGuid = SETUP_GUID;
+
+// Variable Declaration(s)
+AMI_TBT_PLATFORM_POLICY_PROTOCOL gTbtPlatformPolicy;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: TbtOemBoard_Init
+//
+// Description: This function is the entry point for TbtOemBoard.
+//
+// Input: ImageHandle - Image handle
+// SystemTable - Pointer to the system table
+//
+// Output: Return Status based on errors that occurred while waiting for
+// time to expire.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtOemBoard_Init (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable )
+{
+ //
+ // OEM Porting is required.
+ //
+ EFI_STATUS Status = EFI_SUCCESS;
+ EFI_HANDLE Handle = NULL;
+ UINTN VariableSize = sizeof(SETUP_DATA);
+ UINTN HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+ UINT32 Attributes;
+ UINT16 counter;
+ UINT8 TbtSetVariableFlag = 0;
+ CHAR16 TbtHRStatusVar[] = TBT_HR_STATUS_VARIABLE;
+ AMI_TBT_HR_STATUS_DATA HRStatusData;
+ SETUP_DATA SetupData;
+
+ InitAmiLib(ImageHandle, SystemTable);
+
+ //Initial Host Router information
+ Status = pRS->GetVariable( L"TbtHRStatusVar", \
+ &TbtHRStatusGuid, \
+ NULL, \
+ &HRStatusSize, \
+ &HRStatusData );
+ if (EFI_ERROR(Status)){
+ TRACE((-1, "TbtOemBoard: Can not get Thunderbolt Host Router Information !!! \n"));
+ HRStatusData.TbtHRStatus = 0;
+ //Get Thunderbolt host Series
+ HRStatusData.TbtHRSeries = GetHRInfo();
+ TRACE((-1, "TbtOemBoard: Thunderbolt Host Router Chip: %x \n", HRStatusData.TbtHRSeries));
+
+ Status = pRS->SetVariable( TbtHRStatusVar, \
+ &TbtHRStatusGuid, \
+ EFI_VARIABLE_NON_VOLATILE | \
+ EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+ EFI_VARIABLE_RUNTIME_ACCESS, \
+ HRStatusSize, \
+ &HRStatusData );
+ if (!EFI_ERROR(Status))
+ TRACE((-1, "TbtOemBoard: Create Thunderbolt Host Router Information !!! \n"));
+ }
+
+ Status = pRS->GetVariable( L"Setup", \
+ &SetupGuid, \
+ &Attributes, \
+ &VariableSize, \
+ &SetupData );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = pBS->AllocatePool( \
+ EfiBootServicesData, \
+ sizeof(AMI_TBT_PLATFORM_POLICY_PROTOCOL), \
+ (VOID**)&gTbtPlatformPolicy );
+ ASSERT_EFI_ERROR (Status);
+
+ TRACE((-1, "TbtOemBoard: Start install Thunderbolt Platform Policy !!! \n"));
+ pBS->SetMem( &gTbtPlatformPolicy, sizeof(AMI_TBT_PLATFORM_POLICY_PROTOCOL), 0 );
+
+ //
+ // OEM Porting required.
+ //
+/* Sample Code
+ gTbtPlatformPolicy.TbtEnable = SetupData.TbtEnable;
+ gTbtPlatformPolicy.TbtGO2SX = TBT_GO2SX;
+ gTbtPlatformPolicy.TbtForcePWR = TBT_ForcePWR;
+ gTbtPlatformPolicy.TbtHotPlugEvt = TBT_HotPlugEvt;
+ gTbtPlatformPolicy.TbtOK2GO2SX_N = TBT_OK2GO2SX_N;
+ gTbtPlatformPolicy.CacheLineSize = SetupData.TbtCacheLineSize;
+ gTbtPlatformPolicy.TbtWakeupSupport = SetupData.TbtWakeupSupport;
+ gTbtPlatformPolicy.TbtAICSupport = SetupData.TbtAICSupport;
+ gTbtPlatformPolicy.TbtHandlePOC = SetupData.TbtHandlePOC;
+ gTbtPlatformPolicy.TbtSecurityLevel = SetupData.TbtSecurityLevel;
+ gTbtPlatformPolicy.Bus = TBT_UP_PORT_BUS;
+ gTbtPlatformPolicy.Dev = TBT_UP_PORT_DEV;
+ if (gTbtPlatformPolicy.TbtAICSupport == 1){
+ if (SetupData.TbtHostLocation < 0x20){
+ gTbtPlatformPolicy.Fun = SetupData.TbtHostLocation;
+ } else {
+ gTbtPlatformPolicy.Dev = 0x01;
+ gTbtPlatformPolicy.Fun = (SetupData.TbtHostLocation) - 0x20;
+ }
+ } else {
+ gTbtPlatformPolicy.Fun = TBT_UP_PORT_FUNC;
+ }
+ gTbtPlatformPolicy.ReserveMemoryPerSlot = SetupData.ReserveMemoryPerSlot;
+ gTbtPlatformPolicy.ReservePMemoryPerSlot = SetupData.ReservePMemoryPerSlot;
+ gTbtPlatformPolicy.ReserveIOPerSlot = SetupData.ReserveIOPerSlot;
+ gTbtPlatformPolicy.SmiNotifyEnabled = SetupData.SmiNotifyEnabled;
+ gTbtPlatformPolicy.SwSmiEnabled = SetupData.SwSmiEnabled;
+ gTbtPlatformPolicy.NotifyEnabled = SetupData.NotifyEnabled;
+ gTbtPlatformPolicy.TbtOptionRom = SetupData.TbtOptionRom;
+ gTbtPlatformPolicy.TbtRmvReturnValue = SetupData.TbtRmvReturnValue;
+ gTbtPlatformPolicy.TbtIOresourceEnable = SetupData.TbtIOresourceEnable;
+ gTbtPlatformPolicy.TbtNVMversion = SetupData.TbtNVMversion;
+
+ Status = pBS->InstallProtocolInterface (
+ &Handle,
+ &AmiTbtPlatformPpolicyGuid,
+ EFI_NATIVE_INTERFACE,
+ &gTbtPlatformPolicy
+ );
+ ASSERT_EFI_ERROR (Status);
+//*/
+ //synchronize Thunderbolt Host Router Information with Setup Data
+ if (HRStatusData.TbtHRSeries != SetupData.TbtHRSeries){
+ TRACE((-1, "TbtOemBoard: Setting Thunderbolt Host Router Information into Setup Data!!! \n"));
+ SetupData.TbtHRSeries = HRStatusData.TbtHRSeries;
+ TbtSetVariableFlag |= 1;
+ }
+
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+ if (gTbtPlatformPolicy.TbtEnable){
+ if (gTbtPlatformPolicy.TbtAICSupport){
+ if ((gTbtPlatformPolicy.Bus == 0) && (gTbtPlatformPolicy.Dev == 0x1C))
+ { // Thunderbolt AIC is at SB PCIE root port
+ if ((SetupData.PcieMemRsvd[gTbtPlatformPolicy.Fun] != 353) || \
+ (SetupData.PcieMemRsvd[gTbtPlatformPolicy.Fun] != 737)){
+ // Change PCIE root port resource to correct location
+ SetupData.PcieRootPortEn[gTbtPlatformPolicy.Fun] = 1;
+ SetupData.PcieRootPortHPE[gTbtPlatformPolicy.Fun] = 1;
+ SetupData.ExtraBusRsvd[gTbtPlatformPolicy.Fun] = TBT_DEFAULT_EXTRA_BUS_RESERVED;
+ SetupData.PcieMemRsvd[gTbtPlatformPolicy.Fun] = TBT_DEFAULT_PCIE_MEM_RESERVED;
+ SetupData.PcieMemRsvdalig[gTbtPlatformPolicy.Fun] = 26;
+ SetupData.PciePFMemRsvd[gTbtPlatformPolicy.Fun] = TBT_DEFAULT_PCIE_PF_MEM_RESERVED;
+ SetupData.PciePFMemRsvdalig[gTbtPlatformPolicy.Fun] = 28;
+ SetupData.PcieIoRsvd[gTbtPlatformPolicy.Fun] = TBT_DEFAULT_PCIE_IO_RESERVED;
+
+ // Double check resource on other PCIE root port is disable
+ for(counter=0;counter<=7;counter++){
+ if(counter != gTbtPlatformPolicy.Fun){
+ if((SetupData.PcieMemRsvd[counter] == 353) || \
+ (SetupData.PcieMemRsvd[counter] == 737))
+ {
+ SetupData.PcieRootPortHPE[counter] = 0;
+ SetupData.ExtraBusRsvd[counter] = 0;
+ SetupData.PcieMemRsvd[counter] = 10;
+ SetupData.PcieMemRsvdalig[counter] = 1;
+ SetupData.PciePFMemRsvd[counter] = 10;
+ SetupData.PciePFMemRsvdalig[counter] = 1;
+ SetupData.PcieIoRsvd[counter] = 4;
+ }
+ } // counter != gTbtPlatformPolicy.Fun
+ } // for loop
+
+ TbtSetVariableFlag |= 1;
+ } // PCIE root port resource is at incorrect location
+ } else {
+ // Thunderbolt AIC is at NB PCIE root port
+ // Double check resource on other PCIE root port is disable
+ for(counter=0;counter<=7;counter++){
+ if((SetupData.PcieMemRsvd[counter] == 353) || \
+ (SetupData.PcieMemRsvd[counter] == 737))
+ {
+ SetupData.PcieRootPortHPE[counter] = 0;
+ SetupData.ExtraBusRsvd[counter] = 0;
+ SetupData.PcieMemRsvd[counter] = 10;
+ SetupData.PcieMemRsvdalig[counter] = 1;
+ SetupData.PciePFMemRsvd[counter] = 10;
+ SetupData.PciePFMemRsvdalig[counter] = 1;
+ SetupData.PcieIoRsvd[counter] = 4;
+
+ TbtSetVariableFlag |= 1;
+ }
+ } // for loop
+ }
+ } else {
+ if ((SetupData.PcieMemRsvd[TBT_UP_PORT_FUNC] != 353) || \
+ (SetupData.PcieMemRsvd[TBT_UP_PORT_FUNC] != 737))
+ {
+ SetupData.TbtHostLocation = TBT_UP_PORT_FUNC;
+ SetupData.PcieRootPortEn[TBT_UP_PORT_FUNC] = 1;
+ SetupData.PcieRootPortHPE[TBT_UP_PORT_FUNC] = 1;
+ SetupData.ExtraBusRsvd[TBT_UP_PORT_FUNC] = TBT_DEFAULT_EXTRA_BUS_RESERVED;
+ SetupData.PcieMemRsvd[TBT_UP_PORT_FUNC] = TBT_DEFAULT_PCIE_MEM_RESERVED;
+ SetupData.PcieMemRsvdalig[TBT_UP_PORT_FUNC] = 26;
+ SetupData.PciePFMemRsvd[TBT_UP_PORT_FUNC] = TBT_DEFAULT_PCIE_PF_MEM_RESERVED;
+ SetupData.PciePFMemRsvdalig[TBT_UP_PORT_FUNC] = 28;
+ SetupData.PcieIoRsvd[TBT_UP_PORT_FUNC] = TBT_DEFAULT_PCIE_IO_RESERVED;
+
+ // Double check resource on other PCIE root port is disable
+ for(counter=0;counter<=7;counter++){
+ if(counter != TBT_UP_PORT_FUNC){
+ if((SetupData.PcieMemRsvd[counter] == 353) || (SetupData.PcieMemRsvd[counter] == 737)){
+ SetupData.PcieRootPortHPE[counter] = 0;
+ SetupData.ExtraBusRsvd[counter] = 0;
+ SetupData.PcieMemRsvd[counter] = 10;
+ SetupData.PcieMemRsvdalig[counter] = 1;
+ SetupData.PciePFMemRsvd[counter] = 10;
+ SetupData.PciePFMemRsvdalig[counter] = 1;
+ SetupData.PcieIoRsvd[counter] = 4;
+ }
+ } // counter != TBT_UP_PORT_FUNC
+ } // for loop
+
+ TbtSetVariableFlag |= 1;
+ } // PCIE root port resource is not at default location
+ } // gTbtPlatformPolicy.TbtAICSupport
+ } // gTbtPlatformPolicy.TbtEnable
+#endif
+
+ if (TbtSetVariableFlag != 0){
+ Status = pRS->SetVariable( L"Setup", &SetupGuid, Attributes,
+ VariableSize, &SetupData );
+ }
+
+ return EFI_SUCCESS;
+}
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.cif b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.cif
new file mode 100644
index 0000000..32057d9
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.cif
@@ -0,0 +1,17 @@
+<component>
+ name = "TbtOemBoard"
+ category = ModulePart
+ LocalRoot = "Board\EM\Thunderbolt\TbtOemBoard\"
+ RefName = "TbtOemBoard"
+[files]
+"TbtOemBoard.h"
+"TbtOemBoard.c"
+"TbtOemBoard.dxs"
+"TbtOemBoard.mak"
+"TbtOemBoard.sdl"
+"TbtOemLib.c"
+"TbtOemLib.h"
+"TbtOemPorting.asl"
+[parts]
+"TbtSetup"
+<endComponent>
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs
new file mode 100644
index 0000000..4aa8e93
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs
@@ -0,0 +1,48 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs 1 1/10/13 4:57a Barretlin $
+//
+// $Revision: 1 $
+//
+// $Date: 1/10/13 4:57a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs $
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//**********************************************************************
+DEPENDENCY_START
+ TRUE
+DEPENDENCY_END
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.h b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.h
new file mode 100644
index 0000000..c4ce1ac
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.h
@@ -0,0 +1,328 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.h 11 5/19/14 7:15a Barretlin $
+//
+// $Revision: 11 $
+//
+// $Date: 5/19/14 7:15a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.h $
+//
+// 11 5/19/14 7:15a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Using setup item choose return value of _RMV method in
+// ASL code
+// [Files] TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+//
+// 10 2/18/14 7:29a Barretlin
+// [TAG] EIP152401
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] add new Thunderbolt chip series
+// [Files] TbtOemBoard.h
+//
+// 9 2/10/14 1:26p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] remove useless policy item and setup item
+// [Files] TbtOemBoard.h TbtOemBoard.c TbSetup.sdl TbtSetup.sd
+// TbtSetup.uni TbtSmm.c
+//
+// 8 1/05/14 2:06p Barretlin
+// [TAG] EIP N/A
+// [Category] New Feature
+// [Description] Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files] TbtOemBoard.h TbtOemBoard.c TbtOemLib.c TbtOemLib.h
+//
+// 7 7/26/13 1:53a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix build error at MahoBay/ChiefRiver platform
+// [Files] TbtPei.c TbtOemBoard.h
+//
+// 6 6/21/13 7:50a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix build error with non Intel RC project
+// [Files] TbtOemBoard.h TbtOemBoard.sdl
+//
+// 5 6/17/13 2:18a Barretlin
+// [TAG] EIP126581
+// [Category] Improvement
+// [Description] add new AIC support setup item and change
+// TBWakeupSupport name
+// [Files] TbtOemBoard.h TbtOemBoard.c
+//
+// 4 4/24/13 2:40a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Add new series
+// [Files] TbtOemBoard.h
+//
+// 3 4/03/13 3:04a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Adding mask definition for reading Redwood Ridge
+// command
+// [Files] TbtOemBoard.h
+//
+// 2 2/06/13 6:33a Barretlin
+// [TAG] EIP114556
+// [Category] Spec Update
+// [Severity] Normal
+// [Description] Add more definition for Thunderbolt RR Spec 0.9
+// [Files] TbtOemBoard.h
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 15 12/12/12 4:14a Barretlin
+// [TAG] EIP108272
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Update to Spec 1.4 to support Redwood Ridge chip
+// [Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 14 10/28/12 11:50p Barretlin
+// [TAG] EIP104870
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files] TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+//
+// 13 10/28/12 11:21p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Create new setup item for thunderbolt POC handling
+// [Files] TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl TbtSetup.sd
+// TbtSetup.uni
+//
+// 12 10/03/12 9:27p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change Programming security level timing for saving
+// boot time
+// [Files] TbtPei.c TbtDxe.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 11 8/20/12 5:12a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix IO resource workaround broken in 4C 2port case
+// [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+//
+// 10 8/17/12 8:44a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Add IO resource workaround for Thunderbolt Spec1.1
+// Because new spec has removed IO resource for Thunderbolt device
+// [Files] TbtSmm.c TbtOemBoard.h TbtOemBoard.c TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+//
+// 9 7/31/12 4:07a Barretlin
+// [TAG] EIP96350
+// [Category] Spec Update
+// [Severity] Critical
+// [Description] Updated Thunderbolt specification to version 1.00
+// [Files] TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+//
+// 8 7/31/12 3:15a Barretlin
+// [TAG] EIP91119
+// [Category] Improvement
+// [Description] Resolution for enable/disable Thunderbolt device option
+// rom at POST time
+// [Files] TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 7 5/22/12 10:00a Barretlin
+// [TAG] EIP90650
+// [Category] Spec Update
+// [Description] Specificatoin Update 0.94 - The default value of
+// OPTIONAL workaround for devices that don't support surprise-removal
+// should be disable.
+// [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 6 5/07/12 7:00a Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Add three setup items for debug
+// [Files] TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+//
+// 5 3/05/12 1:16a Barretlin
+// [TAG] EIP83266
+// [Category] Spec Update
+// [Description] Specificatoin Update 0.90
+// [Files] TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+//
+// 3 2/20/12 12:57a Wesleychen
+// Add new policy "SmiNotifyEnabled".
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//*************************************************************************
+#ifndef _THUNDERBOLT_OEM_PROTOCOL_
+#define _THUNDERBOLT_OEM_PROTOCOL_
+
+#include <Hob.h>
+
+#define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }
+
+#define AMI_TBT_HR_STATUS_GUID { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0x59, 0x87, 0x32, 0xF1, 0x56 }
+
+#define AMI_TBT_HOB_GUID { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0x5A, 0x87, 0x15, 0x15, 0x47 }
+
+#define TBT_HR_STATUS_VARIABLE L"TbtHRStatusVar"
+
+#define RR_PCIE2TBT 0x54C
+
+#define RR_TBT2PCIE 0x548
+
+#define PCIE2TBT_VLD_B 1
+
+#define TBT2PCIE_DON_R 1
+
+#define MASK_DATA (BIT08 | BIT09 | BIT10 | BIT11)
+
+#define MASK_ERROR (BIT12 | BIT13 | BIT14 | BIT15)
+
+#ifdef PCIEX_BASE_ADDRESS
+#define TBT_CFG_ADDRESS(bus, dev, func, reg) NB_PCIE_CFG_ADDRESS(bus, dev, func, reg)
+#endif
+
+#ifndef R_PCH_RCRB_PM_CFG
+#define R_PCH_RCRB_PM_CFG 0x3318 // Power Management Configuration Register
+#endif
+
+typedef enum {
+ Cactus_Ridge = 1,
+ Redwood_Ridge,
+ Falcon_Ridge,
+ BDW_TBT_LP
+} TBT_HOST_SERIES;
+
+typedef enum {
+ TBT_NORMAL_MODE = 1,
+ TBT_NORMAL_MODE_WO_NHI,
+ TBT_DIRECT_CONNECTED_WO_NHI,
+ TBT_REDRIVER_ONLY,
+ TBT_OFF_MODE,
+ TBT_DEBUG_MODE,
+ TBT_RR_LEGACY_CONNECTION = 0,
+ TBT_RR_UNIQUIE_ID,
+ TBT_RR_ONE_TIME_SAVED_KEY,
+ TBT_RR_DPPLUS
+} TBT_SECURITY_TYPE;
+
+typedef enum {
+ TBT_GO2SX_WITH_WAKE = 2,
+ TBT_GO2SX_NO_WAKE,
+ TBT_SX_EXIT_TBT_CONNECTED,
+ TBT_SX_EXIT_NO_TBT_CONNECTED,
+ TBT_OS_UP,
+ TBT_SET_SECURITY_LEVEL = 8,
+ TBT_GET_SECURITY_LEVEL
+} TBT_RR_COMMOND;
+
+typedef VOID (EFIAPI *TBT_PROGRAM_SEURITY_LVL) (
+ IN TBT_SECURITY_TYPE SecurityLevel
+ );
+
+typedef struct _AMI_TBT_HR_STATUS_DATA {
+ UINT8 TbtHRSeries;
+ UINT8 TbtHRStatus;
+} AMI_TBT_HR_STATUS_DATA;
+
+typedef struct {
+ EFI_HOB_GUID_TYPE Header;
+ UINT8 TbtSecurityLevelFlag;
+} TBT_HOB;
+
+typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
+ UINT8 TbtEnable;
+ UINT8 TbtGO2SX;
+ UINT8 TbtForcePWR;
+ UINT8 TbtHotPlugEvt;
+ UINT8 TbtOK2GO2SX_N;
+ UINT8 CacheLineSize;
+ UINT8 TbtWakeupSupport;
+ UINT8 TbtAICSupport;
+ UINT8 TbtHandlePOC;
+ UINT8 TbtSecurityLevel;
+ UINT8 Bus;
+ UINT8 Dev;
+ UINT8 Fun;
+ UINT16 ReserveMemoryPerSlot;
+ UINT16 ReservePMemoryPerSlot;
+ UINT8 ReserveIOPerSlot;
+ UINT8 SmiNotifyEnabled;
+ UINT8 SwSmiEnabled;
+ UINT8 NotifyEnabled;
+ UINT8 TbtRmvReturnValue;
+ UINT8 TbtOptionRom;
+ UINT8 TbtIOresourceEnable;
+ UINT8 TbtNVMversion;
+} AMI_TBT_PLATFORM_POLICY_PROTOCOL;
+
+#if !defined TBT_INTEL_RC_CONFIG || TBT_INTEL_RC_CONFIG == 0
+#define PCI_DEVICE_NUMBER_PCH_LPC LPC_DEVICE
+#define PCI_FUNCTION_NUMBER_PCH_LPC LPC_FUNC
+#define R_PCH_LPC_GPI_ROUT 0xB8
+#define R_PCH_PCIE_CLS 0x0C
+#define R_PCH_PCIE_SLCTL 0x58
+#define R_PCH_PCIE_SLSTS 0x5A
+#define B_PCH_PCIE_SLSTS_PDS BIT06
+#define R_PCH_PCIE_PMCS 0xA4
+#define B_PCH_PCIE_PMCS_PS (BIT00 | BIT01)
+#endif // TBT_INTEL_RC_CONFIG == 0
+
+#endif // _THUNDERBOLT_OEM_PROTOCOL_
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.mak b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.mak
new file mode 100644
index 0000000..f9d42e5
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.mak
@@ -0,0 +1,95 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.mak 1 1/10/13 4:57a Barretlin $
+#
+# $Revision: 1 $
+#
+# $Date: 1/10/13 4:57a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.mak $
+#
+# 1 1/10/13 4:57a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+#
+# 2 2/19/12 11:57p Wesleychen
+# [TAG] None
+# [Category] Improvement
+# [Description] Add TbtOemLib.
+# [Files] TbtOemLib.c; TbtOemLib.h; TbtOemBoard,mak;
+# TbtOemBoard.cif.
+#
+# 1 12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+#
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name: TbtOemBoard.mak
+#
+# Description:
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+All : TbtOemBoard
+
+TbtOemBoard : $(BUILD_DIR)\TbtOemBoard.mak TbtOemBoardBin
+
+$(BUILD_DIR)\TbtOemBoard.mak : $(TbtOemBoard_DIR)\$(@B).cif $(TbtOemBoard_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(TbtOemBoard_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+TbtOemBoardBin : $(AMICSPLib) $(AMIDXELIB)
+ $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+ /f $(BUILD_DIR)\TbtOemBoard.mak all\
+ GUID=B4DE05C0-1BD0-11E1-8F0E-77F34724019B\
+ ENTRY_POINT=TbtOemBoard_Init \
+ "MY_INCLUDES=$(TBT_OEMBOARD_INCLUDES)"\
+ TYPE=BS_DRIVER\
+ DEPEX1=$(TbtOemBoard_DIR)\TbtOemBoard.dxs\
+ DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+ COMPRESS=1
+
+#----------------------------------------------------------------------------
+# Add files into CSP Library
+#----------------------------------------------------------------------------
+AMI_CSP_LIB_LIBRARY_PATH = $(AMI_CSP_LIB_LIBRARY_PATH);$(TbtOemBoard_DIR)
+
+AMI_CSP_LIB_INCLUDE_FILES = "$(TbtOemBoard_DIR)\TbtOemLib.h" + \
+"$(TbtOemBoard_DIR)\TbtOemBoard.h" + \
+$(AMI_CSP_LIB_INCLUDE_FILES)
+
+AMI_CSP_LIB_OBJS = $(AMI_CSP_LIB_OBJS) \
+$(BUILD_DIR)\TbtOemLib.obj \
+
+{$(TbtOemBoard_DIR)}.c{$(BUILD_DIR)}.obj::
+ $(CC) $(CFLAGS) /I $(TbtDxe_DIR) /Fo$(BUILD_DIR)\ $<
+
+$(BUILD_DIR)\TbtOemLib.obj : $(TbtOemBoard_DIR)\TbtOemLib.c
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#************************************************************************* \ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl
new file mode 100644
index 0000000..e8a79a6
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl
@@ -0,0 +1,495 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl 9 2/18/14 6:11a Barretlin $
+#
+# $Revision: 9 $
+#
+# $Date: 2/18/14 6:11a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl $
+#
+# 9 2/18/14 6:11a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Add new Thunderbolt chip
+# [Files] TbtOemBoard.sdl
+#
+# 8 1/03/14 5:41a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Change default Thunderbolt host chip to Falcon Ridge
+# [Files] TbtOemBoard.sdl
+#
+# 7 6/21/13 7:50a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Fix build error with non Intel RC project
+# [Files] TbtOemBoard.h TbtOemBoard.sdl
+#
+# 6 4/24/13 2:39a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Using token to decide execute Sx_Exit command of RR
+# chip in S5 boot path
+# [Files] TbtPei.c TbtOemBoard.sdl
+#
+# 5 4/12/13 1:48p Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Use token decide default thunderbolt Chip
+# [Files] TbtOemBoard.sdl TbtOemLib.c
+#
+# 4 4/12/13 5:02a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Change token default value
+# [Files] TbtOemBoard.sdl
+#
+# 3 3/21/13 7:00a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Clone Token
+# [Files] TbtOemBoard.sdl
+#
+# 2 1/10/13 5:13a Barretlin
+#
+# 1 1/10/13 4:57a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+#
+# 15 12/12/12 4:14a Barretlin
+# [TAG] EIP108272
+# [Category] Spec Update
+# [Severity] Important
+# [Description] Update to Spec 1.4 to support Redwood Ridge chip
+# [Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+# TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+#
+# 14 10/28/12 11:50p Barretlin
+# [TAG] EIP104870
+# [Category] Spec Update
+# [Severity] Important
+# [Description] Change wake up flow for Spec 1.2 and Spec 1.3
+# [Files] TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+# TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+#
+# 13 10/28/12 10:35p Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Use token to decide to skip thunderbolt device initial
+# or not before PCI bus assigning resource
+# [Files] TbtDxeLib.c TbtOemBoard.sdl
+#
+# 12 10/04/12 5:43p Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Update Setup item
+# [Files] TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+#
+# 11 9/22/12 9:59a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Use token to defien thunderbolt chip pins and update
+# sample code
+# [Files] TbtOemBoard.c TbtOemBoard.sdl
+#
+# 10 8/30/12 4:50a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Add new tokens which related resource for 2C and 4C
+# case
+# [Files] TbtOemBoard.sdl
+#
+# 9 8/20/12 5:07a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Change default value of resources in 4C 2 port case
+# [Files] TbtOemBoard.sdl
+#
+# 8 8/17/12 8:35a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] add new resource token for thunderbolt 4C chip and
+# creat "TBT_FCTP" token to switch max size
+# [Files] TbtOemBoard.sdl
+#
+# 7 7/31/12 4:07a Barretlin
+# [TAG] EIP96350
+# [Category] Spec Update
+# [Severity] Critical
+# [Description] Updated Thunderbolt specification to version 1.00
+# [Files] TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+# TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+#
+# 6 7/31/12 3:15a Barretlin
+# [TAG] EIP91119
+# [Category] Improvement
+# [Description] Resolution for enable/disable Thunderbolt device option
+# rom at POST time
+# [Files] TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+# TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+#
+# 5 7/06/12 5:56a Barretlin
+#
+# 4 5/24/12 9:54p Barretlin
+# [TAG] None
+# [Category] Improvement
+# [Description] Add resource token, it needs the co-ordination of the
+# chipset
+# [Files] TbtOemBoard.sdl
+#
+# 3 5/21/12 2:27a Barretlin
+# [TAG] EIP90003
+# [Category] Improvement
+# [Description] If TBT devices with option rom enabled, system maybe
+# cannot boot to OS.
+# [Files] TbtDxe.c TbtSmm.c TbtOemBoard.sdl
+#
+# 2 4/16/12 10:23a Barretlin
+# [TAG] None
+# [Category] Improvement
+# [Description] Improve ASL code, which redefines device name and RMV
+# method at same address when project supports RMV method,
+# that mightcause conflict
+# [Files] TbtDxe.c TbtGpe.asl TbtOemBoard.sdl
+#
+# 1 12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+#
+#*************************************************************************
+TOKEN
+ Name = "TbtOemBoard_SUPPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ Master = Yes
+ Help = "Main switch to enable TbtOemBoard support in Project"
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_CHIP"
+ Value = "3"
+ Help = "1: Cactus Ridge/2: Redwood Ridge/3: Falcon Ridge/4: Win Ridge."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_UP_PORT_BUS"
+ Value = "0x00"
+ Help = "Thunderbolt Host Router Upstream Port Bus Number."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_UP_PORT_DEV"
+ Value = "0x1C"
+ Help = "Thunderbolt Host Router Upstream Port Device Number."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_UP_PORT_FUNC"
+ Value = "0x00"
+ Help = "Thunderbolt Host Router Upstream Port Function Number."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_GO2SX"
+ Value = "20"
+ Help = "Thunderbolt Host Router GO2SX Pin Number, Only for Cactus Ridge chip host."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_ForcePWR"
+ Value = "21"
+ Help = "Thunderbolt Host Router ForcePWR Pin Number."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_OK2GO2SX_N"
+ Value = "22"
+ Help = "Thunderbolt Host Router OK2GO2SX_N Pin Number, Only for Cactus Ridge chip host."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_HR_PWR"
+ Value = "0xFF"
+ Help = "Thunderbolt Host Router Power Pin Number, Only for Cactus Ridge chip."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_HotPlugEvt"
+ Value = "11"
+ Help = "Thunderbolt Host Router HotPlugEvt Pin Number."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_FCTP"
+ Value = "0"
+ Help = "Thunderbolt Host Router is 4 CIO and 2 phyical Thunderbolt port on board."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_PCIBUS_SKIP"
+ Value = "1"
+ Help = "Allow PCI bus skip thunderbolt device initial"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_RR_S5_SXEXIT"
+ Value = "0"
+ Help = "Enable/Disable execute Sx_Exit command of RR chip in S5 boot path."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "====== Thunderbolt Resource Configuration ======"
+ TokenType = Expression
+End
+
+TOKEN
+ Name = "PCIEX_BASE_ADDRESS"
+ Value = "0xF0000000"
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+TOKEN
+ Name = "PCIEX_BASE_ADDRESS"
+ Value = "0xE0000000"
+ TokenType = Integer
+ TargetEQU = Yes
+ TargetMAK = Yes
+ TargetH = Yes
+ TOKEN = "TBT_FCTP" "=" "1"
+ TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+TOKEN
+ Name = "MAX_ADDITIONAL_P2P_BRIDGES"
+ Value = "0x80"
+ Help = "The number of P2P bridges that can be processed in addition to the ones defined in BusNumXlat.INC."
+ TokenType = Integer
+ TargetH = Yes
+ Range = "1...0FFh"
+ TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+ Name = "COMBINE_MEM_PMEM"
+ Value = "0"
+ Help = "Tells if Chipset correctly supports PF MMIO\if set PF MMIO will be decoded through the same resource\window as NONE PF MMIO. PF MEM BASE and PF MEM LIMIT register pare will not be used."
+ TokenType = Boolean
+ TargetH = Yes
+ Range = "ON or OFF. Default is OFF!"
+End
+
+TOKEN
+ Name = "TBT_PCH_PCIE_TEMP_RP_BUS_NUM_MAX"
+ Value = "255" # (PPTRC060.8)
+ Help = "Temp Root Port Bus Number Max for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_MAX_EXTRA_BUS_RESERVED"
+ Value = "63"
+ Help = "The Max number of extra Bus Reserved for bridges behind this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_MAX_EXTRA_BUS_RESERVED"
+ Value = "245"
+ Help = "The Max number of extra Bus Reserved for bridges behind this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+ TOKEN = "TBT_FCTP" "=" "1"
+ Token = "PCIEX_BASE_ADDRESS" "!=" "0xF8000000"
+End
+
+TOKEN
+ Name = "TBT_DEFAULT_EXTRA_BUS_RESERVED"
+ Value = "56"
+ Help = "The Default number of extra Bus Reserved for bridges behind this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_DEFAULT_EXTRA_BUS_RESERVED"
+ Value = "106"
+ Help = "The Default number of extra Bus Reserved for bridges behind this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+ TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_MAX_PCIE_MEM_RESERVED"
+ Value = "640"
+ Help = "The Max number of reserved memory range for this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_MAX_PCIE_MEM_RESERVED"
+ Value = "1200"
+ Help = "The Max number of reserved memory range for this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+ TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_DEFAULT_PCIE_MEM_RESERVED"
+ Value = "353"
+ Help = "The Default number of reserved memory range for this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_DEFAULT_PCIE_MEM_RESERVED"
+ Value = "737"
+ Help = "The Default number of reserved memory range for this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+ TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_MAX_PCIE_PF_MEM_RESERVED"
+ Value = "640"
+ Help = "The Max number of prefetchable memory range for this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_MAX_PCIE_PF_MEM_RESERVED"
+ Value = "1200"
+ Help = "The Max number of prefetchable memory range for this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+ TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_DEFAULT_PCIE_PF_MEM_RESERVED"
+ Value = "544"
+ Help = "The Default number of prefetchable memory range for this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_DEFAULT_PCIE_PF_MEM_RESERVED"
+ Value = "1184"
+ Help = "The Default number of prefetchable memory range for this Root Bridge for Thunderbolt."
+ TokenType = Integer
+ TargetH = Yes
+ TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+ Name = "TBT_MAX_PCIE_IO_RESERVED"
+ Value = "48"
+ Help = "The Max number of IO range for this Root Bridge."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_DEFAULT_PCIE_IO_RESERVED"
+ Value = "0"
+ Help = "The Default number of IO range for this Root Bridge."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+MODULE
+ Help = "Includes TbtOemBoard.mak to Project"
+ File = "TbtOemBoard.mak"
+End
+
+PATH
+ Name = "TbtOemBoard_DIR"
+End
+
+ELINK
+ Name = "/D TBT_UP_PORT_FUNC_FLAG"
+ Parent = "GLOBAL_DEFINES"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "TBT_OEMBOARD_INCLUDES"
+ InvokeOrder = ReplaceParent
+End
+
+ELINK
+ Name = "/I$(TbtOemBoard_DIR)"
+ Parent = "TBT_OEMBOARD_INCLUDES"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\TbtOemBoard.ffs"
+ Parent = "FV_MAIN"
+ InvokeOrder = AfterParent
+End
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#************************************************************************* \ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.c b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.c
new file mode 100644
index 0000000..9e27a42
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.c
@@ -0,0 +1,1298 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemLib.c 13 5/19/14 7:38a Barretlin $
+//
+// $Revision: 13 $
+//
+// $Date: 5/19/14 7:38a $
+//*************************************************************************
+// ReviGpion History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemLib.c $
+//
+// 13 5/19/14 7:38a Barretlin
+// [TAG] EIP165410
+// [Category] New Feature
+// [Description] Support Thunderbolt AIC at NB PCIE slot
+// [Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+//
+// 12 2/18/14 12:16p Barretlin
+// [TAG] EIP152401
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] add new Thunderbolt chip series
+// [Files] TbtOemLib.c
+//
+// 11 1/05/14 2:06p Barretlin
+// [TAG] EIP N/A
+// [Category] New Feature
+// [Description] Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files] TbtOemBoard.h TbtOemBoard.c TbtOemLib.c TbtOemLib.h
+//
+// 10 5/27/13 8:11a Barretlin
+// [TAG] EIP124914
+// [Category] New Feature
+// [Description] Support Falcon Ridge chip
+// [Files] TbtOemLib.c
+//
+// 9 4/12/13 1:48p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Use token decide default thunderbolt Chip
+// [Files] TbtOemBoard.sdl TbtOemLib.c
+//
+// 8 4/12/13 1:30p Barretlin
+//
+// 7 4/10/13 2:57p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Add new sample code for CRB
+// [Files] TbtOemLib.c
+//
+// 6 4/03/13 2:47a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Double check Security Level between Thunderbolt host FW
+// and BIOS are same or not for Redwood Ridge chip when entering setup
+// page.
+// [Files] TbtOemLib.c TbtOemLib.h TbtSetupReset.c
+//
+// 5 3/21/13 6:48a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Update sample code to fix FW's security level doesn't
+// match BIOS configuration.
+// [Files] TbtOemLib.c
+//
+// 4 2/08/13 2:05a Barretlin
+//
+// 3 2/06/13 6:45a Barretlin
+// [TAG] EIP114556
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] Update RR handshake flow and sample code for
+// Thunderbolt RR Spec 0.9
+// [Files] TbtOemLib.c
+//
+// 2 1/27/13 4:36a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change sample code avoiding side effect
+// [Files] TbtOemLib.c
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 12 12/13/12 4:06a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix build error
+// [Files] TbtOemLib.c
+//
+// 11 12/12/12 4:14a Barretlin
+// [TAG] EIP108272
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Update to Spec 1.4 to support Redwood Ridge chip
+// [Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 10 10/28/12 11:50p Barretlin
+// [TAG] EIP104870
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files] TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+//
+// 9 10/04/12 10:42p Barretlin
+// [TAG] EIP102947
+// [Category] Spec Update
+// [Severity] Normal
+// [Description] Update Thunderbolt Spec to Rev 1.2
+// [Files] TbtPei.c TbtOemLib.c TbtOemLib.h
+//
+// 8 10/03/12 9:27p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change Programming security level timing for saving
+// boot time
+// [Files] TbtPei.c TbtDxe.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 7 5/21/12 2:56a Barretlin
+// [TAG] EIP90334
+// [Category] Improvement
+// [Description] Implement security level function on CRB
+// [Files] TbtOemLib.c
+//
+// 6 4/14/12 4:58a Barretlin
+//
+// 5 3/05/12 1:16a Barretlin
+// [TAG] EIP83266
+// [Category] Spec Update
+// [Description] Specificatoin Update 0.90
+// [Files] TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+//
+// 3 2/20/12 4:50a Wesleychen
+// [TAG] None
+// [Category] Improvement
+// [Description] Add TbtOemLib.
+// [Files] TbtOemLib.c; TbtOemLib.h; TbtOemBoard,mak;
+// TbtOemBoard.cif.
+//
+//*************************************************************************
+#include <Efi.h>
+#include <token.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+// Sample code for ITE8728F
+/*
+VOID SetSioLdn( IN UINT8 Ldn)
+{
+ IoWrite8(0x2e, Ldn);
+ IoWrite8(0x2f, Ldn);
+}
+
+UINT8 ReadSio( IN UINT8 Index )
+{
+ IoWrite8(0x2e, Index);
+ return IoRead8(0x2f);
+}
+
+VOID WriteSio( IN UINT8 Index, IN UINT8 Value )
+{
+ IoWrite8(0x2e, Index);
+ IoWrite8(0x2f, Value);
+}
+
+VOID SetSio( IN UINT8 Index, IN UINT8 Set )
+{
+ UINT8 Data8;
+
+ IoWrite8(0x2e, Index);
+ Data8 = IoRead8(0x2f);
+ Data8 |= Set;
+ IoWrite8(0x2f, Data8);
+}
+
+VOID ResetSio( IN UINT8 Index, IN UINT8 Rst )
+{
+ UINT8 Data8;
+
+ IoWrite8(0x2e, Index);
+ Data8 = IoRead8(0x2f);
+ Data8 &= ~Rst;
+ IoWrite8(0x2f, Data8);
+}
+
+VOID OpenSioConfig ( VOID )
+{
+ IoWrite8(0x2e, 0x87);
+ IoWrite8(0x2e, 0x01);
+ IoWrite8(0x2e, 0x55);
+ IoWrite8(0x2e, 0x55);
+}
+//*/
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: TbtSetPCIe2TBTCommand
+//
+// Description: This snipped code contains PCIE2TBT <-> TBT2PCIE handshake
+// procedure and all related methods called directly or underectly
+// by TbtSetPCIe2TBTCommand.
+// This function is Intel Sample code(Rev. 1.5).
+//
+// Input: UINT8 - UpPortBus
+// UINT8 - Data
+// UINT8 - Command
+// UINTN - Timeout
+//
+// Output: BOOLEAN
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN TbtSetPCIe2TBTCommand(
+ IN UINT8 UpPortBus,
+ IN UINT8 Data,
+ IN UINT8 Command,
+ IN UINTN Timeout
+)
+{
+ UINT32 REG_VAL = 0;
+ UINTN Counter = Timeout;
+
+ REG_VAL = (Data << 8) | (Command << 1) | PCIE2TBT_VLD_B;
+
+ WRITE_PCI32(UpPortBus, 0, 0, RR_PCIE2TBT, REG_VAL);
+
+ while(Counter-- > 0){
+ // BIOS support of Thunderbolt devices Specification Update Revision 0.9
+ // Check Classcode, RevID
+ REG_VAL = MMIO_READ32(TBT_CFG_ADDRESS(UpPortBus, 0, 0, PCI_RID));
+ if (0xFFFFFFFF == REG_VAL){
+ // Device is not here return now
+ return FALSE;
+ }
+
+ // Check TBT2PCIE.Done
+ REG_VAL = MMIO_READ32(TBT_CFG_ADDRESS(UpPortBus, 0, 0, RR_TBT2PCIE));
+ if (REG_VAL & TBT2PCIE_DON_R){
+ break;
+ }
+ }
+ WRITE_PCI32(UpPortBus, 0, 0, RR_PCIE2TBT, 0);
+
+ return TRUE;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: TbtBeforeSxExitFlow
+//
+// Description:
+//
+//
+// Input: EFI_PEI_SERVICES - **PeiServices
+// UINT8 - TbtHostSeries
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID TbtBeforeSxExitFlow(
+ IN VOID *Services,
+ IN UINT8 TbtHostSeries )
+{
+// Sample code for CRB
+/*
+ EFI_PEI_SERVICES **PeiServices;
+ UINT16 GPIOInv;
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+#else
+ UINT32 Data32;
+#endif
+
+ PeiServices = (EFI_PEI_SERVICES **)Services;
+
+ if (TbtHostSeries == Cactus_Ridge){
+ // only for SharkBay CRB
+ GPIOInv = (IoRead16(GPIO_BASE_ADDRESS + GP_IOREG_GPI_INV) & 0xF7FF);
+ IoWrite16(GPIO_BASE_ADDRESS + GP_IOREG_GPI_INV, GPIOInv);
+ }
+
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ OpenSioConfig();
+ SetSioLdn (0x07);
+
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+
+ //program GP20, GP21, GP22 as GPIO pin
+ Data8 = ReadSio (0x26);
+ Data8 |= 0x07;
+ WriteSio (0x26, Data8);
+
+ if (TbtHostSeries == Cactus_Ridge){
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+ //program GP40 as GPIO pin
+ Data8 = ReadSio (0x28);
+ Data8 |= 0x01;
+ WriteSio (0x28, Data8);
+#endif
+
+ //program GP66, GP67 as GPIO pin
+ Data8 = ReadSio (0x29);
+ Data8 |= BIT07;
+ WriteSio (0x29, Data8);
+ } // Cactus Ridge
+
+ //program GP20, GP21, GP22 GPIO polarity
+ Data8 = ReadSio (0xB1);
+ Data8 &= 0xF8;
+ WriteSio (0xB1, Data8);
+
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+ if (TbtHostSeries == Cactus_Ridge){
+ //program GP40 GPIO polarity
+ Data8 = ReadSio (0xB3);
+ Data8 &= 0xFE;
+ WriteSio (0xB3, Data8);
+ }
+#endif
+
+ //GP20, GP21, GP22 internal pull-up enable
+ Data8 = ReadSio (0xB9);
+ Data8 |= 0x03;
+ WriteSio (0xB9, Data8);
+
+ if (TbtHostSeries == Cactus_Ridge){
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+ //GP40 internal internal pull-up enable
+ Data8 = ReadSio (0xBB);
+ Data8 |= 0x01;
+ WriteSio (0xBB, Data8);
+#endif
+
+ //GP66, GP67 internal pull-up enable
+ Data8 = ReadSio (0xBD);
+ Data8 |= 0xC0;
+ WriteSio (0xBD, Data8);
+ }
+
+ //GP20, GP21, GP22 Simple I/O enable
+ Data8 = ReadSio (0xC1);
+ Data8 |= 0x07;
+ WriteSio (0xC1, Data8);
+
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+ if (TbtHostSeries == Cactus_Ridge){
+ //GP40 Simple I/O enable
+ Data8 = ReadSio (0xC3);
+ Data8 |= 0x01;
+ WriteSio (0xC3, Data8);
+ }
+#endif
+
+ //GP20, GP21, GP22 Input/Output Configure
+ //1:Output Mode 0:Input Mode
+ Data8 = ReadSio (0xC9);
+ Data8 |= 0x03;
+ WriteSio (0xC9, Data8);
+
+ if (TbtHostSeries == Cactus_Ridge){
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+ //GP40 Input/Output Configure
+ //1:Output Mode 0:Input Mode
+ Data8 = ReadSio (0xCB);
+ Data8 |= 0x01;
+ WriteSio (0xCB, Data8);
+#endif
+
+ //GP66, GP67 Input/Output Configure
+ //1:Output Mode 0:Input Mode
+ Data8 = ReadSio (0xCD);
+ Data8 |= 0xC0;
+ WriteSio (0xCD, Data8);
+ }
+
+ if (TbtHostSeries != Cactus_Ridge){
+ //Pull high GPIO_9
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, 0x04);
+ } // RR, FR and WR
+#else
+ // program ownship
+ //Data32 = IoRead32(GPIO_BASE_ADDRESS + (TBT_HotPlugEvt/32)*4);
+ //Data32 |= (BIT00 << (TBT_ForcePWR%32));
+ //IoWrite32((GPIO_BASE_ADDRESS + (TBT_HotPlugEvt/32)*4), Data32);
+
+ //Data32 = IoRead32(GPIO_BASE_ADDRESS + (TBT_HotPlugEvt/32)*4);
+ //Data32 &= ~(BIT00 << (TBT_HotPlugEvt%32));
+ //IoWrite32((GPIO_BASE_ADDRESS + (TBT_HotPlugEvt/32)*4), Data32);
+
+ // program GPIO pin setting
+ // TBT_ForcePWR is GPIO, is Output, is Level mode
+ //Data32 = (BIT00 | BIT04) & (~BIT02);
+ //IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+
+ // TBT_HotPlugEvt is GPIO, is input, need invert, is Edge mode
+ //Data32 = (BIT00 | BIT02 | BIT03) & (~BIT04);
+ //IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_HotPlugEvt * 8)), Data32);
+#endif
+//*/
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: GetHRInfo
+//
+// Description: Pull High GPIO_3 and assign temp bus to get Thunderbolt Host
+// Chip Series for distinguishing Thunderbolt host is Cactus Ridge
+// or Redwood Ridge
+//
+// If your case is only support Redwood Ridge or only support Cactus
+// Ridge, you can just return Thunderbolt Host number which is defined
+// in TbtOemBoard.h
+//
+// According test result, the dynamic detect Thunderbolt HR series
+// still has fail rate, so we don't suggest you using the same way
+// to decide HR series. sample code is just for testing !!!
+//
+// Input: None
+//
+// Output: UINT8 - Thunderbolt Host chip Series
+// 1 - Cactus Ridge
+// 2 - Redwood Ridge
+// 3 - Falcon Ridge
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8 GetHRInfo( VOID )
+{
+ UINT8 TBTHostSeries = DEFAULT_TBT_CHIP;
+// Sample code for ITE8728F and WTM2
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+#else
+ UINT32 Data32;
+#endif
+ UINT16 HRID;
+ UINT32 REG_VAL = 0;
+ BOOLEAN RRCmd = FALSE;
+
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ OpenSioConfig();
+
+ SetSioLdn(0x07);
+
+ if(ReadSio (0x62) == 0x00){
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+ }
+
+ //program GP21 as GPIO pin
+ Data8 = ReadSio (0x26);
+ Data8 |= 0x02;
+ WriteSio (0x26, Data8);
+
+ //program GP21 GPIO polarity
+ Data8 = ReadSio (0xB1);
+ Data8 &= 0xFD;
+ WriteSio (0xB1, Data8);
+
+ //program GP21 internal pull-up enable
+ Data8 = ReadSio (0xB9);
+ Data8 |= 0x02;
+ WriteSio (0xB9, Data8);
+
+ //program GP21 Simple I/O enable
+ Data8 = ReadSio (0xC1);
+ Data8 |= 0x02;
+ WriteSio (0xC1, Data8);
+
+ //program GP21 Input/Output Configure
+ //1:Output Mode 0:Input Mode
+ Data8 = ReadSio (0xC9);
+ Data8 |= 0x02;
+ WriteSio (0xC9, Data8);
+#else
+#endif
+
+ // Assign temp bus
+ WRITE_PCI16(TBT_UP_PORT_BUS, TBT_UP_PORT_DEV, TBT_UP_PORT_FUNC, PCI_PBUS+1, 0x0505);
+ // Do a dummy Write
+ WRITE_PCI32(5, 0, 0, PCI_VID, 0x12345678);
+
+ // Pull High GPIO_3(__FORCE_PWR)
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 |= 0x02;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+ Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+ Data32 |= BIT31;
+ IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+
+ // Delay 100 ms
+ CountTime(100000, PM_BASE_ADDRESS);
+
+ //Write OS_UP commond for RR chip
+ TbtSetPCIe2TBTCommand(5, 0, TBT_OS_UP, 0x8FFFF);
+
+ // Delay 600 ms
+ CountTime(600000, PM_BASE_ADDRESS);
+
+ // Get HR Info
+ HRID = READ_PCI16(5, 0, 0, PCI_DID);
+ switch (HRID){
+ case 0x1547: // Cactus Ridge 4C
+ case 0x1548: // Cactus Ridge 2C
+ TBTHostSeries = Cactus_Ridge;
+ break;
+
+ case 0x1567: // Redwood Ridge 2C
+ case 0x1569: // Redwood Ridge 4C
+ case 0x156B: // Falcon Ridge 2C
+ case 0x156D: // Falcon Ridge 4C
+ case 0x157E: // BDW-TBT-LP(WR)
+ default:
+ if ((HRID == 0x1567) || (HRID == 0x1569)){
+ TBTHostSeries = Redwood_Ridge;
+ } else if ((HRID == 0x156B) || (HRID == 0x156D)){
+ TBTHostSeries = Falcon_Ridge;
+ } else {
+ TBTHostSeries = BDW_TBT_LP;
+ }
+
+ // Reset FW's security level for RR chip, only for FW rev.26 or above.
+ TbtSetPCIe2TBTCommand(5, 0, TBT_SET_SECURITY_LEVEL, 0x8FFFF);
+ // Delay 100 ms
+ CountTime(100000, PM_BASE_ADDRESS);
+ } // end switch
+
+ // Pull Low GPIO_3(__FORCE_PWR)
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 &= 0xFD;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+ Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+ Data32 &= ~BIT31;
+ IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+
+ // Delay 100 ms
+ CountTime(100000, PM_BASE_ADDRESS);
+
+ // Remove temp bus
+ WRITE_PCI32(TBT_UP_PORT_BUS, TBT_UP_PORT_DEV, TBT_UP_PORT_FUNC, PCI_PBUS, 0xFF000000);
+//*/
+ return TBTHostSeries;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: SynchSecurityLevel
+//
+// Description: When entering Setup page, double check Security Level setting
+// is same or not between Thunderbolt host Fw and BIOS.
+//
+// This function only work for Thunderbolt Redwood Ridge chip
+//
+// Input: UINT8 BiosSecurityLevel
+// UINT8 TbtHostLocation
+//
+// Output: UINT8 0 - Security Level synchnized without change
+// 1 - Security Level synchnized with programming
+// again
+// 2 - Error
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8 SynchSecurityLevel(
+ IN UINT8 BiosSecurityLevel,
+ IN UINT8 TbtHostLocation
+)
+{
+ UINT8 SynchState = 0;
+// Sample code for ITE8728F and WTM2
+/*
+ UINT8 TbtHRbus;
+ UINT8 PWRFlag = 0;
+ UINT8 TBus = TBT_UP_PORT_BUS;
+ UINT8 TDev = TBT_UP_PORT_DEV;
+ UINT8 TFun = TBT_UP_PORT_FUNC;
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+#else
+ UINT32 Data32;
+#endif
+ UINT32 RegVal;
+ BOOLEAN CmdDone;
+
+ if (TbtHostLocation < 0x20){
+ TFun = TbtHostLocation;
+ } else {
+ TDev = 0x01;
+ TFun = TbtHostLocation - 0x20;
+ }
+
+ // Get Thunderbolt Host Router Location
+ TbtHRbus = READ_PCI8(TBus, TDev, TFun, PCI_SBUS);
+
+ // Check Thunderbolt Host state
+ RegVal = MMIO_READ32(TBT_CFG_ADDRESS(TbtHRbus, 0, 0, PCI_RID));
+ if (RegVal == 0xFFFFFFFF){
+ // Pull high GPIO_3(__FORCE_PWR) pin
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 |= 0x02;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+ Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+ Data32 |= BIT31;
+ IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+
+ // Delay 50ms
+ CountTime(50000, PM_BASE_ADDRESS);
+ PWRFlag = 1;
+ }
+
+ // Do Redwood Ridge handshake to get Thunderbolt FW security level
+ CmdDone = TbtSetPCIe2TBTCommand(TbtHRbus, 0, TBT_GET_SECURITY_LEVEL, 0x008FFFFF);
+
+ if (CmdDone){
+ RegVal = READ_PCI32(TbtHRbus, 0, 0, RR_TBT2PCIE);
+
+ if ((RegVal & MASK_ERROR) == 0){
+ RegVal = (RegVal & MASK_DATA) >> 8;
+ }
+ else SynchState = 2;
+ } else SynchState = 2;
+ // So far, RegVal variable might be:
+ // 1: 0xFFFFFFFF
+ // 2: Thunderbolt host Revision ID and Class Code
+ // 3: Thunderbolt host Fw security level setting
+
+ // check Security Level setting between Thunderbolt Fw and BIOS
+ if ((UINT8)RegVal != (BiosSecurityLevel - 1)){
+ if (PWRFlag == 0){
+ // Pull high GPIO_3(__FORCE_PWR) pin
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 |= 0x02;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+ Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+ Data32 |= BIT31;
+ IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+
+ PWRFlag = 1;
+ }
+ IoWrite8(0x80, (BiosSecurityLevel - 1 + 0xC0));
+ // After testing, TBT Fw needs Delay 600ms
+ CountTime(600000, PM_BASE_ADDRESS);
+
+ // Re-config Security Level with BIOS setting
+ CmdDone = TbtSetPCIe2TBTCommand(TbtHRbus, (BiosSecurityLevel - 1), TBT_SET_SECURITY_LEVEL, 0x008FFFFF);
+
+ if (CmdDone) SynchState = 1;
+ else SynchState = 2;
+ }
+
+ if (PWRFlag == 1){
+ // Pull low GPIO_3(__FORCE_PWR) pin
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 &= 0xFD;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+ Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+ Data32 &= (~BIT31);
+ IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+
+ // Delay 100ms
+ CountTime(100000, PM_BASE_ADDRESS);
+ }
+//*/
+ return SynchState;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: ProgramTbtSecurityLevel
+//
+// Description: This function is configure the Thunderbolt security level.
+// OEM Porting required !!!.
+//
+// Input: UINT8 TbtSecurityLevel
+// UINT8 TBTHostSeries
+// UINT8 TbtHostLocation
+// BOOLEAN IsPei
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID ProgramTbtSecurityLevel(
+ IN UINT8 *TbtSecurityLevel,
+ IN UINT8 TbtHostSeries,
+ IN UINT8 TbtHostLocation,
+ IN BOOLEAN IsPei
+)
+{
+// Sample code for ITE8728F and WTM2
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8 = 0;
+#else
+ UINT32 Data32 = 0;
+#endif
+ UINT8 SecLevel = *TbtSecurityLevel;
+ UINT8 TbtHRbus;
+ BOOLEAN RRCmd = FALSE;
+ UINT8 TBus = TBT_UP_PORT_BUS;
+ UINT8 TDev = TBT_UP_PORT_DEV;
+ UINT8 TFun = TBT_UP_PORT_FUNC;
+
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ if (TbtHostSeries == Cactus_Ridge){
+ // For Cactus Ridge chip
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 3);
+ if (SecLevel == TBT_OFF_MODE){
+ Data8 &= 0xFE;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 3, Data8);
+ return;
+ }
+ if (!(Data8 & BIT0)){
+ Data8 |= 0x01;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 3, Data8);
+ }
+#else
+ if (SecLevel == TBT_OFF_MODE) return;
+#endif
+
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 5);
+ Data8 &= ~(BIT6 | BIT7);
+
+ switch (SecLevel)
+ {
+ case TBT_DIRECT_CONNECTED_WO_NHI:
+ Data8 |= BIT6;
+ break;
+
+ case TBT_REDRIVER_ONLY:
+ Data8 |= BIT7;
+ break;
+
+ case TBT_NORMAL_MODE_WO_NHI:
+ break;
+
+ case TBT_NORMAL_MODE:
+ case TBT_DEBUG_MODE:
+ default:
+ // Normal mode with NHI.
+ Data8 |= (BIT6 | BIT7);
+ break;
+ } // end of switch
+
+ // Set GP66 and GP67
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 5, Data8);
+
+ // Set GPIO6 and GPIO7 to the desired levels and
+ // assert GPIO3 for at least 400ms period.
+ // GP21 Pull high
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 |= 0x02;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+ } else {
+ // For Redwood Ridge / Falcon Ridge / Win Ridge chip
+ if (IsPei != TRUE){
+ if(TbtHostLocation < 0x20){
+ TFun = TbtHostLocation;
+ } else {
+ TDev = 0x01;
+ TFun = TbtHostLocation - 0x20;
+ }
+
+ // Get Thunderbolt Host Router Location
+ TbtHRbus = READ_PCI8(TBus, TDev, TFun, PCI_SBUS);
+
+ // First pull high GPIO_3(__FORCE_PWR) pin
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 |= 0x02;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+
+ IoWrite8(0x80, (0x80 | (SecLevel - 1)));
+ CountTime(500000, PM_BASE_ADDRESS);
+
+ // Do PCIE2TBT handshake
+ RRCmd = TbtSetPCIe2TBTCommand(TbtHRbus, (SecLevel - 1), TBT_SET_SECURITY_LEVEL, 0x008FFFFF);
+ if(RRCmd){
+ IoWrite8(0x80, 0x5D);
+ CountTime(100000, PM_BASE_ADDRESS);
+ }
+
+ // Finial pull low GPIO_3(__FORCE_PWR) pin
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 &= 0xFD;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+ } // is not at PEI phase
+ }
+#else
+ if (IsPei != TRUE){
+ if (TbtHostLocation < 20){
+ TFun = TbtHostLocation;
+ } else {
+ TDev = 0x01;
+ TFun = TbtHostLocation - 0x20;
+ }
+
+ //Get Thunderbolt Host Router Location
+ TbtHRbus = READ_PCI8(TBus, TDev, TFun, PCI_SBUS);
+
+ // First pull high GPIO_3(__FORCE_PWR) pin
+ Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+ Data32 |= BIT31;
+ IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+
+ IoWrite8(0x80, (0x80 | (SecLevel - 1)));
+ CountTime(500000, PM_BASE_ADDRESS);
+
+ // Do PCIE2TBT handshake
+ RRCmd = TbtSetPCIe2TBTCommand(TbtHRbus, (SecLevel - 1), TBT_SET_SECURITY_LEVEL, 0x008FFFFF);
+
+ //for debug
+ if(RRCmd){
+ IoWrite8(0x80, 0x5D);
+ CountTime(100000, PM_BASE_ADDRESS);
+ }
+
+ // finial pull low GPIO_3(__FORCE_PWR) pin
+ Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+ Data32 &= ~BIT31;
+ IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+ }
+#endif
+//*/
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: PeiFinialProgramTbtSecurityLevel
+//
+// Description: if system does not support "Wake from Thunderbolt device"
+// function, BIOS should depend on Security Level and BootMod to
+// pull low FORCE_PWR pin or not in PEI phase
+//
+// This function only work for Thunderbolt Cactus Ridge chip and
+// system doesn't support wake up from Thunderbolt Device
+//
+// Input: UINT8 TbtSecurityLevel
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID PeiFinialProgramTbtSecurityLevel(
+ IN UINT8 TbtSecurityLevel
+)
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+ UINT8 SecLevel = TbtSecurityLevel;
+
+ OpenSioConfig();
+ SetSioLdn (0x07);
+ if(ReadSio (0x62) == 0x00){
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+ }
+
+ //The 400 ms delay has been done in TbtPei.c
+ //So just pull low GPIO_3(__FORCE_PWR) pin without any delay
+ if (SecLevel <= 4) {
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 &= 0xFD;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+ }
+#endif
+//*/
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: FinialProgramTbtSecurityLevel
+//
+// Description: BIOS should depend on Security Level to pull low FORCE_PWR pin
+// or not
+//
+// This function only work for Thunderbolt Cactus Ridge chip
+//
+// Input: AMI_TBT_PLATFORM_POLICY_PROTOCOL *PlatformPolocy
+//
+// Output: None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID FinialProgramTbtSecurityLevel(
+ IN AMI_TBT_PLATFORM_POLICY_PROTOCOL *PlatformPolocy
+)
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+ UINT8 SecLevel = PlatformPolocy->TbtSecurityLevel;
+
+ OpenSioConfig();
+ SetSioLdn (0x07);
+ if(ReadSio (0x62) == 0x00){
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+ }
+
+ if (SecLevel <= 4) {
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 &= 0xFD;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+ }
+#endif
+//*/
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: ActiveTbtGpio2
+//
+// Description: BIOS should assert GO2Sx pin
+// That will trigger Host Router to prepare underlying devices
+// For Thunderbolt host is CR chip
+//
+// This function only work for Thunderbolt Cactus Ridge chip
+//
+// Input: None
+//
+// Output: EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS ActiveTbtGpio2 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+
+ OpenSioConfig();
+
+ SetSioLdn(0x07);
+ if(ReadSio (0x62) == 0x00){
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+ }
+
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 |= BIT0;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#endif
+//*/
+ return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: InactiveTbtGpio2
+//
+// Description: BIOS should deassert GO2Sx pin
+// That will trigger Host Router to prepare underlying devices
+//
+// This function only work for Thunderbolt Cactus Ridge chip
+//
+// Input: None
+//
+// Output: EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS InactiveTbtGpio2 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+
+ OpenSioConfig();
+
+ SetSioLdn(0x07);
+ if(ReadSio (0x62) == 0x00){
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+ }
+
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 &= 0xFE;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#endif
+//*/
+ return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: PollTbtGpio9
+//
+// Description: BIOS should poll OK2GO2SX_N_OD pin
+// Upon completion of all preparations, Host Router will assert
+// this pin to indicate readiness for Sx entry.
+//
+// This function only work for Thunderbolt Cactus Ridge chip
+//
+// Input: None
+//
+// Output: EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS PollTbtGpio9 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT32 counter = 0;
+
+ while(IoRead8(IT8728_GPIO_BASE_ADDRESS + 1) & BIT2){
+ if (counter == 0x008FFFFF) break;
+ counter++;
+ }
+#endif
+//*/
+ return EFI_SUCCESS;
+};
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: PullDownTbtGpio9
+//
+// Description: BIOS should pull down OK2GO2SX_N_OD pin in Wake flow
+// if remebered Host Router state was active.
+//
+// This function only work for Thunderbolt Cactus Ridge chip and
+// system doesn't support wake up from Thunderbolt Device
+//
+// Input: None
+//
+// Output: EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS PullDownTbtGpio9 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+
+ OpenSioConfig();
+
+ SetSioLdn(0x07);
+
+ if(ReadSio (0x62) == 0x00){
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+ }
+
+ //program GP22 as GPIO pin
+ Data8 = ReadSio (0x26);
+ Data8 |= 0x04;
+ WriteSio (0x26, Data8);
+
+ //program GP22 GPIO polarity
+ Data8 = ReadSio (0xB1);
+ Data8 &= 0xF8;
+ WriteSio (0xB1, Data8);
+
+ //program GP22 internal pull-up enable
+ Data8 = ReadSio (0xB9);
+ Data8 |= 0x04;
+ WriteSio (0xB9, Data8);
+
+ //program GP22 Simple I/O enable
+ Data8 = ReadSio (0xC1);
+ Data8 |= 0x04;
+ WriteSio (0xC1, Data8);
+
+ //program GP22 Input/Output Configure
+ //1:Output Mode 0:Input Mode
+ Data8 = ReadSio (0xC9);
+ Data8 |= 0x04;
+ WriteSio (0xC9, Data8);
+
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+ Data8 &= 0xFB;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#endif
+//*/
+ return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: ReleaseTbtGpio9
+//
+// Description: BIOS should release pull down OK2GO2SX_N_OD pin in Wake flow
+// if remebered Host Router state was active
+//
+// This function only work for Thunderbolt Cactus Ridge chip and
+// system doesn't support wake up from Thunderbolt Device
+//
+// Input: None
+//
+// Output: EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS ReleaseTbtGpio9 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+
+ OpenSioConfig();
+
+ SetSioLdn(0x07);
+
+ //program GP22 Input/Output Configure
+ //1:Output Mode 0:Input Mode
+ Data8 = ReadSio (0xC9);
+ Data8 &= 0xFB;
+ WriteSio (0xC9, Data8);
+#endif
+//*/
+ return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: PowerOnPOC
+//
+// Description: Power on POC to wake up thunderbolt
+//
+// This function is optional and only work for Thunderbolt Cactus
+// Ridge chip and system doesn't support wake up from Thunderbolt
+// Device.
+//
+// Input: None
+//
+// Output: EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS PowerOnPOC ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+
+ OpenSioConfig();
+ SetSioLdn(0x07);
+
+ if(ReadSio (0x62) == 0x00){
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+ }
+
+ //program GP40 as GPIO pin
+ Data8 = ReadSio (0x28);
+ Data8 |= 0x01;
+ WriteSio (0x28, Data8);
+
+ //program GP40 GPIO polarity
+ Data8 = ReadSio (0xB3);
+ Data8 &= 0xFE;
+ WriteSio (0xB3, Data8);
+
+ //GP40 internal internal pull-up enable
+ Data8 = ReadSio (0xBB);
+ Data8 |= 0x01;
+ WriteSio (0xBB, Data8);
+
+ //GP40 Simple I/O enable
+ Data8 = ReadSio (0xC3);
+ Data8 |= 0x01;
+ WriteSio (0xC3, Data8);
+
+ //GP40 Input/Output Configure
+ //1:Output Mode 0:Input Mode
+ Data8 = ReadSio (0xCB);
+ Data8 |= 0x01;
+ WriteSio (0xCB, Data8);
+
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 3);
+ if (!(Data8 & BIT0)){
+ Data8 |= 0x01;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 3, Data8);
+ }
+#endif
+//*/
+ return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: PowerOffPOC
+//
+// Description: Power off POC to cut off thunderbolt power
+//
+// This function is optional and only work for Thunderbolt Cactus
+// Ridge chip and system doesn't support wake up from Thunderbolt
+// Device.
+//
+// Input: None
+//
+// Output: EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS PowerOffPOC ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+ UINT8 Data8;
+
+ OpenSioConfig();
+ SetSioLdn(0x07);
+
+ if(ReadSio (0x62) == 0x00){
+ //program Super IO Base Address
+ WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+ WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+ }
+
+ Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 3);
+ Data8 &= 0xFE;
+ IoWrite8(IT8728_GPIO_BASE_ADDRESS + 3, Data8);
+#endif
+//*/
+ return EFI_SUCCESS;
+}
+
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.h b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.h
new file mode 100644
index 0000000..ba3ca91
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.h
@@ -0,0 +1,216 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemLib.h 4 5/19/14 7:38a Barretlin $
+//
+// $ReviGpion: 1 $
+//
+// $Date: 5/19/14 7:38a $
+//*************************************************************************
+// ReviGpion History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemLib.h $
+//
+// 4 5/19/14 7:38a Barretlin
+// [TAG] EIP165410
+// [Category] New Feature
+// [Description] Support Thunderbolt AIC at NB PCIE slot
+// [Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+//
+// 3 1/05/14 2:06p Barretlin
+// [TAG] EIP N/A
+// [Category] New Feature
+// [Description] Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files] TbtOemBoard.h TbtOemBoard.c TbtOemLib.c TbtOemLib.h
+//
+// 2 4/03/13 2:47a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Double check Security Level between Thunderbolt host FW
+// and BIOS are same or not for Redwood Ridge chip when entering setup
+// page.
+// [Files] TbtOemLib.c TbtOemLib.h TbtSetupReset.c
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 7 12/12/12 4:14a Barretlin
+// [TAG] EIP108272
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Update to Spec 1.4 to support Redwood Ridge chip
+// [Files] TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 6 10/28/12 11:50p Barretlin
+// [TAG] EIP104870
+// [Category] Spec Update
+// [Severity] Important
+// [Description] Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files] TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+//
+// 5 10/04/12 10:42p Barretlin
+// [TAG] EIP102947
+// [Category] Spec Update
+// [Severity] Normal
+// [Description] Update Thunderbolt Spec to Rev 1.2
+// [Files] TbtPei.c TbtOemLib.c TbtOemLib.h
+//
+// 4 10/03/12 9:27p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Change Programming security level timing for saving
+// boot time
+// [Files] TbtPei.c TbtDxe.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+//
+// 3 3/05/12 1:16a Barretlin
+// [TAG] EIP83266
+// [Category] Spec Update
+// [Description] Specificatoin Update 0.90
+// [Files] TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+//
+// 1 2/19/12 11:56p Wesleychen
+// [TAG] None
+// [Category] Improvement
+// [Description] Add TbtOemLib.
+// [Files] TbtOemLib.c; TbtOemLib.h; TbtOemBoard,mak;
+// TbtOemBoard.cif.
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//*************************************************************************
+#ifndef _THUNDERBOLT_OEM_LIB_
+#define _THUNDERBOLT_OEM_LIB_
+
+#include "TbtOemBoard.h"
+
+UINT8 ReadSio(
+ IN UINT8 Index
+);
+
+VOID WriteSio(
+ IN UINT8 Index,
+ IN UINT8 Value
+);
+
+VOID SetSio(
+ IN UINT8 Index,
+ IN UINT8 Set
+);
+
+VOID ResetSio(
+ IN UINT8 Index,
+ IN UINT8 Rst
+);
+
+VOID OpenSioConfig(
+ VOID
+);
+
+VOID SetSioLdn(
+ IN UINT8 Ldn
+);
+
+UINT8 GetHRInfo(
+ VOID
+);
+
+BOOLEAN TbtSetPCIe2TBTCommand(
+ IN UINT8 UpPortBus,
+ IN UINT8 Data,
+ IN UINT8 Command,
+ IN UINTN Timeout
+);
+
+VOID TbtBeforeSxExitFlow(
+ IN VOID *Services,
+ IN UINT8 TbtHostSeries
+);
+
+UINT8 SynchSecurityLevel(
+ IN UINT8 BiosSecurityLevel,
+ IN UINT8 TbtHostLocation
+);
+
+VOID ProgramTbtSecurityLevel(
+ IN UINT8 *TbtSecurityLevel,
+ IN UINT8 TbtHostSeries,
+ IN UINT8 TbtHostLocation,
+ IN BOOLEAN IsPei
+);
+
+VOID PeiFinialProgramTbtSecurityLevel(
+ IN UINT8 TbtSecurityLevel
+);
+
+VOID FinialProgramTbtSecurityLevel(
+ IN AMI_TBT_PLATFORM_POLICY_PROTOCOL *PlatformPolocy
+);
+
+EFI_STATUS ActiveTbtGpio2(
+ VOID
+);
+
+EFI_STATUS InactiveTbtGpio2(
+ VOID
+);
+
+EFI_STATUS PollTbtGpio9(
+ VOID
+);
+
+EFI_STATUS PullDownTbtGpio9(
+ VOID
+);
+
+EFI_STATUS ReleaseTbtGpio9(
+ VOID
+);
+
+EFI_STATUS PowerOnPOC(
+ VOID
+);
+
+EFI_STATUS PowerOffPOC(
+ VOID
+);
+
+#endif // _THUNDERBOLT_OEM_LIB_
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemPorting.asl b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemPorting.asl
new file mode 100644
index 0000000..7edd513
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemPorting.asl
@@ -0,0 +1,13 @@
+ // Asserts/De-asserts TBT force power
+ Method(TBFP, 1)
+ {
+ // OEM Porting Required
+ If(Arg0)
+ {
+ // Implementation dependent way to assert TBT force power
+ }
+ Else
+ {
+ // Implementation dependent way to de-assert TBT force power
+ }
+ } \ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c
new file mode 100644
index 0000000..f22b493
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c
@@ -0,0 +1,172 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+//
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c 5 2/18/14 7:31a Barretlin $
+//
+// $Revision: 5 $
+//
+// $Date: 2/18/14 7:31a $
+//
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c $
+//
+// 5 2/18/14 7:31a Barretlin
+// [TAG] EIP152401
+// [Category] Spec Update
+// [Severity] Minor
+// [Description] add new thunderbolt chip series
+// [Files] TbtSetup.c
+//
+// 4 6/19/13 8:33a Barretlin
+// [TAG] EIP126581
+// [Category] Improvement
+// [Description] use thunderbolt FR spec token to update setup string
+// [Files] TbtSeup.c
+//
+// 3 6/16/13 10:23p Barretlin
+// [TAG] EIP None
+// [Category] Improvement
+// [Description] change CR BIOS Spec version display way
+// [Files] TbtSetup.c
+//
+// 2 5/27/13 8:15a Barretlin
+// [TAG] EIP124914
+// [Category] New Feature
+// [Description] Support Falcon Ridge chip
+// [Files] TbtSetup.c
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 4 8/16/12 4:19p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Add Thunderbolt Intel Sample Code version information
+// [Files] Thunderbolt.sdl TbtSetup.sd TbtSetup.uni TbtSetup.c
+//
+// 3 7/31/12 5:28a Barretlin
+//
+// 2 5/24/12 10:20p Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Add Thunderbolt version on setup menu
+// [Files] TbtSetup.sd TbtSetup.uni TbtSetup.c
+// Thunderbolt.sdl
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//**********************************************************************
+#include <token.h>
+#include <Setup.h>
+#include <AmiCSPLib.h>
+#include <AmiDxeLib.h>
+#include <TbtOemBoard.h>
+#include <SetupStrTokens.h>
+#if EFI_SPECIFICATION_VERSION>0x20000
+#include <Protocol\HiiDatabase.h>
+#include <Protocol\HiiString.h>
+#else
+#include <Protocol/Hii.h>
+#endif
+
+//----------------------------------------------------------------------------
+// GUID Definition(s)
+//----------------------------------------------------------------------------
+static EFI_GUID TbtHRStatusGuid = AMI_TBT_HR_STATUS_GUID;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure: InitiTbtInfo
+//
+// Description: Initializes Thunderbolt Setup String
+//
+// Input: HiiHandle - Handle to HII database
+// Class - Indicates the setup class
+//
+// Output: None
+//
+// Notes: PORTING REQUIRED
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID InitiTbtInfo(
+ IN EFI_HII_HANDLE HiiHandle,
+ IN UINT16 Class )
+{
+ EFI_STATUS Status;
+ UINTN HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+ CHAR16 TbtHRStatusVar[] = TBT_HR_STATUS_VARIABLE;
+ AMI_TBT_HR_STATUS_DATA HRStatusData;
+ CHAR16 *TbtCR = L"Cactus Ridge";
+ CHAR16 *TbtRR = L"Redwood Ridge";
+ CHAR16 *TbtFR = L"Falcon Ridge";
+ CHAR16 *TbtWR = L"BDW-TBT-LP(WR)";
+
+ Status = pRS->GetVariable( L"TbtHRStatusVar", \
+ &TbtHRStatusGuid, \
+ NULL, \
+ &HRStatusSize, \
+ &HRStatusData );
+
+ TRACE((-1, "TbtSetup: HR is %x series\n", HRStatusData.TbtHRSeries));
+
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_RC_VERSION_VALUE),
+ L"%d.%d", TBT_RC_VERSION/10, TBT_RC_VERSION%10);
+
+ if (HRStatusData.TbtHRSeries == Cactus_Ridge){
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_SPEC_VERSION_VALUE),
+ L"%d.%d", Thunderbolt_CR_VERSION/10, Thunderbolt_CR_VERSION%10);
+
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_HOST_VALUE),
+ L"%s", TbtCR);
+ } else if (HRStatusData.TbtHRSeries == Redwood_Ridge) {
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_SPEC_VERSION_VALUE),
+ L"%d.%d", Thunderbolt_RR_VERSION/10, Thunderbolt_RR_VERSION%10);
+
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_HOST_VALUE),
+ L"%s", TbtRR);
+ } else if (HRStatusData.TbtHRSeries == Falcon_Ridge){
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_SPEC_VERSION_VALUE),
+ L"%d.%d", Thunderbolt_FR_VERSION/10, Thunderbolt_FR_VERSION%10);
+
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_HOST_VALUE),
+ L"%s", TbtFR);
+ } else {
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_SPEC_VERSION_VALUE),
+ L"%d.%d", Thunderbolt_WR_VERSION/10, Thunderbolt_WR_VERSION%10);
+
+ InitString(HiiHandle, STRING_TOKEN(STR_TBT_HOST_VALUE),
+ L"%s", TbtWR);
+ }
+}
+
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//************************************************************************* \ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.cif b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.cif
new file mode 100644
index 0000000..8b8b975
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.cif
@@ -0,0 +1,14 @@
+<component>
+ name = "TbtSetup"
+ category = ModulePart
+ LocalRoot = "Board\EM\Thunderbolt\TbtOemBoard\TbtSetup"
+ RefName = "TbtSetup"
+[files]
+"TbtSetup.sdl"
+"TbtSetup.mak"
+"TbtSetup.sd"
+"TbtSetup.uni"
+"TbtSetup.c"
+"TbtSetup.h"
+"TbtSetupReset.c"
+<endComponent>
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h
new file mode 100644
index 0000000..f249648
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h
@@ -0,0 +1,70 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+//
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h 1 1/10/13 4:57a Barretlin $
+//
+// $Revision: 1 $
+//
+// $Date: 1/10/13 4:57a $
+//
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h $
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//**********************************************************************
+
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: iFfsSetup.h
+//
+// Description: Header file for iFfsSetup module.
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+
+#ifndef __FFS_SETUP_H__
+#define __FFS_SETUP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+#ifdef __cplusplus
+}
+#endif
+#endif
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak
new file mode 100644
index 0000000..95a1028
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak
@@ -0,0 +1,89 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+#
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak 1 1/10/13 4:57a Barretlin $
+#
+# $Revision: 1 $
+#
+# $Date: 1/10/13 4:57a $
+#
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak $
+#
+# 1 1/10/13 4:57a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+#
+# 2 12/12/12 4:47a Barretlin
+# [TAG] None
+# [Category] New Feature
+# [Description] Add Thunderbolt TSE Setup Reset Hook
+# [Files] TbtSetup.sdl TbtSetup.mak TbtSetup.cif TbtSetupReset.c
+#
+# 1 12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+#
+#**********************************************************************
+#
+#<AMI_FHDR_START>
+#----------------------------------------------------------------------------
+#
+# Name: Tbt Setup.mak
+#
+# Description: Makfile for TBT Setup module.
+#
+#----------------------------------------------------------------------------
+#<AMI_FHDR_END>
+All : TbtSetup
+
+TbtSetup : $(BUILD_DIR)\TbtSetup.mak
+
+SetupSdbs : $(BUILD_DIR)\TbtSetup.sdb
+
+$(BUILD_DIR)\TbtSetup.sdb : $(TbtSetup_DIR)\$(@B).sd $(TbtSetup_DIR)\$(@B).uni
+ $(STRGATHER) -i INCLUDE -parse -newdb -db $(BUILD_DIR)\$(@B).sdb $(TbtSetup_DIR)\$(@B).uni
+ $(STRGATHER) -scan -db $(BUILD_DIR)\$(@B).sdb -od $(BUILD_DIR)\$(@B).sdb $(TbtSetup_DIR)\$(@B).sd
+
+$(BUILD_DIR)\TbtSetup.mak : $(TbtSetup_DIR)\$(@B).cif $(TbtSetup_DIR)\$(@B).mak $(BUILD_RULES)
+ $(CIF2MAK) $(TbtSetup_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SetupBin : $(BUILD_DIR)\TbtSetup.obj
+
+$(BUILD_DIR)\TbtSetup.obj : $(TbtSetup_DIR)\TbtSetup.c $(BUILD_DIR)\SetupStrTokens.h
+ $(CC) $(CFLAGS) $(TBT_OEMBOARD_INCLUDES) /Fo$(BUILD_DIR)\ $(TbtSetup_DIR)\TbtSetup.c
+
+#----------------------------------------------------------------------------
+# Create Thunderbolt Setup TSE Reset Hook
+#----------------------------------------------------------------------------
+AMITSEBin : $(BUILD_DIR)\TbtSetupReset.obj
+
+$(BUILD_DIR)\TbtSetupReset.obj : $(TbtSetup_DIR)\TbtSetupReset.c $(AMICSPLib)
+ $(CC) $(CFLAGS) $(INTEL_PCH_INCLUDES) $(TBT_OEMBOARD_INCLUDES) /Fo$(BUILD_DIR)\ $(TbtSetup_DIR)\TbtSetupReset.c
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2011, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#************************************************************************* \ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd
new file mode 100644
index 0000000..ccc8166
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd
@@ -0,0 +1,1456 @@
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+//
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd 13 5/19/14 7:40a Barretlin $
+//
+// $Revision: 13 $
+//
+// $Date: 5/19/14 7:40a $
+//
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd $
+//
+// 13 5/19/14 7:40a Barretlin
+// [TAG] EIP165410
+// [Category] Improvement
+// [Description] Support Thunderbolt AIC at NB PCIE slot
+// [Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+//
+// 12 5/19/14 7:19a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Using setup item choose return value of _RMV method in
+// ASL code
+// [Files] TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+//
+// 11 2/10/14 1:30p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] remove useless policy item and setup item
+// [Files] TbtOemBoard.h TbtOemBoard.c TbSetup.sdl TbtSetup.sd
+// TbtSetup.uni TbtSmm.c
+//
+// 10 1/05/14 2:14p Barretlin
+// [TAG] EIP N/A
+// [Category] New Feature
+// [Description] Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni TbtSetupReset.c
+//
+// 9 12/24/13 11:40a Barretlin
+// [TAG] EIP148198
+// [Category] Improvement
+// [Description] Updating for Thunderbolt BIOS additions rev.1.8
+// [Files] TbtSetup.sd
+//
+// 8 6/24/13 5:10a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix build error with non Intel RC project
+// [Files] TbtSetup.sd
+//
+// 7 6/17/13 4:25a Barretlin
+// [TAG] EIP126581
+// [Category] Improvement
+// [Description] add new AIC support setup item and change
+// TBWakeupSupport name
+// [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 6 5/06/13 12:13a Barretlin
+//
+// 5 4/24/13 1:38a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Clone APCI PCIE setup item
+// [Files] TbtSetup.sd TbtSetup.uni
+//
+// 4 4/09/13 11:38p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Add cloned PCIE config for ULT platform
+// [Files] TbtSetup.sd
+//
+// 3 3/21/13 6:00a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Clone PCIE prot swap setup item and set disable by
+// default
+// [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 2 2/06/13 1:55a Barretlin
+// [TAG] EIP None
+// [Category] Improvement
+// [Description] Hide unused setup item for RR chip
+// [Files] TbtSetup.sd
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 15 10/27/12 6:16a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Create new setup item for thunderbolt POC handling
+// [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 14 10/04/12 5:40p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Update Setup item
+// [Files] TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+//
+// 13 9/22/12 9:53a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Clone SB PCIE setup item which are related thunderbolt
+// [Files] TbtSetup.sd TbtSetup.uni
+//
+// 12 8/20/12 5:16a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix IO resource workaround broken in 4C 2port case
+// [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+//
+// 11 8/17/12 8:53a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Add IO resource workaround for Thunderbolt Spec1.1
+// Because new spec has removed IO resource for Thunderbolt device
+// [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+//
+// 10 8/16/12 4:19p Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Add Thunderbolt Intel Sample Code version information
+// [Files] Thunderbolt.sdl TbtSetup.sd TbtSetup.uni TbtSetup.c
+//
+// 9 7/31/12 4:01a Barretlin
+// [TAG] EIP96350
+// [Category] Spec Update
+// [Severity] Critical
+// [Description] Updated Thunderbolt specification to version 1.00
+// [Files] TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+//
+// 8 7/31/12 3:28a Barretlin
+// [TAG] EIP91119
+// [Category] Improvement
+// [Description] Resolution for enable/disable Thunderbolt device option
+// rom at POST time
+// [Files] TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 7 5/24/12 10:20p Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Add Thunderbolt version on setup menu
+// [Files] TbtSetup.sd TbtSetup.uni TbtSetup.c
+// Thunderbolt.sdl
+//
+// 6 5/22/12 10:05a Barretlin
+// [TAG] EIP90650
+// [Category] Spec Update
+// [Description] Specificatoin Update 0.94 - The default value of
+// OPTIONAL workaround for devices that don't support surprise-removal
+// should be disable.
+// [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+//
+// 5 5/07/12 7:04a Barretlin
+// [TAG] None
+// [Category] Improvement
+// [Description] Add three setup items for debug
+// [Files] TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+//
+// 4 3/05/12 1:11a Barretlin
+// [TAG] EIP83266
+// [Category] Spec Update
+// [Description] Specificatoin Update 0.90
+// [Files] TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+//
+// 2 2/19/12 11:52p Wesleychen
+// Add new setup item "SmiNotifyEnabled".
+//
+// 1 12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: Thunderbolt Setup.sd
+//
+// Description: Setup for Thunderbolt Setup.
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+
+#ifdef SETUP_DATA_DEFINITION
+/***********************************************************/
+/* Put NVRAM data definitions here.
+/* For example: UINT8 Data1;
+/* These definitions will be converted by the build process
+/* to a definitions of SETUP_DATA fields.
+/***********************************************************/
+ UINT8 TbtEnable;
+ UINT8 TbtHRSeries;
+ UINT8 TbtWakeupSupport;
+ UINT8 TbtAICSupport;
+ UINT8 TbtHostLocation;
+ UINT8 TbtHandlePOC;
+ UINT8 TbtCacheLineSize;
+ UINT8 TbtSecurityLevel;
+ UINT8 SmiNotifyEnabled;
+ UINT8 SwSmiEnabled;
+ UINT8 NotifyEnabled;
+ UINT8 TbtRmvReturnValue;
+ UINT8 TbtOptionRom;
+ UINT16 TbtWakeupDelay;
+ UINT16 TbtSwSMIDelay;
+ //Resources for Per Slot under Thunderbolt
+ UINT16 ReserveMemoryPerSlot;
+ UINT16 ReservePMemoryPerSlot;
+ UINT8 ReserveIOPerSlot;
+ UINT8 TbtIOresourceEnable;
+ UINT8 TbtNVMversion;
+#endif
+
+#if defined(VFRCOMPILE) && !defined(CONTROLS_ARE_DEFINED)
+#define CONTROL_DEFINITION
+#endif
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+#ifdef CONTROL_DEFINITION
+
+#define TBT_ONEOF_TBTENABLE\
+ checkbox varid = SETUP_DATA.TbtEnable,\
+ prompt = STRING_TOKEN (STR_TBT_ENABLE_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_ENABLE_HELP),\
+ flags = DEFAULT_TBT_ENABLE | MANUFACTURING | RESET_REQUIRED,\
+ endcheckbox;
+
+#define TBT_ONEOF_TBTWAKEUPSUPPORT\
+ checkbox varid = SETUP_DATA.TbtWakeupSupport,\
+ prompt = STRING_TOKEN (STR_TBT_DEVICE_WAKE_UP_SUPPORT_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_DEVICE_WAKE_UP_SUPPORT_HELP),\
+ flags = DEFAULT_TB_WAKE_UP_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+ endcheckbox;
+
+#define TBT_ONEOF_TBTHANDLEPOC\
+ checkbox varid = SETUP_DATA.TbtHandlePOC,\
+ prompt = STRING_TOKEN (STR_TBT_HANDLE_POC_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_HANDLE_POC_HELP),\
+ flags = DEFAULT_TBT_HANDLE_POC | RESET_REQUIRED | MANUFACTURING, \
+ endcheckbox;
+
+#define TBT_ONEOF_TBTAICSUPPORT\
+ checkbox varid = SETUP_DATA.TbtAICSupport,\
+ prompt = STRING_TOKEN (STR_TBT_AIC_SUPPORT_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_AIC_SUPPORT_HELP),\
+ flags = DEFAULT_TBT_AIC_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+ endcheckbox;
+
+#define TBT_ONEOF_TBTHOSTLOCATION\
+ oneof varid = SETUP_DATA.TbtHostLocation,\
+ prompt = STRING_TOKEN (STR_TBT_HOST_LOCATION_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_HOST_LOCATION_HELP),\
+ default = DEFAULT_TBT_AIC_LOCATION,\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_000), value = 0x00, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_001), value = 0x01, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_002), value = 0x02, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_003), value = 0x03, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_004), value = 0x04, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_005), value = 0x05, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_006), value = 0x06, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_007), value = 0x07, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_016), value = 0x20, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_017), value = 0x21, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_HOST_LOCATION_018), value = 0x22, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+
+#define TBT_ONEOF_TBTCACHELINESIZE\
+ oneof varid = SETUP_DATA.TbtCacheLineSize,\
+ prompt = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_PROMPT),\
+ help = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_HELP),\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_000), value = 0x00, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_001), value = 0x01, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_002), value = 0x02, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_004), value = 0x04, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_008), value = 0x08, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_016), value = 0x10, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_032), value = 0x20, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_064), value = 0x40, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_128), value = 0x80, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+#define TBT_ONEOF_TBTCRSECURITYLEVEL\
+ oneof varid = SETUP_DATA.TbtSecurityLevel,\
+ prompt = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_PROMPT),\
+ help = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_HELP),\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE1), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE2), value = 2, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE3), value = 3, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE4), value = 4, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE5), value = 5, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE6), value = 6, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#else
+#define TBT_ONEOF_TBTCRSECURITYLEVEL\
+ oneof varid = SETUP_DATA.TbtSecurityLevel,\
+ prompt = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_PROMPT),\
+ help = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_HELP),\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE1), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE2), value = 2, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE3), value = 3, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE4), value = 4, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_CR_MODE6), value = 6, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#define TBT_ONEOF_TBTRRSECURITYLEVEL\
+ oneof varid = SETUP_DATA.TbtSecurityLevel,\
+ prompt = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_PROMPT),\
+ help = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_HELP),\
+ option text = STRING_TOKEN(STR_TBT_RR_MODE1), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_RR_MODE2), value = 2, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_RR_MODE3), value = 3, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_RR_MODE4), value = 4, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+
+#define TBT_ONEOF_SMINOTIFYENABLED\
+ checkbox varid = SETUP_DATA.SmiNotifyEnabled,\
+ prompt = STRING_TOKEN (STR_TBT_SMI_NOTIFY_SUPPORT_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_SMI_NOTIFY_SUPPORT_HELP),\
+ flags = DEFAULT_TB_SMI_NOTIFY_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+ endcheckbox;
+
+#define TBT_ONEOF_SWSMIENABLED\
+ checkbox varid = SETUP_DATA.SwSmiEnabled,\
+ prompt = STRING_TOKEN (STR_TBT_SWSMI_SUPPORT_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_SWSMI_SUPPORT_HELP),\
+ flags = DEFAULT_TB_SMI_NOTIFY_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+ endcheckbox;
+
+#define TBT_ONEOF_NOTIFYENABLED\
+ checkbox varid = SETUP_DATA.NotifyEnabled,\
+ prompt = STRING_TOKEN (STR_TBT_NOTIFY_SUPPORT_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_NOTIFY_SUPPORT_HELP),\
+ flags = DEFAULT_TB_SMI_NOTIFY_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+ endcheckbox;
+
+#define TBT_ONEOF_RMVRETRUNVALUE\
+ oneof varid = SETUP_DATA.TbtRmvReturnValue,\
+ prompt = STRING_TOKEN(STR_TBT_RMV_RETURN_VALUE_PROMPT),\
+ help = STRING_TOKEN(STR_TBT_RMV_RETURN_VALUE_HELP),\
+ default = DEFAULT_TBT_RMV_RETURN_VALUE,\
+ option text = STRING_TOKEN(STR_TBT_RMV_RETURN_VALUE_0), value = 0, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_TBT_RMV_RETURN_VALUE_1), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+
+#define TBT_ONEOF_OPTIONROM\
+ checkbox varid = SETUP_DATA.TbtOptionRom,\
+ prompt = STRING_TOKEN (STR_TBT_OPTIONROM_SUPPORT_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_OPTIONROM_SUPPORT_HELP),\
+ flags = DEFAULT_SKIP_TBT_OPTIONROM | RESET_REQUIRED | MANUFACTURING, \
+ endcheckbox;
+
+#define TBT_ONEOF_TBTWAKEUPDELAY\
+ numeric varid = SETUP_DATA.TbtWakeupDelay,\
+ prompt = STRING_TOKEN (STR_TBT_WAKE_UP_DELAY_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_WAKE_UP_DELAY_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = 65535,\
+ step = 1,\
+ default = DEFAULT_TBT_WAK_DELAY,\
+ option text = STRING_TOKEN (STR_TBT_WAKE_UP_DELAY_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+
+#define TBT_ONEOF_TBTSWSMIDELAY\
+ numeric varid = SETUP_DATA.TbtSwSMIDelay,\
+ prompt = STRING_TOKEN (STR_TBT_SWSMI_DELAY_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_SWSMI_DELAY_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = 65535,\
+ step = 1,\
+ default = DEFAULT_TBT_SWSMI_DELAY,\
+ option text = STRING_TOKEN (STR_TBT_SWSMI_DELAY_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+
+#define TBT_ONEOF_PERSLOTMEMRSVD\
+ numeric varid = SETUP_DATA.ReserveMemoryPerSlot,\
+ prompt = STRING_TOKEN (STR_TBT_PERSLOT_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_PERSLOT_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = TBT_MAX_PCIE_MEM_RESERVED,\
+ step = 1,\
+ default = 32,\
+ option text = STRING_TOKEN (STR_TBT_PERSLOT_RMEM_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+
+#define TBT_ONEOF_PERSLOTPFMEMRSVD\
+ numeric varid = SETUP_DATA.ReservePMemoryPerSlot,\
+ prompt = STRING_TOKEN (STR_TBT_PERSLOT_PF_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_PERSLOT_PF_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+ step = 1,\
+ default = 32,\
+ option text = STRING_TOKEN (STR_TBT_PERSLOT_PF_RMEM_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+
+#define TBT_ONEOF_PERSLOTIORSVD\
+ numeric varid = SETUP_DATA.ReserveIOPerSlot,\
+ prompt = STRING_TOKEN (STR_TBT_PERSLOT_RVIO_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_PERSLOT_RVIO_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 4,\
+ maximum = TBT_MAX_PCIE_IO_RESERVED,\
+ step = 4,\
+ default = 4,\
+ option text = STRING_TOKEN (STR_TBT_PERSLOT_RVIO_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+
+#define TBT_ONEOF_IORESOURCEENABLED\
+ checkbox varid = SETUP_DATA.TbtIOresourceEnable,\
+ prompt = STRING_TOKEN (STR_TBT_IORESOURCE_SUPPORT_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_IORESOURCE_SUPPORT_HELP),\
+ flags = DEFAULT_TBT_IO_RESOURCE_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+ endcheckbox;
+
+#define TBT_ONEOF_NVMVERSION\
+ numeric varid = SETUP_DATA.TbtNVMversion,\
+ prompt = STRING_TOKEN (STR_TBT_NVM_VERSION_PROMPT),\
+ help = STRING_TOKEN (STR_TBT_NVM_VERSION_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 11,\
+ maximum = 65535,\
+ step = 1,\
+ default = TBT_NVM,\
+ option text = STRING_TOKEN (STR_TBT_NVM_VERSION_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+
+#if defined (TBT_INTEL_RC_CONFIG) && (TBT_INTEL_RC_CONFIG == 1)
+//---------------------------------------------------------------------------
+// ACPI PCIE Setting
+//---------------------------------------------------------------------------
+
+#ifdef ACPI_ONEOF_PCIEXPNATIVE
+#undef ACPI_ONEOF_PCIEXPNATIVE
+#define ACPI_ONEOF_PCIEXPNATIVE\
+ oneof varid = SETUP_DATA.PciExpNative,\
+ prompt = STRING_TOKEN(STR_ACPI_PCIE_NATIVE_PROMPT),\
+ help = STRING_TOKEN(STR_ACPI_PCIE_NATIVE_HELP),\
+ option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#ifdef ACPI_ONEOF_NATIVEASPMENABLE
+#undef ACPI_ONEOF_NATIVEASPMENABLE
+#define ACPI_ONEOF_NATIVEASPMENABLE\
+ oneof varid = SETUP_DATA.NativeAspmEnable,\
+ prompt = STRING_TOKEN(STR_ACPI_NATIVE_ASPM_PROMPT),\
+ help = STRING_TOKEN(STR_ACPI_NATIVE_ASPM_HELP),\
+ option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+//---------------------------------------------------------------------------
+// SB PCIE Root Port Setting
+//---------------------------------------------------------------------------
+
+#if defined (DISABLE_PCIE_ROOT_PORT_SWAP) && (DISABLE_PCIE_ROOT_PORT_SWAP == 1)
+#ifdef SB_ONEOF_ROOTPORTFUNCTIONSWAPPING
+#undef SB_ONEOF_ROOTPORTFUNCTIONSWAPPING
+#define SB_ONEOF_ROOTPORTFUNCTIONSWAPPING\
+ oneof varid = SETUP_DATA.RootPortFunctionSwapping,\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PORT_SWAP_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PORT_SWAP_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+#endif
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 0)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE00
+#undef SB_ONEOF_PCIEROOTPORTHPE00
+#define SB_ONEOF_PCIEROOTPORTHPE00\
+ oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_0],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD00
+#undef SB_ONEOF_EXTRABUSRSVD00
+#define SB_ONEOF_EXTRABUSRSVD00\
+ numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_0],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_EXTRA_BUS_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD00
+#undef SB_ONEOF_PCIEMEMRSVD00
+#define SB_ONEOF_PCIEMEMRSVD00\
+ numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_0],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG00
+#undef SB_ONEOF_PCIEMEMRSVDALIG00
+#define SB_ONEOF_PCIEMEMRSVDALIG00\
+ numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_0],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 26,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD00
+#undef SB_ONEOF_PCIEPFMEMRSVD00
+#define SB_ONEOF_PCIEPFMEMRSVD00\
+ numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_0],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG00
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG00
+#define SB_ONEOF_PCIEPFMEMRSVDALIG00\
+ numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_0],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 28,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD00
+#undef SB_ONEOF_PCIEIORSVD00
+#define SB_ONEOF_PCIEIORSVD00\
+ numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_0],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_IO_RESERVED,\
+ step = 4,\
+ default = TBT_DEFAULT_PCIE_IO_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // IO resource
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN01
+#undef SB_ONEOF_PCIEROOTPORTEN01
+#define SB_ONEOF_PCIEROOTPORTEN01\
+ oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_1],\
+ prompt = STRING_TOKEN (STR_PCH_PCIERP2_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif // PCIE root port1 disable
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN02
+#undef SB_ONEOF_PCIEROOTPORTEN02
+#define SB_ONEOF_PCIEROOTPORTEN02\
+ oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_2],\
+ prompt = STRING_TOKEN (STR_PCH_PCIERP3_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif // PCIE root port2 disable
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN03
+#undef SB_ONEOF_PCIEROOTPORTEN03
+#define SB_ONEOF_PCIEROOTPORTEN03\
+ oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_3],\
+ prompt = STRING_TOKEN (STR_PCH_PCIERP4_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif // PCIE root port3 disable
+#endif //TBT_UP_PORT_FUNC == 0
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 1)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE01
+#undef SB_ONEOF_PCIEROOTPORTHPE01
+#define SB_ONEOF_PCIEROOTPORTHPE01\
+ oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_1],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD01
+#undef SB_ONEOF_EXTRABUSRSVD01
+#define SB_ONEOF_EXTRABUSRSVD01\
+ numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_1],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_EXTRA_BUS_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD01
+#undef SB_ONEOF_PCIEMEMRSVD01
+#define SB_ONEOF_PCIEMEMRSVD01\
+ numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_1],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG01
+#undef SB_ONEOF_PCIEMEMRSVDALIG01
+#define SB_ONEOF_PCIEMEMRSVDALIG01\
+ numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_1],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 26,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD01
+#undef SB_ONEOF_PCIEPFMEMRSVD01
+#define SB_ONEOF_PCIEPFMEMRSVD01\
+ numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_1],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG01
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG01
+#define SB_ONEOF_PCIEPFMEMRSVDALIG01\
+ numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_1],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 28,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD01
+#undef SB_ONEOF_PCIEIORSVD01
+#define SB_ONEOF_PCIEIORSVD01\
+ numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_1],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_IO_RESERVED,\
+ step = 4,\
+ default = TBT_DEFAULT_PCIE_IO_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // IO resource
+#endif //TBT_UP_PORT_FUNC == 1
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 2)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE02
+#undef SB_ONEOF_PCIEROOTPORTHPE02
+#define SB_ONEOF_PCIEROOTPORTHPE02\
+ oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_2],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD02
+#undef SB_ONEOF_EXTRABUSRSVD02
+#define SB_ONEOF_EXTRABUSRSVD02\
+ numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_2],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_EXTRA_BUS_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD02
+#undef SB_ONEOF_PCIEMEMRSVD02
+#define SB_ONEOF_PCIEMEMRSVD02\
+ numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_2],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG02
+#undef SB_ONEOF_PCIEMEMRSVDALIG02
+#define SB_ONEOF_PCIEMEMRSVDALIG02\
+ numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_2],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 26,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD02
+#undef SB_ONEOF_PCIEPFMEMRSVD02
+#define SB_ONEOF_PCIEPFMEMRSVD02\
+ numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_2],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG02
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG02
+#define SB_ONEOF_PCIEPFMEMRSVDALIG02\
+ numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_2],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 28,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD02
+#undef SB_ONEOF_PCIEIORSVD02
+#define SB_ONEOF_PCIEIORSVD02\
+ numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_2],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_IO_RESERVED,\
+ step = 4,\
+ default = TBT_DEFAULT_PCIE_IO_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // IO resource
+#endif //TBT_UP_PORT_FUNC == 2
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 3)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE3
+#undef SB_ONEOF_PCIEROOTPORTHPE03
+#define SB_ONEOF_PCIEROOTPORTHPE03\
+ oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_3],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD03
+#undef SB_ONEOF_EXTRABUSRSVD03
+#define SB_ONEOF_EXTRABUSRSVD03\
+ numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_3],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_EXTRA_BUS_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD03
+#undef SB_ONEOF_PCIEMEMRSVD03
+#define SB_ONEOF_PCIEMEMRSVD03\
+ numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_3],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG03
+#undef SB_ONEOF_PCIEMEMRSVDALIG03
+#define SB_ONEOF_PCIEMEMRSVDALIG03\
+ numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_3],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 26,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD03
+#undef SB_ONEOF_PCIEPFMEMRSVD03
+#define SB_ONEOF_PCIEPFMEMRSVD03\
+ numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_3],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_103
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG03
+#define SB_ONEOF_PCIEPFMEMRSVDALIG03\
+ numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_3],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 28,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD03
+#undef SB_ONEOF_PCIEIORSVD03
+#define SB_ONEOF_PCIEIORSVD03\
+ numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_3],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_IO_RESERVED,\
+ step = 4,\
+ default = TBT_DEFAULT_PCIE_IO_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // IO resource
+#endif //TBT_UP_PORT_FUNC == 3
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 4)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE04
+#undef SB_ONEOF_PCIEROOTPORTHPE04
+#define SB_ONEOF_PCIEROOTPORTHPE04\
+ oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_4],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD04
+#undef SB_ONEOF_EXTRABUSRSVD04
+#define SB_ONEOF_EXTRABUSRSVD04\
+ numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_4],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_EXTRA_BUS_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD04
+#undef SB_ONEOF_PCIEMEMRSVD04
+#define SB_ONEOF_PCIEMEMRSVD04\
+ numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_4],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG04
+#undef SB_ONEOF_PCIEMEMRSVDALIG04
+#define SB_ONEOF_PCIEMEMRSVDALIG04\
+ numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_4],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 26,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD04
+#undef SB_ONEOF_PCIEPFMEMRSVD04
+#define SB_ONEOF_PCIEPFMEMRSVD04\
+ numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_4],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG04
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG04
+#define SB_ONEOF_PCIEPFMEMRSVDALIG04\
+ numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_4],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 28,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD04
+#undef SB_ONEOF_PCIEIORSVD04
+#define SB_ONEOF_PCIEIORSVD04\
+ numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_4],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_IO_RESERVED,\
+ step = 4,\
+ default = TBT_DEFAULT_PCIE_IO_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // IO resource
+
+#if !defined (ULT_SUPPORT) || (ULT_SUPPORT == 0)
+#ifdef SB_ONEOF_PCIEROOTPORTEN05
+#undef SB_ONEOF_PCIEROOTPORTEN05
+#define SB_ONEOF_PCIEROOTPORTEN05\
+ oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_5],\
+ prompt = STRING_TOKEN (STR_PCH_PCIERP6_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif // PCIE root port5 disable
+#endif
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN06
+#undef SB_ONEOF_PCIEROOTPORTEN06
+#define SB_ONEOF_PCIEROOTPORTEN06\
+ oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_6],\
+ prompt = STRING_TOKEN (STR_PCH_PCIERP7_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif // PCIE root port6 disable
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN07
+#undef SB_ONEOF_PCIEROOTPORTEN07
+#define SB_ONEOF_PCIEROOTPORTEN07\
+ oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_7],\
+ prompt = STRING_TOKEN (STR_PCH_PCIERP8_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif // PCIE root port7 disable
+#endif //TBT_UP_PORT_FUNC == 4
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 5) && (ULT_SUPPORT == 1)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE05
+#undef SB_ONEOF_PCIEROOTPORTHPE05
+#define SB_ONEOF_PCIEROOTPORTHPE05\
+ oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_5],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD05
+#undef SB_ONEOF_EXTRABUSRSVD05
+#define SB_ONEOF_EXTRABUSRSVD05\
+ numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_5],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_EXTRA_BUS_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD05
+#undef SB_ONEOF_PCIEMEMRSVD05
+#define SB_ONEOF_PCIEMEMRSVD05\
+ numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_5],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG05
+#undef SB_ONEOF_PCIEMEMRSVDALIG05
+#define SB_ONEOF_PCIEMEMRSVDALIG05\
+ numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_5],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 26,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD05
+#undef SB_ONEOF_PCIEPFMEMRSVD05
+#define SB_ONEOF_PCIEPFMEMRSVD05\
+ numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_5],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG05
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG05
+#define SB_ONEOF_PCIEPFMEMRSVDALIG05\
+ numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_5],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 28,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD05
+#undef SB_ONEOF_PCIEIORSVD05
+#define SB_ONEOF_PCIEIORSVD05\
+ numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_5],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_IO_RESERVED,\
+ step = 4,\
+ default = TBT_DEFAULT_PCIE_IO_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // IO resource
+#endif // TBT_UP_PORT_FUNC == 5
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 6)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE06
+#undef SB_ONEOF_PCIEROOTPORTHPE06
+#define SB_ONEOF_PCIEROOTPORTHPE06\
+ oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_6],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+ option text = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+ option text = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+ endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD06
+#undef SB_ONEOF_EXTRABUSRSVD06
+#define SB_ONEOF_EXTRABUSRSVD06\
+ numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_6],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_EXTRA_BUS_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD06
+#undef SB_ONEOF_PCIEMEMRSVD06
+#define SB_ONEOF_PCIEMEMRSVD06\
+ numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_6],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG06
+#undef SB_ONEOF_PCIEMEMRSVDALIG06
+#define SB_ONEOF_PCIEMEMRSVDALIG06\
+ numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_6],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 26,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+ endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD06
+#undef SB_ONEOF_PCIEPFMEMRSVD06
+#define SB_ONEOF_PCIEPFMEMRSVD06\
+ numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_6],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+ step = 1,\
+ default = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG06
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG06
+#define SB_ONEOF_PCIEPFMEMRSVDALIG06\
+ numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_6],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 1,\
+ maximum = 31,\
+ step = 1,\
+ default = 28,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD06
+#undef SB_ONEOF_PCIEIORSVD06
+#define SB_ONEOF_PCIEIORSVD06\
+ numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_6],\
+ prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+ help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+ flags = RESET_REQUIRED,\
+ minimum = 0,\
+ maximum = TBT_MAX_PCIE_IO_RESERVED,\
+ step = 4,\
+ default = TBT_DEFAULT_PCIE_IO_RESERVED,\
+ option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+ endnumeric;
+#endif // IO resource
+#endif //TBT_UP_PORT_FUNC == 6
+
+#endif // TBT_INTEL_RC_CONFIG == 1
+
+#endif // CONTROL_DEFINITION
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+#ifdef CONTROLS_WITH_DEFAULTS
+ TBT_ONEOF_TBTENABLE
+ TBT_ONEOF_TBTWAKEUPSUPPORT
+ TBT_ONEOF_TBTAICSUPPORT
+ TBT_ONEOF_TBTHOSTLOCATION
+ TBT_ONEOF_TBTHANDLEPOC
+ TBT_ONEOF_TBTCACHELINESIZE
+ TBT_ONEOF_TBTCRSECURITYLEVEL
+ TBT_ONEOF_TBTRRSECURITYLEVEL
+ TBT_ONEOF_SMINOTIFYENABLED
+ TBT_ONEOF_SWSMIENABLED
+ TBT_ONEOF_NOTIFYENABLED
+ TBT_ONEOF_RMVRETRUNVALUE
+ TBT_ONEOF_OPTIONROM
+ TBT_ONEOF_TBTWAKEUPDELAY
+ TBT_ONEOF_TBTSWSMIDELAY
+ TBT_ONEOF_PERSLOTMEMRSVD
+ TBT_ONEOF_PERSLOTPFMEMRSVD
+ TBT_ONEOF_PERSLOTIORSVD
+ TBT_ONEOF_IORESOURCEENABLED
+ TBT_ONEOF_NVMVERSION
+#endif // CONTROLS_WITH_DEFAULTS
+//---------------------------------------------------------------------------
+
+
+//**********************************************************************
+// Advanced - TBT Configuration Form
+//**********************************************************************
+
+#ifdef ADVANCED_FORM_SET
+
+#ifdef FORM_SET_TYPEDEF
+ #include <TbtSetup.h>
+#endif
+
+#ifndef SUPPRESS_GRAYOUT_ENDIF //old Core
+ #define SUPPRESS_GRAYOUT_ENDIF endif;
+#endif
+
+#ifdef FORM_SET_GOTO
+// Define goto commands for the forms defined in this file
+ goto TBT_FORM_ID,
+ prompt = STRING_TOKEN(STR_TBT_FORM),
+ help = STRING_TOKEN(STR_TBT_FORM_HELP);
+#endif
+
+#ifdef FORM_SET_FORM
+// Define forms
+
+ #ifndef TBT_FORM_SETUP
+ #define TBT_FORM_SETUP
+
+ form formid = AUTO_ID(TBT_FORM_ID),
+ title = STRING_TOKEN(STR_TBT_FORM);
+
+ SUBTITLE(STRING_TOKEN (STR_TBT_SUBTITLE))
+
+ text
+ help = STRING_TOKEN (STR_TBT_SPEC_VERSION_HELP),
+ text = STRING_TOKEN (STR_TBT_SPEC_VERSION_NAME),
+ text = STRING_TOKEN (STR_TBT_SPEC_VERSION_VALUE),
+ flags = 0, key = 0;
+
+ text
+ help = STRING_TOKEN (STR_TBT_RC_VERSION_HELP),
+ text = STRING_TOKEN (STR_TBT_RC_VERSION_NAME),
+ text = STRING_TOKEN (STR_TBT_RC_VERSION_VALUE),
+ flags = 0, key = 0;
+
+ suppressif ideqval SETUP_DATA.TbtEnable == 0x0;
+ text
+ help = STRING_TOKEN (STR_TBT_HOST_HELP),
+ text = STRING_TOKEN (STR_TBT_HOST_NAME),
+ text = STRING_TOKEN (STR_TBT_HOST_VALUE),
+ flags = 0, key = 0;
+ endif;
+
+ SEPARATOR
+
+ grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER;
+ TBT_ONEOF_TBTENABLE
+ suppressif ideqval SETUP_DATA.TbtEnable == 0x0;
+ suppressif ideqval SETUP_DATA.TbtHRSeries == 0x1;
+ TBT_ONEOF_TBTRRSECURITYLEVEL
+ endif;
+ suppressif NOT ideqval SETUP_DATA.TbtHRSeries == 0x1; // if TBT chip is not equal CR, hide CR setting.
+ TBT_ONEOF_TBTCRSECURITYLEVEL
+ endif;
+ suppressif ideqval SETUP_DATA.TbtSecurityLevel == 0x5;
+ TBT_ONEOF_TBTWAKEUPSUPPORT
+ suppressif ideqval SETUP_DATA.TbtHRSeries == 0x1;
+ TBT_ONEOF_TBTAICSUPPORT
+ suppressif ideqval SETUP_DATA.TbtAICSupport == 0x0;
+ TBT_ONEOF_TBTHOSTLOCATION
+ endif;
+ endif;
+ #if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+ suppressif ideqval SETUP_DATA.TbtWakeupSupport == 0x1;
+ TBT_ONEOF_TBTHANDLEPOC
+ endif;
+ #endif
+ TBT_ONEOF_TBTCACHELINESIZE
+ TBT_ONEOF_SMINOTIFYENABLED
+ suppressif ideqval SETUP_DATA.SmiNotifyEnabled == 0x0;
+ TBT_ONEOF_SWSMIENABLED
+ TBT_ONEOF_NOTIFYENABLED
+ endif;
+ TBT_ONEOF_RMVRETRUNVALUE
+ TBT_ONEOF_OPTIONROM
+ suppressif NOT ideqval SETUP_DATA.TbtHRSeries == 0x1;
+ TBT_ONEOF_TBTWAKEUPDELAY
+ endif;
+ TBT_ONEOF_TBTSWSMIDELAY
+ TBT_ONEOF_IORESOURCEENABLED
+ TBT_ONEOF_PERSLOTMEMRSVD
+ TBT_ONEOF_PERSLOTPFMEMRSVD
+ suppressif ideqval SETUP_DATA.TbtIOresourceEnable ==0x0;
+ TBT_ONEOF_PERSLOTIORSVD
+ #if defined (TBT_FCTP) && (TBT_FCTP == 1)
+ suppressif NOT ideqval SETUP_DATA.TbtHRSeries == 0x1;
+ TBT_ONEOF_NVMVERSION
+ endif;
+ #else
+ #endif
+ endif; // TbtIOresourceEnable ==0x0;
+ endif; // SETUP_DATA.TbtSecurityLevel == 0x5
+ endif; // TbtEnable ==0x0;
+ endif; // SYSTEM_PASSWORD_USER
+ endform; // TBT_FORM_ID
+#endif // TBT_FORM_SETUP
+#endif // FORM_SET_FORM
+
+#endif // ADVANCED_FORM_SET
+
+//*************************************************************************
+//*************************************************************************
+//** **
+//** (C)Copyright 1985-2012, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//*************************************************************************
+//************************************************************************* \ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl
new file mode 100644
index 0000000..5752562
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl
@@ -0,0 +1,386 @@
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl 9 5/19/14 7:40a Barretlin $
+#
+# $Revision: 9 $
+#
+# $Date: 5/19/14 7:40a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl $
+#
+# 9 5/19/14 7:40a Barretlin
+# [TAG] EIP165410
+# [Category] Improvement
+# [Description] Support Thunderbolt AIC at NB PCIE slot
+# [Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+# TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+# TbtSetupReset.c
+#
+# 8 5/19/14 7:19a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Using setup item choose return value of _RMV method in
+# ASL code
+# [Files] TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+# TbtSetup.sdl TbtSetup.uni
+#
+# 7 2/10/14 1:30p Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] remove useless policy item and setup item
+# [Files] TbtOemBoard.h TbtOemBoard.c TbSetup.sdl TbtSetup.sd
+# TbtSetup.uni TbtSmm.c
+#
+# 6 1/05/14 2:13p Barretlin
+# [TAG] EIP N/A
+# [Category] New Feature
+# [Description] Support Thunderbolt feature Enable/Disable in run time
+# Support dynamic Thunderbolt AIC location in run time
+# [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni TbtSetupReset.c
+#
+# 5 6/17/13 4:25a Barretlin
+# [TAG] EIP126581
+# [Category] Improvement
+# [Description] add new AIC support setup item and change
+# TBWakeupSupport name
+# [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+#
+# 4 5/06/13 12:06a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Fix clone ACPI setup item fail
+# [Files] TbtSetup.sdl
+#
+# 3 3/21/13 6:00a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Clone PCIE prot swap setup item and set disable by
+# default
+# [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+#
+# 2 1/10/13 5:11a Barretlin
+#
+# 1 1/10/13 4:57a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+#
+# 11 12/12/12 4:47a Barretlin
+# [TAG] None
+# [Category] New Feature
+# [Description] Add Thunderbolt TSE Setup Reset Hook
+# [Files] TbtSetup.sdl TbtSetup.mak TbtSetup.cif TbtSetupReset.c
+#
+# 10 10/27/12 6:16a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Create new setup item for thunderbolt POC handling
+# [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+#
+# 9 8/20/12 5:16a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Fix IO resource workaround broken in 4C 2port case
+# [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+# TbtSetup.sd TbtSetup.uni
+#
+# 8 8/17/12 8:53a Barretlin
+# [TAG] EIP N/A
+# [Category] Improvement
+# [Description] Add IO resource workaround for Thunderbolt Spec1.1
+# Because new spec has removed IO resource for Thunderbolt device
+# [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+# TbtSetup.sd TbtSetup.uni
+#
+# 7 7/31/12 3:28a Barretlin
+# [TAG] EIP91119
+# [Category] Improvement
+# [Description] Resolution for enable/disable Thunderbolt device option
+# rom at POST time
+# [Files] TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+# TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+#
+# 6 5/22/12 10:05a Barretlin
+# [TAG] EIP90650
+# [Category] Spec Update
+# [Description] Specificatoin Update 0.94 - The default value of
+# OPTIONAL workaround for devices that don't support surprise-removal
+# should be disable.
+# [Files] TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+# TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+#
+# 5 5/20/12 10:42p Barretlin
+# [TAG] EIP90169
+# [Category] Spec Update
+# [Description] Specificatoin Update 0.93 - BIOS should stall wake
+# process for approximately 2.5 seconds to ensure
+# completeness of TBT link to all endpoint devices.
+# [Files] TbtSetup.sdl
+#
+# 4 3/05/12 1:11a Barretlin
+# [TAG] EIP83266
+# [Category] Spec Update
+# [Description] Specificatoin Update 0.90
+# [Files] TbtSetup.sdl
+# TbtSetup.sd
+# TbtSetup.uni
+# TbtSetup.cif
+# TbtOemBoard.h
+# TbtOemLib.c
+# TbtOemLib.h
+# TbtSmm.c
+# TbtPei..
+#
+# 2 2/19/12 11:52p Wesleychen
+# Add new setup item "SmiNotifyEnabled".
+#
+# 1 12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+#
+#*************************************************************************
+TOKEN
+ Name = "Tbt_Setup"
+ Value = "1"
+ Help = "Main switch to enable Tbt Setup support in Project"
+ TokenType = Boolean
+ TargetEQU = Yes
+ TargetMAK = Yes
+ Master = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_ENABLE"
+ Value = "1"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TB_WAKE_UP_SUPPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_AIC_SUPPORT"
+ Value = "0"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_AIC_SUPPORT"
+ Value = "0"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_AIC_LOCATION"
+ Value = "$(TBT_UP_PORT_FUNC) + 0x20"
+ TokenType = Integer
+ TargetMAK = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_DEV" "!=" "0x1C"
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_AIC_LOCATION"
+ Value = "$(TBT_UP_PORT_FUNC)"
+ TokenType = Integer
+ TargetMAK = Yes
+ TargetH = Yes
+ Token = "TBT_UP_PORT_DEV" "=" "0x1C"
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_HANDLE_POC"
+ Value = "1"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TB_SMI_NOTIFY_SUPPORT"
+ Value = "1"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_WAK_DELAY"
+ Value = "2500"
+ Help = "The delay time for wakup in ms.\0: Disable\500 = 500ms\1000 = 1 sec"
+ TokenType = Integer
+ TargetH = Yes
+End
+
+
+TOKEN
+ Name = "DEFAULT_TBT_SWSMI_DELAY"
+ Value = "0"
+ Help = "This delay time for TBT SwSMI in ms. \0 = Disable; 1 = 1ms; 1000 = 1sec ..."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_SKIP_TBT_OPTIONROM"
+ Value = "1"
+ Help = "Enable:1 / Disable:0 skip Thunderbolt Device Option Rom"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_RMV_RETURN_VALUE"
+ Value = "0"
+ TokenType = Integer
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "TBT_NVM"
+ Value = "17"
+ Help = "Thunderbolt Host Router EEEPROM Version. for IO source workaround using."
+ TokenType = Integer
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DEFAULT_TBT_IO_RESOURCE_SUPPORT"
+ Value = "0"
+ Help = "Enable:1 / Disable:0 IO resource for Thunderbolt Device"
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DISABLE_PCIE_ROOT_PORT_SWAP"
+ Value = "1"
+ Help = "Disable Intel RC PCI Express root port swap function."
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+End
+
+TOKEN
+ Name = "DISABLE_PCIE_ROOT_PORT_SWAP"
+ Value = "0"
+ Help = "Disable Intel RC PCI Express root port swap function."
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+ Token = "TBT_PCIE_PORT_SWAP_SUPPORT" "=" "1"
+End
+
+TOKEN
+ Name = "DISABLE_PCIE_ROOT_PORT_SWAP"
+ Value = "0"
+ Help = "Disable Intel RC PCI Express root port swap function. MahoBay platform has no this setup item."
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+ Token = "DESKTOP_306AX" "=" "1"
+End
+
+TOKEN
+ Name = "DISABLE_PCIE_ROOT_PORT_SWAP"
+ Value = "0"
+ Help = "Disable Intel RC PCI Express root port swap function. ChiefRiver platform has no this setup item."
+ TokenType = Boolean
+ TargetMAK = Yes
+ TargetH = Yes
+ Token = "MOBILE_306AX" "=" "1"
+End
+
+PATH
+ Name = "TbtSetup_DIR"
+End
+
+MODULE
+ Help = "Includes TbtSetup.mak to Project"
+ File = "TbtSetup.mak"
+End
+
+ELINK
+ Name = "$(BUILD_DIR)\TbtSetup.sdb"
+ Parent = "SETUP_SDBS"
+ Priority = 40
+ Help = "Includes generic TBT setup screens to the project"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "$(TbtSetup_DIR)\TbtSetup.sd"
+ Parent = "SETUP_DEFINITIONS"
+ Priority = 40
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "/I$(TbtSetup_DIR)"
+ Parent = "TBT_INCLUDES"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "-i $(TbtSetup_DIR)"
+ Parent = "SETUP_VFR_INCLUDES"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "InitiTbtInfo,"
+ Parent = "SetupStringInit"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "TbtProcessEnterSetup,"
+ Parent = "ProcessEnterSetup,"
+ InvokeOrder = AfterParent
+End
+
+ELINK
+ Name = "TbtSetupResetHook,"
+ Parent = "PreSystemResetHook,"
+ InvokeOrder = AfterParent
+End
+
+#*************************************************************************
+#*************************************************************************
+#** **
+#** (C)Copyright 1985-2012, American Megatrends, Inc. **
+#** **
+#** All Rights Reserved. **
+#** **
+#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+#** **
+#** Phone: (770)-246-8600 **
+#** **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.uni b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.uni
new file mode 100644
index 0000000..2774c89
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.uni
Binary files differ
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c
new file mode 100644
index 0000000..c046245
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c
@@ -0,0 +1,243 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2010, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c 8 5/19/14 7:40a Barretlin $
+//
+// $Revision: 8 $
+//
+// $Date: 5/19/14 7:40a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c $
+//
+// 8 5/19/14 7:40a Barretlin
+// [TAG] EIP165410
+// [Category] Improvement
+// [Description] Support Thunderbolt AIC at NB PCIE slot
+// [Files] TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+//
+// 7 1/05/14 2:14p Barretlin
+// [TAG] EIP N/A
+// [Category] New Feature
+// [Description] Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files] TbtSetup.sdl TbtSetup.sd TbtSetup.uni TbtSetupReset.c
+//
+// 6 6/21/13 7:53a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Fix build error with non Intel RC project
+// [Files] TbtSetupReset.c
+//
+// 5 6/21/13 5:16a Barretlin
+// [TAG] EIPNone
+// [Category] Bug Fix
+// [Severity] Minor
+// [Symptom] can not change Falcon Ridge security level
+// [RootCause] can not regconize Falcon Ridge chip
+// [Solution] add Falcon Ridge chip
+// [Files] TbtSetupReset.c
+//
+// 4 4/12/13 1:03p Barretlin
+//
+// 3 4/03/13 2:54a Barretlin
+// [TAG] EIP N/A
+// [Category] Improvement
+// [Description] Double check Security Level between Thunderbolt host FW
+// and BIOS are same or not for Redwood Ridge chip when entering setup
+// page.
+// [Files] TbtOemLib.c TbtOemLib.h TbtSetupReset.c
+//
+// 2 2/06/13 2:25a Barretlin
+//
+// 1 1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+//
+// 1 12/12/12 4:40a Barretlin
+// [TAG] None
+// [Category] New Feature
+// [Description] Add Thunderbolt TSE Setup Reset Hook
+// [Files] TbtSetupReset.c
+//
+// 6 1/13/10 2:13p Felixp
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//
+// Name: TbtSetupReset.c
+//
+// Description: Setup Reset Rountines
+//
+//<AMI_FHDR_END>
+//**********************************************************************
+
+#include <EFI.h>
+#include <Token.h>
+#include <Setup.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <TbtOemLib.h>
+#include <TbtOemBoard.h>
+#if defined(RESET_RUNTIME_SERVICES_SUPPORT) && (RESET_RUNTIME_SERVICES_SUPPORT == 0)
+#include <Protocol\PchReset\PchReset.h>
+#else
+#include <AmiCSPLib.h>
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+#include <PchRegsLpc.h>
+#endif
+#endif
+
+//----------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//----------------------------------------------------------------------------
+static SETUP_DATA gNewSetupData;
+static SETUP_DATA gOldSetupData;
+
+//----------------------------------------------------------------------------
+// GUID Definition(s)
+//----------------------------------------------------------------------------
+static EFI_GUID gEfiSetupGuid = SETUP_GUID;
+static EFI_GUID TbtHRStatusGuid = AMI_TBT_HR_STATUS_GUID;
+
+UINTN HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+AMI_TBT_HR_STATUS_DATA HRStatusData;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: TbtProcessEnterSetup
+//
+// Description: This function is a hook called when TSE determines
+// that it has to load the boot options in the boot
+// order. This function is available as ELINK.
+//
+// Input: VOID
+//
+// Output: VOID
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID TbtProcessEnterSetup(VOID)
+{
+ EFI_STATUS Status;
+ UINTN VariableSize = sizeof (SETUP_DATA);
+ UINT8 SecurityLevelState;
+
+ TRACE((-1, "TbtSetupReset.c: TbtProcessEnterSetup().....\n"));
+ Status = pRS->GetVariable(
+ L"Setup",
+ &gEfiSetupGuid,
+ NULL,
+ &VariableSize,
+ &gOldSetupData);
+ ASSERT_EFI_ERROR(Status);
+
+ Status = pRS->GetVariable( L"TbtHRStatusVar", \
+ &TbtHRStatusGuid, \
+ NULL, \
+ &HRStatusSize, \
+ &HRStatusData );
+ ASSERT_EFI_ERROR(Status);
+
+ //
+ // synchronize Thunderbolt security level config between BIOS and Thunderbolt
+ // host FW
+ if ((gOldSetupData.TbtEnable != 0) && (HRStatusData.TbtHRSeries != Cactus_Ridge)){
+ SecurityLevelState = SynchSecurityLevel(gOldSetupData.TbtSecurityLevel, gOldSetupData.TbtHostLocation);
+ TRACE((-1, "TbtSetupReset: Synchronizing Security Level between host Fw and BIOS state is %x\n", SecurityLevelState));
+ }
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure: TbtSetupResetHook
+//
+// Description: This function is a hook called after some control
+// modified in the setup utility by user. This
+// function is available as ELINK.
+//
+// Input: VOID
+//
+// Output: VOID
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID TbtSetupResetHook(VOID)
+{
+ EFI_STATUS Status;
+ UINT8 SetSecurityFlag = 0;
+ UINT8 ResetFlag = 0;
+ UINTN VariableSize;
+
+ VariableSize = sizeof (SETUP_DATA);
+ Status = pRS->GetVariable (
+ L"Setup",
+ &gEfiSetupGuid,
+ NULL,
+ &VariableSize,
+ &gNewSetupData);
+ ASSERT_EFI_ERROR(Status);
+
+ if ((!EFI_ERROR (Status)) && (gNewSetupData.TbtEnable != 0) && \
+ (HRStatusData.TbtHRSeries != Cactus_Ridge))
+ {
+ // Check Security Setup Setting first
+ if (gNewSetupData.TbtSecurityLevel != gOldSetupData.TbtSecurityLevel){
+ SetSecurityFlag |= 1;
+ } // Thunderbolt security level changed by user
+
+ // Check Thunderbolt host location
+ if (gNewSetupData.TbtHostLocation != gOldSetupData.TbtHostLocation){
+ ResetFlag |= 1;
+ }
+
+ // programming Redwood Ridge's/Falcon Ridge's/Win Ridge's Security Level
+ if (SetSecurityFlag != 0){
+ ProgramTbtSecurityLevel(&(gNewSetupData.TbtSecurityLevel), HRStatusData.TbtHRSeries, gNewSetupData.TbtHostLocation, FALSE);
+ ResetFlag |= 1;
+ }
+
+ // Reset system if need
+ if(ResetFlag != 0){
+#if defined(RESET_RUNTIME_SERVICES_SUPPORT) && (RESET_RUNTIME_SERVICES_SUPPORT == 0)
+ pRS->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
+#else
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+ SBLib_ExtResetSystem (SbResetFull);
+#else
+ SBLib_ResetSystem(FullReset);
+#endif
+#endif
+ EFI_DEADLOOP();
+ }
+ } // Get New Setup Data success && Thunderbolt Function is enable
+}
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2010, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-02 20:28:58 +0000