init. 1AQQW051HEADmaster

38 files changed, 12126 insertions, 0 deletions

diff --git a/Board/EM/Thunderbolt/ReleaseNotes.chm b/Board/EM/Thunderbolt/ReleaseNotes.chm
new file mode 100644
index 0000000..4330c0a
--- /dev/null
+++ b/Board/EM/Thunderbolt/ReleaseNotes.chm
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.c b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.c
new file mode 100644
index 0000000..a1ec300
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.c
@@ -0,0 +1,652 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.c 10    5/19/14 7:32a Barretlin $
+//
+// $Revision: 10 $
+//
+// $Date: 5/19/14 7:32a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.c $
+// 
+// 10    5/19/14 7:32a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 9     5/19/14 7:11a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Using setup item choose return value of _RMV method in
+// ASL code
+// [Files]  		TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+// 
+// 8     2/27/14 8:38a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	when thunderbolt is disable in run time, PCIE device whcih
+// using the same PCIE slot might  work abnormal
+// [RootCause]  	protect thunderbolt device function still work
+// [Solution]  	According thunderbolt policy to skip protect function
+// [Files]  		TbtDxe.c TbtDxeLib.c
+// 
+// 7     1/05/14 1:43p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtDxe.c TbtGpe.asl
+// 
+// 6     6/21/13 7:40a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error with non Intel RC project
+// [Files]  		TbtDxe.sdl TbtDxe.c TbtGpe.asl TbtDxeLib.h
+// 
+// 5     6/18/13 1:41p Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Follow Thunderbolt BIOS Spec rev1.0 to disable ASL code
+// to call Thunderbolt SwSMI when Native PCIE is enable
+// [Files]  		TbtDxe.c
+// 
+// 4     4/10/13 2:31p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change reported MMIO address way in ASL code
+// [Files]  		TbtDxe.c TbtGpe.asl
+// 
+// 3     4/10/13 1:26p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix Thunderbolt ready to boot event does not be excuted
+// on ULT platform
+// [Files]  		TbtDxe.c
+// 
+// 2     1/18/13 2:26a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Improve _RMV ASL code  for SharkBay RC
+// [Files]  		TbtDxe.sdl TbtDxe.c TbtGpe.asl
+// 
+// 1     1/10/13 4:56a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 11    12/12/12 3:02a Barretlin
+// [TAG]  		EIP108272
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+// [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 10    10/28/12 10:50p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change GPIO routing for SharkBay ULT platform
+// [Files]  		TbtDxe.c TbtGpe.asl TbtDxeLib.c TbtDxeLib.h TbtSmm.c
+// 
+// 9     10/03/12 9:15p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change Programming security level timing for saving
+// boot time
+// [Files]  		TbtPei.c TbtDxe.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+// 
+// 8     7/31/12 2:52a Barretlin
+// [TAG]  		EIP96350
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Change ACPI method from level trigger to edge
+// trigger(_L1x to _E1x)
+// [Files]  		TbtDxe.c
+// 
+// 7     7/31/12 2:46a Barretlin
+// [TAG]  		EIP91119
+// [Category]  	Improvement
+// [Description]  	Resolution for enable/disable Thunderbolt device option
+// rom at POST time
+// [Files]  		TbtDxe.c
+// 
+// 6     7/25/12 11:58p Barretlin
+// [TAG]  		EIP90644
+// [Category]  	Improvement
+// [Description]  	Change pre-boot event timing from ready to boot to pci
+// bus finish assigning resources
+// [Files]  		TbtDxe.sdl TbtDxe.c TbtDxeLib.c TbtDxeLib.h
+// 
+// 5     5/21/12 2:21a Barretlin
+// [TAG]  		EIP90003
+// [Category]  	Improvement
+// [Description]  	If TBT devices with option rom enabled, system maybe
+// cannot boot to OS.
+// [Files]  		TbtDxe.c TbtSmm.c TbtOemBoard.sdl
+// 
+// 4     5/07/12 6:34a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Add three setup items for debug
+// [Files]  		TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+// 
+// 3     4/14/12 4:50a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Improve ASL code, which redefines device name and RMV
+// mothod at same address when project supports RMV method, that might
+// cause conflict.
+// [Files]  		TbtDxe.c  TbtGpe.asl
+// 
+// 2     2/20/12 12:15a Wesleychen
+//  - Add ProgramTbtSecurityLevel().
+//  - Add a ready to boot event to invoke SW SMI for resource adjust.
+//  - Revise the ACPI table update routine become a protocol callback
+// routine.
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//*************************************************************************
+#include <Efi.h>
+#include <token.h>
+#include <Setup.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+#include <PciBus.h>
+#include <Acpi20.h>
+#include <Protocol\AcpiSupport.h>
+#include <TbtOemBoard.h>
+
+#if ACPI_SUPPORT
+ #if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x00010014)
+ #include <Protocol\AcpiSystemDescriptionTable.h>
+ #else
+ #include <Protocol\AcpiSupport.h>
+ #endif
+#endif
+#if CSM_SUPPORT
+#include <Protocol\CsmPlatform.h>
+#endif
+#ifndef EFI_SIGNATURE_16
+#define EFI_SIGNATURE_16(A, B)  ((A) | (B << 8))
+#endif
+
+#ifndef EFI_SIGNATURE_32
+#define EFI_SIGNATURE_32(A, B, C, D)  (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16))
+#endif
+
+EFI_GUID   gOemTbtProtocolGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+EFI_GUID   TbtHRStatusGuid     = AMI_TBT_HR_STATUS_GUID;
+EFI_GUID   gTbtHobGuid         = AMI_TBT_HOB_GUID;
+EFI_GUID   HobListGuid         = HOB_LIST_GUID;
+EFI_GUID   SetupGuid           = SETUP_GUID;
+#ifdef CSM_OPRROM_POLICY_GUID
+EFI_GUID   gCsmOpromPolicyGuid = CSM_OPRROM_POLICY_GUID;
+#endif
+
+AMI_TBT_PLATFORM_POLICY_PROTOCOL  *gAmiTbtPlatformPolicy = NULL;
+
+typedef struct {
+  UINT32  Signature;
+  UINT32  Length;
+} EFI_ACPI_COMMON_HEADER;
+
+EFI_EVENT             mAcpiEvent;
+//VOID                  *mAcpiReg;
+VOID                  *CsmOpromPolicyRegs;
+static EFI_BOOT_MODE  BootMode;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   DsdtTableUpdate
+//
+// Description: Update the DSDT table
+//
+// Input:       DsdtTable   - The table points to DSDT table.
+//
+// Output:      None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+DsdtTableUpdate (
+  IN ACPI_HDR   *DsdtTable
+  )
+{
+    UINT8   *CurrPtr;
+    UINT8   *DsdtPointer;
+    UINT32  *Signature = NULL;
+    UINT8   DoneFlag = 0;
+    UINT8   TbtAslStartPoint = 0;
+    UINT8   HexStr[36] = {'0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F','G','H',\
+                          'I','J','K','L','M','N','O','P','Q','R','S','T','U','V','W','X','Y','Z'};
+
+    CurrPtr = (UINT8 *) DsdtTable;
+    if (gAmiTbtPlatformPolicy != NULL && (!(gAmiTbtPlatformPolicy->TbtAICSupport))) {
+        TRACE((-1, "TbtDxe: Updating DSDT table for Thunderbolt\n"));
+        
+        for (DsdtPointer = CurrPtr;
+             DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
+             DsdtPointer++ )
+        {
+            Signature = (UINT32 *) DsdtPointer;
+            
+            if (*Signature == EFI_SIGNATURE_32 ('O', 'E', '1', 'X')) {
+                *DsdtPointer = '_';
+                // BIOS support of Thunderbolt devices Specification Update
+                // Revision 1.00
+                // Change ACPI method from level trigger to edge trigger(_L1x to _E1x)
+      #if defined ULT_SUPPORT && ULT_SUPPORT == 1
+                if(IsULTPchSeries()){
+                    *(DsdtPointer + 2) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt/16];
+                    *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt%16];
+                } else {
+                    *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt];
+                }
+      #else  
+                *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt];
+      #endif
+            
+                DoneFlag = DoneFlag | 0x0f;
+                TRACE((-1, "TbtDxe: Update Thunderbolt GPE event method\n"));
+            } // GPE event
+
+            if(DoneFlag == 0x0F)  return;
+        } //for loop
+    }// !(gAmiTbtPlatformPolicy->TbtAICSupport)
+    
+    if (gAmiTbtPlatformPolicy != NULL && gAmiTbtPlatformPolicy->TbtAICSupport) {
+        TRACE((-1, "TbtDxe: Updating DSDT table for Thunderbolt AIC\n"));
+
+        for (DsdtPointer = CurrPtr;
+             DsdtPointer <= (CurrPtr + ((EFI_ACPI_COMMON_HEADER *) CurrPtr)->Length);
+             DsdtPointer++ )
+        {
+            Signature = (UINT32 *) DsdtPointer;
+            switch(*Signature){
+                case (EFI_SIGNATURE_32 ('O', 'E', '1', 'X')):
+                    *DsdtPointer = '_';
+                    // BIOS support of Thunderbolt devices Specification Update
+                    // Revision 1.00
+                    // Change ACPI method from level trigger to edge trigger(_L1x to _E1x)
+      #if defined ULT_SUPPORT && ULT_SUPPORT == 1
+                    if(IsULTPchSeries()){
+                        *(DsdtPointer + 2) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt/16];
+                        *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt%16];
+                    } else {
+                        *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt];
+                    }
+      #else 
+                    *(DsdtPointer + 3) = HexStr[gAmiTbtPlatformPolicy->TbtHotPlugEvt];
+      #endif
+                    
+                    DoneFlag = DoneFlag | BIT00;
+                    TRACE((-1, "TbtDxe: Update Thunderbolt GPE event method\n"));
+                    break;
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+#if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 0
+                case (EFI_SIGNATURE_32 ('R', 'P', '0', '1')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 1
+                case (EFI_SIGNATURE_32 ('R', 'P', '0', '2')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 2
+                case (EFI_SIGNATURE_32 ('R', 'P', '0', '3')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 3
+                case (EFI_SIGNATURE_32 ('R', 'P', '0', '4')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 4
+                case (EFI_SIGNATURE_32 ('R', 'P', '0', '5')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 5
+                case (EFI_SIGNATURE_32 ('R', 'P', '0', '6')):
+#elif defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 6
+                case (EFI_SIGNATURE_32 ('R', 'P', '0', '7')):
+#else
+                case (EFI_SIGNATURE_32 ('R', 'P', '0', '8')):
+#endif
+#endif // TBT_INTEL_RC_CONFIG
+                    if (DoneFlag){
+                        if (gAmiTbtPlatformPolicy->Dev == 0x1C && \
+                            gAmiTbtPlatformPolicy->Fun != TBT_UP_PORT_FUNC){
+                            *(DsdtPointer + 3) = HexStr[(gAmiTbtPlatformPolicy->Fun + 1)];
+                            DoneFlag++;
+                            TRACE((-1, "TbtDxe: Update Thunderbolt Host ASL location to SB root port %x\n", gAmiTbtPlatformPolicy->Fun));
+                        }
+                        if (gAmiTbtPlatformPolicy->Bus == 0 && \
+                            gAmiTbtPlatformPolicy->Dev == 1){
+                            *DsdtPointer       = HexStr[25]; // 'P'
+                            *(DsdtPointer + 1) = HexStr[14]; // 'E'
+                            *(DsdtPointer + 2) = HexStr[16]; // 'G'
+                            *(DsdtPointer + 3) = HexStr[(gAmiTbtPlatformPolicy->Fun)];
+                            DoneFlag++;
+                            TRACE((-1, "TbtDxe: Update Thunderbolt Host ASL location to PEG%x\n", gAmiTbtPlatformPolicy->Fun));
+                        }
+                    }
+                    break;
+                default:
+                    break;
+            } // switch
+
+#if defined TBT_S3_WAK_SMI && TBT_S3_WAK_SMI == 1 && TBT_PCI0_INI_SUPPORT == 1
+            if(DoneFlag == 0x06)  return;
+#elif defined TBT_PCI0_INI_SUPPORT && TBT_PCI0_INI_SUPPORT == 1
+            if(DoneFlag == 0x05)  return;
+#else
+            if(DoneFlag == 0x04)  return;
+#endif
+        } // for loop
+    }// gAmiTbtPlatformPolicy->TbtAICSupport
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CreateTbtAcpiCallback
+//
+// Description: This function will create all ACPI components for SB when
+//              ACPI support protocol is available.
+//
+// Input:       Event   - Event of callback
+//              Context - Context of callback.
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID CreateTbtAcpiCallback (
+    IN EFI_EVENT        Event,
+    IN VOID             *Context )
+{
+  UINTN                      Index;
+  EFI_ACPI_SUPPORT_PROTOCOL  *As;
+  FACP_20                    *Table = NULL;
+  EFI_ACPI_TABLE_VERSION     Version;
+  UINTN                      Handle;
+  ACPI_HDR                   *DsdtPtr = NULL;
+  EFI_STATUS                 Status;
+  //UINT8                      SubBus;
+  UINTN                      HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+  AMI_TBT_HR_STATUS_DATA     HRStatusData;
+  UINT8                      TbtSmiNotifyEnable;
+  UINT8                      TbtBus;
+  SETUP_DATA                 *SetupData;
+  UINTN                      VariableSize = sizeof(SETUP_DATA);
+
+  Status = pBS->LocateProtocol(&gEfiAcpiSupportGuid, NULL, &As);
+
+  // Find DSDT ACPI Table
+  for (Index = 0; Index < ACPI_RSDT_TABLE_NUM; Index++) {
+    Status = As->GetAcpiTable(As, Index, &Table, &Version, &Handle);
+    if (EFI_ERROR(Status)) break;//no more tables left    
+
+    if ((Table->Header.Signature == FACP_SIG) && (DsdtPtr == NULL)) {
+        DsdtPtr = (ACPI_HDR*)Table->DSDT;
+
+        TRACE((-1, "TbtDxe: Found DSDT Table at 0x%08X\n", DsdtPtr));
+
+        DsdtTableUpdate (DsdtPtr);
+
+        // Thunderbolt BIOS Implementation guide for Redwood Ridge/Falcon Ridge 
+        // based devices rev 1.0
+        // 2.1.3.2 BIOS setup options for Thunderbolt
+        // Switch between Native PCIe Enable and Disabled with the following settings:
+        // --------------------------------------------------------------------
+        // Native PCIe support disabled (default) | Native PCIe support enabled
+        // --------------------------------------------------------------------
+        //           SCI Call Enabled             |      SCI Call Enabled
+        // --------------------------------------------------------------------
+        //           SMI Call Enabled             |      SMI Call Disabled
+        // --------------------------------------------------------------------
+        //          Notify Call Enabled           |      Notify Call Enabled
+        // --------------------------------------------------------------------
+        Status = pBS->AllocatePool( EfiBootServicesData,
+                              VariableSize,
+                              &SetupData );
+        ASSERT_EFI_ERROR(Status);
+        
+        Status = pRS->GetVariable( L"Setup", \
+                                   &SetupGuid, \
+                                   NULL, \
+                                   &VariableSize, \
+                                   SetupData );
+        ASSERT_EFI_ERROR (Status);
+
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+        if (SetupData->PciExpNative){
+            TbtSmiNotifyEnable = gAmiTbtPlatformPolicy->NotifyEnabled << 1;
+        } else {
+            TbtSmiNotifyEnable = gAmiTbtPlatformPolicy->SwSmiEnabled | (gAmiTbtPlatformPolicy->NotifyEnabled << 1);
+        }
+#else
+        // For non Intel RC project
+        TbtSmiNotifyEnable = gAmiTbtPlatformPolicy->SwSmiEnabled | (gAmiTbtPlatformPolicy->NotifyEnabled << 1);
+#endif
+        Status = UpdateAslNameObject(DsdtPtr, "TSNE", TbtSmiNotifyEnable);
+        TRACE((-1, "TbtDxe: Updating TSNE Name Object %r\n", Status));
+        ASSERT_EFI_ERROR(Status);
+        pBS->FreePool(SetupData);
+
+        //Update System MMIO PCIE Base address
+        //TRACE((-1, "TbtDxe: Update TBT Host DownStream port MMIO Base address in ASL code\n"));
+        //SubBus = READ_PCI8(gAmiTbtPlatformPolicy->Bus, gAmiTbtPlatformPolicy->Dev, gAmiTbtPlatformPolicy->Fun, PCI_PBUS+1);
+        //Status = UpdateAslNameObject(DsdtPtr, "PEMA", (PCIEX_BASE_ADDRESS | (SubBus << 20)));
+        //TRACE((-1, "TbtDxe: Updating PEMA Name Object %r\n", Status));
+        //ASSERT_EFI_ERROR(Status);
+
+        //Update TBT Host location bus in ASL code
+        if (gAmiTbtPlatformPolicy->TbtAICSupport){
+            if (gAmiTbtPlatformPolicy->Bus == 0 && gAmiTbtPlatformPolicy->Dev == 0x1c){
+                Status = UpdateAslNameObject(DsdtPtr, "TBRP", (gAmiTbtPlatformPolicy->Fun + 1));
+                TRACE((-1, "TbtDxe: Updating TBRP Name Object %r\n", Status));
+                ASSERT_EFI_ERROR(Status);
+            } else if (gAmiTbtPlatformPolicy->Bus == 0 && gAmiTbtPlatformPolicy->Dev == 1){
+                Status = UpdateAslNameObject(DsdtPtr, "TBRP", (gAmiTbtPlatformPolicy->Fun + 0x20));
+                TRACE((-1, "TbtDxe: Updating TBRP Name Object %r\n", Status));
+                ASSERT_EFI_ERROR(Status);
+            }
+        }
+        TbtBus = MMIO_READ8(TBT_CFG_ADDRESS(gAmiTbtPlatformPolicy->Bus, gAmiTbtPlatformPolicy->Dev, gAmiTbtPlatformPolicy->Fun, PCI_SBUS));
+        Status = UpdateAslNameObject(DsdtPtr, "TBUS", TbtBus);
+        TRACE((-1, "TbtDxe: Updating TBUS Name Object %r\n", Status));
+        ASSERT_EFI_ERROR(Status);
+        
+        //Update TBT Host Information in ASL code
+        TRACE((-1, "TbtDxe: Update TBT Host Information in ASL code\n"));
+        Status = pRS->GetVariable( L"TbtHRStatusVar", \
+                                   &TbtHRStatusGuid, \
+                                   NULL, \
+                                   &HRStatusSize, \
+                                   &HRStatusData );
+        if (!EFI_ERROR(Status)){
+            Status = UpdateAslNameObject(DsdtPtr, "TBHR", HRStatusData.TbtHRSeries);
+            TRACE((-1, "TbtDxe: Updating TBHR Name Object %r\n", Status));
+            ASSERT_EFI_ERROR(Status);
+        }
+        
+        // Update _RMV method return value for Thunderbolt
+        Status = UpdateAslNameObject( DsdtPtr, "TBMV", gAmiTbtPlatformPolicy->TbtRmvReturnValue);
+        TRACE((-1, "TbtDxe: Update TRMV ASL object value = %x, %r\n", gAmiTbtPlatformPolicy->TbtRmvReturnValue, Status));
+        ASSERT_EFI_ERROR(Status);
+
+        break;
+    }
+  }
+  // Kill the Event
+  pBS->CloseEvent(Event);
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   DisableTbtDeviceRomCallback
+//
+// Description: Disable all Tbt devices option ROM to aviod S4 resume problem.
+//
+// Input:       Event   - Event of callback
+//              Context - Context of callback.
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID DisableTbtDeviceRomCallback (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context )
+{
+  EFI_STATUS                  Status;
+  EFI_HANDLE                  Handle;
+  UINTN                       Size = sizeof(EFI_HANDLE);
+  CSM_PLATFORM_POLICY_DATA    *CsmOpromPolicyData;
+  EFI_PCI_IO_PROTOCOL         *PciIo;
+  PCI_DEV_INFO                *Device;
+
+  TRACE((-1, "TbtDxe: DisableTbtDeviceRomCallback() Entry\n"));
+
+  Status = pBS->LocateHandle(ByRegisterNotify, NULL, CsmOpromPolicyRegs, &Size, &Handle);
+  if (EFI_ERROR(Status)) return;
+
+  Status = pBS->HandleProtocol(Handle, &gCsmOpromPolicyGuid, &CsmOpromPolicyData);
+  if (EFI_ERROR(Status)) return;
+
+  if(CsmOpromPolicyData == NULL) return; //post-process OpROM callback
+  if(CsmOpromPolicyData->PciIo == NULL) return; // OEM Service ROM
+
+  PciIo = CsmOpromPolicyData->PciIo;
+  Device = (PCI_DEV_INFO*)PciIo;
+  while ((Device->Type != tPciRootBrg) && (Device->ParentBrg != NULL)) {
+    Device = Device->ParentBrg;
+    if (Device->Address.Addr.Bus != gAmiTbtPlatformPolicy->Bus) continue;
+    if (Device->Address.Addr.Device != gAmiTbtPlatformPolicy->Dev) continue;
+    if (Device->Address.Addr.Function != gAmiTbtPlatformPolicy->Fun) continue;
+    if (gAmiTbtPlatformPolicy->TbtOptionRom || (BootMode & BOOT_ON_S4_RESUME)){
+       CsmOpromPolicyData->ExecuteThisRom = FALSE;  //this attritube default is TRUE
+       TRACE((-1, "TbtDxe: ExecuteThisRom is setted FALSE.\n"));
+    }
+
+    break;
+  }
+
+  TRACE((-1, "TbtDxe: DisableTbtDeviceRomCallback() Exit\n"));
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InvokeSmiHandlerBeforeBoot
+//
+// Description: To invoke SW SMI befor boot for reaource adjust.
+//
+// Input:       Event   - Event of callback
+//              Context - Context of callback.
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID InvokeSmiHandlerBeforeBoot (
+  IN EFI_EVENT    Event,
+  IN VOID         *Context )
+{
+  TbtDxeInvokeSmiHandler();
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtDxe_Init
+//
+// Description: This function is the entry point for this DXE.
+//
+// Input:       ImageHandle - Image handle
+//              SystemTable - Pointer to the system table
+//
+// Output:      Return Status based on errors that occurred while waiting for
+//              time to expire.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtDxe_Init (
+    IN EFI_HANDLE       ImageHandle,
+    IN EFI_SYSTEM_TABLE *SystemTable )
+{
+    EFI_STATUS                 Status;
+    EFI_EVENT                  CsmOpromPolicyEvent = NULL;
+    TBT_HOB                    *gTbtHob;
+
+    InitAmiLib(ImageHandle, SystemTable);
+    TRACE((-1, "TbtDxe: TbtDxe_Init() Entry!!\n"));
+
+    Status = pBS->LocateProtocol( \
+                    &gOemTbtProtocolGuid, \
+                    NULL, \
+                    &gAmiTbtPlatformPolicy);
+    if (!EFI_ERROR(Status)) {
+        BootMode = GetBootMode();
+        if (gAmiTbtPlatformPolicy->TbtEnable){
+#ifdef CSM_OPRROM_POLICY_GUID
+            Status = RegisterProtocolCallback (&gCsmOpromPolicyGuid,
+                                               DisableTbtDeviceRomCallback,
+                                               NULL, &CsmOpromPolicyEvent,
+                                               &CsmOpromPolicyRegs);
+#endif
+            if (gAmiTbtPlatformPolicy->SmiNotifyEnabled) {
+#if (ACPI_SUPPORT)
+                Status = CreateReadyToBootEvent( TPL_NOTIFY,
+                                                 CreateTbtAcpiCallback,
+                                                 NULL,
+                                                 &mAcpiEvent);
+#endif       
+            } // SmiNotifyEnabled
+            
+            gTbtHob = (TBT_HOB *)GetEfiConfigurationTable(SystemTable, &HobListGuid);
+            if (gTbtHob){
+                Status = FindNextHobByGuid((EFI_GUID*)&gTbtHobGuid, &gTbtHob);
+                if (!(EFI_ERROR(Status)) && gTbtHob->TbtSecurityLevelFlag){
+                    TRACE((-1, "TbtDxe: Need Finish final programming !!!\n"));
+                    FinialProgramTbtSecurityLevel(gAmiTbtPlatformPolicy);
+                }
+            } // gTbtHob
+            else TRACE((-1, "TbtDxe: Can not find Thunderbolt Hob !!!\n"));
+        }// TbtEnable
+    }// gAmiTbtPlatformPolicy success
+    TRACE((-1, "TbtDxe: TbtDxe_Init() Exit!!\n"));
+
+    return EFI_SUCCESS;
+}
+
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.cif b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.cif
new file mode 100644
index 0000000..5e71252
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.cif
@@ -0,0 +1,14 @@
+<component>
+	name = "TbtDxe"
+	category = ModulePart
+	LocalRoot = "Board\EM\Thunderbolt\TbtDxe\"
+	RefName = "TbtDxe"
+[files]
+"TbtDxe.sdl"	
+"TbtDxe.mak"	
+"TbtDxe.c"	
+"TbtDxe.dxs"	
+"TbtGpe.asl"	
+"TbtDxeLib.c"	
+"TbtDxeLib.h"	
+<endComponent>
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.dxs b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.dxs
new file mode 100644
index 0000000..3e8c7e0
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.dxs
@@ -0,0 +1,54 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.dxs 1     1/10/13 4:56a Barretlin $
+//
+// $Revision: 1 $
+//
+// $Date: 1/10/13 4:56a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.dxs $
+// 
+// 1     1/10/13 4:56a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 2     2/20/12 12:15a Wesleychen
+// Revise the ACPI table update routine become a protocol callback
+// routine.
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//**********************************************************************
+#include <TbtOemboard.h>
+
+DEPENDENCY_START
+  AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID
+DEPENDENCY_END
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.mak b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.mak
new file mode 100644
index 0000000..7fa124a
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.mak
@@ -0,0 +1,104 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.mak 1     1/10/13 4:56a Barretlin $
+#
+# $Revision: 1 $
+#
+# $Date: 1/10/13 4:56a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.mak $
+# 
+# 1     1/10/13 4:56a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 2     2/20/12 12:09a Wesleychen
+# [TAG]         None
+# [Category]    Improvement
+# [Description] Add TbtDxeLib.
+# [Files]       TbtDxeLib.c; TbtDxeLib.h; TbtDxe.mak; TbtDxe.sdl;
+#               TbtDxe.cif.
+# 
+# 1     12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+# 
+# 6     1/13/10 2:13p Felixp
+# 
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name:	TbtDxe.mak
+#
+# Description:	
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+All : TbtDxe
+
+CFLAGS = $(CFLAGS) /I$(TbtDxe_DIR)
+#----------------------------------------------------------------------------
+#           Generic TBT dependencies
+#----------------------------------------------------------------------------
+$(BUILD_DIR)\TbtDxe.mak : $(TbtDxe_DIR)\$(@B).cif $(TbtDxe_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(TbtDxe_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+#----------------------------------------------------------------------------
+#           Add files into CSP Library
+#----------------------------------------------------------------------------
+AMI_CSP_LIB_LIBRARY_PATH = $(AMI_CSP_LIB_LIBRARY_PATH);$(TbtDxe_DIR)
+
+AMI_CSP_LIB_INCLUDE_FILES = "$(TbtDxe_DIR)\TbtDxeLib.h" + \
+$(AMI_CSP_LIB_INCLUDE_FILES)
+
+AMI_CSP_LIB_OBJS = $(AMI_CSP_LIB_OBJS) \
+$(BUILD_DIR)\TbtDxeLib.obj
+
+{$(TbtDxe_DIR)}.c{$(BUILD_DIR)}.obj::
+    $(CC) $(CFLAGS) /I $(TbtDxe_DIR) /Fo$(BUILD_DIR)\ $<
+
+$(BUILD_DIR)\TbtDxeLib.obj : $(TbtDxe_DIR)\TbtDxeLib.c
+
+#----------------------------------------------------------------------------
+#       Create TBT DXE Component
+#----------------------------------------------------------------------------
+TbtDxe : $(BUILD_DIR)\TbtDxe.mak TbtDxeBin
+TBT_DXE_OBJECTS =\
+$$(BUILD_DIR)\$(TbtDxe_DIR)\TbtDxe.obj \
+
+TbtDxeBin : $(AMICSPLib) $(AMIDXELIB)
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+    /f $(BUILD_DIR)\TbtDxe.mak all\
+    GUID=EFB7F614-BC8B-4DDD-B09A-22079FC1512F\
+    ENTRY_POINT=TbtDxe_Init \
+    "MY_INCLUDES=$(TBT_OEMBOARD_INCLUDES)"\
+    TYPE=BS_DRIVER\
+    DEPEX1=$(TbtDxe_DIR)\TbtDxe.dxs\
+    DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+    COMPRESS=1
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxe.sdl b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.sdl
new file mode 100644
index 0000000..eef55bc
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxe.sdl
@@ -0,0 +1,586 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.sdl 8     7/26/13 2:46a Barretlin $
+#
+# $Revision: 8 $
+#
+# $Date: 7/26/13 2:46a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxe.sdl $
+# 
+# 8     7/26/13 2:46a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Separate ASL code for Intel RC and non Intel RC
+# [Files]  		TbtDxe.sdl TbtDxe.cif
+# 
+# 7     6/21/13 7:40a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Fix build error with non Intel RC project
+# [Files]  		TbtDxe.sdl TbtDxe.c TbtGpe.asl TbtDxeLib.h
+# 
+# 6     5/27/13 8:54a Barretlin
+# [TAG]  		EIP122882
+# [Category]  	Bug Fix
+# [Severity]  	Normal
+# [Symptom]  	let system entering sleep status continually and waking up
+# system via Thunderbolt Lan device, system will auto-wake
+# [RootCause]  	PCIE PME status is not cleared by ASL in SB module
+# [Solution]  	Clear PCIE PME status againg before system entring sleep
+# status
+# [Files]  		TbtDxe.sdl TbtGpe.asl
+# 
+# 5     4/10/13 1:37p Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Adding a TPTS method into _PTS method in ASL code
+# [Files]  		TbtDxe.sdl TbtGpe.asl
+# 
+# 4     3/21/13 4:58a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Use token to decide where location of OS_UP command for
+# RR chip is
+# [Files]  		TbtDxe.sdl TbtGpe.asl
+# 
+# 3     2/08/13 1:23a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Following Intel sample code move _INI method of
+# thunderbolt from under PCIE root port to under system bus
+# [Files]  		TbtDxe.sdl TbtGpe.asl
+# 
+# 2     1/18/13 2:26a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Improve _RMV ASL code  for SharkBay RC
+# [Files]  		TbtDxe.sdl TbtDxe.c TbtGpe.asl
+# 
+# 1     1/10/13 4:56a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 7     12/12/12 3:02a Barretlin
+# [TAG]  		EIP108272
+# [Category]  	Spec Update
+# [Severity]  	Important
+# [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+# [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+# TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+# 
+# 6     7/25/12 11:58p Barretlin
+# [TAG]  		EIP90644
+# [Category]  	Improvement
+# [Description]  	Change pre-boot event timing from ready to boot to pci
+# bus finish assigning resources
+# [Files]  		TbtDxe.sdl TbtDxe.c TbtDxeLib.c TbtDxeLib.h
+# 
+# 5     5/22/12 9:48a Barretlin
+# [TAG]  		EIPNone
+# [Category]  	Improvement
+# [Description]  	Rollback default value of token
+# [Files]  		TbtDxe.sdl
+# 
+# 4     5/07/12 6:30a Barretlin
+# [TAG]  		None
+# [Category]  	Improvement
+# [Description]  	change default value of token, because of it is need
+# SwSMI when S3 resume
+# [Files]  		TbtDxe.sdl
+# 
+# 3     4/16/12 10:17a Barretlin
+# [TAG]  		EIP86590
+# [Category]  	Bug Fix
+# [Symptom]  	Only EP#1 can be detected after resume from S3
+# [Solution]  	Adding a TWAK method into _WAK method
+# [Files]  		TbtDxe.sdl  TbtGpe.asl
+# 
+# 2     2/20/12 12:09a Wesleychen
+# [TAG]         None
+# [Category]    Improvement
+# [Description] Add TbtDxeLib.
+# [Files]       TbtDxeLib.c; TbtDxeLib.h; TbtDxe.mak; TbtDxe.sdl;
+#               TbtDxe.cif.
+# 
+# 1     12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+# 
+#*************************************************************************
+
+TOKEN
+	Name  = "TbtDxe_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable TbtDxe support in Project"
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "1"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "0"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "0"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "2"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "1"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "1"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "1"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "3"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "2"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "2"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "2"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "4"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "3"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "3"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "3"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "5"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "4"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "4"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "4"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "6"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "5"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "5"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "5"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "7"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "6"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "6"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "6"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "8"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "7"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RPNum"
+	Value  = "7"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_FUNC" "=" "7"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RP_NUM"
+	Value  = "\_SB.PCI0.RP0$(TBT_RPNum)"
+	TokenType = Expression
+	TargetH = Yes
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RP_NUM"
+	Value  = "\_SB.PCI0.PEX$(TBT_RPNum)"
+	TokenType = Expression
+	TargetH = Yes
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RMV_REPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Enable:1/Disable:0 Thunderbolt module report _RMV function in ASL code."
+	Token = "DESKTOP_306AX" "=" "1"
+	Token = "HOTPLUG_RMV_SUPPORT" "=" "0"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+TOKEN
+	Name  = "TBT_RMV_REPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Enable:1/Disable:0 Thunderbolt module report _RMV function in ASL code."
+	Token = "MOBILE_306AX" "=" "1"
+	Token = "HOTPLUG_RMV_SUPPORT" "=" "0"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+TOKEN
+	Name  = "TBT_RMV_REPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Enable:1/Disable:0 Thunderbolt module report _RMV function in ASL code."
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+TOKEN
+	Name  = "TBT_WAK_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Main switch to enable TWAK method in ASL code"
+End
+
+TOKEN
+	Name  = "TBT_PTS_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Main switch to enable TPTS method in ASL code"
+End
+
+TOKEN
+	Name  = "TBT_PCI0_INI_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Enable/Disable OS_UP command of RR chip under _INI method of system bus in ASL code."
+End
+
+TOKEN
+	Name  = "TBT_S3_WAK_SMI"
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Enable:1/Disable:0 trigger TBT SMI in ASL code when S3 resuming"
+End
+
+TOKEN
+	Name  = "TBT_WAK"
+	Value  = "\_SB.PCI0.RP0$(TBT_RPNum).TWAK(Arg0)"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Lock = Yes
+	Token = "TBT_WAK_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "TBT_WAK"
+	Value  = "\_SB.PCI0.PEX$(TBT_RPNum).TWAK(Arg0)"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Lock = Yes
+	Token = "TBT_WAK_SUPPORT" "=" "1"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+TOKEN
+	Name  = "TBT_PTS"
+	Value  = "\_SB.PCI0.RP0$(TBT_RPNum).TPTS(Arg0)"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Lock = Yes
+	Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "TBT_PTS"
+	Value  = "\_SB.PCI0.PEX$(TBT_RPNum).TPTS(Arg0)"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Lock = Yes
+	Token = "TBT_PTS_SUPPORT" "=" "1"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+TOKEN
+	Name  = "TBT_CLEAR_PME_STATUS"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Enable:1/Disable:0 Clear PCIE root port thunderbolt host located PME status in ASL code."
+	Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "TBT_CLEAR_PME_STATUS"
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Enable:1/Disable:0 Clear PCIE root port thunderbolt host located PME status in ASL code."
+	Token = "MOBILE_306AX" "=" "1"
+	Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "TBT_CLEAR_PME_STATUS"
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Enable:1/Disable:0 Clear PCIE root port thunderbolt host located PME status in ASL code."
+	Token = "DESKTOP_306AX" "=" "1"
+	Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "TBT_INI"
+	Value  = "\_SB.PCI0.RP0$(TBT_RPNum).TINI()"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Lock = Yes
+	Token = "TBT_PCI0_INI_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "TBT_INI"
+	Value  = "\_SB.PCI0.PEX$(TBT_RPNum).TINI()"
+	TokenType = Expression
+	TargetMak = Yes
+	TargetH = Yes
+	Lock = Yes
+	Token = "TBT_PCI0_INI_SUPPORT" "=" "1"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+MODULE
+	Help  = "Includes TbtDxe.mak to Project"
+	File  = "TbtDxe.mak"
+End
+
+PATH
+	Name  = "TbtDxe_DIR"
+End
+
+ELINK
+	Name  = "/I$(TbtDxe_DIR)"
+	Parent  = "TBT_DXE_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "TBT_DXE_INCLUDES"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(TbtDxe_DIR)\TbtGpe.asl"
+	Parent  = "INTEL_GENERIC_ASL"
+	InvokeOrder = AfterParent
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+ELINK
+	Name  = "$(TbtDxe_DIR)\TbtGpeNonRC.asl"
+	Parent  = "GENERIC_ASL"
+	InvokeOrder = AfterParent
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "0"
+End
+
+ELINK
+	Name  = "$(TBT_WAK)"
+	Parent  = "ASL_WAK"
+	Help  = "Include TBT Specific Function at WAK.\Arg0 is a sleep state the System is resuming from. "
+	SrcFile  = "$(TbtDxe_DIR)\TbtGpe.ASL"
+	InvokeOrder = AfterParent
+	Token = "TBT_WAK_SUPPORT" "=" "1"
+End
+
+ELINK
+	Name  = "$(TBT_PTS)"
+	Parent  = "ASL_PTS"
+	Help  = "Include TBT Specific Function at PTS.\Arg0 is a sleep state the System is resuming from. "
+	SrcFile  = "$(TbtDxe_DIR)\TbtGpe.ASL"
+	InvokeOrder = AfterParent
+	Token = "TBT_PTS_SUPPORT" "=" "1"
+End
+
+ELINK
+	Name  = "$(TBT_INI)"
+	Parent  = "ASL_PCI0_INI"
+	Help  = "Include TBT Specific Function at _INI method of PCI0."
+	SrcFile  = "$(TbtDxe_DIR)\TbtGpe.ASL"
+	InvokeOrder = AfterParent
+	Token = "TBT_PCI0_INI_SUPPORT" "=" "1"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\TbtDxe.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "OEM_PCI_DEVICE_CALLBACK(0, 0, TbtProtectedPciDevice),"
+	Parent  = "OEM_SKIP_PCI_DEVICE"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "TbtDxeInvokeSmiHandler,"
+	Parent  = "ConnectRootBridgeHandles,"
+	InvokeOrder = AfterParent
+End
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.c b/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.c
new file mode 100644
index 0000000..45f6768
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.c
@@ -0,0 +1,209 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxeLib.c 4     5/16/14 6:02p Barretlin $
+//
+// $Revision: 4 $
+//
+// $Date: 5/16/14 6:02p $
+//*************************************************************************
+// Revision History
+// ----------------
+//
+//*************************************************************************
+//---------------------------------------------------------------------------
+// Include(s)
+//---------------------------------------------------------------------------
+
+#include <Efi.h>
+#include <Token.h>
+#include <Setup.h>
+#include <AmiPeiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+// Produced Protocols
+
+// Consumed Protocols
+
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+// Macro Definition(s)
+
+// Type Definition(s)
+
+// Function Prototype(s)
+
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+
+// GUID Definition(s)
+
+// Protocol Definition(s)
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtProtectedPciDevice
+//
+// Description: This function is called by PCI Bus Driver before configuring
+//              or disabling any PCI device. This function should examine the
+//              Vendor/Device ID or PCI Bus, Device and Function numbers to
+//              make sure it is not a south bridge device or any other device
+//              which should no be configured by PCI Bus Driver.
+//
+// Input:       *PciDevice - Pointer to PCI Device Info structure.
+//
+// Output:      EFI_STATUS
+//                  EFI_SUCCESS     - SKIP this device, do not touch
+//                                    PCI Command register.
+//                  EFI_UNSUPPORTED - DON'T SKIP this device do complete
+//                                    enumeration as usual.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtProtectedPciDevice (
+  IN PCI_DEV_INFO *PciDevice )
+{
+    AMI_TBT_PLATFORM_POLICY_PROTOCOL  *gAmiTbtPlatformPolicy = NULL;
+    EFI_GUID      gOemTbtProtocolGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+    EFI_STATUS    Status;
+    UINT8         TBus = TBT_UP_PORT_BUS;
+    UINT8         TDev = TBT_UP_PORT_DEV;
+    UINT8         TFun = TBT_UP_PORT_FUNC;
+
+    TRACE((-1, "\nTbtDxe: TbtProtectedPciDevice Entry !!!\n"));
+    Status = pBS->LocateProtocol( &gOemTbtProtocolGuid, \
+                                  NULL, \
+                                  &gAmiTbtPlatformPolicy);
+    if (EFI_ERROR(Status) || (!(gAmiTbtPlatformPolicy->TbtEnable))){
+        return EFI_UNSUPPORTED;
+    }
+
+    if ((!EFI_ERROR(Status)) && (gAmiTbtPlatformPolicy->TbtAICSupport == 1)){
+        if (gAmiTbtPlatformPolicy->Dev == 0x1c){
+            TFun   = gAmiTbtPlatformPolicy->Fun;
+        } else {
+            TBus   = gAmiTbtPlatformPolicy->Bus;
+            TDev   = gAmiTbtPlatformPolicy->Dev;
+            TFun   = gAmiTbtPlatformPolicy->Fun;
+        }
+    }
+    TRACE((-1, "TbtDxe: PciDevice @B:%x|D:%x|F:%x !!!\n", PciDevice->Address.Addr.Bus, PciDevice->Address.Addr.Device, PciDevice->Address.Addr.Function));
+#if defined TBT_PCIBUS_SKIP && TBT_PCIBUS_SKIP == 1
+    while ((PciDevice->Type != tPciRootBrg) && (PciDevice->ParentBrg != NULL)) {
+        PciDevice = PciDevice->ParentBrg;
+        if (PciDevice->Address.Addr.Bus != TBus) continue;
+        if (PciDevice->Address.Addr.Device != TDev) continue;
+        if (PciDevice->Address.Addr.Function != TFun) continue;
+    
+        TRACE((-1, "TbtDxe: Skip thunderbolt device before PCI BUS assign resource.\n"));
+        return EFI_SUCCESS;
+    }
+#endif
+
+  return EFI_UNSUPPORTED;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtDxeInvokeSmiHandler
+//
+// Description: Invoke SW SMI befor boot for reaource adjust.
+//
+// Input:       None
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID TbtDxeInvokeSmiHandler(){
+    AMI_TBT_PLATFORM_POLICY_PROTOCOL  *gAmiTbtPlatformPolicy = NULL;
+    EFI_GUID      gOemTbtProtocolGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+    EFI_STATUS    Status;
+	
+    TRACE((-1, "TbtDxe: TbtDxeInvokeSmiHandler\n"));
+	Status = pBS->LocateProtocol( &gOemTbtProtocolGuid, \
+                                  NULL, \
+                                  &gAmiTbtPlatformPolicy);
+    if ((!EFI_ERROR(Status)) && (gAmiTbtPlatformPolicy->TbtEnable)){
+        IoWrite8 (SW_SMI_IO_ADDRESS, TBT_SWSMI_VALUE); //trigger SwSMI for Thunderbolt
+    }
+}
+
+#if defined ULT_SUPPORT && ULT_SUPPORT == 1
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   IsULTPchSeries
+//
+// Description: This function is to get PCH series is ULT series or not
+//
+// Input:       None
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+IsULTPchSeries( VOID ){
+    UINT16   PchDeviceId;
+    
+    PchDeviceId = MmPciRead16 (0x00, LPC_DEVICE, LPC_FUNC, 0x02);
+    switch(PchDeviceId){
+       case 0x9C40:   ///< LynxPoint LP Unfuse
+       case 0x9C41:   ///< LynxPoint LP Mobile Super SKU
+       case 0x9C42:   ///< LynxPoint LP Mobile TBD SKU
+       case 0x9C43:   ///< LynxPoint LP Mobile Premium SKU
+       case 0x9C44:   ///< LynxPoint LP Mobile TBD SKU
+       case 0x9C45:   ///< LynxPoint LP Mobile Mainstream SKU
+       case 0x9C46:   ///< LynxPoint LP Mobile TBD SKU
+       case 0x9C47:   ///< LynxPoint LP Mobile Value SKU
+       case 0x9CC1:   ///< WildcatPoint LP Mobile Super SKU HSW
+       case 0x9CC2:   ///< WildcatPoint LP Mobile Super SKU BDW U
+       case 0x9CC3:   ///< WildcatPoint LP Mobile Premium SKU BDW U
+       case 0x9CC4:   ///< WildcatPoint LP Mobile TBD SKU
+       case 0x9CC5:   ///< WildcatPoint LP Mobile Base SKU BDW U
+       case 0x9CC6:   ///< WildcatPoint LP Mobile Super SKU BDW Y
+       case 0x9CC7:   ///< WildcatPoint LP Mobile Premium SKU BDW Y
+       case 0x9CC8:   ///< WildcatPoint LP Mobile TBD SKU
+       case 0x9CC9:   ///< WildcatPoint LP Mobile Base SKU BDW Y
+       case 0x9CCA:   ///< WildcatPoint LP Mobile TBD SKU
+       case 0x9CCB:   ///< WildcatPoint LP Mobile Performance SKU
+           return TRUE;
+    }
+    return FALSE;
+}
+#endif
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.h b/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.h
new file mode 100644
index 0000000..a1dbaa0
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtDxeLib.h
@@ -0,0 +1,74 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtDxeLib.h 2     6/21/13 7:41a Barretlin $
+//
+// $Revision: 2 $
+//
+// $Date: 6/21/13 7:41a $
+//*************************************************************************
+// Revision History
+// ----------------
+//
+//*************************************************************************
+#include <Efi.h>
+#include <token.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+#ifndef __TBTDXELIB_H__
+#define __TBTDXELIB_H__
+
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+EFI_STATUS TbtProtectedPciDevice
+(
+  IN PCI_DEV_INFO *PciDevice
+);
+#endif
+
+VOID TbtDxeInvokeSmiHandler();
+
+#if defined ULT_SUPPORT && ULT_SUPPORT == 1
+BOOLEAN
+IsULTPchSeries
+( 
+  VOID 
+);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtDxe/TbtGpe.asl b/Board/EM/Thunderbolt/TbtDxe/TbtGpe.asl
new file mode 100644
index 0000000..ad17b9f
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtDxe/TbtGpe.asl
@@ -0,0 +1,797 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtGpe.asl 22    5/19/14 7:32a Barretlin $
+//
+// $Revision: 22 $
+//
+// $Date: 5/19/14 7:32a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtDxe/TbtGpe.asl $
+// 
+// 22    5/19/14 7:32a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 21    5/19/14 7:13a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Using setup item choose return value of _RMV method in
+// ASL code
+// [Files]  		TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+// 
+// 20    2/22/14 5:50p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Bug Fix
+// [Severity]  	Important
+// [Symptom]  	For Cactus Ridge host the thunderbolt hotplug event cannot
+// be trigger
+// [RootCause]  	signal event is not trigger under _INI/TINI method cause
+// OS will not set GPE event enable bit
+// [Solution]  	Change signal event location of _INI/TINI method
+// [Files]  		TbtGpe.asl
+// 
+// 19    2/18/14 12:07p Barretlin
+// 
+// 18    2/18/14 6:02a Barretlin
+// [TAG]  		EIP152401
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Update Intel Thunderbolt Sample code rev 1.9
+// [Files]  		TbtSmm.c TbtGpe.asl TbtOemPorting.asl
+// 
+// 17    1/05/14 1:43p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtDxe.c TbtGpe.asl
+// 
+// 16    7/26/13 2:24a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	remove non Intel RC config
+// [Files]  		TbtGpe.asl
+// 
+// 15    6/21/13 7:41a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error with non Intel RC project
+// [Files]  		TbtDxe.sdl TbtDxe.c TbtGpe.asl TbtDxeLib.h
+// 
+// 14    6/19/13 9:24a Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Update Intel Thunderbolt sample code to rev. 1.7
+// [Files]  		TbtGpe.asl
+// 
+// 13    5/27/13 8:57a Barretlin
+// [TAG]  		EIP124914
+// [Category]  	New Feature
+// [Description]  	Support Falcon Ridge chip
+// [Files]  		TbtGpe.asl
+// 
+// 12    5/27/13 8:54a Barretlin
+// [TAG]  		EIP122882
+// [Category]  	Bug Fix
+// [Severity]  	Normal
+// [Symptom]  	let system entering sleep status continually and waking up
+// system via Thunderbolt Lan device, system will auto-wake
+// [RootCause]  	PCIE PME status is not cleared by ASL in SB module
+// [Solution]  	Clear PCIE PME status againg before system entring sleep
+// status
+// [Files]  		TbtDxe.sdl TbtGpe.asl
+// 
+// 11    5/27/13 8:46a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	add sychronized method to make sure executed sequence
+// is one by one
+// [Files]  		TbtGpe.asl
+// 
+// 10    4/12/13 1:18p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Rollback OSUP method and following Intel sample code
+// [Files]  		TbtGpe.asl
+// 
+// 9     4/10/13 2:31p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change reported MMIO address way in ASL code
+// [Files]  		TbtDxe.c TbtGpe.asl
+// 
+// 8     4/10/13 1:37p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Adding a TPTS method into _PTS method in ASL code
+// [Files]  		TbtDxe.sdl TbtGpe.asl
+// 
+// 7     4/03/13 8:42a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix might hang up when S3 resuming
+// [Files]  		TbtGpe.asl
+// 
+// 6     3/21/13 4:58a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Use token to decide where location of OS_UP command for
+// RR chip is
+// [Files]  		TbtDxe.sdl TbtGpe.asl
+// 
+// 5     2/08/13 1:23a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Following Intel sample code move _INI method of
+// thunderbolt from under PCIE root port to under system bus
+// [Files]  		TbtDxe.sdl TbtGpe.asl
+// 
+// 4     2/06/13 7:49a Barretlin
+// [TAG]  		EIP114556
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Update RR handshake flow for Thunderbolt RR Spec 0.9
+// [Files]  		TbtGpe.asl
+// 
+// 3     1/24/13 1:31a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	TBT debug setup item function fail
+// [RootCause]  	ASL updating error
+// [Files]  		TbtGpe.asl
+// 
+// 2     1/18/13 2:26a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Improve _RMV ASL code  for SharkBay RC
+// [Files]  		TbtDxe.sdl TbtDxe.c TbtGpe.asl
+// 
+// 1     1/10/13 4:56a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 6     12/12/12 3:02a Barretlin
+// [TAG]  		EIP108272
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+// [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 5     10/28/12 10:50p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change GPIO routing for SharkBay ULT platform
+// [Files]  		TbtDxe.c TbtGpe.asl TbtDxeLib.c TbtDxeLib.h TbtSmm.c
+// 
+// 4     5/07/12 6:34a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Add three setup items for debug
+// [Files]  		TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+// 
+// 3     4/16/12 10:17a Barretlin
+// [TAG]  		EIP86590
+// [Category]  	Bug Fix
+// [Symptom]  	Only EP#1 can be detected after resume from S3
+// [Solution]  	Adding a TWAK method into _WAK method
+// [Files]  		TbtDxe.sdl  TbtGpe.asl
+// 
+// 2     4/14/12 4:50a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Improve ASL code, which redefines device name and RMV
+// mothod at same address when project supports RMV method, that might
+// cause conflict.
+// [Files]  		TbtDxe.c  TbtGpe.asl
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//*************************************************************************
+Scope(\)
+{
+    Mutex(OSUM, 0)  // OS Up mutex
+    Event(WFEV)
+//    Name(TBTE, 0) // Thunderbolt function enable
+    Name(PEMA, ASL_PCIEX_BASE_ADDRESS) // PCIE base address
+    Name(TBRP, ASL_TBT_RPNum) // PCIE root port location for Thunderbolt Host
+    Name(TBUS, 0xFF) // Thunderbolt Host BUS number
+    Name(TBHR, 0xFF) //1:Cactus Ridge 2:Redwood Ridge 3:Falcon Ridge 4:Win Ridge will be updated
+    Name(TBMV, 0xFF) // _RMV return value for Thunderbolt
+    Name(RPR6, 0)
+    Name(RPR7, 0)
+    Name(RPR8, 0)
+    Name(RPR9, 0)
+    Name(RPRA, 0)
+    Name(RPRB, 0)
+}
+
+Scope(\_SB)
+{
+    // Include OEM porting required ASL
+    Include("..\\TbtOemBoard\\TbtOemPorting.asl")
+
+	// WMI ACPI device to control TBT force power
+    Device(WMTF)
+    {
+        // pnp0c14 is pnp id assigned to WMI mapper
+        Name(_HID, "PNP0C14")
+        Name(_UID, "TBFP")   
+        
+        Name(_WDG, Buffer() {
+            // {86CCFD48-205E-4A77-9C48-2021CBEDE341}
+            0x48, 0xFD, 0xCC, 0x86,
+            0x5E, 0x20,
+            0x77, 0x4A,
+            0x9C, 0x48,
+            0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41,
+            84, 70,    // Object Id (TF)
+            1,         // Instance Count
+            0x02       // Flags (WMIACPI_REGFLAG_METHOD)
+        })
+        
+        // Set TBT force power
+        // Arg2 is force power value
+        Method(WMTF, 3)
+        {
+            CreateByteField(Arg2,0,FP)
+            
+            If(FP)
+            {
+                TBFP(1)
+            }
+            Else
+            {
+                TBFP(0)
+            }						
+        }
+    }
+}
+
+Scope(\_GPE)
+{
+  // OSUP method apply TB2P<->P2TB handshake procedure 
+  // with Command = OS_Up
+  // Arg0 - Memory mapped IO address of RR host router upstream port
+  Method(OSUP, 1)
+  {
+      Add(Arg0, 0x548, Local0)
+      OperationRegion(PXVD,SystemMemory,Local0,0x08)
+      Field(PXVD,DWordAcc, NoLock, Preserve)
+      {
+        TB2P, 32, 
+        P2TB, 32
+      }    
+
+      Store(100, Local1)
+      Store(0x0D, P2TB) // Write (OS_Up << 1) | 1 to PCIe2TBT
+      While(LGreater(Local1, 0))
+      {
+          Store(Subtract(Local1, 1), Local1)
+          Store(TB2P, Local2)
+          If(LEqual(Local2, 0xFFFFFFFF))// Device gone
+          {
+              Return(2)
+          }
+          If(And(Local2, 1)) // Done
+          {
+              break
+          }
+          Sleep(50)
+      }
+      Store(0x00, P2TB) // Write 0 to PCIe2TBT
+      Return(1)
+  }
+
+  Method(MMRP)
+  {
+      // Calculate Memory mapped IO address of RR host router PCIE root port
+      // And put it into XXXXX
+
+      Store(\PEMA, Local0)
+      If(LLessEqual(ToInteger(TBRP), 0x08))     // SB PCIE root port
+      {
+          Add(Local0, 0xE0000, Local0) // RP01
+          Subtract(ToInteger(\TBRP), 1, Local1)
+          Multiply(Local1, 0x1000, Local1)
+          Add(Local0, Local1, Local0) //RP0x
+      }
+      Else                          // NB PCIE root port
+      {
+          Add(Local0, 0x8000, Local0) //PEG0
+          Subtract(ToInteger(\TBRP), 0x20, Local1)
+          Multiply(Local1, 0x1000, Local1)
+          Add(Local0, Local1, Local0)
+      }
+      Return(Local0)
+  }
+
+  // Calculate Memory mapped IO address of RR host router upstream port
+  Method(MMTB)
+  {
+      // Calculate Memory mapped IO address of RR host router upstream port
+      // And put it into XXXXX
+
+      Store(MMRP(), Local0)
+      OperationRegion(MMMM, SystemMemory, Local0, 0x1A)
+      Field(MMMM, AnyAcc, NoLock, Preserve)
+      {
+         Offset(0x19),
+         SBUS, 8
+      }
+
+      Store(SBUS, Local2)
+      Store(\PEMA, Local0)
+      Multiply(Local2, 0x100000, Local2)
+      Add(Local0, Local2, Local0)  //TBT HR US port MMIO address
+      Return(Local0)
+  }
+
+  Method(GDRP)
+  {
+    // Put TBT PCIE root port to D0 state
+
+    Store(MMRP(), Local0)
+    OperationRegion(RP_X, SystemMemory, Local0, 0x100)
+    Field(RP_X, AnyAcc, NoLock, Preserve)
+    {
+        Offset(0x84),
+        NBPS, 2,       // Power State of PEG slot
+        Offset(0xA4),
+        PSD3, 2        // Power State of SB PCIE slot
+    }
+    If(LLess(TBRP, 0x20)){
+        Store(0, PSD3)
+        Return (PSD3)
+    }
+    If(LGreaterEqual(TBRP, 0x20)){
+        Store(0, NBPS)
+        Return (NBPS)
+    }
+  }
+
+  Method(RPDX, 1)
+  {
+    // Change TBT PCIE root port Power state via Arg0
+    // Arg0 - 0: D0 Status
+    //        3: D3 Status
+    
+    Store(MMRP(), Local0)
+    OperationRegion(RP_X, SystemMemory, Local0, 0x100)
+    Field(RP_X, AnyAcc, NoLock, Preserve)
+    {
+        Offset(0x84),
+        NBPS, 2,       // Power State of PEG slot
+        Offset(0xA4),
+        PSD3, 2
+    }
+    If(LLess(TBRP, 0x20)){
+        Store(Arg0, PSD3)
+        Sleep(100)
+    }
+    If(LGreaterEqual(TBRP, 0x20)){
+        Store(Arg0, NBPS)
+        Sleep(100)
+    }
+  }
+
+  Method(TBAC)
+  {
+      // Equal Intel BIOS method TSUB and WSUB
+      
+      Acquire(OSUM, 0xFFFF)
+      Store(MMRP(), Local0)
+      OperationRegion(RP_X, SystemMemory, Local0, 0x100)
+      Field(RP_X, AnyAcc, NoLock, Preserve)
+      {
+        Offset(0x08),
+        RDCC, 32,
+        Offset(0x18),
+        PBUS, 8,
+        SBUS, 8,
+        SUBS, 8,
+        Offset(0x84),
+        NBPS, 2,       // Power State of PEG slot
+        Offset(0xA4),
+        PSD3, 2
+      }
+      Store(0, Local1)
+      While(1)
+      {
+        If(LAnd(LNotEqual(RDCC, 0xFFFFFFFF), LNotEqual(SBUS, 0xFF)))
+        {
+            If(LAnd(LLess(TBRP, 0x20), LEqual(PSD3, 0x0))){
+                Break
+            }
+            If(LAnd(LGreaterEqual(TBRP, 0x20), LEqual(PSD3, 0x0))){
+                Break
+            }
+        }
+        Else
+        {
+            Add(Local1, 0x01, Local1)
+            If(LGreater(Local1, 0x03E8))
+            {
+                P8XH(1,0x7B)
+                P8XH(0,0xAC)
+                Sleep(0x3E8)
+                Break
+            }
+            Else
+            {
+                Sleep(0x10)
+            }
+        }
+      }
+      Release(OSUM)
+  }
+
+  Method(NTFY)
+  {
+    // Intel Chipset Sample code Notify Method
+    Sleep(100)
+    Switch(ToInteger(TBRP)) // TBT Selector
+    {
+        Case (1)
+        {
+            Notify(\_SB.PCI0.RP01,0)
+        }
+        Case (2)
+        {
+            Notify(\_SB.PCI0.RP02,0)
+        }
+        Case (3)
+        {
+            Notify(\_SB.PCI0.RP03,0)
+        }
+        Case (4)
+        {
+            Notify(\_SB.PCI0.RP04,0)
+        }
+        Case (5)
+        {
+            Notify(\_SB.PCI0.RP05,0)
+        }
+        Case (6)
+        {
+            Notify(\_SB.PCI0.RP06,0)
+        }
+        Case (7)
+        {
+            Notify(\_SB.PCI0.RP07,0)
+        }
+        Case (8)
+        {
+            Notify(\_SB.PCI0.RP08,0)
+        }
+        Case (0x20)
+        {
+            Notify(\_SB.PCI0.PEG0,0)
+        }
+        Case (0x21)
+        {
+            Notify(\_SB.PCI0.PEG1,0)
+        }
+        Case (0x22)
+        {
+            Notify(\_SB.PCI0.PEG2,0)
+        }
+    }
+  }
+
+  // Check for 0xFFFFFFFF in TBT Vendor/Device ID
+  // And Call OSUP if true
+  Method(TBFF)
+  {
+      // Get mapped IO address of RR host router upstream port
+      Store(MMTB(), Local0) 
+      OperationRegion(PXVD,SystemMemory,Local0,0x4) 
+      Field(PXVD,DWordAcc, NoLock, Preserve)
+      {
+        VEDI, 32 // Vendor/Device ID
+      }    
+      
+	  //Check Vendor/Device ID for 0xFFFFFFFF
+      Store(VEDI, Local1)
+      If(LEqual(Local1, 0xFFFFFFFF))
+      {
+          Return (OSUP(Local0))
+      }
+      Else
+      {
+          Return (0)
+      }
+  } 
+
+  Method(OE1X)
+  {
+    Name(TSNE, 0xFF) //will be updated by setup menu
+    
+    If(LLess(OSYS,2009)) { Return() } // only support win7 or above OS
+
+    Wait(WFEV, 0xFFFF)
+    Signal(WFEV)
+    TBAC()
+    Acquire(OSUM, 0xFFFF)    
+    If(LNotEqual(\TBHR, 0x01))// For Redwood Ridge/Falcon Ridge
+    {
+        Store(TBFF(), Local0)
+        If(LEqual(Local0, 1))// Only HR
+        {
+            Sleep(16)
+            Release(OSUM)
+            Return ()
+        }
+        If(LEqual(Local0, 2)) // Disconnect
+        {
+            If(And(TSNE, 0x02)) // If notification is enabled call Notify
+            {
+                Sleep(16)
+                NTFY()
+            }
+            P8XH(0,0x7D)
+            Release(OSUM)
+            Return ()
+        }
+    }
+
+    If(And(TSNE, 0x01))
+    {
+        Store(TBSW, SSMP)
+    }
+    If(And(TSNE, 0x02))
+    {
+        NTFY()
+    }
+    Sleep(16)
+    Release(OSUM)
+  }
+}
+
+#if defined (ASL_TBT_RMV_REPORT) && (ASL_TBT_RMV_REPORT == 1)
+Scope (ASL_TBT_RP_NUM.PXSX)
+{
+    Method(_RMV)
+    {
+      Return(TBMV)
+    } // end _RMV
+}
+#endif
+
+Scope (ASL_TBT_RP_NUM)
+{
+#if defined ASL_TBT_PCI0_INI_SUPPORT && ASL_TBT_PCI0_INI_SUPPORT == 1
+  Method(TINI,0)
+#else
+  Method(_INI,0)
+#endif
+  {
+      If(LLess(OSYS,2009)) { Return() } // only support win7 or above OS
+
+      If(LAnd(LNotEqual(\TBHR, 0xFF), LNotEqual(\TBHR, 0x01)))// For Redwood Ridge/Falcon Ridge
+      {
+          Acquire(OSUM, 0xFFFF)
+          P8XH(0, 0x51)     // for debug
+/*
+          Store(MMRP(), Local1)
+          OperationRegion(RP_X, SystemMemory, Local1, 0x20)
+          Field(RP_X, DWordAcc, NoLock, Preserve)
+          {
+            REG0, 32,
+            REG1, 32,
+            REG2, 32,
+            REG3, 32,
+            REG4, 32,
+            REG5, 32,
+            REG6, 32,
+            REG7, 32,
+          }
+          Store(REG6, Local2)
+          Store(0x00F0F000, REG6)
+*/
+          \_GPE.TBAC()
+          // Get memory mapped IO address of RR host router upstream port
+          Store(\_GPE.MMTB(), Local3)
+          // Call OSUP
+          \_GPE.OSUP(Local3)
+          Release(OSUM)
+      }
+      Signal(WFEV)
+  }
+
+#if defined(ASL_TBT_WAK_SUPPORT) && (ASL_TBT_WAK_SUPPORT==1)
+  Method(TWAK, 1)
+  {
+      Name(RPL1, 0)
+      Name(RPL6, 0)
+      Name(RPL7, 0)
+      Name(RPL8, 0)
+      Name(RPL9, 0)
+      Name(RPLA, 0)
+      Name(RPLB, 0)
+      
+      If(LLess(OSYS,2009)) { Return() } // only support win7 or above OS
+
+      If(LAnd(LNotEqual(\TBHR, 0xFF), LNotEqual(\TBHR, 0x01)))// Only for Redwood Ridge/Falcon Ridge
+      {
+          Acquire(OSUM, 0xFFFF)
+          \_GPE.TBAC()
+          //Sleep(50)  // fix hang up when S3 resuming
+          // Get memory mapped IO address of RR host router upstream port
+          Store(\_GPE.MMRP(), Local0)
+          OperationRegion(RP_X, SystemMemory, Local0, 0x34)
+          Field(RP_X, DWordAcc, NoLock, Preserve)
+          {
+            REG0, 32,
+            REG1, 32,
+            REG2, 32,
+            REG3, 32,
+            REG4, 32,
+            REG5, 32,
+            REG6, 32,
+            REG7, 32,
+            REG8, 32,
+            REG9, 32,
+            REGA, 32,
+            REGB, 32,
+            REGC, 32,
+          }
+          Store(REG1, RPL1)
+          Store(REG6, RPL6)
+          Store(REG7, RPL7)
+          Store(REG8, RPL8)
+          Store(REG9, RPL9)
+          Store(REGA, RPLA)
+          Store(REGB, RPLB)
+          Store(RPR6, REG6)
+          Store(RPR7, REG7)
+          Store(RPR8, REG8)
+          Store(RPR9, REG9)
+          Store(RPRA, REGA)
+          Store(RPRB, REGB)
+          Store(0x00100007, REG1)
+          Store(\_GPE.GDRP(), Local2)
+          \_GPE.RPDX(Zero)
+          Store(\_GPE.MMTB(), Local3)
+          // Call OSUP
+          \_GPE.OSUP(Local3)
+          // Restore TBT root port resource/bus/cmd/D state registers as before Sx entry
+          Store(TBSW, SSMP)
+          // Restore original register values as before calling SMI
+          Store(RPL1, REG1)
+          Store(RPL6, REG6)
+          Store(RPL7, REG7)
+          Store(RPL8, REG8)
+          Store(RPL9, REG9)
+          Store(RPLA, REGA)
+          Store(RPLB, REGB)
+          \_GPE.RPDX(Local2)
+          Release(OSUM)
+
+          // For TBT host at NB PCIE slot
+          If(LGreaterEqual(ToInteger(TBRP), 0x20))
+          {
+              Switch(ToInteger(TBRP))
+              {
+                  Case (0x20)
+                  {
+                      Notify(\_SB.PCI0.PEG0,0)
+                  }
+                  Case (0x21)
+                  {
+                      Notify(\_SB.PCI0.PEG1,0)
+                  }
+                  Case (0x22)
+                  {
+                      Notify(\_SB.PCI0.PEG2,0)
+                  }
+              }
+          }
+      }
+
+#if defined(ASL_TBT_S3_WAK_SMI) && (ASL_TBT_S3_WAK_SMI == 1) && (ASL_TBT_WAK_SUPPORT == 1)
+      Store(Arg0,Local0)
+      If(LEqual(Local0, 0x03)){
+           If(ASL_TBT_RP_NUM.PDSX){
+              Store(TBSW, SSMP)
+              NTFY()
+           }
+      }
+#endif
+      Signal(WFEV)
+  }
+#endif
+
+#if defined(ASL_TBT_PTS_SUPPORT) && (ASL_TBT_PTS_SUPPORT==1)
+  Method(TPTS, 1)
+  {
+    If(LLess(OSYS,2009)) { Return() } // only support win7 or above OS
+
+    If(LAnd(LNotEqual(\TBHR, 0xFF), LNotEqual(\TBHR, 0x01)))// Only for Redwood Ridge/Falcon Ridge
+    {
+        Acquire(OSUM, 0xFFFF)
+        Store(\_GPE.MMRP(), Local0)
+        OperationRegion(RP_X, SystemMemory, Local0, 0x34)
+        Field(RP_X, DWordAcc, NoLock, Preserve)
+        {
+            REG0, 32,
+            REG1, 32,
+            REG2, 32,
+            REG3, 32,
+            REG4, 32,
+            REG5, 32,
+            REG6, 32,
+            REG7, 32,
+            REG8, 32,
+            REG9, 32,
+            REGA, 32,
+            REGB, 32,
+            REGC, 32,
+        }
+        Store(REG6, RPR6)
+        Store(REG7, RPR7)
+        Store(REG8, RPR8)
+        Store(REG9, RPR9)
+        Store(REGA, RPRA)
+        Store(REGB, RPRB)
+        Release(OSUM)
+    }
+#if defined(ASL_TBT_CLEAR_PME_STATUS) && (ASL_TBT_CLEAR_PME_STATUS == 1)
+    If(LOr(PSPX, PMEP)){
+        Store(PMEX, Local1)
+        Store(0, PMEX)
+        Sleep(10)
+        Store(1, PSPX)
+        Sleep(10)
+        If(PSPX){
+            Store(1, PSPX)
+            Sleep(10)
+        }
+        Store(Local1, PMEX)
+	}
+#endif
+    Reset(WFEV)
+  }
+#endif
+}
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.c b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.c
new file mode 100644
index 0000000..ce78068
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.c
@@ -0,0 +1,415 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.c 7     5/19/14 7:38a Barretlin $
+//
+// $Revision: 7 $
+//
+// $Date: 5/19/14 7:38a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.c $
+// 
+// 7     5/19/14 7:38a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 6     5/19/14 7:15a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Using setup item choose return value of _RMV method in
+// ASL code
+// [Files]  		TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+// 
+// 5     2/18/14 2:12a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Release PCIE root port control when Thunderbolt
+// function disable in run time
+// [Files]  		TbtOemBoard.c
+// 
+// 4     2/10/14 1:26p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	remove useless policy item and setup item
+// [Files]  		TbtOemBoard.h TbtOemBoard.c TbSetup.sdl TbtSetup.sd
+// TbtSetup.uni TbtSmm.c
+// 
+// 3     1/05/14 2:06p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtOemBoard.h TbtOemBoard.c TbtOemLib.c TbtOemLib.h
+// 
+// 2     6/17/13 2:18a Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Improvement
+// [Description]  	add new AIC support setup item and change
+// TBWakeupSupport name
+// [Files]  		TbtOemBoard.h TbtOemBoard.c
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 12    12/12/12 4:14a Barretlin
+// [TAG]  		EIP108272
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+// [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 11    10/28/12 11:50p Barretlin
+// [TAG]  		EIP104870
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files]  		TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+// 
+// 10    10/28/12 11:21p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Create new setup item for thunderbolt POC handling
+// [Files]  		TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl TbtSetup.sd
+// TbtSetup.uni
+// 
+// 9     9/22/12 9:59a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Use token to defien thunderbolt chip pins and update
+// sample code
+// [Files]  		TbtOemBoard.c TbtOemBoard.sdl
+// 
+// 8     8/20/12 5:12a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix IO resource workaround broken in 4C 2port case
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+// 
+// 7     8/17/12 8:44a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add IO resource workaround for Thunderbolt Spec1.1
+// Because new spec has removed IO resource for Thunderbolt device
+// [Files]  		TbtSmm.c TbtOemBoard.h TbtOemBoard.c TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni 
+// 
+// 6     7/31/12 4:07a Barretlin
+// [TAG]  		EIP96350
+// [Category]  	Spec Update
+// [Severity]  	Critical
+// [Description]  	Updated Thunderbolt specification to version 1.00
+// [Files]  		TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 5     7/31/12 3:15a Barretlin
+// [TAG]  		EIP91119
+// [Category]  	Improvement
+// [Description]  	Resolution for enable/disable Thunderbolt device option
+// rom at POST time
+// [Files]  		TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 4     5/22/12 10:00a Barretlin
+// [TAG]  		EIP90650
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.94 - The default value of
+// OPTIONAL workaround for devices that don't support surprise-removal
+// should be disable.
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 3     5/07/12 7:00a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Add three setup items for debug
+// [Files]  		TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+// 
+// 2     2/20/12 12:01a Wesleychen
+//  - Add new policy "SmiNotifyEnabled".
+//  - Move OemProgramTbtSecurityLevel() to TbtDxe.c.
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//*************************************************************************
+#include <Efi.h>
+#include <token.h>
+#include <Setup.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+#include <TbtOemLib.h>
+#include <TbtOemBoard.h>
+
+// GUID Definition(s)
+EFI_GUID  AmiTbtPlatformPpolicyGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+EFI_GUID  TbtHRStatusGuid           = AMI_TBT_HR_STATUS_GUID;
+EFI_GUID  SetupGuid                 = SETUP_GUID;
+
+// Variable Declaration(s)
+AMI_TBT_PLATFORM_POLICY_PROTOCOL  gTbtPlatformPolicy;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtOemBoard_Init
+//
+// Description: This function is the entry point for TbtOemBoard.
+//
+// Input:       ImageHandle - Image handle
+//              SystemTable - Pointer to the system table
+//
+// Output:      Return Status based on errors that occurred while waiting for
+//              time to expire.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtOemBoard_Init (
+  IN EFI_HANDLE       ImageHandle,
+  IN EFI_SYSTEM_TABLE *SystemTable )
+{
+    //
+    // OEM Porting is required.
+    //
+    EFI_STATUS              Status             = EFI_SUCCESS;
+    EFI_HANDLE              Handle             = NULL;
+    UINTN                   VariableSize       = sizeof(SETUP_DATA);
+    UINTN                   HRStatusSize       = sizeof(AMI_TBT_HR_STATUS_DATA);
+    UINT32                  Attributes;
+    UINT16                  counter;
+    UINT8                   TbtSetVariableFlag = 0;
+    CHAR16                  TbtHRStatusVar[]   = TBT_HR_STATUS_VARIABLE;
+    AMI_TBT_HR_STATUS_DATA  HRStatusData;
+    SETUP_DATA              SetupData;
+    
+    InitAmiLib(ImageHandle, SystemTable);
+    
+    //Initial Host Router information
+    Status = pRS->GetVariable( L"TbtHRStatusVar", \
+                               &TbtHRStatusGuid, \
+                               NULL, \
+                               &HRStatusSize, \
+                               &HRStatusData );
+    if (EFI_ERROR(Status)){
+        TRACE((-1, "TbtOemBoard: Can not get Thunderbolt Host Router Information !!! \n"));
+        HRStatusData.TbtHRStatus   = 0;
+        //Get Thunderbolt host Series
+        HRStatusData.TbtHRSeries = GetHRInfo();
+        TRACE((-1, "TbtOemBoard: Thunderbolt Host Router Chip: %x \n", HRStatusData.TbtHRSeries));
+        
+        Status = pRS->SetVariable( TbtHRStatusVar, \
+                                   &TbtHRStatusGuid, \
+                                   EFI_VARIABLE_NON_VOLATILE | \
+                                   EFI_VARIABLE_BOOTSERVICE_ACCESS | \
+                                   EFI_VARIABLE_RUNTIME_ACCESS, \
+                                   HRStatusSize, \
+                                   &HRStatusData );
+        if (!EFI_ERROR(Status))
+            TRACE((-1, "TbtOemBoard: Create Thunderbolt Host Router Information !!! \n"));
+    }
+    
+    Status = pRS->GetVariable( L"Setup", \
+                               &SetupGuid, \
+                               &Attributes, \
+                               &VariableSize, \
+                               &SetupData );
+    ASSERT_EFI_ERROR (Status);
+    
+    Status = pBS->AllocatePool( \
+                  EfiBootServicesData, \
+                  sizeof(AMI_TBT_PLATFORM_POLICY_PROTOCOL), \
+                  (VOID**)&gTbtPlatformPolicy );
+    ASSERT_EFI_ERROR (Status);
+    
+    TRACE((-1, "TbtOemBoard: Start install Thunderbolt Platform Policy !!! \n"));
+    pBS->SetMem( &gTbtPlatformPolicy, sizeof(AMI_TBT_PLATFORM_POLICY_PROTOCOL), 0 );
+    
+    //
+    // OEM Porting required.
+    //
+/* Sample Code
+    gTbtPlatformPolicy.TbtEnable             = SetupData.TbtEnable;
+    gTbtPlatformPolicy.TbtGO2SX              = TBT_GO2SX;
+    gTbtPlatformPolicy.TbtForcePWR           = TBT_ForcePWR;
+    gTbtPlatformPolicy.TbtHotPlugEvt         = TBT_HotPlugEvt;
+    gTbtPlatformPolicy.TbtOK2GO2SX_N         = TBT_OK2GO2SX_N;
+    gTbtPlatformPolicy.CacheLineSize         = SetupData.TbtCacheLineSize;
+    gTbtPlatformPolicy.TbtWakeupSupport      = SetupData.TbtWakeupSupport;
+    gTbtPlatformPolicy.TbtAICSupport         = SetupData.TbtAICSupport;
+    gTbtPlatformPolicy.TbtHandlePOC          = SetupData.TbtHandlePOC;
+    gTbtPlatformPolicy.TbtSecurityLevel      = SetupData.TbtSecurityLevel;
+    gTbtPlatformPolicy.Bus                   = TBT_UP_PORT_BUS;
+    gTbtPlatformPolicy.Dev                   = TBT_UP_PORT_DEV;
+    if (gTbtPlatformPolicy.TbtAICSupport == 1){
+        if (SetupData.TbtHostLocation < 0x20){
+            gTbtPlatformPolicy.Fun           = SetupData.TbtHostLocation;
+        } else {
+            gTbtPlatformPolicy.Dev           = 0x01;
+            gTbtPlatformPolicy.Fun           = (SetupData.TbtHostLocation) - 0x20;
+        }
+    } else {
+        gTbtPlatformPolicy.Fun               = TBT_UP_PORT_FUNC;
+    }
+    gTbtPlatformPolicy.ReserveMemoryPerSlot  = SetupData.ReserveMemoryPerSlot;
+    gTbtPlatformPolicy.ReservePMemoryPerSlot = SetupData.ReservePMemoryPerSlot;
+    gTbtPlatformPolicy.ReserveIOPerSlot      = SetupData.ReserveIOPerSlot;
+    gTbtPlatformPolicy.SmiNotifyEnabled      = SetupData.SmiNotifyEnabled;
+    gTbtPlatformPolicy.SwSmiEnabled          = SetupData.SwSmiEnabled;
+    gTbtPlatformPolicy.NotifyEnabled         = SetupData.NotifyEnabled;
+    gTbtPlatformPolicy.TbtOptionRom          = SetupData.TbtOptionRom;
+    gTbtPlatformPolicy.TbtRmvReturnValue     = SetupData.TbtRmvReturnValue;
+    gTbtPlatformPolicy.TbtIOresourceEnable   = SetupData.TbtIOresourceEnable;
+    gTbtPlatformPolicy.TbtNVMversion         = SetupData.TbtNVMversion;
+
+    Status = pBS->InstallProtocolInterface (
+                            &Handle,
+                            &AmiTbtPlatformPpolicyGuid,
+                            EFI_NATIVE_INTERFACE,
+                            &gTbtPlatformPolicy
+                            );
+    ASSERT_EFI_ERROR (Status);
+//*/
+    //synchronize Thunderbolt Host Router Information with Setup Data
+    if (HRStatusData.TbtHRSeries != SetupData.TbtHRSeries){
+        TRACE((-1, "TbtOemBoard: Setting Thunderbolt Host Router Information into Setup Data!!! \n"));
+        SetupData.TbtHRSeries = HRStatusData.TbtHRSeries;
+        TbtSetVariableFlag |= 1;
+    }
+    
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+    if (gTbtPlatformPolicy.TbtEnable){
+        if (gTbtPlatformPolicy.TbtAICSupport){
+            if ((gTbtPlatformPolicy.Bus == 0) && (gTbtPlatformPolicy.Dev == 0x1C))
+            {   // Thunderbolt AIC is at SB PCIE root port
+                if ((SetupData.PcieMemRsvd[gTbtPlatformPolicy.Fun] != 353) || \
+                    (SetupData.PcieMemRsvd[gTbtPlatformPolicy.Fun] != 737)){
+                    // Change PCIE root port resource to correct location
+                    SetupData.PcieRootPortEn[gTbtPlatformPolicy.Fun]    = 1;
+                    SetupData.PcieRootPortHPE[gTbtPlatformPolicy.Fun]   = 1;
+                    SetupData.ExtraBusRsvd[gTbtPlatformPolicy.Fun]      = TBT_DEFAULT_EXTRA_BUS_RESERVED;
+                    SetupData.PcieMemRsvd[gTbtPlatformPolicy.Fun]       = TBT_DEFAULT_PCIE_MEM_RESERVED;
+                    SetupData.PcieMemRsvdalig[gTbtPlatformPolicy.Fun]   = 26;
+                    SetupData.PciePFMemRsvd[gTbtPlatformPolicy.Fun]     = TBT_DEFAULT_PCIE_PF_MEM_RESERVED;
+                    SetupData.PciePFMemRsvdalig[gTbtPlatformPolicy.Fun] = 28;
+                    SetupData.PcieIoRsvd[gTbtPlatformPolicy.Fun]        = TBT_DEFAULT_PCIE_IO_RESERVED;
+                    
+                    // Double check resource on other PCIE root port is disable
+                    for(counter=0;counter<=7;counter++){
+                        if(counter != gTbtPlatformPolicy.Fun){
+                            if((SetupData.PcieMemRsvd[counter] == 353) || \
+                               (SetupData.PcieMemRsvd[counter] == 737))
+                            {
+                                SetupData.PcieRootPortHPE[counter]      = 0;
+                                SetupData.ExtraBusRsvd[counter]         = 0;
+                                SetupData.PcieMemRsvd[counter]          = 10;
+                                SetupData.PcieMemRsvdalig[counter]      = 1;
+                                SetupData.PciePFMemRsvd[counter]        = 10;
+                                SetupData.PciePFMemRsvdalig[counter]    = 1;
+                                SetupData.PcieIoRsvd[counter]           = 4;
+                            }
+                        } // counter != gTbtPlatformPolicy.Fun
+                    } // for loop
+                    
+                    TbtSetVariableFlag |= 1;
+                } // PCIE root port resource is at incorrect location
+            } else {
+                // Thunderbolt AIC is at NB PCIE root port
+                // Double check resource on other PCIE root port is disable
+                for(counter=0;counter<=7;counter++){
+                    if((SetupData.PcieMemRsvd[counter] == 353) || \
+                       (SetupData.PcieMemRsvd[counter] == 737))
+                    {
+                        SetupData.PcieRootPortHPE[counter]      = 0;
+                        SetupData.ExtraBusRsvd[counter]         = 0;
+                        SetupData.PcieMemRsvd[counter]          = 10;
+                        SetupData.PcieMemRsvdalig[counter]      = 1;
+                        SetupData.PciePFMemRsvd[counter]        = 10;
+                        SetupData.PciePFMemRsvdalig[counter]    = 1;
+                        SetupData.PcieIoRsvd[counter]           = 4;
+
+                        TbtSetVariableFlag |= 1;
+                    }
+                } // for loop
+            }
+        } else {
+            if ((SetupData.PcieMemRsvd[TBT_UP_PORT_FUNC] != 353) || \
+                (SetupData.PcieMemRsvd[TBT_UP_PORT_FUNC] != 737))
+            {
+                SetupData.TbtHostLocation                     = TBT_UP_PORT_FUNC;
+                SetupData.PcieRootPortEn[TBT_UP_PORT_FUNC]    = 1;
+                SetupData.PcieRootPortHPE[TBT_UP_PORT_FUNC]   = 1;
+                SetupData.ExtraBusRsvd[TBT_UP_PORT_FUNC]      = TBT_DEFAULT_EXTRA_BUS_RESERVED;
+                SetupData.PcieMemRsvd[TBT_UP_PORT_FUNC]       = TBT_DEFAULT_PCIE_MEM_RESERVED;
+                SetupData.PcieMemRsvdalig[TBT_UP_PORT_FUNC]   = 26;
+                SetupData.PciePFMemRsvd[TBT_UP_PORT_FUNC]     = TBT_DEFAULT_PCIE_PF_MEM_RESERVED;
+                SetupData.PciePFMemRsvdalig[TBT_UP_PORT_FUNC] = 28;
+                SetupData.PcieIoRsvd[TBT_UP_PORT_FUNC]        = TBT_DEFAULT_PCIE_IO_RESERVED;
+                
+                // Double check resource on other PCIE root port is disable
+                for(counter=0;counter<=7;counter++){
+                    if(counter != TBT_UP_PORT_FUNC){
+                        if((SetupData.PcieMemRsvd[counter] == 353) || (SetupData.PcieMemRsvd[counter] == 737)){
+                            SetupData.PcieRootPortHPE[counter]   = 0;
+                            SetupData.ExtraBusRsvd[counter]      = 0;
+                            SetupData.PcieMemRsvd[counter]       = 10;
+                            SetupData.PcieMemRsvdalig[counter]   = 1;
+                            SetupData.PciePFMemRsvd[counter]     = 10;
+                            SetupData.PciePFMemRsvdalig[counter] = 1;
+                            SetupData.PcieIoRsvd[counter]        = 4;
+                        }
+                    } // counter != TBT_UP_PORT_FUNC
+                } // for loop
+                
+                TbtSetVariableFlag |= 1;
+            } // PCIE root port resource is not at default location
+        } // gTbtPlatformPolicy.TbtAICSupport
+    } // gTbtPlatformPolicy.TbtEnable
+#endif
+
+  if (TbtSetVariableFlag != 0){
+     Status = pRS->SetVariable( L"Setup", &SetupGuid, Attributes, 
+                                VariableSize, &SetupData );
+  }
+
+  return EFI_SUCCESS;
+}
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.cif b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.cif
new file mode 100644
index 0000000..32057d9
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.cif
@@ -0,0 +1,17 @@
+<component>
+	name = "TbtOemBoard"
+	category = ModulePart
+	LocalRoot = "Board\EM\Thunderbolt\TbtOemBoard\"
+	RefName = "TbtOemBoard"
+[files]
+"TbtOemBoard.h"	
+"TbtOemBoard.c"	
+"TbtOemBoard.dxs"	
+"TbtOemBoard.mak"	
+"TbtOemBoard.sdl"	
+"TbtOemLib.c"	
+"TbtOemLib.h"	
+"TbtOemPorting.asl"	
+[parts]
+"TbtSetup"
+<endComponent>
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs
new file mode 100644
index 0000000..4aa8e93
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs
@@ -0,0 +1,48 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs 1     1/10/13 4:57a Barretlin $
+//
+// $Revision: 1 $
+//
+// $Date: 1/10/13 4:57a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.dxs $
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//**********************************************************************
+DEPENDENCY_START
+ TRUE
+DEPENDENCY_END
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.h b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.h
new file mode 100644
index 0000000..c4ce1ac
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.h
@@ -0,0 +1,328 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.h 11    5/19/14 7:15a Barretlin $
+//
+// $Revision: 11 $
+//
+// $Date: 5/19/14 7:15a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.h $
+// 
+// 11    5/19/14 7:15a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Using setup item choose return value of _RMV method in
+// ASL code
+// [Files]  		TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+// 
+// 10    2/18/14 7:29a Barretlin
+// [TAG]  		EIP152401
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	add new Thunderbolt chip series
+// [Files]  		TbtOemBoard.h
+// 
+// 9     2/10/14 1:26p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	remove useless policy item and setup item
+// [Files]  		TbtOemBoard.h TbtOemBoard.c TbSetup.sdl TbtSetup.sd
+// TbtSetup.uni TbtSmm.c
+// 
+// 8     1/05/14 2:06p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtOemBoard.h TbtOemBoard.c TbtOemLib.c TbtOemLib.h
+// 
+// 7     7/26/13 1:53a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error at MahoBay/ChiefRiver platform
+// [Files]  		TbtPei.c TbtOemBoard.h
+// 
+// 6     6/21/13 7:50a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error with non Intel RC project
+// [Files]  		TbtOemBoard.h TbtOemBoard.sdl
+// 
+// 5     6/17/13 2:18a Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Improvement
+// [Description]  	add new AIC support setup item and change
+// TBWakeupSupport name
+// [Files]  		TbtOemBoard.h TbtOemBoard.c
+// 
+// 4     4/24/13 2:40a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add new series
+// [Files]  		TbtOemBoard.h
+// 
+// 3     4/03/13 3:04a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Adding mask definition for reading Redwood Ridge
+// command
+// [Files]  		TbtOemBoard.h
+// 
+// 2     2/06/13 6:33a Barretlin
+// [TAG]  		EIP114556
+// [Category]  	Spec Update
+// [Severity]  	Normal
+// [Description]  	Add more definition for Thunderbolt RR Spec 0.9
+// [Files]  		TbtOemBoard.h
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 15    12/12/12 4:14a Barretlin
+// [TAG]  		EIP108272
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+// [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 14    10/28/12 11:50p Barretlin
+// [TAG]  		EIP104870
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files]  		TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+// 
+// 13    10/28/12 11:21p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Create new setup item for thunderbolt POC handling
+// [Files]  		TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl TbtSetup.sd
+// TbtSetup.uni
+// 
+// 12    10/03/12 9:27p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change Programming security level timing for saving
+// boot time
+// [Files]  		TbtPei.c TbtDxe.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 11    8/20/12 5:12a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix IO resource workaround broken in 4C 2port case
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+// 
+// 10    8/17/12 8:44a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add IO resource workaround for Thunderbolt Spec1.1
+// Because new spec has removed IO resource for Thunderbolt device
+// [Files]  		TbtSmm.c TbtOemBoard.h TbtOemBoard.c TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni 
+// 
+// 9     7/31/12 4:07a Barretlin
+// [TAG]  		EIP96350
+// [Category]  	Spec Update
+// [Severity]  	Critical
+// [Description]  	Updated Thunderbolt specification to version 1.00
+// [Files]  		TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 8     7/31/12 3:15a Barretlin
+// [TAG]  		EIP91119
+// [Category]  	Improvement
+// [Description]  	Resolution for enable/disable Thunderbolt device option
+// rom at POST time
+// [Files]  		TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 7     5/22/12 10:00a Barretlin
+// [TAG]  		EIP90650
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.94 - The default value of
+// OPTIONAL workaround for devices that don't support surprise-removal
+// should be disable.
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 6     5/07/12 7:00a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Add three setup items for debug
+// [Files]  		TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+// 
+// 5     3/05/12 1:16a Barretlin
+// [TAG]  		EIP83266
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.90
+// [Files]  		TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+// 
+// 3     2/20/12 12:57a Wesleychen
+// Add new policy "SmiNotifyEnabled".
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//*************************************************************************
+#ifndef _THUNDERBOLT_OEM_PROTOCOL_
+#define _THUNDERBOLT_OEM_PROTOCOL_
+
+#include <Hob.h>
+
+#define AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0xEB, 0x47, 0x24, 0x01, 0x9B }
+
+#define AMI_TBT_HR_STATUS_GUID { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0x59, 0x87, 0x32, 0xF1, 0x56 }
+
+#define AMI_TBT_HOB_GUID { 0x380D7A5E, 0x1BCA, 0x11E1, 0xA1, 0x10, 0xE8, 0x5A, 0x87, 0x15, 0x15, 0x47 }
+
+#define TBT_HR_STATUS_VARIABLE L"TbtHRStatusVar"
+
+#define RR_PCIE2TBT 0x54C
+
+#define RR_TBT2PCIE 0x548
+
+#define PCIE2TBT_VLD_B 1
+
+#define TBT2PCIE_DON_R 1
+
+#define MASK_DATA (BIT08 | BIT09 | BIT10 | BIT11)
+
+#define MASK_ERROR (BIT12 | BIT13 | BIT14 | BIT15)
+
+#ifdef PCIEX_BASE_ADDRESS 
+#define TBT_CFG_ADDRESS(bus, dev, func, reg) NB_PCIE_CFG_ADDRESS(bus, dev, func, reg)
+#endif
+
+#ifndef R_PCH_RCRB_PM_CFG
+#define R_PCH_RCRB_PM_CFG   0x3318  // Power Management Configuration Register
+#endif
+
+typedef enum {
+    Cactus_Ridge = 1,
+    Redwood_Ridge,
+    Falcon_Ridge,
+    BDW_TBT_LP
+} TBT_HOST_SERIES;
+
+typedef enum {
+    TBT_NORMAL_MODE = 1,
+    TBT_NORMAL_MODE_WO_NHI,
+    TBT_DIRECT_CONNECTED_WO_NHI,
+    TBT_REDRIVER_ONLY,
+    TBT_OFF_MODE,
+    TBT_DEBUG_MODE,
+    TBT_RR_LEGACY_CONNECTION = 0,
+    TBT_RR_UNIQUIE_ID,
+    TBT_RR_ONE_TIME_SAVED_KEY,
+    TBT_RR_DPPLUS
+} TBT_SECURITY_TYPE;
+
+typedef enum {
+    TBT_GO2SX_WITH_WAKE = 2,
+    TBT_GO2SX_NO_WAKE,
+    TBT_SX_EXIT_TBT_CONNECTED,
+    TBT_SX_EXIT_NO_TBT_CONNECTED,
+    TBT_OS_UP,
+    TBT_SET_SECURITY_LEVEL = 8,
+    TBT_GET_SECURITY_LEVEL
+} TBT_RR_COMMOND;
+
+typedef VOID (EFIAPI *TBT_PROGRAM_SEURITY_LVL) (
+  IN TBT_SECURITY_TYPE   SecurityLevel
+ );
+
+typedef struct _AMI_TBT_HR_STATUS_DATA {
+  UINT8                    TbtHRSeries;
+  UINT8                    TbtHRStatus;
+} AMI_TBT_HR_STATUS_DATA;
+
+typedef struct {
+  EFI_HOB_GUID_TYPE        Header;
+  UINT8                    TbtSecurityLevelFlag;
+} TBT_HOB;
+
+typedef struct _AMI_TBT_PLATFORM_POLICY_PROTOCOL {
+  UINT8                    TbtEnable;
+  UINT8                    TbtGO2SX;
+  UINT8                    TbtForcePWR;
+  UINT8                    TbtHotPlugEvt;
+  UINT8                    TbtOK2GO2SX_N;
+  UINT8                    CacheLineSize;
+  UINT8                    TbtWakeupSupport;
+  UINT8                    TbtAICSupport;
+  UINT8                    TbtHandlePOC;
+  UINT8                    TbtSecurityLevel;
+  UINT8                    Bus;
+  UINT8                    Dev;
+  UINT8                    Fun;
+  UINT16                   ReserveMemoryPerSlot;
+  UINT16                   ReservePMemoryPerSlot;
+  UINT8                    ReserveIOPerSlot;
+  UINT8                    SmiNotifyEnabled;
+  UINT8                    SwSmiEnabled;
+  UINT8                    NotifyEnabled;
+  UINT8                    TbtRmvReturnValue;
+  UINT8                    TbtOptionRom;
+  UINT8                    TbtIOresourceEnable;
+  UINT8                    TbtNVMversion;
+} AMI_TBT_PLATFORM_POLICY_PROTOCOL;
+
+#if !defined TBT_INTEL_RC_CONFIG || TBT_INTEL_RC_CONFIG == 0
+#define PCI_DEVICE_NUMBER_PCH_LPC       LPC_DEVICE
+#define PCI_FUNCTION_NUMBER_PCH_LPC     LPC_FUNC
+#define R_PCH_LPC_GPI_ROUT              0xB8
+#define R_PCH_PCIE_CLS                  0x0C
+#define R_PCH_PCIE_SLCTL                0x58
+#define R_PCH_PCIE_SLSTS                0x5A
+#define B_PCH_PCIE_SLSTS_PDS            BIT06
+#define R_PCH_PCIE_PMCS                 0xA4
+#define B_PCH_PCIE_PMCS_PS              (BIT00 | BIT01)
+#endif // TBT_INTEL_RC_CONFIG == 0
+
+#endif // _THUNDERBOLT_OEM_PROTOCOL_
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.mak b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.mak
new file mode 100644
index 0000000..f9d42e5
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.mak
@@ -0,0 +1,95 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.mak 1     1/10/13 4:57a Barretlin $
+#
+# $Revision: 1 $
+#
+# $Date: 1/10/13 4:57a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.mak $
+# 
+# 1     1/10/13 4:57a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 2     2/19/12 11:57p Wesleychen
+# [TAG]         None
+# [Category]    Improvement
+# [Description] Add TbtOemLib.
+# [Files]       TbtOemLib.c; TbtOemLib.h; TbtOemBoard,mak;
+#               TbtOemBoard.cif.
+# 
+# 1     12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+# 
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name:	TbtOemBoard.mak
+#
+# Description:	
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+All : TbtOemBoard
+
+TbtOemBoard : $(BUILD_DIR)\TbtOemBoard.mak TbtOemBoardBin
+
+$(BUILD_DIR)\TbtOemBoard.mak : $(TbtOemBoard_DIR)\$(@B).cif $(TbtOemBoard_DIR)\$(@B).mak $(BUILD_RULES)
+  $(CIF2MAK) $(TbtOemBoard_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+TbtOemBoardBin : $(AMICSPLib) $(AMIDXELIB)
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+    /f $(BUILD_DIR)\TbtOemBoard.mak all\
+    GUID=B4DE05C0-1BD0-11E1-8F0E-77F34724019B\
+    ENTRY_POINT=TbtOemBoard_Init \
+    "MY_INCLUDES=$(TBT_OEMBOARD_INCLUDES)"\
+    TYPE=BS_DRIVER\
+    DEPEX1=$(TbtOemBoard_DIR)\TbtOemBoard.dxs\
+    DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\
+    COMPRESS=1
+
+#----------------------------------------------------------------------------
+#           Add files into CSP Library
+#----------------------------------------------------------------------------
+AMI_CSP_LIB_LIBRARY_PATH = $(AMI_CSP_LIB_LIBRARY_PATH);$(TbtOemBoard_DIR)
+
+AMI_CSP_LIB_INCLUDE_FILES = "$(TbtOemBoard_DIR)\TbtOemLib.h" + \
+"$(TbtOemBoard_DIR)\TbtOemBoard.h" + \
+$(AMI_CSP_LIB_INCLUDE_FILES)
+
+AMI_CSP_LIB_OBJS = $(AMI_CSP_LIB_OBJS) \
+$(BUILD_DIR)\TbtOemLib.obj \
+
+{$(TbtOemBoard_DIR)}.c{$(BUILD_DIR)}.obj::
+    $(CC) $(CFLAGS) /I $(TbtDxe_DIR) /Fo$(BUILD_DIR)\ $<
+
+$(BUILD_DIR)\TbtOemLib.obj : $(TbtOemBoard_DIR)\TbtOemLib.c
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl
new file mode 100644
index 0000000..e8a79a6
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl
@@ -0,0 +1,495 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl 9     2/18/14 6:11a Barretlin $
+#
+# $Revision: 9 $
+#
+# $Date: 2/18/14 6:11a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemBoard.sdl $
+# 
+# 9     2/18/14 6:11a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Add new Thunderbolt chip
+# [Files]  		TbtOemBoard.sdl
+# 
+# 8     1/03/14 5:41a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Change default Thunderbolt host chip to Falcon Ridge
+# [Files]  		TbtOemBoard.sdl
+# 
+# 7     6/21/13 7:50a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Fix build error with non Intel RC project
+# [Files]  		TbtOemBoard.h TbtOemBoard.sdl
+# 
+# 6     4/24/13 2:39a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Using token to decide execute Sx_Exit command of RR
+# chip in S5 boot path
+# [Files]  		TbtPei.c TbtOemBoard.sdl
+# 
+# 5     4/12/13 1:48p Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Use token decide default thunderbolt Chip
+# [Files]  		TbtOemBoard.sdl TbtOemLib.c
+# 
+# 4     4/12/13 5:02a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Change token default value
+# [Files]  		TbtOemBoard.sdl
+# 
+# 3     3/21/13 7:00a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Clone Token
+# [Files]  		TbtOemBoard.sdl
+# 
+# 2     1/10/13 5:13a Barretlin
+# 
+# 1     1/10/13 4:57a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 15    12/12/12 4:14a Barretlin
+# [TAG]  		EIP108272
+# [Category]  	Spec Update
+# [Severity]  	Important
+# [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+# [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+# TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+# 
+# 14    10/28/12 11:50p Barretlin
+# [TAG]  		EIP104870
+# [Category]  	Spec Update
+# [Severity]  	Important
+# [Description]  	Change wake up flow for Spec 1.2 and Spec 1.3
+# [Files]  		TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+# TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+# 
+# 13    10/28/12 10:35p Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Use token to decide to skip thunderbolt device initial
+# or not before PCI bus assigning resource
+# [Files]  		TbtDxeLib.c TbtOemBoard.sdl
+# 
+# 12    10/04/12 5:43p Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Update Setup item
+# [Files]  		TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+# 
+# 11    9/22/12 9:59a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Use token to defien thunderbolt chip pins and update
+# sample code
+# [Files]  		TbtOemBoard.c TbtOemBoard.sdl
+# 
+# 10    8/30/12 4:50a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Add new tokens which related resource for 2C and 4C
+# case
+# [Files]  		TbtOemBoard.sdl
+# 
+# 9     8/20/12 5:07a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Change default value of resources in 4C 2 port case
+# [Files]  		TbtOemBoard.sdl
+# 
+# 8     8/17/12 8:35a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	add new resource token for thunderbolt 4C chip and
+# creat "TBT_FCTP" token to switch max size
+# [Files]  		TbtOemBoard.sdl
+# 
+# 7     7/31/12 4:07a Barretlin
+# [TAG]  		EIP96350
+# [Category]  	Spec Update
+# [Severity]  	Critical
+# [Description]  	Updated Thunderbolt specification to version 1.00
+# [Files]  		TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+# TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+# 
+# 6     7/31/12 3:15a Barretlin
+# [TAG]  		EIP91119
+# [Category]  	Improvement
+# [Description]  	Resolution for enable/disable Thunderbolt device option
+# rom at POST time
+# [Files]  		TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+# TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+# 
+# 5     7/06/12 5:56a Barretlin
+# 
+# 4     5/24/12 9:54p Barretlin
+# [TAG]  		None
+# [Category]  	Improvement
+# [Description]  	Add resource token, it needs the co-ordination of the
+# chipset
+# [Files]  		TbtOemBoard.sdl
+# 
+# 3     5/21/12 2:27a Barretlin
+# [TAG]  		EIP90003
+# [Category]  	Improvement
+# [Description]  	If TBT devices with option rom enabled, system maybe
+# cannot boot to OS.
+# [Files]  		TbtDxe.c TbtSmm.c TbtOemBoard.sdl
+# 
+# 2     4/16/12 10:23a Barretlin
+# [TAG]  		None 
+# [Category]  	Improvement
+# [Description]  	Improve ASL code, which redefines device name and RMV
+# method at same address when project supports RMV method,
+# that mightcause conflict
+# [Files]  		TbtDxe.c  TbtGpe.asl  TbtOemBoard.sdl
+# 
+# 1     12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+# 
+#*************************************************************************
+TOKEN
+	Name  = "TbtOemBoard_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable TbtOemBoard support in Project"
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_CHIP"
+	Value  = "3"
+	Help  = "1: Cactus Ridge/2: Redwood Ridge/3: Falcon Ridge/4: Win Ridge."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_UP_PORT_BUS"
+	Value  = "0x00"
+	Help  = "Thunderbolt Host Router Upstream Port Bus Number."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_UP_PORT_DEV"
+	Value  = "0x1C"
+	Help  = "Thunderbolt Host Router Upstream Port Device Number."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_UP_PORT_FUNC"
+	Value  = "0x00"
+	Help  = "Thunderbolt Host Router Upstream Port Function Number."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_GO2SX"
+	Value  = "20"
+	Help  = "Thunderbolt Host Router GO2SX Pin Number, Only for Cactus Ridge chip host."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_ForcePWR"
+	Value  = "21"
+	Help  = "Thunderbolt Host Router ForcePWR Pin Number."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_OK2GO2SX_N"
+	Value  = "22"
+	Help  = "Thunderbolt Host Router OK2GO2SX_N Pin Number, Only for Cactus Ridge chip host."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_HR_PWR"
+	Value  = "0xFF"
+	Help  = "Thunderbolt Host Router Power Pin Number, Only for Cactus Ridge chip."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_HotPlugEvt"
+	Value  = "11"
+	Help  = "Thunderbolt Host Router HotPlugEvt Pin Number."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_FCTP"
+	Value  = "0"
+	Help  = "Thunderbolt Host Router is 4 CIO and 2 phyical Thunderbolt port on board."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_PCIBUS_SKIP"
+	Value  = "1"
+	Help  = "Allow PCI bus skip thunderbolt device initial"
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_RR_S5_SXEXIT"
+	Value  = "0"
+	Help  = "Enable/Disable execute Sx_Exit command of RR chip in S5 boot path."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "====== Thunderbolt Resource Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "PCIEX_BASE_ADDRESS"
+	Value  = "0xF0000000"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+TOKEN
+	Name  = "PCIEX_BASE_ADDRESS"
+	Value  = "0xE0000000"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	TOKEN = "TBT_FCTP" "=" "1"
+	TOKEN = "TBT_INTEL_RC_CONFIG" "=" "1"
+End
+
+TOKEN
+	Name  = "MAX_ADDITIONAL_P2P_BRIDGES"
+	Value  = "0x80"
+	Help  = "The number of P2P bridges that can be processed in addition to the ones defined in BusNumXlat.INC."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "1...0FFh"
+	TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+	Name  = "COMBINE_MEM_PMEM"
+	Value  = "0"
+	Help  = "Tells if Chipset correctly supports PF MMIO\if set PF MMIO will be decoded through the same resource\window as NONE PF MMIO. PF MEM BASE and PF MEM LIMIT register pare will not be used."
+	TokenType = Boolean
+	TargetH = Yes
+	Range  = "ON or OFF. Default is OFF!"
+End
+
+TOKEN
+	Name = "TBT_PCH_PCIE_TEMP_RP_BUS_NUM_MAX"
+	Value = "255"                     # (PPTRC060.8)
+	Help = "Temp Root Port Bus Number Max for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "TBT_MAX_EXTRA_BUS_RESERVED"
+	Value = "63"
+	Help = "The Max number of extra Bus Reserved for bridges behind this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "TBT_MAX_EXTRA_BUS_RESERVED"
+	Value = "245"
+	Help = "The Max number of extra Bus Reserved for bridges behind this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+    TOKEN = "TBT_FCTP" "=" "1"
+    Token = "PCIEX_BASE_ADDRESS" "!=" "0xF8000000"
+End
+
+TOKEN
+	Name = "TBT_DEFAULT_EXTRA_BUS_RESERVED"
+	Value = "56"
+	Help = "The Default number of extra Bus Reserved for bridges behind this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "TBT_DEFAULT_EXTRA_BUS_RESERVED"
+	Value = "106"
+	Help = "The Default number of extra Bus Reserved for bridges behind this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+    TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+	Name = "TBT_MAX_PCIE_MEM_RESERVED"
+	Value = "640"
+	Help = "The Max number of reserved memory range for this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "TBT_MAX_PCIE_MEM_RESERVED"
+	Value = "1200"
+	Help = "The Max number of reserved memory range for this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+    TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+	Name = "TBT_DEFAULT_PCIE_MEM_RESERVED"
+	Value = "353"
+	Help = "The Default number of reserved memory range for this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "TBT_DEFAULT_PCIE_MEM_RESERVED"
+	Value = "737"
+	Help = "The Default number of reserved memory range for this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+    TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+	Name = "TBT_MAX_PCIE_PF_MEM_RESERVED"
+	Value = "640"
+	Help = "The Max number of prefetchable memory range for this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "TBT_MAX_PCIE_PF_MEM_RESERVED"
+	Value = "1200"
+	Help = "The Max number of prefetchable memory range for this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+    TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+	Name = "TBT_DEFAULT_PCIE_PF_MEM_RESERVED"
+	Value = "544"
+	Help = "The Default number of prefetchable memory range for this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "TBT_DEFAULT_PCIE_PF_MEM_RESERVED"
+	Value = "1184"
+	Help = "The Default number of prefetchable memory range for this Root Bridge for Thunderbolt."
+	TokenType = Integer
+	TargetH = Yes
+    TOKEN = "TBT_FCTP" "=" "1"
+End
+
+TOKEN
+	Name = "TBT_MAX_PCIE_IO_RESERVED"
+	Value = "48"
+	Help = "The Max number of IO range for this Root Bridge."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "TBT_DEFAULT_PCIE_IO_RESERVED"
+	Value = "0"
+	Help = "The Default number of IO range for this Root Bridge."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+MODULE
+	Help  = "Includes TbtOemBoard.mak to Project"
+	File  = "TbtOemBoard.mak"
+End
+
+PATH
+	Name  = "TbtOemBoard_DIR"
+End
+
+ELINK
+	Name  = "/D TBT_UP_PORT_FUNC_FLAG"
+	Parent  = "GLOBAL_DEFINES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "TBT_OEMBOARD_INCLUDES"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "/I$(TbtOemBoard_DIR)"
+	Parent  = "TBT_OEMBOARD_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\TbtOemBoard.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.c b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.c
new file mode 100644
index 0000000..9e27a42
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.c
@@ -0,0 +1,1298 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemLib.c 13    5/19/14 7:38a Barretlin $
+//
+// $Revision: 13 $
+//
+// $Date: 5/19/14 7:38a $
+//*************************************************************************
+// ReviGpion History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemLib.c $
+// 
+// 13    5/19/14 7:38a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 12    2/18/14 12:16p Barretlin
+// [TAG]  		EIP152401
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	add new Thunderbolt chip series
+// [Files]  		TbtOemLib.c
+// 
+// 11    1/05/14 2:06p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtOemBoard.h TbtOemBoard.c TbtOemLib.c TbtOemLib.h
+// 
+// 10    5/27/13 8:11a Barretlin
+// [TAG]  		EIP124914
+// [Category]  	New Feature
+// [Description]  	Support Falcon Ridge chip
+// [Files]  		TbtOemLib.c
+// 
+// 9     4/12/13 1:48p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Use token decide default thunderbolt Chip
+// [Files]  		TbtOemBoard.sdl TbtOemLib.c
+// 
+// 8     4/12/13 1:30p Barretlin
+// 
+// 7     4/10/13 2:57p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add new sample code for CRB
+// [Files]  		TbtOemLib.c
+// 
+// 6     4/03/13 2:47a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Double check Security Level between Thunderbolt host FW
+// and BIOS are same or not for Redwood Ridge chip when entering setup
+// page.
+// [Files]  		TbtOemLib.c TbtOemLib.h TbtSetupReset.c
+// 
+// 5     3/21/13 6:48a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Update sample code to fix FW's security level doesn't
+// match BIOS configuration.
+// [Files]  		TbtOemLib.c
+// 
+// 4     2/08/13 2:05a Barretlin
+// 
+// 3     2/06/13 6:45a Barretlin
+// [TAG]  		EIP114556
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Update RR handshake flow and sample code for
+// Thunderbolt RR Spec 0.9
+// [Files]  		TbtOemLib.c
+// 
+// 2     1/27/13 4:36a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change sample code avoiding side effect
+// [Files]  		TbtOemLib.c
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 12    12/13/12 4:06a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error
+// [Files]  		TbtOemLib.c
+// 
+// 11    12/12/12 4:14a Barretlin
+// [TAG]  		EIP108272
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+// [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 10    10/28/12 11:50p Barretlin
+// [TAG]  		EIP104870
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files]  		TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+// 
+// 9     10/04/12 10:42p Barretlin
+// [TAG]  		EIP102947
+// [Category]  	Spec Update
+// [Severity]  	Normal
+// [Description]  	Update Thunderbolt Spec to Rev 1.2
+// [Files]  		TbtPei.c TbtOemLib.c TbtOemLib.h
+// 
+// 8     10/03/12 9:27p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change Programming security level timing for saving
+// boot time
+// [Files]  		TbtPei.c TbtDxe.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 7     5/21/12 2:56a Barretlin
+// [TAG]  		EIP90334
+// [Category]  	Improvement
+// [Description]  	Implement security level function on CRB
+// [Files]  		TbtOemLib.c
+// 
+// 6     4/14/12 4:58a Barretlin
+// 
+// 5     3/05/12 1:16a Barretlin
+// [TAG]  		EIP83266
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.90
+// [Files]  		TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+// 
+// 3     2/20/12 4:50a Wesleychen
+// [TAG]         None
+// [Category]    Improvement
+// [Description] Add TbtOemLib.
+// [Files]       TbtOemLib.c; TbtOemLib.h; TbtOemBoard,mak;
+//               TbtOemBoard.cif.
+// 
+//*************************************************************************
+#include <Efi.h>
+#include <token.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+// Sample code for ITE8728F
+/*
+VOID SetSioLdn( IN UINT8 Ldn)
+{
+    IoWrite8(0x2e, Ldn);
+    IoWrite8(0x2f, Ldn);
+}
+
+UINT8 ReadSio( IN UINT8 Index )
+{
+    IoWrite8(0x2e, Index);
+    return IoRead8(0x2f);
+}
+
+VOID WriteSio( IN UINT8 Index, IN UINT8 Value )
+{
+    IoWrite8(0x2e, Index);
+    IoWrite8(0x2f, Value);
+}
+
+VOID SetSio( IN UINT8 Index, IN UINT8 Set )
+{
+    UINT8 Data8;
+
+    IoWrite8(0x2e, Index);
+    Data8 = IoRead8(0x2f);
+    Data8 |= Set;
+    IoWrite8(0x2f, Data8);
+}
+
+VOID ResetSio( IN UINT8 Index, IN UINT8 Rst )
+{
+    UINT8 Data8;
+
+    IoWrite8(0x2e, Index);
+    Data8 = IoRead8(0x2f);
+    Data8 &= ~Rst;
+    IoWrite8(0x2f, Data8);
+}
+
+VOID OpenSioConfig ( VOID ) 
+{
+    IoWrite8(0x2e, 0x87);
+    IoWrite8(0x2e, 0x01);
+    IoWrite8(0x2e, 0x55);
+    IoWrite8(0x2e, 0x55);
+}
+//*/
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtSetPCIe2TBTCommand
+//
+// Description: This snipped code contains PCIE2TBT <-> TBT2PCIE handshake 
+//              procedure and all related methods called directly or underectly 
+//              by TbtSetPCIe2TBTCommand.
+//              This function is Intel Sample code(Rev. 1.5).
+//
+// Input:       UINT8 - UpPortBus
+//              UINT8 - Data
+//              UINT8 - Command
+//              UINTN - Timeout
+//
+// Output:      BOOLEAN
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN TbtSetPCIe2TBTCommand(
+    IN UINT8             UpPortBus,
+    IN UINT8             Data,
+    IN UINT8             Command,
+    IN UINTN             Timeout
+)
+{
+    UINT32 REG_VAL = 0;
+    UINTN  Counter = Timeout;
+    
+    REG_VAL = (Data << 8) | (Command << 1) | PCIE2TBT_VLD_B;
+    
+    WRITE_PCI32(UpPortBus, 0, 0, RR_PCIE2TBT, REG_VAL);
+    
+    while(Counter-- > 0){
+        // BIOS support of Thunderbolt devices Specification Update Revision 0.9
+        // Check Classcode, RevID
+        REG_VAL = MMIO_READ32(TBT_CFG_ADDRESS(UpPortBus, 0, 0, PCI_RID));
+        if (0xFFFFFFFF == REG_VAL){
+            // Device is not here return now
+            return FALSE;
+        }
+    
+        // Check TBT2PCIE.Done
+        REG_VAL = MMIO_READ32(TBT_CFG_ADDRESS(UpPortBus, 0, 0, RR_TBT2PCIE));
+        if (REG_VAL & TBT2PCIE_DON_R){
+            break;
+        }
+    }
+    WRITE_PCI32(UpPortBus, 0, 0, RR_PCIE2TBT, 0);
+    
+    return TRUE;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtBeforeSxExitFlow
+//
+// Description: 
+//              
+//
+// Input:       EFI_PEI_SERVICES - **PeiServices
+//              UINT8            - TbtHostSeries
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID TbtBeforeSxExitFlow(
+    IN VOID              *Services,
+    IN UINT8             TbtHostSeries )
+{
+// Sample code for CRB
+/*
+    EFI_PEI_SERVICES    **PeiServices;
+    UINT16      GPIOInv;
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8       Data8;
+#else
+    UINT32      Data32;
+#endif
+
+    PeiServices = (EFI_PEI_SERVICES **)Services;
+
+    if (TbtHostSeries == Cactus_Ridge){
+        // only for SharkBay CRB
+        GPIOInv = (IoRead16(GPIO_BASE_ADDRESS + GP_IOREG_GPI_INV) & 0xF7FF);
+        IoWrite16(GPIO_BASE_ADDRESS + GP_IOREG_GPI_INV, GPIOInv);
+    }
+
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    OpenSioConfig();
+    SetSioLdn (0x07);
+    
+    //program Super IO Base Address
+    WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+    WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+
+    //program GP20, GP21, GP22 as GPIO pin
+    Data8 = ReadSio (0x26);
+    Data8 |= 0x07;
+    WriteSio (0x26, Data8);
+    
+    if (TbtHostSeries == Cactus_Ridge){
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+        //program GP40 as GPIO pin
+        Data8 = ReadSio (0x28);
+        Data8 |= 0x01;
+        WriteSio (0x28, Data8);
+#endif
+        
+        //program GP66, GP67 as GPIO pin
+        Data8 = ReadSio (0x29);
+        Data8 |= BIT07;
+        WriteSio (0x29, Data8);
+    } // Cactus Ridge
+    
+    //program GP20, GP21, GP22 GPIO polarity
+    Data8 = ReadSio (0xB1);
+    Data8 &= 0xF8;
+    WriteSio (0xB1, Data8);
+    
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+    if (TbtHostSeries == Cactus_Ridge){
+        //program GP40 GPIO polarity
+        Data8 = ReadSio (0xB3);
+        Data8 &= 0xFE;
+        WriteSio (0xB3, Data8);
+    }
+#endif
+    
+    //GP20, GP21, GP22 internal pull-up enable
+    Data8 = ReadSio (0xB9);
+    Data8 |= 0x03;
+    WriteSio (0xB9, Data8);
+    
+    if (TbtHostSeries == Cactus_Ridge){
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+        //GP40 internal internal pull-up enable
+        Data8 = ReadSio (0xBB);
+        Data8 |= 0x01;
+        WriteSio (0xBB, Data8);
+#endif
+     
+        //GP66, GP67 internal pull-up enable
+        Data8 = ReadSio (0xBD);
+        Data8 |= 0xC0;
+        WriteSio (0xBD, Data8);
+    }
+    
+    //GP20, GP21, GP22 Simple I/O enable
+    Data8 = ReadSio (0xC1);
+    Data8 |= 0x07;
+    WriteSio (0xC1, Data8);
+     
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+    if (TbtHostSeries == Cactus_Ridge){
+        //GP40 Simple I/O enable
+        Data8 = ReadSio (0xC3);
+        Data8 |= 0x01;
+        WriteSio (0xC3, Data8);
+    }
+#endif
+     
+    //GP20, GP21, GP22 Input/Output Configure
+    //1:Output Mode 0:Input Mode
+    Data8 = ReadSio (0xC9);
+    Data8 |= 0x03;
+    WriteSio (0xC9, Data8);
+    
+    if (TbtHostSeries == Cactus_Ridge){
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+        //GP40 Input/Output Configure
+        //1:Output Mode 0:Input Mode
+        Data8 = ReadSio (0xCB);
+        Data8 |= 0x01;
+        WriteSio (0xCB, Data8);
+#endif
+        
+        //GP66, GP67 Input/Output Configure
+        //1:Output Mode 0:Input Mode
+        Data8 = ReadSio (0xCD);
+        Data8 |= 0xC0;
+        WriteSio (0xCD, Data8);
+    }
+    
+    if (TbtHostSeries != Cactus_Ridge){
+        //Pull high GPIO_9
+        IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, 0x04);
+    } // RR, FR and WR
+#else
+    // program ownship
+    //Data32 = IoRead32(GPIO_BASE_ADDRESS + (TBT_HotPlugEvt/32)*4);
+    //Data32 |= (BIT00 << (TBT_ForcePWR%32));
+    //IoWrite32((GPIO_BASE_ADDRESS + (TBT_HotPlugEvt/32)*4), Data32);
+    
+    //Data32 = IoRead32(GPIO_BASE_ADDRESS + (TBT_HotPlugEvt/32)*4);
+    //Data32 &= ~(BIT00 << (TBT_HotPlugEvt%32));
+    //IoWrite32((GPIO_BASE_ADDRESS + (TBT_HotPlugEvt/32)*4), Data32);
+    
+    // program GPIO pin setting
+    // TBT_ForcePWR is GPIO, is Output, is Level mode
+    //Data32 = (BIT00 | BIT04) & (~BIT02);
+    //IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+    
+    // TBT_HotPlugEvt is GPIO, is input, need invert, is Edge mode
+    //Data32 = (BIT00 | BIT02 | BIT03) & (~BIT04);
+    //IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_HotPlugEvt * 8)), Data32);
+#endif
+//*/
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   GetHRInfo
+//
+// Description: Pull High GPIO_3 and assign temp bus to get Thunderbolt Host
+//              Chip Series for distinguishing Thunderbolt host is Cactus Ridge 
+//              or Redwood Ridge
+//
+//              If your case is only support Redwood Ridge or only support Cactus
+//              Ridge, you can just return Thunderbolt Host number which is defined
+//              in TbtOemBoard.h
+//
+//              According test result, the dynamic detect Thunderbolt HR series
+//              still has fail rate, so we don't suggest you using the same way
+//              to decide HR series. sample code is just for testing !!!
+//
+// Input:       None
+//
+// Output:      UINT8 - Thunderbolt Host chip Series
+//                      1 - Cactus Ridge
+//                      2 - Redwood Ridge
+//                      3 - Falcon Ridge
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8 GetHRInfo( VOID )
+{
+    UINT8        TBTHostSeries = DEFAULT_TBT_CHIP;
+// Sample code for ITE8728F and WTM2
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8        Data8;
+#else
+    UINT32       Data32;
+#endif
+    UINT16       HRID;
+    UINT32       REG_VAL = 0;
+    BOOLEAN      RRCmd = FALSE;
+
+#if !defined BWT2_BOARD || BWT2_BOARD == 0  
+    OpenSioConfig();
+    
+    SetSioLdn(0x07);
+    
+    if(ReadSio (0x62) == 0x00){
+        //program Super IO Base Address
+        WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+        WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+    }
+    
+    //program GP21 as GPIO pin
+    Data8 = ReadSio (0x26);
+    Data8 |= 0x02;
+    WriteSio (0x26, Data8);
+    
+    //program GP21 GPIO polarity
+    Data8 = ReadSio (0xB1);
+    Data8 &= 0xFD;
+    WriteSio (0xB1, Data8);
+    
+    //program GP21 internal pull-up enable
+    Data8 = ReadSio (0xB9);
+    Data8 |= 0x02;
+    WriteSio (0xB9, Data8);
+    
+    //program GP21 Simple I/O enable
+    Data8 = ReadSio (0xC1);
+    Data8 |= 0x02;
+    WriteSio (0xC1, Data8);
+    
+    //program GP21 Input/Output Configure
+    //1:Output Mode 0:Input Mode
+    Data8 = ReadSio (0xC9);
+    Data8 |= 0x02;
+    WriteSio (0xC9, Data8);
+#else
+#endif
+    
+    // Assign temp bus
+    WRITE_PCI16(TBT_UP_PORT_BUS, TBT_UP_PORT_DEV, TBT_UP_PORT_FUNC, PCI_PBUS+1, 0x0505);
+    // Do a dummy Write
+    WRITE_PCI32(5, 0, 0, PCI_VID, 0x12345678);
+    
+    // Pull High GPIO_3(__FORCE_PWR)
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+    Data8 |= 0x02;
+    IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+    Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+    Data32 |= BIT31;
+    IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+
+    // Delay 100 ms
+    CountTime(100000, PM_BASE_ADDRESS);
+    
+    //Write OS_UP commond for RR chip
+    TbtSetPCIe2TBTCommand(5, 0, TBT_OS_UP, 0x8FFFF);
+    
+    // Delay 600 ms
+    CountTime(600000, PM_BASE_ADDRESS);
+    
+    // Get HR Info
+    HRID = READ_PCI16(5, 0, 0, PCI_DID);
+    switch (HRID){
+        case 0x1547: // Cactus Ridge 4C
+        case 0x1548: // Cactus Ridge 2C
+            TBTHostSeries = Cactus_Ridge;
+            break;
+        
+        case 0x1567: // Redwood Ridge 2C
+        case 0x1569: // Redwood Ridge 4C
+        case 0x156B: // Falcon Ridge 2C
+        case 0x156D: // Falcon Ridge 4C
+        case 0x157E: // BDW-TBT-LP(WR)
+        default:
+            if ((HRID == 0x1567) || (HRID == 0x1569)){
+                TBTHostSeries = Redwood_Ridge;
+            } else if ((HRID == 0x156B) || (HRID == 0x156D)){
+                TBTHostSeries = Falcon_Ridge;
+            } else {
+                TBTHostSeries = BDW_TBT_LP;
+            }
+            
+            // Reset FW's security level for RR chip, only for FW rev.26 or above.
+            TbtSetPCIe2TBTCommand(5, 0, TBT_SET_SECURITY_LEVEL, 0x8FFFF);
+            // Delay 100 ms
+            CountTime(100000, PM_BASE_ADDRESS);
+    } // end switch
+
+    // Pull Low GPIO_3(__FORCE_PWR)
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+    Data8 &= 0xFD;
+    IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+    Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+    Data32 &= ~BIT31;
+    IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+    
+    // Delay 100 ms
+    CountTime(100000, PM_BASE_ADDRESS);
+    
+    // Remove temp bus
+    WRITE_PCI32(TBT_UP_PORT_BUS, TBT_UP_PORT_DEV, TBT_UP_PORT_FUNC, PCI_PBUS, 0xFF000000);
+//*/
+    return TBTHostSeries;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   SynchSecurityLevel
+//
+// Description: When entering Setup page, double check Security Level setting  
+//              is same or not between Thunderbolt host Fw and BIOS.
+//
+//              This function only work for Thunderbolt Redwood Ridge chip
+//
+// Input:       UINT8           BiosSecurityLevel
+//              UINT8           TbtHostLocation
+//
+// Output:      UINT8           0 - Security Level synchnized without change
+//                              1 - Security Level synchnized with programming
+//                                  again
+//                              2 - Error
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8 SynchSecurityLevel(
+    IN UINT8             BiosSecurityLevel,
+    IN UINT8             TbtHostLocation
+)
+{
+    UINT8            SynchState = 0;
+// Sample code for ITE8728F and WTM2
+/*
+    UINT8            TbtHRbus;
+    UINT8            PWRFlag = 0;
+    UINT8            TBus = TBT_UP_PORT_BUS;
+    UINT8            TDev = TBT_UP_PORT_DEV;
+    UINT8            TFun = TBT_UP_PORT_FUNC;
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8            Data8;
+#else
+    UINT32           Data32;
+#endif
+    UINT32           RegVal;
+    BOOLEAN          CmdDone;
+
+    if (TbtHostLocation < 0x20){
+        TFun = TbtHostLocation;
+    } else {
+        TDev = 0x01;
+        TFun = TbtHostLocation - 0x20;
+    }
+
+    // Get Thunderbolt Host Router Location
+    TbtHRbus = READ_PCI8(TBus, TDev, TFun, PCI_SBUS);
+
+    // Check Thunderbolt Host state
+    RegVal = MMIO_READ32(TBT_CFG_ADDRESS(TbtHRbus, 0, 0, PCI_RID));
+    if (RegVal == 0xFFFFFFFF){
+        // Pull high GPIO_3(__FORCE_PWR) pin
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+        Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+        Data8 |= 0x02;
+        IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+        Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+        Data32 |= BIT31;
+        IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+    
+        // Delay 50ms
+        CountTime(50000, PM_BASE_ADDRESS);
+        PWRFlag = 1;
+    }
+    
+    // Do Redwood Ridge handshake to get Thunderbolt FW security level 
+    CmdDone = TbtSetPCIe2TBTCommand(TbtHRbus, 0, TBT_GET_SECURITY_LEVEL, 0x008FFFFF);
+    
+    if (CmdDone){
+        RegVal = READ_PCI32(TbtHRbus, 0, 0, RR_TBT2PCIE);
+
+        if ((RegVal & MASK_ERROR) == 0){
+            RegVal = (RegVal & MASK_DATA) >> 8;
+        }
+        else SynchState = 2;
+    } else SynchState = 2;
+    // So far, RegVal variable might be:
+    // 1: 0xFFFFFFFF
+    // 2: Thunderbolt host Revision ID and Class Code
+    // 3: Thunderbolt host Fw security level setting
+
+    // check Security Level setting between Thunderbolt Fw and BIOS
+    if ((UINT8)RegVal != (BiosSecurityLevel - 1)){ 
+        if (PWRFlag == 0){
+            // Pull high GPIO_3(__FORCE_PWR) pin
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+            Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+            Data8 |= 0x02;
+            IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+            Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+            Data32 |= BIT31;
+            IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+
+            PWRFlag = 1;
+        }
+        IoWrite8(0x80, (BiosSecurityLevel - 1 + 0xC0));
+        // After testing, TBT Fw needs Delay 600ms
+        CountTime(600000, PM_BASE_ADDRESS);
+        
+        // Re-config Security Level with BIOS setting
+        CmdDone = TbtSetPCIe2TBTCommand(TbtHRbus, (BiosSecurityLevel - 1), TBT_SET_SECURITY_LEVEL, 0x008FFFFF);
+
+        if (CmdDone)  SynchState = 1;
+        else SynchState = 2;
+    }
+    
+    if (PWRFlag == 1){
+        // Pull low GPIO_3(__FORCE_PWR) pin
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+        Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+        Data8 &= 0xFD;
+        IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#else
+        Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+        Data32 &= (~BIT31);
+        IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+#endif
+
+        // Delay 100ms
+        CountTime(100000, PM_BASE_ADDRESS);
+    }
+//*/
+    return SynchState;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   ProgramTbtSecurityLevel
+//
+// Description: This function is configure the Thunderbolt security level.
+//              OEM Porting required !!!.
+//
+// Input:       UINT8           TbtSecurityLevel
+//              UINT8           TBTHostSeries
+//              UINT8           TbtHostLocation
+//              BOOLEAN         IsPei
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID ProgramTbtSecurityLevel(
+    IN UINT8             *TbtSecurityLevel,
+    IN UINT8             TbtHostSeries,
+    IN UINT8             TbtHostLocation,
+    IN BOOLEAN           IsPei
+)
+{
+// Sample code for ITE8728F and WTM2
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8               Data8    = 0;
+#else
+    UINT32              Data32   = 0;
+#endif
+    UINT8               SecLevel = *TbtSecurityLevel;
+    UINT8               TbtHRbus;
+    BOOLEAN             RRCmd    = FALSE;
+    UINT8               TBus     = TBT_UP_PORT_BUS;
+    UINT8               TDev     = TBT_UP_PORT_DEV;
+    UINT8               TFun     = TBT_UP_PORT_FUNC;
+
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    if (TbtHostSeries == Cactus_Ridge){
+        // For Cactus Ridge chip
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+        Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 3);
+        if (SecLevel == TBT_OFF_MODE){
+            Data8 &= 0xFE;
+            IoWrite8(IT8728_GPIO_BASE_ADDRESS + 3, Data8);
+            return;
+        }
+        if (!(Data8 & BIT0)){
+            Data8 |= 0x01;
+            IoWrite8(IT8728_GPIO_BASE_ADDRESS + 3, Data8);
+        }
+#else
+        if (SecLevel == TBT_OFF_MODE) return;
+#endif
+        
+        Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 5);
+        Data8 &= ~(BIT6 | BIT7);
+        
+        switch (SecLevel)
+        {
+            case TBT_DIRECT_CONNECTED_WO_NHI:
+                Data8 |= BIT6;
+                break;
+            
+            case TBT_REDRIVER_ONLY:
+                Data8 |= BIT7;
+                break;
+            
+            case TBT_NORMAL_MODE_WO_NHI:
+                break;
+            
+            case TBT_NORMAL_MODE:
+            case TBT_DEBUG_MODE:
+            default:
+                // Normal mode with NHI.
+                Data8 |= (BIT6 | BIT7);
+                break;
+        } // end of switch
+
+        // Set GP66 and GP67
+        IoWrite8(IT8728_GPIO_BASE_ADDRESS + 5, Data8);
+        
+        // Set GPIO6 and GPIO7 to the desired levels and
+        // assert GPIO3 for at least 400ms period.
+        // GP21 Pull high
+        Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+        Data8 |= 0x02;
+        IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+    } else {
+        // For Redwood Ridge / Falcon Ridge / Win Ridge chip
+        if (IsPei != TRUE){
+            if(TbtHostLocation < 0x20){
+                TFun = TbtHostLocation;
+            } else {
+                TDev = 0x01;
+                TFun = TbtHostLocation - 0x20;
+            }
+            
+            // Get Thunderbolt Host Router Location
+            TbtHRbus = READ_PCI8(TBus, TDev, TFun, PCI_SBUS);
+            
+            // First pull high GPIO_3(__FORCE_PWR) pin
+            Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+            Data8 |= 0x02;
+            IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+
+            IoWrite8(0x80, (0x80 | (SecLevel - 1)));
+            CountTime(500000, PM_BASE_ADDRESS);
+            
+            // Do PCIE2TBT handshake
+            RRCmd = TbtSetPCIe2TBTCommand(TbtHRbus, (SecLevel - 1), TBT_SET_SECURITY_LEVEL, 0x008FFFFF);
+            if(RRCmd){
+                IoWrite8(0x80, 0x5D);
+                CountTime(100000, PM_BASE_ADDRESS);
+            }
+
+            // Finial pull low GPIO_3(__FORCE_PWR) pin
+            Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+            Data8 &= 0xFD;
+            IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+        } // is not at PEI phase
+    }
+#else
+    if (IsPei != TRUE){
+        if (TbtHostLocation < 20){
+            TFun = TbtHostLocation;
+        } else {
+            TDev = 0x01;
+            TFun = TbtHostLocation - 0x20;
+        }
+     
+        //Get Thunderbolt Host Router Location
+        TbtHRbus = READ_PCI8(TBus, TDev, TFun, PCI_SBUS);
+        
+        // First pull high GPIO_3(__FORCE_PWR) pin
+        Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+        Data32 |= BIT31;
+        IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+        
+        IoWrite8(0x80, (0x80 | (SecLevel - 1)));
+        CountTime(500000, PM_BASE_ADDRESS);
+        
+        // Do PCIE2TBT handshake
+        RRCmd = TbtSetPCIe2TBTCommand(TbtHRbus, (SecLevel - 1), TBT_SET_SECURITY_LEVEL, 0x008FFFFF);
+        
+        //for debug
+        if(RRCmd){
+            IoWrite8(0x80, 0x5D);
+            CountTime(100000, PM_BASE_ADDRESS);
+        }
+     
+        // finial pull low GPIO_3(__FORCE_PWR) pin
+        Data32 = IoRead32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)));
+        Data32 &= ~BIT31;
+        IoWrite32((GPIO_BASE_ADDRESS + 0x100 + (TBT_ForcePWR * 8)), Data32);
+    }
+#endif
+//*/
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   PeiFinialProgramTbtSecurityLevel
+//
+// Description: if system does not support "Wake from Thunderbolt device" 
+//              function, BIOS should depend on Security Level and BootMod to 
+//              pull low FORCE_PWR pin or not in PEI phase
+//
+//              This function only work for Thunderbolt Cactus Ridge chip and 
+//              system doesn't support wake up from Thunderbolt Device
+//
+// Input:       UINT8           TbtSecurityLevel
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID PeiFinialProgramTbtSecurityLevel(
+    IN UINT8             TbtSecurityLevel
+)
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8 Data8;
+    UINT8 SecLevel = TbtSecurityLevel;
+
+    OpenSioConfig();
+    SetSioLdn (0x07);
+    if(ReadSio (0x62) == 0x00){
+        //program Super IO Base Address
+        WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+        WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+    }
+    
+    //The 400 ms delay has been done in TbtPei.c
+    //So just pull low GPIO_3(__FORCE_PWR) pin without any delay
+    if (SecLevel <= 4) {
+        Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+        Data8 &= 0xFD;
+        IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+    }
+#endif
+//*/
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   FinialProgramTbtSecurityLevel
+//
+// Description: BIOS should depend on Security Level to pull low FORCE_PWR pin
+//              or not
+//
+//              This function only work for Thunderbolt Cactus Ridge chip
+//
+// Input:       AMI_TBT_PLATFORM_POLICY_PROTOCOL *PlatformPolocy
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID FinialProgramTbtSecurityLevel(
+    IN AMI_TBT_PLATFORM_POLICY_PROTOCOL *PlatformPolocy
+)
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8 Data8;
+    UINT8 SecLevel = PlatformPolocy->TbtSecurityLevel;
+    
+    OpenSioConfig();
+    SetSioLdn (0x07);
+    if(ReadSio (0x62) == 0x00){
+        //program Super IO Base Address
+        WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+        WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+    }
+    
+    if (SecLevel <= 4) {
+        Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+        Data8 &= 0xFD;
+        IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+    }
+#endif
+//*/
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   ActiveTbtGpio2
+//
+// Description: BIOS should assert GO2Sx pin
+//              That will trigger Host Router to prepare underlying devices
+//              For Thunderbolt host is CR chip
+//
+//              This function only work for Thunderbolt Cactus Ridge chip 
+//
+// Input:       None
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS ActiveTbtGpio2 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8 Data8;
+
+    OpenSioConfig();
+
+    SetSioLdn(0x07);
+    if(ReadSio (0x62) == 0x00){
+        //program Super IO Base Address
+        WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+        WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+    }
+    
+    Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+    Data8 |= BIT0;
+    IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#endif
+//*/
+    return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InactiveTbtGpio2
+//
+// Description: BIOS should deassert GO2Sx pin
+//              That will trigger Host Router to prepare underlying devices
+//
+//              This function only work for Thunderbolt Cactus Ridge chip
+//
+// Input:       None
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS InactiveTbtGpio2 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8 Data8;
+    
+    OpenSioConfig();
+    
+    SetSioLdn(0x07);
+    if(ReadSio (0x62) == 0x00){
+        //program Super IO Base Address
+        WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+        WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+    }
+  
+    Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+    Data8 &= 0xFE;
+    IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#endif
+//*/
+    return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   PollTbtGpio9
+//
+// Description: BIOS should poll OK2GO2SX_N_OD pin
+//              Upon completion of all preparations, Host Router will assert
+//              this pin to indicate readiness for Sx entry.
+//
+//              This function only work for Thunderbolt Cactus Ridge chip
+//
+// Input:       None
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS PollTbtGpio9 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT32 counter = 0;
+    
+    while(IoRead8(IT8728_GPIO_BASE_ADDRESS + 1) & BIT2){
+        if (counter == 0x008FFFFF) break;
+            counter++;
+    }
+#endif
+//*/
+    return EFI_SUCCESS;
+};
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   PullDownTbtGpio9
+//
+// Description: BIOS should pull down OK2GO2SX_N_OD pin in Wake flow
+//              if remebered Host Router state was active.
+//
+//              This function only work for Thunderbolt Cactus Ridge chip and 
+//              system doesn't support wake up from Thunderbolt Device
+//
+// Input:       None
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS PullDownTbtGpio9 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8 Data8;
+    
+    OpenSioConfig();
+    
+    SetSioLdn(0x07);
+    
+    if(ReadSio (0x62) == 0x00){
+        //program Super IO Base Address
+        WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+        WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+    }
+    
+    //program GP22 as GPIO pin
+    Data8 = ReadSio (0x26);
+    Data8 |= 0x04;
+    WriteSio (0x26, Data8);
+    
+    //program GP22 GPIO polarity
+    Data8 = ReadSio (0xB1);
+    Data8 &= 0xF8;
+    WriteSio (0xB1, Data8);
+    
+    //program GP22 internal pull-up enable
+    Data8 = ReadSio (0xB9);
+    Data8 |= 0x04;
+    WriteSio (0xB9, Data8);
+    
+    //program GP22 Simple I/O enable
+    Data8 = ReadSio (0xC1);
+    Data8 |= 0x04;
+    WriteSio (0xC1, Data8);
+    
+    //program GP22 Input/Output Configure
+    //1:Output Mode 0:Input Mode
+    Data8 = ReadSio (0xC9);
+    Data8 |= 0x04;
+    WriteSio (0xC9, Data8);
+    
+    Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 1);
+    Data8 &= 0xFB;
+    IoWrite8(IT8728_GPIO_BASE_ADDRESS + 1, Data8);
+#endif
+//*/
+    return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   ReleaseTbtGpio9
+//
+// Description: BIOS should release pull down OK2GO2SX_N_OD pin in Wake flow
+//              if remebered Host Router state was active
+//
+//              This function only work for Thunderbolt Cactus Ridge chip and 
+//              system doesn't support wake up from Thunderbolt Device
+//
+// Input:       None
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS ReleaseTbtGpio9 ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8 Data8;
+    
+    OpenSioConfig();
+    
+    SetSioLdn(0x07);
+    
+    //program GP22 Input/Output Configure
+    //1:Output Mode 0:Input Mode
+    Data8 = ReadSio (0xC9);
+    Data8 &= 0xFB;
+    WriteSio (0xC9, Data8);
+#endif
+//*/
+    return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   PowerOnPOC
+//
+// Description: Power on POC to wake up thunderbolt
+//
+//              This function is optional and only work for Thunderbolt Cactus 
+//              Ridge chip and system doesn't support wake up from Thunderbolt 
+//              Device.
+//
+// Input:       None
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS PowerOnPOC ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8 Data8;
+    
+    OpenSioConfig();
+    SetSioLdn(0x07);
+    
+    if(ReadSio (0x62) == 0x00){
+        //program Super IO Base Address
+        WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+        WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+    }
+
+    //program GP40 as GPIO pin
+    Data8 = ReadSio (0x28);
+    Data8 |= 0x01;
+    WriteSio (0x28, Data8);
+    
+    //program GP40 GPIO polarity
+    Data8 = ReadSio (0xB3);
+    Data8 &= 0xFE;
+    WriteSio (0xB3, Data8);
+    
+    //GP40 internal internal pull-up enable
+    Data8 = ReadSio (0xBB);
+    Data8 |= 0x01;
+    WriteSio (0xBB, Data8);
+    
+    //GP40 Simple I/O enable
+    Data8 = ReadSio (0xC3);
+    Data8 |= 0x01;
+    WriteSio (0xC3, Data8);
+    
+    //GP40 Input/Output Configure
+    //1:Output Mode 0:Input Mode
+    Data8 = ReadSio (0xCB);
+    Data8 |= 0x01;
+    WriteSio (0xCB, Data8);
+    
+    Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 3);
+    if (!(Data8 & BIT0)){
+        Data8 |= 0x01;
+        IoWrite8(IT8728_GPIO_BASE_ADDRESS + 3, Data8);
+    }
+#endif
+//*/
+    return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   PowerOffPOC
+//
+// Description: Power off POC to cut off thunderbolt power 
+//
+//              This function is optional and only work for Thunderbolt Cactus 
+//              Ridge chip and system doesn't support wake up from Thunderbolt 
+//              Device.
+//
+// Input:       None
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS PowerOffPOC ( VOID )
+{
+// Sample code for ITE8728F
+/*
+#if !defined BWT2_BOARD || BWT2_BOARD == 0
+    UINT8 Data8;
+    
+    OpenSioConfig();
+    SetSioLdn(0x07);
+    
+    if(ReadSio (0x62) == 0x00){
+        //program Super IO Base Address
+        WriteSio(0x62, (UINT8)(IT8728_GPIO_BASE_ADDRESS >> 8));
+        WriteSio(0x63, (UINT8)(IT8728_GPIO_BASE_ADDRESS & 0xFF));
+    }
+  
+    Data8 = IoRead8(IT8728_GPIO_BASE_ADDRESS + 3);
+    Data8 &= 0xFE;
+    IoWrite8(IT8728_GPIO_BASE_ADDRESS + 3, Data8);
+#endif
+//*/
+    return EFI_SUCCESS;
+}
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.h b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.h
new file mode 100644
index 0000000..ba3ca91
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemLib.h
@@ -0,0 +1,216 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemLib.h 4     5/19/14 7:38a Barretlin $
+//
+// $ReviGpion: 1 $
+//
+// $Date: 5/19/14 7:38a $
+//*************************************************************************
+// ReviGpion History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtOemLib.h $
+// 
+// 4     5/19/14 7:38a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 3     1/05/14 2:06p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtOemBoard.h TbtOemBoard.c TbtOemLib.c TbtOemLib.h
+// 
+// 2     4/03/13 2:47a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Double check Security Level between Thunderbolt host FW
+// and BIOS are same or not for Redwood Ridge chip when entering setup
+// page.
+// [Files]  		TbtOemLib.c TbtOemLib.h TbtSetupReset.c
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 7     12/12/12 4:14a Barretlin
+// [TAG]  		EIP108272
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+// [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 6     10/28/12 11:50p Barretlin
+// [TAG]  		EIP104870
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files]  		TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+// 
+// 5     10/04/12 10:42p Barretlin
+// [TAG]  		EIP102947
+// [Category]  	Spec Update
+// [Severity]  	Normal
+// [Description]  	Update Thunderbolt Spec to Rev 1.2
+// [Files]  		TbtPei.c TbtOemLib.c TbtOemLib.h
+// 
+// 4     10/03/12 9:27p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change Programming security level timing for saving
+// boot time
+// [Files]  		TbtPei.c TbtDxe.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 3     3/05/12 1:16a Barretlin
+// [TAG]  		EIP83266
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.90
+// [Files]  		TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+// 
+// 1     2/19/12 11:56p Wesleychen
+// [TAG]         None
+// [Category]    Improvement
+// [Description] Add TbtOemLib.
+// [Files]       TbtOemLib.c; TbtOemLib.h; TbtOemBoard,mak;
+//               TbtOemBoard.cif.
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+//
+//*************************************************************************
+#ifndef _THUNDERBOLT_OEM_LIB_
+#define _THUNDERBOLT_OEM_LIB_
+
+#include "TbtOemBoard.h"
+
+UINT8 ReadSio(
+  IN UINT8           Index
+);
+
+VOID WriteSio(
+  IN UINT8           Index,
+  IN UINT8           Value
+);
+
+VOID SetSio(
+  IN UINT8           Index,
+  IN UINT8           Set
+);
+
+VOID ResetSio(
+  IN UINT8           Index,
+  IN UINT8           Rst
+);
+
+VOID OpenSioConfig(
+  VOID
+);
+
+VOID SetSioLdn(
+  IN UINT8           Ldn
+);
+
+UINT8 GetHRInfo(
+  VOID
+);
+
+BOOLEAN TbtSetPCIe2TBTCommand(
+  IN UINT8             UpPortBus,
+  IN UINT8             Data,
+  IN UINT8             Command,
+  IN UINTN             Timeout
+);
+
+VOID TbtBeforeSxExitFlow(
+  IN VOID              *Services,
+  IN UINT8             TbtHostSeries
+);
+
+UINT8 SynchSecurityLevel(
+  IN UINT8             BiosSecurityLevel,
+  IN UINT8             TbtHostLocation
+);
+
+VOID ProgramTbtSecurityLevel(
+  IN UINT8             *TbtSecurityLevel,
+  IN UINT8             TbtHostSeries,
+  IN UINT8             TbtHostLocation,
+  IN BOOLEAN           IsPei
+);
+
+VOID PeiFinialProgramTbtSecurityLevel(
+  IN UINT8             TbtSecurityLevel
+);
+
+VOID FinialProgramTbtSecurityLevel(
+  IN AMI_TBT_PLATFORM_POLICY_PROTOCOL *PlatformPolocy
+);
+
+EFI_STATUS ActiveTbtGpio2(
+  VOID
+);
+
+EFI_STATUS InactiveTbtGpio2(
+  VOID
+);
+
+EFI_STATUS PollTbtGpio9(
+  VOID
+);
+
+EFI_STATUS PullDownTbtGpio9(
+  VOID
+);
+
+EFI_STATUS ReleaseTbtGpio9(
+  VOID
+);
+
+EFI_STATUS PowerOnPOC(
+  VOID
+);
+
+EFI_STATUS PowerOffPOC(
+  VOID
+);
+
+#endif // _THUNDERBOLT_OEM_LIB_
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtOemPorting.asl b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemPorting.asl
new file mode 100644
index 0000000..7edd513
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtOemPorting.asl
@@ -0,0 +1,13 @@
+    // Asserts/De-asserts TBT force power
+    Method(TBFP, 1)
+    {
+        // OEM Porting Required
+        If(Arg0)
+        {
+            // Implementation dependent way to assert TBT force power
+        }
+        Else
+        {
+            // Implementation dependent way to de-assert TBT force power
+        }
+    }
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c
new file mode 100644
index 0000000..f22b493
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c
@@ -0,0 +1,172 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+//
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c 5     2/18/14 7:31a Barretlin $
+//
+// $Revision: 5 $
+//
+// $Date: 2/18/14 7:31a $
+//
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.c $
+// 
+// 5     2/18/14 7:31a Barretlin
+// [TAG]  		EIP152401
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	add new thunderbolt chip series
+// [Files]  		TbtSetup.c
+// 
+// 4     6/19/13 8:33a Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Improvement
+// [Description]  	use thunderbolt FR spec token to update setup string
+// [Files]  		TbtSeup.c
+// 
+// 3     6/16/13 10:23p Barretlin
+// [TAG]  		EIP None
+// [Category]  	Improvement
+// [Description]  	change CR BIOS Spec version display way
+// [Files]  		TbtSetup.c
+// 
+// 2     5/27/13 8:15a Barretlin
+// [TAG]  		EIP124914
+// [Category]  	New Feature
+// [Description]  	Support Falcon Ridge chip
+// [Files]  		TbtSetup.c
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 4     8/16/12 4:19p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add Thunderbolt Intel Sample Code version information
+// [Files]  		Thunderbolt.sdl TbtSetup.sd TbtSetup.uni TbtSetup.c
+// 
+// 3     7/31/12 5:28a Barretlin
+// 
+// 2     5/24/12 10:20p Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Add Thunderbolt version on setup menu
+// [Files]  		TbtSetup.sd TbtSetup.uni TbtSetup.c
+// Thunderbolt.sdl
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//**********************************************************************
+#include <token.h>
+#include <Setup.h>
+#include <AmiCSPLib.h>
+#include <AmiDxeLib.h>
+#include <TbtOemBoard.h>
+#include <SetupStrTokens.h>
+#if EFI_SPECIFICATION_VERSION>0x20000
+#include <Protocol\HiiDatabase.h>
+#include <Protocol\HiiString.h>
+#else
+#include <Protocol/Hii.h>
+#endif
+
+//----------------------------------------------------------------------------
+// GUID Definition(s)
+//----------------------------------------------------------------------------
+static EFI_GUID  TbtHRStatusGuid           = AMI_TBT_HR_STATUS_GUID;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InitiTbtInfo
+//
+// Description: Initializes Thunderbolt Setup String
+//
+// Input:       HiiHandle - Handle to HII database
+//              Class - Indicates the setup class
+//
+// Output:      None
+//
+// Notes:       PORTING REQUIRED
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID InitiTbtInfo(
+  IN EFI_HII_HANDLE   HiiHandle,
+  IN UINT16           Class )
+{
+  EFI_STATUS              Status;
+  UINTN                   HRStatusSize     = sizeof(AMI_TBT_HR_STATUS_DATA);
+  CHAR16                  TbtHRStatusVar[] = TBT_HR_STATUS_VARIABLE;
+  AMI_TBT_HR_STATUS_DATA  HRStatusData;
+  CHAR16                  *TbtCR           = L"Cactus Ridge";
+  CHAR16                  *TbtRR           = L"Redwood Ridge";
+  CHAR16                  *TbtFR           = L"Falcon Ridge";
+  CHAR16                  *TbtWR           = L"BDW-TBT-LP(WR)";
+
+  Status = pRS->GetVariable( L"TbtHRStatusVar", \
+                             &TbtHRStatusGuid, \
+                             NULL, \
+                             &HRStatusSize, \
+                             &HRStatusData );
+
+  TRACE((-1, "TbtSetup: HR is %x series\n", HRStatusData.TbtHRSeries));
+
+  InitString(HiiHandle, STRING_TOKEN(STR_TBT_RC_VERSION_VALUE),
+                L"%d.%d", TBT_RC_VERSION/10, TBT_RC_VERSION%10);
+
+  if (HRStatusData.TbtHRSeries == Cactus_Ridge){
+     InitString(HiiHandle, STRING_TOKEN(STR_TBT_SPEC_VERSION_VALUE),
+                   L"%d.%d", Thunderbolt_CR_VERSION/10, Thunderbolt_CR_VERSION%10);
+
+     InitString(HiiHandle, STRING_TOKEN(STR_TBT_HOST_VALUE),
+                   L"%s", TbtCR);
+  } else if (HRStatusData.TbtHRSeries == Redwood_Ridge) {
+     InitString(HiiHandle, STRING_TOKEN(STR_TBT_SPEC_VERSION_VALUE),
+                   L"%d.%d", Thunderbolt_RR_VERSION/10, Thunderbolt_RR_VERSION%10);
+
+     InitString(HiiHandle, STRING_TOKEN(STR_TBT_HOST_VALUE),
+                   L"%s", TbtRR);
+  } else if (HRStatusData.TbtHRSeries == Falcon_Ridge){
+     InitString(HiiHandle, STRING_TOKEN(STR_TBT_SPEC_VERSION_VALUE),
+                   L"%d.%d", Thunderbolt_FR_VERSION/10, Thunderbolt_FR_VERSION%10);
+
+     InitString(HiiHandle, STRING_TOKEN(STR_TBT_HOST_VALUE),
+                   L"%s", TbtFR);
+  } else {
+     InitString(HiiHandle, STRING_TOKEN(STR_TBT_SPEC_VERSION_VALUE),
+                   L"%d.%d", Thunderbolt_WR_VERSION/10, Thunderbolt_WR_VERSION%10);
+
+     InitString(HiiHandle, STRING_TOKEN(STR_TBT_HOST_VALUE),
+                   L"%s", TbtWR);
+  }
+}
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.cif b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.cif
new file mode 100644
index 0000000..8b8b975
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.cif
@@ -0,0 +1,14 @@
+<component>
+	name = "TbtSetup"
+	category = ModulePart
+	LocalRoot = "Board\EM\Thunderbolt\TbtOemBoard\TbtSetup"
+	RefName = "TbtSetup"
+[files]
+"TbtSetup.sdl"	
+"TbtSetup.mak"	
+"TbtSetup.sd"	
+"TbtSetup.uni"	
+"TbtSetup.c"	
+"TbtSetup.h"	
+"TbtSetupReset.c"	
+<endComponent>
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h
new file mode 100644
index 0000000..f249648
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h
@@ -0,0 +1,70 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+//
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h 1     1/10/13 4:57a Barretlin $
+//
+// $Revision: 1 $
+//
+// $Date: 1/10/13 4:57a $
+//
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.h $
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//**********************************************************************
+
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name:            iFfsSetup.h
+//
+// Description:     Header file for iFfsSetup module.
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+
+#ifndef __FFS_SETUP_H__
+#define __FFS_SETUP_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/****** DO NOT WRITE BELOW THIS LINE *******/
+#ifdef __cplusplus
+}
+#endif
+#endif
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak
new file mode 100644
index 0000000..95a1028
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak
@@ -0,0 +1,89 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+#
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak 1     1/10/13 4:57a Barretlin $
+#
+# $Revision: 1 $
+#
+# $Date: 1/10/13 4:57a $
+#
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.mak $
+# 
+# 1     1/10/13 4:57a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 2     12/12/12 4:47a Barretlin
+# [TAG]  		None
+# [Category]  	New Feature
+# [Description]  	Add Thunderbolt TSE Setup Reset Hook
+# [Files]  		TbtSetup.sdl TbtSetup.mak TbtSetup.cif TbtSetupReset.c
+# 
+# 1     12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+# 
+#**********************************************************************
+#
+#<AMI_FHDR_START>
+#----------------------------------------------------------------------------
+#
+# Name:            Tbt Setup.mak
+#
+# Description:     Makfile for TBT Setup module.
+#
+#----------------------------------------------------------------------------
+#<AMI_FHDR_END>
+All : TbtSetup
+
+TbtSetup : $(BUILD_DIR)\TbtSetup.mak
+
+SetupSdbs : $(BUILD_DIR)\TbtSetup.sdb
+
+$(BUILD_DIR)\TbtSetup.sdb : $(TbtSetup_DIR)\$(@B).sd $(TbtSetup_DIR)\$(@B).uni
+        $(STRGATHER) -i INCLUDE -parse -newdb -db $(BUILD_DIR)\$(@B).sdb $(TbtSetup_DIR)\$(@B).uni
+        $(STRGATHER) -scan -db $(BUILD_DIR)\$(@B).sdb -od $(BUILD_DIR)\$(@B).sdb $(TbtSetup_DIR)\$(@B).sd
+
+$(BUILD_DIR)\TbtSetup.mak : $(TbtSetup_DIR)\$(@B).cif $(TbtSetup_DIR)\$(@B).mak $(BUILD_RULES)
+        $(CIF2MAK) $(TbtSetup_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+SetupBin : $(BUILD_DIR)\TbtSetup.obj
+
+$(BUILD_DIR)\TbtSetup.obj : $(TbtSetup_DIR)\TbtSetup.c $(BUILD_DIR)\SetupStrTokens.h
+	$(CC) $(CFLAGS) $(TBT_OEMBOARD_INCLUDES) /Fo$(BUILD_DIR)\ $(TbtSetup_DIR)\TbtSetup.c
+
+#----------------------------------------------------------------------------
+#       Create Thunderbolt Setup TSE Reset Hook
+#----------------------------------------------------------------------------
+AMITSEBin :  $(BUILD_DIR)\TbtSetupReset.obj
+
+$(BUILD_DIR)\TbtSetupReset.obj : $(TbtSetup_DIR)\TbtSetupReset.c $(AMICSPLib)
+		$(CC) $(CFLAGS) $(INTEL_PCH_INCLUDES) $(TBT_OEMBOARD_INCLUDES) /Fo$(BUILD_DIR)\ $(TbtSetup_DIR)\TbtSetupReset.c 
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd
new file mode 100644
index 0000000..ccc8166
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd
@@ -0,0 +1,1456 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+//
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd 13    5/19/14 7:40a Barretlin $
+//
+// $Revision: 13 $
+//
+// $Date: 5/19/14 7:40a $
+//
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sd $
+// 
+// 13    5/19/14 7:40a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	Improvement
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 12    5/19/14 7:19a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Using setup item choose return value of _RMV method in
+// ASL code
+// [Files]  		TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+// TbtSetup.sdl TbtSetup.uni
+// 
+// 11    2/10/14 1:30p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	remove useless policy item and setup item
+// [Files]  		TbtOemBoard.h TbtOemBoard.c TbSetup.sdl TbtSetup.sd
+// TbtSetup.uni TbtSmm.c
+// 
+// 10    1/05/14 2:14p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni TbtSetupReset.c
+// 
+// 9     12/24/13 11:40a Barretlin
+// [TAG]  		EIP148198
+// [Category]  	Improvement
+// [Description]  	Updating for Thunderbolt BIOS additions rev.1.8 
+// [Files]  		TbtSetup.sd
+// 
+// 8     6/24/13 5:10a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error with non Intel RC project
+// [Files]  		TbtSetup.sd
+// 
+// 7     6/17/13 4:25a Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Improvement
+// [Description]  	add new AIC support setup item and change
+// TBWakeupSupport name
+// [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 6     5/06/13 12:13a Barretlin
+// 
+// 5     4/24/13 1:38a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Clone APCI PCIE setup item
+// [Files]  		TbtSetup.sd TbtSetup.uni
+// 
+// 4     4/09/13 11:38p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add cloned PCIE config for ULT platform
+// [Files]  		TbtSetup.sd
+// 
+// 3     3/21/13 6:00a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Clone PCIE prot swap setup item and set disable by
+// default
+// [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 2     2/06/13 1:55a Barretlin
+// [TAG]  		EIP None
+// [Category]  	Improvement
+// [Description]  	Hide unused setup item for RR chip
+// [Files]  		TbtSetup.sd
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 15    10/27/12 6:16a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Create new setup item for thunderbolt POC handling
+// [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 14    10/04/12 5:40p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Update Setup item
+// [Files]  		TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 13    9/22/12 9:53a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Clone SB PCIE setup item which are related thunderbolt
+// [Files]  		TbtSetup.sd TbtSetup.uni
+// 
+// 12    8/20/12 5:16a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix IO resource workaround broken in 4C 2port case
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+// 
+// 11    8/17/12 8:53a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add IO resource workaround for Thunderbolt Spec1.1
+// Because new spec has removed IO resource for Thunderbolt device
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+// 
+// 10    8/16/12 4:19p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add Thunderbolt Intel Sample Code version information
+// [Files]  		Thunderbolt.sdl TbtSetup.sd TbtSetup.uni TbtSetup.c
+// 
+// 9     7/31/12 4:01a Barretlin
+// [TAG]  		EIP96350
+// [Category]  	Spec Update
+// [Severity]  	Critical
+// [Description]  	Updated Thunderbolt specification to version 1.00
+// [Files]  		TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 8     7/31/12 3:28a Barretlin
+// [TAG]  		EIP91119
+// [Category]  	Improvement
+// [Description]  	Resolution for enable/disable Thunderbolt device option
+// rom at POST time
+// [Files]  		TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 7     5/24/12 10:20p Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Add Thunderbolt version on setup menu
+// [Files]  		TbtSetup.sd TbtSetup.uni TbtSetup.c
+// Thunderbolt.sdl
+// 
+// 6     5/22/12 10:05a Barretlin
+// [TAG]  		EIP90650
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.94 - The default value of
+// OPTIONAL workaround for devices that don't support surprise-removal
+// should be disable.
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 5     5/07/12 7:04a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Add three setup items for debug
+// [Files]  		TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+// 
+// 4     3/05/12 1:11a Barretlin
+// [TAG]  		EIP83266
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.90
+// [Files]  		TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+// 
+// 2     2/19/12 11:52p Wesleychen
+// Add new setup item "SmiNotifyEnabled".
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//**********************************************************************
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name:            Thunderbolt Setup.sd
+//
+// Description:     Setup for Thunderbolt Setup.
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+
+#ifdef SETUP_DATA_DEFINITION
+/***********************************************************/
+/* Put NVRAM data definitions here.
+/* For example: UINT8 Data1;
+/* These definitions will be converted by the build process
+/* to a definitions of SETUP_DATA fields.
+/***********************************************************/
+  UINT8  TbtEnable;
+  UINT8  TbtHRSeries;
+  UINT8  TbtWakeupSupport;
+  UINT8  TbtAICSupport;
+  UINT8  TbtHostLocation;
+  UINT8  TbtHandlePOC;
+  UINT8  TbtCacheLineSize;
+  UINT8  TbtSecurityLevel;
+  UINT8  SmiNotifyEnabled;
+  UINT8  SwSmiEnabled;
+  UINT8  NotifyEnabled;
+  UINT8  TbtRmvReturnValue;
+  UINT8  TbtOptionRom;
+  UINT16 TbtWakeupDelay;
+  UINT16 TbtSwSMIDelay;
+  //Resources for Per Slot under Thunderbolt
+  UINT16 ReserveMemoryPerSlot;
+  UINT16 ReservePMemoryPerSlot;
+  UINT8  ReserveIOPerSlot;
+  UINT8  TbtIOresourceEnable;
+  UINT8  TbtNVMversion;
+#endif
+
+#if defined(VFRCOMPILE) && !defined(CONTROLS_ARE_DEFINED)
+#define CONTROL_DEFINITION
+#endif
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+#ifdef CONTROL_DEFINITION
+
+#define TBT_ONEOF_TBTENABLE\
+    checkbox varid = SETUP_DATA.TbtEnable,\
+        prompt       = STRING_TOKEN (STR_TBT_ENABLE_PROMPT),\
+        help         = STRING_TOKEN (STR_TBT_ENABLE_HELP),\
+        flags        = DEFAULT_TBT_ENABLE | MANUFACTURING | RESET_REQUIRED,\
+    endcheckbox;
+
+#define TBT_ONEOF_TBTWAKEUPSUPPORT\
+  checkbox varid = SETUP_DATA.TbtWakeupSupport,\
+    prompt       = STRING_TOKEN (STR_TBT_DEVICE_WAKE_UP_SUPPORT_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_DEVICE_WAKE_UP_SUPPORT_HELP),\
+    flags        = DEFAULT_TB_WAKE_UP_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+  endcheckbox;
+
+#define TBT_ONEOF_TBTHANDLEPOC\
+  checkbox varid = SETUP_DATA.TbtHandlePOC,\
+    prompt       = STRING_TOKEN (STR_TBT_HANDLE_POC_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_HANDLE_POC_HELP),\
+    flags        = DEFAULT_TBT_HANDLE_POC | RESET_REQUIRED | MANUFACTURING, \
+  endcheckbox;
+
+#define TBT_ONEOF_TBTAICSUPPORT\
+  checkbox varid = SETUP_DATA.TbtAICSupport,\
+    prompt       = STRING_TOKEN (STR_TBT_AIC_SUPPORT_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_AIC_SUPPORT_HELP),\
+    flags        = DEFAULT_TBT_AIC_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+  endcheckbox;
+
+#define TBT_ONEOF_TBTHOSTLOCATION\
+  oneof varid      = SETUP_DATA.TbtHostLocation,\
+    prompt       = STRING_TOKEN (STR_TBT_HOST_LOCATION_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_HOST_LOCATION_HELP),\
+    default      = DEFAULT_TBT_AIC_LOCATION,\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_000), value = 0x00, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_001), value = 0x01, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_002), value = 0x02, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_003), value = 0x03, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_004), value = 0x04, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_005), value = 0x05, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_006), value = 0x06, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_007), value = 0x07, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_016), value = 0x20, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_017), value = 0x21, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_HOST_LOCATION_018), value = 0x22, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+
+#define TBT_ONEOF_TBTCACHELINESIZE\
+  oneof varid   = SETUP_DATA.TbtCacheLineSize,\
+    prompt      = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_PROMPT),\
+    help        = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_HELP),\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_000), value = 0x00, flags =  RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_001), value = 0x01, flags =  RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_002), value = 0x02, flags =  RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_004), value = 0x04, flags =  RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_008), value = 0x08, flags =  RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_016), value = 0x10, flags =  RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_032), value = 0x20, flags =  DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_064), value = 0x40, flags =  RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CACHE_LINE_SIZE_128), value = 0x80, flags =  RESET_REQUIRED, key = 0;\
+  endoneof;
+
+#if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+#define TBT_ONEOF_TBTCRSECURITYLEVEL\
+  oneof varid   = SETUP_DATA.TbtSecurityLevel,\
+    prompt      = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_PROMPT),\
+    help        = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_HELP),\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE1), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE2), value = 2, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE3), value = 3, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE4), value = 4, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE5), value = 5, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE6), value = 6, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#else
+#define TBT_ONEOF_TBTCRSECURITYLEVEL\
+  oneof varid   = SETUP_DATA.TbtSecurityLevel,\
+    prompt      = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_PROMPT),\
+    help        = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_HELP),\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE1), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE2), value = 2, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE3), value = 3, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE4), value = 4, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_CR_MODE6), value = 6, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#define TBT_ONEOF_TBTRRSECURITYLEVEL\
+  oneof varid   = SETUP_DATA.TbtSecurityLevel,\
+    prompt      = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_PROMPT),\
+    help        = STRING_TOKEN(STR_TBT_SECURITY_LEVEL_HELP),\
+    option text = STRING_TOKEN(STR_TBT_RR_MODE1), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_RR_MODE2), value = 2, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_RR_MODE3), value = 3, flags = RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_TBT_RR_MODE4), value = 4, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+
+#define TBT_ONEOF_SMINOTIFYENABLED\
+  checkbox varid = SETUP_DATA.SmiNotifyEnabled,\
+    prompt       = STRING_TOKEN (STR_TBT_SMI_NOTIFY_SUPPORT_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_SMI_NOTIFY_SUPPORT_HELP),\
+    flags        = DEFAULT_TB_SMI_NOTIFY_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+  endcheckbox;
+
+#define TBT_ONEOF_SWSMIENABLED\
+  checkbox varid = SETUP_DATA.SwSmiEnabled,\
+    prompt       = STRING_TOKEN (STR_TBT_SWSMI_SUPPORT_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_SWSMI_SUPPORT_HELP),\
+    flags        = DEFAULT_TB_SMI_NOTIFY_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+  endcheckbox;
+
+#define TBT_ONEOF_NOTIFYENABLED\
+  checkbox varid = SETUP_DATA.NotifyEnabled,\
+    prompt       = STRING_TOKEN (STR_TBT_NOTIFY_SUPPORT_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_NOTIFY_SUPPORT_HELP),\
+    flags        = DEFAULT_TB_SMI_NOTIFY_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+  endcheckbox;
+
+#define TBT_ONEOF_RMVRETRUNVALUE\
+  oneof varid    = SETUP_DATA.TbtRmvReturnValue,\
+    prompt       = STRING_TOKEN(STR_TBT_RMV_RETURN_VALUE_PROMPT),\
+    help         = STRING_TOKEN(STR_TBT_RMV_RETURN_VALUE_HELP),\
+    default      = DEFAULT_TBT_RMV_RETURN_VALUE,\
+    option text  = STRING_TOKEN(STR_TBT_RMV_RETURN_VALUE_0), value = 0, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN(STR_TBT_RMV_RETURN_VALUE_1), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+
+#define TBT_ONEOF_OPTIONROM\
+  checkbox varid = SETUP_DATA.TbtOptionRom,\
+    prompt       = STRING_TOKEN (STR_TBT_OPTIONROM_SUPPORT_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_OPTIONROM_SUPPORT_HELP),\
+    flags        = DEFAULT_SKIP_TBT_OPTIONROM | RESET_REQUIRED | MANUFACTURING, \
+  endcheckbox;
+
+#define TBT_ONEOF_TBTWAKEUPDELAY\
+  numeric varid  = SETUP_DATA.TbtWakeupDelay,\
+   prompt       = STRING_TOKEN (STR_TBT_WAKE_UP_DELAY_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_WAKE_UP_DELAY_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = 65535,\
+    step         = 1,\
+    default      = DEFAULT_TBT_WAK_DELAY,\
+    option text  = STRING_TOKEN (STR_TBT_WAKE_UP_DELAY_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+
+#define TBT_ONEOF_TBTSWSMIDELAY\
+  numeric varid  = SETUP_DATA.TbtSwSMIDelay,\
+   prompt       = STRING_TOKEN (STR_TBT_SWSMI_DELAY_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_SWSMI_DELAY_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = 65535,\
+    step         = 1,\
+    default      = DEFAULT_TBT_SWSMI_DELAY,\
+    option text  = STRING_TOKEN (STR_TBT_SWSMI_DELAY_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+
+#define TBT_ONEOF_PERSLOTMEMRSVD\
+  numeric varid  = SETUP_DATA.ReserveMemoryPerSlot,\
+    prompt       = STRING_TOKEN (STR_TBT_PERSLOT_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_PERSLOT_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = TBT_MAX_PCIE_MEM_RESERVED,\
+    step         = 1,\
+    default      = 32,\
+    option text  = STRING_TOKEN (STR_TBT_PERSLOT_RMEM_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+
+#define TBT_ONEOF_PERSLOTPFMEMRSVD\
+  numeric varid  = SETUP_DATA.ReservePMemoryPerSlot,\
+    prompt       = STRING_TOKEN (STR_TBT_PERSLOT_PF_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_PERSLOT_PF_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+    step         = 1,\
+    default      = 32,\
+    option text  = STRING_TOKEN (STR_TBT_PERSLOT_PF_RMEM_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+
+#define TBT_ONEOF_PERSLOTIORSVD\
+  numeric varid  = SETUP_DATA.ReserveIOPerSlot,\
+    prompt       = STRING_TOKEN (STR_TBT_PERSLOT_RVIO_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_PERSLOT_RVIO_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 4,\
+    maximum      = TBT_MAX_PCIE_IO_RESERVED,\
+    step         = 4,\
+    default      = 4,\
+    option text  = STRING_TOKEN (STR_TBT_PERSLOT_RVIO_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+
+#define TBT_ONEOF_IORESOURCEENABLED\
+  checkbox varid = SETUP_DATA.TbtIOresourceEnable,\
+    prompt       = STRING_TOKEN (STR_TBT_IORESOURCE_SUPPORT_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_IORESOURCE_SUPPORT_HELP),\
+    flags        = DEFAULT_TBT_IO_RESOURCE_SUPPORT | RESET_REQUIRED | MANUFACTURING, \
+  endcheckbox;
+
+#define TBT_ONEOF_NVMVERSION\
+  numeric varid  = SETUP_DATA.TbtNVMversion,\
+   prompt       = STRING_TOKEN (STR_TBT_NVM_VERSION_PROMPT),\
+    help         = STRING_TOKEN (STR_TBT_NVM_VERSION_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 11,\
+    maximum      = 65535,\
+    step         = 1,\
+    default      = TBT_NVM,\
+    option text  = STRING_TOKEN (STR_TBT_NVM_VERSION_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+
+#if defined (TBT_INTEL_RC_CONFIG) && (TBT_INTEL_RC_CONFIG == 1)
+//---------------------------------------------------------------------------
+//                          ACPI PCIE Setting 
+//---------------------------------------------------------------------------
+
+#ifdef ACPI_ONEOF_PCIEXPNATIVE
+#undef ACPI_ONEOF_PCIEXPNATIVE
+#define ACPI_ONEOF_PCIEXPNATIVE\
+  oneof varid  = SETUP_DATA.PciExpNative,\
+    prompt = STRING_TOKEN(STR_ACPI_PCIE_NATIVE_PROMPT),\
+    help = STRING_TOKEN(STR_ACPI_PCIE_NATIVE_HELP),\
+    option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#ifdef ACPI_ONEOF_NATIVEASPMENABLE
+#undef ACPI_ONEOF_NATIVEASPMENABLE
+#define ACPI_ONEOF_NATIVEASPMENABLE\
+  oneof varid    = SETUP_DATA.NativeAspmEnable,\
+    prompt   = STRING_TOKEN(STR_ACPI_NATIVE_ASPM_PROMPT),\
+    help     = STRING_TOKEN(STR_ACPI_NATIVE_ASPM_HELP),\
+    option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+//---------------------------------------------------------------------------
+//                       SB PCIE Root Port Setting 
+//---------------------------------------------------------------------------
+
+#if defined (DISABLE_PCIE_ROOT_PORT_SWAP) && (DISABLE_PCIE_ROOT_PORT_SWAP == 1)
+#ifdef SB_ONEOF_ROOTPORTFUNCTIONSWAPPING
+#undef SB_ONEOF_ROOTPORTFUNCTIONSWAPPING
+#define SB_ONEOF_ROOTPORTFUNCTIONSWAPPING\
+  oneof varid    = SETUP_DATA.RootPortFunctionSwapping,\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PORT_SWAP_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PORT_SWAP_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+#endif
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 0)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE00
+#undef SB_ONEOF_PCIEROOTPORTHPE00
+#define SB_ONEOF_PCIEROOTPORTHPE00\
+  oneof varid    = SETUP_DATA.PcieRootPortHPE[OFFSET_0],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD00
+#undef SB_ONEOF_EXTRABUSRSVD00
+#define SB_ONEOF_EXTRABUSRSVD00\
+  numeric varid  = SETUP_DATA.ExtraBusRsvd[OFFSET_0],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_EXTRA_BUS_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD00
+#undef SB_ONEOF_PCIEMEMRSVD00
+#define SB_ONEOF_PCIEMEMRSVD00\
+  numeric varid  = SETUP_DATA.PcieMemRsvd[OFFSET_0],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG00
+#undef SB_ONEOF_PCIEMEMRSVDALIG00
+#define SB_ONEOF_PCIEMEMRSVDALIG00\
+  numeric varid  = SETUP_DATA.PcieMemRsvdalig[OFFSET_0],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 26,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD00
+#undef SB_ONEOF_PCIEPFMEMRSVD00
+#define SB_ONEOF_PCIEPFMEMRSVD00\
+  numeric varid  = SETUP_DATA.PciePFMemRsvd[OFFSET_0],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG00
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG00
+#define SB_ONEOF_PCIEPFMEMRSVDALIG00\
+  numeric varid  = SETUP_DATA.PciePFMemRsvdalig[OFFSET_0],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 28,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD00
+#undef SB_ONEOF_PCIEIORSVD00
+#define SB_ONEOF_PCIEIORSVD00\
+  numeric varid  = SETUP_DATA.PcieIoRsvd[OFFSET_0],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_IO_RESERVED,\
+    step         = 4,\
+    default      = TBT_DEFAULT_PCIE_IO_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // IO resource
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN01
+#undef SB_ONEOF_PCIEROOTPORTEN01
+#define SB_ONEOF_PCIEROOTPORTEN01\
+  oneof varid    = SETUP_DATA.PcieRootPortEn[OFFSET_1],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIERP2_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif // PCIE root port1 disable
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN02
+#undef SB_ONEOF_PCIEROOTPORTEN02
+#define SB_ONEOF_PCIEROOTPORTEN02\
+  oneof varid    = SETUP_DATA.PcieRootPortEn[OFFSET_2],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIERP3_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif // PCIE root port2 disable
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN03
+#undef SB_ONEOF_PCIEROOTPORTEN03
+#define SB_ONEOF_PCIEROOTPORTEN03\
+  oneof varid    = SETUP_DATA.PcieRootPortEn[OFFSET_3],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIERP4_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif // PCIE root port3 disable
+#endif //TBT_UP_PORT_FUNC == 0
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 1)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE01
+#undef SB_ONEOF_PCIEROOTPORTHPE01
+#define SB_ONEOF_PCIEROOTPORTHPE01\
+  oneof varid    = SETUP_DATA.PcieRootPortHPE[OFFSET_1],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD01
+#undef SB_ONEOF_EXTRABUSRSVD01
+#define SB_ONEOF_EXTRABUSRSVD01\
+  numeric varid  = SETUP_DATA.ExtraBusRsvd[OFFSET_1],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_EXTRA_BUS_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD01
+#undef SB_ONEOF_PCIEMEMRSVD01
+#define SB_ONEOF_PCIEMEMRSVD01\
+  numeric varid  = SETUP_DATA.PcieMemRsvd[OFFSET_1],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG01
+#undef SB_ONEOF_PCIEMEMRSVDALIG01
+#define SB_ONEOF_PCIEMEMRSVDALIG01\
+  numeric varid  = SETUP_DATA.PcieMemRsvdalig[OFFSET_1],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 26,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD01
+#undef SB_ONEOF_PCIEPFMEMRSVD01
+#define SB_ONEOF_PCIEPFMEMRSVD01\
+  numeric varid  = SETUP_DATA.PciePFMemRsvd[OFFSET_1],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG01
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG01
+#define SB_ONEOF_PCIEPFMEMRSVDALIG01\
+  numeric varid  = SETUP_DATA.PciePFMemRsvdalig[OFFSET_1],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 28,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD01
+#undef SB_ONEOF_PCIEIORSVD01
+#define SB_ONEOF_PCIEIORSVD01\
+  numeric varid  = SETUP_DATA.PcieIoRsvd[OFFSET_1],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_IO_RESERVED,\
+    step         = 4,\
+    default      = TBT_DEFAULT_PCIE_IO_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // IO resource
+#endif //TBT_UP_PORT_FUNC == 1
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 2)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE02
+#undef SB_ONEOF_PCIEROOTPORTHPE02
+#define SB_ONEOF_PCIEROOTPORTHPE02\
+  oneof varid    = SETUP_DATA.PcieRootPortHPE[OFFSET_2],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD02
+#undef SB_ONEOF_EXTRABUSRSVD02
+#define SB_ONEOF_EXTRABUSRSVD02\
+  numeric varid  = SETUP_DATA.ExtraBusRsvd[OFFSET_2],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_EXTRA_BUS_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD02
+#undef SB_ONEOF_PCIEMEMRSVD02
+#define SB_ONEOF_PCIEMEMRSVD02\
+  numeric varid  = SETUP_DATA.PcieMemRsvd[OFFSET_2],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG02
+#undef SB_ONEOF_PCIEMEMRSVDALIG02
+#define SB_ONEOF_PCIEMEMRSVDALIG02\
+  numeric varid  = SETUP_DATA.PcieMemRsvdalig[OFFSET_2],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 26,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD02
+#undef SB_ONEOF_PCIEPFMEMRSVD02
+#define SB_ONEOF_PCIEPFMEMRSVD02\
+  numeric varid  = SETUP_DATA.PciePFMemRsvd[OFFSET_2],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG02
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG02
+#define SB_ONEOF_PCIEPFMEMRSVDALIG02\
+  numeric varid  = SETUP_DATA.PciePFMemRsvdalig[OFFSET_2],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 28,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD02
+#undef SB_ONEOF_PCIEIORSVD02
+#define SB_ONEOF_PCIEIORSVD02\
+  numeric varid  = SETUP_DATA.PcieIoRsvd[OFFSET_2],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_IO_RESERVED,\
+    step         = 4,\
+    default      = TBT_DEFAULT_PCIE_IO_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // IO resource
+#endif //TBT_UP_PORT_FUNC == 2
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 3)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE3
+#undef SB_ONEOF_PCIEROOTPORTHPE03
+#define SB_ONEOF_PCIEROOTPORTHPE03\
+  oneof varid    = SETUP_DATA.PcieRootPortHPE[OFFSET_3],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD03
+#undef SB_ONEOF_EXTRABUSRSVD03
+#define SB_ONEOF_EXTRABUSRSVD03\
+  numeric varid  = SETUP_DATA.ExtraBusRsvd[OFFSET_3],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_EXTRA_BUS_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD03
+#undef SB_ONEOF_PCIEMEMRSVD03
+#define SB_ONEOF_PCIEMEMRSVD03\
+  numeric varid  = SETUP_DATA.PcieMemRsvd[OFFSET_3],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG03
+#undef SB_ONEOF_PCIEMEMRSVDALIG03
+#define SB_ONEOF_PCIEMEMRSVDALIG03\
+  numeric varid  = SETUP_DATA.PcieMemRsvdalig[OFFSET_3],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 26,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD03
+#undef SB_ONEOF_PCIEPFMEMRSVD03
+#define SB_ONEOF_PCIEPFMEMRSVD03\
+  numeric varid  = SETUP_DATA.PciePFMemRsvd[OFFSET_3],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_103
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG03
+#define SB_ONEOF_PCIEPFMEMRSVDALIG03\
+  numeric varid  = SETUP_DATA.PciePFMemRsvdalig[OFFSET_3],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 28,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD03
+#undef SB_ONEOF_PCIEIORSVD03
+#define SB_ONEOF_PCIEIORSVD03\
+  numeric varid  = SETUP_DATA.PcieIoRsvd[OFFSET_3],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_IO_RESERVED,\
+    step         = 4,\
+    default      = TBT_DEFAULT_PCIE_IO_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // IO resource
+#endif //TBT_UP_PORT_FUNC == 3
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 4)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE04
+#undef SB_ONEOF_PCIEROOTPORTHPE04
+#define SB_ONEOF_PCIEROOTPORTHPE04\
+  oneof varid    = SETUP_DATA.PcieRootPortHPE[OFFSET_4],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD04
+#undef SB_ONEOF_EXTRABUSRSVD04
+#define SB_ONEOF_EXTRABUSRSVD04\
+  numeric varid  = SETUP_DATA.ExtraBusRsvd[OFFSET_4],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_EXTRA_BUS_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD04
+#undef SB_ONEOF_PCIEMEMRSVD04
+#define SB_ONEOF_PCIEMEMRSVD04\
+  numeric varid  = SETUP_DATA.PcieMemRsvd[OFFSET_4],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG04
+#undef SB_ONEOF_PCIEMEMRSVDALIG04
+#define SB_ONEOF_PCIEMEMRSVDALIG04\
+  numeric varid  = SETUP_DATA.PcieMemRsvdalig[OFFSET_4],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 26,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD04
+#undef SB_ONEOF_PCIEPFMEMRSVD04
+#define SB_ONEOF_PCIEPFMEMRSVD04\
+  numeric varid  = SETUP_DATA.PciePFMemRsvd[OFFSET_4],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG04
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG04
+#define SB_ONEOF_PCIEPFMEMRSVDALIG04\
+  numeric varid  = SETUP_DATA.PciePFMemRsvdalig[OFFSET_4],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 28,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD04
+#undef SB_ONEOF_PCIEIORSVD04
+#define SB_ONEOF_PCIEIORSVD04\
+  numeric varid  = SETUP_DATA.PcieIoRsvd[OFFSET_4],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_IO_RESERVED,\
+    step         = 4,\
+    default      = TBT_DEFAULT_PCIE_IO_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // IO resource
+
+#if !defined (ULT_SUPPORT) || (ULT_SUPPORT == 0)
+#ifdef SB_ONEOF_PCIEROOTPORTEN05
+#undef SB_ONEOF_PCIEROOTPORTEN05
+#define SB_ONEOF_PCIEROOTPORTEN05\
+  oneof varid    = SETUP_DATA.PcieRootPortEn[OFFSET_5],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIERP6_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif // PCIE root port5 disable
+#endif
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN06
+#undef SB_ONEOF_PCIEROOTPORTEN06
+#define SB_ONEOF_PCIEROOTPORTEN06\
+  oneof varid    = SETUP_DATA.PcieRootPortEn[OFFSET_6],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIERP7_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif // PCIE root port6 disable
+
+#ifdef SB_ONEOF_PCIEROOTPORTEN07
+#undef SB_ONEOF_PCIEROOTPORTEN07
+#define SB_ONEOF_PCIEROOTPORTEN07\
+  oneof varid    = SETUP_DATA.PcieRootPortEn[OFFSET_7],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIERP8_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIERP_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif // PCIE root port7 disable
+#endif //TBT_UP_PORT_FUNC == 4
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 5) && (ULT_SUPPORT == 1)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE05
+#undef SB_ONEOF_PCIEROOTPORTHPE05
+#define SB_ONEOF_PCIEROOTPORTHPE05\
+  oneof varid    = SETUP_DATA.PcieRootPortHPE[OFFSET_5],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD05
+#undef SB_ONEOF_EXTRABUSRSVD05
+#define SB_ONEOF_EXTRABUSRSVD05\
+  numeric varid  = SETUP_DATA.ExtraBusRsvd[OFFSET_5],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_EXTRA_BUS_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD05
+#undef SB_ONEOF_PCIEMEMRSVD05
+#define SB_ONEOF_PCIEMEMRSVD05\
+  numeric varid  = SETUP_DATA.PcieMemRsvd[OFFSET_5],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG05
+#undef SB_ONEOF_PCIEMEMRSVDALIG05
+#define SB_ONEOF_PCIEMEMRSVDALIG05\
+  numeric varid  = SETUP_DATA.PcieMemRsvdalig[OFFSET_5],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 26,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD05
+#undef SB_ONEOF_PCIEPFMEMRSVD05
+#define SB_ONEOF_PCIEPFMEMRSVD05\
+  numeric varid  = SETUP_DATA.PciePFMemRsvd[OFFSET_5],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG05
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG05
+#define SB_ONEOF_PCIEPFMEMRSVDALIG05\
+  numeric varid  = SETUP_DATA.PciePFMemRsvdalig[OFFSET_5],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 28,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD05
+#undef SB_ONEOF_PCIEIORSVD05
+#define SB_ONEOF_PCIEIORSVD05\
+  numeric varid  = SETUP_DATA.PcieIoRsvd[OFFSET_5],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_IO_RESERVED,\
+    step         = 4,\
+    default      = TBT_DEFAULT_PCIE_IO_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // IO resource
+#endif // TBT_UP_PORT_FUNC == 5
+
+#if defined (TBT_UP_PORT_FUNC) && (TBT_UP_PORT_FUNC == 6)
+#ifdef SB_ONEOF_PCIEROOTPORTHPE06
+#undef SB_ONEOF_PCIEROOTPORTHPE06
+#define SB_ONEOF_PCIEROOTPORTHPE06\
+  oneof varid    = SETUP_DATA.PcieRootPortHPE[OFFSET_6],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\
+    option text  = STRING_TOKEN (STR_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\
+    option text  = STRING_TOKEN (STR_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\
+  endoneof;
+#endif
+
+#ifdef SB_ONEOF_EXTRABUSRSVD06
+#undef SB_ONEOF_EXTRABUSRSVD06
+#define SB_ONEOF_EXTRABUSRSVD06\
+  numeric varid  = SETUP_DATA.ExtraBusRsvd[OFFSET_6],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_EXTRA_BUS_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_EXTRA_BUS_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved bus
+
+#ifdef SB_ONEOF_PCIEMEMRSVD06
+#undef SB_ONEOF_PCIEMEMRSVD06
+#define SB_ONEOF_PCIEMEMRSVD06\
+  numeric varid  = SETUP_DATA.PcieMemRsvd[OFFSET_6],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory
+
+#ifdef SB_ONEOF_PCIEMEMRSVDALIG06
+#undef SB_ONEOF_PCIEMEMRSVDALIG06
+#define SB_ONEOF_PCIEMEMRSVDALIG06\
+  numeric varid  = SETUP_DATA.PcieMemRsvdalig[OFFSET_6],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 26,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \
+  endnumeric;
+#endif //Reserved memory alignment
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVD06
+#undef SB_ONEOF_PCIEPFMEMRSVD06
+#define SB_ONEOF_PCIEPFMEMRSVD06\
+  numeric varid  = SETUP_DATA.PciePFMemRsvd[OFFSET_6],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_PF_MEM_RESERVED,\
+    step         = 1,\
+    default      = TBT_DEFAULT_PCIE_PF_MEM_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory
+
+#ifdef SB_ONEOF_PCIEPFMEMRSVDALIG06
+#undef SB_ONEOF_PCIEPFMEMRSVDALIG06
+#define SB_ONEOF_PCIEPFMEMRSVDALIG06\
+  numeric varid  = SETUP_DATA.PciePFMemRsvdalig[OFFSET_6],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 1,\
+    maximum      = 31,\
+    step         = 1,\
+    default      = 28,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // Prefetchable memory alignment
+
+#ifdef SB_ONEOF_PCIEIORSVD06
+#undef SB_ONEOF_PCIEIORSVD06
+#define SB_ONEOF_PCIEIORSVD06\
+  numeric varid  = SETUP_DATA.PcieIoRsvd[OFFSET_6],\
+    prompt       = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\
+    help         = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\
+    flags        = RESET_REQUIRED,\
+    minimum      = 0,\
+    maximum      = TBT_MAX_PCIE_IO_RESERVED,\
+    step         = 4,\
+    default      = TBT_DEFAULT_PCIE_IO_RESERVED,\
+    option text  = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \
+  endnumeric;
+#endif // IO resource
+#endif //TBT_UP_PORT_FUNC == 6
+
+#endif // TBT_INTEL_RC_CONFIG == 1
+
+#endif // CONTROL_DEFINITION
+//---------------------------------------------------------------------------
+
+//---------------------------------------------------------------------------
+#ifdef CONTROLS_WITH_DEFAULTS
+    TBT_ONEOF_TBTENABLE
+    TBT_ONEOF_TBTWAKEUPSUPPORT
+    TBT_ONEOF_TBTAICSUPPORT
+    TBT_ONEOF_TBTHOSTLOCATION
+    TBT_ONEOF_TBTHANDLEPOC
+    TBT_ONEOF_TBTCACHELINESIZE
+    TBT_ONEOF_TBTCRSECURITYLEVEL
+    TBT_ONEOF_TBTRRSECURITYLEVEL
+    TBT_ONEOF_SMINOTIFYENABLED
+    TBT_ONEOF_SWSMIENABLED
+    TBT_ONEOF_NOTIFYENABLED
+    TBT_ONEOF_RMVRETRUNVALUE
+    TBT_ONEOF_OPTIONROM
+    TBT_ONEOF_TBTWAKEUPDELAY
+    TBT_ONEOF_TBTSWSMIDELAY
+    TBT_ONEOF_PERSLOTMEMRSVD
+    TBT_ONEOF_PERSLOTPFMEMRSVD
+    TBT_ONEOF_PERSLOTIORSVD
+    TBT_ONEOF_IORESOURCEENABLED
+    TBT_ONEOF_NVMVERSION
+#endif // CONTROLS_WITH_DEFAULTS
+//---------------------------------------------------------------------------
+
+
+//**********************************************************************
+//                  Advanced - TBT Configuration Form
+//**********************************************************************
+
+#ifdef ADVANCED_FORM_SET
+
+#ifdef FORM_SET_TYPEDEF
+  #include <TbtSetup.h>
+#endif
+
+#ifndef SUPPRESS_GRAYOUT_ENDIF //old Core
+  #define SUPPRESS_GRAYOUT_ENDIF endif;
+#endif
+
+#ifdef FORM_SET_GOTO
+// Define goto commands for the forms defined in this file
+    goto TBT_FORM_ID,
+    prompt  = STRING_TOKEN(STR_TBT_FORM),
+    help    = STRING_TOKEN(STR_TBT_FORM_HELP);
+#endif
+
+#ifdef FORM_SET_FORM
+// Define forms
+
+    #ifndef TBT_FORM_SETUP
+    #define TBT_FORM_SETUP
+
+    form formid = AUTO_ID(TBT_FORM_ID),
+        title       = STRING_TOKEN(STR_TBT_FORM);
+
+        SUBTITLE(STRING_TOKEN (STR_TBT_SUBTITLE))
+
+        text 
+            help    = STRING_TOKEN (STR_TBT_SPEC_VERSION_HELP),
+            text    = STRING_TOKEN (STR_TBT_SPEC_VERSION_NAME),
+            text    = STRING_TOKEN (STR_TBT_SPEC_VERSION_VALUE),
+            flags   = 0, key = 0;
+
+        text 
+            help    = STRING_TOKEN (STR_TBT_RC_VERSION_HELP),
+            text    = STRING_TOKEN (STR_TBT_RC_VERSION_NAME),
+            text    = STRING_TOKEN (STR_TBT_RC_VERSION_VALUE),
+            flags   = 0, key = 0;
+
+        suppressif ideqval SETUP_DATA.TbtEnable == 0x0;
+            text 
+                help    = STRING_TOKEN (STR_TBT_HOST_HELP),
+                text    = STRING_TOKEN (STR_TBT_HOST_NAME),
+                text    = STRING_TOKEN (STR_TBT_HOST_VALUE),
+                flags   = 0, key = 0;
+        endif;
+
+        SEPARATOR
+
+        grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER;
+            TBT_ONEOF_TBTENABLE
+            suppressif ideqval SETUP_DATA.TbtEnable == 0x0;
+                suppressif ideqval SETUP_DATA.TbtHRSeries == 0x1;
+                    TBT_ONEOF_TBTRRSECURITYLEVEL
+                endif;
+                suppressif NOT ideqval SETUP_DATA.TbtHRSeries == 0x1; // if TBT chip is not equal CR, hide CR setting.
+                    TBT_ONEOF_TBTCRSECURITYLEVEL
+                endif;
+                suppressif ideqval SETUP_DATA.TbtSecurityLevel == 0x5;
+                    TBT_ONEOF_TBTWAKEUPSUPPORT
+                    suppressif ideqval SETUP_DATA.TbtHRSeries == 0x1;
+                        TBT_ONEOF_TBTAICSUPPORT
+                        suppressif ideqval SETUP_DATA.TbtAICSupport == 0x0;
+                            TBT_ONEOF_TBTHOSTLOCATION
+                        endif;
+                    endif;
+                #if defined (TBT_HR_PWR) && (TBT_HR_PWR != 0xFF)
+                    suppressif ideqval SETUP_DATA.TbtWakeupSupport == 0x1;
+                        TBT_ONEOF_TBTHANDLEPOC
+                    endif;
+                #endif
+                    TBT_ONEOF_TBTCACHELINESIZE
+                    TBT_ONEOF_SMINOTIFYENABLED
+                    suppressif ideqval SETUP_DATA.SmiNotifyEnabled == 0x0;
+                        TBT_ONEOF_SWSMIENABLED
+                        TBT_ONEOF_NOTIFYENABLED
+                    endif;
+                    TBT_ONEOF_RMVRETRUNVALUE
+                    TBT_ONEOF_OPTIONROM
+                    suppressif NOT ideqval SETUP_DATA.TbtHRSeries == 0x1;
+                        TBT_ONEOF_TBTWAKEUPDELAY
+                    endif;
+                    TBT_ONEOF_TBTSWSMIDELAY
+                    TBT_ONEOF_IORESOURCEENABLED
+                    TBT_ONEOF_PERSLOTMEMRSVD
+                    TBT_ONEOF_PERSLOTPFMEMRSVD
+                    suppressif ideqval SETUP_DATA.TbtIOresourceEnable ==0x0;
+                        TBT_ONEOF_PERSLOTIORSVD
+                    #if defined (TBT_FCTP) && (TBT_FCTP == 1)
+                        suppressif NOT ideqval SETUP_DATA.TbtHRSeries == 0x1;
+                            TBT_ONEOF_NVMVERSION
+                        endif;
+                    #else
+                    #endif
+                    endif; // TbtIOresourceEnable ==0x0;
+                endif; // SETUP_DATA.TbtSecurityLevel == 0x5
+            endif; // TbtEnable ==0x0;
+        endif; // SYSTEM_PASSWORD_USER
+    endform; // TBT_FORM_ID
+#endif // TBT_FORM_SETUP
+#endif // FORM_SET_FORM
+
+#endif // ADVANCED_FORM_SET
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl
new file mode 100644
index 0000000..5752562
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl
@@ -0,0 +1,386 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl 9     5/19/14 7:40a Barretlin $
+#
+# $Revision: 9 $
+#
+# $Date: 5/19/14 7:40a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.sdl $
+# 
+# 9     5/19/14 7:40a Barretlin
+# [TAG]  		EIP165410
+# [Category]  	Improvement
+# [Description]  	Support Thunderbolt AIC at NB PCIE slot
+# [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+# TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+# TbtSetupReset.c
+# 
+# 8     5/19/14 7:19a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Using setup item choose return value of _RMV method in
+# ASL code
+# [Files]  		TbtDxe.c TbtGpe.asl TbtOemBoard.c TbtOemBoard.h TbtSetup.sd
+# TbtSetup.sdl TbtSetup.uni
+# 
+# 7     2/10/14 1:30p Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	remove useless policy item and setup item
+# [Files]  		TbtOemBoard.h TbtOemBoard.c TbSetup.sdl TbtSetup.sd
+# TbtSetup.uni TbtSmm.c
+# 
+# 6     1/05/14 2:13p Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	New Feature
+# [Description]  	Support Thunderbolt feature Enable/Disable in run time
+# Support dynamic Thunderbolt AIC location in run time
+# [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni TbtSetupReset.c
+# 
+# 5     6/17/13 4:25a Barretlin
+# [TAG]  		EIP126581
+# [Category]  	Improvement
+# [Description]  	add new AIC support setup item and change
+# TBWakeupSupport name
+# [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+# 
+# 4     5/06/13 12:06a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Fix clone ACPI setup item fail
+# [Files]  		TbtSetup.sdl
+# 
+# 3     3/21/13 6:00a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Clone PCIE prot swap setup item and set disable by
+# default
+# [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+# 
+# 2     1/10/13 5:11a Barretlin
+# 
+# 1     1/10/13 4:57a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 11    12/12/12 4:47a Barretlin
+# [TAG]  		None
+# [Category]  	New Feature
+# [Description]  	Add Thunderbolt TSE Setup Reset Hook
+# [Files]  		TbtSetup.sdl TbtSetup.mak TbtSetup.cif TbtSetupReset.c
+# 
+# 10    10/27/12 6:16a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Create new setup item for thunderbolt POC handling
+# [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+# 
+# 9     8/20/12 5:16a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Fix IO resource workaround broken in 4C 2port case
+# [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+# TbtSetup.sd TbtSetup.uni
+# 
+# 8     8/17/12 8:53a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Add IO resource workaround for Thunderbolt Spec1.1
+# Because new spec has removed IO resource for Thunderbolt device
+# [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+# TbtSetup.sd TbtSetup.uni
+# 
+# 7     7/31/12 3:28a Barretlin
+# [TAG]  		EIP91119
+# [Category]  	Improvement
+# [Description]  	Resolution for enable/disable Thunderbolt device option
+# rom at POST time
+# [Files]  		TbtDxe.c TbtOemBoard.c TbtOemBoard.h TbtOemBoard.sdl
+# TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+# 
+# 6     5/22/12 10:05a Barretlin
+# [TAG]  		EIP90650
+# [Category]  	Spec Update
+# [Description]  	Specificatoin Update 0.94 - The default value of
+# OPTIONAL workaround for devices that don't support surprise-removal
+# should be disable.
+# [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+# TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+# 
+# 5     5/20/12 10:42p Barretlin
+# [TAG]  		EIP90169
+# [Category]  	Spec Update
+# [Description]  	Specificatoin Update 0.93 - BIOS should stall wake
+# process for approximately 2.5 seconds to ensure
+# completeness of TBT link to all endpoint devices.
+# [Files]  		TbtSetup.sdl
+# 
+# 4     3/05/12 1:11a Barretlin
+# [TAG]  		EIP83266
+# [Category]  	Spec Update
+# [Description]  	Specificatoin Update 0.90
+# [Files]  		TbtSetup.sdl
+# TbtSetup.sd
+# TbtSetup.uni
+# TbtSetup.cif
+# TbtOemBoard.h
+# TbtOemLib.c
+# TbtOemLib.h
+# TbtSmm.c
+# TbtPei..
+# 
+# 2     2/19/12 11:52p Wesleychen
+# Add new setup item "SmiNotifyEnabled".
+# 
+# 1     12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+# 
+#*************************************************************************
+TOKEN
+	Name  = "Tbt_Setup"
+	Value  = "1"
+	Help  = "Main switch to enable Tbt Setup support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_ENABLE"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_TB_WAKE_UP_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_AIC_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_AIC_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_AIC_LOCATION"
+	Value  = "$(TBT_UP_PORT_FUNC) + 0x20"
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_DEV" "!=" "0x1C"
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_AIC_LOCATION"
+	Value  = "$(TBT_UP_PORT_FUNC)"
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "TBT_UP_PORT_DEV" "=" "0x1C"
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_HANDLE_POC"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_TB_SMI_NOTIFY_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name = "DEFAULT_TBT_WAK_DELAY"
+	Value = "2500"
+	Help = "The delay time for wakup in ms.\0: Disable\500 = 500ms\1000 = 1 sec"
+	TokenType = Integer
+	TargetH = Yes
+End
+
+
+TOKEN
+	Name  = "DEFAULT_TBT_SWSMI_DELAY"
+	Value  = "0"
+	Help  = "This delay time for TBT SwSMI in ms. \0 = Disable; 1 = 1ms; 1000 = 1sec ..."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_SKIP_TBT_OPTIONROM"
+	Value  = "1"
+	Help  = "Enable:1 / Disable:0  skip Thunderbolt Device Option Rom"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_RMV_RETURN_VALUE"
+	Value  = "0"
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_NVM"
+	Value  = "17"
+	Help  = "Thunderbolt Host Router EEEPROM Version. for IO source workaround using."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEFAULT_TBT_IO_RESOURCE_SUPPORT"
+	Value  = "0"
+	Help  = "Enable:1 / Disable:0 IO resource for Thunderbolt Device"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DISABLE_PCIE_ROOT_PORT_SWAP"
+	Value  = "1"
+	Help  = "Disable Intel RC PCI Express root port swap function."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DISABLE_PCIE_ROOT_PORT_SWAP"
+	Value  = "0"
+	Help  = "Disable Intel RC PCI Express root port swap function."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "TBT_PCIE_PORT_SWAP_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "DISABLE_PCIE_ROOT_PORT_SWAP"
+	Value  = "0"
+	Help  = "Disable Intel RC PCI Express root port swap function. MahoBay platform has no this setup item."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "DESKTOP_306AX" "=" "1"
+End
+
+TOKEN
+	Name  = "DISABLE_PCIE_ROOT_PORT_SWAP"
+	Value  = "0"
+	Help  = "Disable Intel RC PCI Express root port swap function. ChiefRiver platform has no this setup item."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "MOBILE_306AX" "=" "1"
+End
+
+PATH
+	Name  = "TbtSetup_DIR"
+End
+
+MODULE
+	Help  = "Includes TbtSetup.mak to Project"
+	File  = "TbtSetup.mak"
+End
+
+ELINK
+        Name  = "$(BUILD_DIR)\TbtSetup.sdb"
+        Parent  = "SETUP_SDBS"
+        Priority  = 40
+        Help  = "Includes generic TBT setup screens to the project"
+        InvokeOrder = AfterParent
+End
+
+ELINK
+        Name  = "$(TbtSetup_DIR)\TbtSetup.sd"
+        Parent  = "SETUP_DEFINITIONS"
+        Priority  = 40
+        InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/I$(TbtSetup_DIR)"
+	Parent  = "TBT_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name = "-i $(TbtSetup_DIR)"
+	Parent = "SETUP_VFR_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "InitiTbtInfo,"
+	Parent  = "SetupStringInit"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "TbtProcessEnterSetup,"
+	Parent  = "ProcessEnterSetup,"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "TbtSetupResetHook,"
+	Parent  = "PreSystemResetHook,"
+	InvokeOrder = AfterParent
+End
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.uni b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.uni
new file mode 100644
index 0000000..2774c89
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetup.uni
diff --git a/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c
new file mode 100644
index 0000000..c046245
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c
@@ -0,0 +1,243 @@
+//**********************************************************************
+//**********************************************************************
+//**                                                                  **
+//**        (C)Copyright 1985-2010, American Megatrends, Inc.         **
+//**                                                                  **
+//**                       All Rights Reserved.                       **
+//**                                                                  **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093        **
+//**                                                                  **
+//**                       Phone: (770)-246-8600                      **
+//**                                                                  **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c 8     5/19/14 7:40a Barretlin $
+//
+// $Revision: 8 $
+//
+// $Date: 5/19/14 7:40a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtOemBoard/TbtSetup/TbtSetupReset.c $
+// 
+// 8     5/19/14 7:40a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	Improvement
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 7     1/05/14 2:14p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtSetup.sdl TbtSetup.sd TbtSetup.uni TbtSetupReset.c
+// 
+// 6     6/21/13 7:53a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error with non Intel RC project
+// [Files]  		TbtSetupReset.c
+// 
+// 5     6/21/13 5:16a Barretlin
+// [TAG]  		EIPNone
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	can not change Falcon Ridge security level
+// [RootCause]  	can not regconize Falcon Ridge chip
+// [Solution]  	add Falcon Ridge chip
+// [Files]  		TbtSetupReset.c
+// 
+// 4     4/12/13 1:03p Barretlin
+// 
+// 3     4/03/13 2:54a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Double check Security Level between Thunderbolt host FW
+// and BIOS are same or not for Redwood Ridge chip when entering setup
+// page.
+// [Files]  		TbtOemLib.c TbtOemLib.h TbtSetupReset.c
+// 
+// 2     2/06/13 2:25a Barretlin
+// 
+// 1     1/10/13 4:57a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 1     12/12/12 4:40a Barretlin
+// [TAG]  		None
+// [Category]  	New Feature
+// [Description]  	Add Thunderbolt TSE Setup Reset Hook
+// [Files]  		TbtSetupReset.c
+// 
+// 6     1/13/10 2:13p Felixp
+// 
+//**********************************************************************
+//<AMI_FHDR_START>
+//
+// Name:  TbtSetupReset.c
+//
+// Description:	Setup Reset Rountines
+//
+//<AMI_FHDR_END>
+//**********************************************************************
+
+#include <EFI.h>
+#include <Token.h>
+#include <Setup.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <TbtOemLib.h>
+#include <TbtOemBoard.h>
+#if defined(RESET_RUNTIME_SERVICES_SUPPORT) && (RESET_RUNTIME_SERVICES_SUPPORT == 0)
+#include <Protocol\PchReset\PchReset.h>
+#else
+#include <AmiCSPLib.h>
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+#include <PchRegsLpc.h>
+#endif
+#endif
+
+//----------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//----------------------------------------------------------------------------
+static SETUP_DATA        gNewSetupData;
+static SETUP_DATA        gOldSetupData;
+
+//----------------------------------------------------------------------------
+// GUID Definition(s)
+//----------------------------------------------------------------------------
+static EFI_GUID          gEfiSetupGuid    = SETUP_GUID;
+static EFI_GUID          TbtHRStatusGuid  = AMI_TBT_HR_STATUS_GUID;
+
+UINTN                    HRStatusSize     = sizeof(AMI_TBT_HR_STATUS_DATA);
+AMI_TBT_HR_STATUS_DATA   HRStatusData;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:	TbtProcessEnterSetup
+//
+// Description:	This function is a hook called when TSE determines
+//              that it has to load the boot options in the boot
+//              order. This function is available as ELINK.
+//
+// Input:       VOID
+//
+// Output:      VOID
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID TbtProcessEnterSetup(VOID)
+{
+    EFI_STATUS              Status;
+    UINTN                   VariableSize = sizeof (SETUP_DATA);
+    UINT8                   SecurityLevelState;
+    
+    TRACE((-1, "TbtSetupReset.c: TbtProcessEnterSetup().....\n"));
+    Status = pRS->GetVariable(
+                            L"Setup",
+                            &gEfiSetupGuid,
+                            NULL,
+                            &VariableSize,
+                            &gOldSetupData);
+    ASSERT_EFI_ERROR(Status);
+    
+    Status = pRS->GetVariable( L"TbtHRStatusVar", \
+                               &TbtHRStatusGuid, \
+                               NULL, \
+                               &HRStatusSize, \
+                               &HRStatusData );
+    ASSERT_EFI_ERROR(Status);
+
+    //
+    // synchronize Thunderbolt security level config between BIOS and Thunderbolt
+    // host FW
+    if ((gOldSetupData.TbtEnable != 0) && (HRStatusData.TbtHRSeries != Cactus_Ridge)){
+        SecurityLevelState = SynchSecurityLevel(gOldSetupData.TbtSecurityLevel, gOldSetupData.TbtHostLocation);
+        TRACE((-1, "TbtSetupReset: Synchronizing Security Level between host Fw and BIOS state is %x\n", SecurityLevelState));
+    }
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:	TbtSetupResetHook
+//
+// Description:	This function is a hook called after some control 
+//              modified in the setup utility by user. This
+//              function is available as ELINK.
+//
+// Input:       VOID
+//
+// Output:      VOID
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID TbtSetupResetHook(VOID)
+{
+    EFI_STATUS              Status;
+    UINT8                   SetSecurityFlag = 0;
+    UINT8                   ResetFlag = 0;    
+    UINTN                   VariableSize;
+    
+    VariableSize = sizeof (SETUP_DATA);
+    Status = pRS->GetVariable (
+                        L"Setup",
+                        &gEfiSetupGuid,
+                        NULL,
+                        &VariableSize,
+                        &gNewSetupData);
+    ASSERT_EFI_ERROR(Status);
+    
+    if ((!EFI_ERROR (Status)) && (gNewSetupData.TbtEnable != 0) && \
+      (HRStatusData.TbtHRSeries != Cactus_Ridge))
+    {
+        // Check Security Setup Setting first
+        if (gNewSetupData.TbtSecurityLevel != gOldSetupData.TbtSecurityLevel){
+            SetSecurityFlag |= 1;
+        } // Thunderbolt security level changed by user
+
+        // Check Thunderbolt host location 
+        if (gNewSetupData.TbtHostLocation != gOldSetupData.TbtHostLocation){
+            ResetFlag |= 1;
+        }
+
+        // programming Redwood Ridge's/Falcon Ridge's/Win Ridge's Security Level
+        if (SetSecurityFlag != 0){
+            ProgramTbtSecurityLevel(&(gNewSetupData.TbtSecurityLevel), HRStatusData.TbtHRSeries, gNewSetupData.TbtHostLocation, FALSE);
+            ResetFlag |= 1;
+        }
+
+        // Reset system if need
+        if(ResetFlag != 0){
+#if defined(RESET_RUNTIME_SERVICES_SUPPORT) && (RESET_RUNTIME_SERVICES_SUPPORT == 0)
+            pRS->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
+#else
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+            SBLib_ExtResetSystem (SbResetFull);
+#else
+            SBLib_ResetSystem(FullReset);
+#endif
+#endif
+            EFI_DEADLOOP();
+        }
+    } // Get New Setup Data success && Thunderbolt Function is enable
+}
+
+//**********************************************************************
+//**********************************************************************
+//**                                                                  **
+//**        (C)Copyright 1985-2010, American Megatrends, Inc.         **
+//**                                                                  **
+//**                       All Rights Reserved.                       **
+//**                                                                  **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093        **
+//**                                                                  **
+//**                       Phone: (770)-246-8600                      **
+//**                                                                  **
+//**********************************************************************
+//**********************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtPei/TbtPei.c b/Board/EM/Thunderbolt/TbtPei/TbtPei.c
new file mode 100644
index 0000000..37a6614
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtPei/TbtPei.c
@@ -0,0 +1,638 @@
+//**********************************************************************
+//**********************************************************************
+//**                                                                  **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.         **
+//**                                                                  **
+//**                       All Rights Reserved.                       **
+//**                                                                  **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093        **
+//**                                                                  **
+//**                       Phone: (770)-246-8600                      **
+//**                                                                  **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtPei/TbtPei.c 11    5/19/14 7:31a Barretlin $
+//
+// $Revision: 11 $
+//
+// $Date: 5/19/14 7:31a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtPei/TbtPei.c $
+// 
+// 11    5/19/14 7:31a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 10    1/06/14 5:21a Barretlin
+// 
+// 9     1/05/14 1:30p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtPei.c
+// 
+// 8     7/26/13 1:50a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error at MahoBay/ChiefRiver platform
+// [Files]  		TbtPei.c TbtOemBoard.h
+// 
+// 7     6/20/13 2:15a Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Follow Thunderbolt RR/FR BIOS Spec rev 1.0 to set PCH
+// PM_CFG register for Add-in Card
+// [Files]  		TbtPei.c
+// 
+// 6     6/17/13 4:36a Barretlin
+// [TAG]  		EIP None
+// [Category]  	Improvement
+// [Description]  	change TBWakeupSupport name
+// [Files]  		TbtPei.c
+// 
+// 5     5/27/13 7:27a Barretlin
+// [TAG]  		EIP124914
+// [Category]  	New Feature
+// [Description]  	Support Falcon Ridge chip
+// [Files]  		TbtPei.c
+// 
+// 4     4/24/13 2:30a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Using token to decide execute Sx_Exit command of RR
+// chip in S5 boot path
+// [Files]  		TbtPei.c TbtOemBoard.sdl
+// 
+// 3     4/12/13 12:51p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix security level of CR chip not be programming in
+// some case
+// [Files]  		TbtPei.c
+// 
+// 2     2/06/13 1:46a Barretlin
+// [TAG]  		EIP114556
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Change fast link bring-up flow for Thunderbolt RR
+// Spec0.9
+// [Files]  		TbtPei.c
+// 
+// 1     1/10/13 4:55a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 7     12/12/12 2:40a Barretlin
+// [TAG]  		EIP108272
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update to Spec. 1.4 to support Redwood Ridge chip
+// [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 6     10/28/12 11:41p Barretlin
+// [TAG]  		EIP104870
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files]  		TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// 
+// 5     10/04/12 10:35p Barretlin
+// [TAG]  		EIP102947
+// [Category]  	Spec Update
+// [Severity]  	Normal
+// [Description]  	Update Thunderbolt Spec to Rev 1.2
+// [Files]  		TbtPei.c TbtOemLib.c TbtOemLib.h
+// 
+// 4     10/03/12 9:06p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change Programming security level timing for saving
+// boot time
+// [Files]  		TbtPei.c TbtDxe.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtOemLib.c TbtOemLib.h
+// 
+// 3     4/14/12 4:26a Barretlin
+// [TAG]                      None
+// [Category]               Improvement
+// [Description]            Fix Programming error at specification 0.90
+// update
+// [Files]                      TbtPei.c
+// 
+// 2     3/05/12 1:21a Barretlin
+// [TAG]  		EIP83266
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.90
+// [Files]  		TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+// 
+//**********************************************************************
+//<AMI_FHDR_START>
+//
+// Name:  <TbtPei.c>
+//
+// Description:	
+//
+//<AMI_FHDR_END>
+//**********************************************************************
+#include <Token.h>
+#include <Setup.h>
+#include <AmiPeiLib.h>
+#include <AmiCspLib.h>
+#include <TbtOemBoard.h>
+#include <PPI\stall.h>
+#include <ppi\ReadOnlyVariable.h>
+#include <PPI\NBPPI.h>
+
+//----------------------------------------------------------------------------
+// GUID Definition(s)
+//----------------------------------------------------------------------------
+EFI_GUID gEfiPeiReadOnlyVariablePpiGuid = EFI_PEI_READ_ONLY_VARIABLE_PPI_GUID;
+EFI_GUID gTbtHRStatusGuid               = AMI_TBT_HR_STATUS_GUID;
+EFI_GUID gPeiStallPpiGuid               = EFI_PEI_STALL_PPI_GUID;
+EFI_GUID gTbtHobGuid                    = AMI_TBT_HOB_GUID;
+EFI_GUID SetupGuid                      = SETUP_GUID;
+
+//----------------------------------------------------------------------------
+// Function Prototype Definition(s)
+//----------------------------------------------------------------------------
+EFI_STATUS TbtCRSxExitFlow (
+    IN EFI_PEI_SERVICES             **PeiServices);
+
+EFI_STATUS TbtSxExitFlow (
+    IN EFI_PEI_SERVICES             **PeiServices);
+
+EFI_STATUS TbtPeiAfterNbPcieReady(
+    IN EFI_PEI_SERVICES             **PeiServices,
+    IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+    IN VOID                         *InvokePpi );
+
+//----------------------------------------------------------------------------
+// Notified PPI Definition(s)
+//----------------------------------------------------------------------------
+static EFI_PEI_NOTIFY_DESCRIPTOR TbtNotifyList[] = {
+        { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \
+          EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \
+//          &gEfiPeiEndOfPeiPhasePpiGuid, TbtPeiAfterNbPcieReady },
+          &gAmiPeiBeforeMrcGuid, TbtPeiAfterNbPcieReady },
+};
+
+//<AMI_PHDR_START>
+//---------------------------------------------------------------------------
+//
+// Procedure: TbtPeiEntry
+//
+// Description:
+//      This function is the main PEI phase entry point for the Thunderbolt
+//      module.
+//
+// Input:
+//      IN EFI_FFS_FILE_HEADER *FfsHeader
+//                  -- FFS file header pointer
+//      IN EFI_PEI_SERVICES **PeiServices
+//                  -- PEI Services table pointer
+//
+// Output:
+//      EFI_STATUS (Return Value)
+//                  = EFI_SUCCESS if successful
+//                  = or other valid EFI error code
+//
+// Notes:
+//---------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtPeiEntry(
+    IN EFI_FFS_FILE_HEADER        *FfsHeader,
+    IN EFI_PEI_SERVICES           **PeiServices )
+{
+    EFI_STATUS                      Status;
+    UINTN                           VariableSize = sizeof(SETUP_DATA);
+    UINTN                           HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+    SETUP_DATA                      SetupData;
+    EFI_PEI_READ_ONLY_VARIABLE_PPI  *ReadOnlyVariable;
+    EFI_BOOT_MODE                   BootMode;
+    AMI_TBT_HR_STATUS_DATA          HRStatusData;
+    UINT8                           TBus = TBT_UP_PORT_BUS;
+    UINT8                           TDev = TBT_UP_PORT_DEV;
+    UINT8                           TFun = TBT_UP_PORT_FUNC;
+
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "Intel Thunderbolt PEI Entry !!!\n"));
+    Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "BootMode = %X\n", BootMode));
+    if (BootMode > BOOT_ON_S3_RESUME){
+        PEI_TRACE((TRACE_ALWAYS, PeiServices, "Thunderbolt dones't support working with this Boot mode !!!\n"));
+        PEI_TRACE((TRACE_ALWAYS, PeiServices, "Intel Thunderbolt PEI Exit !!!\n"));
+        return EFI_SUCCESS;
+    }
+    
+    // Locate PeiReadOnlyVariable ppi.
+    Status = (*PeiServices)->LocatePpi ( PeiServices, \
+                                         &gEfiPeiReadOnlyVariablePpiGuid, \
+                                         0, \
+                                         NULL, \
+                                         &ReadOnlyVariable);
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Locate PeiReadOnlyVariable Ppi Status = %r\n", Status));
+     
+    Status = ReadOnlyVariable->GetVariable ( PeiServices,
+                                             L"Setup",
+                                             &SetupGuid,
+                                             NULL,
+                                             &VariableSize,
+                                             &SetupData );
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Locate Get Setup ReadOnlyVariable Status = %r\n", Status));
+    
+    if ((!EFI_ERROR(Status)) && (SetupData.TbtEnable == 0)){
+        PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Thunderbolt function is disable in Setup...\n"));
+        PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Skip all action for TBT in PEI phase\n"));
+        PEI_TRACE((TRACE_ALWAYS, PeiServices, "Intel Thunderbolt PEI Exit !!!\n"));
+        return EFI_SUCCESS;
+    }
+
+    // Thunderbolt BIOS Implementation guide for Redwood Ridge/Falcon Ridge/Win Ridge
+    // based devices Specification Update Revision 1.0
+    // 2.1.3.7 PCH configuration for hosts with Add-In Card support
+    // During boot, reboot and wake T218 field (bits [1:0]) of PCH PM_CFG register should
+    // be set to 11b - 10 ms (default value is 0b - 10 us)
+    if ((!EFI_ERROR(Status)) && SetupData.TbtAICSupport){
+        SET_MEM8_RCRB(R_PCH_RCRB_PM_CFG, (BIT00 | BIT01));
+    } // end of setting T218 field
+    
+    // Get Thunderbolt host status variable
+    Status = ReadOnlyVariable->GetVariable ( PeiServices,
+                                             L"TbtHRStatusVar",
+                                             &gTbtHRStatusGuid,
+                                             NULL,
+                                             &HRStatusSize,
+                                             &HRStatusData );
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Locate Get TbtHRStatusVar ReadOnlyVariable Status = %r\n", Status));
+
+    if(!EFI_ERROR(Status)){
+        // For OEM doing anything before Thunderbolt Sx Exit flow
+        TbtBeforeSxExitFlow(PeiServices, HRStatusData.TbtHRSeries);
+
+        // Check Thunderbolt host is at NB PCIE slot or SB PCIE slot
+        if (SetupData.TbtHostLocation >= 0x20){
+            // Thunderbolt host is at NB PCIE root port
+            Status = (*PeiServices)->NotifyPpi( PeiServices, TbtNotifyList );
+            PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Thunderbolt host is at NB PCIE slot, create notify event %r\n", Status));
+            ASSERT_PEI_ERROR(PeiServices, Status);
+            PEI_TRACE((TRACE_ALWAYS, PeiServices, "Intel Thunderbolt PEI Exit !!!\n"));
+            return EFI_SUCCESS;
+        }
+
+        switch(HRStatusData.TbtHRSeries){
+            case Cactus_Ridge:
+                PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Cactus Ridge wake flow ...\n"));
+                Status = TbtCRSxExitFlow(PeiServices);
+                break;
+
+            case Redwood_Ridge:
+            case Falcon_Ridge:
+            case BDW_TBT_LP:
+                PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Redwood Ridge/Falcon Ridge/Win Ridge wake flow ...\n"));
+                Status = TbtSxExitFlow(PeiServices);
+                break;
+        } // end of switch
+        ASSERT_PEI_ERROR(PeiServices, Status);
+    } // end of if
+
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "Intel Thunderbolt PEI Exit !!!\n"));
+    return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtCRSxExitFlow
+//
+// Description: Thunderbolt host Sx Exit Flow for Cactus Ridge chip
+//
+// Input:       EFI_PEI_SERVICES             **PeiServices
+//
+// Output:      EFI_STATUS                   
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtCRSxExitFlow (
+    IN EFI_PEI_SERVICES             **PeiServices)
+{
+    EFI_STATUS                      Status    = EFI_SUCCESS;
+    EFI_PEI_READ_ONLY_VARIABLE_PPI  *ReadOnlyVariable;
+    AMI_TBT_HR_STATUS_DATA          TbtHostInfo;
+    SETUP_DATA                      SetupData;
+    EFI_BOOT_MODE                   BootMode;
+    EFI_PEI_STALL_PPI               *StallPpi = NULL;
+    TBT_HOB                         *tHob;
+    UINTN                           VariableSize = sizeof(SETUP_DATA);
+    UINTN                           HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+    UINTN                           Delay;
+    
+    Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+
+    Status = (*PeiServices)->LocatePpi ( PeiServices, &gEfiPeiReadOnlyVariablePpiGuid,
+                                         0, NULL, &ReadOnlyVariable);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+
+    Status = ReadOnlyVariable->GetVariable ( PeiServices, L"Setup",
+                                             &SetupGuid, NULL,
+                                             &VariableSize, &SetupData);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+    
+    Status = ReadOnlyVariable->GetVariable ( PeiServices, L"TbtHRStatusVar",
+                                             &gTbtHRStatusGuid, NULL,
+                                             &HRStatusSize, &TbtHostInfo);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+    
+    if (TbtHostInfo.TbtHRSeries != Cactus_Ridge) return EFI_INVALID_PARAMETER;
+
+    // Locate Stall Ppi
+    Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiStallPpiGuid, 0, NULL, &StallPpi);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+
+    // For Debug, out put 80 port CP 0x14
+    IoWrite8(0x80, 0x14);
+
+    if (SetupData.TbtWakeupSupport){
+        // BIOS support of Thunderbolt devices Specification Update Revision 0.90
+        // When BIOS decides to wake system the first step that should be
+        // performed is deasserting of GO2Sx pin to wake HR.
+        Status = InactiveTbtGpio2();
+
+        // If remembered HR state was active(system went to sleep status with
+        // attached devices), BIOS should stall wake process for approximately
+        // 2.5 seconds to ensure completeness of TBT link to all endpoint devices.
+        if (TbtHostInfo.TbtHRStatus){
+            PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: HR status is active, delay 2.5 seconds...\n"));
+            Delay = (UINTN)((SetupData.TbtWakeupDelay)*1000);
+            if (Delay != 0) StallPpi->Stall(PeiServices, StallPpi, Delay);
+        }
+
+        if (BootMode <= BOOT_ON_S5_RESUME){
+            Status = (*PeiServices)->CreateHob(PeiServices, EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TBT_HOB), &tHob);
+            if (!EFI_ERROR(Status)){
+                PEI_TRACE((TRACE_ALWAYS,PeiServices,"TbtPei: Create Thunderbolt Hob for Programming Cactus Ridge host Security Level = %x !!!\n", SetupData.TbtSecurityLevel));
+                tHob->Header.Name = gTbtHobGuid;
+                tHob->TbtSecurityLevelFlag = 1;
+            }
+        }
+    } else {
+        // BIOS support of Thunderbolt devices Specification Update Revision 1.2
+        // If system does not support "Wake From Thunderbolt Devices" function and
+        // remembered HR state was active(system went to sleep status with attached devices),
+        // BIOS should:
+        // 1. Pull down GPIO_9__OK2GO2SX_N_OD
+        // 2. Stall wake process for approximately 2.5 seconds to ensure
+        //    completeness of TBT link to all endpoint devices.
+        // 3. Release pull down GPIO_9__OK2GO2SX_N_OD (Make control pin as input)
+        
+        // Power on POC of Thunderbolt host chip
+        if (SetupData.TbtHandlePOC)
+            Status = PowerOnPOC();
+
+        if (TbtHostInfo.TbtHRStatus){
+            // program GPIO_9 as output
+            Status = PullDownTbtGpio9();
+            
+            // delay 2.5 seconds
+            Delay = (UINTN)((SetupData.TbtWakeupDelay)*1000);
+            if (Delay != 0) StallPpi->Stall(PeiServices, StallPpi, Delay);
+            
+            // release GPIO_9
+            Status = ReleaseTbtGpio9();
+        }
+
+        if (BootMode != BOOT_ON_S3_RESUME){
+            Status = (*PeiServices)->CreateHob(PeiServices, EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TBT_HOB), &tHob);
+            if (!EFI_ERROR(Status)){
+                PEI_TRACE((TRACE_ALWAYS,PeiServices,"TbtPei: Create Thunderbolt Hob for Programming Cactus Ridge host Security Level = %x !!!\n", SetupData.TbtSecurityLevel));
+                tHob->Header.Name = gTbtHobGuid;
+                tHob->TbtSecurityLevelFlag = 1;
+            }
+        }
+    }
+
+    // Program Thunderbolt host security level
+    PEI_TRACE((TRACE_ALWAYS,PeiServices,"TbtPei: Start Programming Security Level = %x !!!\n", SetupData.TbtSecurityLevel));
+    ProgramTbtSecurityLevel(&(SetupData.TbtSecurityLevel), TbtHostInfo.TbtHRSeries, TBT_UP_PORT_FUNC, TRUE);
+
+    if ((BootMode == BOOT_ON_S3_RESUME) && (!SetupData.TbtWakeupSupport)){
+        PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: No support wake from thunderbolt and in S3 boot path !!!\n"));
+        // delay 400ms
+        StallPpi->Stall(PeiServices, StallPpi, (450*1000));
+
+        // Finish programming security level
+        PeiFinialProgramTbtSecurityLevel(SetupData.TbtSecurityLevel);
+    }
+
+    return Status;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtSxExitFlow
+//
+// Description: Thunderbolt host Sx Exit Flow for Redwood Ridge, Falcon Ridge
+//              and Win Ridge(BDW-TBT-LP) chips
+//
+// Input:       EFI_PEI_SERVICES             **PeiServices
+//
+// Output:      EFI_STATUS                   
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtSxExitFlow (
+    IN EFI_PEI_SERVICES             **PeiServices)
+{
+    EFI_STATUS                      Status    = EFI_SUCCESS;
+    EFI_PEI_READ_ONLY_VARIABLE_PPI  *ReadOnlyVariable;
+    AMI_TBT_HR_STATUS_DATA          TbtHostInfo;
+    SETUP_DATA                      SetupData;
+    EFI_BOOT_MODE                   BootMode;
+    EFI_PEI_STALL_PPI               *StallPpi = NULL;
+    UINTN                           VariableSize = sizeof(SETUP_DATA);
+    UINTN                           HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+    UINTN                           Delay;
+    UINTN                           Counter;
+    UINT32                          REG_VAL = 0;
+    UINT8                           TBus = TBT_UP_PORT_BUS;
+    UINT8                           TDev = TBT_UP_PORT_DEV;
+    UINT8                           TFun = TBT_UP_PORT_FUNC;
+    
+    Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+
+    Status = (*PeiServices)->LocatePpi ( PeiServices, &gEfiPeiReadOnlyVariablePpiGuid,
+                                         0, NULL, &ReadOnlyVariable);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+
+    Status = ReadOnlyVariable->GetVariable ( PeiServices, L"Setup",
+                                             &SetupGuid, NULL,
+                                             &VariableSize, &SetupData);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+    
+    Status = ReadOnlyVariable->GetVariable ( PeiServices, L"TbtHRStatusVar",
+                                             &gTbtHRStatusGuid, NULL,
+                                             &HRStatusSize, &TbtHostInfo);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+    
+    if (TbtHostInfo.TbtHRSeries == Cactus_Ridge) return EFI_INVALID_PARAMETER;
+
+    // Get Thunderbolt host location
+    if (SetupData.TbtHostLocation < 0x20){
+        // Thunderbolt host is at SB PCIE root port
+        TFun = SetupData.TbtHostLocation;
+    } else {
+        // Thunderbolt host is at NB PCIE root port
+        TDev = 0x01;
+        TFun = SetupData.TbtHostLocation - 0x20;
+    }
+
+    //Assign temp bus
+    WRITE_PCI16(TBus, TDev, TFun, PCI_PBUS+1, 0x0505);
+    // Do a dummy Write
+    WRITE_PCI32(5, 0, 0, PCI_VID, 0x12345678);
+
+#if defined TBT_RR_S5_SXEXIT && TBT_RR_S5_SXEXIT == 1
+    if (TbtHostInfo.TbtHRStatus){
+#else
+    if ((TbtHostInfo.TbtHRStatus) && ((BootMode == BOOT_ON_S3_RESUME) || (BootMode == BOOT_ON_S4_RESUME))){
+#endif
+        PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: HR status is active...\n"));
+
+        // Locate Stall Ppi
+        Status = (*PeiServices)->LocatePpi (PeiServices, &gPeiStallPpiGuid, 0, NULL, &StallPpi);
+        ASSERT_PEI_ERROR(PeiServices, Status);
+
+        // For Debug, out put 80 port CP 0x14
+        IoWrite8(0x80, (TBT_SX_EXIT_TBT_CONNECTED | 0x10));
+
+        if (!(SetupData.TbtWakeupSupport)){
+            // BIOS support of Thunderbolt devices Specification for 
+            // RR Revision 1.0 / FR Revision 1.1 / WR Revision 1.0
+            // 2.2.2.4 Sx exit flow for Hosts without Thunderbolt wake support
+            // If BIOS saved pre-Sx Host Router state as active
+            // (system went to sleep with attached devices),
+            // BIOS should add 500ms delay before proceeding to next step
+            Delay = (UINTN)(550 * 1000);
+            StallPpi->Stall(PeiServices, StallPpi, Delay);
+        }
+        // BIOS support of Thunderbolt devices Specification for 
+        // RR Revision 1.0 / FR Revision 1.1 / WR Revision 1.0
+        // 2.2.2.5 Sx exit flow for Hosts with and without Thunderbolt wake support
+        // Upon wake, if BIOS saved pre-Sx Host Router state as active, BIOS sholud:
+        // 1. Apply "PCIE2TBT <-> TBT2PCIE" handshake procedure with 
+        //    "Sx_Exit_TBT_Connected" command.
+        // 2. If procedure above returns true, BIOS sholud perform 
+        //    "wait for fast link bring-up" loop.
+
+        // Excute command...
+        if (MMIO_READ32(TBT_CFG_ADDRESS(0x05, 0, 0, PCI_RID))!= 0xFFFFFFFF){
+            if (TbtSetPCIe2TBTCommand(0x05, 0, TBT_SX_EXIT_TBT_CONNECTED, 0x8FFFFF)){
+                for(Counter=0;Counter<0x2000;Counter++){
+                    if (MMIO_READ32(TBT_CFG_ADDRESS(5, 0, 0, PCI_VID)) != 0xFFFFFFFF){
+                        break;
+                    }
+                    StallPpi->Stall(PeiServices, StallPpi, 1000);
+                } // for loop
+            } //  end of if
+        } //  end of if
+    } // Host is active
+
+    // Remove temp bus
+    WRITE_PCI32(TBus, TDev, TFun, PCI_PBUS, 0xFF000000);
+
+    return Status;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtPeiAfterNbPcieReady
+//
+// Description: When Thunderbolt host is at NB PCIE slot, we do Sx_Exit flow 
+//              here avoiding chipset limitation
+//
+// Input:       EFI_PEI_SERVICES             **PeiServices
+//              EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor
+//              VOID                         *InvokePpi
+//
+// Output:      EFI_STATUS                   
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS TbtPeiAfterNbPcieReady(
+    IN EFI_PEI_SERVICES             **PeiServices,
+    IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+    IN VOID                         *InvokePpi )
+{
+    EFI_STATUS                      Status    = EFI_SUCCESS;
+    EFI_PEI_READ_ONLY_VARIABLE_PPI  *ReadOnlyVariable;
+    SETUP_DATA                      SetupData;
+    AMI_TBT_HR_STATUS_DATA          TbtHostInfo;
+    UINTN                           VariableSize = sizeof(SETUP_DATA);
+    UINTN                           HRStatusSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+
+    PEI_TRACE((TRACE_ALWAYS,PeiServices, "TbtPeiAfterNbPcieReady Start.\n"));
+
+    Status = (*PeiServices)->LocatePpi ( PeiServices, &gEfiPeiReadOnlyVariablePpiGuid,
+                                         0, NULL, &ReadOnlyVariable);
+    ASSERT_PEI_ERROR(PeiServices, Status);
+
+    Status = ReadOnlyVariable->GetVariable ( PeiServices, L"Setup",
+                                             &SetupGuid, NULL,
+                                             &VariableSize, &SetupData);
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Locate Get Setup ReadOnlyVariable Status = %r\n", Status));
+    
+    Status = ReadOnlyVariable->GetVariable ( PeiServices, L"TbtHRStatusVar",
+                                             &gTbtHRStatusGuid, NULL,
+                                             &HRStatusSize, &TbtHostInfo);
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Locate Get TbtHRStatusVar ReadOnlyVariable Status = %r\n", Status));
+    
+    if(!EFI_ERROR(Status) && (SetupData.TbtHostLocation >= 0x20)){
+        switch(TbtHostInfo.TbtHRSeries){
+            case Cactus_Ridge:
+                PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Cactus Ridge wake flow ...\n"));
+                Status = TbtCRSxExitFlow(PeiServices);
+                break;
+
+            case Redwood_Ridge:
+            case Falcon_Ridge:
+            case BDW_TBT_LP:
+                PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPei: Redwood Ridge/Falcon Ridge/Win Ridge wake flow ...\n"));
+                Status = TbtSxExitFlow(PeiServices);
+                break;
+        } // end of switch
+        ASSERT_PEI_ERROR(PeiServices, Status);
+    }
+
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "TbtPeiAfterNbPcieReady End.\n"));
+    return Status;
+}
+
+//**********************************************************************
+//**********************************************************************
+//**                                                                  **
+//**        (C)Copyright 1985-2012, American Megatrends, Inc.         **
+//**                                                                  **
+//**                       All Rights Reserved.                       **
+//**                                                                  **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093        **
+//**                                                                  **
+//**                       Phone: (770)-246-8600                      **
+//**                                                                  **
+//**********************************************************************
+//**********************************************************************
diff --git a/Board/EM/Thunderbolt/TbtPei/TbtPei.cif b/Board/EM/Thunderbolt/TbtPei/TbtPei.cif
new file mode 100644
index 0000000..8eec4a5
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtPei/TbtPei.cif
@@ -0,0 +1,11 @@
+<component>
+	name = "TbtPei"
+	category = ModulePart
+	LocalRoot = "Board\EM\Thunderbolt\TbtPei\"
+	RefName = "TbtPei"
+[files]
+"TbtPei.sdl"	
+"TbtPei.mak"	
+"TbtPei.c"	
+"TbtPei.dxs"	
+<endComponent>
diff --git a/Board/EM/Thunderbolt/TbtPei/TbtPei.dxs b/Board/EM/Thunderbolt/TbtPei/TbtPei.dxs
new file mode 100644
index 0000000..8edea56
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtPei/TbtPei.dxs
@@ -0,0 +1,66 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtPei/TbtPei.dxs 1     1/10/13 4:55a Barretlin $
+//
+// $Revision: 1 $
+//
+// $Date: 1/10/13 4:55a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtPei/TbtPei.dxs $
+// 
+// 1     1/10/13 4:55a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 2     3/05/12 1:21a Barretlin
+// [TAG]  		EIP83266
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.90
+// [Files]  		TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+// 
+//**********************************************************************
+#include <token.h>
+#include <ppi\CpuIo.h>
+#include <PPI\stall.h>
+#include <ppi\ReadOnlyVariable.h>
+
+DEPENDENCY_START
+  EFI_PEI_CPU_IO_PPI_INSTALLED_GUID AND
+  EFI_PEI_READ_ONLY_VARIABLE_PPI_GUID AND
+  EFI_PEI_STALL_PPI_GUID 
+DEPENDENCY_END
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtPei/TbtPei.mak b/Board/EM/Thunderbolt/TbtPei/TbtPei.mak
new file mode 100644
index 0000000..10ecd1a
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtPei/TbtPei.mak
@@ -0,0 +1,82 @@
+#**********************************************************************
+#**********************************************************************
+#**                                                                  **
+#**        (C)Copyright 1985-2010, American Megatrends, Inc.         **
+#**                                                                  **
+#**                       All Rights Reserved.                       **
+#**                                                                  **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093        **
+#**                                                                  **
+#**                       Phone: (770)-246-8600                      **
+#**                                                                  **
+#**********************************************************************
+#**********************************************************************
+
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtPei/TbtPei.mak 1     1/10/13 4:55a Barretlin $
+#
+# $Revision: 1 $
+#
+# $Date: 1/10/13 4:55a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtPei/TbtPei.mak $
+# 
+# 1     1/10/13 4:55a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 2     3/05/12 1:21a Barretlin
+# [TAG]  		EIP83266
+# [Category]  	Spec Update
+# [Description]  	Specificatoin Update 0.90
+# [Files]  		TbtSetup.sdl
+# TbtSetup.sd
+# TbtSetup.uni
+# TbtSetup.cif
+# TbtOemBoard.h
+# TbtOemLib.c
+# TbtOemLib.h
+# TbtSmm.c
+# TbtPei..
+# 
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name:	TbtPei.mak
+#
+# Description:	
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+all : TbtPei
+
+TbtPei : $(BUILD_DIR)\TbtPei.mak TbtPeiBin
+
+$(BUILD_DIR)\TbtPei.mak : $(TbtPei_DIR)\$(@B).cif $(TbtPei_DIR)\$(@B).mak $(BUILD_RULES)
+	$(CIF2MAK) $(TbtPei_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS)
+
+TbtPeiBin : $(AMICSPLib) $(AMIPEILIB) 
+	$(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+		/f $(BUILD_DIR)\TbtPei.mak all\
+		GUID=1A8E9D96-66E6-461B-95D6-882C984D0B00\
+		ENTRY_POINT=TbtPeiEntry\
+        "MY_INCLUDES=$(TBT_OEMBOARD_INCLUDES)"\
+		TYPE=PEIM \
+		DEPEX1=$(TbtPei_DIR)\TbtPei.dxs \
+		DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \
+		COMPRESS=0\
+#**********************************************************************
+#**********************************************************************
+#**                                                                  **
+#**        (C)Copyright 1985-2010, American Megatrends, Inc.         **
+#**                                                                  **
+#**                       All Rights Reserved.                       **
+#**                                                                  **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093        **
+#**                                                                  **
+#**                       Phone: (770)-246-8600                      **
+#**                                                                  **
+#**********************************************************************
+#**********************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtPei/TbtPei.sdl b/Board/EM/Thunderbolt/TbtPei/TbtPei.sdl
new file mode 100644
index 0000000..4e90aa8
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtPei/TbtPei.sdl
@@ -0,0 +1,35 @@
+TOKEN
+	Name  = TbtPei_SUPPORT
+	Value  = 1
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable TbtPei support in Project"
+End
+
+MODULE
+	Help  = "Includes TbtPei.mak to Project"
+	File  = "TbtPei.mak"
+End
+
+PATH
+	Name  = "TbtPei_DIR"
+End
+
+ELINK
+	Name  = "/I$(TbtPei_DIR)"
+	Parent  = "TBT_PEI_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "TBT_PEI_INCLUDES"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\TbtPei.ffs"
+	Parent  = "FV_BB"
+	InvokeOrder = AfterParent
+End
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtSmm/TbtSmm.c b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.c
new file mode 100644
index 0000000..e60f02f
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.c
@@ -0,0 +1,2992 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2014, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtSmm/TbtSmm.c 22    5/19/14 9:02a Barretlin $
+//
+// $Revision: 22 $
+//
+// $Date: 5/19/14 9:02a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtSmm/TbtSmm.c $
+// 
+// 22    5/19/14 9:02a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix check error with cppcheck tool
+// [Files]  		TbtSmm.c
+// 
+// 21    5/19/14 7:34a Barretlin
+// [TAG]  		EIP165410
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt AIC at NB PCIE slot
+// [Files]  		TbtPei.c TbtDxe.c TbtGpe.asl TbtSmm.c TbtOemBoard.c
+// TbtOemLib.c TbtOemLib.h TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// TbtSetupReset.c
+// 
+// 20    5/19/14 4:40a Barretlin
+// [TAG]  		EIP167031
+// [Category]  	Improvement
+// [Description]  	Variable's attribute needs to be reviewed by
+// Thunderbolt component driver
+// [Files]  		TbtSmm.c
+// 
+// 19    2/19/14 2:57p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	fix TBT host chip information record incorrect in SMM
+// [Files]  		TbtSmm.c
+// 
+// 18    2/18/14 1:13a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	fix build error
+// [Files]  		TbtSmm.c
+// 
+// 17    2/10/14 1:35p Barretlin
+// [TAG]  		EIP152401
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Implement Thunderbolt BIOS additions 1.9
+// [Files]  		TbtSmm.c TbtGpe.asl
+// 
+// 16    2/10/14 12:17p Barretlin
+// [TAG]  		EIP151867
+// [Category]  	Bug Fix
+// [Severity]  	Normal
+// [Symptom]  	Build error when using PI 1.0
+// [RootCause]  	GUID and Protocal do not be defined
+// [Solution]  	Using generic GUID and defining correct protocal when
+// using PI 1.0
+// [Files]  		TbtSmm.c
+// 
+// 15    1/05/14 1:57p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	New Feature
+// [Description]  	Support Thunderbolt feature Enable/Disable in run time
+// Support dynamic Thunderbolt AIC location in run time
+// [Files]  		TbtSmm.c
+// 
+// 14    12/25/13 6:06a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Using token to enable/disable double check TBT host
+// router state in SxSMI/PowerButtonSMI
+// [Files]  		TbtSmm.sdl TbtSmm.c
+// 
+// 13    12/24/13 11:35a Barretlin
+// [TAG]  		EIP148198
+// [Category]  	Spec Update
+// [Severity]  	Normal
+// [Description]  	Updating for Thunderbolt BIOS additions - rev.1.8
+// [Files]  		TbtSmm.c
+// 
+// 12    12/24/13 11:25a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix thunderbolt device enumerating fail when
+// TBT_PCIBUS_SKIP is disable
+// [Files]  		TbtSmm.c
+// 
+// 11    6/21/13 7:42a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix build error with non Intel RC project
+// [Files]  		TbtSmm.c
+// 
+// 10    6/20/13 3:38a Barretlin
+// [TAG]  		EIP None
+// [Category]  	Improvement
+// [Description]  	make sure RR and FR handshake work in sleep smi
+// [Files]  		TbtSmm.c
+// 
+// 9     6/19/13 10:34a Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Follow Thunderbolt RR/FR BIOS Spec rev 1.0 to add Sx
+// entry flow for Add-in Card
+// [Files]  		TbtSmm.c
+// 
+// 8     6/18/13 1:15p Barretlin
+// [TAG]  		EIP None
+// [Category]  	Improvement
+// [Description]  	change TBWakeupSupport name
+// [Files]  		TbtSmm.c
+// 
+// 7     6/16/13 11:05p Barretlin
+// [TAG]  		EIP126581
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update Intel Thunderbolt sample code to rev. 1.7
+// [Files]  		TbtSmm.c
+// 
+// 6     5/27/13 9:04a Barretlin
+// [TAG]  		EIP124914
+// [Category]  	New Feature
+// [Description]  	Support Falcon Ridge chip
+// [Files]  		TbtSmm.c
+// 
+// 5     4/23/13 3:25a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix programming error
+// [Files]  		TbtSmm.c
+// 
+// 4     4/10/13 2:09p Barretlin
+// [TAG]  		EIP120580
+// [Category]  	Spec Update
+// [Severity]  	Minor
+// [Description]  	Update Intel Thunderbolt sample code to rev. 1.6
+// [Files]  		TbtSmm.c
+// 
+// 3     4/02/13 11:41p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	Thunderbolt host driver behavior is incorrect in special
+// case
+// [RootCause]  	Host router state is not updating
+// [Solution]  	Double check Presence Detect State bit on PCIE root port
+// in sleep SMI
+// [Files]  		TbtSmm.c
+// 
+// 2     1/25/13 10:08a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Bug Fix
+// [Severity]  	Critical
+// [Symptom]  	IO resource will be changed by win8
+// [RootCause]  	 OpROM address error when assigning OpROM location to
+// PCIE config register
+// [Solution]  	according device type to fill different OpROM address
+// location
+// [Files]  		TbtSmm.c
+// 
+// 1     1/10/13 4:56a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 30    12/13/12 12:12a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Following Spec remove RR handshake with GO2SX command
+// in power button and Sx callback
+// [Files]  		TbtSmm.c
+// 
+// 29    12/12/12 3:32a Barretlin
+// [TAG]  		EIP None
+// [Category]  	Improvement
+// [Description]  	Workaround for synchronizing cache line size of
+// Thunderbolt
+// [Files]  		TbtSmm.c
+// 
+// 28    12/12/12 3:18a Barretlin
+// [TAG]  		EIP108272
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Update to Spec 1.4 to support Redwood Ridge chip
+// [Files]  		TbtPei.c TbtSmm.c TbtDxe.c TbtDxe.sdl TbtGpe.asl
+// TbtOemBoard.c TbtOemBoard.h TbtOemLib.c TbtOemLib.h
+// 
+// 27    10/28/12 11:44p Barretlin
+// [TAG]  		EIP104870
+// [Category]  	Spec Update
+// [Severity]  	Important
+// [Description]  	Change wake up flow for Spec 1.2 and Spec 1.3
+// [Files]  		TbtPei.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// 
+// 26    10/28/12 10:58p Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change GPIO routing for SharkBay ULT platform
+// [Files]  		TbtDxe.c TbtGpe.asl TbtDxeLib.c TbtDxeLib.h TbtSmm.c
+// 
+// 25    10/27/12 6:29a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Create new setup item for thunderbolt POC handling
+// [Files]  		TbtPei.c TbtSmm.c TbtOemboard.c TbtOemboard.h TbtSetup.sdl
+// TbtSetup.sd Tbtsetup.uni
+// 
+// 24    10/04/12 11:53a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Use global definition for genernic
+// [Files]  		TbtSmm.c TbtSmm.mak
+// 
+// 23    9/22/12 10:49a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change IO resource workaround behavior, docking device
+// is not support in 4C 2ports case.
+// [Files]  		TbtSmm.c
+// 
+// 22    9/06/12 1:34a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	fix programming error
+// [Files]  		TbtSmm.c
+// 
+// 21    9/03/12 6:27a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change driver type and dependence for SharkBay platform
+// [Files]  		TbtSmm.mak TbtSmm.c TbtSmm.dxs
+// 
+// 20    9/01/12 4:20a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix Intel sample code bug
+// [Files]  		TbtSmm.c
+// 
+// 19    8/20/12 5:22a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Fix IO resource workaround broken in 4C 2port case
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+// 
+// 18    8/17/12 9:24a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Add IO resource workaround for Thunderbolt Spec1.1
+// Because new spec has removed IO resource for Thunderbolt device
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h TbtSetup.sdl
+// TbtSetup.sd TbtSetup.uni
+// 
+// 17    8/17/12 9:19a Barretlin
+// [TAG]  		EIP98269
+// [Category]  	Spec Update
+// [Severity]  	Normal
+// [Description]  	Update Thunderbolt specification to version 1.1 and
+// sample code to Rev. 1.4
+// [Files]  		TbtSmm.c
+// 
+// 16    7/31/12 5:42a Barretlin
+// [TAG]  		EIP96350
+// [Category]  	Spec Update
+// [Severity]  	Critical
+// [Description]  	Updated Thunderbolt specification to version 1.00
+// [Files]  		TbtDxe.c TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtOemBoard.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 15    7/24/12 11:50p Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Adding power button event
+// [Files]  		TbtSmm.c
+// 
+// 14    5/29/12 5:23a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Removing registered S1callback function when system
+// entering S1state
+// [Files]  		TbtSmm.c
+// 
+// 13    5/29/12 5:17a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	clean redundancy code in surprise-removal workaround
+// [Files]  		TbtSmm.c
+// 
+// 12    5/22/12 9:54a Barretlin
+// [TAG]  		EIP90650
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.94 - The default value of
+// OPTIONAL workaround for devices that don't support surprise-removal
+// should be disable.
+// 
+// [Files]  		TbtSmm.c TbtOemBoard.c TbtOemBoard.h
+// TbtSetup.sdl TbtSetup.sd TbtSetup.uni
+// 
+// 11    5/21/12 2:25a Barretlin
+// [TAG]  		EIP90003
+// [Category]  	Improvement
+// [Description]  	If TBT devices with option rom enabled, system maybe
+// cannot boot to OS.
+// [Files]  		TbtDxe.c TbtSmm.c TbtOemBoard.sdl
+// 
+// 10    5/10/12 6:40a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Fix Programming error at specification 0.92 update
+// [Files]  		TbtSmm.c
+// 
+// 9     5/07/12 6:40a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Add three setup items for debug
+// [Files]  		TbtDxe.c
+// TbtGpe.asl
+// TbtSmm.c
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtOemBoard.c
+// TbtOemBoard.h
+// 
+// 8     5/06/12 1:47a Barretlin
+// [TAG]  		None
+// [Category]  	Bug Fix
+// [Symptom]  	Thunderbolt function is broken in windows 8 and sometime
+// EP#6 shows yellow  mark in windows device manager
+// [RootCause]  	SCI is signaled incorrectly
+// [Solution]  	enable GPIO routing
+// [Files]  		TbtSmm.c
+// 
+// 7     5/05/12 9:20a Barretlin
+// [TAG]  		EIP89207
+// [Category]  	Spec Update
+// [Description]  	OPTIONAL workaround for devices that don't support
+// surprise-removal
+// [Files]  		TbtSmm.c
+// 
+// 6     4/14/12 4:17a Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	Fix Programming error at specification 0.91 update
+// [Files]  		TbtSmm.c
+// 
+// 5     3/05/12 1:18a Barretlin
+// [TAG]  		EIP83266
+// [Category]  	Spec Update
+// [Description]  	Specificatoin Update 0.90
+// [Files]  		TbtSetup.sdl
+// TbtSetup.sd
+// TbtSetup.uni
+// TbtSetup.cif
+// TbtOemBoard.h
+// TbtOemLib.c
+// TbtOemLib.h
+// TbtSmm.c
+// TbtPei..
+// 
+// 3     2/20/12 4:44a Wesleychen
+// Add new SDL token "TBT_SWSMI_DELAY" for debug.
+// 
+// 2     2/20/12 12:04a Wesleychen
+//  - Add SMMSxDispatch.
+//  - Rewrite ThunderboltSwSmiCallback().
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//*************************************************************************
+#include <Token.h>
+#include <Setup.h>
+#include <AmiDxeLib.h>
+#include <AMICSPLIBInc.h>
+#include <AmiCspLib.h>
+#include <TbtOemBoard.h>
+#if defined TBT_INTEL_RC_CONFIG && TBT_INTEL_RC_CONFIG == 1
+#include <PchAccess.h>
+#endif
+#include <Protocol/Variable.h>
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+#include <Protocol\SmmBase2.h>
+#include <Protocol\SmmSwDispatch2.h>
+#include <Protocol\SmmSxDispatch2.h>
+#include <Protocol\SmmPowerButtonDispatch2.h>
+#else
+#include <Protocol\SmmBase.h>
+#include <Protocol\SmmSwDispatch.h>
+#include <Protocol\SmmSxDispatch.h>
+#include <Protocol\SmmPowerButtonDispatch.h>
+#endif
+
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+#define AMI_SMM_BASE_PROTOCOL                  EFI_SMM_BASE2_PROTOCOL
+#define AMI_SMM_SW_DISPATCH_PROTOCOL           EFI_SMM_SW_DISPATCH2_PROTOCOL
+#define AMI_SMM_SW_DISPATCH_CONTEXT            EFI_SMM_SW_REGISTER_CONTEXT
+#define AMI_SMM_SX_DISPATCH_PROTOCOL           EFI_SMM_SX_DISPATCH2_PROTOCOL
+#define AMI_SMM_SX_DISPATCH_CONTEXT            EFI_SMM_SX_REGISTER_CONTEXT
+#define AMI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL
+#define AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT  EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT
+#define SMM_CHILD_DISPATCH_SUCCESS             EFI_SUCCESS
+#define SMM_CHILD_DISPATCH_TIMEOUT             EFI_TIMEOUT
+#define SMM_CHILD_DISPATCH_NO_MEDIA            EFI_NO_MEDIA
+#define SMM_CHILD_DISPATCH_UNSUPPORTED         EFI_UNSUPPORTED
+#else
+#define AMI_SMM_BASE_PROTOCOL                  EFI_SMM_BASE_PROTOCOL
+#define AMI_SMM_SW_DISPATCH_PROTOCOL           EFI_SMM_SW_DISPATCH_PROTOCOL
+#define AMI_SMM_SW_DISPATCH_CONTEXT            EFI_SMM_SW_DISPATCH_CONTEXT
+#define AMI_SMM_SX_DISPATCH_PROTOCOL           EFI_SMM_SX_DISPATCH_PROTOCOL
+#define AMI_SMM_SX_DISPATCH_CONTEXT            EFI_SMM_SX_DISPATCH_CONTEXT
+#define AMI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL EFI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL
+#define AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT  EFI_SMM_POWER_BUTTON_DISPATCH_CONTEXT
+#define SMM_CHILD_DISPATCH_SUCCESS
+#define SMM_CHILD_DISPATCH_TIMEOUT
+#define SMM_CHILD_DISPATCH_NO_MEDIA
+#define SMM_CHILD_DISPATCH_UNSUPPORTED
+#endif
+
+#ifndef EFI_PCI_CAPABILITY_ID_PMI
+#define EFI_PCI_CAPABILITY_ID_PMI    0x01
+#endif
+
+#ifndef EFI_PCI_CAPABILITY_ID_PCIEXP
+#define EFI_PCI_CAPABILITY_ID_PCIEXP 0x10
+#endif
+
+#ifdef SMI_PROGRESS_CODE
+#undef SMI_PROGRESS_CODE
+#endif
+#define SMI_PROGRESS_CODE(Data)     IoWrite8(0x80, Data)
+
+#define SMM_THUNDERBOLT_CALL        TBT_SWSMI_VALUE
+
+#define MAX_TBT_DEPTH                6
+
+#define P2P_BRIDGE                  (((PCI_CL_BRIDGE) << 8) | (PCI_CL_BRIDGE_SCL_P2P))
+
+#define BAR_ALIGN(v, a)             ((((v) - 1) | (a)) + 1)
+
+#define CMD_BUS_MASTER              BIT2
+#define CMD_BM_IO                   (CMD_BUS_MASTER | BIT0)
+#define CMD_BM_MEM                  (CMD_BUS_MASTER | BIT1)
+#define CMD_BM_MEM_IO               (CMD_BUS_MASTER | BIT1 | BIT0)
+
+//#define DEF_RES_IO_PER_DEV          4    //new setup item
+//#define DEF_RES_MEM_PER_DEV         32   //new setup item
+//#define DEF_RES_PMEM_PER_DEV        32   //new setup item
+#define DOCK_BUSSES                 8
+
+#define DISBL_IO_REG1C              0x01F1
+#define DISBL_MEM32_REG20           0x0000FFF0
+#define DISBL_PMEM_REG24            0x0001FFF1
+
+// Light Ridge HR device ID
+#define LR_HR     0x1513
+// Eagle Ridge HR device IDs
+#define ER_SFF_HR 0x151A
+#define ER_HR     0x151B
+// Cactus Ridge HR device IDs
+#define CR_HR_2C  0x1548
+#define CR_HR_4C  0x1547
+// Redwood Ridge HR device IDs
+#define RR_HR_2C  0x1567
+#define RR_HR_4C  0x1569
+// Falcon Ridge HR device IDs
+#define FR_HR_2C  0x156B
+#define FR_HR_4C  0x156D
+// Win Ridge HR device ID
+#define WR_HR_2C  0x157E
+
+#define count(x)                    (sizeof(x) / sizeof((x)[0]))
+
+//
+// Common Memory mapped Pci access macros -----------------------------------
+//
+#define SmiPciAddress( Segment, Bus, Device, Function, Register ) \
+  ( (UINTN)PCIEX_BASE_ADDRESS + \
+    (UINTN)(Bus << 20) + \
+    (UINTN)(Device << 15) + \
+    (UINTN)(Function << 12) + \
+    (UINTN)(Register) \
+  )
+//
+// UINT32
+//
+#define SmiPci32Ptr( Segment, Bus, Device, Function, Register ) \
+  ( (volatile UINT32 *)SmiPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define SmiPci32( Segment, Bus, Device, Function, Register ) \
+  *SmiPci32Ptr( Segment, Bus, Device, Function, Register )
+
+#define SmiPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
+  SmiPci32( Segment, Bus, Device, Function, Register ) = \
+    (UINT32) ( \
+      SmiPci32( Segment, Bus, Device, Function, Register ) | \
+      (UINT32)(OrData) \
+    )
+
+#define SmiPci32And( Segment, Bus, Device, Function, Register, AndData ) \
+  SmiPci32( Segment, Bus, Device, Function, Register ) = \
+    (UINT32) ( \
+      SmiPci32( Segment, Bus, Device, Function, Register ) & \
+      (UINT32)(AndData) \
+    )
+
+#define SmiPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+  SmiPci32( Segment, Bus, Device, Function, Register ) = \
+    (UINT32) ( \
+      ( SmiPci32( Segment, Bus, Device, Function, Register ) & \
+          (UINT32)(AndData) \
+      ) | \
+      (UINT32)(OrData) \
+    )
+//
+// UINT16
+//
+#define SmiPci16Ptr( Segment, Bus, Device, Function, Register ) \
+  ( (volatile UINT16 *)SmiPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define SmiPci16( Segment, Bus, Device, Function, Register ) \
+  *SmiPci16Ptr( Segment, Bus, Device, Function, Register )
+
+#define SmiPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
+  SmiPci16( Segment, Bus, Device, Function, Register ) = \
+    (UINT16) ( \
+      SmiPci16( Segment, Bus, Device, Function, Register ) | \
+      (UINT16)(OrData) \
+    )
+
+#define SmiPci16And( Segment, Bus, Device, Function, Register, AndData ) \
+  SmiPci16( Segment, Bus, Device, Function, Register ) = \
+    (UINT16) ( \
+      SmiPci16( Segment, Bus, Device, Function, Register ) & \
+      (UINT16)(AndData) \
+    )
+
+#define SmiPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+  SmiPci16( Segment, Bus, Device, Function, Register ) = \
+    (UINT16) ( \
+      ( SmiPci16( Segment, Bus, Device, Function, Register ) & \
+          (UINT16)(AndData) \
+      ) | \
+      (UINT16)(OrData) \
+    )
+//
+// UINT8
+//
+#define SmiPci8Ptr( Segment, Bus, Device, Function, Register ) \
+  ( (volatile UINT8 *)SmiPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define SmiPci8( Segment, Bus, Device, Function, Register ) \
+  *SmiPci8Ptr( Segment, Bus, Device, Function, Register )
+
+#define SmiPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
+  SmiPci8( Segment, Bus, Device, Function, Register ) = \
+    (UINT8) ( \
+      SmiPci8( Segment, Bus, Device, Function, Register ) | \
+      (UINT8)(OrData) \
+    )
+
+#define SmiPci8And( Segment, Bus, Device, Function, Register, AndData ) \
+  SmiPci8( Segment, Bus, Device, Function, Register ) = \
+    (UINT8) ( \
+      SmiPci8( Segment, Bus, Device, Function, Register ) & \
+      (UINT8)(AndData) \
+    )
+
+#define SmiPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+  SmiPci8( Segment, Bus, Device, Function, Register ) = \
+    (UINT8) ( \
+      ( SmiPci8( Segment, Bus, Device, Function, Register ) & \
+          (UINT8)(AndData) \
+        ) | \
+      (UINT8)(OrData) \
+    )
+
+// Type Definition(s)
+
+// Function Prototype(s)
+
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+EFI_SMM_BASE2_PROTOCOL   *gSmmBase2;
+EFI_SMM_SYSTEM_TABLE2    *pSmst2;
+#endif
+
+UINT16  HostDeviceId;
+UINT8   gCacheLineSize;
+UINT8   gTbtBus;
+UINT8   gTbtDev;
+UINT8   gTbtFun;
+UINT16  gReserveMemoryPerSlot;
+UINT16  gReservePMemoryPerSlot;
+UINT8   gReserveIOPerSlot;
+UINT8   gTbtHotPlugEvent;
+UINT8   gTbtNVMversion;
+#if !defined TBT_PCIBUS_SKIP || TBT_PCIBUS_SKIP == 0
+UINT8   IsFirstEnterFlag     = 1;
+#endif
+UINT32  AmiTbtHrStatusAttribute = 0;
+BOOLEAN gTbtEnable           = FALSE;
+BOOLEAN gTbtWakeupSupport    = FALSE;
+BOOLEAN gTbtAICSupport       = FALSE;
+BOOLEAN gTbtHandlePOC        = FALSE;
+BOOLEAN gTbtIOresourceEnable = FALSE;
+
+// GUID Definition(s)
+EFI_GUID  TbtHRStatusGuid    = AMI_TBT_HR_STATUS_GUID;
+
+// Protocol Definition(s)
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//----------------------------------------------------------------------------
+
+#if defined(EFI64) || defined(EFIx64)
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   SmiDivU64x32
+//
+// Description: This routine allows a 64 bit value to be divided with a 32 bit
+//              value returns  64bit result and the Remainder.
+//
+// Input:       UINT64  Dividend
+//              UINT64  Divisor
+//
+// Output:      UINTN   *Remainder OPTIONAL      
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+static UINT64 SmiDivU64x32 (
+    IN UINT64   Dividend,
+    IN UINTN    Divisor,
+    OUT UINTN   *Remainder OPTIONAL
+)
+{
+    UINT64  Result = Dividend/Divisor;
+    if (Remainder) *Remainder=Dividend%Divisor;
+    return Result;
+}
+
+#else
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   SmiDivU64x32
+//
+// Description: This routine allows a 64 bit value to be divided with a 32 bit
+//              value returns 64bit result and the Remainder.
+//
+// Input:       UINT64  Dividend
+//              UINT64  Divisor
+//
+// Output:      UINTN   *Remainder OPTIONAL      
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+static UINT64 SmiDivU64x32 (
+    IN UINT64   Dividend,
+    IN UINTN    Divisor,    //Can only be 31 bits.
+    OUT UINTN   *Remainder OPTIONAL
+)
+{
+    UINT64  Result;
+    UINT32  Rem;
+    _asm
+    {
+        mov     eax, dword ptr Dividend[0]
+        mov     edx, dword ptr Dividend[4]
+        mov     esi, Divisor
+        xor     edi, edi                    ;/// Remainder
+        mov     ecx, 64                     ;/// 64 bits
+Div64_loop:
+        shl     eax, 1                      ;/// Shift dividend left. This clears bit 0.
+        rcl     edx, 1    
+        rcl     edi, 1                      ;/// Shift remainder left. Bit 0 = previous dividend bit 63.
+
+        cmp     edi, esi                    ;/// If Rem >= Divisor, do not adjust
+        cmc                                 ;/// else adjust dividend and subtract divisor.
+        sbb     ebx, ebx                    ;/// if Rem >= Divisor, ebx = 0, else ebx = -1.
+        sub     eax, ebx                    ;/// if adjust, bit 0 of dividend = 1
+        and     ebx, esi                    ;/// if adjust, ebx = Divisor, else ebx = 0. 
+        sub     edi, ebx                    ;/// if adjust, subtract divisor from remainder.
+        loop    Div64_loop
+
+        mov     dword ptr Result[0], eax
+        mov     dword ptr Result[4], edx
+        mov     Rem, edi
+    }
+
+    if (Remainder) *Remainder = Rem;
+
+    return Result;
+}
+
+#endif
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------
+// Procedure:   SmiStall
+//
+// Description: Stalls for the Required Amount of MicroSeconds
+//
+// Parameters:  Usec - UINTN
+//
+// Returns:     None
+//
+//----------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID SmiStall (
+    UINTN   Usec                           
+)
+{
+    UINTN   Counter, i;
+    UINT32  Data32, PrevData;
+    UINTN   Remainder;
+
+    Counter = (UINTN)SmiDivU64x32 ((Usec * 10), 3, &Remainder);
+
+    if (Remainder != 0) {
+        Counter++;
+    }
+
+    //
+    // Call WaitForTick for Counter + 1 ticks to try to guarantee Counter tick
+    // periods, thus attempting to ensure Microseconds of stall time.
+    //
+    if (Counter != 0) {
+
+        PrevData = IoRead32(PM_BASE_ADDRESS + 8);
+        for (i = 0; i < Counter; ) {
+            Data32 = IoRead32(PM_BASE_ADDRESS + 8);    
+            if (Data32 < PrevData) {        // Reset if there is a overlap
+                PrevData=Data32;
+                continue;
+            }
+            i += (Data32 - PrevData);        
+            PrevData = Data32;
+        }
+    }
+    return;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------
+// Procedure:   IsTBTDevice
+//
+// Description: Check device is Thunderbolt device or not
+//
+// Parameters:  UINT16 - DeviceID
+//
+// Returns:     BOOLEAN - TRUE
+//                        FALSE
+//----------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN IsTBTDevice(
+    IN UINT16       DeviceID )
+{
+    switch(DeviceID)
+    {
+    case 0x1513:
+    case 0x151A:
+    case 0x151B:
+    case 0x1547: // Cactus Ridge 4C
+    case 0x1548: // Cactus Ridge 2C
+    case 0x1567: // Redwood Ridge 2C
+    case 0x1569: // Redwood Ridge 4C
+    case 0x156B: // Falcon Ridge 2C
+    case 0x156D: // Falcon Ridge 4C
+        return TRUE;
+    }
+  return FALSE;
+}//IsTBTDevice
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------
+// Procedure:   TbtHotplugPinSciRouting
+//
+// Description: Find the Offset to a given Capabilities 
+//              ID CAPID list:
+//                  0x01 = PCI Power Management Interface
+//                  0x04 = Slot Identification
+//                  0x05 = MSI Capability
+//                  0x10 = PCI Express Capability
+//
+// Parameters:  UINT8 Bus     - Pci Bus Number
+//              UINT8 Dev     - Pci Device Number
+//              UINT8 Fun     - Pci Function Number
+//              UINT8 CapId   - CAPID to search for
+//
+// Returns: UINT8    0        - CAPID not found
+//          UINT8    Other    - CAPID found, Offset of desired CAPID
+//----------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8 PcieFindCapId (
+    IN UINT8    Bus,
+    IN UINT8    Dev,
+    IN UINT8    Fun,
+    IN UINT8    CapId)
+{
+    UINT8 CapHeader;
+    
+    CapHeader = SmiPci8(0x00, Bus, Dev, Fun, 0x34);
+    if (CapHeader == 0xFF) {
+        return 0;
+    }
+    while (CapHeader != 0) {
+        // Bottom 2 bits of the pointers are reserved per PCI Local Bus Spec 2.2
+        CapHeader &= ~(BIT1 | BIT0);
+        
+        // Search for desired CapID
+        if (SmiPci8 (0x00, Bus, Dev, Fun, CapHeader) == CapId) {
+            return CapHeader;
+        }
+        
+        CapHeader = SmiPci8 (0x00, Bus, Dev, Fun, (CapHeader + 1));
+    } // while loop
+    return 0;
+}
+
+BOOLEAN
+IsTBTHostRouter(
+    IN        UINT16  DeviceID
+)
+{
+    switch(DeviceID)
+    {
+	    case LR_HR:
+	    case ER_SFF_HR:
+	    case ER_HR:
+	    case CR_HR_4C:
+	    case CR_HR_2C:
+	    case RR_HR_2C: 
+	    case RR_HR_4C:
+	    case FR_HR_2C:
+	    case FR_HR_4C:
+	    case WR_HR_2C:
+            return TRUE;
+    }
+  return FALSE;
+}//IsTBTHostRouter
+
+typedef struct _PortInfo
+{
+	UINT8      IOBase;
+	UINT8      IOLimit;
+	UINT16     MemBase;
+	UINT16     MemLimit;
+    UINT64     PMemBase64;
+    UINT64     PMemLimit64;
+	UINT8      BusNumLimit;
+	UINT8      ConfedEP;
+} PortInfo;
+
+typedef struct _MEM_REGS
+{
+    UINT32 Base;
+    UINT32 Limit;
+} MEM_REGS;
+
+typedef struct _PMEM_REGS
+{
+    UINT64 Base64;
+    UINT64 Limit64;
+} PMEM_REGS;
+
+typedef struct _IO_REGS
+{
+    UINT16 Base;
+    UINT16 Limit;
+} IO_REGS;
+
+VOID
+PortInfoInit(
+    IN    OUT    PortInfo *pi
+)
+{
+    pi->BusNumLimit = 4;
+}//PortInfoInit
+
+BOOLEAN isLegacyDevice = FALSE;
+
+#define MEM_PER_SLOT  gReserveMemoryPerSlot
+#define PMEM_PER_SLOT gReservePMemoryPerSlot
+
+UINT16
+MemPerSlot(
+	IN		UINT16 currUsage
+)
+{
+	if(currUsage == 0)
+		return 0;
+	
+	if(currUsage <= 16)
+		return 16;
+	if(currUsage <= 64)
+		return 64;
+	if(currUsage <= 128)
+		return 128;
+	if(currUsage <= 256)
+		return 256;
+	if(currUsage <= 512)
+		return 512;
+	if(currUsage <= 1024)
+		return 1024;
+
+	return currUsage;
+}//MemPerSlot
+
+UINT64
+PMemPerSlot(
+	IN		UINT64 currUsage
+)
+{
+	if(currUsage == 0)
+		return 0;
+	
+	if(currUsage <= 1024ULL)
+		return 1024ULL;
+	if(currUsage <= 4096ULL)
+		return 4096ULL;
+
+	return currUsage;
+}//PMemPerSlot
+
+VOID
+SetPHYPortResources(
+    IN        UINT8 Bus, 
+    IN        UINT8 Dev, 
+    IN        UINT8 SubBus, 
+	IN		  INT8  Depth, 
+    IN        PortInfo* CurrentPi,
+    IN    OUT PortInfo* pi
+)
+{
+    UINT8    Cmd = CMD_BUS_MASTER;
+	UINT16	 deltaMEM;
+    UINT64   deltaPMEM;
+	UINT8    deltaIO;
+
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_SUBUS) = SubBus;
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_CMD) = Cmd;
+
+	deltaIO = pi->IOBase - CurrentPi->IOBase;
+	if(Depth >= 0 && gReserveIOPerSlot && deltaIO < gReserveIOPerSlot)
+		pi->IOBase += gReserveIOPerSlot - deltaIO;
+
+    if (pi->IOBase > CurrentPi->IOBase && (pi->IOBase - 0x10) <= pi->IOLimit)
+    {
+        SmiPci8  (0x00, Bus, Dev, 0x00, PCI_IOBASE) = CurrentPi->IOBase;
+        SmiPci8  (0x00, Bus, Dev, 0x00, PCI_IOLIMIT) = pi->IOBase - 0x10;
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_IOBASE_U) = 0x00000000;
+        Cmd |= CMD_BM_IO;
+    }
+    else
+    {
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_IOBASE) = DISBL_IO_REG1C;
+        pi->IOBase = CurrentPi->IOBase;
+    }
+
+	deltaMEM = pi->MemBase - CurrentPi->MemBase;
+
+	if(isLegacyDevice)
+	{
+		if(Depth >= 0 && gReserveMemoryPerSlot && deltaMEM < MEM_PER_SLOT)
+			pi->MemBase += MEM_PER_SLOT - deltaMEM;
+	}
+	else
+	{
+		if(deltaMEM < MemPerSlot(deltaMEM))
+			pi->MemBase += MemPerSlot(deltaMEM) - deltaMEM;
+	}
+
+    if (pi->MemBase > CurrentPi->MemBase && (pi->MemBase - 0x10) <= pi->MemLimit)
+    {
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_MEMBASE) = CurrentPi->MemBase;
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_MEMLIMIT) = pi->MemBase - 0x10;
+        Cmd |= CMD_BM_MEM;
+    }
+    else
+    {
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_MEMBASE) = DISBL_MEM32_REG20;
+        pi->MemBase = CurrentPi->MemBase;
+    }
+
+    deltaPMEM = pi->PMemBase64 - CurrentPi->PMemBase64;
+	if(isLegacyDevice)
+	{
+		if(Depth >= 0 && gReservePMemoryPerSlot && deltaPMEM < PMEM_PER_SLOT)
+			pi->PMemBase64 += PMEM_PER_SLOT - deltaPMEM;
+	}
+	else
+	{
+		if(deltaPMEM < PMemPerSlot(deltaPMEM))
+			pi->PMemBase64 += PMemPerSlot(deltaPMEM) - deltaPMEM;
+	}
+
+    if (pi->PMemBase64 > CurrentPi->PMemBase64 && (pi->PMemBase64 - 0x10) <= pi->PMemLimit64)
+    {
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE) = (UINT16)(CurrentPi->PMemBase64 & 0xFFFF);
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMLIMIT) = (UINT16)((pi->PMemBase64 - 0x10) & 0xFFFF);
+		SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE_U) = (UINT32)(CurrentPi->PMemBase64 >> 16);
+		SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMLIMIT_U) = (UINT32)((pi->PMemBase64 - 0x10) >> 16);
+        Cmd |= CMD_BM_MEM;
+    }
+    else
+    {
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE) = DISBL_PMEM_REG24;
+		SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE_U) = 0;
+		SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMLIMIT_U) = 0;
+        pi->PMemBase64 = CurrentPi->PMemBase64;
+    }
+
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_CMD) = Cmd;
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_CLS) = gCacheLineSize;
+}//SetPHYPortResources
+
+UINT32
+SaveSetGetRestoreBAR(
+    IN        volatile UINT32* BAR
+)
+{
+    UINT32  BarReq;
+    UINT32  OrigBar = *BAR;// Save BAR
+    *BAR = 0xFFFFFFFF;       // Set BAR
+    BarReq = *BAR;           // Get BAR
+    *BAR = OrigBar;           // Restore BAR
+    
+    return BarReq;
+}//SaveSetGetRestoreBAR
+
+VOID
+SetIOBAR(
+    IN        volatile
+            UINT32*  BAR,
+    IN        UINT32   BarReq,
+    IN    OUT    UINT8*   Cmd,
+    IN    OUT    IO_REGS* io_r
+)
+{
+    UINT16 Alignment = ~(BarReq & 0xFFFC);
+    UINT16 Size = Alignment + 1;
+    UINT16 NewBase;
+
+    if(io_r->Base > io_r->Limit || !Size)
+        return;
+
+    NewBase = BAR_ALIGN(io_r->Base, Alignment);
+    if(NewBase > io_r->Limit || NewBase + Size - 1 > io_r->Limit)
+        return;
+
+    *BAR = NewBase; // Set BAR
+    io_r->Base = NewBase + Size; // Advance to new position
+    *Cmd |= CMD_BM_IO; // Set IO Space Enable
+}//SetIOBAR
+
+VOID
+SetMemBAR(
+    IN        volatile 
+            UINT32*   BAR,
+    IN        UINT32    BarReq,
+    IN    OUT    UINT8*    Cmd,
+    IN    OUT    MEM_REGS* mem_r
+)
+{
+    UINT32 Alignment = ~(BarReq & 0xFFFFFFF0);
+    UINT32 Size = Alignment + 1;
+    UINT32 NewBase;
+
+    if(mem_r->Base > mem_r->Limit || !Size)
+        return;
+
+    NewBase = BAR_ALIGN(mem_r->Base, Alignment);
+    if(NewBase > mem_r->Limit || NewBase + Size - 1 > mem_r->Limit)
+        return;
+
+    *BAR = NewBase; // Set BAR
+    mem_r->Base = NewBase + Size; // Advance to new position
+    *Cmd |= CMD_BM_MEM; // Set Memory Space Enable
+}//SetMemBAR
+
+VOID
+SetPMem64BAR(
+    IN        volatile 
+            UINT32*   BAR,
+	IN		BOOLEAN   IsMaxBAR,
+    IN        UINT32    BarReq,
+    IN    OUT    UINT8*    Cmd,
+    IN    OUT    PMEM_REGS* mem_r
+)
+{
+    UINT32 Alignment = ~(BarReq & 0xFFFFFFF0);
+    UINT32 Size = Alignment + 1;
+    UINT64 NewBase;
+
+    if(mem_r->Base64 > mem_r->Limit64 || !Size)
+        return;
+
+    NewBase = BAR_ALIGN(mem_r->Base64, Alignment);
+    if(NewBase > mem_r->Limit64 || NewBase + Size - 1 > mem_r->Limit64)
+        return;
+
+    *BAR = (UINT32)(NewBase & 0xFFFFFFFF); // Set BAR
+	if(!IsMaxBAR)
+	{
+		BAR++;
+		*BAR = (UINT32)(NewBase >> 32); // Set BAR U
+	}
+    mem_r->Base64 = NewBase + Size; // Advance to new position
+    *Cmd |= CMD_BM_MEM; // Set Memory Space Enable
+}//SetPMem64BAR
+
+VOID
+SetDevResources(
+    IN        UINT8      Bus,
+    IN        UINT8      Dev,
+    IN        UINT8      FUNC_MAX, // PCI_MAX_FUNC for devices, 1 for bridge
+    IN        UINT8      BAR_MAX, // PCI_BAR5 for devices, PCI_BAR1 for bridge
+    IN    OUT    PortInfo   *pi
+)
+{
+    UINT8       Fun;
+    UINT8       Reg;
+    UINT8       BCC; //Base Class Code
+    UINT16      VendorID;
+    UINT16      DeviceID;
+    UINT32      BarReq;
+    IO_REGS IO;
+    MEM_REGS Mem;
+    PMEM_REGS PMem;
+
+    IO.Base = pi->IOBase << 8;
+    IO.Limit = (pi->IOLimit << 8) | 0xFF;
+    Mem.Base = pi->MemBase << 16;
+    Mem.Limit = (pi->MemLimit << 16) | 0xFFFF;
+    PMem.Base64 = pi->PMemBase64 << 16;
+    PMem.Limit64 = (pi->PMemLimit64 << 16) | 0xFFFF;
+
+    for (Fun = 0; Fun < FUNC_MAX; ++Fun)
+    {
+        UINT8 Cmd = SmiPci8 (0x00, Bus, Dev, Fun, PCI_CMD) = CMD_BUS_MASTER;
+        BCC      = SmiPci8 (0x00, Bus, Dev, Fun, PCI_BCC);
+        VendorID = SmiPci16 (0x00, Bus, Dev, Fun, PCI_VID);
+        DeviceID = SmiPci16 (0x00, Bus, Dev, Fun, PCI_DID);
+
+        if (0xFFFF == DeviceID)
+            continue;
+
+        for (Reg = PCI_BAR0; Reg <= BAR_MAX; Reg += 4)
+        {
+            BarReq = SaveSetGetRestoreBAR(SmiPci32Ptr (0x00, Bus, Dev, Fun, Reg));// Perform BAR sizing
+
+            if (BarReq & BIT0) // I/O BAR
+            {
+                SetIOBAR(SmiPci32Ptr(0x00, Bus, Dev, Fun, Reg),
+                    BarReq, &Cmd, &IO);
+                continue;
+            }
+
+			if(BarReq & BIT3)// P-Memory BAR
+			{
+				SetPMem64BAR(SmiPci32Ptr(0x00, Bus, Dev, Fun, Reg), BAR_MAX == Reg, BarReq, &Cmd, &PMem);
+			}
+			else
+			{
+				SetMemBAR(SmiPci32Ptr(0x00, Bus, Dev, Fun, Reg), BarReq, &Cmd, &Mem);
+			}
+
+            if (BIT2 == (BarReq & (BIT2 | BIT1))) // Base address is 64 bits wide
+            {
+                Reg += 4;
+                if(!(BarReq & BIT3))// 64-bit memory bar
+                    SmiPci32 (0x00, Bus, Dev, Fun, Reg) = 0; // Allocate from 32 bit space
+            }
+        }
+
+        // Assign ROM BAR
+        if (!(IsTBTDevice(DeviceID) && VendorID == 0x8086)){
+            TRACE((-1, "Start Assign ROM BAR for device....\n"));
+            if (BCC == PCI_CL_BRIDGE)
+                Reg = PCI_P2P_ROM_BAR;
+            else
+                Reg = PCI_DEV_ROM_BAR;
+
+            BarReq = SaveSetGetRestoreBAR(SmiPci32Ptr (0x00, Bus, Dev, Fun, Reg));// Perform BAR sizing
+            SetMemBAR(SmiPci32Ptr(0x00, Bus, Dev, Fun, Reg), BarReq, &Cmd, &Mem);
+            TRACE((-1, "Assign rom bar end....\n"));
+        }
+
+        if(Cmd & BIT1) // If device uses I/O and MEM mapping use only MEM mepping
+            Cmd &= ~BIT0;
+
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_CMD) = Cmd;
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_CLS) = gCacheLineSize;
+    }// Fun < PCI_MAX_FUNC
+    
+    // Update pi if any changes
+    if (IO.Base > ((UINT32)pi->IOBase << 8))
+        pi->IOBase = (UINT8)(BAR_ALIGN(IO.Base, 0xFFF) >> 8);
+
+    if (Mem.Base > ((UINT32)pi->MemBase << 16))
+        pi->MemBase = (UINT16)(BAR_ALIGN(Mem.Base, 0xFFFFF) >> 16);
+
+    if (PMem.Base64 > (pi->PMemBase64 << 16))
+        pi->PMemBase64 = (BAR_ALIGN(PMem.Base64, 0xFFFFF) >> 16);
+}// SetDevResources
+
+typedef struct _DEV_ID
+{
+  UINT8     Bus;
+  UINT8     Dev;
+  UINT8     Fun;
+} DEV_ID;
+
+DEV_ID HR_Slots[] = 
+{
+    {0x00, 0x1C, 0x00},// PCH slot 0
+    {0x00, 0x1C, 0x01},// PCH slot 1
+    {0x00, 0x1C, 0x02},// PCH slot 2
+    {0x00, 0x1C, 0x03},// PCH slot 3
+    {0x00, 0x1C, 0x04},// PCH slot 4
+    {0x00, 0x1C, 0x05},// PCH slot 5
+    {0x00, 0x1C, 0x06},// PCH slot 6
+    {0x00, 0x1C, 0x07},// PCH slot 7
+    {0x00, 0x01, 0x00},// PEG slot
+};
+
+//#define count(x) (sizeof(x) / sizeof((x)[0]))
+
+typedef struct _BRDG_RES_CONFIG
+{
+	UINT8    Cmd;
+	UINT8    Cls;
+	UINT8    IOBase;
+	UINT8    IOLimit;
+	UINT16   MemBase;
+	UINT16   MemLimit;
+    UINT64   PMemBase64;
+    UINT64   PMemLimit64;
+} BRDG_RES_CONFIG;
+
+const
+BRDG_RES_CONFIG NOT_IN_USE_BRIDGE = 
+{
+	CMD_BUS_MASTER,
+	0,
+	DISBL_IO_REG1C & 0xFF,
+	DISBL_IO_REG1C >> 8,
+	DISBL_MEM32_REG20 & 0xFFFF,
+	DISBL_MEM32_REG20 >> 16,
+	DISBL_PMEM_REG24 & 0xFFFF,
+    DISBL_PMEM_REG24 >> 16
+};
+
+typedef struct _BRDG_CONFIG
+{
+    DEV_ID           DevId;
+    UINT8            PBus;
+    UINT8            SBus;
+    UINT8            SubBus;
+    BRDG_RES_CONFIG  Res;
+} BRDG_CONFIG;
+
+enum {
+HR_US_PORT, 
+HR_DS_PORT0,
+HR_DS_PORT3,
+HR_DS_PORT4,
+HR_DS_PORT5,
+HR_DS_PORT6,
+MAX_CFG_PORTS
+};
+
+enum {
+	HR_DS_PORT1 = HR_DS_PORT3
+};
+
+BRDG_CONFIG HRConfigs[MAX_CFG_PORTS];// US(X:0:0), DS(X+1:3:0),DS(X+1:4:0),DS(X+1:5:0),DS(X+1:6:0)
+
+typedef struct _HR_CONFIG
+{
+	UINT16           DeviceId;
+	UINT8            HRBus;
+	UINT8            MinDSNumber;
+	UINT8            MaxDSNumber;
+	UINT8            BridgeLoops;
+} HR_CONFIG;
+
+VOID
+InitCommonHRConfigs(
+    IN        HR_CONFIG *HR_Config,
+    IN        UINT8 BusNumLimit,
+    IN    OUT    BRDG_RES_CONFIG* HRResConf
+)
+{
+    UINT8 i,j;
+    // US(HRBus:0:0)
+    HRConfigs[HR_US_PORT].DevId.Bus = HR_Config->HRBus;
+    HRConfigs[HR_US_PORT].DevId.Dev = 0;
+    HRConfigs[HR_US_PORT].DevId.Fun = 0;
+    HRConfigs[HR_US_PORT].Res = *HRResConf;
+	if (gTbtIOresourceEnable == FALSE){
+	   HRConfigs[HR_US_PORT].Res.IOBase = 0xF1;
+	   HRConfigs[HR_US_PORT].Res.IOLimit = 0x01;
+	}
+    HRConfigs[HR_US_PORT].PBus = HRConfigs[HR_US_PORT].DevId.Bus;
+    HRConfigs[HR_US_PORT].SBus = HRConfigs[HR_US_PORT].PBus + 1;
+    HRConfigs[HR_US_PORT].SubBus = BusNumLimit;
+
+    // NHI resides here
+    HRConfigs[HR_DS_PORT0].DevId.Bus = HRConfigs[HR_US_PORT].DevId.Bus + 1;
+    HRConfigs[HR_DS_PORT0].DevId.Dev = 0;
+    HRConfigs[HR_DS_PORT0].DevId.Fun = 0;
+    HRConfigs[HR_DS_PORT0].Res = NOT_IN_USE_BRIDGE;
+    HRConfigs[HR_DS_PORT0].Res.MemBase = HRResConf->MemLimit;
+    HRConfigs[HR_DS_PORT0].Res.MemLimit = HRResConf->MemLimit;
+    HRResConf->MemLimit -= 0x10; //This 1 MB chunk will be used by NHI
+    HRConfigs[HR_DS_PORT0].Res.Cmd = CMD_BM_MEM;
+    HRConfigs[HR_DS_PORT0].Res.Cls = gCacheLineSize;
+    HRConfigs[HR_DS_PORT0].PBus = HRConfigs[HR_DS_PORT0].DevId.Bus;
+    HRConfigs[HR_DS_PORT0].SBus = HRConfigs[HR_DS_PORT0].PBus + 1;
+    HRConfigs[HR_DS_PORT0].SubBus = HRConfigs[HR_DS_PORT0].PBus + 1;
+
+	switch(HR_Config->DeviceId)
+	{
+		case WR_HR_2C:// HR with 1 DS only
+			HRConfigs[HR_DS_PORT1].DevId.Bus = HRConfigs[HR_US_PORT].DevId.Bus + 1;
+			HRConfigs[HR_DS_PORT1].DevId.Dev = 1;
+			HRConfigs[HR_DS_PORT1].DevId.Fun = 0;
+			HRConfigs[HR_DS_PORT1].Res = *HRResConf;
+			HRConfigs[HR_DS_PORT1].PBus = HRConfigs[HR_DS_PORT1].DevId.Bus;
+			HRConfigs[HR_DS_PORT1].SBus = HRConfigs[HR_DS_PORT0].SubBus + 1;
+			HRConfigs[HR_DS_PORT1].SubBus = BusNumLimit;
+			HR_Config->MinDSNumber = HRConfigs[HR_DS_PORT1].DevId.Dev;
+			HR_Config->MaxDSNumber = HRConfigs[HR_DS_PORT1].DevId.Dev;
+			HR_Config->BridgeLoops = 3;
+			break;
+		default:
+		// DS(HRBus+2:3-6:0)
+		HR_Config->MinDSNumber = 3;
+		HR_Config->MaxDSNumber = 6;
+		HR_Config->BridgeLoops = count(HRConfigs);
+
+		for(j = 2, i = HR_Config->MinDSNumber; j < count(HRConfigs) && i <= HR_Config->MaxDSNumber; ++j, ++i)
+		{
+			HRConfigs[j].DevId.Bus = HRConfigs[HR_US_PORT].DevId.Bus + 1;
+			HRConfigs[j].DevId.Dev = i;
+			HRConfigs[j].DevId.Fun = 0;
+			HRConfigs[j].PBus = HRConfigs[j].DevId.Bus;
+			HRConfigs[j].Res.Cls = gCacheLineSize;
+		}
+	}
+}//InitCommonHRConfigs
+
+VOID
+InitHRDSPort_Disable(
+    IN        UINT8 id,
+    IN    OUT    BRDG_CONFIG* BrdgConf
+)
+{
+    HRConfigs[id].Res = NOT_IN_USE_BRIDGE;
+    HRConfigs[id].SBus = BrdgConf->SBus;
+    HRConfigs[id].SubBus = BrdgConf->SBus;
+
+    BrdgConf->SBus++;
+}//InitHRDSPort_Disable
+
+VOID
+InitHRDSPort_1Port(
+	IN	OUT	BRDG_CONFIG* BrdgConf
+)
+{
+	UINT16 MemBase	= BrdgConf->Res.MemBase & 0xFFF0;
+    UINT64 PMemBase64 = BrdgConf->Res.PMemBase64 & ~0xFULL;
+	UINT8  IOBase   = BrdgConf->Res.IOBase & 0xF0;
+	UINT8  BusRange = BrdgConf->SubBus - BrdgConf->PBus - (MAX_CFG_PORTS - 2); // MAX_CFG_PORTS-1(US)-1(HIA) is num of bridges in HR, on each bridge bus# is incremented
+	BusRange -= DOCK_BUSSES; // Bus range for Dock port
+
+    if (gTbtIOresourceEnable == TRUE)
+	   HRConfigs[HR_DS_PORT3].Res.Cmd = CMD_BM_MEM_IO;
+	else{
+	   HRConfigs[HR_DS_PORT3].Res = NOT_IN_USE_BRIDGE;
+	   HRConfigs[HR_DS_PORT3].Res.Cmd = CMD_BM_MEM;
+    }
+	HRConfigs[HR_DS_PORT3].Res.Cls = gCacheLineSize;
+	HRConfigs[HR_DS_PORT3].Res.MemBase = MemBase;
+	HRConfigs[HR_DS_PORT3].Res.MemLimit = MemBase + 0xE00 - 1;
+    HRConfigs[HR_DS_PORT3].Res.PMemBase64 = PMemBase64;
+    HRConfigs[HR_DS_PORT3].Res.PMemLimit64 = PMemBase64 + 0x1A00 - 1;
+
+	if (gTbtIOresourceEnable == TRUE){
+	   HRConfigs[HR_DS_PORT3].Res.IOBase = IOBase;
+       if ((BrdgConf->Res.IOLimit & 0xF0) < (IOBase + 0x50))
+         HRConfigs[HR_DS_PORT3].Res.IOLimit = BrdgConf->Res.IOLimit & 0xF0;
+       else
+	     HRConfigs[HR_DS_PORT3].Res.IOLimit = IOBase + 0x50;
+	}
+
+	HRConfigs[HR_DS_PORT3].SBus = BrdgConf->SBus;
+	HRConfigs[HR_DS_PORT3].SubBus = BrdgConf->SBus + BusRange;
+
+	BrdgConf->SBus = HRConfigs[HR_DS_PORT3].SubBus + 1;
+
+    if (gTbtIOresourceEnable == TRUE)
+	   HRConfigs[HR_DS_PORT4].Res.Cmd = CMD_BM_MEM_IO;
+	else{
+	   HRConfigs[HR_DS_PORT4].Res = NOT_IN_USE_BRIDGE;
+	   HRConfigs[HR_DS_PORT4].Res.Cmd = CMD_BM_MEM;
+    }
+	HRConfigs[HR_DS_PORT4].Res.Cls = gCacheLineSize;
+	HRConfigs[HR_DS_PORT4].Res.MemBase = MemBase + 0xE00;
+	HRConfigs[HR_DS_PORT4].Res.MemLimit = MemBase + 0x1600 - 1;
+    HRConfigs[HR_DS_PORT4].Res.PMemBase64 = PMemBase64 + 0x1A00;
+    HRConfigs[HR_DS_PORT4].Res.PMemLimit64 = PMemBase64 + 0x2200 - 1;
+
+	if (gTbtIOresourceEnable == TRUE){
+       if (HRConfigs[HR_DS_PORT3].Res.IOLimit == (BrdgConf->Res.IOLimit & 0xF0)){
+	      HRConfigs[HR_DS_PORT4].Res.IOBase = 0xF1;
+	      HRConfigs[HR_DS_PORT4].Res.IOLimit = 0x01;
+       }
+       else{
+	      HRConfigs[HR_DS_PORT4].Res.IOBase = IOBase + 0x60;
+	      HRConfigs[HR_DS_PORT4].Res.IOLimit = BrdgConf->Res.IOLimit & 0xF0;
+       }
+	}
+
+	HRConfigs[HR_DS_PORT4].SBus = BrdgConf->SBus;
+	HRConfigs[HR_DS_PORT4].SubBus = BrdgConf->SBus + DOCK_BUSSES;
+
+	BrdgConf->SBus = HRConfigs[HR_DS_PORT4].SubBus + 1;
+}//InitHRDSPort_1Port
+
+VOID
+InitHRDSPort_2Port(
+	IN	OUT	BRDG_CONFIG* BrdgConf
+)
+{
+	UINT16 MemBase	= BrdgConf->Res.MemBase & 0xFFF0;
+    UINT64 PMemBase64 = BrdgConf->Res.PMemBase64 & ~0xFULL;
+	UINT8  IOBase   = BrdgConf->Res.IOBase & 0xF0;
+	UINT8  BusRange = BrdgConf->SubBus - BrdgConf->PBus - (MAX_CFG_PORTS - 2); // MAX_CFG_PORTS-1(US)-1(HIA) is num of bridges in HR, on each bridge bus# is incremented
+
+	BusRange -= 2 * DOCK_BUSSES; // Bus range for Dock ports
+	// Rest of busses split between ports 3 and 5
+	BusRange /= 2; // Bus range for port 3/5
+
+    if (gTbtIOresourceEnable == TRUE)
+	   HRConfigs[HR_DS_PORT3].Res.Cmd = CMD_BM_MEM_IO;
+	else{
+       HRConfigs[HR_DS_PORT3].Res = NOT_IN_USE_BRIDGE;
+	   HRConfigs[HR_DS_PORT3].Res.Cmd = CMD_BM_MEM;
+    }
+	HRConfigs[HR_DS_PORT3].Res.Cls = gCacheLineSize;
+	HRConfigs[HR_DS_PORT3].Res.MemBase = MemBase;
+	HRConfigs[HR_DS_PORT3].Res.MemLimit = MemBase + 0x1000 - 1;
+    HRConfigs[HR_DS_PORT3].Res.PMemBase64 = PMemBase64;
+    HRConfigs[HR_DS_PORT3].Res.PMemLimit64 = PMemBase64 + 0x2000 - 1;
+
+	if (gTbtIOresourceEnable == TRUE){
+	   HRConfigs[HR_DS_PORT3].Res.IOBase = IOBase;
+       if ((BrdgConf->Res.IOLimit & 0xF0) < (IOBase + 0x50))
+         HRConfigs[HR_DS_PORT3].Res.IOLimit = BrdgConf->Res.IOLimit & 0xF0;
+       else
+	     HRConfigs[HR_DS_PORT3].Res.IOLimit = IOBase + 0x50;
+	}
+
+	HRConfigs[HR_DS_PORT3].SBus = BrdgConf->SBus;
+	HRConfigs[HR_DS_PORT3].SubBus = BrdgConf->SBus + BusRange;
+
+	BrdgConf->SBus = HRConfigs[HR_DS_PORT3].SubBus + 1;
+
+	if (gTbtIOresourceEnable == TRUE)
+	   HRConfigs[HR_DS_PORT4].Res.Cmd = CMD_BM_MEM_IO;
+	else{
+       HRConfigs[HR_DS_PORT4].Res = NOT_IN_USE_BRIDGE;
+	   HRConfigs[HR_DS_PORT4].Res.Cmd = CMD_BM_MEM;
+    }
+	HRConfigs[HR_DS_PORT4].Res.Cls = gCacheLineSize;
+	HRConfigs[HR_DS_PORT4].Res.MemBase = MemBase + 0x1000;
+	HRConfigs[HR_DS_PORT4].Res.MemLimit = MemBase + 0x1800 - 1;
+    HRConfigs[HR_DS_PORT4].Res.PMemBase64 = PMemBase64 + 0x2000;
+    HRConfigs[HR_DS_PORT4].Res.PMemLimit64 = PMemBase64 + 0x2800 - 1;
+
+	if (gTbtIOresourceEnable == TRUE){
+       if (gTbtNVMversion > 14){
+          HRConfigs[HR_DS_PORT4].Res.Cmd     = CMD_BM_MEM;
+	      HRConfigs[HR_DS_PORT4].Res.IOBase  = 0xF1;
+	      HRConfigs[HR_DS_PORT4].Res.IOLimit = 0x01;
+       }
+       else{
+          if (HRConfigs[HR_DS_PORT3].Res.IOLimit == (BrdgConf->Res.IOLimit & 0xF0)){
+             HRConfigs[HR_DS_PORT4].Res.IOBase  = 0xF1;
+	         HRConfigs[HR_DS_PORT4].Res.IOLimit = 0x01;
+          }
+          else{
+             HRConfigs[HR_DS_PORT4].Res.IOBase  = IOBase + 0x60;
+	         HRConfigs[HR_DS_PORT4].Res.IOLimit = BrdgConf->Res.IOLimit & 0xF0;
+          }
+       }
+	}
+
+	HRConfigs[HR_DS_PORT4].SBus = BrdgConf->SBus;
+	HRConfigs[HR_DS_PORT4].SubBus = BrdgConf->SBus + DOCK_BUSSES;
+
+	BrdgConf->SBus = HRConfigs[HR_DS_PORT4].SubBus + 1;
+
+	if (gTbtIOresourceEnable == TRUE)
+	   HRConfigs[HR_DS_PORT5].Res.Cmd = CMD_BM_MEM_IO;
+	else{
+       HRConfigs[HR_DS_PORT5].Res = NOT_IN_USE_BRIDGE;
+	   HRConfigs[HR_DS_PORT5].Res.Cmd = CMD_BM_MEM;
+    }
+	HRConfigs[HR_DS_PORT5].Res.Cls = gCacheLineSize;
+	HRConfigs[HR_DS_PORT5].Res.MemBase = MemBase + 0x1800;
+	HRConfigs[HR_DS_PORT5].Res.MemLimit = MemBase + 0x2600 - 1;
+    HRConfigs[HR_DS_PORT5].Res.PMemBase64 = PMemBase64 + 0x3000;
+    HRConfigs[HR_DS_PORT5].Res.PMemLimit64 = PMemBase64 + 0x4A00 - 1;
+
+	if (gTbtIOresourceEnable == TRUE){
+       if (gTbtNVMversion > 14){
+          if (HRConfigs[HR_DS_PORT3].Res.IOLimit == (BrdgConf->Res.IOLimit & 0xF0)){
+             HRConfigs[HR_DS_PORT5].Res.IOBase  = 0xF1;
+	         HRConfigs[HR_DS_PORT5].Res.IOLimit = 0x01;
+          }
+          else{
+             HRConfigs[HR_DS_PORT5].Res.IOBase  = IOBase + 0x60;
+	         HRConfigs[HR_DS_PORT5].Res.IOLimit = BrdgConf->Res.IOLimit & 0xF0;
+          }
+       }
+       else{
+          HRConfigs[HR_DS_PORT5].Res.Cmd     = CMD_BM_MEM;
+	      HRConfigs[HR_DS_PORT5].Res.IOBase  = 0xF1;
+	      HRConfigs[HR_DS_PORT5].Res.IOLimit = 0x01;
+       }
+	}
+	HRConfigs[HR_DS_PORT5].SBus = BrdgConf->SBus;
+	HRConfigs[HR_DS_PORT5].SubBus = BrdgConf->SBus + BusRange;
+
+	BrdgConf->SBus = HRConfigs[HR_DS_PORT5].SubBus + 1;
+
+	if (gTbtIOresourceEnable == TRUE)
+	   HRConfigs[HR_DS_PORT6].Res.Cmd = CMD_BM_MEM_IO;
+	else{
+       HRConfigs[HR_DS_PORT6].Res = NOT_IN_USE_BRIDGE;
+	   HRConfigs[HR_DS_PORT6].Res.Cmd = CMD_BM_MEM;
+    }
+	HRConfigs[HR_DS_PORT6].Res.Cls = gCacheLineSize;
+	HRConfigs[HR_DS_PORT6].Res.MemBase = MemBase + 0x2600;
+	HRConfigs[HR_DS_PORT6].Res.MemLimit = MemBase + 0x2E00 - 1;
+    HRConfigs[HR_DS_PORT6].Res.PMemBase64 = PMemBase64 + 0x2800;
+    HRConfigs[HR_DS_PORT6].Res.PMemLimit64 = PMemBase64 + 0x3000 - 1;
+	if (gTbtIOresourceEnable == TRUE){
+          HRConfigs[HR_DS_PORT6].Res.Cmd     = CMD_BM_MEM;
+	      HRConfigs[HR_DS_PORT6].Res.IOBase  = 0xF1;
+	      HRConfigs[HR_DS_PORT6].Res.IOLimit = 0x01;
+	}
+	HRConfigs[HR_DS_PORT6].SBus = BrdgConf->SBus;
+	HRConfigs[HR_DS_PORT6].SubBus = BrdgConf->SBus + DOCK_BUSSES;
+
+	BrdgConf->SBus = HRConfigs[HR_DS_PORT6].SubBus + 1;
+}//InitHRDSPort_2Port
+
+BOOLEAN
+CheckLimits(
+	IN		BOOLEAN			Is2PortDev,
+	IN		BRDG_RES_CONFIG *HRResConf,
+	IN		UINT8			BusRange
+)
+{
+	UINT16 MemBase	= HRResConf->MemBase & 0xFFF0;
+	UINT16 MemLimit = HRResConf->MemLimit & 0xFFF0;
+    UINT64 PMemBase64  = HRResConf->PMemBase64 & 0xFFF0;
+    UINT64 PMemLimit64 = HRResConf->PMemLimit64 & 0xFFF0;
+	UINT8  IOBase   = HRResConf->IOBase & 0xF0;
+	UINT8  IOLimit  = HRResConf->IOLimit & 0xF0;
+
+    TRACE((-1, "TbtSmm.c: MemBase   = %x\n", MemBase));
+    TRACE((-1, "TbtSmm.c: MemLimit  = %x\n", MemLimit));
+    TRACE((-1, "TbtSmm.c: PMemBase  = %x\n", PMemBase64));
+    TRACE((-1, "TbtSmm.c: PMemLimit = %x\n", PMemLimit64));
+
+	// Check memory alignment
+	if(MemBase & 0x3FF)
+	{
+        TRACE((-1, "TbtSmm.c: M alig is not 64 MB.\n"));
+		return FALSE;
+	}
+	if(PMemBase64 & 0xFFF)
+	{
+        TRACE((-1, "TbtSmm.c: PM alig is not 256 MB.\n"));
+		return FALSE;
+	}
+
+	// Check mem size
+	
+	if(Is2PortDev)
+	{
+		// Check mem size
+		if(MemLimit + 0x10 - MemBase < 0x2E00)
+		{
+			TRACE((-1, "TbtSmm.c: M size is small than 737 MB.\n"));
+			return FALSE;
+		}
+		// Check P-mem size
+		if(PMemLimit64 + 0x10 - PMemBase64 < 0x4A00)
+		{
+			TRACE((-1, "TbtSmm.c: PM size is small than 1184 MB.\n"));
+			return FALSE;
+		}
+		// Check bus range
+		if(BusRange < 106)
+		{
+			TRACE((-1, "TbtSmm.c: Bus range is small than 106.\n"));
+			return FALSE;
+		}
+	}
+	else
+	{
+		if(MemLimit + 0x10 - MemBase < 0x1600) //Reserved mem min: 353MB
+		{
+            TRACE((-1, "TbtSmm.c: M size is small than 353 MB.\n"));
+			return FALSE;
+		}
+		if(PMemLimit64 + 0x10 - PMemBase64 < 0x2200) //Prefetchable mem min: 544MB
+		{
+            TRACE((-1, "TbtSmm.c: PM size is small than 544 MB.\n"));
+			return FALSE;
+		}
+		if(BusRange < 56) //Reserved bus min: 56
+		{
+            TRACE((-1, "TbtSmm.c: Bus range is small than 56\n"));
+			return FALSE;
+		}
+	}
+
+	return TRUE;
+}
+
+
+
+BOOLEAN
+InitHRResConfigs(
+    IN	  OUT    HR_CONFIG *HR_Config,
+    IN           UINT8 BusNumLimit,
+    IN    OUT    BRDG_RES_CONFIG* HRResConf
+)
+{
+    BRDG_CONFIG BrdgConf = {0};
+    InitCommonHRConfigs(HR_Config, BusNumLimit, HRResConf);
+    BrdgConf.PBus = HR_Config->HRBus + 2;
+    BrdgConf.SBus = HR_Config->HRBus + 3;
+    BrdgConf.SubBus = BusNumLimit;
+    BrdgConf.Res = *HRResConf;
+    while(TRUE){
+      switch(HR_Config->DeviceId)
+      {
+      case CR_HR_4C:
+      case RR_HR_4C: 
+      case FR_HR_4C: // 2 Port host
+          if(CheckLimits(TRUE, HRResConf, BusNumLimit - HR_Config->HRBus))
+          {
+              InitHRDSPort_2Port(&BrdgConf);
+              return TRUE;
+          }
+          else
+          {
+              HR_Config->DeviceId = 0; // Jump to default on next loop
+              continue;
+          }
+      case CR_HR_2C:
+      case RR_HR_2C:
+      case FR_HR_2C: // 1 Port host
+          if(CheckLimits(FALSE, HRResConf, BusNumLimit - HR_Config->HRBus))
+          {	
+              InitHRDSPort_1Port(&BrdgConf);
+              InitHRDSPort_Disable(HR_DS_PORT5, &BrdgConf);
+              InitHRDSPort_Disable(HR_DS_PORT6, &BrdgConf);
+              return TRUE;
+          }
+      case WR_HR_2C: // 1 Port host
+          return TRUE;
+      default:
+              InitHRDSPort_Disable(HR_DS_PORT3, &BrdgConf);
+              InitHRDSPort_Disable(HR_DS_PORT4, &BrdgConf);
+              InitHRDSPort_Disable(HR_DS_PORT5, &BrdgConf);
+              InitHRDSPort_Disable(HR_DS_PORT6, &BrdgConf);
+              return FALSE;
+      }//switch
+    }//while
+}//InitHRResConfigs
+
+BOOLEAN
+InitializeHostRouter(
+        OUT  HR_CONFIG  *HR_Config
+)
+{
+    UINT8             BusNumLimit;
+    BRDG_RES_CONFIG   HRResConf = {0};
+    UINT8             i;
+	BOOLEAN           Ret = TRUE;
+
+    for(i = 0; i < count(HR_Slots); ++i)
+    {
+        HR_Config->HRBus  = SmiPci8  (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_SBUS);
+        HR_Config->DeviceId = SmiPci16 (0x00, HR_Config->HRBus, 0x00, 0x00, PCI_DID);
+        if (IsTBTHostRouter(HR_Config->DeviceId))
+            break;
+    }
+
+    if(i >= count(HR_Slots))
+        return FALSE;
+
+    if (gTbtIOresourceEnable == TRUE)
+	   HRResConf.Cmd         = CMD_BM_MEM_IO;
+	else
+       HRResConf.Cmd         = CMD_BM_MEM;
+    HRResConf.Cls         = gCacheLineSize;
+    HRResConf.IOBase      = SmiPci8  (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_IOBASE);
+    HRResConf.IOLimit     = SmiPci8  (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_IOLIMIT);
+    HRResConf.MemBase     = SmiPci16 (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_MEMBASE);
+    HRResConf.MemLimit    = SmiPci16 (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_MEMLIMIT);
+    HRResConf.PMemBase64  = SmiPci16 (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_PRE_MEMBASE);
+    HRResConf.PMemLimit64 = SmiPci16 (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_PRE_MEMLIMIT);
+    HRResConf.PMemBase64 |= SmiPci32 (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_PRE_MEMBASE_U) << 16;
+    HRResConf.PMemLimit64|= SmiPci32 (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_PRE_MEMLIMIT_U) << 16;
+    BusNumLimit           = SmiPci8  (0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_SUBUS);
+
+    // BIOS support of Thunderbolt devices Specification Update
+    // Revision 0.91
+    // 8.1.2 VGA Enable should not be set
+    // VGA Enable and VGA 16-bit decode registers of Bridge 
+    // control register of Root port where Host router resides
+    // should be cleaned(Both of them should set into 0).
+    SmiPci8And(0x00, HR_Slots[i].Bus, HR_Slots[i].Dev, HR_Slots[i].Fun, PCI_BRIDGE_CNTL, 0xE7);
+
+	Ret = InitHRResConfigs(HR_Config, BusNumLimit, &HRResConf);
+
+    for(i = 0; i < HR_Config->BridgeLoops; ++i)
+    {
+        UINT8 Bus = HRConfigs[i].DevId.Bus;
+        UINT8 Dev = HRConfigs[i].DevId.Dev;
+        UINT8 Fun = HRConfigs[i].DevId.Fun;
+
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_CLS) = HRConfigs[i].Res.Cls;
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_PBUS) = HRConfigs[i].PBus;
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_SBUS) = HRConfigs[i].SBus;
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_SUBUS) = HRConfigs[i].SubBus;
+        SmiPci16 (0x00, Bus, Dev, Fun, PCI_MEMBASE) = HRConfigs[i].Res.MemBase;
+        SmiPci16 (0x00, Bus, Dev, Fun, PCI_MEMLIMIT) = HRConfigs[i].Res.MemLimit;
+        SmiPci16 (0x00, Bus, Dev, Fun, PCI_PRE_MEMBASE) = (UINT16)(HRConfigs[i].Res.PMemBase64 & 0xFFFF);
+        SmiPci16 (0x00, Bus, Dev, Fun, PCI_PRE_MEMLIMIT) = (UINT16)(HRConfigs[i].Res.PMemLimit64 & 0xFFFF);
+        SmiPci32 (0x00, Bus, Dev, Fun, PCI_PRE_MEMBASE_U) = (UINT32)(HRConfigs[i].Res.PMemBase64 >> 16);
+        SmiPci32 (0x00, Bus, Dev, Fun, PCI_PRE_MEMLIMIT_U) = (UINT32)(HRConfigs[i].Res.PMemLimit64 >> 16);
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_IOBASE) = HRConfigs[i].Res.IOBase;
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_IOLIMIT) = HRConfigs[i].Res.IOLimit;
+        SmiPci32 (0x00, Bus, Dev, Fun, PCI_IOBASE_U) = 0x00000000;
+        SmiPci8  (0x00, Bus, Dev, Fun, PCI_CMD) = HRConfigs[i].Res.Cmd;
+    }
+
+    SmiPci32 (0x00, (HR_Config->HRBus + 2), 0x00, 0x00, PCI_BAR0) = HRConfigs[HR_DS_PORT0].Res.MemLimit << 16;
+    SmiPci32 (0x00, (HR_Config->HRBus + 2), 0x00, 0x00, PCI_BAR1) = (HRConfigs[HR_DS_PORT0].Res.MemLimit + 0x4) << 16;
+    SmiPci8  (0x00, (HR_Config->HRBus + 2), 0x00, 0x00, PCI_CLS)  = gCacheLineSize;
+    SmiPci8  (0x00, (HR_Config->HRBus + 2), 0x00, 0x00, PCI_CMD)  = CMD_BM_MEM;
+    
+	return Ret;
+}//InitializeHostRouter
+
+UINT8
+ConfigureSlot(
+    IN        UINT8     Bus,
+    IN        UINT8     MAX_DEVICE,
+	IN		  INT8	    Depth, 
+    IN    OUT    PortInfo* pi
+)
+{
+    UINT8    Device;
+    UINT8    SBus;
+    UINT8    UsedBusNumbers;
+    UINT8    RetBusNum = 0;
+    PortInfo CurrentSlot;
+
+    for (Device = 0; Device < MAX_DEVICE; Device++)
+    {
+        // Continue if device is absent
+        if (0xFFFF == SmiPci16 (0x00, Bus, Device, 0x00, PCI_DID))
+            continue;
+
+        if (P2P_BRIDGE != SmiPci16 (0x00, Bus, Device, 0x00, PCI_SCC))
+        {
+             SetDevResources(Bus, Device,
+                PCI_MAX_FUNC, PCI_BAR5, pi);
+            continue;
+        }
+        // Else Bridge
+
+        CurrentSlot = *pi; // Save before update
+
+        ++RetBusNum; // UP Bridge
+        SBus = Bus + RetBusNum; // DS Bridge
+
+        if (SBus + 1 >= pi->BusNumLimit)
+            continue;
+
+        SetDevResources(Bus, Device, 1, PCI_BAR1, pi);
+
+        // Init UP Bridge to reach DS Bridge
+        SmiPci8 (0x00, Bus, Device, 0x00, PCI_PBUS) = Bus;
+        SmiPci8 (0x00, Bus, Device, 0x00, PCI_SBUS) = SBus;
+        SmiPci8 (0x00, Bus, Device, 0x00, PCI_SUBUS) = pi->BusNumLimit;// Just in case
+		if (gTbtIOresourceEnable == TRUE)
+		   SmiPci8 (0x00, Bus, Device, 0x00, PCI_CMD) = CMD_BM_MEM_IO;
+		else
+           SmiPci8 (0x00, Bus, Device, 0x00, PCI_CMD) = CMD_BM_MEM;
+
+		UsedBusNumbers = ConfigureSlot(SBus, PCI_MAX_DEVICE + 1, -1, pi);
+
+        RetBusNum += UsedBusNumbers;
+
+        SetPHYPortResources(Bus, Device,
+			SBus + UsedBusNumbers, Depth,
+            &CurrentSlot, pi);
+    }//for (Device = 0; Device <= PCI_MAX_DEVICE; Device++)
+    return RetBusNum;
+}// ConfigureSlot
+
+VOID
+SetCIOPortResources(
+    IN        UINT8 Bus, 
+    IN        UINT8 Dev,
+    IN        UINT8 SBus,
+    IN        UINT8 SubBus,
+	IN		PortInfo* portInfoBeforeChange, 
+	IN	OUT	PortInfo* pi
+)
+{
+    UINT8    Cmd = CMD_BUS_MASTER;
+
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_PBUS) = Bus;
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_SBUS) = SBus;
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_SUBUS) = SubBus;
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_CMD) = Cmd;
+
+    if (pi->IOBase <= pi->IOLimit)
+    {
+        SmiPci8  (0x00, Bus, Dev, 0x00, PCI_IOBASE) = pi->IOBase;
+        SmiPci8  (0x00, Bus, Dev, 0x00, PCI_IOLIMIT) = pi->IOLimit;
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_IOBASE_U) = 0x00000000;
+        Cmd |= CMD_BM_IO;
+    }
+    else
+    {
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_IOBASE) = DISBL_IO_REG1C;
+    }
+
+    if (pi->MemBase <= pi->MemLimit)
+    {
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_MEMBASE) = pi->MemBase;
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_MEMLIMIT) = pi->MemLimit;
+        Cmd |= CMD_BM_MEM;
+    }
+    else
+    {
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_MEMBASE) = DISBL_MEM32_REG20;
+    }
+
+    if (pi->PMemBase64 <= pi->PMemLimit64)
+    {
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE) = (UINT16)(pi->PMemBase64 & 0xFFFF);
+        SmiPci16 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMLIMIT) = (UINT16)(pi->PMemLimit64 & 0xFFFF);
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE_U) = (UINT32)(pi->PMemBase64 >> 16);
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMLIMIT_U) = (UINT32)(pi->PMemLimit64 >> 16);
+        Cmd |= CMD_BM_MEM;
+    }
+    else
+    {
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE) = DISBL_PMEM_REG24;
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE_U) = 0;
+        SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMLIMIT_U) = 0;
+    }
+
+    SmiPci8  (0x00, Bus, Dev, 0x00, PCI_CMD) = Cmd;
+    SmiPci8 (0x00, Bus, Dev, 0x00, PCI_CLS) = gCacheLineSize;
+}//SetCIOPortResources
+
+VOID
+SetSlotsAsUnused(
+    IN        UINT8 Bus,
+    IN        UINT8 MaxSlotNum,
+    IN        UINT8 CIOSlot,
+    IN    OUT PortInfo* pi
+)
+{
+    UINT8 Slot;
+    for (Slot = MaxSlotNum; Slot > CIOSlot; --Slot)
+    {
+        if (0xFFFF == SmiPci16 (0x00, Bus, Slot, 0x00, PCI_DID))
+            continue;
+
+        SmiPci8 (0x00, Bus, Slot, 0x00, PCI_CLS) = gCacheLineSize;
+        SmiPci8  (0x00, Bus, Slot, 0x00, PCI_PBUS) = Bus;
+        SmiPci8  (0x00, Bus, Slot, 0x00, PCI_SBUS) = pi->BusNumLimit;
+        SmiPci8  (0x00, Bus, Slot, 0x00, PCI_SUBUS) = pi->BusNumLimit;
+        SmiPci16 (0x00, Bus, Slot, 0x00, PCI_IOBASE) = DISBL_IO_REG1C;
+        SmiPci32 (0x00, Bus, Slot, 0x00, PCI_MEMBASE) = DISBL_MEM32_REG20;
+        SmiPci32 (0x00, Bus, Slot, 0x00, PCI_PRE_MEMBASE) = DISBL_PMEM_REG24;
+        SmiPci8  (0x00, Bus, Slot, 0x00, PCI_CMD) = CMD_BUS_MASTER;
+
+        pi->BusNumLimit--;
+    }
+}//SetSlotsAsUnused
+
+#define PCIE_CAP_ID_VSEC   0x000B
+
+UINT16
+FindVendorSpecificHeader(
+    IN        UINT8  Bus
+)
+{
+    PCIE_EXT_CAP_HDR  ExtCap;
+    UINT16 ExtendedRegister = 0x100;
+
+    while (ExtendedRegister)
+    {
+        ExtCap.EXT_CAP_HDR = SmiPci32  (0x00, Bus, 0x00, 0x00, ExtendedRegister);
+        if (ExtCap.ExtCapId == 0xFFFF)
+            return 0x0000; // No Vendor-Specific Extended Capability header
+
+        if (PCIE_CAP_ID_VSEC == ExtCap.ExtCapId)
+            return ExtendedRegister;
+
+        ExtendedRegister = (UINT16)ExtCap.NextItemPtr;
+    }
+    return 0x0000; // No Vendor-Specific Extended Capability header
+}
+
+#define PCIE_CAP_ID_SSID_SSVID   0x0D
+
+UINT8
+FindSSID_SSVIDHeader(
+    IN        UINT8  Bus
+)
+{
+	UINT8  CapHeaderId;
+	UINT8  CapHeaderOffset = SmiPci8 (0x00, Bus, 0x00, 0x00, PCI_CAPP);
+
+	while (CapHeaderOffset != 0)
+	{
+		CapHeaderId = SmiPci8 (0x00, Bus, 0x00, 0x00, CapHeaderOffset);
+
+		if (CapHeaderId == PCIE_CAP_ID_SSID_SSVID)
+			return CapHeaderOffset;
+
+		CapHeaderOffset = SmiPci8 (0x00, Bus, 0x00, 0x00, CapHeaderOffset + 1);
+	}
+	TRACE((-1, "TbtSmm.c: Cannot find SSID Capability header...\n"));
+	return 0;
+}//FindSSID_SSVIDHeader
+
+typedef union _BRDG_CIO_MAP_REG
+{
+    UINT32    AB_REG;
+    struct
+    {
+        UINT32        NumOfDSPorts : 5;
+        UINT32        CIOPortMap   : 27;
+    };
+}BRDG_CIO_MAP_REG;
+
+BOOLEAN
+GetCIOSlotByDevId(
+    IN        UINT8  Bus,
+        OUT    UINT8* CIOSlot,
+        OUT    UINT8* MaxSlotNum
+)
+{
+    UINT16            VSECRegister;
+    BRDG_CIO_MAP_REG  BridgMap;
+    UINT32            BitScanRes;
+    UINT16            DevId = SmiPci16 (0x00, Bus, 0x00, 0x00, PCI_DID);
+
+    // Init out params in case device is not recognised
+    *CIOSlot = 4;
+    *MaxSlotNum = 7;
+
+    switch(DevId) // For known device IDs
+    {
+    case 0x1513:
+    case 0x151A:
+    case 0x151B:
+    case 0x1547:
+    case 0x1548:
+    case 0x1549:
+        return TRUE; // Just return
+    }
+
+    VSECRegister = FindVendorSpecificHeader(Bus);
+    if(!VSECRegister)
+        return TRUE; // Just return
+
+    // Go to Bridge/CIO map register
+    VSECRegister += 0x18;
+
+    BridgMap.AB_REG = SmiPci32  (0x00, Bus, 0x00, 0x00, VSECRegister);
+    // Check for range
+    if(BridgMap.NumOfDSPorts < 1 || BridgMap.NumOfDSPorts > 27)
+        return TRUE;// Not a valid register
+
+    // Set OUT params
+
+    *MaxSlotNum = (UINT8)BridgMap.NumOfDSPorts;
+    
+    if(!_BitScanForward(&BitScanRes, BridgMap.CIOPortMap))// No DS bridge which is CIO port
+        return FALSE;
+
+    *CIOSlot = (UINT8)BitScanRes;
+    return TRUE;
+}//GetCIOSlotByDevId
+
+#define TBT_LEGACY_SUB_SYS_ID 0x11112222
+
+BOOLEAN
+IsLegacyDevice(
+    IN        UINT8  Bus
+)
+{
+    UINT32 SID;
+	UINT8  SIDRegister;
+	UINT16 DevId = SmiPci16 (0x00, Bus, 0x00, 0x00, PCI_DID);
+    switch(DevId) // For known device IDs
+    {
+    case 0x1513:
+    case 0x151A:
+    case 0x151B:
+		TRACE((-1, "TbtSmm.c: Legacy device %x...\n", DevId));
+        return TRUE; // Legacy device by Device Id
+    }
+
+	SIDRegister = FindSSID_SSVIDHeader(Bus);
+
+    if(!SIDRegister)
+        return TRUE; // May be absent for legacy devices
+
+    // Go to register
+    SIDRegister += 0x4;
+
+    SID = SmiPci32  (0x00, Bus, 0x00, 0x00, SIDRegister);
+	TRACE((-1, "TbtSmm.c: SSID of device is %x...\n", SID));
+
+	return TBT_LEGACY_SUB_SYS_ID == SID || 0 == SID;
+}//IsLegacyDevice
+
+BOOLEAN
+ConfigureEP(
+	IN		INT8  Depth, 
+    IN    OUT UINT8* Bus,
+    IN    OUT PortInfo* pi
+)
+{
+    UINT8     SBus;
+    UINT8     CIOSlot = 4;
+    UINT8     MaxSlotNum = 7;
+    UINT8     MaxPHYSlots;
+    UINT8     UsedBusNumbers;
+	UINT8     cmd;
+    BOOLEAN   CIOSlotPresent;
+    BOOLEAN   Continue;
+	PortInfo  portInfo = *pi;
+
+    // Based on Device ID assign CIO slot and max number of PHY slots to scan
+    CIOSlotPresent = GetCIOSlotByDevId(*Bus, &CIOSlot, &MaxSlotNum);
+    MaxPHYSlots = MaxSlotNum;// Correct if CIO slot is absent
+	// Check whether EP already configured by examining CMD register
+	cmd = SmiPci8  (0x00, *Bus, 0x00, 0x00, PCI_CMD);
+#if !defined TBT_PCIBUS_SKIP || TBT_PCIBUS_SKIP == 0
+    if(IsFirstEnterFlag) cmd &= 0;  //AMI_OVERWRITE
+#endif
+	if(cmd & CMD_BUS_MASTER) // Yes no need to touch this EP, just move to next one in chain
+	{
+		UINT8  CIOBus = *Bus + 1;
+		if(!CIOSlotPresent)// CIO slot is not present in EP, just return FALSE
+		{
+			//PrintCPStr("BMF");
+            TRACE((-1, "TbtSmm.c: CIO slot is not present in EP, just return FALSE.\n"));
+			return FALSE;
+		}
+		// Take all resources from CIO slot and return
+		pi->BusNumLimit = SmiPci8  (0x00, CIOBus, CIOSlot, 0x00, PCI_SUBUS);
+		pi->IOBase		= SmiPci8  (0x00, CIOBus, CIOSlot, 0x00, PCI_IOBASE);
+		pi->IOLimit		= SmiPci8  (0x00, CIOBus, CIOSlot, 0x00, PCI_IOLIMIT);
+		pi->MemBase		= SmiPci16 (0x00, CIOBus, CIOSlot, 0x00, PCI_MEMBASE);
+		pi->MemLimit	= SmiPci16 (0x00, CIOBus, CIOSlot, 0x00, PCI_MEMLIMIT);
+        pi->PMemBase64	= SmiPci16 (0x00, CIOBus, CIOSlot, 0x00, PCI_PRE_MEMBASE) & 0xFFF0;
+        pi->PMemLimit64	= SmiPci16 (0x00, CIOBus, CIOSlot, 0x00, PCI_PRE_MEMLIMIT) & 0xFFF0;
+        pi->PMemBase64 |= SmiPci32 (0x00, CIOBus, CIOSlot, 0x00, PCI_PRE_MEMBASE_U) << 16;
+        pi->PMemLimit64|= SmiPci32 (0x00, CIOBus, CIOSlot, 0x00, PCI_PRE_MEMLIMIT_U) << 16;
+        pi->PMemLimit64|= 0xF;
+		// Jump to next EP
+		*Bus = SmiPci8  (0x00, CIOBus, CIOSlot, 0x00, PCI_SBUS);
+		// Should we continue?
+		Continue = 0xFFFF != SmiPci16 (0x00, *Bus, 0x00, 0x00, PCI_DID);
+		return Continue;
+	}
+
+	//Set is legacy dvice
+	isLegacyDevice = IsLegacyDevice(*Bus);
+
+    SetCIOPortResources(*Bus, 0, // Assign all available resources to US port of EP
+		*Bus + 1, pi->BusNumLimit, 0, pi);
+
+    SBus = *Bus + 1;// Jump to DS port 
+
+    if(CIOSlotPresent)
+        MaxPHYSlots = CIOSlot;
+
+	UsedBusNumbers = ConfigureSlot(SBus, MaxPHYSlots, Depth, pi);
+
+    if(!CIOSlotPresent)
+        return FALSE; // Stop resource assignment on this chain
+
+    // Set rest of slots us unused
+    SetSlotsAsUnused(SBus, MaxSlotNum, CIOSlot, pi);
+
+    SetCIOPortResources(SBus, CIOSlot,
+        SBus + UsedBusNumbers + 1,
+		pi->BusNumLimit, &portInfo, pi);
+
+    *Bus = SBus + UsedBusNumbers + 1;// Go to next EP
+
+    if (*Bus > pi->BusNumLimit - 2) // In case of bus numbers are exhausted stop enumeration
+        return FALSE;
+
+    // BIOS support of Thunderbolt devices Specification Update
+    // Revision 0.94
+    // This OPTIONAL workaround sholud be disable by default
+
+    // BIOS support of Thunderbolt devices Specification Update
+    // Revision 0.92
+    // OPTIONAL workaround for devices that don't support surprise-removal
+    // If SMI Handler cannot find any device behind a CIO port it means no more TBT devices 
+    // attached to this PCIe sub-tree.  In this case BIOS should set MBASE = MLIMIT.
+    // Check whether we should continue on this chain
+	Continue = 0xFFFF != SmiPci16 (0x00, *Bus, 0x00, 0x00, PCI_DID);
+    
+	return Continue;
+}//ConfigureEP
+
+VOID
+GetPortResources(
+    IN        UINT8 Bus,
+    IN        UINT8 Dev,
+    IN    OUT PortInfo* pi
+)
+{
+    pi->BusNumLimit = SmiPci8  (0x00, Bus, Dev, 0x00, PCI_SUBUS);
+    pi->IOBase      = SmiPci8  (0x00, Bus, Dev, 0x00, PCI_IOBASE) & 0xF0;
+    pi->IOLimit     = SmiPci8  (0x00, Bus, Dev, 0x00, PCI_IOLIMIT) & 0xF0;
+    pi->MemBase     = SmiPci16 (0x00, Bus, Dev, 0x00, PCI_MEMBASE) & 0xFFF0;
+    pi->MemLimit    = SmiPci16 (0x00, Bus, Dev, 0x00, PCI_MEMLIMIT) & 0xFFF0;
+	pi->PMemBase64	= SmiPci16 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE) & 0xFFF0;
+	pi->PMemLimit64	= SmiPci16 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMLIMIT) & 0xFFF0;
+	pi->PMemBase64 |= SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMBASE_U) << 16;
+	pi->PMemLimit64|= SmiPci32 (0x00, Bus, Dev, 0x00, PCI_PRE_MEMLIMIT_U) << 16;
+    pi->IOLimit |= 0xF;
+    pi->MemLimit |= 0xF;
+    pi->PMemLimit64 |= 0xF;
+}//GetPortResources
+
+VOID
+ConfigurePort(
+    IN        UINT8 Bus,
+    IN        UINT8 Dev,
+    IN    OUT PortInfo* pi
+)
+{
+	INT8      i;
+    UINT8     USBusNum = SmiPci8  (0x00, Bus, Dev, 0x00, PCI_SBUS);
+
+    if (0xFFFF == SmiPci16 (0x00, USBusNum, 0x00, 0x00, PCI_DID))// Nothing to do if TBT device is not connected
+        return;
+    
+    GetPortResources(Bus, Dev, pi);// Take reserved resources from DS port
+
+    // Assign resources to EPs
+    for (i = 0; i < MAX_TBT_DEPTH; ++i)
+    {
+        pi->ConfedEP++;
+		if(!ConfigureEP(i, &USBusNum, pi))
+            return;
+    }
+}//ConfigurePort
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   ThunderboltSwSmiCallback
+//
+// Description: This is a TBT software SMI Handler for Porting.
+//
+// Input:       DispatchHandle  - EFI Handle
+//              DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+EFI_STATUS ThunderboltSwSmiCallback (
+    IN EFI_HANDLE       DispatchHandle,
+    IN CONST VOID       *DispatchContext OPTIONAL,
+    IN OUT VOID         *CommBuffer OPTIONAL,
+    IN OUT UINTN        *CommBufferSize OPTIONAL )
+#else
+VOID ThunderboltSwSmiCallback (
+    IN EFI_HANDLE                   DispatchHandle,
+    IN AMI_SMM_SW_DISPATCH_CONTEXT  *DispatchContext)
+#endif
+{
+    PortInfo                portInfo = {0};
+    HR_CONFIG               HrConfig = {0};
+    UINT8                   i;
+    EFI_STATUS              Status;
+    EFI_GUID                SetupGuid = SETUP_GUID;
+    EFI_GUID                TbtHRStatusGuid = AMI_TBT_HR_STATUS_GUID;
+    CHAR16                  TbtHRStatusVar[] = TBT_HR_STATUS_VARIABLE;
+    UINTN                   SetupDataSize = sizeof(SETUP_DATA);
+    SETUP_DATA              SetupData;
+    AMI_TBT_HR_STATUS_DATA  TbtHRStatusData;
+    
+    TRACE((-1, "TbtSmm.c: Thunderbolt SWSMI Callback Function Entry !!!\n"));
+    Status = pRS->GetVariable(L"Setup", &SetupGuid, NULL, &SetupDataSize, &SetupData);
+    if (!EFI_ERROR(Status)){
+        SmiStall((UINTN)(SetupData.TbtSwSMIDelay * 1000));
+    }
+    
+    // Workaround for synchronizing cache line size of Thunderbolt
+    if (gCacheLineSize != SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, R_PCH_PCIE_CLS))
+        SmiPci8AndThenOr( 0x00, gTbtBus, gTbtDev, gTbtFun, R_PCH_PCIE_CLS, 0x00, gCacheLineSize);
+    
+    SMI_PROGRESS_CODE (SMM_THUNDERBOLT_CALL);
+    
+    PortInfoInit(&portInfo);
+
+    if (!InitializeHostRouter(&HrConfig)){
+        SMI_PROGRESS_CODE (0xCB); //Cable is unplugged
+        
+        // BIOS support of Thunderbolt devices Specification Update
+        // Revision 0.90
+        // BIOS should remember whether HR is active(it is active 
+        // when cable is connected)
+        
+        // HR status is setted inactive
+        TbtHRStatusData.TbtHRStatus = 0;
+        if ((HostDeviceId == 0x1547) || (HostDeviceId == 0x1548)) {
+            TbtHRStatusData.TbtHRSeries = Cactus_Ridge;
+        } else if ((HostDeviceId == 0x1567) || (HostDeviceId == 0x1569)) {
+            TbtHRStatusData.TbtHRSeries = Redwood_Ridge;
+        } else if ((HostDeviceId == 0x156B) || (HostDeviceId == 0x156D)){
+            TbtHRStatusData.TbtHRSeries = Falcon_Ridge;
+        } else {
+            TbtHRStatusData.TbtHRSeries = BDW_TBT_LP;
+        }
+        
+        Status = pRS->SetVariable( TbtHRStatusVar, \
+                                 &TbtHRStatusGuid, \
+                                 AmiTbtHrStatusAttribute, \
+                                 sizeof(AMI_TBT_HR_STATUS_DATA), \
+                                 &TbtHRStatusData );
+
+#if !defined TBT_PCIBUS_SKIP || TBT_PCIBUS_SKIP == 0
+        if(IsFirstEnterFlag) IsFirstEnterFlag = 0;
+#endif
+        TRACE((-1, "TbtSmm.c: Thunderbolt SWSMI Callback Function Exit !!!\n"));
+        return SMM_CHILD_DISPATCH_SUCCESS;
+    }
+    
+    // Configure DS ports
+	for(i = HrConfig.MinDSNumber; i <= HrConfig.MaxDSNumber; ++i)
+    {
+		ConfigurePort(HrConfig.HRBus + 1, i, &portInfo);
+    }
+    SMI_PROGRESS_CODE (SMM_THUNDERBOLT_CALL + 2 + portInfo.ConfedEP); //PostCode = 0xAC + # of connected EP
+    
+    // BIOS support of Thunderbolt devices Specification Update
+    // Revision 0.90
+    // BIOS should remember whether HR is active(it is active 
+    // when cable is connected)
+    // HR status is setted active
+    HostDeviceId  = SmiPci16 (0x00, HrConfig.HRBus, 0x00, 0x00, PCI_DID);
+    TRACE((-1, "TbtSmm.c: Get Thunderbolt Host Device ID %x in SWSMI from Bus:%x \n", HostDeviceId, HrConfig.HRBus));
+    if ((HostDeviceId == 0x1547) || (HostDeviceId == 0x1548))
+        TbtHRStatusData.TbtHRSeries = Cactus_Ridge;
+    if ((HostDeviceId == 0x1567) || (HostDeviceId == 0x1569))
+        TbtHRStatusData.TbtHRSeries = Redwood_Ridge;
+    if ((HostDeviceId == 0x156B) || (HostDeviceId == 0x156D))
+        TbtHRStatusData.TbtHRSeries = Falcon_Ridge;
+    if (HostDeviceId == 0x157E)
+        TbtHRStatusData.TbtHRSeries = BDW_TBT_LP;
+               
+    TbtHRStatusData.TbtHRStatus = 1;
+    Status = pRS->SetVariable( TbtHRStatusVar, \
+                               &TbtHRStatusGuid, \
+                               AmiTbtHrStatusAttribute, \
+                               sizeof(AMI_TBT_HR_STATUS_DATA), \
+                               &TbtHRStatusData );
+    
+#if !defined TBT_PCIBUS_SKIP || TBT_PCIBUS_SKIP == 0
+    if(IsFirstEnterFlag) IsFirstEnterFlag = 0;
+#endif
+    TRACE((-1, "TbtSmm.c: Thunderbolt SWSMI Callback Function Exit !!!\n"));
+    return SMM_CHILD_DISPATCH_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtPowerButtonCallback
+//
+// Description: The following flow should be performed as a last step before
+//              instructing the platform to enter Sx state:
+//                 BIOS should assert GO2Sx pin
+//              That will trigger Host Router to prepare underlying devices
+//                 BIOS should poll OK2GO2SX_N_OD pin
+//              Upon completion of all preparations, Host Router will assert
+//              this pin to indicate readiness for Sx entry
+//              At this stage BIOS should continue with legacy Sx entry steps
+//
+// Input:       DispatchHandle   - SMI dispatcher handle
+//              *DispatchContext - Pointer to the dispatch context
+//
+// Output:      Nothing
+//
+// Notes:       This function does not need to put the system to sleep.  This is
+//              handled by PutToSleep.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+EFI_STATUS TbtPowerButtonCallback (
+    IN EFI_HANDLE       DispatchHandle,
+    IN CONST VOID       *DispatchContext OPTIONAL,
+    IN OUT VOID         *CommBuffer OPTIONAL,
+    IN OUT UINTN        *CommBufferSize OPTIONAL )
+#else
+VOID TbtPowerButtonCallback (
+    IN EFI_HANDLE                               DispatchHandle,
+    IN AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT    *DispatchContext)
+#endif
+{
+    EFI_STATUS     Status;
+    UINT8          UpPortBus;
+    UINT8          RegVal8;
+    UINT16         PresenceFlag = 0;
+    UINT8          SlotStatusCapOffset;
+    UINT8          PowerManagerCapOffset;
+#if defined TBT_HR_SX_CHECK && TBT_HR_SX_CHECK == 1
+    UINT32         Attributes;
+    UINTN          TbtHRStatusDataSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+    CHAR16         TbtHRStatusVar[]    = TBT_HR_STATUS_VARIABLE;
+    EFI_GUID       TbtHRStatusGuid     = AMI_TBT_HR_STATUS_GUID;
+    AMI_TBT_HR_STATUS_DATA  TbtHRStatusData;
+
+    // Double check Thunderbolt Host status
+    SlotStatusCapOffset = PcieFindCapId(gTbtBus, gTbtDev, gTbtFun, EFI_PCI_CAPABILITY_ID_PCIEXP);
+    PresenceFlag = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (SlotStatusCapOffset + 0x1A));
+
+    Status = pRS->GetVariable(TbtHRStatusVar, &TbtHRStatusGuid, &Attributes, &TbtHRStatusDataSize, &TbtHRStatusData);
+    if (!EFI_ERROR(Status)){
+        TRACE((-1, "Thunderbolt Presence bit on PCIE root port%x :%x(Bit06)\n", gTbtFun, PresenceFlag));
+        if (TbtHRStatusData.TbtHRStatus){
+            if ((PresenceFlag & B_PCH_PCIE_SLSTS_PDS) == 0){
+                // Host route status record is active but no device connect actually
+                TbtHRStatusData.TbtHRStatus = 0;
+                //TbtHRStatusData.TbtHRSeries = HostDeviceId;
+                Status = pRS->SetVariable( TbtHRStatusVar, \
+                                           &TbtHRStatusGuid, \
+                                           Attributes, \
+                                           sizeof(AMI_TBT_HR_STATUS_DATA), \
+                                           &TbtHRStatusData );
+                TRACE((-1, "Host route status record is active but no device connect actually !!!\nReset Thunderbolt Host state %r\n", Status));
+            }
+        } else {
+            if ((PresenceFlag & B_PCH_PCIE_SLSTS_PDS) != 0){
+                // Host route status record is inactive but device connect actually
+                TbtHRStatusData.TbtHRStatus = 1;
+                //TbtHRStatusData.TbtHRSeries = HostDeviceId;
+                Status = pRS->SetVariable( TbtHRStatusVar, \
+                                           &TbtHRStatusGuid, \
+                                           Attributes, \
+                                           sizeof(AMI_TBT_HR_STATUS_DATA), \
+                                           &TbtHRStatusData );
+                TRACE((-1, "Host route status record is inactive but device connect actually !!!\nReset Thunderbolt Host state %r\n", Status));
+            }
+        } //TbtHRStatus
+    } // !EFI_ERROR(Status)
+#endif
+
+    if (!gTbtWakeupSupport){
+        // System does not support wake from Thunderbolt device
+        if ((HostDeviceId == 0x1547) || (HostDeviceId == 0x1548)){
+            // Sleep entry flow for Cactus Ridge chip
+#if defined TBT_HR_PWR && (TBT_HR_PWR != 0xFF)
+            if (gTbtHandlePOC){
+                Status = PowerOffPOC();
+                TRACE((-1, "TbtSmm.c: Cut off Thunderbolt POC power %r !!!\n", Status));
+                ASSERT_EFI_ERROR(Status);
+            }
+            else
+#endif
+                return SMM_CHILD_DISPATCH_UNSUPPORTED;
+        } else {
+            // Sleep entry flow for Redwood Ridge / Falcon Ridge / BDW-TBT-LP chip 
+            // when system doesn't support thunderbolt wake function
+            
+            // put PCIE root port power state back to D0
+            PowerManagerCapOffset = PcieFindCapId(gTbtBus, gTbtDev, gTbtFun, EFI_PCI_CAPABILITY_ID_PMI);
+            RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+            RegVal8 &= B_PCH_PCIE_PMCS_PS;
+            SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+            
+            // BIOS support of Thunderbolt devices Specification Update Revision 1.4
+            // 2.3.2.2 Sx Entry flow for RR Hosts without Thunderbolt wake support
+            UpPortBus = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, PCI_SBUS);
+            if (!TbtSetPCIe2TBTCommand(UpPortBus, 0, TBT_GO2SX_NO_WAKE, 0x8FFFF)){
+                // restore PCIE root port power state back to D3
+                RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+                RegVal8 |= B_PCH_PCIE_PMCS_PS;
+                SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+                
+                return SMM_CHILD_DISPATCH_NO_MEDIA;
+            }
+            
+            // restore PCIE root port power state back to D3
+            RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+            RegVal8 |= B_PCH_PCIE_PMCS_PS;
+            SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+        }
+    } else {
+        // System support wake from Thunderbolt device
+        if ((HostDeviceId == 0x1547) || (HostDeviceId == 0x1548)){
+            // BIOS support of Thunderbolt devices Specification Update
+            // Revision 0.85
+            // 5. System power state (Sx) handing
+            // For Cactus Ridge (CR) Host Router component, those GPIO's 
+            // should be connected to the following pins:
+            // 1. GPIO_2__GO2SX - active high
+            // 2. GPIO_9__OK2GO2SX_N_OD - active low
+            Status = ActiveTbtGpio2();
+            ASSERT_EFI_ERROR(Status);
+            
+            Status = PollTbtGpio9();
+            ASSERT_EFI_ERROR(Status);
+        } else {
+            // Sleep entry flow for Redwood Ridge / Falcon Ridge / BDW-TBT-LP chip 
+            // when system support thunderbolt wake function
+            //
+            // Thunderbolt BIOS Implementation guide for Redwood Ridge/Falcon Ridge/BDW-TBT-LP based 
+            // devices Specification Update Revision 1.0
+            // 2.2.2.3 Sx Entry Flow for Host with Add-In Card support
+            
+#if !defined TBT_HR_SX_CHECK || TBT_HR_SX_CHECK == 0
+            SlotStatusCapOffset = PcieFindCapId(gTbtBus, gTbtDev, gTbtFun, EFI_PCI_CAPABILITY_ID_PCIEXP);
+            PresenceFlag = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (SlotStatusCapOffset + 0x1A));
+#endif      
+            if (gTbtAICSupport){
+                if((PresenceFlag & B_PCH_PCIE_SLSTS_PDS) != 0){
+                    // put PCIE root port power state back to D0
+                    PowerManagerCapOffset = PcieFindCapId(gTbtBus, gTbtDev, gTbtFun, EFI_PCI_CAPABILITY_ID_PMI);
+                    RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+                    RegVal8 &= B_PCH_PCIE_PMCS_PS;
+                    SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+                    
+                    // Get Thunderbolt host location
+                    UpPortBus = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, PCI_SBUS);
+                    if (!TbtSetPCIe2TBTCommand(UpPortBus, 0, TBT_GO2SX_WITH_WAKE, 0x8FFFF)){
+                        // restore PCIE root port power state back to D3
+                        RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+                        RegVal8 |= B_PCH_PCIE_PMCS_PS;
+                        SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+                        
+                        return SMM_CHILD_DISPATCH_TIMEOUT;
+                    }
+                    
+                    // restore PCIE root port power state back to D3
+                    RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+                    RegVal8 |= B_PCH_PCIE_PMCS_PS;
+                    SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+                }
+            }// end of AIC support
+            
+            //
+            // BIOS support of Thunderbolt devices Specification Update Revision 1.4
+            // 2.3.2.1 Sx Entry flow for RR/FR/WR Hosts with Thunderbolt wake support
+            
+            //UpPortBus = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, PCI_SBUS);
+            //if (!TbtSetPCIe2TBTCommand(UpPortBus, 0, TBT_GO2SX_WITH_WAKE, 0x8FFFF))
+            //   return SMM_CHILD_DISPATCH_NO_MEDIA;
+        }
+    }
+    TRACE((-1, "TbtSmm: TbtPowerButtonCallback() !!!\n"));
+    return SMM_CHILD_DISPATCH_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtGo2SxCallback
+//
+// Description: The following flow should be performed as a last step before
+//              instructing the platform to enter Sx state:
+//                 BIOS should assert GO2Sx pin
+//              That will trigger Host Router to prepare underlying devices
+//                 BIOS should poll OK2GO2SX_N_OD pin
+//              Upon completion of all preparations, Host Router will assert
+//              this pin to indicate readiness for Sx entry
+//              At this stage BIOS should continue with legacy Sx entry steps
+//
+// Input:       DispatchHandle   - SMI dispatcher handle
+//              *DispatchContext - Pointer to the dispatch context
+//
+// Output:      Nothing
+//
+// Notes:       This function does not need to put the system to sleep.  This is
+//              handled by PutToSleep.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+EFI_STATUS TbtGo2SxCallback (
+  IN EFI_HANDLE       DispatchHandle,
+  IN CONST VOID       *DispatchContext OPTIONAL,
+  IN OUT VOID         *CommBuffer OPTIONAL,
+  IN OUT UINTN        *CommBufferSize OPTIONAL )
+#else
+VOID TbtGo2SxCallback (
+  IN EFI_HANDLE                   DispatchHandle,
+  IN EFI_SMM_SX_DISPATCH_CONTEXT  *DispatchContext )
+#endif
+{
+    EFI_STATUS     Status;
+    UINT8          UpPortBus;
+    UINT8          RegVal8;
+    UINT16         PresenceFlag = 0;
+    UINT8          SlotStatusCapOffset;
+    UINT8          PowerManagerCapOffset;
+#if defined TBT_HR_SX_CHECK && TBT_HR_SX_CHECK == 1
+    UINT32         Attributes;
+    UINTN          TbtHRStatusDataSize = sizeof(AMI_TBT_HR_STATUS_DATA);
+    CHAR16         TbtHRStatusVar[]    = TBT_HR_STATUS_VARIABLE;
+    EFI_GUID       TbtHRStatusGuid     = AMI_TBT_HR_STATUS_GUID;
+    AMI_TBT_HR_STATUS_DATA  TbtHRStatusData;
+
+    // Double check Thunderbolt Host status
+    SlotStatusCapOffset = PcieFindCapId(gTbtBus, gTbtDev, gTbtFun, EFI_PCI_CAPABILITY_ID_PCIEXP);
+    PresenceFlag = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (SlotStatusCapOffset + 0x1A));
+
+    Status = pRS->GetVariable(TbtHRStatusVar, &TbtHRStatusGuid, &Attributes, &TbtHRStatusDataSize, &TbtHRStatusData);
+    if (!EFI_ERROR(Status)){
+        TRACE((-1, "Thunderbolt Presence bit on PCIE root port%x :%x(Bit06)\n", gTbtFun, PresenceFlag));
+        if (TbtHRStatusData.TbtHRStatus){
+            if ((PresenceFlag & B_PCH_PCIE_SLSTS_PDS) == 0){
+                // Host route status record is active but no device connect actually
+                TbtHRStatusData.TbtHRStatus = 0;
+                //TbtHRStatusData.TbtHRSeries = HostDeviceId;
+                Status = pRS->SetVariable( TbtHRStatusVar, \
+                                           &TbtHRStatusGuid, \
+                                           Attributes, \
+                                           sizeof(AMI_TBT_HR_STATUS_DATA), \
+                                           &TbtHRStatusData );
+                TRACE((-1, "Host route status record is active but no device connect actually !!!\nReset Thunderbolt Host state %r\n", Status));
+            }
+        } else {
+            if ((PresenceFlag & B_PCH_PCIE_SLSTS_PDS) != 0){
+                // Host route status record is inactive but device connect actually
+                TbtHRStatusData.TbtHRStatus = 1;
+                //TbtHRStatusData.TbtHRSeries = HostDeviceId;
+                Status = pRS->SetVariable( TbtHRStatusVar, \
+                                           &TbtHRStatusGuid, \
+                                           Attributes, \
+                                           sizeof(AMI_TBT_HR_STATUS_DATA), \
+                                           &TbtHRStatusData );
+                TRACE((-1, "Host route status record is inactive but device connect actually !!!\nReset Thunderbolt Host state %r\n", Status));
+            }
+        } //TbtHRStatus
+    } // !EFI_ERROR(Status)
+#endif
+
+    if (!gTbtWakeupSupport){
+        // System does not support wake from Thunderbolt device
+        if ((HostDeviceId == 0x1547) || (HostDeviceId == 0x1548)){
+            // Sleep entry flow for Cactus Ridge chip
+#if defined TBT_HR_PWR && (TBT_HR_PWR != 0xFF)
+            if (gTbtHandlePOC){
+                Status = PowerOffPOC();
+                TRACE((-1, "TbtSmm.c: Cut off Thunderbolt POC power %r !!!\n", Status));
+                ASSERT_EFI_ERROR(Status);
+            }
+            else
+#endif
+                return SMM_CHILD_DISPATCH_UNSUPPORTED;
+        } else {
+            // Sleep entry flow for Redwood Ridge / Falcon Ridge / BDW-TBT-LP chip 
+            // when system doesn't support thunderbolt wake function
+            
+            // put PCIE root port power state back to D0
+            PowerManagerCapOffset = PcieFindCapId(gTbtBus, gTbtDev, gTbtFun, EFI_PCI_CAPABILITY_ID_PMI);
+            RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+            RegVal8 &= B_PCH_PCIE_PMCS_PS;
+            SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+            
+            // BIOS support of Thunderbolt devices Specification Update Revision 1.4
+            // 2.3.2.2 Sx Entry flow for RR Hosts without Thunderbolt wake support
+            UpPortBus = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, PCI_SBUS);
+            if (!TbtSetPCIe2TBTCommand(UpPortBus, 0, TBT_GO2SX_NO_WAKE, 0x8FFFF)){
+                // restore PCIE root port power state back to D3
+                RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+                RegVal8 |= B_PCH_PCIE_PMCS_PS;
+                SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+                
+                return SMM_CHILD_DISPATCH_NO_MEDIA;
+            }
+            
+            // restore PCIE root port power state back to D3
+            RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+            RegVal8 |= B_PCH_PCIE_PMCS_PS;
+            SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+        }
+    } else {
+        // System support wake from Thunderbolt device
+        if ((HostDeviceId == 0x1547) || (HostDeviceId == 0x1548)){
+            // BIOS support of Thunderbolt devices Specification Update
+            // Revision 0.85
+            // 5. System power state (Sx) handing
+            // For Cactus Ridge (CR) Host Router component, those GPIO's 
+            // should be connected to the following pins:
+            // 1. GPIO_2__GO2SX - active high
+            // 2. GPIO_9__OK2GO2SX_N_OD - active low
+            Status = ActiveTbtGpio2();
+            ASSERT_EFI_ERROR(Status);
+            
+            Status = PollTbtGpio9();
+            ASSERT_EFI_ERROR(Status);
+        } else {
+            // Sleep entry flow for Redwood Ridge / Falcon Ridge / BDW-TBT-LP chip 
+            // when system support thunderbolt wake function
+            //
+            // Thunderbolt BIOS Implementation guide for Redwood Ridge/Falcon Ridge/BDW-TBT-LP based 
+            // devices Specification Update Revision 1.0
+            // 2.2.2.3 Sx Entry Flow for Host with Add-In Card support
+            
+#if !defined TBT_HR_SX_CHECK || TBT_HR_SX_CHECK == 0
+            SlotStatusCapOffset = PcieFindCapId(gTbtBus, gTbtDev, gTbtFun, EFI_PCI_CAPABILITY_ID_PCIEXP);
+            PresenceFlag = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (SlotStatusCapOffset + 0x1A));
+#endif      
+            if (gTbtAICSupport){
+                if((PresenceFlag & B_PCH_PCIE_SLSTS_PDS) != 0){
+                    // put PCIE root port power state back to D0
+                    PowerManagerCapOffset = PcieFindCapId(gTbtBus, gTbtDev, gTbtFun, EFI_PCI_CAPABILITY_ID_PMI);
+                    RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+                    RegVal8 &= B_PCH_PCIE_PMCS_PS;
+                    SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+                    
+                    // Get Thunderbolt host location
+                    UpPortBus = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, PCI_SBUS);
+                    if (!TbtSetPCIe2TBTCommand(UpPortBus, 0, TBT_GO2SX_WITH_WAKE, 0x8FFFF)){
+                        // restore PCIE root port power state back to D3
+                        RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+                        RegVal8 |= B_PCH_PCIE_PMCS_PS;
+                        SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+                        
+                        return SMM_CHILD_DISPATCH_TIMEOUT;
+                    }
+                    
+                    // restore PCIE root port power state back to D3
+                    RegVal8 = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04));
+                    RegVal8 |= B_PCH_PCIE_PMCS_PS;
+                    SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, (PowerManagerCapOffset + 0x04)) = RegVal8;
+                }
+            }// end of AIC support
+            
+            //
+            // BIOS support of Thunderbolt devices Specification Update Revision 1.4
+            // 2.3.2.1 Sx Entry flow for RR/FR/WR Hosts with Thunderbolt wake support
+            
+            //UpPortBus = SmiPci8(0x00, gTbtBus, gTbtDev, gTbtFun, PCI_SBUS);
+            //if (!TbtSetPCIe2TBTCommand(UpPortBus, 0, TBT_GO2SX_WITH_WAKE, 0x8FFFF))
+            //   return SMM_CHILD_DISPATCH_NO_MEDIA;
+        }
+    }
+    
+    return SMM_CHILD_DISPATCH_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InSmmFunction
+//
+// Description: Installs TBT SMM Child Dispatcher Handler.
+//
+// Input:       ImageHandle  - Image handle
+//              *SystemTable - Pointer to the system table
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS InSmmFunction (
+    IN EFI_HANDLE           ImageHandle,
+    IN EFI_SYSTEM_TABLE     *SystemTable )
+{
+    EFI_STATUS                             Status;
+    EFI_HANDLE                             SwHandle = NULL;
+    EFI_HANDLE                             hS1Smi   = NULL;
+    EFI_HANDLE                             hS3Smi   = NULL;
+    EFI_HANDLE                             hS4Smi   = NULL;
+    EFI_HANDLE                             hS5Smi   = NULL;
+    EFI_HANDLE                             hPBSmi   = NULL;
+    AMI_SMM_SW_DISPATCH_PROTOCOL           *SwDispatch;
+    AMI_SMM_SX_DISPATCH_PROTOCOL           *SxDispatch;
+    AMI_SMM_POWER_BUTTON_DISPATCH_PROTOCOL *PowerButton;
+    AMI_SMM_SW_DISPATCH_CONTEXT            SwContext;
+    AMI_SMM_SX_DISPATCH_CONTEXT            S1DispatchContext  = {SxS1, SxEntry};
+    AMI_SMM_SX_DISPATCH_CONTEXT            S3DispatchContext  = {SxS3, SxEntry};
+    AMI_SMM_SX_DISPATCH_CONTEXT            S4DispatchContext  = {SxS4, SxEntry};
+    AMI_SMM_SX_DISPATCH_CONTEXT            S5DispatchContext  = {SxS5, SxEntry};
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+    AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT  PwrContext         = {EfiPowerButtonEntry};
+#else
+    AMI_SMM_POWER_BUTTON_DISPATCH_CONTEXT  PwrContext         = {PowerButtonEntry};
+    EFI_SMM_BASE_PROTOCOL                  *SmmBaseProtocol;
+#endif
+
+#if defined ULT_SUPPORT && ULT_SUPPORT == 1
+    UINT8 Data;
+
+    if (IsULTPchSeries()){
+       // Enable Thunderbolt Hotplug Pin SCI route for ULT platform
+       Data = IoRead8(GPIO_BASE_ADDRESS + R_PCH_LP_LPC_GPI_ROUT0 + gTbtHotPlugEvent/8);
+       Data = Data & ~(BIT00 << (gTbtHotPlugEvent%8));
+       IoWrite8(GPIO_BASE_ADDRESS + R_PCH_LP_LPC_GPI_ROUT0 + gTbtHotPlugEvent/8, Data);
+    }
+    else{
+       // Enable Thunderbolt Hotplug Pin SCI route
+       SmiPci8Or( 0x00, 0x00, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, (R_PCH_LPC_GPI_ROUT + gTbtHotPlugEvent/4), (0x2 << (gTbtHotPlugEvent%4)*2) );
+    }
+#else
+    // Enable Thunderbolt Hotplug Pin SCI route
+    SmiPci8Or( 0x00, 0x00, PCI_DEVICE_NUMBER_PCH_LPC, PCI_FUNCTION_NUMBER_PCH_LPC, (R_PCH_LPC_GPI_ROUT + gTbtHotPlugEvent/4), (0x2 << (gTbtHotPlugEvent%4)*2) );
+#endif
+
+    // Presence Detect Changed Enable
+    SmiPci8Or( 0x00, gTbtBus, gTbtDev, gTbtFun, R_PCH_PCIE_SLCTL, 0x08);
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+
+    Status  = pSmst2->SmmLocateProtocol( &gEfiSmmSwDispatch2ProtocolGuid, \
+                                          NULL, \
+                                          &SwDispatch );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status = pSmst2->SmmLocateProtocol( &gEfiSmmSxDispatch2ProtocolGuid , \
+                                       NULL, \
+                                       &SxDispatch );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status  = pSmst2->SmmLocateProtocol( &gEfiSmmPowerButtonDispatch2ProtocolGuid, \
+                                        NULL, \
+                                        &PowerButton );
+    if (EFI_ERROR(Status)) return Status;
+#else
+    Status = pBS->LocateProtocol( &gEfiSmmBaseProtocolGuid, \
+                                  NULL, \
+                                  &SmmBaseProtocol );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status = pBS->LocateProtocol( &gEfiSmmSwDispatchProtocolGuid, \
+                                  NULL, \
+                                  &SwDispatch );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status = pBS->LocateProtocol( &gEfiSmmSxDispatchProtocolGuid, \
+                                  NULL, \
+                                  &SxDispatch );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status = pBS->LocateProtocol( &gEfiSmmPowerButtonDispatchProtocolGuid,
+                                  NULL,
+                                  &PowerButton);
+    if (EFI_ERROR(Status)) return Status;
+#endif
+
+    SwContext.SwSmiInputValue = TBT_SWSMI_VALUE;
+    Status = SwDispatch->Register (
+                          SwDispatch,
+                          ThunderboltSwSmiCallback,
+                          &SwContext,
+                          &SwHandle );
+    if (EFI_ERROR(Status)) return Status;
+
+    if (gTbtEnable == FALSE){
+        TRACE((-1, "TbtSmm.c: Thunderbolt function is disable in Setup.\n"));
+        TRACE((-1, "TbtSmm.c: Only register Tbt SwSMI for debug.\n"));
+        return EFI_SUCCESS;
+    }
+
+    Status = SxDispatch->Register(
+                          SxDispatch, \
+                          TbtGo2SxCallback, \
+                          &S3DispatchContext, \
+                          &hS3Smi );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status = SxDispatch->Register(
+                          SxDispatch, \
+                          TbtGo2SxCallback, \
+                          &S4DispatchContext, \
+                          &hS4Smi );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status = SxDispatch->Register(
+                          SxDispatch, \
+                          TbtGo2SxCallback, \
+                          &S5DispatchContext, \
+                          &hS5Smi );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status = PowerButton->Register( 
+                           PowerButton,
+                           TbtPowerButtonCallback,
+                           &PwrContext,
+                           &hPBSmi );
+    if (EFI_ERROR(Status)) return Status;
+
+    return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   TbtSmm_Init
+//
+// Description: Installs TBT SMM Child Dispatcher Handler.
+//
+// Input:       ImageHandle  - Image handle
+//              *SystemTable - Pointer to the system table
+//
+// Output:      EFI_STATUS
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS TbtSmm_Init (
+    IN EFI_HANDLE           ImageHandle,
+    IN EFI_SYSTEM_TABLE     *SystemTable )
+{
+    EFI_STATUS                         Status = EFI_SUCCESS;
+    EFI_GUID                           AmiTbtPlatformPolicyGuid = AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID;
+    BOOLEAN                            InSmram = FALSE;
+    AMI_TBT_PLATFORM_POLICY_PROTOCOL   *AmiTbtPlatformPolicy = NULL;
+    UINTN                              HRStatusSize     = sizeof(AMI_TBT_HR_STATUS_DATA);
+    CHAR16                             TbtHRStatusVar[] = TBT_HR_STATUS_VARIABLE;
+    AMI_TBT_HR_STATUS_DATA             HRStatusData;
+
+    InitAmiLib(ImageHandle, SystemTable);
+
+    Status = pBS->LocateProtocol( \
+                        &AmiTbtPlatformPolicyGuid, \
+                        NULL, \
+                        &AmiTbtPlatformPolicy );
+
+    if (!EFI_ERROR(Status)) {
+      gCacheLineSize          = AmiTbtPlatformPolicy->CacheLineSize;
+      gTbtBus                 = AmiTbtPlatformPolicy->Bus;
+      gTbtDev                 = AmiTbtPlatformPolicy->Dev;
+      gTbtFun                 = AmiTbtPlatformPolicy->Fun;
+      gReserveMemoryPerSlot   = AmiTbtPlatformPolicy->ReserveMemoryPerSlot;
+      gReservePMemoryPerSlot  = AmiTbtPlatformPolicy->ReservePMemoryPerSlot;
+      gReserveIOPerSlot       = AmiTbtPlatformPolicy->ReserveIOPerSlot;
+      if (AmiTbtPlatformPolicy->TbtWakeupSupport)
+          gTbtWakeupSupport   = TRUE;
+      if (AmiTbtPlatformPolicy->TbtAICSupport)
+          gTbtAICSupport      = TRUE;
+      if (AmiTbtPlatformPolicy->TbtHandlePOC)
+          gTbtHandlePOC       = TRUE;
+      gTbtHotPlugEvent        = AmiTbtPlatformPolicy->TbtHotPlugEvt;
+      if (AmiTbtPlatformPolicy->TbtIOresourceEnable)
+          gTbtIOresourceEnable = TRUE;
+      gTbtNVMversion          = AmiTbtPlatformPolicy->TbtNVMversion;
+      if (AmiTbtPlatformPolicy->TbtEnable)
+          gTbtEnable           = TRUE;
+
+      // Convert slot resource to register format
+      gReserveMemoryPerSlot  <<= 4;
+      gReservePMemoryPerSlot <<= 4;
+      gReserveIOPerSlot      <<= 2;
+      TRACE((-1, "TbtSmm.c: gReserveMemoryPerSlot  = %x\n", gReserveMemoryPerSlot));
+      TRACE((-1, "TbtSmm.c: gReservePMemoryPerSlot = %x\n", gReservePMemoryPerSlot));
+      TRACE((-1, "TbtSmm.c: gReserveIOPerSlot      = %x\n", gReserveIOPerSlot));
+    }
+
+    // Init Tbt Host Information in SMM RAM
+    Status = pRS->GetVariable( L"TbtHRStatusVar", \
+                               &TbtHRStatusGuid, \
+                               &AmiTbtHrStatusAttribute, \
+                               &HRStatusSize, \
+                               &HRStatusData );
+    if (!EFI_ERROR(Status)){
+       if (HRStatusData.TbtHRSeries == Cactus_Ridge) HostDeviceId = 0x1548;
+       else if (HRStatusData.TbtHRSeries == Redwood_Ridge) HostDeviceId = 0x1567;
+       else if (HRStatusData.TbtHRSeries == Falcon_Ridge) HostDeviceId = 0x156B;
+       else HostDeviceId = 0x157E;
+    }
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+    Status = pBS->LocateProtocol( \
+                    &gEfiSmmBase2ProtocolGuid, \
+                    NULL, \
+                    &gSmmBase2 );
+
+    if (!EFI_ERROR(Status))
+    {
+        Status = gSmmBase2->InSmm(gSmmBase2, &InSmram);
+        if ((!EFI_ERROR(Status)) &&
+            (InSmram))
+        {
+            Status = InitAmiSmmLib( ImageHandle, SystemTable );
+            if (EFI_ERROR(Status))
+                return Status;
+
+            Status = gSmmBase2->GetSmstLocation(gSmmBase2, &pSmst2);
+            if (!EFI_ERROR(Status))
+            {
+                Status = InSmmFunction(ImageHandle, SystemTable);
+                return Status;
+            }
+            else
+            {
+                pSmst2 = NULL;
+            }
+        }
+        else
+        {
+            // DXE initialize.
+        }
+    }
+
+    return EFI_SUCCESS;
+#else
+    return InitSmmHandler(ImageHandle, SystemTable, InSmmFunction, NULL);
+#endif
+}
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2014, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtSmm/TbtSmm.cif b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.cif
new file mode 100644
index 0000000..92a02d4
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.cif
@@ -0,0 +1,11 @@
+<component>
+	name = "TbtSmm"
+	category = ModulePart
+	LocalRoot = "Board\EM\Thunderbolt\TbtSmm\"
+	RefName = "TbtSmm"
+[files]
+"TbtSmm.sdl"	
+"TbtSmm.mak"	
+"TbtSmm.c"	
+"TbtSmm.dxs"	
+<endComponent>
diff --git a/Board/EM/Thunderbolt/TbtSmm/TbtSmm.dxs b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.dxs
new file mode 100644
index 0000000..36857a6
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.dxs
@@ -0,0 +1,83 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtSmm/TbtSmm.dxs 1     1/10/13 4:56a Barretlin $
+//
+// $Revision: 1 $
+//
+// $Date: 1/10/13 4:56a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtSmm/TbtSmm.dxs $
+// 
+// 1     1/10/13 4:56a Barretlin
+// Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+// Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+// 
+// 4     9/03/12 6:27a Barretlin
+// [TAG]  		EIP N/A
+// [Category]  	Improvement
+// [Description]  	Change driver type and dependence for SharkBay platform
+// [Files]  		TbtSmm.mak TbtSmm.c TbtSmm.dxs
+// 
+// 3     6/12/12 11:30p Barretlin
+// [TAG]  		None
+// [Category]  	Improvement
+// [Description]  	fix programming error
+// [Files]  		TbtSmm.dxs
+// 
+// 2     12/22/11 9:15a Wesleychen
+// Included "token.h".
+// 
+// 1     12/08/11 4:09a Wesleychen
+// Thunderbolt eModule initially releases.
+// 
+//**********************************************************************
+#include <token.h>
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+#include <Protocol\SmmBase2.h>
+#include <Protocol\SmmSwDispatch2.h>
+#include <Protocol\SmmSxDispatch2.h>
+#else
+#include <Protocol\SmmSwDispatch.h>
+#include <Protocol\SmmSxDispatch.h>
+#endif
+#include <TbtOemBoard.h>
+
+DEPENDENCY_START
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)&&(CORE_COMBINED_VERSION >= 0x4028B)
+    EFI_SMM_BASE2_PROTOCOL_GUID AND
+    EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID AND
+    EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID AND
+#else
+    EFI_SMM_SW_DISPATCH_PROTOCOL_GUID AND
+    EFI_SMM_SX_DISPATCH_PROTOCOL_GUID AND
+#endif
+    AMI_TBT_PLATFROM_POLICY_PROTOCOL_GUID
+DEPENDENCY_END
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/EM/Thunderbolt/TbtSmm/TbtSmm.mak b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.mak
new file mode 100644
index 0000000..ec271c9
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.mak
@@ -0,0 +1,113 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtSmm/TbtSmm.mak 3     6/21/13 7:44a Barretlin $
+#
+# $Revision: 3 $
+#
+# $Date: 6/21/13 7:44a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtSmm/TbtSmm.mak $
+# 
+# 3     6/21/13 7:44a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Fix build error with non Intel RC project
+# [Files]  		TbtSmm.mak
+# 
+# 2     6/13/13 11:36p Barretlin
+# [TAG]  		EIP None
+# [Category]  	Improvement
+# [Description]  	change obj file name to avoid ambiguous
+# [Files]  		TbtSmm.mak
+# 
+# 1     1/10/13 4:56a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 3     10/04/12 11:53a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Use global definition for genernic
+# [Files]  		TbtSmm.c TbtSmm.mak
+# 
+# 2     9/03/12 6:27a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Change driver type and dependence for SharkBay platform
+# [Files]  		TbtSmm.mak TbtSmm.c TbtSmm.dxs
+# 
+# 1     12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+# 
+#**********************************************************************
+#<AMI_FHDR_START>
+#
+# Name:	TbtSmm.mak
+#
+# Description:	
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+all : TbtSmm
+
+TbtSmm: $(BUILD_DIR)\TbtSmm.mak TbtSmmBin
+
+TBT_SMM_OBJECTS = \
+!IF $(TBT_INTEL_RC_CONFIG) == 1
+$(BUILD_SB_BOARD_DIR)\GetSetupData.obj \
+!ENDIF
+$(BUILD_DIR)\$(TbtSmm_DIR)\TbtSmm.obj
+
+$(BUILD_DIR)\TbtSmm.mak : $(TbtSmm_DIR)\TbtSmm.cif $(TbtSmm_DIR)\$(@B).mak $(BUILD_RULES)
+    $(CIF2MAK) $(TbtSmm_DIR)\TbtSmm.cif $(CIF2MAK_DEFAULTS)
+
+TbtSmm_INCLUDES=\
+    $(TBT_OEMBOARD_INCLUDES)\
+!IF $(TBT_INTEL_RC_CONFIG) == 1
+    $(INTEL_PCH_INCLUDES)\
+!ENDIF
+
+TbtSmmBin : $(AMIDXELIB) $(AMICSPLib)
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+        /f $(BUILD_DIR)\TbtSmm.mak all\
+        "CFLAGS=$(CFLAGS)"\
+        OBJECTS="$(TBT_SMM_OBJECTS)" \
+        GUID=B7D9F0D7-EBDB-4EE4-AB77-B30C4B9093CC\
+        ENTRY_POINT=TbtSmm_Init\
+        "MY_INCLUDES=$(TbtSmm_INCLUDES)"\
+!IF $(PI_SPECIFICATION_VERSION) >= 0x1000A && $(CORE_COMBINED_VERSION) >= 0x4028B
+        TYPE=DXESMM_DRIVER PE_TYPE=RT_DRIVER \
+        DEPEX1=$(TbtSmm_DIR)\TbtSmm.DXS DEPEX1_TYPE=EFI_SECTION_SMM_DEPEX \
+        DEPEX2=$(TbtSmm_DIR)\TbtSmm.DXS DEPEX2_TYPE=EFI_SECTION_DXE_DEPEX \
+!ELSE
+        TYPE=BS_DRIVER \
+        DEPEX1=$(TbtSmm_DIR)\TbtSmm.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \
+!ENDIF
+        COMPRESS=1
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/TbtSmm/TbtSmm.sdl b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.sdl
new file mode 100644
index 0000000..c4f98b1
--- /dev/null
+++ b/Board/EM/Thunderbolt/TbtSmm/TbtSmm.sdl
@@ -0,0 +1,120 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#*************************************************************************
+# $Header: /Alaska/SOURCE/Modules/Thunderbolt/TbtSmm/TbtSmm.sdl 2     12/25/13 6:06a Barretlin $
+#
+# $Revision: 2 $
+#
+# $Date: 12/25/13 6:06a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Modules/Thunderbolt/TbtSmm/TbtSmm.sdl $
+# 
+# 2     12/25/13 6:06a Barretlin
+# [TAG]  		EIP N/A
+# [Category]  	Improvement
+# [Description]  	Using token to enable/disable double check TBT host
+# router state in SxSMI/PowerButtonSMI
+# [Files]  		TbtSmm.sdl TbtSmm.c
+# 
+# 1     1/10/13 4:56a Barretlin
+# Change SS path and update module for Thunderbolt Spec 1.6 for Cactus
+# Ridge chip and Thunderbolt Spec 0.5 for Redwood Ridge chip
+# 
+# 3     5/07/12 6:44a Barretlin
+# [TAG]  		None
+# [Category]  	Improvement
+# [Description]  	Change SwSMI value avoiding conflict
+# [Files]  		TbtSmm.sdl
+# 
+# 2     2/20/12 4:45a Wesleychen
+# Add new SDL token "TBT_SWSMI_DELAY" for debug.
+# 
+# 1     12/08/11 4:09a Wesleychen
+# Thunderbolt eModule initially releases.
+# 
+#*************************************************************************
+TOKEN
+	Name  = TbtSmm_SUPPORT
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+	Help  = "Main switch to enable TbtSmm support in Project"
+End
+
+TOKEN
+	Name  = "TBT_SWSMI_VALUE"
+	Value  = "0xBC"
+	Help  = "Thunderbolt SWSMI value"
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBSW"
+	Value  = "$(TBT_SWSMI_VALUE)"
+	Help  = "Thunderbolt SWSMI value"
+	TokenType = Integer
+	TargetASL = Yes
+End
+
+TOKEN
+	Name  = "TBT_HR_SX_CHECK"
+	Value  = "0"
+	Help  = "Double check Thunderbolt host router status in SxSMI/PowerButton SMI"
+	TokenType = Integer
+	TargetH = Yes
+End
+
+MODULE
+	Help  = "Includes TbtSmm.mak to Project"
+	File  = "TbtSmm.mak"
+End
+
+PATH
+	Name  = "TbtSmm_DIR"
+End
+
+ELINK
+	Name  = "/I$(TbtSmm_DIR)"
+	Parent  = "TBT_SMM_INCLUDES"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "TBT_SMM_INCLUDES"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\TbtSmm.ffs"
+	Parent  = "FV_MAIN"
+	InvokeOrder = AfterParent
+End
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2012, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
\ No newline at end of file
diff --git a/Board/EM/Thunderbolt/Thunderbolt.cif b/Board/EM/Thunderbolt/Thunderbolt.cif
new file mode 100644
index 0000000..afe5c07
--- /dev/null
+++ b/Board/EM/Thunderbolt/Thunderbolt.cif
@@ -0,0 +1,14 @@
+<component>
+	name = "Thunderbolt"
+	category = eModule
+	LocalRoot = "Board\EM\Thunderbolt\"
+	RefName = "Thunderbolt"
+[files]
+"Thunderbolt.sdl"	
+"ReleaseNotes.chm"	
+[parts]
+"TbtPei"
+"TbtDxe"
+"TbtSmm"
+"TbtOemBoard"
+<endComponent>
diff --git a/Board/EM/Thunderbolt/Thunderbolt.sdl b/Board/EM/Thunderbolt/Thunderbolt.sdl
new file mode 100644
index 0000000..2d7c45c
--- /dev/null
+++ b/Board/EM/Thunderbolt/Thunderbolt.sdl
@@ -0,0 +1,116 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+TOKEN
+	Name  = "Thunderbolt_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable Thunderbolt support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+    Token = "HOTPLUG_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "Thunderbolt_CR_VERSION"
+	Value  = "16"
+	Help  = "Thunderbolt Spec Version for Cactus Ridge chip."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "Thunderbolt_RR_VERSION"
+	Value  = "10"
+	Help  = "Thunderbolt Spec Version for Redwood Ridge chip."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "Thunderbolt_FR_VERSION"
+	Value  = "11"
+	Help  = "Thunderbolt Spec Version for Falcon Ridge chip."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "Thunderbolt_WR_VERSION"
+	Value  = "10"
+	Help  = "Thunderbolt Spec Version for BDW-TBT-LP chip."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "TBT_RC_VERSION"
+	Value  = "19"
+	Help  = "Thunderbolt RC Version."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TBT_INTEL_RC_CONFIG"
+	Value  = "1"
+	Help  = "If set, it means PCH and ACPI platform modules are using Intel RC"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+PATH
+	Name  = "Thunderbolt_DIR"
+End
+
+ELINK
+	Name  = "TBT_INCLUDES"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "/I$(Thunderbolt_DIR)"
+	Parent  = "TBT_INCLUDES"
+	InvokeOrder = AfterParent
+End
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************