init. 1AQQW051HEADmaster

10 files changed, 4267 insertions, 0 deletions

diff --git a/Board/Flash/SPI/ICHx/ICHxSpi.sdl b/Board/Flash/SPI/ICHx/ICHxSpi.sdl
new file mode 100644
index 0000000..d145678
--- /dev/null
+++ b/Board/Flash/SPI/ICHx/ICHxSpi.sdl
@@ -0,0 +1,86 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#**********************************************************************
+# $Header: /Alaska/SOURCE/Flash_Combined_2/CSP_SPI/Intel/ICHx/ICHxSpi.sdl 3     9/14/10 3:25a Calvinchen $
+#
+# $Revision: 3 $
+#
+# $Date: 9/14/10 3:25a $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/SOURCE/Flash_Combined_2/CSP_SPI/Intel/ICHx/ICHxSpi.sdl $
+# 
+# 3     9/14/10 3:25a Calvinchen
+# Added the "SPI_INITIALIAL_WITH_VSCC" token for VSCC register
+# initialize.
+# 
+# 2     6/24/09 3:25a Calvinchen
+# (EIP22177) Updated for Aptio Source Enhancement.
+#
+#
+#**********************************************************************
+
+TOKEN
+	Name  = "ICHx_SPI_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable ICHx SPI support in Project"
+	TokenType = Boolean
+	Master = Yes
+End
+
+TOKEN
+	Name  = "SPI_INITIALIZE_WITH_VSCC"
+	Value  = "0"
+	Help  = "Program Host Lower/Upper Vendor Specific Component Capabilities Register."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "LOWER_VSCC_REG"
+	Value  = "0xC4"
+	Help  = "Host Lower Vendor Specific Component Capabilities Register."
+	TokenType = Integer
+	TargetH = Yes
+	Token = "SPI_INITIALIZE_WITH_VSCC" "=" "1"
+End
+
+TOKEN
+	Name  = "UPPER_VSCC_REG"
+	Value  = "0xC8"
+	Help  = "Host Upper Vendor Specific Component Capabilities Register."
+	TokenType = Integer
+	TargetH = Yes
+	Token = "SPI_INITIALIZE_WITH_VSCC" "=" "1"
+End
+
+PATH
+	Name  = "SPI_CSP_DIR"
+End
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
\ No newline at end of file
diff --git a/Board/Flash/SPI/ICHx/SPIFlash.c b/Board/Flash/SPI/ICHx/SPIFlash.c
new file mode 100644
index 0000000..022e2ae
--- /dev/null
+++ b/Board/Flash/SPI/ICHx/SPIFlash.c
@@ -0,0 +1,1369 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/ICHx/SPIFlash.c 1     11/02/17 1:44a Chienhsieh $
+//
+// $Revision: 1 $
+//
+// $Date: 11/02/17 1:44a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/ICHx/SPIFlash.c $
+// 
+// 1     11/02/17 1:44a Chienhsieh
+// [TAG]  		EIP358409
+// [Category]  	Improvement
+// [Description]  	[SAx0039][Flash_17/16/14/11/10/09/08/7] SPI security
+// [Files]  		Board\Flash\SPI\ICHx\SPIFlash.c
+// 
+// 19    6/10/13 5:26a Calvinchen
+// [TAG]  		EIPNone
+// [Category]  	Bug Fix
+// [Severity]  	Important
+// [Symptom]  	System hangs in EFI OS if Nvram Garbage collection occurred
+// [RootCause]  	RCBA base don't convert to virtual address causes system
+// hangs at checking TOP_SWAP bit.
+// [Solution]  	Need to convert RCBA base.
+// [Files]  		SPIFlash.c
+// 
+// 18    3/08/13 3:37a Calvinchen
+// [TAG]  		EIP110515
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	Microchip SST26VF064B & SST26VF064BA 8MB SPI Flash part
+// support 
+// [RootCause]  	Need "Global Block Protection Unlock" before programming.
+// [Solution]  	Added "Global Block Protection Unlock" before programming.
+// [Files]  		SPIFlash.c
+// 
+// 17    12/11/12 5:54a Calvinchen
+// [TAG]  		EIP108531
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	Unable to use AMI Flash Lib inside DXE Core
+// [RootCause]  	Procedure Name duplicated
+// [Solution]  	Rename IoDelay to SpiIoDelay
+// [Files]  		SpiFlash.c
+// 
+// 16    10/31/12 3:08a Calvinchen
+// [TAG]  		EIP104018
+// [Category]  	Improvement
+// [Description]  	Changes for Top Swap enabled.
+// [Files]  		SpiFlash.c
+// 
+// 15    10/18/12 3:05a Calvinchen
+// Added SFDP support for VSCC.
+// 
+// 14    9/25/12 12:10a Calvinchen
+// [TAG]  		EIP97017
+// [Category]  	Improvement
+// [Description]  	1. MahoBay Flash error fail save
+// 2. Keep Quad Enable bit (Bit6) of Status Register for MXIC flash.
+// [Files]  		SPIFlash.c
+// 
+// 13    1/12/12 1:08a Calvinchen
+// [TAG]  		EIP80707
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	Flash Error
+// [RootCause]  	Coding Mistake.
+// [Solution]  	Fix coding mistake.
+// [Files]  		SPIFlash.c
+// 
+// 12    2/10/11 3:27a Calvinchen
+// Bug Fixed : (EIP#53185)Reading 64 Bytes failed if cross over 4K
+// boundary.
+// Description : This is supposed to be an ICH/PCH limitation.
+// 
+// 11    10/25/10 9:41a Calvinchen
+// Very Slow SPI Read Byte Access.
+// 
+// 10    10/25/10 6:22a Calvinchen
+// (EIP45843)Very Slow SPI Read Byte Access.
+// 
+// 9     9/14/10 3:25a Calvinchen
+// Added the "SPI_INITIALIAL_WITH_VSCC" token for VSCC register
+// initialize.
+// 
+// 8     5/21/10 2:14a Calvinchen
+// Bug fixed: Build failed with "undeclared identifier".
+// 
+// 7     3/11/10 6:41a Calvinchen
+// Improvement : Added SST AAIWordProgram SPI command to speed up the
+// programming time with Intel chipset.
+// 
+// 6     6/24/09 3:25a Calvinchen
+// (EIP22177) Updated for Aptio Source Enhancement.
+//
+// 5     4/27/09 3:30a Calvinchen
+// 2.(EIP20459) Added Multiple SPI CSP component support.
+//
+// 4     12/03/08 1:00a Calvinchen
+// (EIP17945)Bug Fixed : Fail to unlock the BIOS region of Flash
+// Descriptor.
+//
+// 3     8/26/08 3:02a Calvinchen
+// 1.Fixed Fail to un-protect ATMEL flash.
+// 2.Fixed Building failed if ICH_FDOC/FDOD not defined.
+// 3.Increase the Timeout counter for waiting the ICH SPI cycle done.
+//
+// 2     6/26/08 6:56a Calvinchen
+// Generic bug fixed.
+//
+// 1     3/13/08 6:37a Calvinchen
+// Added support for Intel ICHx SPI.
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//
+// Name:    FlashWrite.c
+//
+// Description: Flash update routines
+//
+//<AMI_FHDR_END>
+//**********************************************************************
+//----------------------------------------------------------------------------
+// Includes
+#include <efi.h>
+#include <AmiDxeLib.h>
+#include "FlashPart.h"
+#include "SpiFlash.h"
+#include "token.h"
+//----------------------------------------------------------------------------
+// Local defines for transaction types
+// ICH8/9/10 SPI register defines.
+#define     SPI_STS                     0x90    //  SPI Status
+#define     SPI_CTL                     0x91    //  SPI Control
+#define     SPI_ADR                     0x08    //  SPI Address
+#define     SPI_DAT0                    0x10    //  SPI Data 0
+#define     SPI_PREOP                   0x94    //  Prefix Opcode Configuration
+#define     SPI_OPTYPE                  0x96    //  Opcode Type Configuration
+#define     SPI_OPMENU                  0x98    //  Opcode Menu Configuration
+#define     RCRB_MMIO_BUC               0x3414  //  Backed Up Control Register
+//  SPI default opcode slots
+#define     SPI_OPCODE_WRITE_INDEX      0x0
+#define     SPI_OPCODE_READ_INDEX       0x1
+#define     SPI_OPCODE_ERASE_INDEX      0x2
+#define     SPI_OPCODE_READ_S_INDEX     0x3
+#define     SPI_OPCODE_READ_ID_INDEX    0x4
+#define     SPI_OPCODE_WRITE_S_INDEX    0x5
+#define     SPI_OPCODE_WRITE_S_E_INDEX  0x6
+#define     SPI_OPCODE_WRITE_E_INDEX    0x7
+#define     SPI_OPCODE_AAI_INDEX        0x6
+#define     SPI_OPCODE_WRITE_D_INDEX    0x7
+#define     SPI_PREFIX_WRITE_S_EN       0x1
+#define     SPI_PREFIX_WRITE_EN         0x0
+#define     SPI_MAX_DATA_TRANSFER       0x40
+#define     ICHX_FDOC                   0xb0    // Flash Descriptor Observability Control Register
+#define     ICHX_FDOD                   0xb4    // Flash Descriptor Observability Data Register
+#define     FLASH_VALID_SIGNATURE       0x0ff0a55a
+#define     NO_ADDRESS_UPDATE           0
+#ifndef     SPI_OPCODE_TYPE_READ_NO_ADDRESS
+#define     SPI_OPCODE_TYPE_READ_NO_ADDRESS     0x0
+#define     SPI_OPCODE_TYPE_WRITE_NO_ADDRESS    0x1
+#define     SPI_OPCODE_TYPE_READ_WITH_ADDRESS   0x2
+#define     SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS  0x3
+#endif
+#define     SPI_FLASH_DEVICE_BASE_ADDRESS       (0xFFFFFFFF-FLASH_SIZE+1)   // [ EIP358409 ]
+//----------------------------------------------------------------------------
+// Module level global data
+extern UINT16       gFlashId;
+extern FLASH_PART   *FlashAPI;
+//----------------------------------------------------------------------------
+// Function Externs
+extern
+VOID
+SpiChipsetVirtualFixup  (
+    IN EFI_RUNTIME_SERVICES *pRS
+);
+//----------------------------------------------------------------------------
+// Local prototypes
+VOID
+CommonSpiEraseCommand   (
+    volatile UINT8          *pBlockAddress
+);
+VOID
+CommonSpiProgramCommand (
+    volatile UINT8          *pByteAddress,
+    UINT8                   *Byte,
+    UINT32                  *Length
+);
+VOID
+CommonSpiReadCommand    (
+    volatile UINT8          *pByteAddress,
+    UINT8                   *Byte,
+    UINT32                  *Length
+);
+BOOLEAN
+CommonSpiIsEraseCompleted   (
+    volatile UINT8          *pBlockAddress,
+    BOOLEAN                 *pError,
+    UINTN                   *pStatus
+);
+BOOLEAN
+CommonSpiIsProgramCompleted (
+    volatile UINT8          *pByteAddress,
+    UINT8                   *Byte,
+    UINT32                  Length,
+    BOOLEAN                 *pError,
+    UINTN                   *pStatus
+);
+VOID
+CommonSpiBlockWriteEnable   (
+    volatile UINT8          *pBlockAddress
+);
+VOID
+CommonSpiBlockWriteDisable  (
+    volatile UINT8          *pBlockAddress
+);
+VOID
+CommonSpiDeviceWriteEnable  (
+    VOID
+);
+VOID
+CommonSpiDeviceWriteDisable (
+    VOID
+);
+VOID
+CommonSpiDeviceVirtualFixup (
+    EFI_RUNTIME_SERVICES    *pRS
+);
+// [ EIP358409 ]+>>>
+VOID
+SpiBlockProtectUpdate (
+    IN volatile UINT8           *pBlockAddress,
+    IN UINT8                    bStatusData
+);
+// [ EIP358409 ]+<<<
+//----------------------------------------------------------------------------
+// Local Variables
+FLASH_PART mCommonSpiFlash ={
+    CommonSpiReadCommand,
+    CommonSpiEraseCommand,
+    CommonSpiProgramCommand,
+    CommonSpiIsEraseCompleted,
+    CommonSpiIsProgramCompleted,
+    CommonSpiBlockWriteEnable,
+    CommonSpiBlockWriteDisable,
+    CommonSpiDeviceWriteEnable,
+    CommonSpiDeviceWriteDisable,
+    CommonSpiDeviceVirtualFixup,
+    1,                      // default value, should be changed in Init function
+    SECTOR_SIZE_4KB
+};
+EX_FLASH_PART mExFlashPart = {
+      {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},0,0},
+      FLASH_SIZE,           // flash size, should be changed in Init function
+      0,                    // flash part id, should be changed in Init function
+      0                     // flash part string, should be changed in
+                            // Init function
+};
+volatile UINT8  *gSPIBASE = (UINT8*)(UINTN)(SB_RCBA + SPI_BASE_ADDRESS);
+volatile UINT8  *gRCBABASE = (UINT8*)(UINTN)SB_RCBA;
+UINT8           gbDeviceVirtual = 0;
+UINT8           gbDeviceWriteEnabled = 0;
+//----------------------------------------------------------------------------
+// Function Definitions
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   SpiIoDelay
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+SpiIoDelay (VOID)
+{
+    UINT8               bTimeout;
+    for ( bTimeout = 0; bTimeout < 33; bTimeout++ ) {
+        IoWrite8( 0xEB, 0x55 );
+        IoWrite8( 0xEB, 0xAA );
+    }
+    return ;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   WaitForSpiCycleDone
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+WaitForSpiCycleDone (VOID)
+{
+    UINT32              dTimeout;
+    UINT8               bCyclyDone;
+
+    for ( dTimeout = 0, bCyclyDone = 0; dTimeout < 0x4000000; dTimeout++ ) {
+        bCyclyDone = *(volatile UINT8*)( gSPIBASE + SPI_STS );
+        if ( bCyclyDone & BIT02 ) break;
+    }
+    // write BIT2 to clear CycleDone status
+    *(volatile UINT8*)( gSPIBASE + SPI_STS ) = BIT02;
+
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   SpiWriteDisable
+//
+// Description: This procedure issuess SPI Write Disable if AAIWordProgram. 
+//
+// Input:       None.
+//
+// Output:      None.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID SpiWriteDisable (VOID)
+{
+    // Opcode menu slot 7 is configured as "Write Disable" if AAIWordProgram.
+    *(volatile UINT16*)(gSPIBASE + SPI_CTL) = \
+                                ( SPI_OPCODE_WRITE_D_INDEX << 4) + BIT01;
+    // wait for chipset SPI cycle completed.
+    WaitForSpiCycleDone();
+    return ;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CheckAaiWordProram
+//
+// Description: This procedure checks whether issues the AAIWordProgram command. 
+//
+// Input:       dAddr   - Start address to be written.
+//              dLength - Number of bytes to be written.
+//
+// Output:      TRUE    - Yes
+//              FALSE   - No
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+CheckAaiWordProram (
+    IN UINT32               dAddr,
+    IN UINT32               dLength
+)
+{
+    if ((mExFlashPart.AAIWordProgram != 0) && !(dAddr & 1) && (dLength >= 2))
+        return TRUE;
+    return FALSE;    
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonSpiReadStatus
+//
+// Description:
+//
+// Input:       None.
+//
+// Output:      Status Register which is read from SPI flash.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8
+CommonSpiReadStatus   (
+    IN UINT32               dUpdateAddr
+)
+{
+    UINT16  wSpiCmd;
+
+    if( dUpdateAddr ) *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = dUpdateAddr;
+    // Opcode menu slot 3 is configured as "Read Status Register"
+    wSpiCmd = SPI_OPCODE_READ_S_INDEX << 4;
+    // indicate that data phase is required
+    wSpiCmd += (1 << 14);
+    // Set BIT1 (Go)
+    *(volatile UINT16*)( gSPIBASE + SPI_CTL ) =  wSpiCmd + BIT01;
+    // wait for spi cycle completed.
+    WaitForSpiCycleDone();
+    // return status register.
+    return ( *(volatile UINT8*)( gSPIBASE + SPI_DAT0 ) );
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   WaitForWriteOperationCompleted
+//
+// Description:
+//
+// Input:       None.
+//
+// Output:      None.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+WaitForWriteOperationCompleted (VOID)
+{
+    UINT16              wWaitStsRetry;
+    UINT8               bStatus;
+
+    for( wWaitStsRetry = 0; wWaitStsRetry < 0xFFFF; wWaitStsRetry++ ) {
+        // read flash status register.
+        bStatus = CommonSpiReadStatus( NO_ADDRESS_UPDATE );
+        // Is operation busy ?
+        if( !( bStatus & 0x1 ) ) break;
+    }
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonSpiWriteStatus
+//
+// Description: Routine for Write SPI Status Register.
+//
+// Input:       None.
+//
+// Output:      Status Register which is read from SPI flash.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiWriteStatus    (
+    IN UINT8                bWriteData,
+    IN UINT8                bOpcodeIndex,
+    IN UINT8                bIsDataPhase,
+    IN UINT8                bPrefixOp,
+    IN UINT32               dSectorAddress
+)
+{
+    UINT16  wSpiCmd;
+
+    *(volatile UINT8*)( gSPIBASE + SPI_DAT0 ) = bWriteData;
+    *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = dSectorAddress;
+    // Opcode menu slot 3 is configured as "Read Status Register"
+    wSpiCmd = bOpcodeIndex << 4;
+    // indicate that data phase is required
+    wSpiCmd += ( bIsDataPhase << 14 );
+    // BIT3(Preop 1)
+    wSpiCmd += ( bPrefixOp << 3 );
+    // Set BIT1 (Go), BIT2(Atomic w/ Prefix),
+    *(volatile UINT16*)( gSPIBASE + SPI_CTL ) =  wSpiCmd + BIT01 + BIT02;
+    // wait for spi cycle completed.
+    WaitForSpiCycleDone();
+    // wait for SPI flash operation completed.
+    WaitForWriteOperationCompleted();
+    // return status register.
+    return ;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonSpiReadByte
+//
+// Description:
+//
+// Input:       dByteAddress    Address that need to be read.
+//
+// Output:      BYTE            Value which is read from SPI flash.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8
+CommonSpiReadByte   (
+    IN UINT32               dByteAddress
+)
+{
+    UINT8           bData;
+    UINT32          dLength = sizeof(UINT8);
+    CommonSpiReadCommand((volatile UINT8*)dByteAddress, &bData, &dLength);
+    return bData;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonConvertSpiAddress
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+CommonConvertSpiAddress   (
+    IN  volatile UINT8      *pAddress,
+    OUT UINT32              *pdCnvtAddress
+)
+{
+    UINT32              dIchSpiFDOD;
+    static UINT32       gBiosRegionBase = 0, gBiosRegionLimit = 0;
+
+    // if flash identified, here checks the BIOS region of Flash
+    // Descriptor Table.
+    if ( mExFlashPart.FlashVenDevId ) {
+        if ( !gBiosRegionBase ) {
+            *(volatile UINT32*)( gSPIBASE + ICHX_FDOC ) = 0;
+            dIchSpiFDOD = *(volatile UINT32*)( gSPIBASE + ICHX_FDOD );
+            if ( dIchSpiFDOD == FLASH_VALID_SIGNATURE ) {
+                *(volatile UINT32*)( gSPIBASE + ICHX_FDOC ) = ( BIT13 + BIT02 );
+                do {
+                    dIchSpiFDOD = *(volatile UINT32*)( gSPIBASE + ICHX_FDOD );
+                } while( dIchSpiFDOD == FLASH_VALID_SIGNATURE );
+                gBiosRegionBase = ( ( (dIchSpiFDOD >> 16) + 1 ) << 12 );
+                gBiosRegionLimit = ((dIchSpiFDOD >> 4) | 0xfff) + 1;
+            }
+            else {
+                gBiosRegionBase = mExFlashPart.FlashCapacity;
+                gBiosRegionLimit = mExFlashPart.FlashCapacity;
+            }    
+        }
+    }
+    if ( gbDeviceVirtual ) {
+        // pAddress - offset from Flash Device Base.
+        pAddress -= FlashDeviceBase;
+        // pAddress - 32bit memory mapping address.
+        pAddress += (0xFFFFFFFF - FLASH_SIZE) + 1;
+    }
+    // pAddress - physical address in flash.
+    pAddress += gBiosRegionBase;
+    if ((UINT32)pAddress >= gBiosRegionLimit) return EFI_INVALID_PARAMETER;
+    *pdCnvtAddress = (UINT32)pAddress;
+    return EFI_SUCCESS;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InitializeSpiEnvironment
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+InitializeSpiEnvironment (
+    IN OUT  FLASH_INFO      *FlashInfo
+)
+{
+    //Program first DWORD of opcode commands
+    *((volatile UINT32*)( gSPIBASE + R_RCRB_SPI_OPMENU + 0 )) = (UINT32)
+        // Write Byte
+        ( (FlashInfo->Write.Opcode << (SPI_OPCODE_WRITE_INDEX * 8)) | \
+        // Read Data
+          (FlashInfo->Read.Opcode << (SPI_OPCODE_READ_INDEX * 8)) | \
+        // Erase 64k Sector
+          (FlashInfo->Erase.Opcode << (SPI_OPCODE_ERASE_INDEX * 8)) | \
+        // Read Device Status Reg
+          (FlashInfo->ReadStatus.Opcode << (SPI_OPCODE_READ_S_INDEX * 8)) );
+
+    //Program second DWORD of Opcode commands
+    *((volatile UINT32*)( gSPIBASE + R_RCRB_SPI_OPMENU + 4 )) = (UINT32)
+        // Read device ID
+      ((FlashInfo->ReadId.Opcode << ((SPI_OPCODE_READ_ID_INDEX - 4) * 8)) | \
+        // Write Status Register
+       (FlashInfo->WriteStatus.Opcode << \
+                                    ((SPI_OPCODE_WRITE_S_INDEX - 4) * 8)) | \
+        // Write Status Enable Register
+       (FlashInfo->WriteStatusEnable.Opcode << \
+                                    ((SPI_OPCODE_WRITE_S_E_INDEX - 4) * 8)));
+
+    //Program opcode types
+    *((volatile UINT16*)( gSPIBASE + R_RCRB_SPI_OPTYPE )) = (UINT16)
+        // write with address.
+        (FlashInfo->Write.OpcodeType << (SPI_OPCODE_WRITE_INDEX * 2) | \
+        // read with address.
+         FlashInfo->Read.OpcodeType << (SPI_OPCODE_READ_INDEX * 2) | \
+        // write with address.
+         FlashInfo->Erase.OpcodeType << (SPI_OPCODE_ERASE_INDEX * 2) | \
+        // read w/o no adress.
+         FlashInfo->ReadStatus.OpcodeType << (SPI_OPCODE_READ_S_INDEX * 2) | \
+        // read with address.
+         FlashInfo->ReadId.OpcodeType << (SPI_OPCODE_READ_ID_INDEX * 2) | \
+        // write w/o address.
+         FlashInfo->WriteStatus.OpcodeType << (SPI_OPCODE_WRITE_S_INDEX * 2) | \
+        // write w/o address.
+         FlashInfo->WriteStatusEnable.OpcodeType << \
+                                    (SPI_OPCODE_WRITE_S_E_INDEX * 2));
+
+    //set up the prefix opcodes for commands
+    *((volatile UINT16*)( gSPIBASE + R_RCRB_SPI_PREOP )) = (UINT16)
+        ( ( FlashInfo->WriteStatusEnable.Opcode << 8 ) | \
+                                    ( FlashInfo->WriteEnable.Opcode ) );
+
+    //set up Program Opcode and Optype if AAIWordProgram.
+    if (mExFlashPart.AAIWordProgram != 0) {
+        UINT8  bOpType = 0;
+        *((volatile UINT16*)(gSPIBASE + R_RCRB_SPI_OPMENU + 6)) = 0x4ad; 
+        bOpType = *((volatile UINT8*)(gSPIBASE + R_RCRB_SPI_OPTYPE + 1));
+        bOpType = ((bOpType & 0xf) | \
+                 (SPI_OPCODE_TYPE_WRITE_NO_ADDRESS << 6) | \
+                 (SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS << 4));
+        *((volatile UINT8*)(gSPIBASE + R_RCRB_SPI_OPTYPE + 1)) = bOpType;
+    }
+    return ;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   SerialFlashDiscoveryForQuadRead
+//
+// Description: This procedure checks SPI Quad Read support through SFDP.
+//
+// Input:       None.
+//
+// Output:      EFI_STATUS
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS
+SerialFlashDiscoveryForQuadRead (VOID)
+{
+#if defined SPI_INITIALIZE_WITH_VSCC && SPI_INITIALIZE_WITH_VSCC == 1
+    UINT8               SfdpData[256]; 
+    UINT16              wSpiCmd, wOffset, j;
+    UINT32              Index;
+    // Serial Flash Discoverable Parameters Command "0x5A".
+  	*(volatile UINT8*)(gSPIBASE + SPI_OPMENU + 7) = 0x5a;
+  	// Do nothing if SPI Registers is locked.
+  	if (*(volatile UINT8*)(gSPIBASE + SPI_OPMENU + 7) != 0x5a) 
+  	    return EFI_WRITE_PROTECTED;
+  	// Update SPI OpMenu[7] to "READ WITH ADDRESS".
+  	SfdpData[0] = *(volatile UINT8*)(gSPIBASE + SPI_OPTYPE + 1);
+    *(volatile UINT8*)(gSPIBASE + SPI_OPTYPE + 1) = (SfdpData[0] & 0x3f) | 0x80;
+   	MemSet(SfdpData, 256, 0);
+    for (Index = 0; Index < 256; Index += 64) {
+    	// Set SPI read-address = 0, 64, 128, 256 
+    	*(volatile UINT32*)(gSPIBASE + SPI_ADR) = Index;
+    	// set opcode for "5A"
+    	wSpiCmd = SPI_OPCODE_WRITE_E_INDEX << 4;
+    	// set transaction = 64 bytes
+    	wSpiCmd += ((64 - 1) << 8);
+    	// indicate that data phase is required
+    	wSpiCmd += (1 << 14);
+    	// Go (BIT1)
+    	*(volatile UINT16*)(gSPIBASE + SPI_CTL) =  wSpiCmd + BIT01;
+    	WaitForSpiCycleDone();
+    	for (j = 0; j < 64; j++)
+    	    *(SfdpData + Index + j) = *(volatile UINT8*)(gSPIBASE + SPI_DAT0 + j);
+  	    // Serial Flash Discoverable Parameters (SFDP) Signature = 50444653h
+    	if (Index == 0) {
+    	    wOffset = 0;
+    	    if (*(UINT32*)&SfdpData[wOffset] != 0x50444653) {
+                if (*(UINT32*)&SfdpData[++wOffset] != 0x50444653) 
+                    return EFI_UNSUPPORTED;
+            }        
+        }            
+    }
+  	// SFDP opode at address Ch bits 23:00 = Parameter ID 0 table Address
+  	Index = (*(UINT32*)&SfdpData[wOffset + 0xC] & 0x00FFFFFF);
+  	// SFDP opode at address 05h(SFPD Major Revisions) must = 0001h
+  	// SFDP opode at address 0Ah(Serial Flash Basic Major Revisions) must = 0001h
+  	if ((SfdpData[wOffset + 5] != 0x1) || (SfdpData[wOffset + 0xA] != 0x1) || \
+        ((Index + 0x10) > 256)) return EFI_UNSUPPORTED;
+    // Parameter ID 0 Table BIT[21] - Fast Read Quad I/O.
+    // Parameter ID 0 Table BIT[22] - Fast Read Quad Output.
+    if (*(UINT32*)&SfdpData[Index + 1] & (BIT21 + BIT22)) return EFI_SUCCESS;
+#endif
+    return EFI_UNSUPPORTED;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   GlobalBlockProtectionUnlock
+//
+// Description: This procedure unlocks "Global Block Protection" for Microchip
+//              26VF series flash parts. 
+//
+// Input:       None
+//
+// Output:      None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+GlobalBlockProtectionUnlock (VOID)
+{
+    UINT8           SavedOpType;
+    
+    if (mExFlashPart.GlobalBlockUnlock != TRUE) return;
+    // Serial Flash Discoverable Parameters Command "0x5A".
+  	*(volatile UINT8*)(gSPIBASE + SPI_OPMENU + 7) = 0x98;
+  	// Do nothing if SPI Registers is locked.
+  	if (*(volatile UINT8*)(gSPIBASE + SPI_OPMENU + 7) != 0x98) return;
+  	// Update SPI OpMenu[7] to "WRITE W/O ADDRESS".
+  	SavedOpType = *(volatile UINT8*)(gSPIBASE + SPI_OPTYPE + 1);
+    *(volatile UINT8*)(gSPIBASE + SPI_OPTYPE + 1) = (SavedOpType & 0x3f) | BIT06;
+    // Opcode menu slot 7 is configured as "Write Disable" if AAIWordProgram.
+    *(volatile UINT16*)(gSPIBASE + SPI_CTL) = \
+                                    (SPI_OPCODE_WRITE_D_INDEX << 4) + BIT01;
+    // wait for chipset SPI cycle completed.
+    WaitForSpiCycleDone();
+    return ;
+}
+// [ EIP358409 ]+>>>
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   RemoveWriteStatusOpcode
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+RemoveWriteStatusOpcode (
+    IN OUT  FLASH_INFO      *FlashInfo
+)
+{
+    
+	FlashInfo->WriteStatus.Opcode = FlashInfo->ReadId.Opcode;
+	FlashInfo->WriteStatus.OpcodeType = FlashInfo->ReadId.OpcodeType;
+	
+    //Program second DWORD of Opcode commands
+    *((volatile UINT32*)( gSPIBASE + R_RCRB_SPI_OPMENU + 4 )) = (UINT32)
+        // Read device ID
+      ((FlashInfo->ReadId.Opcode << ((SPI_OPCODE_READ_ID_INDEX - 4) * 8)) | \
+        // Write Status Register
+       (FlashInfo->WriteStatus.Opcode << \
+                                    ((SPI_OPCODE_WRITE_S_INDEX - 4) * 8)) | \
+        // Write Status Enable Register
+       (FlashInfo->WriteStatusEnable.Opcode << \
+                                    ((SPI_OPCODE_WRITE_S_E_INDEX - 4) * 8)));
+
+    //Program opcode types
+    *((volatile UINT16*)( gSPIBASE + R_RCRB_SPI_OPTYPE )) = (UINT16)
+        // write with address.
+        (FlashInfo->Write.OpcodeType << (SPI_OPCODE_WRITE_INDEX * 2) | \
+        // read with address.
+         FlashInfo->Read.OpcodeType << (SPI_OPCODE_READ_INDEX * 2) | \
+        // write with address.
+         FlashInfo->Erase.OpcodeType << (SPI_OPCODE_ERASE_INDEX * 2) | \
+        // read w/o no adress.
+         FlashInfo->ReadStatus.OpcodeType << (SPI_OPCODE_READ_S_INDEX * 2) | \
+        // read with address.
+         FlashInfo->ReadId.OpcodeType << (SPI_OPCODE_READ_ID_INDEX * 2) | \
+        // write w/o address.
+         FlashInfo->WriteStatus.OpcodeType << (SPI_OPCODE_WRITE_S_INDEX * 2) | \
+        // write w/o address.
+         FlashInfo->WriteStatusEnable.OpcodeType << \
+                                    (SPI_OPCODE_WRITE_S_E_INDEX * 2));
+
+   
+    return ;
+}
+// [ EIP358409 ]+<<<
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   ReinitializeSpiEnvironment
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+ReinitializeSpiEnvironment (
+    IN OUT  FLASH_INFO      *FlashInfo
+)
+{
+    UINT8 *BlockAddress;    // [ EIP358409 ]
+#if defined SPI_INITIALIZE_WITH_VSCC && SPI_INITIALIZE_WITH_VSCC == 1
+    // Program UPPER/LOWER VSCC register.
+    UINT32          dVSCC = 0;
+    EFI_STATUS      Status;
+    // Erase Opcode. 
+    dVSCC = FlashInfo->Erase.Opcode << 8;
+    // Block/Sector Erase Size.
+    if (FlashInfo->SectorSize == SECTOR_SIZE_4KB) dVSCC |= BIT00;
+    else if (FlashInfo->SectorSize == SECTOR_SIZE_8KB) dVSCC |= BIT01;
+    else if (FlashInfo->SectorSize == SECTOR_SIZE_64KB) dVSCC |= (BIT00 + BIT01);
+    // Write Granularity.
+    if (FlashInfo->PageSize != 1) dVSCC |= BIT02;
+    // Write Status Required.
+    if (FlashInfo->WriteStatusEnable.Opcode == 0x50) dVSCC |= BIT03;
+    // Write Enable On Write Status.
+    if (FlashInfo->WriteStatusEnable.Opcode == 0x39) dVSCC |= BIT04;
+    Status = SerialFlashDiscoveryForQuadRead();
+    if (!EFI_ERROR(Status)) {
+        switch ((UINT8)mExFlashPart.FlashVenDevId) {
+            case 0xEF : // Winbond         
+            case 0x37 : // AMIC
+            case 0x01 : // Spansion
+                dVSCC |= BIT5;  break;
+            case 0xC2 : // MXIC
+                dVSCC |= BIT6;  break;
+            case 0x1F : // Atmel
+                dVSCC |= (BIT5 + BIT6); break;
+            case 0xBF : // SST/Microchip
+                dVSCC |= BIT7;  break;
+                break;
+            default : break;
+        }
+    }    
+    if (Status != EFI_WRITE_PROTECTED) {
+#if LOWER_VSCC_REG != 0
+        *(volatile UINT32*)(gSPIBASE + LOWER_VSCC_REG) = dVSCC;
+#endif 
+#if UPPER_VSCC_REG != 0
+        *(volatile UINT32*)(gSPIBASE + UPPER_VSCC_REG) = dVSCC;
+#endif 
+    }
+#endif 
+    GlobalBlockProtectionUnlock();
+    InitializeSpiEnvironment ( FlashInfo );
+// [ EIP358409 ]+>>>
+	BlockAddress = (UINT8*)SPI_FLASH_DEVICE_BASE_ADDRESS;
+	SpiBlockProtectUpdate (BlockAddress, 0);
+	RemoveWriteStatusOpcode(FlashInfo);	
+// [ EIP358409 ]+<<<
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonSpiReadId
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+CommonSpiReadId (
+    IN      FLASH_INFO      *FlashInfo,
+    IN OUT  UINT32          *dFlashId
+)
+{
+    UINT16              wSpiCmd = 0xFFFF;
+
+    InitializeSpiEnvironment( FlashInfo );
+    // Set SPI read-address = 0
+    *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = 0;
+    // set opcode for "Read ID"
+    wSpiCmd = SPI_OPCODE_READ_ID_INDEX << 4;
+    // set transaction = 3 bytes
+    wSpiCmd += ( ( 3 - 1 ) << 8 );
+    // indicate that data phase is required
+    wSpiCmd += ( 1 << 14 );
+    // Go (BIT1)
+    *(volatile UINT16*)( gSPIBASE + SPI_CTL ) =  wSpiCmd + BIT01;
+    WaitForSpiCycleDone();
+    SpiIoDelay();
+    *dFlashId = *(volatile UINT32*)( gSPIBASE + SPI_DAT0 ) & 0x00FFFFFF;
+    return  TRUE;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiEraseCommand
+//
+// Description: This API function erases a block in the flash. Flash model
+//              specific code will branch out from this routine
+//
+// Input:       pBlockAddress   Block that need to be erased
+//
+// Output:      Nothing
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiEraseCommand   (
+    IN volatile UINT8*      pBlockAddress
+)
+{
+    volatile UINT32     dSectorAddr;
+    UINT32              dNByte, dPhyAddress;
+    UINT16              wEraseRetry, wNumSectors, wSector;
+    UINT16              wSpiCmd;
+
+    // These parts only erase in 64K sectors
+    InitializeSpiEnvironment( &mExFlashPart.FlashCommandMenu );
+    wNumSectors = ( FlashBlockSize / FlashAPI->FlashSectorSize );
+    for ( wSector = 0; wSector < wNumSectors ; wSector++ ) {
+        dSectorAddr = (UINT32)(pBlockAddress + \
+                                (wSector * FlashAPI->FlashSectorSize));
+        if (EFI_ERROR(CommonConvertSpiAddress( \
+                (volatile UINT8*)dSectorAddr, &dPhyAddress))) return;
+        for ( dNByte = 0; dNByte < FlashAPI->FlashSectorSize; dNByte++ ) {
+            if (0xFF != CommonSpiReadByte(dSectorAddr + dNByte)) break;
+        }
+        if  ( dNByte == FlashAPI->FlashSectorSize )   continue;
+        for ( wEraseRetry = 0; wEraseRetry < FLASH_RETRIES; wEraseRetry++ ) {
+            *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = dPhyAddress;
+            // opcode index 2 is programmed for erase command.
+            // Set BIT1 (Go), BIT2(Atomic w/ Prefix)
+            wSpiCmd = ( SPI_OPCODE_ERASE_INDEX << 4) + BIT01 + BIT02;
+            *(volatile UINT16*)( gSPIBASE + SPI_CTL ) = wSpiCmd;
+            // wait for chipset SPI cycle completed.
+            WaitForSpiCycleDone();
+            // wait for SPI flash operation completed.
+            WaitForWriteOperationCompleted();
+            // write operation appeared to succeed, now read back byte
+            // and compare.
+            if (CommonSpiReadByte(dSectorAddr) == 0xFF)   break;
+        }
+    }
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiProgramCommand
+//
+// Description: This function programs a byte data to the specified location
+//
+// Input:   *pByteAddress   Location where the data to be written
+//          Bytes - data to be written.
+//          Length - number of bytes to write
+//
+// Output:  Length - number of bytes that were not written
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiProgramCommand (
+    IN volatile UINT8       *pByteAddress,
+    IN UINT8                *Byte,
+    IN OUT UINT32           *Length
+)
+{
+    UINT8               bFlashRetry = 0;
+    UINT16              wProgBytes = 0, wNumBytes = 0;
+    UINT16              wSpiCmd = 0, wRetry = 0, wMaxNumBytes = 0;
+    UINT32              dPhyAddress = 0;
+
+
+    InitializeSpiEnvironment( &mExFlashPart.FlashCommandMenu );
+    wProgBytes = mCommonSpiFlash.FlashProgramSize;
+    if ( mCommonSpiFlash.FlashProgramSize != 1 ) {
+        // Limit the max transfer to the number of bytes the chipset can
+        // transfer per cycle
+        if ( *Length >= SPI_MAX_DATA_TRANSFER )
+            wProgBytes = SPI_MAX_DATA_TRANSFER;
+        else wProgBytes = *Length;
+        // this is currently for the WINBOND parts only
+        // mask off lowest 8 bits of address so that we can determine how
+        // many bytes we can write before we hit the end of a page
+        wMaxNumBytes = 0x100 - ((UINT32)pByteAddress & 0xFF);
+        if ( (UINT32)pByteAddress & 0x1 )   wProgBytes = 1;
+        else if ( wProgBytes > wMaxNumBytes ) wProgBytes = wMaxNumBytes;
+    } else if(CheckAaiWordProram((UINT32)pByteAddress, *Length)) wProgBytes = 2;
+    for ( bFlashRetry = 0; bFlashRetry < FLASH_RETRIES; bFlashRetry++ ) {
+        // check if do the data need to be programmed ?
+        for ( wNumBytes = 0; wNumBytes < wProgBytes; wNumBytes++ ) {
+            if ( *( Byte + wNumBytes ) != 0xFF )    break;
+        }
+        // The data is empty and don't need to be programmed.
+        if ( wNumBytes == wProgBytes )  break;
+        // update data to chipset SPI data transfer registers.
+        for ( wNumBytes = 0; wNumBytes < wProgBytes; wNumBytes++ ) {
+            for ( wRetry = 0; wRetry < 0x400; wRetry ++ ) {
+                *(volatile UINT8*)( gSPIBASE + SPI_DAT0 + wNumBytes ) = \
+                                                         *( Byte + wNumBytes );
+                // verified for checking the data is correct.
+                if ( *( Byte + wNumBytes ) == \
+                        *(volatile UINT8*)( gSPIBASE + SPI_DAT0 + wNumBytes ) )
+                    break;
+            }
+        }
+        if (EFI_ERROR(CommonConvertSpiAddress( \
+                (volatile UINT8*)pByteAddress, &dPhyAddress))) return;
+        *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = dPhyAddress;
+        // BIT14 - indicate that it's data cycle.
+        wSpiCmd = ( 1 << 14 );
+        // BIT[8..13] - update the number of bytes to be written.
+        wSpiCmd += ( wProgBytes - 1 ) << 8;
+        // opcode index 0 is programmed for program command.
+        // Set BIT1 (Go), BIT2(Atomic w/ Prefix)
+        if (CheckAaiWordProram(dPhyAddress, wProgBytes))
+            wSpiCmd += ( SPI_OPCODE_AAI_INDEX << 4) + BIT01 + BIT02;
+        else wSpiCmd += ( SPI_OPCODE_WRITE_INDEX << 4) + BIT01 + BIT02;
+        *(volatile UINT16*)( gSPIBASE + SPI_CTL ) = wSpiCmd;
+        // wait for chipset SPI cycle completed.
+        WaitForSpiCycleDone();
+        // wait for chipset SPI flash operation completed.
+        WaitForWriteOperationCompleted();
+        // Issue SPI Write Disable if SST AAIWordProgram supported.
+        if (CheckAaiWordProram(dPhyAddress, wProgBytes)) SpiWriteDisable();
+        // write operation appeared to succeed, now read back byte and compare
+        // set control for 1-byte data read, no prefix
+        for ( wNumBytes = 0; wNumBytes < wProgBytes; wNumBytes++ ) {
+            if (*(Byte + wNumBytes) != \
+                CommonSpiReadByte((UINT32)(pByteAddress + wNumBytes))) break;
+        }
+        if ( wNumBytes == wProgBytes )  break;
+    }
+    // Don't forget to return the number of bytes not written
+    *Length = *Length - (UINT32)wProgBytes;
+    return;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiReadCommand
+//
+// Description: This function programs a byte data to the specified location
+//
+// Input:   *pByteAddress   Location where the data to be written
+//          Bytes - data to be written.
+//          Length - number of bytes to write
+//
+// Output:  Length - number of bytes that were not written
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID CommonSpiReadCommand   (
+    IN  volatile UINT8      *pByteAddress,
+    OUT UINT8               *Byte,
+    IN  OUT UINT32          *Length
+)
+{
+    UINT32              dReadAddress = 0; 
+    UINT16              wSpiCmd, i, wMaxRead = 0;
+
+    InitializeSpiEnvironment( &mExFlashPart.FlashCommandMenu );
+    if (EFI_ERROR(CommonConvertSpiAddress( \
+                (volatile UINT8*)pByteAddress, &dReadAddress))) return;
+    wMaxRead = 0x100 - (dReadAddress & 0xff);
+    if (wMaxRead > SPI_MAX_DATA_TRANSFER) wMaxRead = SPI_MAX_DATA_TRANSFER;
+    if (wMaxRead > *Length) wMaxRead = (UINT16)*Length;
+    // update the read address.
+    *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = dReadAddress;
+    // Opcode menu slot 1 is configured as "Read Flash"
+    wSpiCmd = ( SPI_OPCODE_READ_INDEX << 4 ) + BIT01;
+    // indicate that data phase is required
+    wSpiCmd += (1 << 14);
+    // BIT[8..13] - update the number of bytes to be read.
+    wSpiCmd += (wMaxRead - 1) << 8;
+    *(volatile UINT16*)( gSPIBASE + SPI_CTL ) = wSpiCmd;
+    // wait for spi cycle completed.
+    WaitForSpiCycleDone();
+    // read data
+    for (i = 0; i < wMaxRead; i++) 
+        *(Byte + i) = *(volatile UINT8*)(gSPIBASE + SPI_DAT0 + i);
+    *Length = *Length - (UINT32)wMaxRead;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiIsEraseCompleted
+//
+// Description: This function verifies whether the block erase
+//      command is completed and returns the status of the command
+//
+// Input:   *pBlockAddress  Location of the block erase
+//
+// Output:  *pError         True on error and false on success
+//          *Status         Error status code (0 - Success)
+//
+// Return:  TRUE        If operation completed successfully
+//                          *pError = FALSE, *pStatus = 0
+//          FALSE       If operation failed
+//                          *pError = TRUE, *pStatus = error status
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+CommonSpiIsEraseCompleted   (
+    IN  volatile UINT8          *pBlockAddress,
+    OUT BOOLEAN                 *pError,
+    OUT UINTN                   *pStatus
+)
+{
+    UINT32                      dNumBytes;
+    UINT8                       bByte;
+
+    for ( dNumBytes = 0; dNumBytes < FlashBlockSize; dNumBytes++ ) {
+        // Check for Top Swap enabled
+        if (*(volatile UINT8*)(gRCBABASE + RCRB_MMIO_BUC) & BIT00)
+            bByte = CommonSpiReadByte((UINT32)(pBlockAddress + dNumBytes));
+        else bByte = *(volatile UINT8*)(pBlockAddress + dNumBytes);
+        if (bByte != 0xFF) {   
+            if ( pStatus ) *pStatus = EFI_NOT_READY;
+            if ( pError ) *pError = TRUE;
+            return FALSE;
+        }
+    }
+    if ( pError ) *pError = FALSE;
+    if ( pStatus ) *pStatus = EFI_SUCCESS;
+    return TRUE;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiIsProgramCompleted
+//
+// Description: This function verifies whether the program (page or byte)
+//      command is completed and returns the status of the command
+//
+// Input:   *pByteAddress   Location of the program command
+//          Byte            Last data byte written
+//
+// Output:  *pError         True on error and false on success
+//          *Status         Error status code (0 - Success)
+//
+// Return:  TRUE        If operation completed successfully
+//                          *pError = FALSE, *pStatus = 0
+//          FALSE       If operation failed
+//                          *pError = TRUE, *pStatus = error status
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+CommonSpiIsProgramCompleted (
+    IN  volatile UINT8          *pByteAddress,
+    IN  UINT8                   *Byte,
+    IN  UINT32                  Length,
+    OUT BOOLEAN                 *pError,
+    OUT UINTN                   *pStatus
+)
+{
+    UINT32                      dNumBytes;
+    UINT8                       bByte, bReadByte;
+
+    for ( dNumBytes = 0; dNumBytes < Length; dNumBytes++ ) {
+        bByte = *(Byte + dNumBytes);
+        // Check for Top Swap enabled
+        if (*(volatile UINT8*)(gRCBABASE + RCRB_MMIO_BUC) & BIT00)
+            bReadByte = CommonSpiReadByte((UINT32)(pByteAddress + dNumBytes));
+        else bReadByte = *(volatile UINT8*)(pByteAddress + dNumBytes);
+        if (bByte != bReadByte) {   
+            if ( pStatus ) *pStatus = EFI_NOT_READY;
+            if ( pError ) *pError = TRUE;
+            return FALSE;
+        }
+    }
+    if ( pError ) *pError = FALSE;
+    if ( pStatus ) *pStatus = EFI_SUCCESS;
+    return TRUE;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   SpiBlockProtectUpdate
+//
+// Description: This function writes the status register.
+//
+// Input:   *pBlockAddress - Address within the block to write enable.
+//          bStatusData - Value to be written to Status Register.
+//
+// Output:      None
+//
+// Return:      None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+SpiBlockProtectUpdate (
+    IN volatile UINT8           *pBlockAddress,
+    IN UINT8                    bStatusData
+)
+{
+    UINT8                   bStatusReg = 0, bPrefixOp, bDataPhase = 1, bBPbits;
+    UINT32                  dSectorAddr = 0;
+
+    if (EFI_ERROR(CommonConvertSpiAddress(pBlockAddress, &dSectorAddr))) return;
+    bStatusReg = CommonSpiReadStatus (dSectorAddr);
+    bPrefixOp = SPI_PREFIX_WRITE_EN;    // Use Prefix 0 w/o address
+    switch ( (UINT8)mExFlashPart.FlashVenDevId ) {
+        case 0xBF :
+            // if SST flash, prefix 1 w/o address
+            if (mExFlashPart.GlobalBlockUnlock == TRUE) return;
+            bBPbits = (BIT02 + BIT03 + BIT04 + BIT05);
+            bPrefixOp = SPI_PREFIX_WRITE_S_EN;
+            break;
+        case 0x1F :
+            // if ATMEL flash, prefix 0 w/ address
+            bBPbits = (BIT02 + BIT03);
+            break;
+        case 0x20 :
+            // if MXIC flash, keep Quad Enable bit (BIT6) state.
+            bBPbits = (BIT02 + BIT03 + BIT04 + BIT06);
+            break;
+        default :
+            bBPbits = (BIT02 + BIT03 + BIT04);
+    }
+    bStatusReg &= bBPbits;              // keep valid bits.
+    bStatusData &= bBPbits;             // keep valid bits.
+    if (bStatusReg != bStatusData) {
+        CommonSpiWriteStatus (  bStatusData, \
+                                SPI_OPCODE_WRITE_S_INDEX, \
+                                bDataPhase, \
+                                bPrefixOp, \
+                                dSectorAddr );
+    }                                
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiBlockWriteEnable
+//
+// Description: This function contains any flash specific code need to
+//              enable a particular flash block write
+//
+// Input:   *pBlockAddress - Address within the block to write enable
+//
+// Output:      None
+//
+// Return:      None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiBlockWriteEnable   (
+    IN volatile UINT8       *pBlockAddress
+)
+{
+    SpiBlockProtectUpdate (pBlockAddress, 0);
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiBlockWriteDisable
+//
+// Description: This function contains any flash specific code need to
+//              disable a particular flash block write
+//
+// Input:   *pBlockAddress - Address within the block to write disable
+//
+// Output:  None
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiBlockWriteDisable  (
+    IN volatile UINT8           *pBlockAddress
+)
+{
+#if BLOCK_PROTECT_ENABLE
+    SpiBlockProtectUpdate (pBlockAddress, 0xff);
+#endif
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiDeviceWriteEnable
+//
+// Description: This function contains any flash specific code need to
+//              enable flash write
+//
+// Input:   None
+//
+// Output:  None
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiDeviceWriteEnable (VOID)
+{
+    // check is DeviceWrite enabled, if yes, don't enable it again,
+    // else, enable it.
+    if ( !gbDeviceWriteEnabled ) {
+        gbDeviceWriteEnabled = 1;
+    }
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiDeviceWriteDisable
+//
+// Description: This function contains any flash specific code need to
+//              disable flash write
+//
+// Input:       None
+//
+// Output:      None
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiDeviceWriteDisable (VOID)
+{
+    // check is DeviceWrite enabled, if yes, disable it,
+    // if no, don't disable it.
+    if ( gbDeviceWriteEnabled ) {
+        gbDeviceWriteEnabled = 0;
+    }
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiDeviceVirtualFixup
+//
+// Description: This function will be invoked by the core to convert
+//              runtime pointers to virtual address
+//
+// Input:       *pRS    Pointer to runtime services
+//
+// Output:      None
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+static
+VOID
+CommonSpiDeviceVirtualFixup (
+    IN EFI_RUNTIME_SERVICES  *pRS
+)
+{
+
+//  // Following is an example code for virtual address conversion
+//  pRS->ConvertPointer(0, (VOID**)&FlashDeviceBase);
+
+//-    SpiChipsetVirtualFixup(pRS);
+    pRS->ConvertPointer(0, (VOID **)&gSPIBASE);
+    pRS->ConvertPointer(0, (VOID **)&gRCBABASE);
+    gbDeviceVirtual = 1;
+
+    return;
+}
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
\ No newline at end of file
diff --git a/Board/Flash/SPI/ICHx/SpiCspSrc.cif b/Board/Flash/SPI/ICHx/SpiCspSrc.cif
new file mode 100644
index 0000000..c32774f
--- /dev/null
+++ b/Board/Flash/SPI/ICHx/SpiCspSrc.cif
@@ -0,0 +1,9 @@
+<component>
+	name = "CSP : Intel ICHx SPI - Source"
+	category = ModulePart
+	LocalRoot = "Board\Flash\SPI\ICHx"
+	RefName = "ICHX_SPI_CSP_SOURCE"
+[files]
+"ICHxSpi.sdl"	
+"SPIFlash.c"	
+<endComponent>
diff --git a/Board/Flash/SPI/SpiFlash.cif b/Board/Flash/SPI/SpiFlash.cif
new file mode 100644
index 0000000..fef787f
--- /dev/null
+++ b/Board/Flash/SPI/SpiFlash.cif
@@ -0,0 +1,14 @@
+<component>
+	name = "SPI Interface - Source"
+	category = ModulePart
+	LocalRoot = "Board\Flash\SPI"
+	RefName = "SPI_INTERFACE_SOURCE"
+[files]
+"SpiFlash.sdl"	
+"SpiFlash.mak"	
+"SpiFlash.h"	
+"SpiIdentify.c"	
+[parts]
+"DUMMY_SPI_CSP_SOURCE"
+"ICHX_SPI_CSP_SOURCE"
+<endComponent>
diff --git a/Board/Flash/SPI/SpiFlash.h b/Board/Flash/SPI/SpiFlash.h
new file mode 100644
index 0000000..9aca707
--- /dev/null
+++ b/Board/Flash/SPI/SpiFlash.h
@@ -0,0 +1,531 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2008, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/SpiFlash.h 2     4/24/13 11:10p Thomaschen $
+//
+// $Revision: 2 $
+//
+// $Date: 4/24/13 11:10p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/SpiFlash.h $
+// 
+// 2     4/24/13 11:10p Thomaschen
+// 
+// 29    3/08/13 3:12a Calvinchen
+// [TAG]  		EIP110515
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	Microchip SST26VF064B & SST26VF064BA 8MB SPI Flash part
+// support 
+// [RootCause]  	Need "Global Block Protection Unlock" before programming.
+// [Solution]  	Added "Global Block Protection Unlock" before programming.
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// SpiFlash.cif
+// 
+// 28    2/18/13 5:14a Calvinchen
+// [TAG]  		EIP114488
+// [Category]  	Improvement
+// [Description]  	1. Added MXIC MX25U6435F SPI Flash part support
+// 2. Added GigaDevice 25LQ series flash part.
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// 
+// 27    1/14/13 5:40a Calvinchen
+// [TAG]  		EIP110515
+// [Category]  	Improvement
+// [Description]  	Microchip SST26VF064B & SST26VF064BA 8MB SPI Flash part
+// support
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// 
+// 26    12/13/12 2:22a Calvinchen
+// Added support for winbond W25Q F and W series Flash Parts.
+// 
+// 25    7/18/12 6:10a Calvinchen
+// 1. Changed N25Q128 to 4K erase.
+// 2. Added N25Q128A support.
+// 
+// 24    10/31/11 6:46a Calvinchen
+// [TAG]  		EIP68872
+// [Category]  	Improvement
+// [Description]  	Added ESMT 25L64QA.
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// 
+// 23    8/24/11 7:58a Calvinchen
+// Improvement :
+// Added Token "FAST_READ_SUPPORT" for switching the SPI
+// Read(03)/FastRead(0B)/DualOutputFastRead(3B) command. To use the
+// FastRead and the Dual Output Fast Read command MUST have Hardware SPI
+// support. **Only validated with Intel Mahobay platform (Southbridge:
+// PatherPoint)**
+// 
+// 22    7/21/11 5:07a Calvinchen
+// [TAG]  		EIP65366
+// [Category]  	Improvement
+// [Description]  	New SPI Flash supports for EON 25QH and ESMT 25L PA
+// flash part. 
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// 
+// 21    4/08/11 3:05a Chunweitseng
+// [TAG]  		EIP57327
+// [Category]  	Improvement
+// [Description]  	 Added Support for FIDELIX FM25Q32A/64A and AMIC
+// 25LQ032.
+// 
+// [Files]  		SpiFlash.h, SpiIdentify.c
+// 
+// 20    2/10/11 5:43a Calvinchen
+// [TAG]  		EIP53437
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	Corrected Numonyx M25P128 Minimum Sector Size to 256K. 
+// [RootCause]  	None.
+// [Solution]  	None.
+// [Files]  		SpiFlash.sdl
+// SpiFlash.mak
+// SpiFlash.h
+// SpiIdentify.c
+// SpiFlash.cif
+// 
+// 19    11/30/10 3:28a Calvinchen
+// Added Numonyx N25Q Series.
+// 
+// 17    3/11/10 6:43a Calvinchen
+// Improvement : Added SST AAIWordProgram SPI command to speed up the
+// programming time.
+// 
+// 16    1/07/10 5:34a Calvinchen
+// Addes support for Spansion S25FL128/129P.
+// 
+// 15    12/31/09 1:50a Klzhan
+// Improvement : Support EON 25Q32/64.
+// 
+// 14    12/23/09 6:13a Calvinchen
+// Improvement:1.Added FWH/LPC/STD Flash Device Number support.
+// 
+// 13    12/22/09 2:30a Calvinchen
+// Added support for ATMEL 25DQ161.
+// 
+// 12    12/16/09 3:45a Calvinchen
+// 
+// 11    12/15/09 5:49a Calvinchen
+// Improvement : 
+// 1.Added support for GigaDevie 25Q80/16.
+// 2.Added Flash Chip Name support.
+// 
+// 9     6/24/09 3:14a Calvinchen
+// (EIP22177) Updated for Aptio Source Enhancement. 
+//
+// 8     5/11/09 7:21a Calvinchen
+// Added support for SST 25VF064C and MXIC MX25L1635/3235/6435..
+//
+// 7     4/27/09 3:19a Calvinchen
+// 1.Added support for Winbond 25Q128
+// 2.(EIP20459) Added Multiple SPI CSP component support.
+//
+// 6     12/10/08 5:53a Calvinchen
+// Added support for Winbond W25Q80/16 1M/2M SPI flash.
+//
+// 5     9/30/08 10:09a Calvinchen
+// According to Intel ICH7/ICH8/ICH9/ICH10 - SPI Family Flash Programming
+// Guide Application Note - Rev#2.4,
+// Section#5.3 Software Sequencing Opcode Requirements and
+// Recommendations,It is strongly recommended that the "9Fh" JEDEC ID be
+// used instead of "90h" or "AB".
+// Intel utilities such as the Flash Programming tool (Fprog.exe and
+// fpt.exe) will incorrectly detect the flash part in the system and it
+// may lead to undesired program operation.
+//
+// 4     9/11/08 2:30a Calvinchen
+// Added support for EON 25F32.
+//
+// 3     8/26/08 2:54a Calvinchen
+// 1.Added support for AMTME 25DF641.
+// 2.Fixed Fail to un-protect ATMEL flash.
+// 3.Fixed building failed if $(CFLAGS) = /W4.
+//
+// 2     5/09/08 3:35a Calvinchen
+// Added support for STM M25PF32.
+//
+// 1     3/13/08 6:31a Calvinchen
+//
+// 12    3/05/08 9:11a Robert
+//
+// 11    2/13/08 6:14p Robert
+//
+// 2     2/13/08 6:03p Robert
+// coding updates and addition of Intel SPI part
+//
+// 10    1/07/08 3:05p Robert
+// updated for coding standard
+//
+// 9     1/02/08 12:04p Robert
+// Added the MX25L1605 device ID
+//
+// 8     11/09/07 3:49p Alexp
+// Added SPI opcode Read Index
+//
+// 7     10/24/07 4:23p Robert
+// Needed to add a function prototype for SpiTransfer()
+//
+// 6     10/09/07 1:11p Robert
+// added a new VID/DID and cleaned up other additions of parts
+//
+// 5     10/01/07 4:19a Klzhan
+// Added support for AMIC A25L080 , MXIC 25L6405 25L3205 , ST 25P32 .
+//
+// 4     8/20/07 2:22p Robert
+// Added support for Atmel AT26DF321 and for winbond w25x32 parts
+//
+// 3     8/02/07 2:51p Artems
+// Added support Atmel 1MB
+//
+// 2     2/20/07 6:44p Robert
+// removed some unneeded definitions and added a few new ones
+//
+// 1     12/18/06 3:39p Robert
+// Initial Check in
+//
+// 2     11/16/06 6:27p Robert
+// removed unused definition
+//
+// 1     10/31/06 2:30p Sivagarn
+// Initial Checkin
+//
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//
+// Name:    SpiFlash.h
+//
+// Description: Contains Vendor IDs and Device IDs for ths supported
+//      parts.  also contains the command values for each supported part
+//
+//<AMI_FHDR_END>
+//**********************************************************************
+
+#ifndef _SPIFlash_H_
+#define _SPIFlash_H_
+
+
+#include <token.h>
+#include "Board\Sb\Sb.h"
+
+
+VOID SpiFlashLock(UINT16 MfgDevId, BOOLEAN Lock);
+
+
+//-------------------------------------------------------------------
+// Supported SPI devices
+// MFG and Device code
+#define SST_25LF040A                0x44bf
+#define SST_25LF040                 0x40bf
+#define SST_25LF080A                0x80bf
+
+#define SST_25VF040B                0x8dbf
+#define SST_25VF080B                0x8ebf
+#define SST_25VF016B                0x41bf
+#define SST_25VF032B                0x4abf
+#define SST_25VFxxx_ID              0x25bf
+#define SST_26VFxxx_ID              0x26bf
+
+
+//PMC 25LVxxx Device ID/Manufacturer ID
+#define PMC_25LV040                 0x7e9d
+#define PMC_25LVxxx_ID              0x9d7f
+
+#define ATMEL_26DF041               0x441f
+#define ATMEL_26DF081               0x451f
+#define ATMEL_26DF161               0x461f
+#define ATMEL_26DF321               0x471f  // ATMEL 26DF321 32Mbit
+#define ATMEL_25DF641               0x481f  // ATMEL 25DF641 64Mbit
+#define ATMEL_25DQ161               0x861f
+
+//Winbond W25Xxx Device ID/Manufacturer ID
+#define WINBOND_W25X10              0x10ef
+#define WINBOND_W25X20              0x11ef
+#define WINBOND_W25X40              0x12ef
+#define WINBOND_W25X80              0x13ef
+#define WINBOND_W25X16              0x14ef
+#define WINBOND_25Xxx_ID            0x30ef
+#define WINBOND_25Qxx_ID            0x40ef
+#define WINBOND_25QxxW_ID           0x50ef
+#define WINBOND_25QxxF_ID           0x60ef
+
+// MXIC Device ID/Manufacturer ID
+#define MX25L4005_DEVICE_ID         0x13c2
+#define MX25L8005_DEVICE_ID         0x14c2
+#define MX25L1605_DEVICE_ID         0x15c2
+#define MX25L3205_DEVICE_ID         0x16c2
+#define MX25L6405_DEVICE_ID         0x17c2
+#define MXIC_25Lxxxx_ID             0x20c2
+#define MXIC_25Lxx35_ID             0x24c2
+#define MXIC_25Lxx36_ID             0x5ec2
+#define MXIC_25Uxx35_ID             0x25c2
+
+// Spansion S25FL008A Device ID/Manufacturer ID
+#define SPANSION_25FL004A           0x1201
+#define SPANSION_25FL008A           0x1301
+#define SPANSION_25FLxxx_ID         0x0201
+#define SPANSION_25FLxxxP_ID        0x2001
+
+// ESMT F25L00xA Device ID/Manufacturer ID
+#define ESMT_25L004A                0x128c
+#define ESMT_25L008A                0x138c
+#define ESMT_25L016A                0x148c
+#define ESMT_25L032A                0x158c
+#define ESMT_25LxxxT_ID             0x208c
+#define ESMT_25LxxxB_ID             0x218c
+#define ESMT_25Lxx_ID               0x408c
+#define ESMT_25LxxQ_ID              0x418c
+
+// ST Micro/Micron/Numonyx M25Pxx Device ID/Manufacturer ID
+#define STM_M25P40                  0x1320
+#define STM_M25P80                  0x1420
+#define STM_M25P32                  0x2020
+#define STM_25PExx_ID               0x8020
+#define STM_25PXxx_ID               0x7120      // M25PX16/32
+#define STM_25PFxx_ID               0x7020      // M25PF32
+#define STM_25Pxx_ID                0x2020      // M25P16/32/64
+#define Numonyx_25Qxx_ID            0xBA20      // N25Q16/32/64/128
+#define Numonyx_25QxxA_ID           0xBB20      // N25Q16/32/64/128
+
+// AMIC 25Lxx Device ID/Manufacturer ID
+#define AMIC_25Lxx_ID               0x377f
+#define AMIC_25Lxxx_ID              0x3037
+#define AMIC_25LQxxx_ID             0x4037
+
+// EON  25P/Fxx Device ID/Manufacturer ID
+#define EON_25Fxx_ID                0x311c
+#define EON_25Pxx_ID                0x201c
+#define EON_25Qxx_ID                0x301c
+#define EON_25QHxx_ID               0x701c
+
+// INTEL 25Fxxx Device ID/Manufacturer ID
+#define INTEL_25Fxxx_ID             0x8989
+#define INTEL_25Fxxx_ID             0x8989
+
+// Giga Device GD25Qxx Device ID/Manufacturer ID
+#define GD_25Qxx_ID                 0x40C8
+#define GD_25LQxx_ID                0x60C8
+
+// FIDELIX Device FM_25Qxx Device ID/Manufacturer ID
+#define FM_25Qxx_ID                 0x32F8
+
+//-------------------------------------------------------------------
+//  NOTE: Assuming that 8Mbit flash will only contain a 4Mbit binary.
+//        Treating 4Mbit and 8Mbit devices the same.
+
+//-------------------------------------------------------------------
+// BIOS Base Address
+#define BIOS_BASE_ADDRESS_4M 0xfff80000
+#define BIOS_BASE_ADDRESS_8M 0xfff00000
+
+//-------------------------------------------------------------------
+// block and sector sizes
+#define SECTOR_SIZE_256B    0x100       // 4kBytes sector size
+#define SECTOR_SIZE_4KB     0x1000      // 4kBytes sector size
+#define SECTOR_SIZE_8KB     0x2000      // 8kbytes sector size
+#define SECTOR_SIZE_64KB    0x10000     // 64kBytes sector size
+#define SECTOR_SIZE_256KB   0x40000     // 256kBytes sector size
+#define BLOCK_SIZE_32KB     0x8000      // 32Kbytes block size
+
+//-------------------------------------------------------------------
+// Flash commands
+
+// Commands for SST 25LFxx and 25VFxx parts
+#define SPI_SST25LF_COMMAND_WRITE         0x02
+#define SPI_SST25LF_COMMAND_READ          0x03
+#if FAST_READ_SUPPORT == 0
+#define SPI_SST25VF_COMMAND_READ          0x03        // Read Byte
+#elif FAST_READ_SUPPORT == 1
+#define SPI_SST25VF_COMMAND_READ          0x0B        // Fast Read
+#elif FAST_READ_SUPPORT == 2
+#define SPI_SST25VF_COMMAND_READ          0x3B        // Dual Output Fast Read
+#endif
+#define SPI_SST25LF_COMMAND_ERASE         0x20
+#define SPI_SST25LF_COMMAND_WRITE_DISABLE 0x04
+#define SPI_SST25LF_COMMAND_READ_STATUS   0x05
+#define SPI_SST25LF_COMMAND_WRITE_ENABLE  0x06
+//#define SPI_SST25LF_COMMAND_READ_ID       0xab
+#define SPI_SST25LF_COMMAND_READ_ID       0x90
+#define SPI_SST25VF_COMMAND_READ_ID       0x9f
+#define SPI_SST25LF_COMMAND_WRITE_S_EN    0x50
+#define SPI_SST25LF_COMMAND_WRITE_S       0x01
+
+// PMC commands
+#define SPI_PMC25LV_COMMAND_WRITE         0x02
+#define SPI_PMC25LV_COMMAND_READ          0x03
+#define SPI_PMC25LV_COMMAND_ERASE         0xd7
+#define SPI_PMC25LV_COMMAND_WRITE_DISABLE 0x04
+#define SPI_PMC25LV_COMMAND_READ_STATUS   0x05
+#define SPI_PMC25LV_COMMAND_WRITE_ENABLE  0x06
+#define SPI_PMC25LV_COMMAND_READ_ID       0xab
+#define SPI_PMC25LV_COMMAND_WRITE_S_EN    0x06
+#define SPI_PMC25LV_COMMAND_WRITE_S       0x01
+
+// Atmel commands
+#define SPI_AT26DF_COMMAND_WRITE         0x02
+#if FAST_READ_SUPPORT == 0
+#define SPI_AT26DF_COMMAND_READ          0x03        // Read Byte
+#elif FAST_READ_SUPPORT == 1
+#define SPI_AT26DF_COMMAND_READ          0x0B        // Fast Read
+#elif FAST_READ_SUPPORT == 2
+#define SPI_AT26DF_COMMAND_READ          0x3B        // Dual Output Fast Read
+#endif
+#define SPI_AT26DF_COMMAND_ERASE         0x20
+#define SPI_AT26DF_COMMAND_WRITE_DISABLE 0x04
+#define SPI_AT26DF_COMMAND_READ_STATUS   0x05
+#define SPI_AT26DF_COMMAND_WRITE_ENABLE  0x06
+#define SPI_AT26DF_COMMAND_READ_ID       0x9f
+#define SPI_AT26DF_COMMAND_WRITE_S_EN    0x00
+#define SPI_AT26DF_COMMAND_WRITE_S       0x01
+// ATMEL 26DF321 32Mbit SPI Flash part support
+#define SPI_AT26DF_COMMAND_PROTECT       0x36
+#define SPI_AT26DF_COMMAND_UNPROTECT     0x39
+
+// Winbond W25Xxx serial flash commands
+#define SPI_WIN_W25X_COMMAND_WRITE         0x02     // page program
+#define SPI_WIN_W25X_COMMAND_READ          0x03     // Read Byte
+#define SPI_WIN_W25X_COMMAND_ERASE         0x20     // erase 4K sectors
+#define SPI_WIN_W25X_COMMAND_WRITE_DISABLE 0x04     // Write Disable
+#define SPI_WIN_W25X_COMMAND_READ_STATUS   0x05     // read Status Register
+#define SPI_WIN_W25X_COMMAND_WRITE_ENABLE  0x06     // Write Enable
+#define SPI_WIN_W25X_COMMAND_READ_ID       0x90     // Manufacturer/Device ID
+#define SPI_WIN_W25X_COMMAND_WRITE_S       0x01     // Write Status register
+
+// MXIC MX25Lx005 commands
+#define SPI_MXIC_M25L_COMMAND_WRITE             0x02        // page program
+#define SPI_MXIC_M25L_COMMAND_READ              0x03        // Read Byte
+#define SPI_MXIC_M25L_COMMAND_ERASE             0x20        // erase 4K sectors
+#define SPI_MXIC_M25L_COMMAND_WRITE_DISABLE     0x04        // Write Disable
+#define SPI_MXIC_M25L_COMMAND_READ_STATUS       0x05        // read Status Register
+#define SPI_MXIC_M25L_COMMAND_WRITE_ENABLE      0x06        // Write Enable
+#define SPI_MXIC_M25L_COMMAND_READ_ID           0x9f        // Manufacturer/Device ID
+#define SPI_MXIC_M25L_COMMAND_WRITE_S           0x01        // Write Status register
+
+// Spansion S25FL00xA commands
+#define SPI_S25FL00xA_COMMAND_WRITE             0x02        // page program
+#define SPI_S25FL00xA_COMMAND_READ              0x03        // Read Byte
+#define SPI_S25FL00xA_COMMAND_ERASE             0xd8        // erase 64K sectors
+#define SPI_S25FL00xA_COMMAND_WRITE_DISABLE     0x04        // Write Disable
+#define SPI_S25FL00xA_COMMAND_READ_STATUS       0x05        // read Status Register
+#define SPI_S25FL00xA_COMMAND_WRITE_ENABLE      0x06        // Write Enable
+#define SPI_S25FL00xA_COMMAND_READ_ID           0x9f        // Manufacturer/Device ID
+#define SPI_S25FL00xA_COMMAND_WRITE_S           0x01        // Write Status register
+
+// ESMT F25L00xA commands
+#define SPI_ESMT_F25L00x_COMMAND_WRITE          0x02        // page program
+#define SPI_ESMT_F25L00x_COMMAND_READ           0x03        // Read Byte
+#define SPI_ESMT_F25L00x_COMMAND_ERASE          0x20        // erase 4K sectors
+#define SPI_ESMT_F25L00x_COMMAND_WRITE_DISABLE  0x04        // Write Disable
+#define SPI_ESMT_F25L00x_COMMAND_READ_STATUS    0x05        // read Status Register
+#define SPI_ESMT_F25L00x_COMMAND_WRITE_ENABLE   0x06        // Write Enable
+#define SPI_ESMT_F25L00x_COMMAND_READ_ID        0x90        // Manufacturer/Device ID
+#define SPI_ESMT_F25L00x_COMMAND_WRITE_S_EN     0x50        // Write Status Enable register
+#define SPI_ESMT_F25L00x_COMMAND_WRITE_S        0x01        // Write Status register
+
+// ST Micro M25Pxx commands
+#define SPI_M25Pxx_COMMAND_WRITE            0x02        // page program
+#define SPI_M25Pxx_COMMAND_READ             0x03        // Read Byte
+#define SPI_M25Pxx_COMMAND_ERASE            0xd8        // erase 64K sectors
+#define SPI_M25Pxx_COMMAND_WRITE_DISABLE    0x04        // Write Disable
+#define SPI_M25Pxx_COMMAND_READ_STATUS      0x05        // read Status Register
+#define SPI_M25Pxx_COMMAND_WRITE_ENABLE     0x06        // Write Enable
+#define SPI_M25Pxx_COMMAND_READ_ID          0x9f        // Manufacturer/Device ID
+#define SPI_M25Pxx_COMMAND_WRITE_S          0x01        // Write Status register
+
+// ST Micro M25Pxx commands
+#define SPI_M25PExx_COMMAND_WRITE           0x02        // page program
+#if FAST_READ_SUPPORT == 0
+#define SPI_M25PExx_COMMAND_READ            0x03        // Read Byte
+#elif FAST_READ_SUPPORT == 1
+#define SPI_M25PExx_COMMAND_READ            0x0B        // Fast Read
+#elif FAST_READ_SUPPORT == 2
+#define SPI_M25PExx_COMMAND_READ            0x3B        //  Dual Output Fast Read
+#endif
+#define SPI_M25PExx_COMMAND_ERASE           0xD8        // erase 64K sectors
+#define SPI_M25PExx_COMMAND_PAGE_ERASE      0xDB        // erase 256 byte pages
+#define SPI_M25PExx_COMMAND_WRITE_DISABLE   0x04        // Write Disable
+#define SPI_M25PExx_COMMAND_READ_STATUS     0x05        // read Status Register
+#define SPI_M25PExx_COMMAND_WRITE_ENABLE    0x06        // Write Enable
+#define SPI_M25PExx_COMMAND_READ_ID         0x9F        // Manufacturer/Device ID
+#define SPI_M25PExx_COMMAND_WRITE_S         0x01        // Write Status register
+
+
+//#define SECTOR_SIZE_4KB   0x1000  // Common 4kBytes sector size
+//#define SECTOR_SIZE_64KB  0x10000  // Common 64kBytes sector size
+#define BLOCK_SIZE_64KB     0x00010000  // Common 64kBytes block size
+#define MAX_FWH_SIZE        0x00100000  // 8Mbit (Note that this can also be used for the 4Mbit )
+
+
+extern const UINT8 SpiMaxTransfer;
+
+// SPI default opcode slots
+extern const UINT8 SpiOpcodeWriteIndex;
+extern const UINT8 SpiOpcodeReadIndex;
+extern const UINT8 SpiOpcodeEraseIndex;
+extern const UINT8 SpiOpcodeWriteStatusIndex;
+
+#endif
+
+//<AMI_STHDR_START>
+//============================================================================
+// Structure:   EX_FLASH_PART
+//
+// Description: This structure contains variables that define the detals and
+//              and command set of flash part.
+//
+// Fields:
+//      FlashCommandMenu - FLASH_INFO - Defines the flash part command sets.
+//      FlashCapacity - UINT32 - Defines the Capacity of flash part.
+//      FlashVenDevId - UINT32 - Defines the Vendor and Device ID of flash part.
+//      DeviceName - UINT8 * - Pointer to a buffer that can contain the part
+//          number of flash part (Reserved for future used).
+//
+// Referral:
+//      None
+//============================================================================
+//<AMI_STHDR_END>
+#pragma pack(push, 1)
+
+typedef struct _EX_FLASH_PART {
+    FLASH_INFO                      FlashCommandMenu;
+    UINT32                          FlashCapacity;
+    UINT32                          FlashVenDevId;
+    UINT8                           AAIWordProgram;
+    UINT8                           GlobalBlockUnlock;
+    UINT8                           bReserved[2];
+} EX_FLASH_PART;
+
+#pragma pack(pop)
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2008, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/Flash/SPI/SpiFlash.mak b/Board/Flash/SPI/SpiFlash.mak
new file mode 100644
index 0000000..33003e8
--- /dev/null
+++ b/Board/Flash/SPI/SpiFlash.mak
@@ -0,0 +1,115 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2010, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+# $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/SpiFlash.mak 2     4/24/13 11:11p Thomaschen $
+#
+# $Revision: 2 $
+#
+# $Date: 4/24/13 11:11p $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/SpiFlash.mak $
+# 
+# 2     4/24/13 11:11p Thomaschen
+# 
+# 5     10/25/10 5:55a Calvinchen
+# Added support for PEI Flash Library.
+# 
+# 4     6/24/09 3:14a Calvinchen
+# (EIP22177) Updated for Aptio Source Enhancement. 
+#
+# 3     4/27/09 3:19a Calvinchen
+# 1.Added support for Winbond 25Q128
+# 2.(EIP20459) Added Multiple SPI CSP component support.
+#
+# 2     8/26/08 2:54a Calvinchen
+# 1.Added support for AMTME 25DF641.
+# 2.Fixed Fail to un-protect ATMEL flash.
+# 3.Fixed building failed if $(CFLAGS) = /W4.
+#
+# 1     3/13/08 6:31a Calvinchen
+#
+# 1     12/18/06 3:39p Robert
+# Initial Check in
+#
+# 1     10/31/06 2:30p Sivagarn
+# Initial Checkin
+#
+#
+#**********************************************************************
+
+
+#<AMI_FHDR_START>
+#
+# Name: FlashSrc.mak
+#
+# Description:
+#
+#<AMI_FHDR_END>
+#**********************************************************************
+all : SPIFlash
+
+!IFNDEF SPI_CSP_DIR
+SPI_CSP_DIR = $(SPIFlash_DIR)\Template
+!ENDIF
+SPIFlash : $(BUILD_DIR)\SPIFlash.mak SPIFlashBin
+
+#---------------------------------------------------------------------------
+#			Generic SPIFLASH dependencies
+#---------------------------------------------------------------------------
+$(BUILD_DIR)\SPIFlash.mak : $(SPIFlash_DIR)\$(@B).cif $(SPI_CSP_DIR)\SpiCspSrc.cif $(SPIFlash_DIR)\$(@B).mak $(BUILD_RULES)
+    $(CIF2MAK) $(SPIFlash_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) $(SPI_CSP_DIR)\SpiCspSrc.cif
+
+#---------------------------------------------------------------------------
+#			Create SPIFlash Library
+#---------------------------------------------------------------------------
+SPI_INCLUDES = \
+/I $(SPIFlash_DIR)
+
+SPIFLASH_OBJECTS = $(BUILD_DIR)\$(SPIFlash_DIR)\SpiIdentify.obj \
+                   $(BUILD_DIR)\$(SPI_CSP_DIR)\SpiFlash.obj
+
+SPIFlashBin :
+                @set INCLUDE=%%INCLUDE%%
+                $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+                /f $(BUILD_DIR)\SPIFlash.mak all\
+                "CFLAGS=$(CFLAGS:/W4=/W3) $(SPI_INCLUDES)"\
+                NAME=SPIFlash \
+                OBJECTS="$(SPIFLASH_OBJECTS)" \
+                TYPE=LIBRARY LIBRARY_NAME=$(SPIFLASHLIB)
+!IF "$(x64_BUILD)"=="1" && "$(BUILD_PEI_FLASH_LIB)"=="1"
+                $(MAKE) /$(MAKEFLAGS) BUILD_ROOT=$(BUILD_DIR)\
+                "EXT_OBJS=$(**:Build\=Build\IA32\)" PROJECT_DIR=$(PROJECT_DIR)\
+                /f $(BUILD_DIR)\SPIFlash.mak all\
+                "CFLAGS=$(CFLAGS:/W4=/W3) $(SPI_INCLUDES)"\
+                BUILD_DIR=$(BUILD_DIR)\IA32\
+                TYPE=PEI_LIBRARY NAME=SPIFlash
+!ENDIF
+
+$(SPIFLASHLIB) : SPIFlash
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2010, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/Flash/SPI/SpiFlash.sdl b/Board/Flash/SPI/SpiFlash.sdl
new file mode 100644
index 0000000..aa4b757
--- /dev/null
+++ b/Board/Flash/SPI/SpiFlash.sdl
@@ -0,0 +1,232 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+#**********************************************************************
+# $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/SpiFlash.sdl 2     4/24/13 11:11p Thomaschen $
+#
+# $Revision: 2 $
+#
+# $Date: 4/24/13 11:11p $
+#**********************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/SpiFlash.sdl $
+# 
+# 2     4/24/13 11:11p Thomaschen
+# 
+# 8     4/27/12 5:12a Calvinchen
+# [TAG]  		EIP86044
+# [Category]  	Improvement
+# [Description]  	[Pegatron-DT] SMIFlash module update for display SPIROM
+# size in AFU
+# [Files]  		SpiFlash.sdl
+# SpiIdentify.c
+# 
+# 7     8/24/11 7:58a Calvinchen
+# Improvement :
+# Added Token "FAST_READ_SUPPORT" for switching the SPI
+# Read(03)/FastRead(0B)/DualOutputFastRead(3B) command. To use the
+# FastRead and the Dual Output Fast Read command MUST have Hardware SPI
+# support. **Only validated with Intel Mahobay platform (Southbridge:
+# PatherPoint)**
+# 
+# 6     2/10/11 5:43a Calvinchen
+# [TAG]  		EIP53437
+# [Category]  	Bug Fix
+# [Severity]  	Minor
+# [Symptom]  	Corrected Numonyx M25P128 Minimum Sector Size to 256K. 
+# [RootCause]  	None.
+# [Solution]  	None.
+# [Files]  		SpiFlash.sdl
+# SpiFlash.mak
+# SpiFlash.h
+# SpiIdentify.c
+# SpiFlash.cif
+# 
+# 5     10/25/10 5:55a Calvinchen
+# Added support for PEI Flash Library.
+# 
+# 4     6/24/09 3:14a Calvinchen
+# (EIP22177) Updated for Aptio Source Enhancement. 
+#
+#
+#**********************************************************************
+TOKEN
+	Name  = "SPIFlash_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable SPI Flash support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SPIFLASHLIB"
+	Value  = "$(BUILD_DIR)\SPIFlash.lib"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "SST_25VFxxx"
+	Value  = "1"
+	Help  = "Support for SST 25VF series and ESMT SPI flash parts."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SST_25LFxxx"
+	Value  = "1"
+	Help  = "Support for SST 25LF040, 25LF080A SPI flash parts."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "STM_25PExx"
+	Value  = "1"
+	Help  = "Support for ST-Micro, SPANSION, Winbond, PMC, Eon, AMIC, MXIC and Intel SPI flash parts."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ATMEL_26DFxxx"
+	Value  = "1"
+	Help  = "Support for ATMEL SPI flash parts."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "Numonyx_M25P128"
+	Value  = "0"
+	Help  = "Support for Numonyx M25P128 SPI flash parts."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "FLASH_BLOCK_SIZE"
+	Value  = "0x40000"
+	Help  = "Size of the Flash Device Block"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Lock = Yes
+	Token = "Numonyx_M25P128" "=" "1"
+End
+
+TOKEN
+	Name  = "SPI_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Master = Yes
+End
+
+TOKEN
+	Name  = "FAST_READ_SUPPORT"
+	Value  = "0"
+	Help  = "Fast Read Support(Need Hardware SPI Support). 0 - Read(03), 1 - Fast Read(0B), 2 - Dual Output Fast Read(3B)."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "AAI_WORD_PROGRAM"
+	Value  = "0"
+	Help  = "AAI Word Program Support(SST/PCT only)."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "BLOCK_PROTECT_ENABLE"
+	Value  = "0"
+	Help  = "Support for enabling the softwaft block protect mode. ON : set BP 0,1,2 of flash status register."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+PATH
+	Name  = "SPIFlash_DIR"
+End
+
+MODULE
+	Help  = "Includes FlashSrc.mak to Project"
+	File  = "SPIFlash.mak"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\SPIFlash.lib"
+	Parent  = "$(Flash_DIR)\SPIFlash.lib"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "$(Flash_DIR)\SPIFlash.lib"
+	Parent  = "FLASHLISTLIB"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "IdentifySst_25VF,"
+	Parent  = "FlashList"
+	Token = "SST_25VFxxx" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "IdentifyStm_25PExx,"
+	Parent  = "FlashList"
+	Token = "STM_25PExx" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "IdentifyAtmel_26DF,"
+	Parent  = "FlashList"
+	Token = "ATMEL_26DFxxx" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "IdentifySst_25LF,"
+	Parent  = "FlashList"
+	Token = "SST_25LFxxx" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/Board/Flash/SPI/SpiIdentify.c b/Board/Flash/SPI/SpiIdentify.c
new file mode 100644
index 0000000..fd0d37f
--- /dev/null
+++ b/Board/Flash/SPI/SpiIdentify.c
@@ -0,0 +1,865 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/SpiIdentify.c 2     4/24/13 11:11p Thomaschen $
+//
+// $Revision: 2 $
+//
+// $Date: 4/24/13 11:11p $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Board/Flash/SPI/SpiIdentify.c $
+// 
+// 2     4/24/13 11:11p Thomaschen
+// 
+// 37    3/08/13 3:12a Calvinchen
+// [TAG]  		EIP110515
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	Microchip SST26VF064B & SST26VF064BA 8MB SPI Flash part
+// support 
+// [RootCause]  	Need "Global Block Protection Unlock" before programming.
+// [Solution]  	Added "Global Block Protection Unlock" before programming.
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// SpiFlash.cif
+// 
+// 36    2/18/13 5:15a Calvinchen
+// [TAG]  		EIP114488
+// [Category]  	Improvement
+// [Description]  	1. Added MXIC MX25U6435F SPI Flash part support
+// 2. Added GigaDevice 25LQ series flash part.
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// 
+// 35    1/14/13 5:40a Calvinchen
+// [TAG]  		EIP110515
+// [Category]  	Improvement
+// [Description]  	Microchip SST26VF064B & SST26VF064BA 8MB SPI Flash part
+// support
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// 
+// 34    12/13/12 2:23a Calvinchen
+// Added support for winbond W25Q F and W series Flash Parts.
+// 
+// 33    10/18/12 3:29a Calvinchen
+// Improvement:
+// 1. Changed N25Q128 to 4K erase.
+// 2. Added N25Q128A support. 
+// Bug Fixed :1. Fixed for ESMT 25L B Series.
+// 
+// 32    7/18/12 6:10a Calvinchen
+// 1. Changed N25Q128 to 4K erase.
+// 2. Added N25Q128A support.
+// 
+// 31    4/27/12 5:12a Calvinchen
+// [TAG]  		EIP86044
+// [Category]  	Improvement
+// [Description]  	[Pegatron-DT] SMIFlash module update for display SPIROM
+// size in AFU
+// [Files]  		SpiFlash.sdl
+// SpiIdentify.c
+// 
+// 30    4/02/12 1:41a Klzhan
+// [TAG]  		EIP86044
+// [Category]  	Improvement
+// [Description]  	Customized AFU to support a parameter to display the
+// current SPI's name and size
+// 
+// 29    10/31/11 6:46a Calvinchen
+// [TAG]  		EIP68872
+// [Category]  	Improvement
+// [Description]  	Added ESMT 25L64QA.
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// 
+// 28    8/24/11 7:58a Calvinchen
+// Improvement :
+// Added Token "FAST_READ_SUPPORT" for switching the SPI
+// Read(03)/FastRead(0B)/DualOutputFastRead(3B) command. To use the
+// FastRead and the Dual Output Fast Read command MUST have Hardware SPI
+// support. **Only validated with Intel Mahobay platform (Southbridge:
+// PatherPoint)**
+// 
+// 27    8/02/11 12:05a Calvinchen
+// [TAG]  		EIP48934
+// [Category]  	Improvement
+// [Description]  	Missing support for flash device Numonyx NX25Q064 on
+// Sugarbay platform
+// [Files]  		SpiIdentify.c
+// 
+// 26    7/21/11 5:07a Calvinchen
+// [TAG]  		EIP65366
+// [Category]  	Improvement
+// [Description]  	New SPI Flash supports for EON 25QH and ESMT 25L PA
+// flash part. 
+// [Files]  		SpiFlash.h
+// SpiIdentify.c
+// 
+// 25    4/08/11 3:08a Chunweitseng
+// [TAG]  		EIP57327
+// [Category]  	Improvement
+// [Description]  	 Added Support for FIDELIX FM25Q32A/64A and AMIC
+// 25LQ032.
+// 
+// [Files]  		SpiFlash.h, SpiIdentify.c
+// 
+// 24    2/17/11 3:36a Klzhan
+// Add support 64K flash.
+// 
+// 23    2/10/11 5:43a Calvinchen
+// [TAG]  		EIP53437
+// [Category]  	Bug Fix
+// [Severity]  	Minor
+// [Symptom]  	Corrected Numonyx M25P128 Minimum Sector Size to 256K. 
+// [RootCause]  	None.
+// [Solution]  	None.
+// [Files]  		SpiFlash.sdl
+// SpiFlash.mak
+// SpiFlash.h
+// SpiIdentify.c
+// SpiFlash.cif
+// 
+// 22    11/25/10 3:02a Calvinchen
+// Added Support for Micron/Numonyx N25Q128.
+// 
+// 19    9/14/10 3:31a Calvinchen
+// Improved for adding the "SPI_INITIALIAL_WITH_VSCC" token support for
+// Intel ICHx SPI. 
+// 
+// 18    5/21/10 2:13a Calvinchen
+// Bug fixed: Build failed with "undeclared identifier".
+// 
+// 17    3/11/10 6:43a Calvinchen
+// Improvement : Added SST AAIWordProgram SPI command to speed up the
+// programming time.
+// 
+// 16    1/07/10 5:34a Calvinchen
+// Addes support for Spansion S25FL128/129P.
+// 
+// 15    12/31/09 1:50a Klzhan
+// Improvement : Support EON 25Q32/64.
+// 
+// 14    12/23/09 6:13a Calvinchen
+// Improvement:1.Added FWH/LPC/STD Flash Device Number support.
+// 
+// 13    12/22/09 2:30a Calvinchen
+// Added support for ATMEL 25DQ161.
+//
+// 12    12/15/09 5:49a Calvinchen
+// Improvement :
+// 1.Added support for GigaDevie 25Q80/16.
+// 2.Added Flash Chip Name support.
+//
+// 10    6/24/09 3:14a Calvinchen
+// (EIP22177) Updated for Aptio Source Enhancement.
+//
+// 9     5/11/09 7:21a Calvinchen
+// Added support for SST 25VF064C and MXIC MX25L1635/3235/6435..
+//
+// 7     3/12/09 4:47a Calvinchen
+// Improvement : Added Unprotect Command OpCode (39h) to AMTEL SPI
+// FLASH_INFO structure.
+// Bug Fixed : Sometimes failed to unlock the Block Protect of SST SPI
+// flash if Label "4.6.3_Flash_Combined_2_6" or later.
+//
+// 6     12/10/08 5:53a Calvinchen
+// Added support for Winbond W25Q80/16 1M/2M SPI flash.
+//
+// 5     9/30/08 10:09a Calvinchen
+// According to Intel ICH7/ICH8/ICH9/ICH10 - SPI Family Flash Programming
+// Guide Application Note - Rev#2.4,
+// Section#5.3 Software Sequencing Opcode Requirements and
+// Recommendations,It is strongly recommended that the "9Fh" JEDEC ID be
+// used instead of "90h" or "AB".
+// Intel utilities such as the Flash Programming tool (Fprog.exe and
+// fpt.exe) will incorrectly detect the flash part in the system and it
+// may lead to undesired program operation.
+//
+// 4     9/11/08 2:30a Calvinchen
+// Added support for EON 25F32.
+//
+// 3     8/26/08 2:54a Calvinchen
+// 1.Added support for AMTME 25DF641.
+// 2.Fixed Fail to un-protect ATMEL flash.
+// 3.Fixed building failed if $(CFLAGS) = /W4.
+//
+// 2     5/09/08 3:35a Calvinchen
+// Added support for STM M25PF32.
+//
+// 1     3/13/08 6:31a Calvinchen
+//
+// 7     3/26/07 7:22p Robert
+// Coding standard updates
+//
+// 6     2/20/07 6:45p Robert
+// added support for the new sector size variable in the data structure
+// and added support for the changed lock functionality
+//
+// 5     2/13/07 3:45p Robert
+// added support for SST 25VF016B and fixed a coding error in one of the
+// identify functions  prototype
+//
+// 4     2/13/07 11:30a Robert
+//
+// 1     12/18/06 3:39p Robert
+// Initial Check in
+//
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//
+// Name:    SpiIdentify.c
+//
+// Description: Provides device specific indentify functions for the
+//  supported spi parts
+//
+//<AMI_FHDR_END>
+//**********************************************************************
+
+//----------------------------------------------------------------------------
+// Includes
+#include <efi.h>
+#include <AmiDxeLib.h>
+#include "FlashPart.h"
+#include "SpiFlash.h"
+#include "token.h"
+//----------------------------------------------------------------------------
+// Local defines for transaction types
+#ifndef SPI_OPCODE_TYPE_READ_NO_ADDRESS
+#define SPI_OPCODE_TYPE_READ_NO_ADDRESS     0x0
+#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS    0x1
+#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS   0x2
+#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS  0x3
+#endif
+//----------------------------------------------------------------------------
+// Module level global data
+UINT32  MfgDevId = 0;
+extern  UINT16          gFlashId;
+extern  FLASH_PART      mCommonSpiFlash;
+extern  EX_FLASH_PART   mExFlashPart;
+extern  UINT8           pFlashDeviceNumber[FLASH_PART_STRING_LENGTH];
+//----------------------------------------------------------------------------
+// Extern Function Prototypes
+extern
+BOOLEAN
+CommonSpiReadId (
+    FLASH_INFO          *FlashInfo,
+    UINT32              *dFlashId
+);
+extern
+VOID
+ReinitializeSpiEnvironment (
+    FLASH_INFO          *FlashInfo
+);
+//----------------------------------------------------------------------------
+// Flash Part Data Structures
+FLASH_INFO Sst_25VF =
+    {
+        // Write Byte
+        {SPI_SST25LF_COMMAND_WRITE,         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS},
+         // Read Data
+        {SPI_SST25VF_COMMAND_READ,          SPI_OPCODE_TYPE_READ_WITH_ADDRESS},
+        // Erase 4k Sector
+        {SPI_SST25LF_COMMAND_ERASE,         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS},
+        // Read Device Status Reg
+        {SPI_SST25LF_COMMAND_READ_STATUS,   SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Read device ID
+        {SPI_SST25VF_COMMAND_READ_ID,       SPI_OPCODE_TYPE_READ_WITH_ADDRESS},
+        // Write Status Register
+        {SPI_SST25LF_COMMAND_WRITE_S,       SPI_OPCODE_TYPE_WRITE_NO_ADDRESS},
+        // Write Status Enable
+        {SPI_SST25LF_COMMAND_WRITE_S_EN,    SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Write Enable
+        {SPI_SST25LF_COMMAND_WRITE_ENABLE,  SPI_OPCODE_TYPE_WRITE_NO_ADDRESS},
+        1,                                  // Page Size
+        SECTOR_SIZE_4KB
+    };
+
+FLASH_INFO Sst_25LF =
+    {
+        // Write Byte
+        {SPI_SST25LF_COMMAND_WRITE,         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS},
+        // Read Data
+        {SPI_SST25LF_COMMAND_READ,          SPI_OPCODE_TYPE_READ_WITH_ADDRESS},
+        // Erase 4k Sector
+        {SPI_SST25LF_COMMAND_ERASE,         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS},
+        // Read Device Status Reg
+        {SPI_SST25LF_COMMAND_READ_STATUS,   SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Read device ID
+        {SPI_SST25LF_COMMAND_READ_ID,       SPI_OPCODE_TYPE_READ_WITH_ADDRESS},
+        // Write Status Register
+        {SPI_SST25LF_COMMAND_WRITE_S,       SPI_OPCODE_TYPE_WRITE_NO_ADDRESS},
+        // Write Status Enable
+        {SPI_SST25LF_COMMAND_WRITE_S_EN,    SPI_OPCODE_TYPE_WRITE_NO_ADDRESS},
+        // Write Enable
+        {SPI_SST25LF_COMMAND_WRITE_ENABLE,  SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        1,                                  // Page Size
+        SECTOR_SIZE_4KB
+    };
+
+FLASH_INFO Stm_25PE =
+    {
+        // Write Byte
+        {SPI_M25PExx_COMMAND_WRITE,         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS},
+        // Read Data
+        {SPI_M25PExx_COMMAND_READ,          SPI_OPCODE_TYPE_READ_WITH_ADDRESS},
+        // Erase 64k Sector
+        {SPI_M25PExx_COMMAND_ERASE,         SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS},
+        // Read Device Status Reg
+        {SPI_M25PExx_COMMAND_READ_STATUS,   SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Read device ID
+        {SPI_M25PExx_COMMAND_READ_ID,       SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Write Status Register
+        {SPI_M25PExx_COMMAND_WRITE_S,       SPI_OPCODE_TYPE_WRITE_NO_ADDRESS},
+        // Write Status Enable - Not available on this part
+        {0,                                 SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Write Enable
+        {SPI_M25PExx_COMMAND_WRITE_ENABLE,  SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        256,
+        SECTOR_SIZE_64KB
+    };
+
+FLASH_INFO Atmel_26DF =
+    {
+        // Write Byte
+        {SPI_AT26DF_COMMAND_WRITE,          SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS},
+        // Read Data
+        {SPI_AT26DF_COMMAND_READ,           SPI_OPCODE_TYPE_READ_WITH_ADDRESS},
+        // Erase 4k Sector
+        {SPI_AT26DF_COMMAND_ERASE,          SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS},
+        // Read Device Status Reg
+        {SPI_AT26DF_COMMAND_READ_STATUS,    SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Read device ID
+        {SPI_AT26DF_COMMAND_READ_ID,        SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Write Status Register
+        {SPI_AT26DF_COMMAND_WRITE_S,        SPI_OPCODE_TYPE_WRITE_NO_ADDRESS},
+        // Write Status Enable
+        {SPI_AT26DF_COMMAND_UNPROTECT,      SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        // Write Enable
+        {SPI_AT26DF_COMMAND_WRITE_ENABLE,   SPI_OPCODE_TYPE_READ_NO_ADDRESS},
+        256,
+        SECTOR_SIZE_4KB
+    };
+//----------------------------------------------------------------------------
+// Functions Definitions
+
+//----------------------------------------------------------------------------
+// Identify Functions
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   IdentifySst_25LF
+//
+// Description: This function identifies the supported SPI flash parts and
+//              returns appropriate flash device API pointer. If flash part is
+//              not supported by this module it will return FALSE.
+//              Supports the following SPI parts
+//              SST 25LF040/080/106A, ESMT 25L004/008/016A
+//
+//
+// Input:       pBlockAddress   Block address of the flash part. Can be used to
+//                              send ID command
+//
+// Output:      **FlashApi      Pointer to hold the returned flash API
+//
+// Return:      TRUE            If flash part is supported, FlashApi contains
+//                              routines to handle the flash requests
+//              FALSE           Flash part is not supported
+//
+// Note:        This routine is part of the global flash init list. Make sure
+//              it is properly linked to the init list "FlashList" (in SDL file)
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+IdentifySst_25LF    (
+    IN  volatile UINT8      *pBlockAddress,
+    OUT FLASH_PART          **FlashStruct
+)
+{
+    if ( !CommonSpiReadId( &Sst_25LF, &MfgDevId ) )    return FALSE;
+    switch ( (UINT16)MfgDevId ) {
+        // Is SST 4M SPI flash part ?
+        case SST_25LF040A :
+            mExFlashPart.FlashCapacity = 0x80000;
+            MemCpy ( pFlashDeviceNumber, "SST 25LF040", 14 );
+            break;
+        // Is SST 8M SPI flash part ?
+        case SST_25LF080A :
+            mExFlashPart.FlashCapacity = 0x100000;
+            MemCpy ( pFlashDeviceNumber, "SST 25LF080", 14 );
+            break;
+        default :
+            return  FALSE;
+    }
+    *FlashStruct = &mCommonSpiFlash;
+    MemCpy( &mExFlashPart.FlashCommandMenu, &Sst_25LF, sizeof(FLASH_INFO) );
+    mExFlashPart.FlashVenDevId = MfgDevId;
+    gFlashId = MfgDevId;
+    *(UINT32*)(pFlashDeviceNumber + FLASH_PART_STRING_LENGTH - 4) = \
+                                                mExFlashPart.FlashCapacity;
+    (*FlashStruct)->FlashProgramSize = Sst_25LF.PageSize;
+    (*FlashStruct)->FlashSectorSize = Sst_25LF.SectorSize;
+    (*FlashStruct)->FlashPartNumber = pFlashDeviceNumber;
+    // Update the OpCode to OpMenu immediately if need.
+    // ReinitializeSpiEnvironment ( &mExFlashPart.FlashCommandMenu );
+    return  TRUE;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   IdentifyAtmel_26DF
+//
+// Description: This function identifies the supported LPC flash parts and
+//              returns appropriate flash device API pointer. If flash part is
+//              not supported by this module it will return FALSE.
+//              Supports the following SPI parts
+//              ATMEL 26DFxx parts
+//
+// Input:   pBlockAddress   Block address of the flash part. Can be used to
+//                              send ID command
+//
+// Output:  **FlashApi      Pointer to hold the returned flash API
+//
+// Return:  TRUE            If flash part is supported, FlashApi contains
+//                              routines to handle the flash requests
+//          FALSE           Flash part is not supported
+//
+// Note:   This routine is part of the global flash init list. Make sure
+//         it is properly linked to the init list "FlashList" (in SDL file)
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+IdentifyAtmel_26DF  (
+    IN  volatile UINT8      *pBlockAddress,
+    OUT FLASH_PART          **FlashStruct
+)
+{
+    if ( !CommonSpiReadId( &Atmel_26DF, &MfgDevId ) )    return FALSE;
+    switch ( (UINT16)MfgDevId ) {
+        // Is Atmel 4M SPI flash part ?
+        case ATMEL_26DF041 :
+            mExFlashPart.FlashCapacity = 0x80000;
+            MemCpy ( pFlashDeviceNumber, "ATMEL 26DF041/25DF041", 21 );
+            break;
+        // Is Atmel 8M SPI flash part ?
+        case ATMEL_26DF081 :
+            mExFlashPart.FlashCapacity = 0x100000;
+            MemCpy ( pFlashDeviceNumber, "ATMEL 26DF081/25DF081", 21 );
+            break;
+        // Is Atmel 16M SPI flash part ?
+        case ATMEL_26DF161 :
+        case ATMEL_25DQ161 :
+            mExFlashPart.FlashCapacity = 0x200000;
+            MemCpy ( pFlashDeviceNumber, "ATMEL 26DF161/25DQ161", 21 );
+            break;
+        // Is Atmel 32M SPI flash part ?
+        case ATMEL_26DF321 :
+            mExFlashPart.FlashCapacity = 0x400000;
+            MemCpy ( pFlashDeviceNumber, "ATMEL 26DF321/25DF321", 21 );
+            break;
+        // Is Atmel 64M SPI flash part ?
+        case ATMEL_25DF641 :
+            mExFlashPart.FlashCapacity = 0x800000;
+            MemCpy ( pFlashDeviceNumber, "ATMEL 26DF641/25DF641", 21 );
+            break;
+        default :   return  FALSE;
+    }
+    *FlashStruct = &mCommonSpiFlash;
+    MemCpy( &mExFlashPart.FlashCommandMenu, &Atmel_26DF, sizeof(FLASH_INFO) );
+    mExFlashPart.FlashVenDevId = MfgDevId;
+    gFlashId = MfgDevId;
+    *(UINT32*)(pFlashDeviceNumber + FLASH_PART_STRING_LENGTH - 4) = \
+                                                mExFlashPart.FlashCapacity;
+    (*FlashStruct)->FlashProgramSize = Atmel_26DF.PageSize;
+    (*FlashStruct)->FlashSectorSize = Atmel_26DF.SectorSize;
+    (*FlashStruct)->FlashPartNumber = pFlashDeviceNumber;
+    // Update the OpCode to OpMenu immediately if need.
+    ReinitializeSpiEnvironment ( &mExFlashPart.FlashCommandMenu );
+    return  TRUE;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   StmCheckMemoryCapacity
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT32
+StmCheckMemoryCapacity  (
+    IN UINT32               dVenDevId
+)
+{
+    switch ( ( dVenDevId & 0x00FF0000 ) >> 16 ) {
+        case 0x10 : return ( 0x10000 );
+        case 0x11 : return ( 0x20000 );
+        case 0x12 : return ( 0x40000 );
+        case 0x13 : return ( 0x80000 );
+        case 0x14 : return ( 0x100000 );
+        case 0x15 : return ( 0x200000 );
+        case 0x36 : // MX25U32xx 
+        case 0x16 : return ( 0x400000 );
+        case 0x37 : // MX25U64xx 
+        case 0x17 : return ( 0x800000 );
+        case 0x18 : return ( 0x1000000 );
+    }
+    return ( FLASH_SIZE );
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   SpansionCheckMemoryCapacity
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT32
+SpansionCheckMemoryCapacity  (
+    IN UINT32               dVenDevId
+)
+{
+    switch ( ( dVenDevId & 0x00FF0000 ) >> 16 ) {
+        case 0x12 : return ( 0x80000 );
+        case 0x13 : return ( 0x100000 );
+        case 0x14 : return ( 0x200000 );
+        case 0x46 :                         // PMC 25LQ032
+        case 0x15 : return ( 0x400000 );
+        case 0x16 : return ( 0x800000 );
+        case 0x17 : return ( 0x1000000 );
+    }
+    return ( FLASH_SIZE );
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   IntelCheckMemoryCapacity
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT32
+IntelCheckMemoryCapacity  (
+    IN UINT32               dVenDevId
+)
+{
+    switch ( ( dVenDevId & 0x00FF0000 ) >> 16 ) {
+        case 0x11 :
+        case 0x15 :   return ( 0x200000 );
+        case 0x12 :
+        case 0x16 :   return ( 0x400000 );
+        case 0x13 :
+        case 0x17 :   return ( 0x800000 );
+    }
+    return ( FLASH_SIZE );
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   SstCheckMemoryCapacity
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT32
+SstCheckMemoryCapacity  (
+    IN UINT32               dVenDevId
+)
+{
+    switch ( ( dVenDevId & 0x00FF0000 ) >> 16 ) {
+        case 0x8c :   return ( 0x40000 );
+        case 0x8d :   return ( 0x80000 );
+        case 0x8e :   return ( 0x100000 );
+        case 0x01 :   // SST 26VF016
+        case 0x41 :   return ( 0x200000 );
+        case 0x02 :   // SST 26VF032
+        case 0x4a :   return ( 0x400000 );
+        case 0x43 :   // SST 26VF064
+        case 0x4b :   return ( 0x800000 );
+    }
+    return ( FLASH_SIZE );
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   IdentifySTM_25PExx
+//
+// Description: This function identifies the supported SPI flash parts and
+//              returns appropriate flash device API pointer. If flash part is
+//              not supported by this module it will return FALSE.
+//              Supports the following SPI parts
+//              ST Micro M25P80, M25P40
+//
+// Input:   pBlockAddress   Block address of the flash part. Can be used to
+//                              send ID command
+//
+// Output:  **FlashApi      Pointer to hold the returned flash API
+//
+// Return:  TRUE            If flash part is supported, FlashApi contains
+//                              routines to handle the flash requests
+//          FALSE           Flash part is not supported
+//
+// Note:   This routine is part of the global flash init list. Make sure
+//         it is properly linked to the init list "FlashList" (in SDL file)
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+IdentifyStm_25PExx  (
+    IN  volatile UINT8      *pBlockAddress,
+    OUT FLASH_PART          **FlashStruct
+)
+{
+    if ( !CommonSpiReadId( &Stm_25PE, &MfgDevId ) )    return FALSE;
+    switch ( (UINT16)MfgDevId ) {
+        // erase page size = 256 bytes.
+        case STM_25PExx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_256B;
+            Stm_25PE.Erase.Opcode = SPI_M25PExx_COMMAND_PAGE_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "STM/Numonyx 25PE Series", 23 );
+            break;
+        // erase sector size = 4K bytes.
+        case SST_26VFxxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            mExFlashPart.GlobalBlockUnlock = TRUE;
+            mExFlashPart.FlashCapacity = SstCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "SST 26VF Series", 15 );
+            break;
+        case PMC_25LVxxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_PMC25LV_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = \
+                                SpansionCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "PMC 25LV/LQ Series", 18 );
+            break;
+        case AMIC_25Lxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            mExFlashPart.FlashCapacity = \
+                                SpansionCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "AMIC 25L Series", 15 );
+            break;
+        case AMIC_25Lxxx_ID :
+        case AMIC_25LQxxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "AMIC 25L/LQ Series", 18 );
+            break;
+        case EON_25Fxx_ID :
+        case EON_25Qxx_ID :
+        case EON_25QHxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "EON 25F/Q/QH Series", 19 );
+            break;         
+        case STM_25PXxx_ID :
+        case STM_25PFxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy (pFlashDeviceNumber, "STM/Micron/Numonyx 25PF/PX Series", 33);
+            break;
+        case MXIC_25Lxxxx_ID :
+        case MXIC_25Lxx35_ID :
+        case MXIC_25Lxx36_ID :
+        case MXIC_25Uxx35_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "MXIC 25L/U Series", 17 );
+            break;
+        case WINBOND_25Xxx_ID :
+        case WINBOND_25Qxx_ID :
+        case WINBOND_25QxxF_ID :
+        case WINBOND_25QxxW_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "Winbond 25X/Q Series", 20 );
+            break;
+        case GD_25Qxx_ID :
+        case GD_25LQxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "GigaDevice 25Q Series", 21 );
+            break;
+        // erase block size = 64K bytes.
+        case EON_25Pxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_64KB;
+            Stm_25PE.Erase.Opcode = SPI_M25PExx_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "EON 25P Series", 14 );
+            break;         
+        case STM_25Pxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_64KB;
+            Stm_25PE.Erase.Opcode = SPI_M25PExx_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            if (mExFlashPart.FlashCapacity == 0x1000000) {
+                Stm_25PE.SectorSize = SECTOR_SIZE_256KB;  
+            }       
+            MemCpy (pFlashDeviceNumber, "STM/Micron/Numonyx 25P Series", 29);
+            break;
+        case Numonyx_25Qxx_ID :
+        case Numonyx_25QxxA_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy (pFlashDeviceNumber, "Micron/Numonyx 25Q Series", 25);
+            break;
+        case SPANSION_25FLxxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_64KB;
+            mExFlashPart.FlashCapacity = \
+                                    SpansionCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "Spansion 25FL Series", 19 );
+            break;
+        case SPANSION_25FLxxxP_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_64KB;
+            mExFlashPart.FlashCapacity = \
+                                    StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "Spansion 25FL(P) Series", 23 );
+            break;
+        case INTEL_25Fxxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_64KB;
+            mExFlashPart.FlashCapacity = IntelCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "Intel/Numonyx 25F160/320", 24 );
+            break;
+        case FM_25Qxx_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "FIDELIX 25Q Series", 18 );
+            break;
+        case ESMT_25Lxx_ID :
+        case ESMT_25LxxQ_ID :
+            Stm_25PE.SectorSize = SECTOR_SIZE_4KB;
+            Stm_25PE.Erase.Opcode = SPI_MXIC_M25L_COMMAND_ERASE;
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "ESMT 25L QA/PA Series", 21 );
+            break;
+        default :
+            return  FALSE;
+    }
+    *FlashStruct = &mCommonSpiFlash;
+    MemCpy( &mExFlashPart.FlashCommandMenu, &Stm_25PE, sizeof(FLASH_INFO) );
+    mExFlashPart.FlashVenDevId = MfgDevId;
+    gFlashId = MfgDevId;
+    *(UINT32*)(pFlashDeviceNumber + FLASH_PART_STRING_LENGTH - 4) = \
+                                                mExFlashPart.FlashCapacity;
+    (*FlashStruct)->FlashProgramSize = Stm_25PE.PageSize;
+    (*FlashStruct)->FlashSectorSize = Stm_25PE.SectorSize;
+    (*FlashStruct)->FlashPartNumber = pFlashDeviceNumber;
+    // Update the OpCode to OpMenu immediately if need.
+    ReinitializeSpiEnvironment ( &mExFlashPart.FlashCommandMenu );
+    return  TRUE;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   IdentifySst_25VF
+//
+// Description: This function identifies the supported SPI flash parts and
+//              returns appropriate flash device API pointer. If flash part is
+//              not supported by this module it will return FALSE.
+//              Supports the following SPI parts
+//              SST 25VF040B/080B/016B/032B, ESMT
+//
+// Input:   pBlockAddress   Block address of the flash part. Can be used to
+//                              send ID command
+//
+// Output:  **FlashApi      Pointer to hold the returned flash API
+//
+// Return:  TRUE            If flash part is supported, FlashApi contains
+//                              routines to handle the flash requests
+//          FALSE           Flash part is not supported
+//
+// Note:   This routine is part of the global flash init list. Make sure
+//         it is properly linked to the init list "FlashList" (in SDL file)
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+IdentifySst_25VF    (
+    IN  volatile UINT8      *pBlockAddress,
+    OUT FLASH_PART          **FlashStruct
+)
+{
+    if ( !CommonSpiReadId( &Sst_25VF, &MfgDevId ) )    return FALSE;
+    switch ( (UINT16)MfgDevId ) {
+        case SST_25VFxxx_ID :
+            mExFlashPart.FlashCapacity = SstCheckMemoryCapacity( MfgDevId );
+            if (mExFlashPart.FlashCapacity >= 0x800000) Sst_25VF.PageSize = 256;
+#if defined AAI_WORD_PROGRAM && AAI_WORD_PROGRAM == 1
+            else mExFlashPart.AAIWordProgram = TRUE;    
+#endif
+            MemCpy ( pFlashDeviceNumber, "SST 25VF Series", 15 );
+            break;
+        case ESMT_25LxxxT_ID :
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            MemCpy ( pFlashDeviceNumber, "ESMT 25L T Series", 17 );
+            break;
+        case ESMT_25LxxxB_ID :
+            mExFlashPart.FlashCapacity = StmCheckMemoryCapacity( MfgDevId );
+            Sst_25VF.WriteStatusEnable.Opcode = 0;
+            MemCpy ( pFlashDeviceNumber, "ESMT 25L B Series", 17 );
+            break;
+        default :   return  FALSE;
+    }
+    *FlashStruct = &mCommonSpiFlash;
+    MemCpy( &mExFlashPart.FlashCommandMenu, &Sst_25VF, sizeof(FLASH_INFO) );
+    mExFlashPart.FlashVenDevId = MfgDevId;
+    *(UINT32*)(pFlashDeviceNumber + FLASH_PART_STRING_LENGTH - 4) = \
+                                                mExFlashPart.FlashCapacity;
+    gFlashId = MfgDevId;
+    (*FlashStruct)->FlashProgramSize = Sst_25VF.PageSize;
+    (*FlashStruct)->FlashSectorSize = Sst_25VF.SectorSize;
+    (*FlashStruct)->FlashPartNumber = pFlashDeviceNumber;
+    // Update the OpCode to OpMenu immediately if need.
+    ReinitializeSpiEnvironment ( &mExFlashPart.FlashCommandMenu );
+    return  TRUE;
+}
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/Board/Flash/SPI/Template/SPIFlash.c b/Board/Flash/SPI/Template/SPIFlash.c
new file mode 100644
index 0000000..d7677b5
--- /dev/null
+++ b/Board/Flash/SPI/Template/SPIFlash.c
@@ -0,0 +1,1038 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Flash_Combined_2/Core/SPI/Template/SpiFlash.c 4     6/24/09 3:14a Calvinchen $
+//
+// $Revision: 4 $
+//
+// $Date: 6/24/09 3:14a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Flash_Combined_2/Core/SPI/Template/SpiFlash.c $
+// 
+// 4     6/24/09 3:14a Calvinchen
+// (EIP22177) Updated for Aptio Source Enhancement. 
+//
+// 3     4/27/09 3:24a Calvinchen
+// 2.(EIP20459) Added Multiple SPI CSP component support.
+//
+// 2     6/19/08 4:30a Calvinchen
+//
+// 1     3/13/08 6:32a Calvinchen
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//
+// Name:    FlashWrite.c
+//
+// Description: Flash update routines
+//
+//<AMI_FHDR_END>
+//**********************************************************************
+//----------------------------------------------------------------------------
+// Includes
+#include <efi.h>
+#include <AmiDxeLib.h>
+#include "FlashPart.h"
+#include "SpiFlash.h"
+#include "token.h"
+//----------------------------------------------------------------------------
+// Local defines for transaction types
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+// ICH8/9/10 SPI register defines.
+#define     SPI_STS                     0x90    //  SPI Status
+#define     SPI_CTL                     0x91    //  SPI Control
+#define     SPI_ADR                     0x08    //  SPI Address
+#define     SPI_DAT0                    0x10    //  SPI Data 0
+#define     SPI_PREOP                   0x94    //  Prefix Opcode Configuration
+#define     SPI_OPTYPE                  0x96    //  Opcode Type Configuration
+#define     SPI_OPMENU                  0x98    //  Opcode Menu Configuration
+//  SPI default opcode slots
+#define     SPI_OPCODE_WRITE_INDEX      0x0
+#define     SPI_OPCODE_READ_INDEX       0x1
+#define     SPI_OPCODE_ERASE_INDEX      0x2
+#define     SPI_OPCODE_READ_S_INDEX     0x3
+#define     SPI_OPCODE_READ_ID_INDEX    0x4
+#define     SPI_OPCODE_WRITE_S_INDEX    0x5
+#define     SPI_OPCODE_WRITE_E_INDEX    0x6
+#define     SPI_OPCODE_WRITE_S_E_INDEX  0x7
+#define     SPI_PREFIX_WRITE_S_EN       0x1
+#define     SPI_PREFIX_WRITE_EN         0x0
+#define     SPI_MAX_DATA_TRANSFER       0x40
+    ---------------------   PORTING REQUIRED   ---------------------*/
+//----------------------------------------------------------------------------
+// Module level global data
+//============================================================================
+extern UINT16       gFlashId;
+extern FLASH_PART   *FlashAPI;
+//----------------------------------------------------------------------------
+// Function Externs
+//-extern
+//-VOID
+//-SpiChipsetVirtualFixup  (
+//-    IN EFI_RUNTIME_SERVICES *pRS
+//-);
+//----------------------------------------------------------------------------
+// Local prototypes
+VOID
+CommonSpiEraseCommand   (
+    volatile UINT8          *pBlockAddress
+);
+VOID
+CommonSpiProgramCommand (
+    volatile UINT8          *pByteAddress,
+    UINT8                   *Byte,
+    UINT32                  *Length
+);
+VOID
+CommonSpiReadCommand    (
+    volatile UINT8          *pByteAddress,
+    UINT8                   *Byte,
+    UINT32                  *Length
+);
+BOOLEAN
+CommonSpiIsEraseCompleted   (
+    volatile UINT8          *pBlockAddress,
+    BOOLEAN                 *pError,
+    UINTN                   *pStatus
+);
+BOOLEAN
+CommonSpiIsProgramCompleted (
+    volatile UINT8          *pByteAddress,
+    UINT8                   *Byte,
+    UINT32                  Length,
+    BOOLEAN                 *pError,
+    UINTN                   *pStatus
+);
+VOID
+CommonSpiBlockWriteEnable   (
+    volatile UINT8          *pBlockAddress
+);
+VOID
+CommonSpiBlockWriteDisable  (
+    volatile UINT8          *pBlockAddress
+);
+VOID
+CommonSpiDeviceWriteEnable  (
+    VOID
+);
+VOID
+CommonSpiDeviceWriteDisable (
+    VOID
+);
+VOID
+CommonSpiDeviceVirtualFixup (
+    EFI_RUNTIME_SERVICES    *pRS
+);
+//============================================================================
+// Local Variables
+//============================================================================
+FLASH_PART mCommonSpiFlash ={
+    CommonSpiReadCommand,
+    CommonSpiEraseCommand,
+    CommonSpiProgramCommand,
+    CommonSpiIsEraseCompleted,
+    CommonSpiIsProgramCompleted,
+    CommonSpiBlockWriteEnable,
+    CommonSpiBlockWriteDisable,
+    CommonSpiDeviceWriteEnable,
+    CommonSpiDeviceWriteDisable,
+    CommonSpiDeviceVirtualFixup,
+    1,                      // default value, should be changed in Init function
+    SECTOR_SIZE_4KB
+};
+EX_FLASH_PART mExFlashPart = {
+      {{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},{0,0},0,0},
+      FLASH_SIZE,         // flash size, should be changed in Init function
+      0,                  // flash part id, should be changed in Init function
+      0                   // flash part string, should be changed in Init function
+};
+UINT8           gbDeviceVirtual = 0;
+UINT8           gbDeviceWriteEnabled = 0;
+//----------------------------------------------------------------------------
+// Function Definitions
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   IoDelay
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+IoDelay (VOID)
+{
+    UINT8               bTimeout;
+    for ( bTimeout = 0; bTimeout < 33; bTimeout++ ) {
+        IoWrite8( 0xEB, 0x55 );
+        IoWrite8( 0xEB, 0xAA );
+    }
+    return ;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   WaitForSpiCycleDone
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+WaitForSpiCycleDone (VOID)
+{
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT16              wTimeout;
+    UINT8               bCyclyDone;
+
+    for ( wTimeout = 0, bCyclyDone = 0; wTimeout < 0xFFFF; wTimeout++ ) {
+        bCyclyDone = *(volatile UINT8*)( gSPIBASE + SPI_STS );
+        if ( bCyclyDone & BIT02 ) break;
+    }
+    // write BIT2 to clear CycleDone status
+    *(volatile UINT8*)( gSPIBASE + SPI_STS ) = BIT02;
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonSpiReadStatus
+//
+// Description:
+//
+// Input:       None.
+//
+// Output:      Status Register which is read from SPI flash.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8
+CommonSpiReadStatus (VOID)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT16  wSpiCmd;
+    // Opcode menu slot 3 is configured as "Read Status Register"
+    wSpiCmd = SPI_OPCODE_READ_S_INDEX << 4;
+    // indicate that data phase is required
+    wSpiCmd += (1 << 14);
+    // Set BIT1 (Go)
+    *(volatile UINT16*)( gSPIBASE + SPI_CTL ) =  wSpiCmd + BIT01;
+    // wait for spi cycle completed.
+    WaitForSpiCycleDone();
+    // return status register.
+    return ( *(volatile UINT8*)( gSPIBASE + SPI_DAT0 ) );
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+
+    return ( (UINT8)EFI_NOT_READY );    // For Template compiling only.
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   WaitForWriteOperationCompleted
+//
+// Description:
+//
+// Input:       None.
+//
+// Output:      None.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+WaitForWriteOperationCompleted (VOID)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT16              wWaitStsRetry;
+    UINT8               bStatus;
+
+    for( wWaitStsRetry = 0; wWaitStsRetry < 0xFFFF; wWaitStsRetry++ ) {
+        // read flash status register.
+        bStatus = CommonSpiReadStatus();
+        // Is operation busy ?
+        if( !( bStatus & 0x1 ) ) break;
+    }
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonSpiWriteStatus
+//
+// Description: Routine for Write SPI Status Register.
+//
+// Input:       None.
+//
+// Output:      Status Register which is read from SPI flash.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiWriteStatus    (
+    IN UINT8                bWriteData,
+    IN UINT8                bOpcodeIndex,
+    IN UINT8                bIsDataPhase,
+    IN UINT8                bPrefixOp,
+    IN UINT32               dSectorAddress
+)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT16  wSpiCmd;
+
+    *(volatile UINT8*)( gSPIBASE + SPI_DAT0 ) = bWriteData;
+    *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = dSectorAddress;
+    // Opcode menu slot 3 is configured as "Read Status Register"
+    wSpiCmd = bOpcodeIndex << 4;
+    // indicate that data phase is required
+    wSpiCmd += ( bIsDataPhase << 14 );
+    // BIT3(Preop 1)
+    wSpiCmd += ( bPrefixOp << 3 );
+    // Set BIT1 (Go), BIT2(Atomic w/ Prefix),
+    *(volatile UINT16*)( gSPIBASE + SPI_CTL ) =  wSpiCmd + BIT01 + BIT02;
+    // wait for spi cycle completed.
+    WaitForSpiCycleDone();
+    // wait for SPI flash operation completed.
+    WaitForWriteOperationCompleted();
+    // return status register.
+    return ;
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonSpiReadByte
+//
+// Description:
+//
+// Input:       dByteAddress    Address that need to be read.
+//
+// Output:      BYTE            Value which is read from SPI flash.
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8
+CommonSpiReadByte   (
+    IN UINT32               dByteAddress
+)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+    UINT16  wSpiCmd;
+
+    // update the
+    *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = dByteAddress;
+    // Opcode menu slot 1 is configured as "Read Flash"
+    wSpiCmd = ( SPI_OPCODE_READ_INDEX << 4 ) + BIT01;
+    // indicate that data phase is required
+    wSpiCmd += (1 << 14);
+    *(volatile UINT16*)( gSPIBASE + SPI_CTL ) = wSpiCmd;
+    // wait for spi cycle completed.
+    WaitForSpiCycleDone();
+    // return data.
+    return( *(volatile UINT8*)( gSPIBASE + SPI_DAT0 ) );
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+    return ( (UINT8)EFI_NOT_READY );    // For Template compiling only.
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonConvertSpiAddress
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT32
+CommonConvertSpiAddress   (
+    IN volatile UINT8       *pAddress
+)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    if ( gbDeviceVirtual ) {
+        // pAddress - offset from Flash Device Base.
+        pAddress -= FlashDeviceBase;
+        // pAddress - 32bit memory mapping address.
+        pAddress += (0xFFFFFFFF - FLASH_SIZE) + 1;
+    }
+    ---------------------   PORTING REQUIRED   ---------------------*/
+
+    return ((UINT32)pAddress);
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InitializeSpiEnvironment
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+InitializeSpiEnvironment (
+    IN FLASH_INFO       *FlashInfo
+)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT32              dIchSpiFDOD;
+
+    //Program first DWORD of opcode commands
+    *((volatile UINT32*)( gSPIBASE+R_RCRB_SPI_OPMENU+0 )) = (UINT32)
+        // Write Byte
+        ( (FlashInfo->Write.Opcode << (SPI_OPCODE_WRITE_INDEX * 8))
+        // Read Data
+        | (FlashInfo->Read.Opcode << (SPI_OPCODE_READ_INDEX * 8))
+        // Erase 64k Sector
+        | (FlashInfo->Erase.Opcode << (SPI_OPCODE_ERASE_INDEX * 8))
+        // Read Device Status Reg
+        | (FlashInfo->ReadStatus.Opcode << (SPI_OPCODE_READ_S_INDEX * 8)) );
+
+    //Program second DWORD of Opcode commands
+    *((volatile UINT32*)( gSPIBASE+R_RCRB_SPI_OPMENU+4 )) = (UINT32)
+        // Read device ID
+        ( (FlashInfo->ReadId.Opcode << ((SPI_OPCODE_READ_ID_INDEX - 4) * 8))
+        // Write Status Register
+        | (FlashInfo->WriteStatus.Opcode << ((SPI_OPCODE_WRITE_S_INDEX - 4) * 8))
+        // Write Status Enable Register
+        | (FlashInfo->WriteStatusEnable.Opcode << ((SPI_OPCODE_WRITE_E_INDEX - 4) * 8)));
+
+    //Program opcode types
+    *((volatile UINT16*)( gSPIBASE+R_RCRB_SPI_OPTYPE )) = (UINT16)
+        // write with address.
+        ( FlashInfo->Write.OpcodeType << (SPI_OPCODE_WRITE_INDEX*2)
+        // read with address.
+        | FlashInfo->Read.OpcodeType << (SPI_OPCODE_READ_INDEX*2)
+        // write with address.
+        | FlashInfo->Erase.OpcodeType << (SPI_OPCODE_ERASE_INDEX*2)
+        // read w/o no adress.
+        | FlashInfo->ReadStatus.OpcodeType << (SPI_OPCODE_READ_S_INDEX*2)
+        // read with address.
+        | FlashInfo->ReadId.OpcodeType << (SPI_OPCODE_READ_ID_INDEX*2)
+        // write w/o address.
+        | FlashInfo->WriteStatus.OpcodeType << (SPI_OPCODE_WRITE_S_INDEX*2)
+        // write w/o address.
+        | FlashInfo->WriteStatusEnable.OpcodeType << (SPI_OPCODE_WRITE_E_INDEX*2) );
+
+    //set up the prefix opcodes for commands
+    *((volatile UINT16*)( gSPIBASE+R_RCRB_SPI_PREOP )) = (UINT16)
+        ( ( FlashInfo->WriteStatusEnable.Opcode << 8 )
+        | ( FlashInfo->WriteEnable.Opcode ) );
+
+    // Here checks the BIOS region of Flash Descriptor Table.
+    if ( mExFlashPart.FlashCommandMenu != NULL ) {
+        if ( !gBiosRegionBase ) {
+            *(volatile UINT32*)( gSPIBASE + ICH_SPI_FDOC ) = 0;
+            dIchSpiFDOD = *(volatile UINT32*)( gSPIBASE + ICH_SPI_FDOD );
+            if ( dIchSpiFDOD == 0x0FF0A55A )
+            {
+                *(volatile UINT32 *)( gSPIBASE + ICH_SPI_FDOC ) = (BIT13+BIT02);
+                do {
+                    dIchSpiFDOD = *(volatile UINT32*)( gSPIBASE+ICH_SPI_FDOD );
+                } while( dIchSpiFDOD == 0x0FF0A55A );
+                gBiosRegionBase = ( ( (dIchSpiFDOD >> 16) + 1 ) << 12 );
+            }
+            else
+                gBiosRegionBase = mExFlashPart.FlashCapacity;
+        }
+    }
+    return ;
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   ReinitializeSpiEnvironment
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+ReinitializeSpiEnvironment (
+    IN FLASH_INFO           *FlashInfo
+)
+{
+    return ;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CommonSpiReadId
+//
+// Description:
+//
+// Input:
+//
+// Output:
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+CommonSpiReadId (
+    IN FLASH_INFO           *FlashInfo,
+    IN UINT32               *dFlashId
+)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT16              wSpiCmd = 0xFFFF;
+
+    InitializeSpiEnvironment( FlashInfo );
+    // Set SPI read-address = 0
+    *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = 0;
+    // set opcode for "Read ID"
+    wSpiCmd = SPI_OPCODE_READ_ID_INDEX << 4;
+    // set transaction = 3 bytes
+    wSpiCmd += ( ( 3 - 1 ) << 8 );
+    // indicate that data phase is required
+    wSpiCmd += ( 1 << 14 );
+    // Go (BIT1)
+    *(volatile UINT16*)( gSPIBASE + SPI_CTL ) =  wSpiCmd + BIT01;
+    WaitForSpiCycleDone();
+    IoDelay();
+    *dFlashId = *(volatile UINT32*)( gSPIBASE + SPI_DAT0 ) & 0x00FFFFFF;
+    TRACE ((-1, " FLASH ID  - %08X\n", *dFlashId));
+    return  TRUE;
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+
+    return ( (UINT8)EFI_NOT_READY );    // For Template compiling only.
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiEraseCommand
+//
+// Description: This API function erases a block in the flash. Flash model
+//              specific code will branch out from this routine
+//
+// Input:       pBlockAddress   Block that need to be erased
+//
+// Output:      Nothing
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiEraseCommand   (
+    IN volatile UINT8*      pBlockAddress
+)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    volatile UINT32     dSectorAddr;
+    UINT32              dNByte;
+    UINT16              wEraseRetry, wNumSectors, wSector;
+    UINT16              wSpiCmd;
+
+    // These parts only erase in 64K sectors
+    InitializeSpiEnvironment( mExFlashPart.FlashCommandMenu );
+    wNumSectors = ( FlashBlockSize / FlashAPI->FlashSectorSize );
+    for ( wSector = 0; wSector < wNumSectors ; wSector++ ) {
+        dSectorAddr = (UINT32)
+                        ( pBlockAddress + wSector * FlashAPI->FlashSectorSize );
+        for ( dNByte = 0; dNByte < FlashAPI->FlashSectorSize; dNByte++ ) {
+            if ( *(volatile UINT8*)( dSectorAddr + dNByte ) != 0xFF )  break;
+        }
+        if  ( dNByte == FlashAPI->FlashSectorSize )   break;
+        for ( wEraseRetry = 0; wEraseRetry < FLASH_RETRIES; wEraseRetry++ ) {
+            dSectorAddr += gBiosRegionBase;
+            *(volatile UINT32*)( gSPIBASE + SPI_ADR ) = dSectorAddr;
+            // opcode index 2 is programmed for erase command.
+            // Set BIT1 (Go), BIT2(Atomic w/ Prefix)
+            wSpiCmd = ( SPI_OPCODE_ERASE_INDEX << 4) + BIT01 + BIT02;
+            *(volatile UINT16*)( gSPIBASE + SPI_CTL ) = wSpiCmd;
+            // wait for chipset SPI cycle completed.
+            WaitForSpiCycleDone();
+            // wait for SPI flash operation completed.
+            WaitForWriteOperationCompleted();
+            // write operation appeared to succeed, now read back byte and compare.
+            if ( CommonSpiReadByte( dSectorAddr ) == 0xFF )   break;
+        }
+    }
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiProgramCommand
+//
+// Description: This function programs a byte data to the specified location
+//
+// Input:   *pByteAddress   Location where the data to be written
+//          Bytes - data to be written.
+//          Length - number of bytes to write
+//
+// Output:  Length - number of bytes that were not written
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiProgramCommand (
+    IN volatile UINT8*      pByteAddress,
+    IN UINT8                *Byte,
+    IN OUT UINT32           *Length
+)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT8               bFlashRetry = 0, bProgBytes = 0, bNumBytes = 0;
+    UINT16              wSpiCmd = 0, wRetry = 0, wMaxNumBytes = 0;
+
+    InitializeSpiEnvironment( mExFlashPart.FlashCommandMenu );
+    bProgBytes = mCommonSpiFlash.FlashProgramSize;
+    if ( mCommonSpiFlash.FlashProgramSize != 1 ) {
+        // Limit the max transfer to the number of bytes the chipset can
+        // transfer per cycle
+        if ( *Length >= SPI_MAX_DATA_TRANSFER )
+            bProgBytes = SPI_MAX_DATA_TRANSFER;
+        else
+            bProgBytes = *Length;
+        // this is currently for the WINBOND parts only
+        // mask off lowest 8 bits of address so that we can determine how
+        // many bytes we can write before we hit the end of a page
+        wMaxNumBytes = 0x100 - ((UINT8)pByteAddress & 0xFF);
+        if ( (UINT32)pByteAddress & 0x1 )   bProgBytes = 1;
+        else if ( (UINT16)bProgBytes > wMaxNumBytes )
+                bProgBytes = (UINT8)wMaxNumBytes;
+    }
+    for ( bFlashRetry = 0; bFlashRetry < FLASH_RETRIES; bFlashRetry++ ) {
+        // check if do the data need to be programmed ?
+        for ( bNumBytes = 0; bNumBytes < bProgBytes; bNumBytes++ ) {
+            if ( *( Byte + bNumBytes ) != 0xFF )    break;
+        }
+
+        // The data is empty and don't need to be programmed.
+        if ( bNumBytes == bProgBytes )  break;
+        // update data to chipset SPI data transfer registers.
+        for ( bNumBytes = 0; bNumBytes < bProgBytes; bNumBytes++ ) {
+            for ( wRetry = 0; wRetry < 0x400; wRetry ++ ) {
+                *(volatile UINT8*)( gSPIBASE+SPI_DAT0+bNumBytes ) =
+                                                            *( Byte+bNumBytes );
+                // verified for checking the data is correct.
+                if ( *(Byte+bNumBytes) == *(volatile UINT8*)
+                                            ( gSPIBASE+SPI_DAT0+bNumBytes ) )
+                    break;
+            }
+        }
+        *(volatile UINT32*)( gSPIBASE + SPI_ADR ) =
+                                    (UINT32)( pByteAddress + gBiosRegionBase );
+        // BIT14 - indicate that it's data cycle.
+        wSpiCmd = ( 1 << 14 );
+        // BIT[8..13] - update the number of bytes to be written.
+        wSpiCmd += ( bProgBytes - 1 ) << 8;
+        // opcode index 0 is programmed for program command.
+        // Set BIT1 (Go), BIT2(Atomic w/ Prefix)
+        wSpiCmd += ( SPI_OPCODE_WRITE_INDEX << 4) + BIT01 + BIT02;
+        *(volatile UINT16*)( gSPIBASE + SPI_CTL ) = wSpiCmd;
+        // wait for chipset SPI cycle completed.
+        WaitForSpiCycleDone();
+        // wait for chipset SPI flash operation completed.
+        WaitForWriteOperationCompleted();
+        // write operation appeared to succeed, now read back byte and compare
+        // set control for 1-byte data read, no prefix
+        for ( bNumBytes = 0; bNumBytes < bProgBytes; bNumBytes++ ) {
+            if (*(Byte + bNumBytes) != CommonSpiReadByte (
+                        (UINT32)( pByteAddress + bNumBytes + gBiosRegionBase )))
+                break;
+        }
+        if ( bNumBytes == bProgBytes )  break;
+    }
+    // Don't forget to return the number of bytes not written
+    *Length = *Length - (UINT32)bProgBytes;
+    return;
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+
+}
+
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiReadCommand
+//
+// Description: This function programs a byte data to the specified location
+//
+// Input:   *pByteAddress   Location where the data to be written
+//          Bytes - data to be written.
+//          Length - number of bytes to write
+//
+// Output:  Length - number of bytes that were not written
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiReadCommand   (
+    IN  volatile UINT8      *pByteAddress,
+    OUT UINT8               *Byte,
+    IN  OUT UINT32          *Length
+)
+{
+    UINT32              dReadAddress = 0, dNumBytes = 0;
+
+    InitializeSpiEnvironment( &mExFlashPart.FlashCommandMenu );
+    dReadAddress = CommonConvertSpiAddress ( pByteAddress );
+    for ( dNumBytes = 0; dNumBytes < *Length ; dNumBytes++ )
+        *( Byte + dNumBytes ) = CommonSpiReadByte( dReadAddress + dNumBytes );
+    *Length = 0;
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiIsEraseCompleted
+//
+// Description: This function verifies whether the block erase
+//      command is completed and returns the status of the command
+//
+// Input:   *pBlockAddress  Location of the block erase
+//
+// Output:  *pError         True on error and false on success
+//          *Status         Error status code (0 - Success)
+//
+// Return:  TRUE        If operation completed successfully
+//                          *pError = FALSE, *pStatus = 0
+//          FALSE       If operation failed
+//                          *pError = TRUE, *pStatus = error status
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+CommonSpiIsEraseCompleted   (
+    IN  volatile UINT8          *pBlockAddress,
+    OUT BOOLEAN                 *pError,
+    OUT UINTN                   *pStatus
+)
+{
+    UINT32                      dNumBytes;
+
+    for ( dNumBytes = 0; dNumBytes < FlashBlockSize; dNumBytes++ ) {
+        if ( *(volatile UINT8*)( pBlockAddress + dNumBytes ) != 0xFF ) {
+            *pStatus = EFI_NOT_READY;
+            *pError = TRUE;
+            break;
+        }
+    }
+    *pError = FALSE;
+    *pStatus = EFI_SUCCESS;
+    return TRUE;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiIsProgramCompleted
+//
+// Description: This function verifies whether the program (page or byte)
+//      command is completed and returns the status of the command
+//
+// Input:   *pByteAddress   Location of the program command
+//          Byte            Last data byte written
+//
+// Output:  *pError         True on error and false on success
+//          *Status         Error status code (0 - Success)
+//
+// Return:  TRUE        If operation completed successfully
+//                          *pError = FALSE, *pStatus = 0
+//          FALSE       If operation failed
+//                          *pError = TRUE, *pStatus = error status
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN
+CommonSpiIsProgramCompleted (
+    IN  volatile UINT8          *pByteAddress,
+    IN  UINT8                   *Byte,
+    IN  UINT32                  Length,
+    OUT BOOLEAN                 *pError,
+    OUT UINTN                   *pStatus
+)
+{
+    UINT32                      dNumBytes;
+    UINT8                       bByte;
+
+    for ( dNumBytes = 0; dNumBytes < Length; dNumBytes++ ) {
+        bByte = * ( Byte + dNumBytes );
+        if ( bByte != *(volatile UINT8*)( pByteAddress + dNumBytes ) ) {
+            *pStatus = EFI_NOT_READY;
+            *pError = TRUE;
+            break;
+        }
+    }
+    *pError = FALSE;
+    *pStatus = EFI_SUCCESS;
+    return TRUE;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiBlockWriteEnable
+//
+// Description: This function contains any flash specific code need to
+//              enable a particular flash block write
+//
+// Input:   *pBlockAddress - Address within the block to write enable
+//
+// Output:      None
+//
+// Return:      None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiBlockWriteEnable   (
+    IN volatile UINT8       *pBlockAddress
+)
+{
+
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT8                   bStatusReg = 0, bPrefixOp, bDataPhase = 1;
+    UINT16                  wNumSector = 1;
+    UINT32                  dSectorAddr = 0;
+
+    bStatusReg = CommonSpiReadStatus();
+    switch ( (UINT8)mExFlashPart.FlashVenDevId ) {
+        // if SST flash, prefix 1 w/o address
+        case 0xBF :
+            bStatusReg &= 0x1C;
+            bPrefixOp = SPI_PREFIX_WRITE_S_EN;
+            break;
+        // if ATMEL flash, prefix 0 w/ address
+        case 0x1F :
+            bStatusReg &= 0xC;
+            dSectorAddr = ~(UINT32)mExFlashPart.FlashCapacity + 1;
+            wNumSector = ( mExFlashPart.FlashCapacity/FlashAPI->FlashSectorSize );
+            bPrefixOp = SPI_PREFIX_WRITE_EN;
+            bDataPhase = 0;
+            break;
+        default :
+        // default flash, prefix 0 w/o address
+            bStatusReg &= 0x1C;
+            bPrefixOp = SPI_PREFIX_WRITE_EN;
+    }
+    if ( bStatusReg ) {
+        for ( ; wNumSector > 0; wNumSector-- ) {
+            CommonSpiWriteStatus (  0,
+                                    SPI_OPCODE_WRITE_S_INDEX,
+                                    bDataPhase,
+                                    bPrefixOp,
+                                    dSectorAddr );
+            dSectorAddr += FlashAPI->FlashSectorSize;
+        }
+    }
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiBlockWriteDisable
+//
+// Description: This function contains any flash specific code need to
+//              disable a particular flash block write
+//
+// Input:   *pBlockAddress - Address within the block to write disable
+//
+// Output:  None
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiBlockWriteDisable  (
+    IN volatile UINT8           *pBlockAddress
+)
+{
+#if BLOCK_PROTECT_ENABLE
+/*  ---------------------   PORTING REQUIRED   ---------------------
+
+    UINT8                   bStatusReg = 0, bPrefixOp, bDataPhase = 1;
+    UINT8                   bOpmenuIndex;
+    UINT16                  wNumSector = 1;
+    UINT32                  dSectorAddr = 0;
+
+    bStatusReg = CommonSpiReadStatus();
+    bOpmenuIndex = SPI_OPCODE_WRITE_S_INDEX;
+    switch ( (UINT8)mExFlashPart.FlashVenDevId ) {
+        // if SST flash, prefix 1 w/o address
+        case 0xBF :
+            bStatusReg &= 0x1C;
+            bPrefixOp = SPI_PREFIX_WRITE_S_EN;
+            break;
+        // if ATMEL flash, prefix 0 w/ address
+        case 0x1F :
+            bStatusReg &= 0xC;
+            dSectorAddr = ~(UINT32)mExFlashPart.FlashCapacity + 1;
+            wNumSector = ( mExFlashPart.FlashCapacity/FlashAPI->FlashSectorSize );
+            bPrefixOp = SPI_PREFIX_WRITE_EN;
+            bOpmenuIndex = SPI_OPCODE_WRITE_E_INDEX;
+            bDataPhase = 0;
+            break;
+        default :
+        // default flash, prefix 0 w/o address
+            bStatusReg &= 0x1C;
+            bPrefixOp = SPI_PREFIX_WRITE_EN;
+    }
+    if ( !bStatusReg ) {
+        for ( ; wNumSector > 0; wNumSector-- ) {
+            CommonSpiWriteStatus (  0x1C,
+                                    bOpmenuIndex,
+                                    bDataPhase,
+                                    bPrefixOp,
+                                    dSectorAddr );
+            dSectorAddr += FlashAPI->FlashSectorSize;
+        }
+    }
+
+    ---------------------   PORTING REQUIRED   ---------------------*/
+#endif
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiDeviceWriteEnable
+//
+// Description: This function contains any flash specific code need to
+//              enable flash write
+//
+// Input:   None
+//
+// Output:  None
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiDeviceWriteEnable (VOID)
+{
+    // check is DeviceWrite enabled, if yes, don't enable it again, else, enable it.
+    if ( !gbDeviceWriteEnabled ) {
+        gbDeviceWriteEnabled = 1;
+    }
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiDeviceWriteDisable
+//
+// Description: This function contains any flash specific code need to
+//              disable flash write
+//
+// Input:       None
+//
+// Output:      None
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CommonSpiDeviceWriteDisable (VOID)
+{
+    // check is DeviceWrite enabled, if yes, disable it, 
+    // if no, don't disable it.
+    if ( gbDeviceWriteEnabled ) {
+        gbDeviceWriteEnabled = 0;
+    }
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CommonSpiDeviceVirtualFixup
+//
+// Description: This function will be invoked by the core to convert
+//              runtime pointers to virtual address
+//
+// Input:       *pRS    Pointer to runtime services
+//
+// Output:      None
+//
+// Return:  None
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+static
+VOID
+CommonSpiDeviceVirtualFixup (
+    IN EFI_RUNTIME_SERVICES  *pRS
+)
+{
+
+//  // Following is an example code for virtual address conversion
+//  pRS->ConvertPointer(0, (VOID**)&FlashDeviceBase);
+
+//-    SpiChipsetVirtualFixup(pRS);
+    gbDeviceVirtual = 1;
+
+    return;
+}
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2009, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
\ No newline at end of file
diff --git a/Board/Flash/SPI/Template/SpiCspSrc.cif b/Board/Flash/SPI/Template/SpiCspSrc.cif
new file mode 100644
index 0000000..e50f0c3
--- /dev/null
+++ b/Board/Flash/SPI/Template/SpiCspSrc.cif
@@ -0,0 +1,8 @@
+<component>
+	name = "CSP : DUMMY SPI - Do Not Delete"
+	category = ModulePart
+	LocalRoot = "Board\Flash\SPI\Template"
+	RefName = "DUMMY_SPI_CSP_SOURCE"
+[files]
+"SPIFlash.c"
+<endComponent>