diff options
| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /Board/SB | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'Board/SB')
| -rw-r--r-- | Board/SB/GetSetupData.c | 974 | ||||
| -rw-r--r-- | Board/SB/HDAVBTBL.h | 77 | ||||
| -rw-r--r-- | Board/SB/SB.H | 998 | ||||
| -rw-r--r-- | Board/SB/SB.mak | 366 | ||||
| -rw-r--r-- | Board/SB/SB.sdl | 5432 | ||||
| -rw-r--r-- | Board/SB/SBDXE.dxs | 76 | ||||
| -rw-r--r-- | Board/SB/SBDXEBoard.c | 152 | ||||
| -rw-r--r-- | Board/SB/SBPEI.dxs | 65 | ||||
| -rw-r--r-- | Board/SB/SBPEIBoard.c | 343 | ||||
| -rw-r--r-- | Board/SB/SBPeiDebugger.c | 1309 | ||||
| -rw-r--r-- | Board/SB/SBRun.dxs | 55 | ||||
| -rw-r--r-- | Board/SB/SBSECInit.asm | 389 | ||||
| -rw-r--r-- | Board/SB/SBSetup/SB.sd | 7876 | ||||
| -rw-r--r-- | Board/SB/SBSetup/SB.uni | bin | 0 -> 144652 bytes | |||
| -rw-r--r-- | Board/SB/SBSetup/SBSetup.c | 787 | ||||
| -rw-r--r-- | Board/SB/SBSetup/SBSetup.cif | 12 | ||||
| -rw-r--r-- | Board/SB/SBSetup/SBSetup.mak | 68 | ||||
| -rw-r--r-- | Board/SB/SBSetup/SBSetup.sdl | 98 | ||||
| -rw-r--r-- | Board/SB/Sb.ssp | 79 | ||||
| -rw-r--r-- | Board/SB/SbSetupData.h | 503 | ||||
| -rw-r--r-- | Board/SB/sbBOARD.CIF | 23 |
21 files changed, 19682 insertions, 0 deletions
diff --git a/Board/SB/GetSetupData.c b/Board/SB/GetSetupData.c new file mode 100644 index 0000000..9fd1274 --- /dev/null +++ b/Board/SB/GetSetupData.c @@ -0,0 +1,974 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/GetSetupData.c 28 3/13/14 11:06a Barretlin $ +// +// $Revision: 28 $ +// +// $Date: 3/13/14 11:06a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/GetSetupData.c $ +// +// 28 3/13/14 11:06a Barretlin +// [TAG] EIP153695 +// [Category] Improvement +// [Description] USB Per port control is not reasonable when +// OEM_USBPREPORT_DISABLE_SUPPORT token is Enabled and USB devices are +// behind hubs +// [Files] Sb.sdl Sb.sd Sb.uni GetSetupData.c SbDxe.c PchUsbCommon.c +// PchRegsUsb.h +// +// 27 8/01/13 4:32a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add PCIE LTR setup items. +// [Files] SB.sd, SB.uni, SBDxe.c, GetSetupData.c, SbSetupData.h +// +// 26 7/09/13 5:16a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create "PCH Cross Throttling" setup item.(Only ULT +// support) +// [Files] SBDxe.c, SB.sd, SB.uni, GetSetupData.c, SB.sd +// +// 25 5/13/13 8:58a Scottyang +// [TAG] EIP123496 +// [Category] Improvement +// [Description] Update PCH RC 1.5.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.* , SBDxe.C, SBPEI.c, +// SB.sd, SB.uni, SbSetupData.h, GetSetupData.c +// +// 24 3/15/13 3:40a Scottyang +// [TAG] EIP118121 +// [Category] Improvement +// [Description] Update PCH RC 1.3.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupData.h +// +// 23 3/04/13 10:08p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add Solid State Drive item to port 6. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd +// +// 22 2/19/13 9:59p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add setup buffer for NFC. +// [Files] GetSetupData.c +// +// 21 2/09/13 12:13a Scottyang +// [TAG] EIP114922 +// [Category] Improvement +// [Description] Update PCH RC 1.1.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupDara.h +// +// 20 1/31/13 10:56a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add Serial IO GNVS setup option. +// [Files] SBDxe.c, SB.sd, SB.uni, SbSetupData.h, GetSetupData.c +// +// 19 1/10/13 4:49a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create DTIO value and DM value option +// [Files] SB.sd, SB.uni, SbSetupData.h, GetSetupData.c, SBDxe.c +// +// 18 1/03/13 4:56a Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Build error when set IDE mode as default. +// [RootCause] The ULT did not support IDE mode that made the value +// redefine. +// [Solution] Separate Sata inter face for 2 Chip and ULT. +// [Files] SB.sd, GetSetupData.c, SbSetupData.h +// +// 17 12/24/12 5:42a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add option for XHCI Idel L1 workaroung. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c, +// SBPEI.c +// +// 16 12/22/12 2:05a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add PCIE "L1 Substates"setup option. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c +// +// 15 12/18/12 6:03a Scottyang +// [TAG] EIP109697 +// [Category] Improvement +// [Description] Update PCH RC 0.8.1 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// +// 14 12/17/12 6:41a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add setup menu for LPSS and ECTG. +// [Files] GetSetupData.c +// SbSetupData.h +// SB.sd +// SB.uni +// SBDxe.c +// +// 13 12/13/12 10:34a Scottyang +// [TAG] EIP106687 +// [Category] Improvement +// [Description] Add option for delay to detect PCIE card. +// [Files] SBPEI.c, SB.sd, SB.uni, GetSetupData.c, SbSetupData.h, +// PciBus.c +// +// 12 11/20/12 9:45a Scottyang +// [TAG] EIP107014 +// [Category] Improvement +// [Description] Update RC 0.8.0 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SbSetupData.c, GetSetupDate.c +// +// 11 11/08/12 8:33a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add device item that connect LPSS. +// [Files] GetSetupData.c, SbSetupData.h, SBDxe.c, SB.sd, SB.uni +// +// 10 11/07/12 6:09a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove HDMI item. +// [Files] SB.sd, SB.uni, GetSetupData.c, SbSetupData.h +// +// 9 10/23/12 8:27a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create Device Sleep at setup menu +// [Files] SB.sd, SB.uni, SBDxe.c, GetSetupData.c, SbSetupData.h +// +// 8 10/16/12 2:15a Scottyang +// [TAG] EIP103924 +// [Category] Improvement +// [Description] Update RC 0.7.1 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// +// 7 9/26/12 3:46a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement ULT platform LPSS and ADSP setup option. +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SB.sdl +// +// 6 9/12/12 5:08a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Modify for Thunderbolt support. +// [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +// PciHotPlug.c +// +// 5 8/13/12 10:12a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove useless Dppm items. +// [Files] GetSetupData.c, SB.sd, SbSetupData.h, SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Implement USB Precondition option for policy +// "UsbPrecondition". +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SBPEI.c +// +// 4 7/27/12 6:04a Victortu +// Update setup items and policies. +// +// 3 7/02/12 10:21a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Change default setup of USB 3.0 mode and Pre-Boot +// Support. +// [Files] GetSetupData.c, SB.sd +// +// 2 4/25/12 9:07a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Relayout PCH USB Setup. +// [Files] GetSetupData.c; SB.sd; SB.uni; SbSetupData.h; SBDxe.c +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: GetSetupData.c +// +// Description: Custom South Bridge setup data behavior implementation +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <AmiCspLib.h> +#include <Setup.h> +#include <Ppi\ReadOnlyVariable2.h> + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +typedef VOID (SB_OEM_SETUP_CALLBACK) ( + IN VOID *Services, + IN OUT SB_SETUP_DATA *SbSetupData, + IN SETUP_DATA *SetupData, + IN BOOLEAN Pei +); + +// Function Prototype(s) +VOID SbSetupCallbacks ( + IN VOID *Services, + IN OUT SB_SETUP_DATA *SbSetupData, + IN SETUP_DATA *SetupData, + IN BOOLEAN Pei +); + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- + +// GUID Definition(s) + +static EFI_GUID gSetupGuid = SETUP_GUID; +static EFI_GUID gPeiReadOnlyVarPpiGuid = EFI_PEI_READ_ONLY_VARIABLE2_PPI_GUID; + +// Protocol/Ppi Definition(s) + +// External Declaration(s) + +extern SB_OEM_SETUP_CALLBACK SB_OEM_SETUP_CALLBACK_LIST EndOfList; + +// Variable Declaration(s) + +SB_OEM_SETUP_CALLBACK* SbOemSetupCallbackList[] = \ + {SB_OEM_SETUP_CALLBACK_LIST NULL}; +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SbOemSetupCallbacks +// +// Description: This function calls registered callbacks for OEM/custom setup. +// +// Input: *Services - Pointer to PeiServices or RuntimeServices +// structure +// *SbSetupData - Pointer to custom setup data to return +// *SetupData - Pointer to system setup data. +// Pei - Pei flag. If TRUE we are in PEI phase +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SbOemSetupCallbacks ( + IN VOID *Services, + IN OUT SB_SETUP_DATA *SbSetupData, + IN SETUP_DATA *SetupData, + IN BOOLEAN Pei ) +{ + UINTN i; + + for (i = 0; SbOemSetupCallbackList[i] != NULL; i++) + SbOemSetupCallbackList[i]( Services, SbSetupData, SetupData, Pei); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetSbSetupData +// +// Description: This function returns custom setup data from system SetupData +// variable +// +// Input: *Services - Pointer to PeiServices or RuntimeServices +// structure +// *SbSetupData - Pointer to custom setup data to return +// Pei - Pei flag. If TRUE we are in PEI phase +// +// Output: None +// +// Notes: PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID GetSbSetupData ( + IN VOID *Services, + IN OUT SB_SETUP_DATA *SbSetupData, + IN BOOLEAN Pei ) +{ + EFI_STATUS Status; + SETUP_DATA SetupData; + EFI_PEI_SERVICES **PeiServices; + EFI_RUNTIME_SERVICES *RunServices; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariable = NULL; + UINTN VariableSize = sizeof( SETUP_DATA ); + UINT8 i; + UINT32 Buffer32; + PCH_SERIES PchSeries = GetPchSeries(); + + // Porting Start + // Update SB_SETUP_DATA according to the default values. + SbSetupData->PchLan = 1; + SbSetupData->PchWakeOnLan = 1; + SbSetupData->SlpLanLow = 1; + SbSetupData->BoardCapability = 0; + SbSetupData->DeepSxBattMode = 0; + SbSetupData->DeepSxMode = 0; + SbSetupData->Gp27Wake = 1; + SbSetupData->PcieWake = 0; + SbSetupData->PchAzalia = 2; + SbSetupData->AzaliaDs = 0; + SbSetupData->AzaliaPme = 0; + SbSetupData->PchPciClockRun = 1; + SbSetupData->SirqMode = 0; + SbSetupData->PchEnableCrid = 1; + SbSetupData->PchDisplay = 1; + SbSetupData->Hpet = 1; + SbSetupData->SlpS4AssW = 3; + SbSetupData->LastState = 2; + SbSetupData->Port80Route = RESERVED_PAGE_ROUTE; + SbSetupData->AspmMode = 0; + SbSetupData->SmiLock = 0; + SbSetupData->BiosLock = 0; + SbSetupData->GpioLock = 0; + SbSetupData->BiosInterfaceLock = 0; + SbSetupData->RtcLock = 1; + SbSetupData->PchDmiAspm = 1; + SbSetupData->PchDmiExtSync = 0; + SbSetupData->PcieClockGating = 1; + SbSetupData->RootPortFunctionSwapping = 1; + SbSetupData->PcieUsbWa = 0; + SbSetupData->PchUsbPerPortCtl = 0; + +#if EHCI_CON_DISCON_WAKE_UP_SUPPORT + SbSetupData->EhciConDisConWakeUp = 0; +#endif + + SbSetupData->PchSata = 1; + if(PchSeries == PchLp){ + SbSetupData->ULTSataInterfaceMode = 1; + }else{ + SbSetupData->SataInterfaceMode = 0; + } + SbSetupData->SataTestMode = 0; +#if SataDriver_SUPPORT + SbSetupData->SataRaidRom = 0; +#endif + SbSetupData->SalpSupport = 1; + SbSetupData->SataControllerSpeed = 3; + SbSetupData->SataAlternateId = 0; + SbSetupData->PcieRootPortSBDE = 0; + SbSetupData->PcieSBDEPort = 0; + //do not use i[8] + for(i = 0; i < 8; i++) { + SbSetupData->PcieRootPortEn[i] = 1; + SbSetupData->PcieRootPortAspm[i] = 4; + SbSetupData->PcieRootPortURE[i] = 0; + SbSetupData->PcieRootPortFEE[i] = 0; + SbSetupData->PcieRootPortNFE[i] = 0; + SbSetupData->PcieRootPortCEE[i] = 0; + SbSetupData->PcieRootPortCTD[i] = 0; + SbSetupData->PcieRootPortPIE[i] = 0; + SbSetupData->PcieRootPortSFE[i] = 0; + SbSetupData->PcieRootPortSNE[i] = 0; + SbSetupData->PcieRootPortSCE[i] = 0; + SbSetupData->PcieRootPortL1S[i] = 0; + SbSetupData->PcieRootPortPMCE[i] = 1; + SbSetupData->PcieRootPortHPE[i] = 0; + SbSetupData->PcieRootPortSpeed[i] = 0; + SbSetupData->PcieRPDetectNonComplaint[i] = 0; + SbSetupData->PcieLtrEnable[i] = 1; + SbSetupData->PcieLtrConfigLock[i] = 1; + SbSetupData->PcieSnoopLatencyOverrideMode[i] = 2; + SbSetupData->PcieSnoopLatencyOverrideMultiplier[i] = 2; + SbSetupData->PcieSnoopLatencyOverrideValue[i] = 60; + SbSetupData->PcieNonSnoopLatencyOverrideMode[i] = 2; + SbSetupData->PcieNonSnoopLatencyOverrideMultiplier[i] = 2; + SbSetupData->PcieNonSnoopLatencyOverrideValue[i] = 60; + +#if Thunderbolt_SUPPORT + if (i == TBT_UP_PORT_FUNC){ + SbSetupData->PcieMemRsvdalig[i] = 26; + SbSetupData->PciePFMemRsvdalig[i] = 28; + } + else{ + SbSetupData->PcieMemRsvdalig[i] = 1; + SbSetupData->PciePFMemRsvdalig[i] = 1; + } +#else + SbSetupData->PcieMemRsvdalig[i] = 1; + SbSetupData->PciePFMemRsvdalig[i] = 1; +#endif + } + + //do not use i[14] + for(i = 0; i < 14; i++) { + SbSetupData->PchUsbPort[i] = 1; + } + + //do not use i[6] + for(i = 0; i < 6; i++) { + SbSetupData->PchUsb30Port[i] = 1; + } + + //do not use i[6] + for(i = 0; i < 6; i++) { + SbSetupData->SataPort[i] = 0; + SbSetupData->SataHotPlug[i] = 0; + SbSetupData->SataMechanicalSw[i] = 0; + SbSetupData->ExternalSata[i] = 0; + SbSetupData->SataSpinUp[i] = 0; + SbSetupData->SataDevSlp[i] = 0; + SbSetupData->EnableDitoConfig[i] = 0; + SbSetupData->DmVal[i] = 15; + SbSetupData->DitoVal[i] = 625; + SbSetupData->SolidStateDrive[i] = 0; + } + + SbSetupData->UsbPrecondition = 0; + SbSetupData->PchUsb30Mode = 3; +// for(i = 0; i < 4; i++) { +// SbSetupData->PchUsb30HsPortSwitchable[i] = 1; +// } + SbSetupData->PchEnableRmh1 = 1; + + //do not use i[2] + for(i = 0; i < 2; i++) { + SbSetupData->PchUsb20[i] = 1; + } + SbSetupData->PchUsb30PreBootSupport = 1; + SbSetupData->PchUsb30IdleL1 = 1; + SbSetupData->PchUsb30Btcg = 0; + SbSetupData->PchUsb20PinRoute = 1; + SbSetupData->PchUsb30PinEnable = 1; + for(i = 0; i < 14; i++) { + SbSetupData->ManualModeUsb20PerPinRoute[i] = 0; + } + for(i = 0; i < 6; i++) { + SbSetupData->ManualModeUsb30PerPinEnable[i] = 0; + } +// SbSetupData->XhciStreams = 1; + + SbSetupData->SataRaidR0 = 1; + SbSetupData->SataRaidR1 = 1; + SbSetupData->SataRaidR10 = 1; + SbSetupData->SataRaidR5 = 1; + SbSetupData->SataRaidIrrt = 1; + SbSetupData->SataRaidOub = 1; + SbSetupData->SataHddlk = 1; + SbSetupData->SataLedl = 1; + SbSetupData->SataRaidIooe = 1; + SbSetupData->SmartStorage = 1; + SbSetupData->OromUiDelay = 0; + + // PCH Thermal + SbSetupData->AutoThermalReport = 1; + SbSetupData->Ac1TripPoint = 55; + SbSetupData->Ac0TripPoint = 71; + SbSetupData->Ac0FanSpeed = 100; + SbSetupData->Ac1FanSpeed = 75; + SbSetupData->PassiveThermalTripPoint = 95; + SbSetupData->CriticalThermalTripPoint = 100; + SbSetupData->PassiveTc1Value = 1; + SbSetupData->PassiveTc2Value = 5; + SbSetupData->PassiveTspValue = 10; + + SbSetupData->ThermalDeviceEnable = 0; + SbSetupData->PchCrossThrottling = 0; + SbSetupData->CPUTempReadEnable = 1; + SbSetupData->CPUEnergyReadEnable = 1; + SbSetupData->PCHTempReadEnable = 1; + + SbSetupData->AlertEnableLock = 0; + SbSetupData->PchAlert = 0; + SbSetupData->DimmAlert = 0; + + SbSetupData->PchHotLevel = 0; + SbSetupData->TPV_Restrict_Enable = 0; + + SbSetupData->TsOnDimm1 = 0; + SbSetupData->TsOnDimm2 = 0; + SbSetupData->TsOnDimm3 = 0; + SbSetupData->TsOnDimm4 = 0; + + SbSetupData->SMBusECMsgLen = 0; + SbSetupData->SMBusECMsgPEC = 0; + + SbSetupData->ECTurboControlMode = 0; + SbSetupData->ACBrickCapacity = 1; + SbSetupData->ECPollingPeriod = 1; + SbSetupData->ECGuardBandValue = 0; + SbSetupData->ECAlgorithmSel = 1; + SbSetupData->ECHybridPowerBoost = 0; + SbSetupData->ECHybridCurrent = 0x1284; + SbSetupData->ECTG = 0; + + // PchLp LPSS + SbSetupData->LpssDmaEnable = 1; + SbSetupData->LpssI2c0Enable = 1; + SbSetupData->LpssI2c1Enable = 1; + SbSetupData->LpssSpi0Enable = 1; + SbSetupData->LpssSpi1Enable = 1; + SbSetupData->LpssUart0Enable = 1; + SbSetupData->LpssUart1Enable = 1; + SbSetupData->LpssSdioEnable = 1; + SbSetupData->LpssMode = 1; + SbSetupData->LpssIntMode = 1; + SbSetupData->I2C0VoltageSelect = 1; + SbSetupData->I2C1VoltageSelect = 0; + SbSetupData->SensorHub = 0; + SbSetupData->TPD4 = 0; + SbSetupData->AtmelTPL = 0; + SbSetupData->ElanTPL = 0; + SbSetupData->ElanTPD = 0; + SbSetupData->SynaTPD = 0; + SbSetupData->NtriTPL = 0; + SbSetupData->EetiTPL = 0; + SbSetupData->AlpsTPD = 0; + SbSetupData->CyprTPD = 0; + SbSetupData->Bluetooth0 = 0; + SbSetupData->Bluetooth1 = 0; + + SbSetupData->I2C0SSH = 432; + SbSetupData->I2C0SSL = 507; + SbSetupData->I2C0SSD = 9; + SbSetupData->I2C0FMH = 72; + SbSetupData->I2C0FML = 160; + SbSetupData->I2C0FMD = 9; + SbSetupData->I2C0FPH = 29; + SbSetupData->I2C0FPL = 50; + SbSetupData->I2C0FPD = 5; + SbSetupData->I2C0M0C0 = 500; + SbSetupData->I2C0M1C0 = 2000; + SbSetupData->I2C0M2C0 = 0; + + SbSetupData->I2C1SSH = 432; + SbSetupData->I2C1SSL = 507; + SbSetupData->I2C1SSD = 9; + SbSetupData->I2C1FMH = 72; + SbSetupData->I2C1FML = 160; + SbSetupData->I2C1FMD = 9; + SbSetupData->I2C1FPH = 29; + SbSetupData->I2C1FPL = 50; + SbSetupData->I2C1FPD = 5; + SbSetupData->I2C1M0C1 = 500; + SbSetupData->I2C1M1C1 = 2000; + SbSetupData->I2C1M2C1 = 0; + + SbSetupData->SPI0M0C2 = 500; + SbSetupData->SPI0M1C2 = 2000; + + SbSetupData->SPI1M0C3 = 500; + SbSetupData->SPI1M1C3 = 2000; + + SbSetupData->UAR0M0C4 = 500; + SbSetupData->UAR0M1C4 = 2000; + + SbSetupData->UAR1M0C5 = 500; + SbSetupData->UAR1M1C5 = 2000; + + // PchLp Audio DSP + SbSetupData->ADspEnable = 0; + SbSetupData->ADspD3PG = 1; + SbSetupData->ADspCodecSelect = 0; + SbSetupData->ADspBluetooth = 0; + SbSetupData->ADspMode = 1; + // Porting End + SbSetupData->NFCE = 0; + + if (Pei) { + PeiServices = (EFI_PEI_SERVICES **)Services; + Status = (*PeiServices)->LocatePpi( PeiServices, \ + &gPeiReadOnlyVarPpiGuid, \ + 0, \ + NULL, \ + &ReadOnlyVariable ); + + if (!EFI_ERROR(Status)) { + Status = ReadOnlyVariable->GetVariable( ReadOnlyVariable, \ + L"Setup", \ + &gSetupGuid, \ + NULL, \ + &VariableSize, \ + &SetupData ); + } + } else { + RunServices = (EFI_RUNTIME_SERVICES *)Services; + Status = RunServices->GetVariable( L"Setup", \ + &gSetupGuid, \ + NULL, \ + &VariableSize, \ + &SetupData ); + } + + if (EFI_ERROR(Status)) { + SbOemSetupCallbacks( Services, SbSetupData, NULL, Pei ); + } else { + SbOemSetupCallbacks( Services, SbSetupData, &SetupData, Pei ); + } + + // Thermal reporting policy is based on strap settings (PCH Strap 15 [14]) + if ((READ_MEM16_SPI (0x04) & BIT14) == BIT14) { // Check Flash Descriptor Valid + Buffer32 = READ_MEM32_SPI(R_RCRB_SPI_FDOC) & (~(B_PCH_SPI_FDOC_FDSS_MASK | B_PCH_SPI_FDOC_FDSI_MASK)); + Buffer32 |= (UINT32) (V_PCH_SPI_FDOC_FDSS_PCHS | R_PCH_SPI_STRP15); + MMIO_WRITE32(SB_RCRB_BASE_ADDRESS + SPI_BASE_ADDRESS|R_RCRB_SPI_FDOC, Buffer32); + Buffer32 = READ_MEM32_SPI(R_RCRB_SPI_FDOD); + if ((Buffer32 & BIT14) == 0) { + SbSetupData->TrEnabled = 1; + } else { + SbSetupData->TrEnabled = 0; + } + } +} + +#if defined SB_SETUP_SUPPORT && SB_SETUP_SUPPORT == 1 +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SbSetupCallbacks +// +// Description: This function returns SB Chipset setup data from system SetupData +// variable +// +// Input: *Services - Pointer to PeiServices or RuntimeServices +// structure +// *SbSetupData - Pointer to custom setup data to return +// *SetupData - Pointer to system setup data. +// Pei - Pei flag. If TRUE we are in PEI phase +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SbSetupCallbacks ( + IN VOID *Services, + IN OUT SB_SETUP_DATA *SbSetupData, + IN SETUP_DATA *SetupData, + IN BOOLEAN Pei ) +{ + UINT8 i; + PCH_SERIES PchSeries = GetPchSeries(); + + if (SetupData != NULL) { + // Porting Start + // Update SB_SETUP_DATA according to the setup datas. + SbSetupData->PchLan = SetupData->PchLan; + SbSetupData->PchWakeOnLan = SetupData->PchWakeOnLan; + SbSetupData->SlpLanLow = SetupData->SlpLanLow; + SbSetupData->BoardCapability = SetupData->BoardCapability; + SbSetupData->DeepSxBattMode = SetupData->DeepSxBattMode; + SbSetupData->DeepSxMode = SetupData->DeepSxMode; + SbSetupData->Gp27Wake = SetupData->Gp27Wake; + SbSetupData->PcieWake = SetupData->PcieWake; + SbSetupData->PchAzalia = SetupData->PchAzalia; + SbSetupData->AzaliaDs = SetupData->AzaliaDs; + SbSetupData->AzaliaPme = SetupData->AzaliaPme; + SbSetupData->Hpet = SetupData->Hpet; + SbSetupData->PchPciClockRun = SetupData->PchPciClockRun; + SbSetupData->SirqMode = SetupData->SirqMode; + SbSetupData->PchEnableCrid = SetupData->PchEnableCrid; + SbSetupData->PchDisplay = SetupData->PchDisplay; + SbSetupData->SlpS4AssW = SetupData->SlpS4AssW; + SbSetupData->Port80Route = SetupData->Port80Route; + SbSetupData->LastState = SetupData->LastState; +#if PCI_EXPRESS_SUPPORT + SbSetupData->AspmMode = SetupData->AspmMode; +#else + SbSetupData->AspmMode = 0; +#endif + + SbSetupData->SmiLock = SetupData->SmiLock; + SbSetupData->BiosLock = SetupData->BiosLock; + SbSetupData->GpioLock = SetupData->GpioLock; + SbSetupData->BiosInterfaceLock = SetupData->BiosInterfaceLock; + SbSetupData->RtcLock = SetupData->RtcLock; + + SbSetupData->PchDmiAspm = SetupData->PchDmiAspm; + SbSetupData->PchDmiExtSync = SetupData->PchDmiExtSync; + SbSetupData->PcieClockGating = SetupData->PcieClockGating; + SbSetupData->RootPortFunctionSwapping = SetupData->RootPortFunctionSwapping; + SbSetupData->PcieUsbWa = SetupData->PcieUsbWa; + SbSetupData->PchUsbPerPortCtl = SetupData->PchUsbPerPortCtl; + +#if EHCI_CON_DISCON_WAKE_UP_SUPPORT + SbSetupData->EhciConDisConWakeUp = SetupData->EhciConDisConWakeUp; +#endif + + SbSetupData->PchSata = SetupData->PchSata; + if(PchSeries == PchLp){ + SbSetupData->SataInterfaceMode = SetupData->ULTSataInterfaceMode; + }else{ + SbSetupData->SataInterfaceMode = SetupData->SataInterfaceMode; + } + SbSetupData->SataTestMode = SetupData->SataTestMode; +#if SataDriver_SUPPORT + SbSetupData->SataRaidRom = SetupData->SataRaidRom; +#endif + SbSetupData->SalpSupport = SetupData->SalpSupport; + SbSetupData->SataControllerSpeed = SetupData->SataControllerSpeed; + SbSetupData->SataAlternateId = SetupData->SataAlternateId; + SbSetupData->PcieRootPortSBDE = SetupData->PcieRootPortSBDE; + SbSetupData->PcieSBDEPort = SetupData->PcieSBDEPort; + //do not use i[8] + for(i = 0; i < 8; i++) { + SbSetupData->PcieRootPortEn[i] = SetupData->PcieRootPortEn[i]; + SbSetupData->PcieRootPortAspm[i] = SetupData->PcieRootPortAspm[i]; + SbSetupData->PcieRootPortURE[i] = SetupData->PcieRootPortURE[i]; + SbSetupData->PcieRootPortFEE[i] = SetupData->PcieRootPortFEE[i]; + SbSetupData->PcieRootPortNFE[i] = SetupData->PcieRootPortNFE[i]; + SbSetupData->PcieRootPortCEE[i] = SetupData->PcieRootPortCEE[i]; + SbSetupData->PcieRootPortCTD[i] = SetupData->PcieRootPortCTD[i]; + SbSetupData->PcieRootPortPIE[i] = SetupData->PcieRootPortPIE[i]; + SbSetupData->PcieRootPortSFE[i] = SetupData->PcieRootPortSFE[i]; + SbSetupData->PcieRootPortSNE[i] = SetupData->PcieRootPortSNE[i]; + SbSetupData->PcieRootPortSCE[i] = SetupData->PcieRootPortSCE[i]; + SbSetupData->PcieRootPortL1S[i] = SetupData->PcieRootPortL1S[i]; + SbSetupData->PcieRootPortPMCE[i] = SetupData->PcieRootPortPMCE[i]; + SbSetupData->PcieRootPortHPE[i] = SetupData->PcieRootPortHPE[i]; + SbSetupData->PcieRootPortSpeed[i] = SetupData->PcieRootPortSpeed[i]; + SbSetupData->PcieMemRsvdalig[i] = SetupData->PcieMemRsvdalig[i]; + SbSetupData->PciePFMemRsvdalig[i] = SetupData->PciePFMemRsvdalig[i]; + SbSetupData->PcieRPDetectNonComplaint[i] = SetupData->PcieRPDetectNonComplaint[i]; + SbSetupData->PcieLtrEnable[i] = SetupData->PcieLtrEnable[i];; + SbSetupData->PcieLtrConfigLock[i] = SetupData->PcieLtrConfigLock[i];; + SbSetupData->PcieSnoopLatencyOverrideMode[i] = SetupData->PcieSnoopLatencyOverrideMode[i];; + SbSetupData->PcieSnoopLatencyOverrideMultiplier[i] = SetupData->PcieSnoopLatencyOverrideMultiplier[i];; + SbSetupData->PcieSnoopLatencyOverrideValue[i] = SetupData->PcieSnoopLatencyOverrideValue[i];; + SbSetupData->PcieNonSnoopLatencyOverrideMode[i] = SetupData->PcieNonSnoopLatencyOverrideMode[i];; + SbSetupData->PcieNonSnoopLatencyOverrideMultiplier[i] = SetupData->PcieNonSnoopLatencyOverrideMultiplier[i];; + SbSetupData->PcieNonSnoopLatencyOverrideValue[i] = SetupData->PcieNonSnoopLatencyOverrideValue[i];; + } + + //do not use i[14] + for(i = 0; i < 14; i++) { + SbSetupData->PchUsbPort[i] = SetupData->PchUsbPort[i]; + } + + //do not use i[6] + for(i = 0; i < 6; i++) { + SbSetupData->PchUsb30Port[i] = SetupData->PchUsbPort[i]; + } + + //do not use i[6] + for(i = 0; i < 6; i++) { + SbSetupData->SataPort[i] = SetupData->SataPort[i]; + SbSetupData->SataHotPlug[i] = SetupData->SataHotPlug[i]; + + if (SbSetupData->SataHotPlug[i] == 1) + SbSetupData->SataMechanicalSw[i]= SetupData->SataMechanicalSw[i]; + else + SbSetupData->SataMechanicalSw[i]= 0; + + SbSetupData->ExternalSata[i] = SetupData->ExternalSata[i]; + + SbSetupData->SataSpinUp[i] = SetupData->SataSpinUp[i]; + SbSetupData->SataDevSlp[i] = SetupData->SataDevSlp[i]; + SbSetupData->EnableDitoConfig[i] = SetupData->SataEnableDitoConfig[i]; + SbSetupData->DitoVal[i] = SetupData->SataDitoVal[i]; + SbSetupData->DmVal[i] = SetupData->SataDmVal[i]; + SbSetupData->SolidStateDrive[i] = SetupData->SolidStateDrive[i]; + } + + SbSetupData->UsbPrecondition = SetupData->UsbPrecondition; + SbSetupData->PchUsb30Mode = SetupData->PchUsb30Mode; +// for(i = 0; i < 4; i++) { +// SbSetupData->PchUsb30HsPortSwitchable[i] = SetupData->PchUsb30HsPortSwitchable[i]; +// } + SbSetupData->PchEnableRmh1 = SetupData->PchEnableRmh1; + + SbSetupData->PchUsb30PreBootSupport = SetupData->PchUsb30PreBootSupport; + SbSetupData->PchUsb30IdleL1 = SetupData->PchUsb30IdleL1; + SbSetupData->PchUsb30Btcg = SetupData->PchUsb30Btcg; + + SbSetupData->PchUsb20PinRoute = SetupData->PchUsb20PinRoute; + SbSetupData->PchUsb30PinEnable = SetupData->PchUsb30PinEnable; + for(i = 0; i < 14; i++) { + SbSetupData->ManualModeUsb20PerPinRoute[i] = SetupData->ManualModeUsb20PerPinRoute[i]; + } + for(i = 0; i < 6; i++) { + SbSetupData->ManualModeUsb30PerPinEnable[i] = SetupData->ManualModeUsb30PerPinEnable[i]; + } +// SbSetupData->XhciStreams = SetupData->XhciStreams; + + //do not use i[2] + for(i = 0; i < 2; i++) { + SbSetupData->PchUsb20[i] = SetupData->PchUsb20[i]; + } + + SbSetupData->SataRaidR0 = SetupData->SataRaidR0; + SbSetupData->SataRaidR1 = SetupData->SataRaidR1; + SbSetupData->SataRaidR10 = SetupData->SataRaidR10; + SbSetupData->SataRaidR5 = SetupData->SataRaidR5; + SbSetupData->SataRaidIrrt = SetupData->SataRaidIrrt; + SbSetupData->SataRaidOub = SetupData->SataRaidOub; + SbSetupData->SataHddlk = SetupData->SataHddlk; + SbSetupData->SataLedl = SetupData->SataLedl; + SbSetupData->SataRaidIooe = SetupData->SataRaidIooe; + SbSetupData->SmartStorage = SetupData->SmartStorage; + SbSetupData->OromUiDelay = SetupData->OromUiDelay; + + // PCH Thermal + SbSetupData->AutoThermalReport = SetupData->AutoThermalReport; + SbSetupData->Ac1TripPoint = SetupData->Ac1TripPoint; + SbSetupData->Ac0TripPoint = SetupData->Ac0TripPoint; + SbSetupData->Ac0FanSpeed = SetupData->Ac0FanSpeed; + SbSetupData->Ac1FanSpeed = SetupData->Ac1FanSpeed; + SbSetupData->PassiveThermalTripPoint = SetupData->PassiveThermalTripPoint; + SbSetupData->CriticalThermalTripPoint = SetupData->CriticalThermalTripPoint; + SbSetupData->PassiveTc1Value = SetupData->PassiveTc1Value; + SbSetupData->PassiveTc2Value = SetupData->PassiveTc2Value; + SbSetupData->PassiveTspValue = SetupData->PassiveTspValue; + + SbSetupData->AlertEnableLock = SetupData->AlertEnableLock; + SbSetupData->PchAlert = SetupData->PchAlert; + SbSetupData->DimmAlert = SetupData->DimmAlert; + + SbSetupData->CPUTempReadEnable = SetupData->CPUTempReadEnable; + SbSetupData->CPUEnergyReadEnable = SetupData->CPUEnergyReadEnable; + SbSetupData->ThermalDeviceEnable = SetupData->ThermalDeviceEnable; + SbSetupData->PchCrossThrottling = SetupData->PchCrossThrottling; + SbSetupData->PCHTempReadEnable = SetupData->PCHTempReadEnable; + + SbSetupData->PchHotLevel = SetupData->PchHotLevel; + SbSetupData->TPV_Restrict_Enable = SetupData->TPV_Restrict_Enable; + + SbSetupData->TsOnDimm1 = SetupData->TsOnDimm1; + SbSetupData->TsOnDimm2 = SetupData->TsOnDimm2; + SbSetupData->TsOnDimm3 = SetupData->TsOnDimm3; + SbSetupData->TsOnDimm4 = SetupData->TsOnDimm4; + + SbSetupData->SMBusECMsgLen = SetupData->SMBusECMsgLen; + SbSetupData->SMBusECMsgPEC = SetupData->SMBusECMsgPEC; + + SbSetupData->ECTurboControlMode = SetupData->ECTurboControlMode; + SbSetupData->ACBrickCapacity = SetupData->ACBrickCapacity; + SbSetupData->ECPollingPeriod = SetupData->ECPollingPeriod; + SbSetupData->ECGuardBandValue = SetupData->ECGuardBandValue; + SbSetupData->ECAlgorithmSel = SetupData->ECAlgorithmSel; + SbSetupData->ECHybridPowerBoost = SetupData->ECHybridPowerBoost; + SbSetupData->ECHybridCurrent = SetupData->ECHybridCurrent; + SbSetupData->ECTG = SetupData->ECTG; + + // PchLp LPSS + SbSetupData->LpssDmaEnable = SetupData->LpssDmaEnable; + SbSetupData->LpssI2c0Enable = SetupData->LpssI2c0Enable; + SbSetupData->LpssI2c1Enable = SetupData->LpssI2c1Enable; + SbSetupData->LpssSpi0Enable = SetupData->LpssSpi0Enable; + SbSetupData->LpssSpi1Enable = SetupData->LpssSpi1Enable; + SbSetupData->LpssUart0Enable = SetupData->LpssUart0Enable; + SbSetupData->LpssUart1Enable = SetupData->LpssUart1Enable; + SbSetupData->LpssSdioEnable = SetupData->LpssSdioEnable; + SbSetupData->LpssMode = SetupData->LpssMode; + SbSetupData->LpssIntMode = SetupData->LpssIntMode; + SbSetupData->I2C0VoltageSelect = SetupData->I2C0VoltageSelect; + SbSetupData->I2C1VoltageSelect = SetupData->I2C1VoltageSelect; + SbSetupData->SensorHub = SetupData->SensorHub; + SbSetupData->TPD4 = SetupData->TPD4; + SbSetupData->AtmelTPL = SetupData->AtmelTPL; + SbSetupData->ElanTPL = SetupData->ElanTPL; + SbSetupData->ElanTPD = SetupData->ElanTPD; + SbSetupData->SynaTPD = SetupData->SynaTPD; + SbSetupData->NtriTPL = SetupData->NtriTPL; + SbSetupData->EetiTPL = SetupData->EetiTPL; + SbSetupData->AlpsTPD = SetupData->AlpsTPD; + SbSetupData->CyprTPD = SetupData->CyprTPD; + SbSetupData->Bluetooth0 = SetupData->Bluetooth0; + SbSetupData->Bluetooth1 = SetupData->Bluetooth1; + + SbSetupData->I2C0SSH = SetupData->I2C0SSH; + SbSetupData->I2C0SSL = SetupData->I2C0SSL; + SbSetupData->I2C0SSD = SetupData->I2C0SSD; + SbSetupData->I2C0FMH = SetupData->I2C0FMH; + SbSetupData->I2C0FML = SetupData->I2C0FML; + SbSetupData->I2C0FMD = SetupData->I2C0FMD; + SbSetupData->I2C0FPH = SetupData->I2C0FPH; + SbSetupData->I2C0FPL = SetupData->I2C0FPL; + SbSetupData->I2C0FPD = SetupData->I2C0FPD; + SbSetupData->I2C0M0C0 = SetupData->I2C0M0C0; + SbSetupData->I2C0M1C0 = SetupData->I2C0M1C0; + SbSetupData->I2C0M2C0 = SetupData->I2C0M2C0; + + SbSetupData->I2C1SSH = SetupData->I2C1SSH; + SbSetupData->I2C1SSL = SetupData->I2C1SSL; + SbSetupData->I2C1SSD = SetupData->I2C1SSD; + SbSetupData->I2C1FMH = SetupData->I2C1FMH; + SbSetupData->I2C1FML = SetupData->I2C1FML; + SbSetupData->I2C1FMD = SetupData->I2C1FMD; + SbSetupData->I2C1FPH = SetupData->I2C1FPH; + SbSetupData->I2C1FPL = SetupData->I2C1FPL; + SbSetupData->I2C1FPD = SetupData->I2C1FPD; + SbSetupData->I2C1M0C1 = SetupData->I2C1M0C1; + SbSetupData->I2C1M1C1 = SetupData->I2C1M1C1; + SbSetupData->I2C1M2C1 = SetupData->I2C1M2C1; + + SbSetupData->SPI0M0C2 = SetupData->SPI0M0C2; + SbSetupData->SPI0M1C2 = SetupData->SPI0M1C2; + + SbSetupData->SPI1M0C3 = SetupData->SPI1M0C3; + SbSetupData->SPI1M1C3 = SetupData->SPI1M1C3; + + SbSetupData->UAR0M0C4 = SetupData->UAR0M0C4; + SbSetupData->UAR0M1C4 = SetupData->UAR0M1C4; + + SbSetupData->UAR1M0C5 = SetupData->UAR1M0C5; + SbSetupData->UAR1M1C5 = SetupData->UAR1M1C5; + + // PchLp Audio DSP + SbSetupData->ADspEnable = SetupData->ADspEnable; + SbSetupData->ADspD3PG = SetupData->ADspD3PG; + SbSetupData->ADspCodecSelect = SetupData->ADspCodecSelect; + SbSetupData->ADspBluetooth = SetupData->ADspBluetooth; + SbSetupData->ADspMode = SetupData->ADspMode; + // Porting End + SbSetupData->NFCE = SetupData->NFCE; + } +} + +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/HDAVBTBL.h b/Board/SB/HDAVBTBL.h new file mode 100644 index 0000000..5523909 --- /dev/null +++ b/Board/SB/HDAVBTBL.h @@ -0,0 +1,77 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/HDAVBTBL.h 1 2/08/12 8:22a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:22a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/HDAVBTBL.h $ +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: HDAVBTBL.h +// +// Description: HD Audio Verb Table +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef _HDAVBTBL_H // To Avoid this header get compiled twice +#define _HDAVBTBL_H +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + UINT32 CodecId32; + UINT16 CodecSubId16; + UINT8 RevisionId; // 0xFF applies to all steppings + UINT8 FrontPanel; + UINT16 RearSideNo; + UINT16 frontSideNo; + UINT32 *VerbPtr; +} HDA_VERB_TABLE; + +OEM_HDA_VERB_TABLE_CONTENT +HDA_VERB_TABLE HdaVerbTbl[] = { OEM_HDA_VERB_TABLE }; + + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/SB.H b/Board/SB/SB.H new file mode 100644 index 0000000..195aa23 --- /dev/null +++ b/Board/SB/SB.H @@ -0,0 +1,998 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SB.H 11 5/16/14 6:19a Barretlin $ +// +// $Revision: 11 $ +// +// $Date: 5/16/14 6:19a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SB.H $ +// +// 11 5/16/14 6:19a Barretlin +// [TAG] EIP167087 +// [Category] Improvement +// [Description] BIOS security improvement on Haswell CRB project +// [Files] SBGeneric.c SBDxe.c SBCspLib.h Sb.sdl Sb.sd Sb.h +// +// 10 10/28/13 2:46a Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] add programming serial IO device's SSID +// [Files] SB.sdl SB.H +// +// 9 5/10/13 1:40a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remover ULT_SUPPORT token at SB.h. +// [Files] SB.h +// +// 8 4/24/13 2:14a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Porting GPI interrupt by LPT-LP EDS 1.5. +// [Files] SB.sdl, SB.H, SBPPI.h, SBPEI.c +// +// 7 4/16/13 11:24p Wesleychen +// [TAG] EIP120787 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] System might halts at CKP 0x55 with some specific +// combinations. (Ex: i7-4770 / 4570 + Hynix 4G / 2G) +// [RootCause] All Reference codes are validated with Traditional and +// ULT build flags enabled. +// Having one of the flags disable may lead code execution +// that is not validated by Intel and may cause system +// instability. +// [Solution] Make "TRAD_FLAG" and "ULT_FLAG" are coexist. +// [Files] MemoryInit.sdl; SB.h +// +// 6 3/22/13 7:00a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Wireless LAN PHY use SLP_WLAN# pin +// [Files] SB.sdl, SBDxe.c, SB.H +// +// 5 9/26/12 3:47a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for PCH LP GPIO compatible. +// [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c +// +// 4 9/12/12 5:09a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Support OEM update VSCC table. +// [Files] SB.H, SB.mak, SB.sdl, SBDXE.c +// +// [TAG] None +// [Category] Improvement +// [Description] Modify for ULT GPIO changed by PCH LPT-LP EDS 1.0. +// [Files] SB.H, SB.sdl, AcpiModeEnable.c, AcpiModeEnable.sdl, +// SBPEI.c +// +// 3 7/27/12 6:03a Victortu +// Update to support ULT Platform. +// +// 2 6/13/12 11:33p Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement Warm Boot function for Secure Flash feature. +// [Files] SB.H, SB.mak, SB.sdl, SBDxe.c, SBGeneric.c, SBPEI.c, +// SBSMI.c +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SB.h +// +// Description: South Bridge header file, define all the South Bridge +// specific equates and structures in this file. +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef _SB_H // To Avoid this header get compiled twice +#define _SB_H + +#include <Token.h> + +#define SB_PCI_CFG_ADDRESS(bus, dev, func, reg) \ + (UINT64) ((((UINT8)(bus) << 24) + ((UINT8)(dev) << 16) + \ + ((UINT8)(func) << 8) + ((UINT8)(reg))) & 0xffffffff) + +#ifdef PCIEX_BASE_ADDRESS +#define SB_PCIE_CFG_ADDRESS(bus, dev, func, reg) \ + ((UINTN)(PCIEX_BASE_ADDRESS + ((UINT8)(bus) << 20) + \ + ((UINT8)(dev) << 15) + ((UINT8)(func) << 12) + (reg))) +#endif + +#ifndef CORE_VERSION +#define CORE_VERSION ( CORE_MAJOR_VERSION * 1000 + \ + CORE_MINOR_VERSION * 100 + \ + CORE_REVISION * 10 + \ + CORE_BUILD_NUMBER ) +#endif + +#ifndef PCIBUS_VERSION +#define PCIBUS_VERSION ( PCI_BUS_MAJOR_VER * 10000 + \ + PCI_BUS_MINOR_VER * 100 + \ + PCI_BUS_REVISION ) +#endif + +// 8259 Hardware definitions + +#define LEGACY_MODE_BASE_VECTOR_MASTER 0x08 +#define LEGACY_MODE_BASE_VECTOR_SLAVE 0x10 +#define LEGACY_8259_CONTROL_REGISTER_MASTER 0x20 +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21 +#define LEGACY_8259_CONTROL_REGISTER_SLAVE 0xa0 +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xa1 +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4d0 +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4d1 +#define LEGACY_8259_EOI 0x20 + +// 8254 Timer definitions +#define LEGACY_TIMER_0_COUNT 0x40 +#define LEGACY_TIMER_1_COUNT 0x41 +#define LEGACY_TIMER_CTRL 0x43 + +#define SLP_S5 7 // Porting Required. + +#define NUM_BITS_IN_ACPI_TIMER 24 // Programmed to 24 not 32 +// This is the maximum possible bits in the timer. +// Currently this is 32 according to the spec. +#define MAX_ACPI_TIMER_BITS 32 + +typedef struct DMA_INIT_tag{ + UINT8 PortAddr; + UINT8 Value; +} DMA_INIT; + +#define SB_ASL_BUFFER_PTR_GUID { 0x1f33c25, 0x764d, 0x43ea, 0xae, 0xea, 0x6b, \ + 0x5a, 0x41, 0xf3, 0xf3, 0xe8 } + +#define SB_ASL_BUFFER_PTR_VARIABLE L"SbAslBufferPtrVar" + +typedef struct { + UINT8 SbAslByte0; + UINT8 SbAslByte1; + UINT8 SbAslByte2; + UINT8 SbAslByte3; + UINT8 SbAslByte4; + UINT8 SbAslByte5; + UINT8 SbAslByte6; + UINT8 SbAslByte7; + UINT8 SbAslByte8; + UINT8 SbAslByte9; + UINT8 SbAslByte10; + UINT8 SbAslByte11; + UINT8 SbAslByte12; + UINT8 SbAslByte13; + UINT8 SbAslByte14; + UINT8 SbAslByte15; +} SB_ASL_BUFFER; + +#define SB_WARM_RESET_GUID {0xb8cafa84, 0x4593, 0x4aa9, 0xae, 0xf7, 0x8e, \ + 0x68, 0x6e, 0xb0, 0x73, 0x20} + +#define SB_WARM_RESET_VARIABLE L"SbWarmResetVar" + +#define SB_WARM_RESET_TAG 'IsWR' + +#define RESET_PORT 0x0CF9 +#define CLEAR_RESET_BITS 0x0F9 +#define COLD_RESET 0x02 // Set bit 1 for cold reset +#define RST_CPU 0x04 // Setting this bit triggers a reset of the CPU + +typedef enum _SB_RESET_TYPE +{ + HardReset = 0, + SoftReset, + ShutDown, + FullReset = 0x80, + GlobalReset +} SB_RESET_TYPE; + +//---------------------------------------------------------------------------- +// INTEL PCH PCI Bus Number Equates +//---------------------------------------------------------------------------- +#define SB_BUS 0 // South Bridge Bus Number +#define LPC_BUS SB_BUS +#define SATA_BUS 0 // Serial ATA Controller Bus Number 1 +#define SATA2_BUS 0 // Serial ATA Controller Bus Number 1 +#define SMBUS_BUS 0 // SMBus Controller Bus Number +#define XHCI_BUS 0 // XHCI Controller 1 Bus Number +#define EHCI_BUS 0 // EHCI Controller 1 Bus Number +#define EHCI2_BUS 0 // EHCI Controller 2 Bus Number +#define THERMAL_BUS 0 // THERMAL Controller Bus Number +#define HDA_BUS 0 // HD Audio Controller Bus Number +#define LAN_BUS 0 // Ethernet GBE Controller Bus Num. +#define PCIBR_BUS 0 // South Bridge PCI Bus Bridge + // Bus Number +#define PCIEBRS_BUS 0 // South Bridge PCI Express Bridge 1 + // Bus Number +#define SBPCIE_BUS PCIEBRS_BUS +#define PCIEBRS2_BUS 0 // South Bridge PCI Express Bridge 2 + // Bus Number +#define PCIEBRS3_BUS 0 // South Bridge PCI Express Bridge 3 + // Bus Number +#define PCIEBRS4_BUS 0 // South Bridge PCI Express Bridge 4 + // Bus Number +#define PCIEBRS5_BUS 0 // South Bridge PCI Express Bridge 5 + // Bus Number +#define PCIEBRS6_BUS 0 // South Bridge PCI Express Bridge 6 + // Bus Number +#define PCIEBRS7_BUS 0 // South Bridge PCI Express Bridge 7 + // Bus Number +#define PCIEBRS8_BUS 0 // South Bridge PCI Express Bridge 8 + // Bus Number +#define HECI_BUS 0 // ME HECI Controller + // Interface Bus Number +#ifndef HECI2_BUS +#define HECI2_BUS 0 // ME HECI 2 Controller + // Interface Bus Number +#endif + +#define IDER_BUS 0 // ME IDER Controller + // Interface Bus Number +#define KT_BUS 0 // ME KT Controller + // Interface Bus Number + +#define SIO_DMA_BUS 0 // SIO DMA Controller + // Interface Bus Number +#define SIO_I2C0_BUS 0 // SIO I2C 0 Controller + // Interface Bus Number +#define SIO_I2C1_BUS 0 // SIO I2C 1 Controller + // Interface Bus Number +#define SIO_GSPI0_BUS 0 // SIO GSPI 0 Controller + // Interface Bus Number +#define SIO_GSPI1_BUS 0 // SIO GSPI 1 Controller + // Interface Bus Number +#define SIO_UART0_BUS 0 // SIO UART 0 Controller + // Interface Bus Number +#define SIO_UART1_BUS 0 // SIO UART 1 Controller + // Interface Bus Number +#define SIO_SDIO_BUS 0 // SIO SDIO Controller + // Interface Bus Number + +//---------------------------------------------------------------------------- +// INTEL PCH PCI Device Number Equates +//---------------------------------------------------------------------------- +#define SB_DEV 0x1f // South Bridge Device Number +#define LPC_DEVICE SB_DEV +#define SATA_DEV SB_DEV // Serial ATA Controller Device Num 1. +#define SATA2_DEV SB_DEV // Serial ATA Controller Device Num 1. +#define SMBUS_DEV SB_DEV // SMBus Controller Device Number. +#define XHCI_DEV 0x14 // XHCI Controller Device Number +#define EHCI_DEV 0x1d // EHCI Controller 1 Device Number +#define EHCI2_DEV 0x1a // EHCI Controller 2 Device Number +#define THERMAL_DEV SB_DEV // THERMAL Controller Device Number +#define LAN_DEV 0x19 // Ethernet GBE Controller Device Num. +#define HDA_DEV 0x1b // HD Audio Controller Device Number +#define PCIBR_DEV 0x1e // South Bridge PCI Bus Bridge + // Device Number +#define PCIEBRS_DEV 0x1c // South Bridge PCI Express Bridge 1 + // Device Number +#define SBPCIE_DEV PCIEBRS_DEV +#define PCIEBRS2_DEV 0x1c // South Bridge PCI Express Bridge 2 + // Device Number +#define PCIEBRS3_DEV 0x1c // South Bridge PCI Express Bridge 3 + // Device Number +#define PCIEBRS4_DEV 0x1c // South Bridge PCI Express Bridge 4 + // Device Number +#define PCIEBRS5_DEV 0x1c // South Bridge PCI Express Bridge 5 + // Device Number +#define PCIEBRS6_DEV 0x1c // South Bridge PCI Express Bridge 6 + // Device Number +#define PCIEBRS7_DEV 0x1c // South Bridge PCI Express Bridge 7 + // Device Number +#define PCIEBRS8_DEV 0x1c // South Bridge PCI Express Bridge 8 + // Device Number +#define HECI_DEV 0x16 // ME HECI 2 Controller + // Interface Device Number +#define ME_DEV HECI_DEV + +#define HECI2_DEV 0x16 // ME HECI 2 Controller + // Interface Device Number +#define IDER_DEV 0x16 // ME IDER Controller + // Interface Device Number +#define KT_DEV 0x16 // ME KT Controller + // Interface Device Number + +#define SIO_DMA_DEV 0x15 // SIO DMA Controller + // Interface Device Number +#define SIO_I2C0_DEV 0x15 // SIO I2C 0 Controller + // Interface Device Number +#define SIO_I2C1_DEV 0x15 // SIO I2C 1 Controller + // Interface Device Number +#define SIO_GSPI0_DEV 0x15 // SIO GSPI 0 Controller + // Interface Device Number +#define SIO_GSPI1_DEV 0x15 // SIO GSPI 1 Controller + // Interface Device Number +#define SIO_UART0_DEV 0x15 // SIO UART 0 Controller + // Interface Device Number +#define SIO_UART1_DEV 0x15 // SIO UART 1 Controller + // Interface Device Number +#define SIO_SDIO_DEV 0x17 // SIO SDIO Controller + // Interface Device Number + +//---------------------------------------------------------------------------- +// INTEL PCH PCI Function Number Equates +//---------------------------------------------------------------------------- +#define SB_FUN 0x00 // South Bridge Function Number +#define LPC_FUNC SB_FUN +#define SATA_FUN 0x02 // Serial ATA Controller Function Num. +#define SMBUS_FUN 0x03 // SMBus Controller Function Number. +#define SATA2_FUN 0x05 // Serial ATA Controller Function Num. +#define THERMAL_FUN 0x06 // THERMAL Controller Function Number +#define XHCI_FUN 0x00 // XHCI Controller Function Number +#define EHCI_FUN 0x00 // EHCI Controller 1 Function Number +#define EHCI2_FUN 0x00 // EHCI Controller 1 Function Number +#define HDA_FUN 0x00 // HD Audio Controller Function Num. +#define LAN_FUN 0x00 // Ethernet GBE Controller Function + // Number +#define PCIBR_FUN 0x00 // South Bridge PCI Bus Bridge + // Function Number +#define PCIEBRS_FUN 0x00 // South Bridge PCI Express Bridge 1 + // Function Number +#define SBPCIE_FUNC_0 PCIEBRS_FUN +#define PCIEBRS2_FUN 0x01 // South Bridge PCI Express Bridge 2 + // Function Number +#define PCIEBRS3_FUN 0x02 // South Bridge PCI Express Bridge 3 + // Function Number +#define PCIEBRS4_FUN 0x03 // South Bridge PCI Express Bridge 4 + // Function Number +#define PCIEBRS5_FUN 0x04 // South Bridge PCI Express Bridge 5 + // Function Number +#define PCIEBRS6_FUN 0x05 // South Bridge PCI Express Bridge 6 + // Function Number +#define PCIEBRS7_FUN 0x06 // South Bridge PCI Express Bridge 7 + // Function Number +#define PCIEBRS8_FUN 0x07 // South Bridge PCI Express Bridge 8 + // Function Number +#define HECI_FUN 0x00 // ME HECI Controller + // Interface Function Number +#define ME_FUNC0 HECI_FUN + +#define HECI2_FUN 0x01 // ME HECI 2 Controller + // Interface Function Number +#define ME_FUNC1 HECI2_FUN +#define IDER_FUN 0x02 // ME IDER Controller + // Interface Function Number +#define KT_FUN 0x03 // ME KT Controller + // Interface Function Number + +#define SIO_DMA_FUN 0x00 // SIO DMA Controller + // Interface Function Number +#define SIO_I2C0_FUN 0x01 // SIO I2C 0 Controller + // Interface Function Number +#define SIO_I2C1_FUN 0x02 // SIO I2C 1 Controller + // Interface Function Number +#define SIO_GSPI0_FUN 0x03 // SIO GSPI 0 Controller + // Interface Function Number +#define SIO_GSPI1_FUN 0x04 // SIO GSPI 1 Controller + // Interface Function Number +#define SIO_UART0_FUN 0x05 // SIO UART 0 Controller + // Interface Function Number +#define SIO_UART1_FUN 0x06 // SIO UART 1 Controller + // Interface Device Number +#define SIO_SDIO_FUN 0x00 // SIO SDIO Controller + // Interface Device Number + +//---------------------------------------------------------------------------- +// INTEL PCH PCI Bus/Device/Function/Register Number Macros +//---------------------------------------------------------------------------- +#define SB_REG(Reg) SB_PCI_CFG_ADDRESS(SB_BUS, SB_DEV, \ + SB_FUN, Reg) +#define HECI_REG(Reg) SB_PCI_CFG_ADDRESS(HECI_BUS, HECI_DEV, \ + HECI_FUN, Reg) +#define HECI2_REG(Reg) SB_PCI_CFG_ADDRESS(HECI2_BUS, HECI2_DEV, \ + HECI2_FUN, Reg) +#define IDER_REG(Reg) SB_PCI_CFG_ADDRESS(IDER_BUS, IDER_DEV, \ + IDER_FUN, Reg) +#define KT_REG(Reg) SB_PCI_CFG_ADDRESS(KT_BUS, KT_DEV, \ + KT_FUN, Reg) +#define SB_REG(Reg) SB_PCI_CFG_ADDRESS(SB_BUS, SB_DEV, \ + SB_FUN, Reg) +#define SB_REG(Reg) SB_PCI_CFG_ADDRESS(SB_BUS, SB_DEV, \ + SB_FUN, Reg) +#define XHCI_REG(Reg) SB_PCI_CFG_ADDRESS(XHCI_BUS, XHCI_DEV, \ + XHCI_FUN, Reg) +#define EHCI_REG(Reg) SB_PCI_CFG_ADDRESS(EHCI_BUS, EHCI_DEV, \ + EHCI_FUN, Reg) +#define EHCI2_REG(Reg) SB_PCI_CFG_ADDRESS(EHCI2_BUS, EHCI2_DEV, \ + EHCI2_FUN, Reg) +#define SATA_REG(Reg) SB_PCI_CFG_ADDRESS(SATA_BUS, SATA_DEV, \ + SATA_FUN, Reg) +#define SATA2_REG(Reg) SB_PCI_CFG_ADDRESS(SATA2_BUS, SATA2_DEV, \ + SATA2_FUN, Reg) +#define SMBUS_REG(Reg) SB_PCI_CFG_ADDRESS(SMBUS_BUS, SMBUS_DEV, \ + SMBUS_FUN, Reg) +#define THERMAL_REG(Reg) SB_PCI_CFG_ADDRESS(THERMAL_BUS, THERMAL_DEV, \ + THERMAL_FUN, Reg) +#define HDA_REG(Reg) SB_PCI_CFG_ADDRESS(HDA_BUS, HDA_DEV, \ + HDA_FUN, Reg) +#define LAN_REG(Reg) SB_PCI_CFG_ADDRESS(LAN_BUS, LAN_DEV, \ + LAN_FUN, Reg) +#define PCIBR_REG(Reg) SB_PCI_CFG_ADDRESS(PCIBR_BUS, PCIBR_DEV, \ + PCIBR_FUN, Reg) +#define PCIEBRS_REG(Reg) SB_PCI_CFG_ADDRESS(PCIEBRS_BUS, \ + PCIEBRS_DEV, \ + PCIEBRS_FUN, Reg) +#define PCIEBRS2_REG(Reg) SB_PCI_CFG_ADDRESS(PCIEBRS2_BUS, \ + PCIEBRS2_DEV, \ + PCIEBRS2_FUN, Reg) +#define PCIEBRS3_REG(Reg) SB_PCI_CFG_ADDRESS(PCIEBRS3_BUS, \ + PCIEBRS3_DEV, \ + PCIEBRS3_FUN, Reg) +#define PCIEBRS4_REG(Reg) SB_PCI_CFG_ADDRESS(PCIEBRS4_BUS, \ + PCIEBRS4_DEV, \ + PCIEBRS4_FUN, Reg) +#define PCIEBRS5_REG(Reg) SB_PCI_CFG_ADDRESS(PCIEBRS5_BUS, \ + PCIEBRS5_DEV, \ + PCIEBRS5_FUN, Reg) +#define PCIEBRS6_REG(Reg) SB_PCI_CFG_ADDRESS(PCIEBRS6_BUS, \ + PCIEBRS6_DEV, \ + PCIEBRS6_FUN, Reg) +#define PCIEBRS7_REG(Reg) SB_PCI_CFG_ADDRESS(PCIEBRS7_BUS, \ + PCIEBRS7_DEV, \ + PCIEBRS7_FUN, Reg) +#define PCIEBRS8_REG(Reg) SB_PCI_CFG_ADDRESS(PCIEBRS8_BUS, \ + PCIEBRS8_DEV, \ + PCIEBRS8_FUN, Reg) + +#define SIO_DMA_REG(Reg) SB_PCI_CFG_ADDRESS(SIO_DMA_BUS, \ + SIO_DMA_DEV, \ + SIO_DMA_FUN, Reg) +#define SIO_I2C0_REG(Reg) SB_PCI_CFG_ADDRESS(SIO_I2C0_BUS, \ + SIO_I2C0_DEV, \ + SIO_I2C0_FUN, Reg) +#define SIO_I2C1_REG(Reg) SB_PCI_CFG_ADDRESS(SIO_I2C1_BUS, \ + SIO_I2C1_DEV, \ + SIO_I2C1_FUN, Reg) +#define SIO_GSPI0_REG(Reg) SB_PCI_CFG_ADDRESS(SIO_GSPI0_BUS, \ + SIO_GSPI0_DEV, \ + SIO_GSPI0_FUN, Reg) +#define SIO_GSPI1_REG(Reg) SB_PCI_CFG_ADDRESS(SIO_GSPI1_BUS, \ + SIO_GSPI1_DEV, \ + SIO_GSPI1_FUN, Reg) +#define SIO_UART0_REG(Reg) SB_PCI_CFG_ADDRESS(SIO_UART0_BUS, \ + SIO_UART0_DEV, \ + SIO_UART0_FUN, Reg) +#define SIO_UART1_REG(Reg) SB_PCI_CFG_ADDRESS(SIO_UART1_BUS, \ + SIO_UART1_DEV, \ + SIO_UART1_FUN, Reg) +#define SIO_SDIO_REG(Reg) SB_PCI_CFG_ADDRESS(SIO_SDIO_BUS, \ + SIO_SDIO_DEV, \ + SIO_SDIO_FUN, Reg) + +#ifdef PCIEX_BASE_ADDRESS +#define HECI_PCIE_REG(Reg) SB_PCIE_CFG_ADDRESS(HECI_BUS, HECI_DEV, \ + HECI_FUN, Reg) +#define HECI2_PCIE_REG(Reg) SB_PCIE_CFG_ADDRESS(HECI2_BUS, HECI2_DEV, \ + HECI2_FUN, Reg) +#define SATA_PCIE_REG(Reg) SB_PCIE_CFG_ADDRESS(SATA_BUS, SATA_DEV, \ + SATA_FUN, Reg) +#define SATA2_PCIE_REG(Reg) SB_PCIE_CFG_ADDRESS(SATA2_BUS, SATA2_DEV, \ + SATA2_FUN, Reg) +#endif + + +//---------------------------------------------------------------------------- +// INTEL PCH PCI Bus/Device/Function Number Macros +//---------------------------------------------------------------------------- +#define HECI_BUS_DEV_FUN HECI_REG(0) +#define HECI2_BUS_DEV_FUN HECI2_REG(0) +#define IDER_BUS_DEV_FUN IDER_REG(0) +#define KT_BUS_DEV_FUN KT_REG(0) +#define SB_BUS_DEV_FUN SB_REG(0) +#define XHCI_BUS_DEV_FUN XHCI_REG(0) +#define EHCI_BUS_DEV_FUN EHCI_REG(0) +#define EHCI2_BUS_DEV_FUN EHCI2_REG(0) +#define SATA_BUS_DEV_FUN SATA_REG(0) +#define SATA2_BUS_DEV_FUN SATA2_REG(0) +#define SMBUS_BUS_DEV_FUN SMBUS_REG(0) +#define THERMAL_BUS_DEV_FUN THERMAL_REG(0) +#define HDA_BUS_DEV_FUN HDA_REG(0) +#define LAN_BUS_DEV_FUN LAN_REG(0) +#define PCIBR_BUS_DEV_FUN PCIBR_REG(0) +#define PCIEBRS_BUS_DEV_FUN PCIEBRS_REG(0) +#define PCIEBRS2_BUS_DEV_FUN PCIEBRS2_REG(0) +#define PCIEBRS3_BUS_DEV_FUN PCIEBRS3_REG(0) +#define PCIEBRS4_BUS_DEV_FUN PCIEBRS4_REG(0) +#define PCIEBRS5_BUS_DEV_FUN PCIEBRS5_REG(0) +#define PCIEBRS6_BUS_DEV_FUN PCIEBRS6_REG(0) +#define PCIEBRS7_BUS_DEV_FUN PCIEBRS7_REG(0) +#define PCIEBRS8_BUS_DEV_FUN PCIEBRS8_REG(0) + +#define SIO_DMA_BUS_DEV_FUN SIO_DMA_REG(0) +#define SIO_I2C0_BUS_DEV_FUN SIO_I2C0_REG(0) +#define SIO_I2C1_BUS_DEV_FUN SIO_I2C1_REG(0) +#define SIO_GSPI0_BUS_DEV_FUN SIO_GSPI0_REG(0) +#define SIO_GSPI1_BUS_DEV_FUN SIO_GSPI1_REG(0) +#define SIO_UART0_BUS_DEV_FUN SIO_UART0_REG(0) +#define SIO_UART1_BUS_DEV_FUN SIO_UART1_REG(0) +#define SIO_SDIO_BUS_DEV_FUN SIO_SDIO_REG(0) + +//---------------------------------------------------------------------------- +// INTEL PCH RCRB Equates +//---------------------------------------------------------------------------- +#define R_ICH_HPET_CONFIG 0x3404 +//---------------------------------------------------------------------------- +// INTEL PCH ME HECIx Controller (D22:F0/F1/F2/F3) Equates +//---------------------------------------------------------------------------- +#define ME_REG_VID 0x00 // PCI Vendor ID Register +#define ICH_REG_ME_VID ME_REG_VID +#define ME_REG_PCICMD 0x04 // PCI Command Register +#define ICH_REG_ME_PCICMD ME_REG_PCICMD +#define ME_REG_HECI_MBAR 0x10 // HECI MMIO Base Address Register +#define ICH_REG_ME_HECI0_BAR ME_REG_HECI_MBAR +#define ME_REG_HECI_EXT_BAR 0x14 +#define ICH_REG_ME_HECI0_EXT_BAR ME_REG_HECI_EXT_BAR +#define ME_REG_SVID 0x2c // Sub-Vendor/SubSystem IDs Register +#define ME_REG_HIDM 0xA0 +#define ICH_REG_ME_HIDM ME_REG_HIDM + +//---------------------------------------------------------------------------- +// INTEL PCH LPC Bridge (D31:F0) Equates +//---------------------------------------------------------------------------- +#define ICH_REG_LPC_VID 0x00 +#define SB_REG_PMBASE 0x40 // ACPI Base Address Reg. +#define SB_REG_ACPI_CNTL 0x44 // ACPI Control Reg. +#define SB_REG_GPIOBASE 0x48 // GPIO Base Address Reg. +#define SB_REG_GC 0x4c // GPIO Control Reg. +#define SB_REG_PIRQ_A 0x60 // PCI IRQ Route Control A Reg. +#define SB_REG_PIRQ_B 0x61 // PCI IRQ Route Control B Reg. +#define SB_REG_PIRQ_C 0x62 // PCI IRQ Route Control C Reg. +#define SB_REG_PIRQ_D 0x63 // PCI IRQ Route Control D Reg. +#define SB_REG_SIRQ_CNTL 0x64 // Serial IRQ Control Reg. +#define SB_REG_PIRQ_E 0x68 // PCI IRQ Route Control E Reg. +#define SB_REG_PIRQ_F 0x69 // PCI IRQ Route Control F Reg. +#define SB_REG_PIRQ_G 0x6a // PCI IRQ Route Control G Reg. +#define SB_REG_PIRQ_H 0x6b // PCI IRQ Route Control H Reg. +#define SB_REG_LPC_IO_DEC 0x80 // I/O Decode Ranges Reg. +#define SB_REG_LPC_EN 0x82 // LPC Interface Enables Reg. +#define SB_REG_GEN1_DEC 0x84 // LPC Interface Generic Decode + // Range 1 Reg. +#define SB_REG_GEN2_DEC 0x88 // LPC Interface Generic Decode + // Range 2 Reg. +#define SB_REG_GEN3_DEC 0x8c // LPC Interface Generic Decode + // Range 3 Reg. +#define SB_REG_GEN4_DEC 0x90 // LPC Interface Generic Decode + // Range 4 Reg. +#define SB_REG_GEN_PMCON_1 0xa0 // General Power Management + // Configuration 1 Reg. +#define SB_REG_GEN_PMCON_2 0xa2 // General Power Management + // Configuration 2 Reg. +#define SB_REG_GEN_PMCON_3 0xa4 // General Power Management + // Configuration 3 Reg. +#define SB_REG_LPC_PMIR 0xac // +#define ICH_REG_LPC_PMIR SB_REG_LPC_PMIR +#define B_ICH_LPC_PMIR_CF9GR BIT20 // CF9h Global Reset +#define B_ICH_LPC_PMIR_CF9LOCK BIT31 // CF9h Lockdown +#define SB_REG_GPI_ROUT 0xb8 // GPI Route Control Reg. +#define SB_REG_BIOS_CNTL 0xdc // BIOS Control Reg. +#define SB_REG_RCBA 0xf0 // Root Complex Base Address Reg. +#define ICH_REG_LPC_RCBA SB_REG_RCBA + +//---------------------------------------------------------------------------- +// INTEL PCH Serial ATA Controller (D31:F2/F5) Equates +//---------------------------------------------------------------------------- +#define SATA_REG_DEVID 0x02 // Device ID Reg. +#define SATA_REG_PCICMD 0x04 // Command Register +#define SATA_REG_RID 0x08 // Revision ID Reg. +#define SATA_REG_PCIPI 0x09 // Programming Interface Register +#define SATA_REG_MLT 0x0d // Primary Master Latnecy Timer Reg. +#define SATA_REG_PCMD_BAR 0x10 // Primary Command Block Base Address Register +#define SATA_REG_PCNL_BAR 0x14 // Primary Control Block Base Address Register +#define SATA_REG_SCMD_BAR 0x18 // Secondary Command Block Base Address Register +#define SATA_REG_SCNL_BAR 0x1C // Secondary Control Block Base Address Register +#define SATA_REG_BM_BASE 0x20 // Bus Master Base Address Register +#define SATA_REG_ABAR 0x24 // AHCI Base Address Register +#define SATA_REG_SVID 0x2C // Sub-Vendor/SubSystem IDs register +#define SATA_REG_INTR_LN 0x3C // Interrupt Line Register +#define SATA_REG_IDETIM 0x40 // Primary & Secondary drive timings register +#define SATA_REG_SIDETIM 0x44 // Slave Primary & Secondary drive timings register +#define SATA_REG_SDMACTL 0x48 // Synchronous DMA Control register +#define SATA_REG_SDMATIM 0x4A // Synchronous DMA Timing register +#define SATA_REG_IDE_CONFIG 0x54 // IDE I/O Configuration register +#define SATA_REG_PID 0x70 // PCI Power Management Capability ID register +#define SATA_REG_PC 0x72 // PCI Power Management Capability register +#define SATA_REG_PMCS 0x74 // PCI Power Management Control & Status register +#define SATA_REG_MSICI 0x80 // Message Signaled Interrupt Identifiers register +#define SATA_REG_MSIMC 0x82 // Message Signaled Interrupt Message Control register +#define SATA_REG_MSIMA 0x84 // Message Signaled Interrupt Message Address register +#define SATA_REG_MSIMD 0x88 // Message Signaled Interrupt Message Data register +#define SATA_REG_MAP 0x90 // Address Map register +#define SATA_REG_PCS 0x92 // Port Status & Control register +#define SATA_REG_SIR 0x94 // Initialization register +#define SATA_REG_SIRI 0xA0 // S-ATA Register Index register +#define SATA_REG_STRD 0xA4 // S-ATA Register Data register + +//---------------------------------------------------------------------------- +// INTEL PCH SMBus Controller (D31:F3) Equates +//---------------------------------------------------------------------------- +#define SMBUS_REG_DEVID 0x02 // Device ID Reg. +#define SMBUS_REG_PCICMD 0x04 // PCI Command Register +#define SMBUS_REG_RID 0x08 // Revision Identification Register +#define SMBUS_REG_MBASE0_ADDR 0x10 // SMBus Memory base 0 address register +#define SMBUS_REG_MBASE1_ADDR 0x14 // SMBus Memory base 1 address register +#define SMBUS_REG_BASE_ADDR 0x20 // SMBus I/O base address register +#define SMBUS_REG_SVID 0x2c // SMBus System Vendor ID register +#define SMBUS_REG_INTR_LN 0x3c // Interrupt Line Register +#define SMBUS_REG_HOST_CONFIG 0x40 // SMBUS Host Configuration register + +//---------------------------------------------------------------------------- +// INTEL PCH THERMAL Controller (D31:F6) Equates +//---------------------------------------------------------------------------- +#define THERMAL_REG_PCICMD 0x04 // PCI Command Register +#define THERMAL_REG_TBAR 0x10 // Thermal Memory Base Address Register +#define THERMAL_REG_INTR_LN 0x3c // Interrupt Line Register + +//---------------------------------------------------------------------------- +// INTEL PCH USB 3.0 Controller (D20:F0) Equates +//---------------------------------------------------------------------------- +#define XHCI_REG_VID 0x00 // Vendor ID Reg. +#define XHCI_REG_DEVID 0x02 // Device ID Reg. +#define XHCI_REG_PCICMD 0x04 // PCI Command Register +#define XHCI_REG_RID 0x08 // Revision Identification Register +#define XHCI_REG_SVID 0x2c // USB 3.0 System Vendor ID register + +//---------------------------------------------------------------------------- +// INTEL PCH USB 2.0 Controller (D26/29:F0) Equates +//---------------------------------------------------------------------------- +#define EHCI_REG_VID 0x00 // Vendor ID Reg. +#define EHCI_REG_DEVID 0x02 // Device ID Reg. +#define EHCI_REG_PCICMD 0x04 // PCI Command Register +#define EHCI_REG_RID 0x08 // Revision Identification Register +#define EHCI_REG_MBASE_ADDR 0x10 // USB 2.0 Memory base address register +#define EHCI_REG_SVID 0x2c // USB 2.0 System Vendor ID register +#define EHCI_REG_INTR_LN 0x3c // Interrupt Line Register +#define EHCI_REG_LEG_EXT_CAP 0x68 // USB EHCI Legacy Support Extended + // Capability Register +#define EHCI_REG_LEG_EXT_CS 0x6c // USB EHCI Legacy Support Extended + // Control/Status Register +#define EHCI_REG_SPECIAL_SMI 0x70 // INTEL Specific USB 2.0 SMI register +#define EHCI_REG_IR2 0xfc + +//---------------------------------------------------------------------------- +// INTEL PCH GBE Controller (D25:F0) Equates +//---------------------------------------------------------------------------- +#define LAN_REG_MBARA 0x10 // Memory Base Address Register A +#define LAN_REG_MBARB 0x14 // Memory Base Address Register B +#define LAN_REG_SVID 0x2C // Subsystem Vendor ID register +#define LAN_REG_PMCS 0xCC // PCI Power Management Control and Status + +//---------------------------------------------------------------------------- +// INTEL PCH PCI Express Bridge (D28:F0/1/2/3/4/5) Equates +//---------------------------------------------------------------------------- +#define PCIEBRS_REG_SVID 0x94 // Subsystem Vendor IDs Reg. +#define ICH_REG_PCIE_BNUM 0x018 +#define ICH_REG_PCIE_PCICMD 0x004 +#define ICH_REG_PCIE_SLCAP 0x054 +//---------------------------------------------------------------------------- +// INTEL PCH AZALIA Controller (D27:F0) Equates +//---------------------------------------------------------------------------- +#define HDA_REG_SVID 0x2c // Subsystem Vendor ID Reg. + +//---------------------------------------------------------------------------- +// INTEL PCH PCI Bus P2P Bridge (D30:F0) Equates +//---------------------------------------------------------------------------- +#define PCIBR_REG_PCICMD 0x04 // Command Reg. +#define PCIBR_REG_IOBASE 0x1c // I/O base Reg. +#define PCIBR_REG_PBUSN 0x18 // Primary Bus Number Reg. +#define PCIBR_REG_SBUSN 0x19 // Secondary Bus Number Reg. +#define PCIBR_REG_SUBUSN 0x1a // Subordinate Bus Number Reg. +#define PCIBR_REG_MBASE 0x20 // Memory Base Reg. +#define PCIBR_REG_PMBASE 0x24 // Prefretchable memory Base Reg. +#define PCIBR_REG_PMBASEU 0x28 // Prefretchable memory Base +#define PCIBR_REG_INTR_LN 0x3c // Interrupt Line Reg. +#define PCIBR_REG_SPDH 0x40 // Secondary PCI Device Hiding Register. +#define PCIBR_REG_DTC 0x44 // Delayed Transaction Control Register. +#define PCIBR_REG_BPC 0x4c // Bridge Policy Configuration Register. +#define PCIBR_REG_SVID 0x54 // Subsystem Vendor IDs Reg. + +//---------------------------------------------------------------------------- +// INTEL PCH RCRB Mmemory Mapped I/O Registers +//---------------------------------------------------------------------------- +#define RCRB_MMIO_TRSR 0x1e00 // Trap Status Register +#define RCRB_MMIO_TRCR 0x1e10 // Trapped Cycle Register +#define RCRB_MMIO_TWDR 0x1e18 // Trap Write Data Register +#define RCRB_MMIO_IO_TRAP_0 0x1e80 // Trap Configuration Register 0 +#define RCRB_MMIO_IO_TRAP_1 0x1e88 // Trap Configuration Register 1 +#define RCRB_MMIO_IO_TRAP_2 0x1e90 // Trap Configuration Register 2 +#define RCRB_MMIO_IO_TRAP_3 0x1e98 // Trap Configuration Register 3 +#define ICH_RCRB_PRSTS 0x3310 // Power and Reset Srtatus Register +#define ICH_RCRB_PMCFG 0x3318 // Power Management Configuration Register +#define RCRB_MMIO_HPTC 0x3404 // High Precision Timer Configuration + // Register +#define RCRB_MMIO_GCS 0x3410 // General Control and Status Register +#define RCRB_MMIO_BUC 0x3414 // Backed Up Control Register +#define RCRB_MMIO_FD 0x3418 // Function Disable Register +#define ICH_RCRB_FD2 0x3428 // Function Disable Register 2 +#define RCRB_MMIO_RMHWKCTL 0x35B0 // Rate Matching Hub Wake Control Register + + +//---------------------------------------------------------------------------- +// INTEL PCH ACPI Power Management I/O Registers +//---------------------------------------------------------------------------- +#define ACPI_IOREG_PM1_STS 0x00 // Power Management 1 Status Reg. +#define ACPI_IOREG_PM1_EN 0x02 // Power Management 1 Enables Reg. +#define ACPI_IOREG_PM1_CNTL 0x04 // Power Management 1 Control Reg. +#define ACPI_IOREG_PM1_TMR 0x08 // Power Management 1 Timer Reg. +#define ACPI_IOREG_PROC_CNTL 0x10 // Processor Control Reg. + +#define ACPI_PCHLP_IOREG_GPE0_STS 0x80 // General Purpose Event 0 Status Reg for PchLp. +#define ACPI_PCHLP_IOREG_GPE0_EN 0x90 // General Purpose Event 0 Enable Reg for PchLp. +#define ACPI_IOREG_GPE0_STS 0x20 // General Purpose Event 0 Status Reg. +#define ACPI_IOREG_GPE0_EN 0x28 // General Purpose Event 0 Enable Reg. + + +#define ICH_LP_IOREG_GPE0_STS ACPI_PCHLP_IOREG_GPE0_STS + 0x0c +#define ICH_LP_IOREG_GPE0_EN ACPI_PCHLP_IOREG_GPE0_EN + 0x0c + +#define ICH_IOREG_GPE0_STS ACPI_IOREG_GPE0_STS +#define ICH_IOREG_GPE0_EN ACPI_IOREG_GPE0_EN + + +#define ACPI_IOREG_SMI_EN 0x30 // SMI Control and Enable Reg. +#define ICH_IOREG_SMI_EN ACPI_IOREG_SMI_EN +#define ACPI_IOREG_SMI_STS 0x34 // SMI status Reg. +#define ICH_IOREG_SMI_STS ACPI_IOREG_SMI_STS + +#define ACPI_IOREG_ALTGP_SMI_EN 0x38 // Alternate GPI SMI Enable Reg. +#define ACPI_IOREG_ALTGP_SMI_STS 0x3a // Alternate GPI SMI Status Reg. +#define ACPI_IOREG_UPRWC 0x3c // USB Per-Port Regs Write Control. +#define ACPI_IOREG_GPE_CNTL 0x42 // General Purpose Event Control Reg. +#define ACPI_IOREG_DEVACT_STS 0x44 // Device Activity Status Reg. +#define ACPI_IOREG_PM2_CNTL 0x50 // Power Management 2 Control Reg. + +//---------------------------------------------------------------------------- +// INTEL PCH System Management TCO I/O Registers +//---------------------------------------------------------------------------- +#define TCO_IOREG_RLD 0x00 // TCO Timer Reload and Current Value +#define TCO_IOREG_DAT_IN 0x02 // TCO Data In Reg. +#define TCO_IOREG_DAT_OUT 0x03 // TCO Data Out Reg. +#define TCO_IOREG_STS1 0x04 // TCO Status 1 Reg. +#define ICH_IOREG_TCO1_STS TCO_IOREG_STS1 +#define TCO_IOREG_STS2 0x06 // TCO Status 2 Reg. +#define TCO_IOREG_CNT1 0x08 // TCO Control 1 Reg. +#define TCO_IOREG_CNT2 0x0a // TCO Control 2 Reg. +#define TCO_IOREG_MESSAGE1 0x0c // TCO Message 1 Reg. +#define TCO_IOREG_MESSAGE2 0x0d // TCO Message 2 Reg. +#define TCO_IOREG_WDCNT 0x0e // TCO Watchdog Control Reg. +#define TCO_IOREG_SWIRQ_GEN 0x10 // Software IRQ Generation Reg. +#define TCO_IOREG_TMR 0x12 // TCO Timer Initial Value Reg + +//---------------------------------------------------------------------------- +// INTEL PCH System Management Bus I/O Space Equates +//---------------------------------------------------------------------------- +#define SMB_IOREG_HST_STS 0x00 // Host Status Reg. +#define HST_STS_HOST_BUSY 0x01 // R/WC +#define HST_STS_INTR 0x02 // R/WC +#define HST_STS_DEV_ERR 0x04 // R/WC +#define HST_STS_BUS_ERR 0x08 // R/WC +#define HST_STS_FAILED 0x10 // R/WC +#define HST_STS_SMBALERT_STS 0x20 // R/WC +#define HST_STS_INUSE_STS 0x40 // R/WC +#define HST_STS_BDS 0x80 // R/WC +#define HST_STS_ALL 0xff // R/WC +#define HST_STS_ERROR 0x1c // R/WC +#define SMB_IOREG_HST_CNT 0x02 // Host Control Reg. +#define HST_CNT_INTREN 0x01 // RW +#define HST_CNT_KILL 0x02 // RW +#define HST_CNT_SMB_CMD 0x1C // RW +#define SMB_CMD_BYTE 0x04 +#define SMB_CMD_BYTE_DATA 0x08 +#define SMB_CMD_WORD_DATA 0x0c +#define SMB_CMD_BLOCK 0x14 +#define HST_CNT_LAST_BYTE 0x20 // RW +#define HST_CNT_START 0x40 // RW +#define HST_CNT_PEC_EN 0x80 // RW +#define SMB_IOREG_HST_CMD 0x03 // Host Command Reg. +#define SMB_IOREG_XMIT_SLVA 0x04 // Transmit Slave Address Reg. +#define XMIT_SLVA_RW 0x01 // RW +#define SMB_IOREG_HST_D0 0x05 // Host Data 0 +#define SMB_IOREG_HST_D1 0x06 // Host Data 1 +#define SMB_IOREG_HOST_BLOCK_DB 0x07 // Host Block Data Byte Reg. +#define SMB_IOREG_PEC 0x08 // Packet Error Check Reg. +#define SMB_IOREG_RCV_SLVA 0x09 // Receive Slave Address Reg. +#define SMB_IOREG_SLV_DATA0 0x0a // Receive Slave Data 0 Reg. +#define SMB_IOREG_SLV_DATA1 0x0b // Receive Slave Data 1 Reg. +#define SMB_IOREG_AUX_STS 0x0c // Auxiliary Status Reg. +#define AUX_STS_CRC_ERR 0x01 // R/WC +#define AUX_STS_STCO 0x02 // RO +#define SMB_IOREG_AUX_CTL 0x0d // Auxiliary Control Reg. +#define AUX_CTL_AAC 0x01 // R/W +#define AUX_CTL_E32B 0x02 // R/W +#define SMB_IOREG_SMLINK_PIN_CTL 0x0e // SMLink Pin Control Reg. +#define SMB_IOREG_SMBUS_PIN_CTL 0x0f // SMBus Pin Control Reg. +#define SMB_IOREG_SLV_STS 0x10 // Slave Status Reg. +#define SMB_IOREG_SLV_CMD 0x11 // Slave Command Reg. +#define SMB_IOREG_NOTIFY_DADDR 0x14 // Notify Device Address Reg. +#define SMB_IOREG_NOTIFY_DLOW 0x16 // Notify Data Low Reg. +#define SMB_IOREG_NOTIFY_DHIGH 0x17 // Notify Data High Reg. + +#define SMBUS_NUM_RESERVED 21 // Number of device addresses + // that are reserved by the + // SMBus spec. + +#define SMBUS_DEVICE_DEFAULT_ADDRESS 0xc2 >> 1 +#define PREPARE_TO_ARP 0x01 +#define GET_UDID_DIRECTED 0x01 +#define RESET_DEVICE_GENERAL 0x02 +#define GET_UDID_GENERAL 0x03 +#define ASSIGN_ADDRESS 0x04 +#define GET_UDID_DATA_LENGTH 0x11 // 16 byte UDID + 1 byte address + +//---------------------------------------------------------------------------- +// INTEL PCH GP I/O Register Equates +//---------------------------------------------------------------------------- +#define GP_IOREG_GP_OWN1 0x00 // GPIO determines the appropriate status for PchLp +#define GP_IOREG_GP_OWN2 0x04 // GPIO determines the appropriate status for PchLp +#define GP_IOREG_GP_OWN3 0x08 // GPIO determines the appropriate status for PchLp +#define GPI_IRQ_2_IOAPIC 0x10 // enables the corresponding GPIO PIRQ[X:I] pin to generate IOxAPIC interrupt for PchLp +#define GP_IOREG_GPI_ROUT 0x30 // GPI Route Control Reg for PchLp +#define GP_IOREG_GPI_ROUT2 0x34 // GPI Route Control Reg for PchLp +#define GP_IOREG_GPI_ROUT3 0x38 // GPI Route Control Reg for PchLp +#define GP_IOREG_USE_SEL 0x00 // GPIO Use Select register +#define GP_IOREG_IO_SEL 0x04 // GPIO Input/Output select +#define GP_IOREG_GP_LVL 0x0c // GPIO Level for Input/Ouput +#define GP_IOREG_GPI_INV 0x2c // GPI Invert register +#define GP_IOREG_USE_SEL2 0x30 // GPIO Use Select 2 register +#define GP_IOREG_IO_SEL2 0x34 // GPIO Input/Output select 2 +#define GP_IOREG_GP_LVL2 0x38 // GPIO Level 2 for Input/Ouput +#define GP_IOREG_USE_SEL3 0x40 // GPIO Use Select 3 register +#define GP_IOREG_IO_SEL3 0x44 // GPIO Input/Output select 3 +#define GP_IOREG_GP_LVL3 0x48 // GPIO Level 3 for Input/Ouput + +#define GP_IOREG_GPO_BLINK 0x18 // GPIO Blink Register +#define GP_IOREG_GP_SER_BLINK 0x1c // GP Serial Blink Register +#define GP_IOREG_GP_SB_CMDTST 0x20 // GP Serial Blink Command Status Reg. +#define GP_IOREG_GP_SB_DATA 0x24 // GP Serial Blink Data Register +#define GP_IOREG_GPI_NMI_EN 0x28 // GPI NMI Enable Register +#define GP_IOREG_GPI_NMI_STS 0x2a // GPI NMI Status Register + +#define GP_IOREG_GP_RST_SEL1 0x60 // GPIO Reset Select 1 register +#define GP_IOREG_GP_RST_SEL2 0x64 // GPIO Reset Select 2 register +#define GP_IOREG_GP_RST_SEL3 0x68 // GPIO Reset Select 3 register + +#define GP_IOREG_PCHLP_GPI_NMI_EN GP_IOREG_GPI_NMI_EN // GPI NMI Enable Reg for PchLp. +#define GP_IOREG_PCHLP_GPI_NMI_STS GP_IOREG_GPI_NMI_STS // GPI NMI Status Reg for PchLp. +#define GP_IOREG_ALTGP_SMI_STS 0x50 // Alternate GPI SMI Status Reg for PchLp. +#define GP_IOREG_ALTGP_SMI_EN 0x54 // Alternate GPI SMI Enable Reg for PchLp. + +#define GP_IOREG_GP_INT_SEL1 0x90 // GPIO Interrupt Select 1 register +#define GP_IOREG_GP_INT_SEL2 0x94 // GPIO Interrupt Select 2 register +#define GP_IOREG_GP_INT_SEL3 0x98 // GPIO Interrupt Select 3 register + +#define GP_IOREG_GP_GPN_CFG1 0x100 // GPIOn Config [31:0] register for PchLp +#define GP_IOREG_GP_GPN_CFG2 0x104 // GPIOn Config [64:32] register for PchLp +#define GP_GPIO_CONFIG_SIZE 0x08 // GPIO Config register size for PchLp + +//---------------------------------------------------------------------------- +// INTEL PCH USB 2.0 Memory Mapped I/O Registers +//---------------------------------------------------------------------------- + +//---------------------------------------------------------------------------- +// INTEL PCH HD Audio Memory Mapped I/O Registers +//---------------------------------------------------------------------------- + +//---------------------------------------------------------------------------- +// INTEL PCH SPI Registers (Porting Required) +//---------------------------------------------------------------------------- +#define R_SB_RCRB_SPI_BFPR 0x00 // BIOS Flash Primary Region Register(32bits), which is RO and contains the same value from FREG1 +#define B_SB_SPI_BFPR_PRL 0x7FFF0000 // BIOS Flash Primary Region Limit mask +#define B_SB_SPI_BFPR_PRB 0x00007FFF // BIOS Flash Primary Region Base mask +#define R_RCRB_SPI_FADDR 0x08 // Flash Address Register +#define R_RCRB_SPI_FDATA0 0x10 // Flash Data 0 Register +#define R_RCRB_SPI_FDOC 0xB0 // Flash Descriptor Observability Control Register +#define R_RCRB_SPI_FDOD 0xB4 // Flash Descriptor Observability Data Register +#define R_SB_RCRB_SPI_FREG0_FLASHD 0x54 // Flash Region 0(Flash Descriptor)(32bits) +#define R_SB_RCRB_SPI_FREG1_BIOS 0x58 // Flash Region 1(BIOS)(32bits) +#define R_SB_RCRB_SPI_FREG2_ME 0x5C // Flash Region 2(ME)(32bits) +#define R_SB_RCRB_SPI_FREG3_GBE 0x60 // Flash Region 3(GbE)(32bits) +#define R_SB_RCRB_SPI_FREG4_PLATFORM_DATA 0x64 // Flash Region 4(Platform Data)(32bits) +#define S_SB_SPI_FREGX 4 // Size of Flash Region register +#define B_SB_SPI_FREGX_LIMIT_MASK 0x7FFF0000 // Size, [30:16] here represents limit[26:12] +#define B_SB_SPI_FREGX_BASE_MASK 0x00007FFF // Base, [14:0] here represents base [26:12] +#define R_SB_RCRB_SPI_PR0 0x74 // Protected Region 0 Register +#define R_SB_RCRB_SPI_PR1 0x78 // Protected Region 1 Register +#define R_SB_RCRB_SPI_PR2 0x7C // Protected Region 2 Register +#define R_SB_RCRB_SPI_PR3 0x80 // Protected Region 3 Register +#define R_SB_RCRB_SPI_PR4 0x84 // Protected Region 4 Register +#define B_SB_SPI_PRx_WPE BIT31 // Write Protection Enable +#define B_SB_SPI_PRx_RPE BIT15 // Read Protection Enable +#define R_RCRB_SPI_SSFSTS 0x90 // Software Squencing Flash Status +#define R_RCRB_SPI_SSFCTL 0x91 // Software Squencing Flash Control +#define R_RCRB_SPI_PREOP 0x94 // Prefix Opcode Configuration +#define R_RCRB_SPI_OPTYPE 0x96 // Opcode Type Configuration +#define R_RCRB_SPI_OPMENU 0x98 // Opcode Menu Configuration +#define R_RCRB_SPI_LVSCC 0xC4 // Host Lower Vendor Specific Component Capabilities Register +#define R_RCRB_SPI_UVSCC 0xC8 // Host Upper Vendor Specific Component Capabilities Register + +#define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descritor Section Select +#define V_PCH_SPI_FDOC_FDSS_PCHS 0x4000 // ICH soft straps +#define B_PCH_SPI_FDOC_FDSI_MASK 0x0FFC // Flash Descriptor Section Index +#define R_PCH_SPI_STRP15 0x3C + +//---------------------------------------------------------------------------- +// INTEL PCH Legacy Power Management I/O Registers +//---------------------------------------------------------------------------- +#define ICH_IOREG_APMC 0xb2 // APM Control I/O Address +#define ICH_IOREG_APMS 0xb3 // APM Status I/O Address + +//---------------------------------------------------------------------------- +// INTEL PCH Misc. I/O Registers +//---------------------------------------------------------------------------- +#define KBC_IO_DATA 0x60 // Keyboard Controller Data Port +#define PORTB_IO_CNTL 0x61 // Port B control Register +#define KBC_IO_STS 0x64 // Keyboard Controller Status Port +#define CMOS_IO_EXT_INDEX 0x72 // CMOS I/O Extended Index Port +#define CMOS_IO_EXT_DATA 0x73 // CMOS I/O Extended Data Port +#define CMOS_IO_INDEX_BACKDOOR 0x74 // RTC I/O Index Port (Back Door) +#define CMOS_IO_DATA_BACKDOOR 0x75 // RTC I/O Data Port (Back Door) +#define RESET_PORT 0x0CF9 +#define COLD_RESET 0x02 // Set bit 1 for cold reset. +#define RST_CPU 0x04 // Setting this bit triggers a + // reset of the CPU. +#define FULL_RESET 0x08 // Set bit 3 for full reset. +#define IO_DELAY_PORT 0xed // Use for I/O delay + +//---------------------------------------------------------------------------- +// INTEL PCH Internal Device Interrupt Pin Definition +//---------------------------------------------------------------------------- + +#define RCRB_IRQ0 0x00 // No Interrupt +#define RCRB_IRQA 0x01 // INTA# +#define RCRB_IRQB 0x02 // INTB# +#define RCRB_IRQC 0x03 // INTC# +#define RCRB_IRQD 0x04 // INTD# +#define RCRB_PIRQA 0x00 // PIRQA# +#define RCRB_PIRQB 0x01 // PIRQB# +#define RCRB_PIRQC 0x02 // PIRQC# +#define RCRB_PIRQD 0x03 // PIRQD# +#define RCRB_PIRQE 0x04 // PIRQE# +#define RCRB_PIRQF 0x05 // PIRQF# +#define RCRB_PIRQG 0x06 // PIRQG# +#define RCRB_PIRQH 0x07 // PIRQH# + + +#define ONE_SECOND 1000000 // The stall PPI is defined in + // microseconds, this should be + // one second in microseconds. +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2013, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/SB.mak b/Board/SB/SB.mak new file mode 100644 index 0000000..1baed5e --- /dev/null +++ b/Board/SB/SB.mak @@ -0,0 +1,366 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SB.mak 13 8/22/13 3:01a Barretlin $ +# +# $Revision: 13 $ +# +# $Date: 8/22/13 3:01a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SB.mak $ +# +# 13 8/22/13 3:01a Barretlin +# [TAG] EIP N/A +# [Category] Improvement +# [Description] make sure CRB without SIO solution only for SharkBay +# MB/ULT CRB +# [Files] SB.sdl SB.mak +# +# 12 7/30/13 3:05a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Support CRB without Super IO. +# [Files] SB.sdl, SB.mak +# +# 11 5/28/13 11:33p Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Change IASL compiler path. +# [Files] SB.mak +# +# 10 1/10/13 8:18a Scottyang +# [TAG] EIP111666 +# [Category] New Feature +# [Description] Support OEM reset callback function Elink. +# [Files] SB.mak, SBCspLib.h, SBGeneric.c, SB.sdl, PchReset.c +# +# 9 12/18/12 6:38a Scottyang +# [TAG] EIP109697 +# [Category] Improvement +# [Description] Update PCH RC 0.8.1 +# [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, SB.sd, +# SbSetupData.c, GetSetupDate.c +# +# 8 11/20/12 9:52p Scottyang +# [TAG] None +# [Category] Improvement +# +# [Description] Change ASL build path by token. +# +# [Files] SB.sdl, SB.mak +# +# 7 11/19/12 3:55a Scottyang +# [TAG] EIP106353 +# [Category] Bug Fix +# [Severity] Critical +# [Symptom] The system has assert error when PFAT is Disabled and Debug +# Mode is Enabled. +# [RootCause] Use build time PFAT flag that make some code not run whrn +# PFAT disable. +# [Solution] Detect PFAT flag useing MSR. +# [Files] SBGeneric, SB.mak +# +# 6 10/23/12 3:11a Scottyang +# [TAG] EIP84560 +# [Category] Bug Fix +# [Symptom] Can't enter Win8 after Win8 AHCI driver version:11.5.0.1122 +# install. +# [Solution] fixed in EIP84560 +# [Files] sb.sdl, sb.mak, sata.asl +# +# 5 9/26/12 3:48a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Update from EIP#95440 to resolve the RAID driver +# compatibility issue. +# [Files] SB.mak, SB.sdl, SBDXE.c +# +# 4 9/12/12 5:10a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Support OEM update VSCC table. +# [Files] SB.H, SB.mak, SB.sdl, SBDXE.c +# +# 3 7/27/12 6:03a Victortu +# Update to support ULT Platform. +# +# 2 6/13/12 11:33p Victortu +# [TAG] None +# [Category] Improvement +# [Description] Implement Warm Boot function for Secure Flash feature. +# [Files] SB.H, SB.mak, SB.sdl, SBDxe.c, SBGeneric.c, SBPEI.c, +# SBSMI.c +# +# 1 2/08/12 8:22a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SB.mak +# +# Description: This make file builds South bridge SEC,PEI & DXE +# components and link them to respective binary +# +#<AMI_FHDR_END> +#************************************************************************* + +all : SBPEI SBDXE SBRun SBCSPLibBin SBSATAIDE + +BUILD_SB_BOARD_DIR = $(BUILD_DIR)\$(SB_BOARD_DIR) +BUILD_SB_CHIPSET_DIR = $(BUILD_DIR)\$(SB_CHIPSET_DIR) + +CFLAGS = $(CFLAGS) /I$(SB_BOARD_DIR) /I$(SB_CHIPSET_DIR) + +#---------------------------------------------------------------------------- +# Generic SB dependencies +#---------------------------------------------------------------------------- +$(BUILD_DIR)\SB.mak : $(SB_BOARD_DIR)\SBBoard.cif $(SB_CHIPSET_DIR)\SBCSP.cif $(BUILD_RULES) + $(CIF2MAK) $(SB_BOARD_DIR)\SBBoard.cif $(CIF2MAK_DEFAULTS) $(SB_CHIPSET_DIR)\SBCSP.cif + +#---------------------------------------------------------------------------- +# Add files into CSP Library +#---------------------------------------------------------------------------- + +$(BUILD_DIR)\AMICSPLIBInc.H : $(SB_BOARD_DIR)\sb.h $(SB_CHIPSET_DIR)\SBCspLib.h $(SB_BOARD_DIR)\SbSetupData.h +AMICSPLibBin : $(SBCSPLib) + +SB_CSP_OBJECTS =\ +$$(BUILD_DIR)\$(SB_CHIPSET_DIR)\SBGeneric.obj \ +$$(BUILD_DIR)\$(SB_BOARD_DIR)\GetSetupData.obj +SB_RUN_LISTS = \ +/D\"SB_RUN_RESET_CALLBACK_LIST=$(SbRuntimeResetElinkList)\" + +$(SBCSPLib) : $(BUILD_DIR)\SB.mak SBCSPLibBin + +SBCSPLibBin : + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\Sb.mak all\ + NAME=AMISBCSPLib\ + MAKEFILE=$(BUILD_DIR)\Sb.mak\ + OBJECTS="$(SB_CSP_OBJECTS)"\ + TYPE=LIBRARY\ + "MY_INCLUDES=$(INTEL_PCH_INCLUDES) $(PROJECT_CPU_INCLUDES)" \ + "CFLAGS=$(CFLAGS) $(SB_RUN_LISTS) /D\"SB_OEM_SETUP_CALLBACK_LIST=$(SbConfigurationList)\" /D\"SB_OEM_S3_WARMRESET_CALLBACK_LIST=$(SbS3WarmResetLink)\"" + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\Sb.mak all\ + BUILD_DIR=$(BUILD_DIR)\IA32\ + NAME=AMISBCSPLib\ + MAKEFILE=$(BUILD_DIR)\Sb.mak\ + OBJECTS="$(SB_CSP_OBJECTS)"\ + TYPE=PEI_LIBRARY\ + "MY_INCLUDES=$(INTEL_PCH_INCLUDES) $(PROJECT_CPU_INCLUDES)" \ + "CFLAGS=$(CFLAGS) $(SB_RUN_LISTS) /D\"SB_OEM_SETUP_CALLBACK_LIST=$(SbConfigurationList)\" /D\"SB_OEM_S3_WARMRESET_CALLBACK_LIST=$(SbS3WarmResetLink)\"" + +#---------------------------------------------------------------------------- +# Add files for SB SEC code +#---------------------------------------------------------------------------- +CREATE_SB_SEC : $(BUILD_DIR)\SBSECInit.OBJ + +SB_SEC_ASM_FLAGS = /c /nologo /Sa $(SB_INCLUDES) +!if "$(SEC_CREATE_PE32)" == "1" +SB_SEC_ASM_FLAGS = $(SB_SEC_ASM_FLAGS) /coff +!endif + +$(BUILD_DIR)\SBSECInit.OBJ : $(SB_BOARD_DIR)\SBSECInit.asm + $(ASM) $(SB_SEC_ASM_FLAGS) /I$(SB_BOARD_DIR) /Fo$(BUILD_DIR)\SBSECInit.obj $(SB_BOARD_DIR)\SBSECInit.asm + +#---------------------------------------------------------------------------- +# Create SB PEI Component +#---------------------------------------------------------------------------- +SBPEI : $(BUILD_DIR)\SBGPIO.h $(BUILD_DIR)\SB.mak SBPEIBin + +$(BUILD_DIR)\SBGPIO.h: + copy << $(BUILD_DIR)\sbgpio.bat +@echo off +for /L %%i in (0, 1, 9) do ( + @echo #ifdef GPIO_00%%i>> $(BUILD_DIR)\SBGPIO.h + @echo { %%i, GPIO_00%%i },>> $(BUILD_DIR)\SBGPIO.h + @echo #endif>> $(BUILD_DIR)\SBGPIO.h +) +for /L %%i in (10, 1, 95) do ( + @echo #ifdef GPIO_0%%i>> $(BUILD_DIR)\SBGPIO.h + @echo { %%i, GPIO_0%%i },>> $(BUILD_DIR)\SBGPIO.h + @echo #endif>> $(BUILD_DIR)\SBGPIO.h +) + @echo { 0xFFFF, 0xFFFF }>> $(BUILD_DIR)\SBGPIO.h +<< + $(BUILD_DIR)\sbgpio.bat + +SB_PEI_OBJECTS = $$(BUILD_DIR)\$(SB_BOARD_DIR)\SBPeiBoard.obj \ +$$(BUILD_DIR)\$(SB_BOARD_DIR)\GetSetupData.obj \ +$$(BUILD_DIR)\$(SB_CHIPSET_DIR)\SBPei.obj + +SBPEIBin : $(AMIPEILIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SB.mak all\ + NAME=SBPEI\ + MAKEFILE=$(BUILD_DIR)\SB.mak \ +!IF "$(x64_BUILD)"=="1" + BUILD_DIR=$(BUILD_DIR)\IA32\ +!ELSE + BUILD_DIR=$(BUILD_DIR)\ +!ENDIF + OBJECTS="$(SB_PEI_OBJECTS)" \ + GUID=C1FBD624-27EA-40d1-AA48-94C3DC5C7E0D \ + "CFLAGS=$(CFLAGS) /D\"SB_OEM_SETUP_CALLBACK_LIST=$(SbConfigurationList)\""\ + ENTRY_POINT=SBPEI_Init \ + TYPE=PEIM \ + "MY_INCLUDES=$(INTEL_PCH_INCLUDES) $(ME_INCLUDES)" \ + DEPEX1=$(SB_BOARD_DIR)\SBPEI.DXS DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \ + COMPRESS=0 + +# FILE GUID for SBPEI BIN +#// {C1FBD624-27EA-40d1-AA48-94C3DC5C7E0D} +#DEFINE_GUID(<<name>>, +#0xc1fbd624, 0x27ea, 0x40d1, 0xaa, 0x48, 0x94, 0xc3, 0xdc, 0x5c, 0x7e, 0xd); + +#---------------------------------------------------------------------------- +# Create SB DXE Component +#---------------------------------------------------------------------------- +SBDXE : $(BUILD_DIR)\SB.MAK SBDXEBin + +#$(BUILD_DIR)\SBDXE.mak : $(SB_BOARD_DIR)\SBBoard.cif $(SB_CHIPSET_DIR)\SBCSP.cif $(BUILD_RULES) +# $(CIF2MAK) $(SB_BOARD_DIR)\SBDXEBoard.cif $(CIF2MAK_DEFAULTS) $(SB_CHIPSET_DIR)\SBDXE.cif + +SB_DXE_OBJECTS = $(BUILD_SB_BOARD_DIR)\SBDxeBoard.obj \ +$(BUILD_SB_BOARD_DIR)\GetSetupData.obj \ +$(BUILD_SB_CHIPSET_DIR)\SBSmm.obj \ +$(BUILD_SB_CHIPSET_DIR)\SBDxe.obj + +SBDXEBin : $(AMICSPLib) $(AMIDXELIB) $(DxeKscLib_LIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SB.mak all\ + NAME=SBDXE\ + MAKEFILE=$(BUILD_DIR)\SB.mak \ + OBJECTS="$(SB_DXE_OBJECTS)" \ + GUID=B7D19491-E55A-470d-8508-85A5DFA41974 \ + ENTRY_POINT=SBDXE_Init \ + "CFLAGS=$(CFLAGS) $(ACPI_PLATFORM_INCLUDES) $(DxeKscLib_INCLUDES) $(INTEL_PCH_INCLUDES) $(ME_INCLUDES) /D\"OEM_HDA_VERB_TABLE=$(OEM_HDA_VERB_TABLE)\" /D\"OEM_HDA_VERB_TABLE_CONTENT=$(OEM_HDA_VERB_TABLE_CONTENT)\" /D\"SAVE_RESTORE_CALLBACK_LIST=$(SbTimerSaveRestoreRegistersCallbacks)\" /D\"SB_OEM_SETUP_CALLBACK_LIST=$(SbConfigurationList)\" /D\"OEM_SPI_VSCC_TABLE=$(OEM_SPI_VSCC_TABLE)\" /D\"BUS_OVERRIDE_GUIDS_FOR_RAID=$(BusOverrideGuidsforUefiRaid)\""\ + TYPE=BS_DRIVER \ + DEPEX1=$(SB_BOARD_DIR)\SBDXE.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1 + +# FILE GUID for SBDXE BIN +#// {B7D19491-E55A-470d-8508-85A5DFA41974} +#DEFINE_GUID(<<name>>, +#0xb7d19491, 0xe55a, 0x470d, 0x85, 0x8, 0x85, 0xa5, 0xdf, 0xa4, 0x19, 0x74); + +#---------------------------------------------------------------------------- +# Create SB Runtime DXE Component +#---------------------------------------------------------------------------- +SBRun : $(BUILD_DIR)\SB.MAK SBRunBin + +SB_RUN_OBJECTS = $(BUILD_SB_CHIPSET_DIR)\SBRun.obj + +SBRunBin : $(AMICSPLib) $(AMIDXELIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\SB.mak all\ + NAME=SBRun\ + MAKEFILE=$(BUILD_DIR)\SB.mak \ + OBJECTS="$(SB_RUN_OBJECTS)" \ + "CFLAGS=$(CFLAGS) /I$(SB_BOARD_DIR)"\ + GUID=E23F86E1-056E-4888-B685-CFCD67C179D4 \ + ENTRY_POINT=SBRun_Init \ + TYPE=RT_DRIVER \ + DEPEX1=$(SB_BOARD_DIR)\SBRun.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1 + +# FILE GUID for SBRun BIN +#// {E23F86E1-056E-4888-B685-CFCD67C179D4} +#DEFINE_GUID(<<name>>, +#0xe23f86e1, 0x56e, 0x4888, 0xb6, 0x85, 0xcf, 0xcd, 0x67, 0xc1, 0x79, 0xd4); + +# "EXT_HEADERS=$(BUILD_DIR)\token.h"\ +#---------------------------------------------------------------------------- +# SB Debugger Initialization +#---------------------------------------------------------------------------- +PEI_SB_DBG_FLAGS = $(CFLAGS) \ +!IF "$(USB_DEBUG_TRANSPORT)" == "1" + /DUSB_DEBUGGER +!ENDIF + +$(BUILD_SB_BOARD_DIR)\SBPeiDebugger.obj : $(PROJECT_DIR)\$(SB_BOARD_DIR)\SBPeiDebugger.c + $(CC) $(PEI_SB_DBG_FLAGS) $(INTEL_PCH_INCLUDES) /Fo$(BUILD_SB_BOARD_DIR)\SBPeiDebugger.obj $(PROJECT_DIR)\$(SB_BOARD_DIR)\SBPeiDebugger.c + +!IF "$(CRB_UART_CONFIG)" == "1" +CORE_PEIBin : $(BUILD_SB_BOARD_DIR)\SBPeiDebugger.obj $(AMICSPLib) +!ENDIF + +PeiDbgPortBin : $(BUILD_SB_BOARD_DIR)\SBPeiDebugger.obj $(AMICSPLib) + +IchEhciDbgBin : $(BUILD_SB_BOARD_DIR)\SBPeiDebugger.obj $(AMICSPLib) + +SBSATAIDE: $(BUILD_DIR)\SBSATAIDE.ffs +#----------------------------------------------------------------------- +# ASL compiler definition +#----------------------------------------------------------------------- +!IF "$(ACPIPLATFORM_ASL_COMPILER)"=="" +!ERROR It is an invalid path, please check your ASL compiler path. +!ENDIF + +IASL = $(ACPIPLATFORM_ASL_COMPILER) +#----------------------------------------------------------------------- + +#----------------------------------------------------------------------- +$(BUILD_DIR)\SATA.aml $(BUILD_DIR)\IDE.aml : $(BUILD_DIR)\SATA.asl $(BUILD_DIR)\IDE.asl + $(SILENT)$(IASL) -p $@ $*.asl + +$(BUILD_DIR)\SATA.sec $(BUILD_DIR)\IDE.sec : $(BUILD_DIR)\SATA.aml $(BUILD_DIR)\IDE.aml + $(GENSECTION) -I $*.aml -O $@ -S EFI_SECTION_RAW + + +$(BUILD_DIR)\SBSATAIDE.ffs: $(BUILD_DIR)\SATA.sec $(BUILD_DIR)\IDE.sec + $(GENFFSFILE) -B $(BUILD_DIR) -V -o $@ -P1 <<$(BUILD_DIR)\SBSATAIDE.pkg + +PACKAGE.INF +[.] +BASE_NAME = SBSATAIDE +FFS_FILEGUID = 22046D50-F390-498c-92E5-5BA4F8E7F8B6 +FFS_FILETYPE = EFI_FV_FILETYPE_FREEFORM +FFS_ATTRIB_CHECKSUM = TRUE + +IMAGE_SCRIPT = +{ + Compress (dummy) { + $(PROJECT_DIR)\$(BUILD_DIR)\SATA.sec + $(PROJECT_DIR)\$(BUILD_DIR)\IDE.sec + } +} +<<KEEP + +#-----------------------------------------------------------------------# +# Process SBSATAIDE asl files +#-----------------------------------------------------------------------# +$(BUILD_DIR)\SATA.asl $(BUILD_DIR)\IDE.asl : $(INTEL_SATA_ASL_FILE) $(INTEL_IDE_ASL_FILE) + $(CP) /I$(SB_CHIPSET_DIR) /FItoken.h /FItokenAsl.h /C $(SB_CHIPSET_DIR)\$(@F) > $@ +# include the token.h if needed to check for SDL flags +# /FItoken.h + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/SB/SB.sdl b/Board/SB/SB.sdl new file mode 100644 index 0000000..9c0fe11 --- /dev/null +++ b/Board/SB/SB.sdl @@ -0,0 +1,5432 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SB.sdl 65 7/21/14 10:45p Mirayang $ +# +# $Revision: 65 $ +# +# $Date: 7/21/14 10:45p $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SB.sdl $ +# +# 65 7/21/14 10:45p Mirayang +# [TAG] EIP176923 +# [Category] Improvement +# [Description] Program BUC.SDO to 1 on normal boot in PCH component. +# +# 64 5/16/14 6:19a Barretlin +# [TAG] EIP167087 +# [Category] Improvement +# [Description] BIOS security improvement on Haswell CRB project +# [Files] SBGeneric.c SBDxe.c SBCspLib.h Sb.sdl Sb.sd Sb.h +# +# 63 3/13/14 11:06a Barretlin +# [TAG] EIP153695 +# [Category] Improvement +# [Description] USB Per port control is not reasonable when +# OEM_USBPREPORT_DISABLE_SUPPORT token is Enabled and USB devices are +# behind hubs +# [Files] Sb.sdl Sb.sd Sb.uni GetSetupData.c SbDxe.c PchUsbCommon.c +# PchRegsUsb.h +# +# 62 11/19/13 7:34a Barretlin +# [TAG] EIP141917 +# [Category] New Feature +# [Description] Support SetTimer() with HPET Timer on Lynx Point +# [Files] SB.sdl SBGeneric.c SBDxe.c SbHpet.h sbProtocal.cif +# SamrtTimer.sdl +# +# 61 10/28/13 2:46a Barretlin +# [TAG] EIP N/A +# [Category] Improvement +# [Description] add programming serial IO device's SSID +# [Files] SB.sdl SB.H +# +# 60 10/06/13 2:27a Barretlin +# [TAG] EIP138340 +# [Category] Improvement +# [Description] SATA drive detection issue in PCH Platform BIOS +# reference code revision 1.6.2 +# [Files] SB.sdl SBPEI.c +# +# 59 9/18/13 1:01a Barretlin +# [TAG] EIP N/A +# [Category] Improvement +# [Description] change default value of PCH_RCRB_OIC_CEN token +# [Files] SB.sdl +# +# 58 9/17/13 2:46p Barretlin +# [TAG] EIP N/A +# [Category] Improvement +# [Description] use token to decide SATA RxEq policy vaule +# [Files] SB.sdl SbPei.c +# +# 57 9/17/13 1:58p Barretlin +# [TAG] EIP N/A +# [Category] Improvement +# [Description] set a token to enable/disable SATA DLAE bit +# [Files] SB.sdl SBDxe.c +# +# 56 9/17/13 8:32a Barretlin +# [TAG] EIP136354 +# [Category] Improvement +# [Description] remove setting RCBA Coprocessor Error Enable bit +# [Files] SB.sdl SbPei.c +# +# 55 8/23/13 3:39a Barretlin +# [TAG] EIP133819 +# [Category] Improvement +# [Description] update for Intel PCH RC 1.6.2.0 +# [Files] SB.sdl SBPEI.c +# +# 54 8/22/13 3:01a Barretlin +# [TAG] EIP N/A +# [Category] Improvement +# [Description] make sure CRB without SIO solution only for SharkBay +# MB/ULT CRB +# [Files] SB.sdl SB.mak +# +# 53 7/30/13 3:05a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Support CRB without Super IO. +# [Files] SB.sdl, SB.mak +# +# 52 7/03/13 8:05a Scottyang +# [TAG] EIP124410 +# [Category] Improvement +# [Description] Implement SMBIOS type 88h for CRID. +# [Files] SBDxe.c, SB.sdl, SB.sd, SBSetup.c, SBSetup.sdl +# +# 51 4/24/13 2:14a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Porting GPI interrupt by LPT-LP EDS 1.5. +# [Files] SB.sdl, SB.H, SBPPI.h, SBPEI.c +# +# 50 4/23/13 4:15a Wesleychen +# [TAG] None +# [Category] Improvement +# [Description] Add token "ONLY_CLEAR_RTC_EN_IN_PEI" for improve +# "EIP120623". +# [Files] AcpiModeEnable.c; SB.SDL; SBPEI.c +# +# 49 4/15/13 10:58p Wesleychen +# [TAG] None +# [Category] Improvement +# [Description] Change the default of SX_NOTIFY_PWRB to 1. +# [Files] SB.SDL +# +# 48 4/09/13 11:42p Wesleychen +# [TAG] EIP120480 +# [Category] Improvement +# [Description] Always disabling PCH platform policy "ExternalObffEn". +# [Files] SB.SDL, SBDXE.c +# +# 47 4/08/13 2:55a Wesleychen +# +# [TAG] EIP118045 +# [Category] Improvement +# [Description] Creat tokens to support Power Button Notify +# for misc events. +# Neew token: "SX_NOTIFY_PWRB" +# [Files] SB.SDL; SB.ASL +# +# 46 4/08/13 2:46a Wesleychen +# [TAG] EIP120159 +# [Category] Improvement +# [Description] Update for Intel PCH LPT RC140. +# Added new tokens: +# 1. "PCH_RESET_CYCLE_DURATION" +# 2. "LEGACY_DMA_DISABLE" +# [Files] SB.SDL; SBDXE.c +# +# 45 4/08/13 2:40a Wesleychen +# [TAG] EIP116939 +# [Category] Bug Fix +# [Severity] Normal +# [Symptom] The available memory size is less than +# 2GB in Windowss 7 32 bit. +# [RootCause] The "SB_TEMP_MMIO_BASE" is too low. +# [Solution] Rearrange "SB_TEMP_MMIO_BASE" to +# 4GB - 16M(ROM) - 64KB (Intel Required). +# [Files] SB.SDL; SBDxe.c +# +# 44 4/02/13 10:30a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Follow Intel BIOS 114.4 GPIO setting at ULT platform. +# [Files] SB.sdl +# SBPEIBoard.c +# +# 42 4/02/13 3:32a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Clear PCIE retrain bit for some device which cannot +# clear this bit. +# [Files] SB.sdl, PchPciExpressHelpersLibrary.c +# +# 41 3/22/13 5:09a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Wireless LAN PHY use SLP_WLAN# pin +# [Files] SB.sdl, SBDxe.c +# +# 40 3/04/13 9:58p Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Add token for PCH policy. +# [Files] SBDxe.c, SB.sdl +# +# 39 2/26/13 1:01a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Follow intel BIOS V112 to change IRQ rout. +# [Files] SB.sdl, SBPEI.c +# +# 38 2/18/13 2:54a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Set PCIE root port function swapping default is +# disable. +# [Files] SB.sd, SB.uni, SB.sdl +# +# 37 1/30/13 12:58a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Update for 4.6.5.3_TBT_002. +# [Files] SB.sd, SB.sdl +# +# 36 1/28/13 4:14a Scottyang +# [TAG] EIP108803 +# [Category] Improvement +# [Description] Disable usb port after setup. +# [Files] SB.sdl, SBDxe.c +# +# 35 1/25/13 7:51a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Use token to set "BIOS Lock", "SMI Lock", BIOS +# Interface Lock", "GPIO Lock" and "RTC RAM Lock". +# [Files] SB.sd, SB.sdl +# +# 34 1/24/13 12:48a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Create GPIO function token for ULT. +# [Files] SB.sdl +# +# 33 1/17/13 3:33a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Correct ULT GPIO's help message +# [Files] SB.sdl +# SBPEIBoard.c +# +# 32 1/11/13 1:52a Scottyang +# [TAG] EIP88358 +# [Category] Improvement +# [Description] Add FORCE_USER_TO_SETUP_IF_CMOS_BAD token +# [Files] SBDex.c, SBPei.c, RTC.h, SB.sdl +# +# 31 1/11/13 12:44a Scottyang +# [TAG] EIP81593 +# [Category] Improvement +# [Description] Added new SDL token "COLD_RESET_WITH_POWER_CYCLE". +# [Files] SB.sdl, SBGeneric.c, PchResetCommon.c, +# PchResetCommonLib.sdl +# +# 30 1/10/13 8:19a Scottyang +# [TAG] EIP111666 +# [Category] New Feature +# [Description] Support OEM reset callback function Elink. +# [Files] SB.mak, SBCspLib.h, SBGeneric.c, SB.sdl, PchReset.c +# +# 29 1/09/13 8:24a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Synchronous GPIO with Intel BIOS V104.2. +# [Files] SB.sdl +# SBPEIBoard.c +# +# 28 11/20/12 9:52p Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Change ASL build path by token. +# [Files] SB.sdl, SB.mak +# +# 27 11/08/12 8:41p Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Change APIC ID to 02. +# [Files] SB.sdl +# +# 26 11/08/12 7:15a Scottyang +# [TAG] None +# [Category] New Feature +# [Description] Add token "PROGRAM_GPIO_TYPE" for select ULT GPIO +# program function(token or array directly). +# [Files] SB.sdl, SBPEIBoard.c +# +# 25 11/06/12 8:03a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Change "SB_TEMP_MMIO_BASE" to "0xDFFF0000" +# [Files] SB.sdl +# +# 23 10/30/12 10:10p Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Update SATA RAID rom to 12.5.0.1710 +# [Files] SataDriver.efi, SataOrom125.bin, SB.sdl +# +# 22 10/25/12 8:17a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Add new device and remove device which no use +# [Files] SBPEI.c, SB.sdl +# +# 21 10/23/12 3:11a Scottyang +# [TAG] EIP84560 +# [Category] Bug Fix +# [Symptom] Can't enter Win8 after Win8 AHCI driver version:11.5.0.1122 +# install. +# [Solution] fixed in EIP84560 +# [Files] sb.sdl, sb.mak, sata.asl +# +# 18 10/16/12 5:01a Scottyang +# [TAG] EIP84720 +# [Category] Improvement +# [Description] Support Hot-Plug in Shark Bay +# [Files] PchRootPort.c, PchPcie.asl, PchPciExpressHelpersLib.mak, +# PchPciExpressHlpersLibrary.c, SB.sdl +# +# 17 10/14/12 6:04a Scottyang +# [TAG] None +# [Category] Improvement +# [Description] Correct LNKA is 16 +# +# 16 10/12/12 4:54a Scottyang +# [TAG] EIP87695 +# [Category] Improvement +# [Description] System should reboot successfully next time if S3 +# resume fail +# [Files] SB.sdl, SBPei.c +# +# 14 10/01/12 5:54a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Create new token "SOLUTION_FOR_EIP95440" for EIP#95440 +# changed. +# [Files] SB.sdl, SBDXE.c +# +# 13 9/26/12 3:49a Victortu +# [TAG] None +# [Category] Improvement +# [Description] If SPI Flash module support VSCC updated, skip +# programming VSCC. +# [Files] SB.sdl, SBDxe.c +# +# [TAG] None +# [Category] Improvement +# [Description] Update from EIP#95440 to resolve the RAID driver +# compatibility issue. +# [Files] SB.mak, SB.sdl, SBDXE.c +# +# [TAG] None +# [Category] Improvement +# [Description] Update for Intel PCH LPT RC070. +# [Files] SB.sdl, SBDXE.c, SBPEI.c, Pch.sdl, SB.sd, SB.uni +# +# [TAG] None +# [Category] Improvement +# [Description] Update for PCH LP GPIO compatible. +# [Files] SB.sdl, SB.H, AcpiModeEnable.c, AcpiModeEnable.sdl, +# SBDxe.c, SBGeneric.c, SBPEI.c, SBSMI.c, SleepSmi.c, +# SmiHandlerPorting.c, SmiHandlerPorting2.c +# +# [TAG] None +# [Category] Improvement +# [Description] Implement ULT platform LPSS and ADSP setup option. +# [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +# SB.sdl +# +# 12 9/12/12 5:11a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Remove useless HdmiVerbTable. +# [Files] SB.sdl, SBCspLib.h, SBDxe.c, SBGeneric.c +# +# [TAG] None +# [Category] Improvement +# [Description] Change "SB_TEMP_IO_BASE" to "0x1200". +# [Files] SB.sdl +# +# [TAG] None +# [Category] Improvement +# [Description] Support OEM update VSCC table. +# [Files] SB.H, SB.mak, SB.sdl, SBDXE.c +# +# [TAG] None +# [Category] Improvement +# [Description] Modify for Thunderbolt support. +# [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +# PciHotPlug.c +# +# [TAG] None +# [Category] Improvement +# [Description] Modify for ULT GPIO changed by PCH LPT-LP EDS 1.0. +# [Files] SB.H, SB.sdl, AcpiModeEnable.c, AcpiModeEnable.sdl, +# SBPEI.c +# +# 11 8/30/12 9:47a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Change "GPIO_BASE_ADDRESS" to "0x1C00". +# [Files] SB.sdl +# +# [TAG] None +# [Category] Improvement +# [Description] Update "GPE0_BLK_ADDRESS" and "GPE0_BLK_LENGTH" for +# RTD3 support. +# [Files] SB.sdl +# +# [TAG] None +# [Category] Improvement +# [Description] Fixed building error when disable all PCI slots. +# [Files] SB.sdl +# +# 10 8/24/12 6:48a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Remove useless SB_SHADOW_CONTROL. +# [Files] SB.sdl, SBCspLib.h, SBGeneric.c +# +# [TAG] None +# [Category] Improvement +# [Description] Update RC_PORT_x for PCIe. +# [Files] SB.sdl, SB.sd, SBDxe.c +# +# [TAG] None +# [Category] Improvement +# [Description] Corrected EHCI_MMIO_BASE_ADDRESS1 to fix system hang at +# 0x71 when AMI_DEBUGGER_SUPPORT. +# [Files] SB.sdl +# +# 9 8/15/12 1:11a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Update "SB_TEMP_MMIO_BASE" and +# "EHCI_MMIO_BASE_ADDRESS". +# [Files] SB.sdl, SBDxe.c, SBPEI.c +# +# 8 8/13/12 10:14a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Remove ThimblePeak 1/2/3. +# [Files] SB.sdl +# +# [TAG] None +# [Category] Improvement +# [Description] Create the token "USB30_OVER_CURRENT_MAPPING_SETTINGS" +# for the policy "Usb30OverCurrentPins". +# [Files] SB.sdl, SBDxe.c +# +# [TAG] None +# [Category] Improvement +# [Description] Changed PM Base Address from 0x400 to 0x1800. +# [Files] SB.sdl +# +# [TAG] None +# [Category] Improvement +# [Description] Update PCH Policy. +# [Files] SB.sdl, SBDxe.c, SBPEI.c +# +# 7 7/27/12 6:02a Victortu +# Update setup items and policies. +# +# 6 7/02/12 10:21a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Updated and modified for PCH RC 0.6.0. +# [Files] SBGeneric.c, SB.sdl, SBCspLib.h, SBDxe.c, SBPEI.c +# +# 5 6/13/12 11:33p Victortu +# [TAG] None +# [Category] Improvement +# [Description] Implement Warm Boot function for Secure Flash feature. +# [Files] SB.H, SB.mak, SB.sdl, SBDxe.c, SBGeneric.c, SBPEI.c, +# SBSMI.c +# +# 4 5/03/12 6:32a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Modify to support Thunderbolt. +# [Files] SB.sd; SB.uni; SB.sdl; SbSetupData.h; PciHotPlug.c +# +# 3 3/22/12 10:22a Victortu +# [TAG] None +# [Category] Improvement +# [Description] Rename SataOpROM. Notice : This SataOrom120.bin file is +# dummy +# [Files] SB.sdl, SataOrom120.bin, sbCSP.CIF +# +# [TAG] None +# [Category] Bug Fix +# [Severity] Normal +# [Symptom] System hang up if enable "DEBUG_MODE" +# [Solution] Set "USB_PORTS_LENGTH" to 0x80 as default +# [Files] SB.sdl +# +# 2 2/20/12 4:21a Yurenlai +# [TAG] None +# [Category] Improvement +# [Description] Fill in a temp value for token "USB_PORTS_LENGTH". +# [Files] SB.sdl +# +# 1 2/08/12 8:22a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* + +IRQLINK + Name = "LNKA" + Reg = 060h + IrqList = 3,4,5,6,10,11,12,14,15 + InterruptType = LevelLow +End + +IRQLINK + Name = "LNKB" + Reg = 061h + IrqList = 3,4,5,6,10,11,12,14,15 + InterruptType = LevelLow +End + +IRQLINK + Name = "LNKC" + Reg = 062h + IrqList = 3,4,5,6,10,11,12,14,15 + InterruptType = LevelLow +End + +IRQLINK + Name = "LNKD" + Reg = 063h + IrqList = 3,4,5,6,10,11,12,14,15 + InterruptType = LevelLow +End + +IRQLINK + Name = "LNKE" + Reg = 068h + IrqList = 3,4,5,6,10,11,12,14,15 + InterruptType = LevelLow +End + +IRQLINK + Name = "LNKF" + Reg = 069h + IrqList = 3,4,5,6,10,11,12,14,15 + InterruptType = LevelLow +End + +IRQLINK + Name = "LNKG" + Reg = 06ah + IrqList = 3,4,5,6,10,11,12,14,15 + InterruptType = LevelLow +End + +IRQLINK + Name = "LNKH" + Reg = 06bh + IrqList = 3,4,5,6,10,11,12,14,15 + InterruptType = LevelLow +End + +PCIDEVICE + Title = "LPC Bridge" + Bus = 00h + Dev = 01fh + Fun = 00h + ASLfile = "$(INTEL_ACPI_ASL_DIR)\Lpcb.ASL" + ASLdeviceName = "LPCB" + IntA = LNKF; 21 + IntB = LNKD; 19 + IntC = LNKC; 18 + IntD = LNKA; 16 + DeviceType = OnBoard + PCIBusSize = 32bit + LPCBridge = Yes + PWRBwake = Yes + ROMMain = No +End + +PCIDEVICE + Title = "SATA #0" + Bus = 00h + Dev = 01fh + Fun = 02h + IntB = LNKD; 19 + DeviceType = OnBoard + PCIBusSize = 32bit + ROMMain = No +End + +PCIDEVICE + Title = "SATA #1" + Bus = 00h + Dev = 01fh + Fun = 05h + IntB = LNKD; 19 + DeviceType = OnBoard + PCIBusSize = 32bit + ROMMain = No +End + +PCIDEVICE + Title = "SATA RAID Controller(Mobile)" + Bus = 00h + Dev = 01fh + Fun = 02h + ROMFile = "Chipset\SB\SataOrom125.bin" + DeviceID = 0282ah + VendorID = 08086h + IntB = LNKD; 19 + DeviceType = OnBoard + PCIBusSize = 32bit + OptionROM = Yes + CompressedROM = Yes + Token = "PCH_SKU" "=" "1" +End + +PCIDEVICE + Title = "SATA RAID Controller(Desktop)" + Bus = 00h + Dev = 01fh + Fun = 02h + ROMFile = "Chipset\SB\SataOrom125.bin" + DeviceID = 02822h + VendorID = 08086h + IntB = LNKD; 19 + DeviceType = OnBoard + PCIBusSize = 32bit + OptionROM = Yes + CompressedROM = Yes + Token = "PCH_SKU" "=" "0" +End + +PCIDEVICE + Title = "SMBus Controller" + Bus = 00h + Dev = 01fh + Fun = 03h + IntC = LNKC; 18 + DeviceType = OnBoard + PCIBusSize = 32bit +End + +PCIDEVICE + Title = "Thermal Controller" + Bus = 00h + Dev = 01fh + Fun = 06h + IntC = LNKC; 18 + DeviceType = OnBoard + PCIBusSize = 32bit +End + +PCIDEVICE + Title = "XHCI Controller" + Bus = 00h + Dev = 014h + Fun = 00h + IntA = LNKA; 16 + DeviceType = OnBoard + PCIBusSize = 32bit +End + +PCIDEVICE + Title = "EHCI #0" + Bus = 00h + Dev = 01dh + Fun = 00h + IntA = LNKH; 23 + DeviceType = OnBoard + PCIBusSize = 32bit +End + +PCIDEVICE + Title = "EHCI #1" + Bus = 00h + Dev = 01ah + Fun = 00h + IntA = LNKA; 16 + DeviceType = OnBoard + PCIBusSize = 32bit +End + +PCIDEVICE + Title = "High Definition Audio" + Bus = 00h + Dev = 01bh + Fun = 00h + IntA = LNKG; 22 + DeviceType = OnBoard + PCIBusSize = PciEx + ROMMain = No +End + +PCIDEVICE + Title = "GbE Controller" + Bus = 00h + Dev = 019h + Fun = 00h + ROMFile = "Chipset\SB\GbE_OR.BIN" + DeviceID = 01502h + VendorID = 08086h + IntA = LNKE; 20 + DeviceType = OnBoard + PCIBusSize = 32bit + OptionROM = Yes + CompressedROM = Yes + LinkDevice = Yes +End + +PCIDEVICE + Title = "ME" + Bus = 00h + Dev = 016h + IntA = LNKA; 16 + IntB = LNKD; 19 + IntC = LNKC; 18 + IntD = LNKB; 17 + DeviceType = OnBoard + PCIBusSize = 32bit + ROMMain = No +End + +PCIDEVICE + Title = "PCIE Root Port #1" + Bus = 00h + Dev = 01ch + Fun = 00h + BridgeBus = 04h + GPEbit = 09h + SleepNum = 04h + ASLfile = "$(PchAcpiTables_DIR)\PchPcie.asl" + ASLdeviceName = "RP01" + IntA = LNKA; 16 + IntB = LNKB; 17 + IntC = LNKC; 18 + IntD = LNKD; 19 + Token = "RC_PORT_0" "=" "1" + DeviceType = OnBoard + PCIBusSize = PciEx + PCIBridge = Yes + ROMMain = No +End + +PCIDEVICE + Title = "PCIE Root Port #2" + Bus = 00h + Dev = 01ch + Fun = 01h + BridgeBus = 05h + GPEbit = 09h + SleepNum = 04h + ASLfile = "$(PchAcpiTables_DIR)\PchPcie.asl" + ASLdeviceName = "RP02" + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_1" "=" "1" + DeviceType = OnBoard + PCIBusSize = PciEx + PCIBridge = Yes +End + +PCIDEVICE + Title = "PCIE Root Port #3" + Bus = 00h + Dev = 01ch + Fun = 02h + BridgeBus = 06h + GPEbit = 09h + SleepNum = 04h + ASLfile = "$(PchAcpiTables_DIR)\PchPcie.asl" + ASLdeviceName = "RP03" + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_2" "=" "1" + DeviceType = OnBoard + PCIBusSize = PciEx + PCIBridge = Yes +End + +PCIDEVICE + Title = "PCIE Root Port #4" + Bus = 00h + Dev = 01ch + Fun = 03h + BridgeBus = 07h + GPEbit = 09h + SleepNum = 04h + ASLfile = "$(PchAcpiTables_DIR)\PchPcie.asl" + ASLdeviceName = "RP04" + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_3" "=" "1" + DeviceType = OnBoard + PCIBusSize = PciEx + PCIBridge = Yes +End + +PCIDEVICE + Title = "PCIE Root Port #5" + Bus = 00h + Dev = 01ch + Fun = 04h + BridgeBus = 08h + GPEbit = 09h + SleepNum = 04h + ASLfile = "$(PchAcpiTables_DIR)\PchPcie.asl" + ASLdeviceName = "RP05" + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_4" "=" "1" + DeviceType = OnBoard + PCIBusSize = PciEx + PCIBridge = Yes +End + +PCIDEVICE + Title = "PCIE Root Port #6" + Bus = 00h + Dev = 01ch + Fun = 05h + BridgeBus = 09h + GPEbit = 09h + SleepNum = 04h + ASLfile = "$(PchAcpiTables_DIR)\PchPcie.asl" + ASLdeviceName = "RP06" + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_5" "=" "1" + DeviceType = OnBoard + PCIBusSize = PciEx + PCIBridge = Yes +End + +PCIDEVICE + Title = "PCIE Root Port #7" + Bus = 00h + Dev = 01ch + Fun = 06h + BridgeBus = 0eh + GPEbit = 09h + SleepNum = 04h + ASLfile = "$(PchAcpiTables_DIR)\PchPcie.asl" + ASLdeviceName = "RP07" + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_6" "=" "1" + DeviceType = OnBoard + PCIBusSize = PciEx + PCIBridge = Yes +End + +PCIDEVICE + Title = "PCIE Root Port #8" + Bus = 00h + Dev = 01ch + Fun = 07h + BridgeBus = 0fh + GPEbit = 09h + SleepNum = 04h + ASLfile = "$(PchAcpiTables_DIR)\PchPcie.asl" + ASLdeviceName = "RP08" + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_7" "=" "1" + DeviceType = OnBoard + PCIBusSize = PciEx + PCIBridge = Yes +End + +PCIDEVICE + Title = "PCIE Port #1 Slot" + Bus = 04h + Dev = 00h + Slot = 021h + IntA = LNKA; 16 + IntB = LNKB; 17 + IntC = LNKC; 18 + IntD = LNKD; 19 + Token = "RC_PORT_0" "=" "1" + DeviceType = Slot + PCIBusSize = PciEx +End + +PCIDEVICE + Title = "PCIE Port #2 Slot" + Bus = 05h + Dev = 00h + Slot = 022h + IntA = LNKB; 17 + IntB = LNKC; 18 + IntC = LNKD; 19 + IntD = LNKA; 16 + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_1" "=" "1" + DeviceType = Slot + PCIBusSize = PciEx +End + +PCIDEVICE + Title = "PCIE Port #3 Slot" + Bus = 06h + Dev = 00h + Slot = 08h + IntA = LNKC; 18 + IntB = LNKD; 19 + IntC = LNKA; 16 + IntD = LNKB; 17 + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_2" "=" "1" + DeviceType = Slot + PCIBusSize = PciEx +End + +PCIDEVICE + Title = "PCIE Port #4 Slot" + Bus = 07h + Dev = 00h + Slot = 09h + IntA = LNKD; 19 + IntB = LNKA; 16 + IntC = LNKB; 17 + IntD = LNKC; 18 + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_3" "=" "1" + DeviceType = Slot + PCIBusSize = PciEx +End + +PCIDEVICE + Title = "PCIE Port #5 Slot" + Bus = 08h + Dev = 00h + Slot = 0ah + IntA = LNKA; 16 + IntB = LNKB; 17 + IntC = LNKC; 18 + IntD = LNKD; 19 + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_4" "=" "1" + DeviceType = Slot + PCIBusSize = PciEx +End + +PCIDEVICE + Title = "PCIE Port #6 Slot" + Bus = 09h + Dev = 00h + Slot = 010h + IntA = LNKB; 17 + IntB = LNKC; 18 + IntC = LNKD; 19 + IntD = LNKA; 16 + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_5" "=" "1" + DeviceType = Slot + PCIBusSize = PciEx +End + +PCIDEVICE + Title = "PCIE Port #7 Slot" + Bus = 0eh + Dev = 00h + Slot = 011h + IntA = LNKC; 18 + IntB = LNKD; 19 + IntC = LNKA; 16 + IntD = LNKB; 17 + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_6" "=" "1" + DeviceType = Slot + PCIBusSize = PciEx +End + +PCIDEVICE + Title = "PCIE Port #8 Slot" + Bus = 0fh + Dev = 00h + Slot = 012h + IntA = LNKD; 19 + IntB = LNKA; 16 + IntC = LNKB; 17 + IntD = LNKC; 18 + Token = "RC_PORT_0" "=" "1" + Token = "RC_PORT_7" "=" "1" + DeviceType = Slot + PCIBusSize = PciEx +End + +PCIDEVICE + Title = "DMA Controller" + Bus = 00h + Dev = 015h + Fun = 00h + IntB = LNKE; 20 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +PCIDEVICE + Title = "I2c0" + Bus = 00h + Dev = 015h + Fun = 01h + IntC = LNKF; 21 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +PCIDEVICE + Title = "I2c1" + Bus = 00h + Dev = 015h + Fun = 02h + IntC = LNKF; 21 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +PCIDEVICE + Title = "SPI0" + Bus = 00h + Dev = 015h + Fun = 03h + IntC = LNKF; 21 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +PCIDEVICE + Title = "SPI1" + Bus = 00h + Dev = 015h + Fun = 04h + IntC = LNKF; 21 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +PCIDEVICE + Title = "UART0" + Bus = 00h + Dev = 015h + Fun = 05h + IntD = LNKF; 21 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +PCIDEVICE + Title = "UART1" + Bus = 00h + Dev = 015h + Fun = 06h + IntD = LNKF; 21 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +PCIDEVICE + Title = "SDIO" + Bus = 00h + Dev = 017h + Fun = 00h + IntA = LNKG; 22 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +PCIDEVICE + Title = "Audio DSP" + Bus = 00h + Dev = 013h + Fun = 00h + IntA = LNKH; 23 + DeviceType = OnBoard + PCIBusSize = 32bit + Token = "ULT_SUPPORT" "=" "1" +End + +IOAPIC + Title = "IO APIC" + APICID = 02h + VectorBase = 00h + VectorRange = 017h + AddressBase = 0fec00000h +End + +TOKEN + Name = "SB_SUPPORT" + Value = "1" + Help = "Main switch to enable Template - SouthBridge support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "SB_TEMPLATE_VER" + Value = "0006" + Help = "South Bridge Template Version Number.\ DO NOT CHANGE THIS VALUE" + TokenType = Integer + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SB_DEBUG_MESSAGE" + Value = "1" + Help = "Enables/disables debug message in SB module" + TokenType = Boolean + TargetEQU = Yes + TargetH = Yes + Token = "DEBUG_MODE" "!=" "0" +End + +TOKEN + Name = "SB_RESET_PPI_SUPPORT" + Value = "1" + Help = "Enable this token if reset PPI is from south bridge.\ If not disable this and provide reset functionality from other PEIM." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "COLD_RESET_WITH_POWER_CYCLE" + Value = "0" + Help = "Enable this token for EfiResetCold do full reset.\ If not disable this and provide EfiResetCold do hard reset." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SB_STALL_PPI_SUPPORT" + Value = "1" + Help = "Enable this token if Stall PPI is from south bridge.\ If not disable this and provide reset functionality from other PEIM." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "OEM_UPDATE_VSCC_TABLE_SUPPORT" + Value = "1" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "OEM_UPDATE_VSCC_TABLE_SUPPORT" + Value = "0" + TokenType = Boolean + TargetH = Yes + Token = "SPI_INITIALIZE_WITH_VSCC" "=" "1" +End + +TOKEN + Name = " " + TokenType = Integer +End + +TOKEN + Name = "=============== SB Specific Tokens ==============" + TokenType = Expression +End + +TOKEN + Name = "ENABLE_RTC_ONE_SECOND_WAKEUP" + Value = "0" + Help = "1: Setups RTC 1 second alarm as well." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PERFORM_KBC_RESET" + Value = "0" + Help = "WARNING: When this token is enabled, it might pull down the system boot speed." + TokenType = Boolean + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "HECI_BASE_ADDRESS" + Value = "0xFEDB0000" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "HECI2_BASE_ADDRESS" + Value = "0xFEDC0000" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SMBUS_BASE_ADDRESS" + Value = "0x0580" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SMBS" + Value = "$(SMBUS_BASE_ADDRESS)" + Help = "SMBus I/O Registes Base Address" + TokenType = Integer + TargetASL = Yes + TargetH = Yes +End + +TOKEN + Name = "SMBL" + Value = "0x20" + Help = "SMBus I/O Registes Range" + TokenType = Integer + TargetASL = Yes + TargetH = Yes +End + +TOKEN + Name = "SB_PIRQ_ROUTER_VID" + Value = "0x8086" + Help = "IRQ Router Vendor ID. \PLEASE CHANGE THIS AS PER CHIPSET" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SB_PIRQ_ROUTER_DID" + Value = "0x27B8" + Help = "IRQ Router Device ID. \PLEASE CHANGE THIS AS PER CHIPSET" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SPI_BASE_ADDRESS" + Value = "0x3800" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "PM_BASE_ADDRESS" + Value = "0x1800" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "PBLK" + Value = "$(PM_BASE_ADDRESS) + 10h" + Help = "Boot-starp CPU Control Block register address. Use return value of PM_BASE_ADDRESS with proper offset.\Value can be returned by CPUx_PBLK tokens, x is the Processor index the PBLK is wired to.\Example : $(PM_BASE_ADDRESS) + 10h\" + TokenType = Integer + TargetH = Yes + Lock = Yes + Range = "16-bit IO register" +End + +TOKEN + Name = "PMBS" + Value = "$(PM_BASE_ADDRESS)" + Help = "ASL alias for ACPI I/O base address." + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "PMLN" + Value = "0x100" + Help = "Power Management registers block length" + TokenType = Integer + TargetASL = Yes + TargetH = Yes +End + +TOKEN + Name = "TCO_BASE_ADDRESS" + Value = "$(PM_BASE_ADDRESS) + 60h" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_BASE_ADDRESS" + Value = "0x1C00" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPI_IRQ_2_IOXAPIC" + Value = "0xFFFF" + Help = "Enable the corresponding GPIO PIRQ pin to generate IOxAPIC interrupt for PchLp" + TokenType = Integer + Range = "{0-0xFFFF}" + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "GPBS" + Value = "$(GPIO_BASE_ADDRESS)" + Help = "ASL alias for General Purpose I/O base address." + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "GPLN" + Value = "0x400" + Help = "GP I/O Registes Range" + TokenType = Integer + TargetASL = Yes + TargetH = Yes +End + +TOKEN + Name = "SW_SMI_IO_ADDRESS" + Value = "0xb2" + Help = "PLEASE CHANGE THIS VALUE AS PER PM_BASE_ADDRESS" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SW_SMI_IO_DATA_ADDRESS" + Value = "0xb3" + Help = "PLEASE CHANGE THIS VALUE AS PER PM_BASE_ADDRESS" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SMIP" + Value = "$(SW_SMI_IO_ADDRESS)" + Help = "Token to go to ASL Name Definitions" + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "PCH_SKU" + Value = "1" + Help = "0:Desktop, Workstation\1:Mobile\2:UP Server" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "COUGAR_POINT_SKU" + Value = "$(PCH_SKU)" + Help = "0:Desktop, Workstation\1:Mobile\2:UP Server" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SPI_READ_CONFIG" + Value = "2" + Help = "0:No prefetching, but caching enabled.\1:No prefetching and no caching.\2:Prefetching and Caching enabled." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "HIDE_BIOS_SECURITY_PAGE" + Value = "0" + Help = "Hide Bios security page in the setup." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SMI_LOCK_ENABLE" + Value = "1" + Help = "0:Set the default value to 'Disabled'.\1:Set the default value to 'Enabled'.\B0:D31:F0:A0h[4]" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "BIOS_INTERFACE_LOCKDOWN" + Value = "1" + Help = "0:Set the default value to 'Disabled'.\1:Set the default value to 'Enabled'.\BLE, RCBA + 3410h[0]" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "GPIO_LOCKDOWN_ENABLE" + Value = "0" + Help = "0:Set the default value to 'Disabled'.\1:Set the default value to 'Enabled'.\GLE, B0:D31:F0:4Ch[0]" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "BIOS_LOCK_ENABLE" + Value = "1" + Help = "0:Set the default value to 'Disabled'.\1:Set the default value to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "RTC_LOCK_ENABLE" + Value = "0" + Help = "0:Set the default value to 'Disabled'.\1:Set the default value to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "ROOT_PORT_FUN_SWAP_ENABLE" + Value = "0" + Help = "0:Set the default value to 'Disabled'.\1:Set the default value to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "DEFAULT_CRID_ENABLE" + Value = "0" + Help = "1:Enable CRID feature/0:Disable CRID feature" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "PCH_PWR_OPT_DMI" + Value = "1" + Help = "0:Set the function to 'Disabled'.\1:Set the function to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_PWR_OPT_GBE" + Value = "1" + Help = "0:Set the function to 'Disabled'.\1:Set the function to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_PWR_OPT_XHCI" + Value = "0" + Help = "0:Set the function to 'Disabled'.\1:Set the function to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_PWR_OPT_EHCI" + Value = "0" + Help = "0:Set the function to 'Disabled'.\1:Set the function to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_PWR_OPT_SATA" + Value = "1" + Help = "0:Set the function to 'Disabled'.\1:Set the function to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "MEM_CLOSE_STATE_EN" + Value = "1" + Help = "0:Set the function to 'Disabled'.\1:Set the function to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "INTERNAL_OBFF_EN" + Value = "1" + Help = "0:Set the function to 'Disabled'.\1:Set the function to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "NUM_OF_DEVLTR_OVERRID" + Value = "0" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "DEVLTR_OVERRID" + Value = "0" + Help = "0:Set the function to 'Disabled'.\1:Set the function to 'Enabled'." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "LEGACY_DMA_DISABLE" + Value = "0" + Help = "0:Legacy DMA is enable.\1:Legacy DMA is disable.\Supported in PCH RC v1.4.0." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "USB_PORTS_LENGTH" + Value = "0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80" + Help = "0x33 = 3.3 inch, 0x146 = 14.6 inch ...." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "USB_OVER_CURRENT_MAPPING_SETTINGS" + Value = "0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "ULT_USB_OVER_CURRENT_MAPPING_SETTINGS" + Value = "0, 0, 8, 8, 2, 2, 1, 1" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "USB30_OVER_CURRENT_MAPPING_SETTINGS" + Value = "0, 0, 1, 1, 2, 2" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "USB_PORT_LOCATION_CONFIG" + Value = "1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1" + Help = "BIT0 = Port0; BIT1 = Port1 ... ; BIT13 = Port13\0:BackPanel\1:FrontPanel\2:Dock\3:MiniPciE\4:Flex\5:InternalTopology\6:Skip\7:Max" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "EHCI_CON_DISCON_WAKE_UP_SUPPORT" + Value = "0" + Help = "WARNING: Not all OS support this function, for more detail please refer to Intel PCH Spec. 12.8 Platform Controller Hub (PCH) USB 2.0 Wake On Connect / Disconnect Handling and PCH EDS RMHWKCTL - Rate Matching Hub Wake Control Reg (PCH EDS RCBA + 35B0h)." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "OEM_USB_PER_PORT_DISABLE_SUPPORT" + Value = "0" + Help = "USB per-port disable function will execute at ready to boot. USB device can use at setup when port is disable but not at OS, DOS or Shell." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SB_PCI_DEVICES_SSID_TABLE" + Value = "{HECI_BUS_DEV_FUN, -1}, {HECI2_BUS_DEV_FUN, -1}, {IDER_BUS_DEV_FUN, -1}, {KT_BUS_DEV_FUN, -1}, {LAN_BUS_DEV_FUN, -1}, {XHCI_BUS_DEV_FUN, -1}, {EHCI2_BUS_DEV_FUN, -1}, {HDA_BUS_DEV_FUN, -1}, {PCIEBRS_BUS_DEV_FUN, -1}, {PCIEBRS2_BUS_DEV_FUN, -1}, {PCIEBRS3_BUS_DEV_FUN, -1}, {PCIEBRS4_BUS_DEV_FUN, -1}, {PCIEBRS5_BUS_DEV_FUN, -1}, {PCIEBRS6_BUS_DEV_FUN, -1}, {PCIEBRS7_BUS_DEV_FUN, -1}, {PCIEBRS8_BUS_DEV_FUN, -1}, {EHCI_BUS_DEV_FUN, -1}, {PCIBR_BUS_DEV_FUN, -1}, {SB_BUS_DEV_FUN, -1}, {SATA_BUS_DEV_FUN, -1}, {SMBUS_BUS_DEV_FUN, -1}, {SATA2_BUS_DEV_FUN, -1}, {THERMAL_BUS_DEV_FUN, -1}, {-1, -1}" + Help = "List of PCI device's Sub-System ID in the following format:\{Device#1 Bus/Device/Function, Device#1 Sub-ID}, {Device#2 Bus/Device/Function, Device#2 Sub-ID}...\The format of the PCI bus/device/function is followed by EFI_PCI_CONFIGURATION_ADDRESS.\If the value of Sub-ID is -1, that means BIOS will use PCI Vendor-ID and Device-ID instead.\The last structure {-1, -1} is end of the table, don't remove it!" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SB_PCI_DEVICES_SSID_TABLE" + Value = "{SIO_DMA_BUS_DEV_FUN, -1}, {SIO_I2C0_BUS_DEV_FUN, -1}, {SIO_I2C1_BUS_DEV_FUN, -1}, {SIO_GSPI0_BUS_DEV_FUN, -1}, {SIO_GSPI1_BUS_DEV_FUN, -1}, {SIO_UART0_BUS_DEV_FUN, -1}, {SIO_UART1_BUS_DEV_FUN, -1}, {SIO_SDIO_BUS_DEV_FUN, -1}, {HECI_BUS_DEV_FUN, -1}, {HECI2_BUS_DEV_FUN, -1}, {IDER_BUS_DEV_FUN, -1}, {KT_BUS_DEV_FUN, -1}, {LAN_BUS_DEV_FUN, -1}, {XHCI_BUS_DEV_FUN, -1}, {EHCI2_BUS_DEV_FUN, -1}, {HDA_BUS_DEV_FUN, -1}, {PCIEBRS_BUS_DEV_FUN, -1}, {PCIEBRS2_BUS_DEV_FUN, -1}, {PCIEBRS3_BUS_DEV_FUN, -1}, {PCIEBRS4_BUS_DEV_FUN, -1}, {PCIEBRS5_BUS_DEV_FUN, -1}, {PCIEBRS6_BUS_DEV_FUN, -1}, {PCIEBRS7_BUS_DEV_FUN, -1}, {PCIEBRS8_BUS_DEV_FUN, -1}, {EHCI_BUS_DEV_FUN, -1}, {PCIBR_BUS_DEV_FUN, -1}, {SB_BUS_DEV_FUN, -1}, {SATA_BUS_DEV_FUN, -1}, {SMBUS_BUS_DEV_FUN, -1}, {SATA2_BUS_DEV_FUN, -1}, {THERMAL_BUS_DEV_FUN, -1}, {-1, -1}" + Help = "List of PCI device's Sub-System ID in the following format:\{Device#1 Bus/Device/Function, Device#1 Sub-ID}, {Device#2 Bus/Device/Function, Device#2 Sub-ID}...\The format of the PCI bus/device/function is followed by EFI_PCI_CONFIGURATION_ADDRESS.\If the value of Sub-ID is -1, that means BIOS will use PCI Vendor-ID and Device-ID instead.\The last structure {-1, -1} is end of the table, don't remove it!" + TokenType = Expression + TargetH = Yes + Token = "ULT_SUPPORT" "=" "1" +End + +TOKEN + Name = "TSGPIO_C_PMSYN" + Value = "1" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "TSGPIO_D_PMSYN" + Value = "1" + Help = "0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "TSGPIO_C_C0_TRANSMIT" + Value = "1" + Help = "0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "TSGPIO_D_C0_TRANSMIT" + Value = "1" + Help = "0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "TSGPIO_C_PIN_SEL" + Value = "1" + TokenType = Integer + TargetH = Yes + Range = "0-1" +End + +TOKEN + Name = "TSGPIO_D_PIN_SEL" + Value = "0" + TokenType = Integer + TargetH = Yes + Range = "0-1" +End + +TOKEN + Name = "DEVICE_NAME_LENGTH" + Value = "14" + Help = "ATA/ATAPI Device name length, this token is defined the maximum characters of the device name will be showed on SETUP." + TokenType = Integer + TargetH = Yes + Range = "2-41" +End + +TOKEN + Name = "SB_SWSMI_WRITE_TO_BOOTSCRIPT" + Value = "0" + Help = "0: Software SMI SW_SMI_ACPI_ENABLE and SW_SMI_SB_ACPI_S3 will be written to boot script in CSM module.\1: Software SMI SW_SMI_ACPI_ENABLE and SW_SMI_SB_ACPI_S3 will be written to boot script in SB eChipset." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SB_SWSMI_WRITE_TO_BOOTSCRIPT" + Value = "1" + Help = "0: Software SMI SW_SMI_ACPI_ENABLE and SW_SMI_SB_ACPI_S3 will be written to boot script in CSM module.\1: Software SMI SW_SMI_ACPI_ENABLE and SW_SMI_SB_ACPI_S3 will be written to boot script in SB eChipset." + TokenType = Boolean + TargetH = Yes + Token = "LegacyInterrupt_SUPPORT" "=" "0" +End + +TOKEN + Name = "PCH_IO_APIC_ID" + Value = "02" + Help = "Assign IO APIC ID" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PCH_APIC_RANGE_SELECT" + Value = "0" + Help = "Program APIC Range Select bits at RCBA + 31FEh[7:0]" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "HDA_RESET_WAIT_TIMER" + Value = "300" + Help = "Minimum link timing requirements." + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "ME_WAKE_STS" + Value = "1" + Help = "Clear Intel ME WAKE STATUS." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "ME_HRST_COLD_STS" + Value = "1" + Help = "Clear Intel ME Host Reset Cold Status." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "ME_HRST_WARM_STS" + Value = "1" + Help = "Clear Intel ME Host Reset Warm Status" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_SLP_S3_MIN_ASSERT_VALUE" + Value = "2" + Help = "SLP_S3# Stretch\0:60us\1:1ms\2:50ms\3:2s" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PCH_SLP_SUS_MIN_ASSERT_VALUE" + Value = "3" + Help = "SLP_SUS# Minimum Assertion Width.\0:0ms\1:500ms\2:1s\3:4s" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PCH_SLPA_MIN_ASSERT_VALUE" + Value = "3" + Help = "SLP_A# Minimum Assertion Width.\0:0ms\1:4s\2:98ms\3:2s" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PCH_RESET_CYCLE_DURATION" + Value = "4" + Help = "Reset Power Cycle Duration.\1:1-2s\2:2-3s\3:3-4s\4:4-5s\Supported in PCH RC v1.4.0." + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SLP_STRCH_SUS_UP" + Value = "0" + Help = "SLP Stretching After SUS Well Power Up\0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "TTLEVELS_SUGGEST" + Value = "1" + Help = "Thermal Throttling.\0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "DMIHAAWC_SUGGEST" + Value = "1" + Help = "0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SATATT_SUGGEST" + Value = "1" + Help = "0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SIRQ_ENABLE" + Value = "1" + Help = "0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SIRQ_START_FRAME_PULSE" + Value = "0" + Help = "0:4 clocks\1:6 clocks\2:8 clocks" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PCH_PCIE_ADVANCED_ERROR_REPORTING" + Value = "0" + Help = "0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_PCIE_PME_INTERRUPT" + Value = "0" + Help = "0:Disable\1:Enable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_PCIE_COMPLETION_TIME_OUT" + Value = "0" + Help = "0:Default\1:50us~100us\2:1ms~10ms\3:16ms~55ms\4:65ms~210ms\5:260ms~900ms\6:1s~3.5s\7:4s~13s\8:17s~64s\9:Disable" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PCH_PCIE_TEMP_RP_BUS_NUM_MIN" + Value = "2" + Help = "Temp Root Port Bus Number Min" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PCH_PCIE_TEMP_RP_BUS_NUM_MAX" + Value = "4" + Help = "Temp Root Port Bus Number Max" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PCH_PCIE_TEMP_RP_BUS_NUM_MAX" + Value = "$(TBT_PCH_PCIE_TEMP_RP_BUS_NUM_MAX)" + Help = "Temp Root Port Bus Number Max" + TokenType = Integer + TargetH = Yes + Token = "Thunderbolt_SUPPORT" "=" "1" +End + +TOKEN + Name = "MAX_EXTRA_BUS_RESERVED" + Value = "7" + Help = "The Max number of extra Bus Reserved for bridges behind this Root Bridge " + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "MAX_EXTRA_BUS_RESERVED" + Value = "$(TBT_MAX_EXTRA_BUS_RESERVED)" + Help = "The Max number of extra Bus Reserved for bridges behind this Root Bridge " + TokenType = Integer + TargetH = Yes + Token = "Thunderbolt_SUPPORT" "=" "1" +End + +TOKEN + Name = "MAX_PCIE_MEM_RESERVED" + Value = "20" + Help = "The Max number of reserved memory range for this Root Bridge." + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "MAX_PCIE_MEM_RESERVED" + Value = "$(TBT_MAX_PCIE_MEM_RESERVED)" + Help = "The Max number of reserved memory range for this Root Bridge." + TokenType = Integer + TargetH = Yes + Token = "Thunderbolt_SUPPORT" "=" "1" +End + +TOKEN + Name = "MAX_PCIE_PF_MEM_RESERVED" + Value = "20" + Help = "The Max number of prefetchable memory range for this Root Bridge." + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "MAX_PCIE_PF_MEM_RESERVED" + Value = "$(TBT_MAX_PCIE_PF_MEM_RESERVED)" + Help = "The Max number of prefetchable memory range for this Root Bridge." + TokenType = Integer + TargetH = Yes + Token = "Thunderbolt_SUPPORT" "=" "1" +End + +TOKEN + Name = "MAX_PCIE_IO_RESERVED" + Value = "20" + Help = "The Max number of IO range for this Root Bridge." + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "MAX_PCIE_IO_RESERVED" + Value = "$(TBT_MAX_PCIE_IO_RESERVED)" + Help = "The Max number of IO range for this Root Bridge." + TokenType = Integer + TargetH = Yes + TOKEN = "Thunderbolt_SUPPORT" "=" "1" +End + +TOKEN + Name = "SATA_MODE_IDE" + Value = "0" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SATA_MODE_AHCI" + Value = "1" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SATA_MODE_RAID" + Value = "2" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SATA_PORT1_LENGTH_CONFIG" + Value = "{1, 0, 1, 0, 1, 2}" + Help = "format: SATA_GEN1_RXEQ_ENABLE, SATA_GEN1_RXEQ_VALUE, SATA_GEN2_RXEQ_ENABLE, SATA_GEN2_RXEQ_VALUE, SATA_GEN3_RXEQ_ENABLE, SATA_GEN3_RXEQ_VALUE. Enable item: Enable:1\Disable:0. Value item:vaule range for ULT platform:0 ~ 0xF. \ vaule range for Two-chip platform:1 ~ 0xC. Please refer Intel PCH EDS for detail information." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SATA_PORT2_LENGTH_CONFIG" + Value = "{1, 0, 1, 0, 1, 2}" + Help = "format: SATA_GEN1_RXEQ_ENABLE, SATA_GEN1_RXEQ_VALUE, SATA_GEN2_RXEQ_ENABLE, SATA_GEN2_RXEQ_VALUE, SATA_GEN3_RXEQ_ENABLE, SATA_GEN3_RXEQ_VALUE. Enable item: Enable:1\Disable:0. Value item:vaule range for ULT platform:0 ~ 0xF. \ vaule range for Two-chip platform:1 ~ 0xC. Please refer Intel PCH EDS for detail information." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SATA_PORT3_LENGTH_CONFIG" + Value = "{1, 0, 1, 0, 1, 2}" + Help = "format: SATA_GEN1_RXEQ_ENABLE, SATA_GEN1_RXEQ_VALUE, SATA_GEN2_RXEQ_ENABLE, SATA_GEN2_RXEQ_VALUE, SATA_GEN3_RXEQ_ENABLE, SATA_GEN3_RXEQ_VALUE. Enable item: Enable:1\Disable:0. Value item:vaule range for ULT platform:0 ~ 0xF. \ vaule range for Two-chip platform:1 ~ 0xC. Please refer Intel PCH EDS for detail information." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SATA_PORT4_LENGTH_CONFIG" + Value = "{1, 0, 1, 0, 1, 2}" + Help = "format: SATA_GEN1_RXEQ_ENABLE, SATA_GEN1_RXEQ_VALUE, SATA_GEN2_RXEQ_ENABLE, SATA_GEN2_RXEQ_VALUE, SATA_GEN3_RXEQ_ENABLE, SATA_GEN3_RXEQ_VALUE. Enable item: Enable:1\Disable:0. Value item:vaule range for ULT platform:0 ~ 0xF. \ vaule range for Two-chip platform:1 ~ 0xC. Please refer Intel PCH EDS for detail information." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SATA_PORT5_LENGTH_CONFIG" + Value = "{1, 0, 1, 0, 1, 2}" + Help = "format: SATA_GEN1_RXEQ_ENABLE, SATA_GEN1_RXEQ_VALUE, SATA_GEN2_RXEQ_ENABLE, SATA_GEN2_RXEQ_VALUE, SATA_GEN3_RXEQ_ENABLE, SATA_GEN3_RXEQ_VALUE. Enable item: Enable:1\Disable:0. Value item:vaule range for ULT platform:0 ~ 0xF. \ vaule range for Two-chip platform:1 ~ 0xC. Please refer Intel PCH EDS for detail information." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SATA_PORT6_LENGTH_CONFIG" + Value = "{1, 0, 1, 0, 1, 2}" + Help = "format: SATA_GEN1_RXEQ_ENABLE, SATA_GEN1_RXEQ_VALUE, SATA_GEN2_RXEQ_ENABLE, SATA_GEN2_RXEQ_VALUE, SATA_GEN3_RXEQ_ENABLE, SATA_GEN3_RXEQ_VALUE. Enable item: Enable:1\Disable:0. Value item:vaule range for ULT platform:0 ~ 0xF. \ vaule range for Two-chip platform:1 ~ 0xC. Please refer Intel PCH EDS for detail information" + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SPI_FV_BB_PROTECTED_RANGE_BASE" + Value = "$(FLASH_SIZE) - (0xFFFFFFFF - $(FV_BB_BASE) + 1)" + Help = "it is BIOS rom address offset, C code will translate it to Flash rom address" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SPI_FV_BB_PROTECTED_RANGE_LENGTH" + Value = "$(FV_BB_BLOCKS) * $(FLASH_BLOCK_SIZE)" + Help = "Protected region length" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SPI_FV_MAIN_PROTECTED_RANGE_BASE" + Value = "$(FLASH_SIZE) - (0xFFFFFFFF - $(FV_MAIN_BASE) + 1)" + Help = "it is BIOS rom address offset, C code will translate it to Flash rom address" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SPI_FV_MAIN_PROTECTED_RANGE_LENGTH" + Value = "$(FV_MAIN_BLOCKS) * $(FLASH_BLOCK_SIZE)" + Help = "Protected region length" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SPI_FV_DATA_PROTECTED_RANGE_BASE" + Value = "$(FLASH_SIZE) - (0xFFFFFFFF - $(FV_DATA_BASE) + 1)" + Help = "it is BIOS rom address offset, C code will translate it to Flash rom address" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SPI_FV_DATA_PROTECTED_RANGE_LENGTH" + Value = "$(FV_DATA_SIZE)" + Help = "Protected range length" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "SPI_PROTECTED_RANGE_0" + Value = "{2, FALSE, FALSE, $(SPI_FV_BB_PROTECTED_RANGE_BASE), $(SPI_FV_BB_PROTECTED_RANGE_LENGTH)}" + Help = "Format:\ 1st - The type of protected range 0, the available types are Undefined Type(0), Descriptor Type(1), BIOS Type(2), ME/TXE Type(3) abd GBE Type(4).\ 2nd - Write Protected Enable.\ 3rd - Read Protected Enable.\ 4th - The protection range base(MUST be 4KB alignment), it is only used for the protected types 0(Undefined) and 2(BIOS).\ 5th - The protection range length(the minimun length MUST be 4KB).\ Note : If 2nd & 3rd parameters both are Zeros, then this protected range will be disabled.\ This protected range is default for FV_BB, but you can update it according to your own design." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SPI_PROTECTED_RANGE_1" + Value = "{2, FALSE, FALSE, $(SPI_FV_MAIN_PROTECTED_RANGE_BASE), $(SPI_FV_MAIN_PROTECTED_RANGE_LENGTH)}" + Help = "Format:\ 1st - The type of protected range 1, the available types are Undefined Type(0), Descriptor Type(1), BIOS Type(2), ME/TXE Type(3) abd GBE Type(4).\ 2nd - Write Protected Enable.\ 3rd - Read Protected Enable.\ 4th - The protection range base(MUST be 4KB alignment), it is only used for the protected types 0(Undefined) and 2(BIOS).\ 5th - The protection range length(the minimun length MUST be 4KB).\ Note : If 2nd & 3rd parameters both are Zeros, then this protected range will be disabled.\ This protected range is default for FV_MAIN, but you can update it according to your own design." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SPI_PROTECTED_RANGE_2" + Value = "{2, FALSE, FALSE, $(SPI_FV_DATA_PROTECTED_RANGE_BASE), $(SPI_FV_DATA_PROTECTED_RANGE_LENGTH)}" + Help = "Format:\ 1st - The type of protected range 2, the available types are Undefined Type(0), Descriptor Type(1), BIOS Type(2), ME/TXE Type(3) abd GBE Type(4).\ 2nd - Write Protected Enable.\ 3rd - Read Protected Enable.\ 4th - The protection range base(MUST be 4KB alignment), it is only used for the protected types 0(Undefined) and 2(BIOS).\ 5th - The protection range length(the minimun length MUST be 4KB).\ Note : If 2nd & 3rd parameters both are Zeros, then this protected range will be disabled.\ This protected range is default for FV_DATA, but you can update it according to your own design." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SPI_PROTECTED_RANGE_3" + Value = "{0, FALSE, FALSE, 0, 0}" + Help = "Format:\ 1st - The type of protected range 3, the available types are Undefined Type(0), Descriptor Type(1), BIOS Type(2), ME/TXE Type(3) abd GBE Type(4).\ 2nd - Write Protected Enable.\ 3rd - Read Protected Enable.\ 4th - The protection range base(MUST be 4KB alignment), it is only used for the protected types 0(Undefined) and 2(BIOS).\ 5th - The protection range length(the minimun length MUST be 4KB).\ Note : If 2nd & 3rd parameters both are Zeros, then this protected range will be disabled." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "SPI_PROTECTED_RANGE_4" + Value = "{0, FALSE, FALSE, 0, 0}" + Help = "Format:\ 1st - The type of protected range 4, the available types are Undefined Type(0), Descriptor Type(1), BIOS Type(2), ME/TXE Type(3) abd GBE Type(4).\ 2nd - Write Protected Enable.\ 3rd - Read Protected Enable.\ 4th - The protection range base(MUST be 4KB alignment), it is only used for the protected types 0(Undefined) and 2(BIOS).\ 5th - The protection range length(the minimun length MUST be 4KB).\ Note : If 2nd & 3rd parameters both are Zeros, then this protected range will be disabled." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = "FORCE_USER_TO_SETUP_IF_CMOS_BAD" + Value = "0" + Help = "When this flag is on, Setup will be automatically launched whenever CMOS is bad." + TokenType = Boolean + TargetH = Yes +End + # [EIP87695]> +TOKEN + Name = "SYSTEM_REBOOT_NORMALLY_IF_S3_IS_FAILED" + Value = "0" + Help = "Add a workaround path to avoid that the system can't reboot normally when S3 resume is failed." + TokenType = Boolean + TargetH = Yes +End + # <[EIP87695] + +TOKEN + Name = "ZPODD_SATA_PORT" + Value = "0x02" + Help = "ZPODD SATA Port Number." + TokenType = Integer + TargetH = Yes + Token = "PCH_SKU" "=" "1" +End + +TOKEN + Name = "SB_SATA_DLAE" + Value = "0" + Help = "Drive LED on ATAPI Enable (DLAE).\ 1:Enable \ 0:Disable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PCH_RCRB_OIC_CEN" + Value = "1" + Help = "Set RCBA Coprocessor Error Enable bit.\ 1:Enable \ 0:Disable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "HOST_WLAN_PP_EN" + Value = "0" + Help = "Host Wireless LAN PHY Power.\ 1:Enable \ 0:Disable" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "ONLY_CLEAR_RTC_EN_IN_PEI" + Value = "1" + Help = "1: Only clear RTC_EN in PM1_EN \ 0: Clear all enable bits in PM1_EN." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = " " + TokenType = Integer +End + +TOKEN + Name = "=============== PCH CMOS Tokens ==============" + TokenType = Expression +End + +TOKEN + Name = "SB_CMOS_MISC_FLAG_REG" + Value = "0x90" + Help = "[1:0] = 00b: COMPLETE_SAVE_RESTORE_STD_CMOS.\[1:0] = 01b: ENABLE_NMI_BEFORE_SMI_EXIT.\[1:0] = 10b: DISABLE_NMI_BEFORE_SMI_EXIT." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Lock = Yes + Token = "CMOS_MANAGER_SUPPORT" "=" "1" +End + +TOKEN + Name = " " + TokenType = Integer +End + +TOKEN + Name = "============== IO DECODE SETINNG ==============" + Value = " " + TokenType = Expression +End + +TOKEN + Name = "SB_IO_DECODE_IN_SEC" + Value = "0" + Help = "The value of SIO_PME_BASE_ADDRESS, '0' means no function." + TokenType = Boolean + TargetEQU = Yes +End + +TOKEN + Name = "SB_GEN_DECODE_RANGE_1" + Value = "0" +# Value = "$(SIO_PME_BASE_ADDRESS)" <example> +# Value = "$(IT8720F_PME_BASE_ADDRESS)" <example> + Help = "The value of SIO_PME_BASE_ADDRESS, '0' means no function." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Range = "00 - 0FFFFh" + Token = "SB_IO_DECODE_IN_SEC" "=" "1" +End + +TOKEN + Name = "SB_GEN_DECODE_RANGE_2" + Value = "0" +# Value = "$(SIO_PME_BASE_ADDRESS)" <example> +# Value = "$(IT8720F_PME_BASE_ADDRESS)" <example> + Help = "The value of SIO_PME_BASE_ADDRESS, '0' means no function." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Range = "00 - 0FFFFh" + Token = "SB_IO_DECODE_IN_SEC" "=" "1" +End + +TOKEN + Name = "SB_GEN_DECODE_RANGE_3" + Value = "0" +# Value = "$(SIO_PME_BASE_ADDRESS)" <example> +# Value = "$(IT8720F_PME_BASE_ADDRESS)" <example> + Help = "The value of SIO_PME_BASE_ADDRESS, '0' means no function." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Range = "00 - 0FFFFh" + Token = "SB_IO_DECODE_IN_SEC" "=" "1" +End + +TOKEN + Name = "SB_GEN_DECODE_RANGE_4" + Value = "0" +# Value = "$(SIO_PME_BASE_ADDRESS)" <example> +# Value = "$(IT8720F_PME_BASE_ADDRESS)" <example> + Help = "The value of SIO_PME_BASE_ADDRESS, '0' means no function." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Range = "00 - 0FFFFh" + Token = "SB_IO_DECODE_IN_SEC" "=" "1" +End + +TOKEN + Name = " " + TokenType = Integer +End + +TOKEN + Name = "============== GPIO SETINNG ==============" + Value = " " + TokenType = Expression +End + +TOKEN + Name = "PROGRAM_DEFAULT_GPIO" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "PROGRAM_GPIO_TYPE" + Value = "0" + Help = "0:use array directly/1:use token define" + TokenType = Boolean + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "IS_GPIO" + Value = "0x0001" + Help = "It is a GPIO, the pin will be used as a GPIO." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "IS_NOT_GPIO" + Value = "0x0000" + Help = "It is not a GPIO, the pin will be used as native function." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "IS_GPI" + Value = "0x0002" + Help = "It is a GPIO and is an input." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "IS_GPO" + Value = "0x0000" + Help = "It is a GPIO and is an output." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "OUTPUT_HIGH" + Value = "0x0004" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "OUTPUT_LOW" + Value = "0x0000" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPO_HIGH" + Value = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_HIGH)" + Help = "It is a GP output and driving a high level on the pin." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPO_LOW" + Value = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_LOW)" + Help = "It is a GP output and driving a low level on the pin." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPI_NON_INV" + Value = "0x0000" + Help = "The GPI pin will active high to cause SMI# or SCI. \This value must be combined with token IS_GPI." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPI_INV" + Value = "0x0008" + Help = "The GPI pin will active low to cause SMI# or SCI. \This value must be combined with token IS_GPI." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPO_BLINK" + Value = "0x0010" + Help = "The GPO pin will blink at a rate of approximately once per second. This value must be combined with tokens GPO_HIGH or GPO_LOW." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPIO_RESET" + Value = "0x0020" + Help = "" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPIO_OWN_ACPI" + Value = "0x0000" + Help = "It is GPIO use by ACPI driver." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPIO_OWN_GPIO" + Value = "0x0040" + Help = "It is GPIO use by GPIO driver." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPI_LEB_EDGE" + Value = "0x0000" + Help = "The GPI pin use by Edge Mode." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPI_LEB_LEVEL" + Value = "0x0080" + Help = "The GPI pin use by Level Mode." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPI_NDIS_ENABLE" + Value = "0x0000" + Help = "The GPI pin Input seneing enable." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPI_NDIS_DISABLE" + Value = "0x0100" + Help = "The GPI pin Iutput seneing disable." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPIO_GPIWP_NONE" + Value = "0x0000" + Help = "None" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPIO_GPIWP_DOWN" + Value = "0x0200" + Help = "Pull Down" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPIO_GPIWP_UP" + Value = "0x0400" + Help = "Pull Up" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPIO_GPIWP_INVALID" + Value = "0x0600" + Help = "Invalid" + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPI_INT_ENABLE" + Value = "0x0800" + Help = "This bit enables the corresponding GPIOn to generate APIC interrupt." + TokenType = Integer + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "GPIO_002" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_003" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_004" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_005" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_010" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_019" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_021" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_022" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_024" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_029" + Value = "$(GPO_HIGH)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_035" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_036" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_037" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_038" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_039" + Value = "$(IS_NOT_GPIO)" + TokenType = Integer + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "GPIO_048" + Value = "$(IS_NOT_GPIO)" + Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "ULT_GPIO_000" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_001" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_002" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_003" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_004" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_005" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_006" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_007" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_008" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_009" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_010" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_011" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_012" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_013" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_014" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPIO_GPIWP_DOWN)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_015" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_016" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_017" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_018" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_019" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_020" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_021" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_022" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_023" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_024" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPIO_OWN_GPIO)+$(GPIO_RESET)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_025" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_026" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_027" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPI_LEB_LEVEL)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_028" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_029" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_030" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_031" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_032" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_033" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_034" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_035" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(OUTPUT_HIGH)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_036" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_037" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_038" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_039" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_040" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_041" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_042" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_043" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_044" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_045" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_046" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_047" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_048" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_049" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_050" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_051" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_052" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_053" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_054" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_055" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_056" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_057" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_058" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_059" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_060" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_061" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_062" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_063" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_064" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_065" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_066" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_067" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_068" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_069" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_070" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_071" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_072" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_073" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_074" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_075" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_076" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_077" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_078" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_079" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_INV)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_080" + Value = "$(IS_GPIO)+$(IS_GPI)+$(GPI_LEB_LEVEL)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_081" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_082" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_083" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_084" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_085" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_086" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_LEB_LEVEL)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_087" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_088" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_089" + Value = "$(IS_GPIO)+$(OUTPUT_HIGH)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_090" + Value = "$(IS_GPIO)+$(OUTPUT_LOW)+$(GPI_NDIS_DISABLE)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_091" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_092" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_093" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_094" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "ULT_GPIO_095" + Value = "$(IS_NOT_GPIO)+$(OUTPUT_HIGH)+$(GPIO_OWN_GPIO)" + Help = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input sensing enable/ 1: Output sensing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid \ BIT11 - 0: GPI Interrupt Disable / 1: GPI Interrupt Enable" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Token = "PROGRAM_GPIO_TYPE" "=" "1" +End + +TOKEN + Name = "=============== ACPI Specific Tokens ==============" + TokenType = Expression +End + +TOKEN + Name = "APCB" + Value = "0x0FEC00000" + Help = "Default I/O APIC(s) memory start address, bytes\0x0FEC00000 - default, 0 - I/O APIC's disabled" + TokenType = Integer + TargetASL = Yes + TargetH = Yes +End + +TOKEN + Name = "APCL" + Value = "0x1000" + Help = "I/O APIC(s) memory decoded range, bytes\0x1000 - default,\0 - I/O APIC's not decoded " + TokenType = Integer + TargetASL = Yes + TargetH = Yes +End + +TOKEN + Name = "A_POS_DECODE" + Value = "0" + TokenType = Boolean + TargetMAK = Yes +End + +TOKEN + Name = "SW_SMI_SB_ACPI_S3" + Value = "0xb8" + Help = "Value to be written into SMI command register \to enable S3 patched codes" + TokenType = Integer + TargetH = Yes + Range = "0xB7 - 0xBD" +End + +TOKEN + Name = "SMCR" + Value = "$(PM_BASE_ADDRESS)+0x30" + Help = "SMI Control Register" + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "ACPI_SCI_INT" + Value = "9" + Help = "SCI Interrupt number" + TokenType = Integer + TargetH = Yes + Range = "4-15" +End + +TOKEN + Name = "PM_SCI_ENABLE" + Value = "0x01" + Help = "Value that needs to be written in PM1_CNT regirter \to Enable SCI generation on PM events" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "ACPI_ALARM_DAY_CMOS" + Value = "0x0d" + Help = "RTC Index of the Day-of-Month alarm" + TokenType = Integer + TargetH = Yes + Range = "0 - 0xff 0 = not supported" +End + +TOKEN + Name = "ACPI_ALARM_MONTH_CMOS" + Value = "0x00" + Help = "RTC Index of the Month-of-year alarm\" + TokenType = Integer + TargetH = Yes + Range = "0-0xff 0 = not supported" +End + +TOKEN + Name = "ACPI_CENTURY_CMOS" + Value = "0x32" + Help = "RTC Index of the Century-of-Data\" + TokenType = Integer + TargetH = Yes + Range = "0-0xff 0 = not supported" +End + +TOKEN + Name = "ACPI_RESET_REG_ADDRESS" + Value = "0xcf9" + Help = "Reset Register Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "ACPI_RESET_REG_TYPE" + Value = "1" + Help = "Reset Register Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "ACPI_RESET_REG_BITWIDTH" + Value = "8" + Help = "Reset Register Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "ACPI_RESET_REG_BITOFFSET" + Value = "0" + Help = "Reset Register Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "ACPI_RESET_REG_VALUE" + Value = "006h" + Help = "Value to write to the Reset Register to initiate System Reset" + TokenType = Integer + TargetH = Yes + Range = "? - chipset specific" +End + +TOKEN + Name = "PM1A_EVT_BLK_ADDRESS" + Value = "$(PM_BASE_ADDRESS)" + Help = "PM1a_EVT BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "PM1A_EVT_BLK_TYPE" + Value = "1" + Help = "PM1a_EVT BLK Registes Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "PM1A_EVT_BLK_BITWIDTH" + Value = "32" + Help = "PM1a_EVT BLK Registes Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1A_EVT_BLK_BITOFFSET" + Value = "0" + Help = "PM1a_EVT BLK Registes Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1_EVT_LENGTH" + Value = "4" + Help = "PM1a_EVT BLK length in bytes" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1A_CNT_BLK_ADDRESS" + Value = "$(PM_BASE_ADDRESS)+0x04" + Help = "PM1a_CNT BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "PM1A_CNT_BLK_TYPE" + Value = "1" + Help = "PM1a_CNT BLK Registes Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "PM1A_CNT_BLK_BITWIDTH" + Value = "16" + Help = "PM1a_CNT BLK Registes Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1A_CNT_BLK_BITOFFSET" + Value = "0" + Help = "PM1a_CNTT BLK Registes Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1_CNT_LENGTH" + Value = "2" + Help = "PM1a_CNT BLK length in bytes" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1B_EVT_BLK_ADDRESS" + Value = "0" + Help = "PM1b_EVT BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "PM1B_EVT_BLK_TYPE" + Value = "1" + Help = "PM1b_EVT BLK Registes Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "PM1B_EVT_BLK_BITWIDTH" + Value = "0" + Help = "PM1a_EVT BLK Registes Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1B_EVT_BLK_BITOFFSET" + Value = "0" + Help = "PM1a_EVT BLK Registes Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1B_CNT_BLK_ADDRESS" + Value = "0" + Help = "PM1b_CNT BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "PM1B_CNT_BLK_TYPE" + Value = "1" + Help = "PM1a_CNT BLK Registes Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "PM1B_CNT_BLK_BITWIDTH" + Value = "0" + Help = "PM1a_CNT BLK Registes Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM1B_CNT_BLK_BITOFFSET" + Value = "0" + Help = "PM1a_CNTT BLK Registes Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM2_CNT_BLK_ADDRESS" + Value = "$(PM_BASE_ADDRESS)+0x50" + Help = "PM2_CNT BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "PM2_CNT_BLK_TYPE" + Value = "1" + Help = "PM2_CNT BLK Registes Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "PM2_CNT_BLK_BITWIDTH" + Value = "8" + Help = "PM2_CNT BLK Registes Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM2_CNT_BLK_BITOFFSET" + Value = "0" + Help = "PM2_CNT BLK Registes Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM2_CNT_LENGTH" + Value = "1" + Help = "PM2_CNT BLK length in bytes" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM_TMR_BLK_ADDRESS" + Value = "$(PM_BASE_ADDRESS)+0x08" + Help = "PM_TMR BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "PM_TMR_BLK_TYPE" + Value = "1" + Help = "PM_TMR BLK Registes Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "PM_TMR_BLK_BITWIDTH" + Value = "32" + Help = "PM_TMR BLK Registes Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM_TMR_BLK_BITOFFSET" + Value = "0" + Help = "PM_TMR BLK Registes Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "PM_TMR_LENGTH" + Value = "4" + Help = "PM_TMR BLK length in bytes" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "GPE0_BLK_ADDRESS" + Value = "$(PM_BASE_ADDRESS)+0x20" + Help = "GPE0 BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "GPE0_BLK_ADDRESS" + Value = "$(PM_BASE_ADDRESS)+0x80" + Help = "GPE0 BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Token = "ULT_SUPPORT" "=" "1" + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "GPE0_BLK_TYPE" + Value = "1" + Help = "GPE0 BLK Registes Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "GPE0_BLK_BITWIDTH" + Value = "128" + Help = "GPE0 BLK Registes Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "GPE0_BLK_BITOFFSET" + Value = "0" + Help = "GPE0 BLK Registes Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "GPE0_BLK_LENGTH" + Value = "16" + Help = "GPE0 BLK length in bytes" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "GPE0_BLK_LENGTH" + Value = "32" + Help = "GPE0 BLK length in bytes" + TokenType = Integer + TargetH = Yes + Token = "ULT_SUPPORT" "=" "1" + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "GPE1_BLK_ADDRESS" + Value = "0" + Help = "GPE1 BLK Base Address (Part of GAS Structure refer, to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0 = not Supported other values depends on other GAS elements" +End + +TOKEN + Name = "GPE1_BLK_TYPE" + Value = "1" + Help = "GPE1 BLK Registes Id (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "0=System memory; 1=System I/O; 2=PCI Config Space; 3=Embeded Controller; 4=SMBus; 0x7F=Functional Fixed Hardware; All other values reserved" +End + +TOKEN + Name = "GPE1_BLK_BITWIDTH" + Value = "0" + Help = "GPE1 BLK Registes Bit Width (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "GPE1_BLK_BITOFFSET" + Value = "0" + Help = "GPE1 BLK Registes Bit Offset (Part of GAS Structure, refer to ACPI v2.0 spec for details)" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "GPE1_BLK_LENGTH" + Value = "0" + Help = "GPE1 BLK length in bytes" + TokenType = Integer + TargetH = Yes + Range = "value range depends on other GAS elements" +End + +TOKEN + Name = "GPE1_BASE_OFFSET" + Value = "0" + Help = "GPE1 Base offset within the ACPI general purpose event model (FADT byte 94)" + TokenType = Integer + TargetH = Yes + Range = "0-0xff" +End + +TOKEN + Name = "GPE1_BASE_OFFSET" + Value = "0x10" + Help = "GPE1 Base offset within the ACPI general purpose event model (FADT byte 94)" + TokenType = Integer + TargetH = Yes + Token = "ULT_SUPPORT" "=" "1" + Range = "0-0xff" +End + +TOKEN + Name = "PRIMARY_CHANNEL_ENABLE" + Value = "1" + Help = "Enable/Disable Primary Channel" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "PRIMARY_MASTER_DRIVE_ENABLE" + Value = "1" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "MAX_UDMA" + Value = "5" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "MAX_PIO" + Value = "4" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "PRIMARY_SLAVE_DRIVE_ENABLE" + Value = "1" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SECONDARY_CHANNEL_ENABLE" + Value = "1" + Help = "Enable/Disable Secondary Channel" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SECONDARY_MASTER_DRIVE_ENABLE" + Value = "1" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SECONDARY_SLAVE_DRIVE_ENABLE" + Value = "1" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "BUSMASTER_ENABLE" + Value = "1" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "MASTER_INTERRUPT_BASE" + Value = "0x58" + Help = "This value set the Interrupt Vector base for the master. Hardware IRQ0 = this base.\In legacy real mode this value is 8. It can not be 8 in protected mode.\This value must be a multiple of 8, and the this value must be different than SLAVE_INTERRUPT_BASE." + TokenType = Integer + TargetH = Yes + Range = "0-F8" +End + +TOKEN + Name = "SLAVE_INTERRUPT_BASE" + Value = "0x70" + Help = "This value set the Interrupt Vector base for the slave. Hardware IRQ8 = this base.\In legacy real mode this value is 0x70.\This value must be a multiple of 8, and the this value must be different than MASTER_INTERRUPT_BASE." + TokenType = Integer + TargetH = Yes + Range = "0-F8" +End + +TOKEN + Name = "A_S0_PKG" + Value = "0x0,0x0,0,0" + Help = "Intel ICH(x) example. Modify for a new Chipset" + TokenType = Expression + TargetMAK = Yes + Range = "4 decimal or Hex (use '0x' prefix) values sepparated with ','" +End + +TOKEN + Name = "A_S1_PKG" + Value = "0x1,0x0,0,0" + Help = "Intel ICH(x) example. Modify for a new Chipset" + TokenType = Expression + TargetMAK = Yes + Range = "4 decimal or Hex (use '0x' prefix) values separated with ','" +End + +TOKEN + Name = "A_S2_PKG" + Value = "0x2,0x0,0,0" + TokenType = Expression + TargetMAK = Yes + Range = "4 decimal or Hex (use '0x' prefix) values separated with ','" +End + +TOKEN + Name = "A_S3_PKG" + Value = "0x5,0x0,0,0" + Help = "Intel ICH(x) example. Modify for a new Chipset" + TokenType = Expression + TargetMAK = Yes + Range = "4 decimal or Hex (use '0x' prefix) values separated with ','" +End + +TOKEN + Name = "A_S4_PKG" + Value = "0x6,0x0,0,0" + Help = "Intel ICH(x) example. Modify for a new Chipset" + TokenType = Expression + TargetMAK = Yes + Range = "4 decimal or Hex (use '0x' prefix) values separated with ','" +End + +TOKEN + Name = "A_S5_PKG" + Value = "0x7,0x0,0,0" + Help = "Intel ICH(x) example. Modify for a new Chipset" + TokenType = Expression + TargetMAK = Yes + Range = "4 decimal or Hex (use '0x' prefix) values separated with ','" +End + +TOKEN + Name = "S4_WAKE_FROM_RTC_SUPPORTED" + Value = "1" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "REMOTE_POWER_ON_SUPPORTED" + Value = "0" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "INCLUDE_SB_ASM_FILE_IN_SEC" + Value = "1" + Help = "Includes an ASM file and an eLink in SEC build process for SB code modification:" + TokenType = Boolean +End + +TOKEN + Name = "SLEEP_BUTTON_SUPPORT" + Value = "0" + Help = "Enable/Disable ACPI Sleep Button." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "HPET_SUPPORT" + Value = "1" + Help = "Enables High Performance Event Timer (HPET) Support in Project" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "HPET_BASE_ADDRESS" + Value = "0xFED00000" + Help = "HPET Block Registers" + TokenType = Integer + TargetH = Yes + Range = "0xFED00000 or 0xFED01000 or 0xFED02000 or 0xFED04000" + Token = "HPET_SUPPORT" "=" "1" +End + +TOKEN + Name = "HPTB" + Value = "$(HPET_BASE_ADDRESS)" + Help = "Same as HPET_BASE_ADDRESS for ASL use " + TokenType = Integer + TargetASL = Yes + TargetH = Yes + Token = "HPET_SUPPORT" "=" "1" +End + +TOKEN + Name = "HPTC" + Value = "$(SB_RCRB_BASE_ADDRESS)+0x3404" + Help = "High Precision Event Timer Configuration Register" + TokenType = Integer + TargetASL = Yes + Range = "offset 0x3404 from RCBA " + Token = "HPET_SUPPORT" "=" "1" +End + +TOKEN + Name = "HPET_PROTOCOL_SUPPORT" + Value = "0" + Help = "Use High Performance Event Timer (HPET) instead of 8254 to support Timer protocol in Project" + TokenType = Boolean + TargetH = Yes + Token = "HPET_SUPPORT" "=" "1" +End + +TOKEN + Name = "HPET_DEFAULT_TICK_DURATION" + Value = "10000" + Help = "The unit is 100ns, the default value is 1ms." + TokenType = Integer + TargetH = Yes + Token = "HPET_SUPPORT" "=" "1" + Token = "HPET_PROTOCOL_SUPPORT" "=" "1" +End + +TOKEN + Name = "HPET_OFFSET" + Value = "0" + Help = "The offset of High Performance Event Timer.\This value can't exceed in the number of HPET capability.\The timer must also be able to support periodic mode." + TokenType = Integer + TargetH = Yes + Token = "HPET_SUPPORT" "=" "1" + Token = "HPET_PROTOCOL_SUPPORT" "=" "1" +End + +TOKEN + Name = "HPET_APIC_INTERRUPT_MODE" + Value = "1" + Help = "Off : The timer interrupt will be routed to PIC(8259).\On : The timer interrupt will be routed to APIC." + TokenType = Boolean + TargetH = Yes + Token = "HPET_SUPPORT" "=" "1" + Token = "HPET_PROTOCOL_SUPPORT" "=" "1" +End + +TOKEN + Name = "HPET_APIC_INTERRUPT_PIN" + Value = "20" + Help = "Select an APIC interrupt pin for the timer's interrupt.\Notice! Please refer to your HPET F/W porting guide to know which APIC interrupt pins can be used for this timer's interrupt." + TokenType = Integer + TargetH = Yes + Token = "HPET_SUPPORT" "=" "1" + Token = "HPET_PROTOCOL_SUPPORT" "=" "1" + Token = "HPET_APIC_INTERRUPT_MODE" "=" "1" + Range = "20, 21, 22, 23" +End + +TOKEN + Name = "HPET_INTERRUPT_POLARITY" + Value = "0" + Help = "On : The polarity is high.\Off : The polarity is low." + TokenType = Boolean + TargetH = Yes + Token = "HPET_SUPPORT" "=" "1" + Token = "HPET_PROTOCOL_SUPPORT" "=" "1" + Token = "HPET_APIC_INTERRUPT_MODE" "=" "1" +End + +TOKEN + Name = "HPET_INTERRUPT_TRIGGER" + Value = "0" + Help = "On : level triggered.\Off : edge triggered." + TokenType = Boolean + TargetH = Yes + Token = "HPET_SUPPORT" "=" "1" + Token = "HPET_PROTOCOL_SUPPORT" "=" "1" + Token = "HPET_APIC_INTERRUPT_MODE" "=" "1" +End + +TOKEN + Name = "HDD_POWER_LOSS_IN_S3" + Value = "1" + Help = "Disable this feature if HDD doesn't lose power \during S3 resume. HDD need to be unlocked during \S3 resume if it loses power and \also HDD need to be put in Freeze state.\" + TokenType = Boolean + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "CMOS_ADDR_PORT" + Value = "0x70" + Help = "CMOS Index Port." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "CMOS_DATA_PORT" + Value = "0x71" + Help = "CMOS Data Port." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "CMOS_BAD_REG" + Value = "0x0E" + Help = "CMOS Diagnostics Port." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "DEFAULT_YEAR" + Value = "2009" + Help = "Year, that will be set in RTC in case of date corruption" + TokenType = Integer + TargetH = Yes + Range = "1998-2099" +End + +TOKEN + Name = "DEFAULT_MONTH" + Value = "1" + Help = "Month, that will be set in RTC in case of date corruption" + TokenType = Integer + TargetH = Yes + Range = "1-12" +End + +TOKEN + Name = "DEFAULT_DAY" + Value = "1" + Help = "Day, that will be set in RTC in case of date corruption" + TokenType = Integer + TargetH = Yes + Range = "1-31" +End + +TOKEN + Name = "EARLIEST_YEAR" + Value = "1998" + Help = "If year, stored in RTC is less than this value, date will be considered as incorrect" + TokenType = Integer + TargetH = Yes + Range = "1998" +End + +TOKEN + Name = "PCI_DEBUG_PORT" + Value = "080h" + Help = "Debug Card I/O Port, default is 80h" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SB_TEMP_IO_BASE" + Value = "0x1200" + Help = "A Temporal I/O Base Address for Init.\Its length is 1K bytes." + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "AMI_INIT_VERB_TABLE_IN_S3" + Value = "0" + Help = "This is a backup solution for Intel RC" + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "RESERVED_ROM_LENGTH" + Value = "0x1000000" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "RESERVED_ROM_BASE" + Value = "(0xFFFFFFFF-$(RESERVED_ROM_LENGTH)+1)" + Help = "Reserved for ROM image." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SB_TEMP_MMIO_BASE" + Value = "($(RESERVED_ROM_BASE)-$(SB_TEMP_MMIO_BASE_LENGTH))" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SB_TEMP_MMIO_BASE_LENGTH" + Value = "0x10000" + Help = "Intel required minimum size is 64KB bytes." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Lock = Yes +End + +TOKEN + Name = "MAX_NUM_HD_CODECS" + Value = "0x04" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "KBC_AUTODETECT_PORTS" + Value = "0" + Help = "Auto detection of KB/MS using AMI KB-5. This switch will enable/disable the connector swap of Keyboard and PS2 Mouse i.e. keyboard\can be connected to PS2 Mouse connector and vice-versa." + TokenType = Boolean + TargetH = Yes +End + +TOKEN + Name = "SIO_SB_DEV_NUM" + Value = "0x1F" + Help = "SB LPC Device Number" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "FLSZ" + Value = "$(FLASH_SIZE)" + Help = "Size of the Flash Device in bytes" + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "SB_RCRB_BASE_ADDRESS" + Value = "0FED1C000h" + Help = "\The Root Complex Base Address of PCH.\Must be aligned a 16-KB boundary." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SB_RCBA" + Value = "$(SB_RCRB_BASE_ADDRESS)" + Help = "\The Root Complex Base Address of PCH.\Must be aligned a 16-KB boundary." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "SB_RCRB_LENGTH" + Value = "0x4000" + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "SRCB" + Value = "$(SB_RCRB_BASE_ADDRESS)" + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "RCLN" + Value = "$(SB_RCRB_LENGTH)" + TokenType = Integer + TargetASL = Yes +End + +TOKEN + Name = "RESERVED_PAGE_ROUTE" + Value = "0" + Help = "0 - Forward to LPC.\1 - Forward to PCI.\Please refer to RCBA#3410h[2]." + TokenType = Integer + TargetEQU = Yes + TargetH = Yes +End + +TOKEN + Name = "RC_PORT_0" + Value = "1" + Help = "Set to 'On' if PCH Root Complex Port #0 phisically enabled and connected on the board" + TokenType = Boolean + TargetH = Yes + Range = "On - Off" +End + +TOKEN + Name = "RC_PORT_1" + Value = "1" + Help = "Set to 'On' if PCH Root Complex Port #1 phisically enabled and connected on the board" + TokenType = Boolean + TargetH = Yes + Range = "On - Off" + Token = "RC_PORT_0" "=" "1" +End + +TOKEN + Name = "RC_PORT_2" + Value = "1" + Help = "Set to 'On' if PCH Root Complex Port #2 phisically enabled and connected on the board" + TokenType = Boolean + TargetH = Yes + Range = "On - Off" + Token = "RC_PORT_0" "=" "1" +End + +TOKEN + Name = "RC_PORT_3" + Value = "1" + Help = "Set to 'On' if PCH Root Complex Port #3 phisically enabled and connected on the board" + TokenType = Boolean + TargetH = Yes + Range = "On - Off" + Token = "RC_PORT_0" "=" "1" +End + +TOKEN + Name = "RC_PORT_4" + Value = "1" + Help = "Set to 'On' if PCH Root Complex Port #4 phisically enabled and connected on the board" + TokenType = Boolean + TargetH = Yes + Range = "On - Off" + Token = "RC_PORT_0" "=" "1" +End + +TOKEN + Name = "RC_PORT_5" + Value = "1" + Help = "Set to 'On' if PCH Root Complex Port #5 phisically enabled and connected on the board" + TokenType = Boolean + TargetH = Yes + Range = "On - Off" + Token = "RC_PORT_0" "=" "1" +End + +TOKEN + Name = "RC_PORT_6" + Value = "1" + Help = "Set to 'On' if PCH Root Complex Port #6 phisically enabled and connected on the board" + TokenType = Boolean + TargetH = Yes + Range = "On - Off" + Token = "RC_PORT_0" "=" "1" +End + +TOKEN + Name = "RC_PORT_7" + Value = "1" + Help = "Set to 'On' if PCH Root Complex Port #7 phisically enabled and connected on the board" + TokenType = Boolean + TargetH = Yes + Range = "On - Off" + Token = "RC_PORT_0" "=" "1" +End + +TOKEN + Name = "HOTPLUG_RMV_SUPPORT" + Value = "0" + Help = "Main switch if PCH Root Complex Port support _RMV function which is defined in ASL code. 0:Disable\1:Enable" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Token = "HOTPLUG_SUPPORT" "=" "1" +End + +ELINK + Name = "/D HOTPLUG_EOI_FLAG" + Parent = "GLOBAL_DEFINES" + InvokeOrder = AfterParent + Token = "HOTPLUG_RMV_SUPPORT" "=" "0" +End + +TOKEN + Name = "SX_NOTIFY_PWRB" + Value = "1" + Help = "Enable/Disable report notify power button event when system resume form sleep state." + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "PCIE_CLEAR_RETRAIN_BIT_SUPPORT" + Value = "0" + Help = "Main switch to clear PCH Root Port retrain bit for some device will not clear this bit. It will make 1 ms delay for each PCIE device 0:Disable\1:Enable" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes +End + +ELINK + Name = "/D PCIE_CLEAR_RETRAIN_BIT_SUPPORT_FLAG" + Parent = "GLOBAL_DEFINES" + InvokeOrder = AfterParent + Token = "PCIE_CLEAR_RETRAIN_BIT_SUPPORT" "=" "1" +End + +TOKEN + Name = " " + TokenType = Integer +End + +TOKEN + Name = "====== SB USB Rx Configuration ======" + TokenType = Expression +End + +TOKEN + Name = "PCI_EHCI_BUS_NUMBER" + Value = "0x0" + Help = "EHCI controller bus number" + TokenType = Integer + TargetH = Yes + Token = "USB_DEBUG_TRANSPORT" "=" "1" +End + +TOKEN + Name = "PCI_EHCI_DEV_FUNC_NUMBER" + Value = "0xD0" + Help = "EHCI controller device and function number. \Bit 0-2 represents function number and\ Bit 3-7 represents device number" + TokenType = Integer + TargetH = Yes + Token = "USB_DEBUG_TRANSPORT" "=" "1" +End + +TOKEN + Name = "PCI_EHCI_BAR_OFFSET" + Value = "0x10" + TokenType = Integer + TargetH = Yes + Token = "USB_DEBUG_TRANSPORT" "=" "1" +End + +TOKEN + Name = "EHCI_MMIO_BASE_ADDRESS" + Value = "$(EHCI_MMIO_BASE_ADDRESS1)" + TokenType = Integer + TargetH = Yes + Token = "PCI_EHCI_DEV_FUNC_NUMBER" "=" "0xD0" + Token = "USB_DEBUG_TRANSPORT" "=" "1" +End + +TOKEN + Name = "EHCI_MMIO_BASE_ADDRESS" + Value = "$(EHCI_MMIO_BASE_ADDRESS2)" + TokenType = Integer + TargetH = Yes + Token = "PCI_EHCI_DEV_FUNC_NUMBER" "=" "0xE8" + Token = "USB_DEBUG_TRANSPORT" "=" "1" +End + +TOKEN + Name = "EHCI_MMIO_BASE_ADDRESS1" + Value = "0xFECD0000" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "EHCI_MMIO_BASE_ADDRESS2" + Value = "$(EHCI_MMIO_BASE_ADDRESS1)+0xC00" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes +End + +TOKEN + Name = "EHCI_MMIO_SIZE" + Value = "0x400" + TokenType = Integer + TargetH = Yes + Token = "USB_DEBUG_TRANSPORT" "=" "1" +End + +TOKEN + Name = "CLOCK_GENERATOR_ADDRESS" + Value = "0xD2" + Help = "Clock generator address. Set to 0xFF to disable\clock generator programming." + TokenType = Integer + TargetH = Yes +End + +TOKEN + Name = "CLOCK_GENERATOR_SETTINGS" + Value = "{0x35, 0x83, 0xFF, 0xFF, 0xFC, 0x00, 0x00, 0x26, 0x03, 0x25, 0xFD, 0x56, 0x0D}" + Help = "List of initial clock controller register settings for Desktop." + TokenType = Expression + TargetH = Yes +End + +TOKEN + Name = " " + TokenType = Integer +End + +TOKEN + Name = "====== UEFI based Configuration ======" + TokenType = Expression +End + +TOKEN + Name = "OFFSET_0" + Value = "1" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_0" + Value = "0" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_1" + Value = "2" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_1" + Value = "1" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_2" + Value = "3" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_2" + Value = "2" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_3" + Value = "4" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_3" + Value = "3" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_4" + Value = "5" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_4" + Value = "4" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_5" + Value = "6" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_5" + Value = "5" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_6" + Value = "7" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_6" + Value = "6" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_7" + Value = "8" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_7" + Value = "7" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_8" + Value = "9" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_8" + Value = "8" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_9" + Value = "10" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_9" + Value = "9" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_10" + Value = "11" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_10" + Value = "10" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_11" + Value = "12" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_11" + Value = "11" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_12" + Value = "13" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_12" + Value = "12" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = "OFFSET_13" + Value = "14" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000" +End + +TOKEN + Name = "OFFSET_13" + Value = "13" + Help = "Offset 0 based in UEFI 2.1 and 1 based in UEFI 2.0" + TokenType = Integer + TargetMAK = Yes + TargetH = Yes + Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000" +End + +TOKEN + Name = " " + TokenType = Integer +End + +PATH + Name = "SB_CHIPSET_DIR" + Path = "Chipset\SB" +End + +TOKEN + Name = "INTEL_SATA_ASL_FILE" + Value = "$(SB_CHIPSET_DIR)\SATA.asl" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "INTEL_IDE_ASL_FILE" + Value = "$(SB_CHIPSET_DIR)\IDE.asl" + TokenType = Expression + TargetMAK = Yes +End + +PATH + Name = "SB_BOARD_DIR" + Path = "Board\SB" +End + +MODULE + Help = "Includes SB.mak to Project" + File = "SB.mak" +End + +ELINK + Name = "SBPEIDBG_Initialize," + Parent = "PeiDebuggerInitialize" + Priority = 10 + Token = "AMIDEBUG_RX_SUPPORT" "=" "1" + Token = "PeiDebugger_SUPPORT" "=" "1" + InvokeOrder = AfterParent +End + +# Only for Mobile/ULT CRB >>> +TOKEN + Name = "CRB_UART_CONFIG" + Value = "1" + Help = "Only for Mobile/ULT CRB UART configuration" + TokenType = Boolean + TargetMAK = Yes + Token = "PCH_SKU" "=" "1" + Token = "CRB_SIO_SUPPORT" "=" "0" + Token = "VirtualSerial_SUPPORT" "=" "1" + Token = "DEBUG_MODE" "=" "1" +End + +ELINK + Name = "SBPEIDBG_Initialize," + Parent = "PeiCoreInitialize" + Priority = 10 + Token = "PCH_SKU" "=" "1" + Token = "CRB_SIO_SUPPORT" "=" "0" + Token = "VirtualSerial_SUPPORT" "=" "1" + Token = "DEBUG_MODE" "=" "1" + InvokeOrder = AfterParent +End +# Only for Mobile/ULT CRB <<< + +ELINK + Name = "$(SB_CHIPSET_DIR)\SB.asl" + Parent = "INTEL_GENERIC_ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "\_SB.PCI0.SBRG.SPTS(Arg0)" + Parent = "ASL_PTS" + Help = "Include South Bridge Specific Function at PTS.\Arg0 is a sleep state the System is targeted for." + InvokeOrder = AfterParent +End + +ELINK + Name = "\_SB.PCI0.SBRG.SWAK(Arg0)" + Parent = "ASL_WAK" + Help = "Include South Bridge Specific Function at WAK.\Arg0 is a sleep state the System is resuming from. " + SrcFile = "Chipset\SB\SB.ASL" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(SB_BOARD_DIR)" + Parent = "$(GLOBAL_DEFINES)" + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(SB_CHIPSET_DIR)" + Parent = "$(GLOBAL_DEFINES)" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SBPEI.ffs" + Parent = "FV_BB" + Help = "INTEL ICH7 SB PEI component" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SBDXE.ffs" + Parent = "FV_MAIN" + Help = "INTEL ICH7 SB DXE component" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SBRUN.ffs" + Parent = "FV_MAIN" + Help = "INTEL ICH7 SB Runtime DXE component" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SBSATAIDE.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SBSECInit.OBJ" + Parent = "ADDON_SEC_CORE_OBJ_FILES" + Token = "INCLUDE_SB_ASM_FILE_IN_SEC" "=" "1" + InvokeOrder = AfterParent +End + +TOKEN + Name = "SBCSPLib" + Value = "$$(LIB_BUILD_DIR)\AmiSbCSPLib.lib" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "\_SB.SBPS(Arg0)" + Parent = "ASL_PTS" + Help = "Include South Bridge Specific Function at PTS." + SrcFile = "Chipset\SB\SLEEPBTN.ASL" + Token = "SLEEP_BUTTON_SUPPORT" "=" "1" + Token = "ACPI_SUPPORT" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(SB_CHIPSET_DIR)\RRIORDMA.ASL" + Parent = "INTEL_GENERIC_ASL" + Help = "Include LPC RRIO & RDMA ASL" + Token = "ACPI_SUPPORT" "=" "1" + Token = "ACPI_MODULE_VER" ">" "30" + InvokeOrder = AfterParent +End + +ELINK + Name = "UsbDxeDebuggerInitialize" + Token = "USB_DEBUG_TRANSPORT" "=" "1" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "SBPEIDBG_InitUsbEhci," + Parent = "PeiDebuggerInitialize" + Priority = 150 + Token = "USB_DEBUG_TRANSPORT" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "SBPEIDBG_InitUsbEhci," + Parent = "UsbDxeDebuggerInitialize" + Token = "USB_DEBUG_TRANSPORT" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "SBSmmSaveRestoreStates," + Parent = "SmmSaveRestoreEnvironment" + Token = "SMM_SUPPORT" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "{0, 0, 0x80, 0xff, ReadWriteCmosBank2}," + Parent = "CMOS_PORT_MAPPING" + Help = "Second bank CMOS access range (Registers in range: 0x80-0xff)" + Token = "CMOS_MANAGER_SUPPORT" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "SbGetRtcPowerStatus" + Parent = "CMOS_BATTERY_TEST_MAPPING" + Help = "Link the standard function to determine whether or not the CMOS battery is good." + Token = "CMOS_MANAGER_SUPPORT" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(SB_BOARD_DIR)\Sb.ssp" + Parent = "ADDON_SSP_FILES" + Token = "CMOS_MANAGER_SUPPORT" "=" "1" + InvokeOrder = AfterParent +End + +ELINK + Name = "SbConfigurationList" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "SbTimerSaveRestoreRegistersCallbacks" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "OEM_HDA_VERB_TABLE" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "OEM_SPI_VSCC_TABLE" + Help = "{VidDid, Vscc}" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "OEM_HDA_VERB_TABLE_CONTENT" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "SBIsDefaultConfigMode," + Parent = "IsDefaultConfigMode" + InvokeOrder = AfterParent +End + +ELINK + Name = "OEM_PCI_DEVICE_CALLBACK(0, 0, SBProtectedPciDevice)," + Parent = "OEM_SKIP_PCI_DEVICE" + InvokeOrder = AfterParent +End + +ELINK + Name = "OEM_PCI_DEVICE_CALLBACK(0, 0, SBProgramPciDevice)," + Parent = "OEM_PROGRAM_PCI_DEVICE" + InvokeOrder = AfterParent +End + +ELINK + Name = "OEM_PCI_DEVICE_CALLBACK(0, 0, SBUpdatePciDeviceAttributes)," + Parent = "OEM_PCI_ATTRIBUTES" + InvokeOrder = AfterParent +End + +ELINK + Name = "SECSB_EarlyInit" + Parent = "GainestownSecRcEntry" + Help = "SB Early Init in SEC (before Cache as memory enabling)" + SrcFile = "Board\SB\SBSECInit.ASM" + Token = "INCLUDE_SB_ASM_FILE_IN_SEC" "=" "1" + InvokeOrder = BeforeParent +End + +ELINK + Name = "{0xFFFFFFFF, 0, 0xFF, FALSE, 1, 0, DummyVerbTable}," + Parent = "OEM_HDA_VERB_TABLE" + Help = "Dummy Verb Table" + InvokeOrder = AfterParent +End + +ELINK + Name = "{0xEF4017, 0x2025}," + Parent = "OEM_SPI_VSCC_TABLE" + Help = "W25Q64" + InvokeOrder = AfterParent +End + +ELINK + Name = "BiosLockEnableSMIFlashHook," + Parent = "SMIFlashEndHandlerList" + InvokeOrder = AfterParent +End + +ELINK + Name = "SbS3WarmResetLink" + InvokeOrder = ReplaceParent + Token = "SecureMod_SUPPORT" "=" "1" +End + +ELINK + Name = "SBLib_BeforeShutdown," + Parent = "SbS3WarmResetLink" + InvokeOrder = AfterParent + Token = "SecureMod_SUPPORT" "=" "1" +End + +ELINK + Name = "BusOverrideGuidsforUefiRaid" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "SbRuntimeResetElinkList" + InvokeOrder = ReplaceParent +End + +ELINK + Name = "{0xBB65942B,0x521F,0x4EC3,0xBA,0xF9,0xA9,0x25,0x40,0xCF,0x60,0xD2}," + Parent = "BusOverrideGuidsforUefiRaid" + Help = "FFS Guid of Satacontroller Driver" + InvokeOrder = AfterParent +End + +ELINK + Name = "{0x8F5A2E02,0x538C,0x4D59,0xB9,0x20,0xC4,0x78,0x6A,0xCB,0xC5,0x52}," + Parent = "BusOverrideGuidsforUefiRaid" + Help = "FFS Guid of AHCI Driver" + InvokeOrder = AfterParent +End + +TOKEN + Name = "DISABLE_DAYLIGHT_SAVINGS" + Value = "0" + Help = "1: Disable Daylight Savings; 0: Enable Daylight Savings" + TokenType = Expression + TargetH = Yes +End + + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Board/SB/SBDXE.dxs b/Board/SB/SBDXE.dxs new file mode 100644 index 0000000..56151f0 --- /dev/null +++ b/Board/SB/SBDXE.dxs @@ -0,0 +1,76 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBDXE.dxs 1 2/08/12 8:22a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:22a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBDXE.dxs $ +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBDxe.DXS +// +// Description: This file is the dependency file for the SB DXE driver. +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <Protocol\Cpu.h> +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) +#include <Protocol\SmmAccess2.h> +#include <Protocol\S3SaveState.h> +#else +#include <Protocol\SmmAccess.h> +#include <AmiDxeLib.h> +#endif +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\Variable.h> +#include <token.h> + +DEPENDENCY_START + EFI_CPU_ARCH_PROTOCOL_GUID AND + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID AND +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) + EFI_SMM_ACCESS2_PROTOCOL_GUID AND + EFI_S3_SAVE_STATE_PROTOCOL_GUID AND +#else + EFI_SMM_ACCESS_PROTOCOL_GUID AND + EFI_BOOT_SCRIPT_SAVE_GUID AND +#endif + EFI_VARIABLE_WRITE_ARCH_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Board/SB/SBDXEBoard.c b/Board/SB/SBDXEBoard.c new file mode 100644 index 0000000..af6d133 --- /dev/null +++ b/Board/SB/SBDXEBoard.c @@ -0,0 +1,152 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBDXEBoard.c 1 2/08/12 8:22a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:22a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBDXEBoard.c $ +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBDxeBoard.C +// +// Description: This file contains DXE stage board component code for +// South Bridge. +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Efi.h> +#include <DXE.h> +#include <token.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <setup.h> +#include <AmiCspLib.h> + +// Produced Protocols + +// Consumed Protocols +#include <Protocol\PciIO.h> +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\BootScriptSave.h> + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +typedef VOID (SAVE_RESTORE_CALLBACK)( BOOLEAN Save ); + +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +SAVE_RESTORE_CALLBACK* SaveRestoreCallbackList[] = \ + { SAVE_RESTORE_CALLBACK_LIST NULL }; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +extern SAVE_RESTORE_CALLBACK SAVE_RESTORE_CALLBACK_LIST EndOfList; + +// Function Definition(s) + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SBDXE_BoardInit +// +// Description: This function initializes the board specific component in +// in the chipset South bridge +// +// Input: ImageHandle - Image handle +// SystemTable - Pointer to the system table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS SBDXE_BoardInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + InitAmiLib( ImageHandle, SystemTable ); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SaveRestoreRegisters +// +// Description: This function calls registered callbacks to save/restore +// registers value in timer interrupt routine +// +// Input: BOOLEAN Save - if TRUE - save registers, FALSE - restore back +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID SaveRestoreRegisters ( + IN BOOLEAN Save ) +{ + UINTN i; + + for (i = 0; SaveRestoreCallbackList[i] != NULL; i++) + SaveRestoreCallbackList[i]( Save ); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/SBPEI.dxs b/Board/SB/SBPEI.dxs new file mode 100644 index 0000000..ae04a72 --- /dev/null +++ b/Board/SB/SBPEI.dxs @@ -0,0 +1,65 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBPEI.dxs 1 2/08/12 8:22a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:22a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBPEI.dxs $ +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBPEI.DXS +// +// Description: This file is the dependency file for the SB PEI +// driver +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <pei.h> +#include <ppi\CpuIo.h> +#include <ppi\PciCfg2.h> +#include <ppi\CspLibPpi.h> +#include <Ppi\PchInit\PchInit.h> + +DEPENDENCY_START + EFI_PEI_CPU_IO_PPI_INSTALLED_GUID AND + EFI_PEI_PCI_CFG2_PPI_GUID AND + AMI_PEI_PCI_TABLE_INIT_PPI_GUID AND + PCH_INIT_PPI_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Board/SB/SBPEIBoard.c b/Board/SB/SBPEIBoard.c new file mode 100644 index 0000000..c9cc67b --- /dev/null +++ b/Board/SB/SBPEIBoard.c @@ -0,0 +1,343 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBPEIBoard.c 6 4/02/13 10:30a Scottyang $ +// +// $Revision: 6 $ +// +// $Date: 4/02/13 10:30a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBPEIBoard.c $ +// +// 6 4/02/13 10:30a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Follow Intel BIOS 114.4 GPIO setting at ULT platform. +// [Files] SB.sdl +// SBPEIBoard.c +// +// 5 1/17/13 3:33a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Correct ULT GPIO's help message +// [Files] SB.sdl +// SBPEIBoard.c +// +// 4 1/09/13 8:24a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Synchronous GPIO with Intel BIOS V104.2. +// [Files] SB.sdl +// SBPEIBoard.c +// +// 3 11/08/12 7:15a Scottyang +// [TAG] None +// [Category] New Feature +// [Description] Add token "PROGRAM_GPIO_TYPE" for select ULT GPIO +// program function(token or array directly). +// [Files] SB.sdl, SBPEIBoard.c +// +// 2 10/14/12 8:24a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] One rom for two chip and one chip. +// [Files] SPPEIBoard.c, SB.sd, SBDxe.c, SBPEI.c, PCH.asl +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBPeiBoard.C +// +// Description: This file contains PEI stage board component code for +// South Bridge. +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <Pei.h> +#include <token.h> +#include <AmiLib.h> +#include <Ppi\CspLibPpi.h> +#include <Ppi\SBPPI.h> +#include <AmiCspLib.h> +#include "Sb.h" + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +// GUID Definition(s) + +// PPI Definition(s) + +// PPI that are installed + +// PPI that are notified + +// External Declaration(s) + +// Function Definition(s) + +//---------------------------------------------------------------------------- + +//----------------------------------------------------------------------- +// SB : GPIO Initialize Table +//----------------------------------------------------------------------- +AMI_GPIO_INIT_TABLE_STRUCT stSB_GPIODefaultInitTable[] = +{ +// { OFFSET, VALUE } +#include <SBGPIO.h> +}; + +AMI_GPIO_INIT_TABLE_STRUCT stSB_GPIODefaultULTInitTable[] = +{ +#if defined (PROGRAM_GPIO_TYPE) && (PROGRAM_GPIO_TYPE == 1) && (ULT_SUPPORT == 1) +// { OFFSET, VALUE } + {0, ULT_GPIO_000}, + {1, ULT_GPIO_001}, + {2, ULT_GPIO_002}, + {3, ULT_GPIO_003}, + {4, ULT_GPIO_004}, + {5, ULT_GPIO_005}, + {6, ULT_GPIO_006}, + {7, ULT_GPIO_007}, + {8, ULT_GPIO_008}, + {9, ULT_GPIO_009}, + {10, ULT_GPIO_010}, + {11, ULT_GPIO_011}, + {12, ULT_GPIO_012}, + {13, ULT_GPIO_013}, + {14, ULT_GPIO_014}, + {15, ULT_GPIO_015}, + {16, ULT_GPIO_016}, + {17, ULT_GPIO_017}, + {18, ULT_GPIO_018}, + {19, ULT_GPIO_019}, + {20, ULT_GPIO_020}, + {21, ULT_GPIO_021}, + {22, ULT_GPIO_022}, + {23, ULT_GPIO_023}, + {24, ULT_GPIO_024}, + {25, ULT_GPIO_025}, + {26, ULT_GPIO_026}, + {27, ULT_GPIO_027}, + {28, ULT_GPIO_028}, + {29, ULT_GPIO_029}, + {30, ULT_GPIO_030}, + {31, ULT_GPIO_031}, + {32, ULT_GPIO_032}, + {33, ULT_GPIO_033}, + {34, ULT_GPIO_034}, + {35, ULT_GPIO_035}, + {36, ULT_GPIO_036}, + {37, ULT_GPIO_037}, + {38, ULT_GPIO_038}, + {39, ULT_GPIO_039}, + {40, ULT_GPIO_040}, + {41, ULT_GPIO_041}, + {42, ULT_GPIO_042}, + {43, ULT_GPIO_043}, + {44, ULT_GPIO_044}, + {45, ULT_GPIO_045}, + {46, ULT_GPIO_046}, + {47, ULT_GPIO_047}, + {48, ULT_GPIO_048}, + {49, ULT_GPIO_049}, + {50, ULT_GPIO_050}, + {51, ULT_GPIO_051}, + {52, ULT_GPIO_052}, + {53, ULT_GPIO_053}, + {54, ULT_GPIO_054}, + {55, ULT_GPIO_055}, + {56, ULT_GPIO_056}, + {57, ULT_GPIO_057}, + {58, ULT_GPIO_058}, + {59, ULT_GPIO_059}, + {60, ULT_GPIO_060}, + {61, ULT_GPIO_061}, + {62, ULT_GPIO_062}, + {63, ULT_GPIO_063}, + {64, ULT_GPIO_064}, + {65, ULT_GPIO_065}, + {66, ULT_GPIO_066}, + {67, ULT_GPIO_067}, + {68, ULT_GPIO_068}, + {69, ULT_GPIO_069}, + {70, ULT_GPIO_070}, + {71, ULT_GPIO_071}, + {72, ULT_GPIO_072}, + {73, ULT_GPIO_073}, + {74, ULT_GPIO_074}, + {75, ULT_GPIO_075}, + {76, ULT_GPIO_076}, + {77, ULT_GPIO_077}, + {78, ULT_GPIO_078}, + {79, ULT_GPIO_079}, + {80, ULT_GPIO_080}, + {81, ULT_GPIO_081}, + {82, ULT_GPIO_082}, + {83, ULT_GPIO_083}, + {84, ULT_GPIO_084}, + {85, ULT_GPIO_085}, + {86, ULT_GPIO_086}, + {87, ULT_GPIO_087}, + {88, ULT_GPIO_088}, + {89, ULT_GPIO_089}, + {90, ULT_GPIO_090}, + {91, ULT_GPIO_091}, + {92, ULT_GPIO_092}, + {93, ULT_GPIO_093}, + {94, ULT_GPIO_094}, + {95, ULT_GPIO_095}, +#else +// { OFFSET, VALUE("BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select.\BIT6:GPIO OWN - 0:ACPI driver/ 1:GPIO driver \ BIT7:GPIO LEB - 0: Edge Mode/ 1: Level Mode \BIT8: GPIO DIS - 0: Input seneing enable/ 1: Iutput seneing disable \BIT9~10 - 00: none/ 01:pull down/ 10: pull up/ 11: invalid ") } + {0, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {1, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {2, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {3, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {4, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {5, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {6, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {7, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {8, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {9, (IS_GPIO)|(IS_GPI)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {10, (IS_GPIO)|(IS_GPI)|(GPI_INV)}, + {11, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {12, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {13, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {14, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPIO_GPIWP_DOWN)|(GPIO_OWN_GPIO)}, + {15, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {16, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {17, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {18, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {19, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {20, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {21, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {22, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {23, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {24, (IS_GPIO)|(IS_GPI)|(GPIO_OWN_GPIO)|(GPIO_RESET)}, + {25, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {26, (IS_GPIO)|(IS_GPI)|(GPIO_OWN_GPIO)}, + {27, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPI_LEB_LEVEL)}, + {28, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {29, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {30, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {31, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {32, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {33, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {34, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPIO_OWN_GPIO)}, + {35, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(OUTPUT_HIGH)}, + {36, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {37, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {38, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {39, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {40, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {41, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {42, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {43, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {44, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {45, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {46, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {47, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPIO_OWN_GPIO)}, + {48, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {49, (IS_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {50, (IS_GPIO)|(IS_GPI)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {51, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {52, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {53, (IS_GPIO)|(IS_GPI)|(GPIO_OWN_GPIO)}, + {54, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {55, (IS_GPIO)|(IS_GPI)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {56, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {57, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {58, (IS_GPIO)|(IS_GPI)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {59, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {60, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {61, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {62, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {63, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {64, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {65, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {66, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {67, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {68, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {69, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {70, (IS_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {71, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {72, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {73, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {74, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {75, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {76, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {77, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {78, (IS_GPIO)|(IS_GPI)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {79, (IS_GPIO)|(IS_GPI)|(GPI_INV)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {80, (IS_GPIO)|(IS_GPI)|(GPI_LEB_LEVEL)|(GPIO_OWN_GPIO)}, + {81, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {82, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {83, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {84, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {85, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {86, (IS_GPIO)|(OUTPUT_LOW)|(GPI_LEB_LEVEL)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {87, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {88, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {89, (IS_GPIO)|(OUTPUT_HIGH)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {90, (IS_GPIO)|(OUTPUT_LOW)|(GPI_NDIS_DISABLE)|(GPIO_OWN_GPIO)}, + {91, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {92, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {93, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {94, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, + {95, (IS_NOT_GPIO)|(OUTPUT_HIGH)|(GPIO_OWN_GPIO)}, +#endif + {0xffff, 0xffff}, // End of the table. + +}; + +//---------------------------------------------------------------------------- + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/SBPeiDebugger.c b/Board/SB/SBPeiDebugger.c new file mode 100644 index 0000000..f6adc7f --- /dev/null +++ b/Board/SB/SBPeiDebugger.c @@ -0,0 +1,1309 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBPeiDebugger.c 1 2/08/12 8:22a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:22a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBPeiDebugger.c $ +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +//<AMI_FHDR_START> +//---------------------------------------------------------------------------- +// +// Name: SBPeiDebugger.C +// +// Description: This file contains PEI stage board component code for +// Template SB +// +//---------------------------------------------------------------------------- +//<AMI_FHDR_END> + +#include <Efi.h> +#include <AmiLib.h> +#include <Token.h> +#include "SB.h" +#include <PchAccess.h> + +#include "AmiDebugPort.h" + +#define EHCI_DEV_FUN_1A_7 0xD7 //1A Func 7 +#define EHCI_DEV_FUN_1A_0 0xD0 //1A Func 0 +#define EHCI_DEV_FUN_1D_7 0xEF //1D Func 7 +#define EHCI_DEV_FUN_1D_0 0xE8 //1D Func 0 +#define SMBUS_DEV_FUN (0x1F << 3) + 3 //1F Func 3 +#define THERMAL_DEV_FUN_1F_6 (0x1F << 3) + 6 //1F Func 6 + +#define ICH5_PMCSR 0x8000 +#define PWR_MGT_CAP_ID 1 +#define DBG_PRT_CAP_ID 0xA +#define TIMER_CONTROL_PORT 0x43 +#define TIMER0_COUNT_PORT 0x40 +#define B_PCH_LPC_RID_0 0xFF +#define V_PCH_LPC_RID_0 0x00 +#define R_PCH_THERMAL_TBARB 0x40 +#define R_PCH_THERMAL_TBARBH 0x44 + +// Function Prototypes +UINT8 ReadPCIRegByte(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc); +UINT16 ReadPCIRegWord(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc); +UINT32 ReadPCIRegDWord(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc); +VOID WritePCIRegByte(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc, UINT8 val); +VOID OrPCIRegByte(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc, UINT8 val); +VOID WritePCIRegWord(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc, UINT16 val); +VOID WritePCIRegDWord(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc, UINT32 val); +VOID OrPCIRegDWord(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc, UINT32 val); +VOID ANDPCIRegDWord(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc, UINT32 val); +VOID ANDPCIRegByte(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc, UINT8 val); +VOID OrWritePCIRegByte(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc, UINT8 val); + +UINT32 GetPCIAddrFormat(UINT8 RegNum,UINT8 BusNum,UINT8 DevFunc); +UINT8 FindCapPtr(UINT8 Bus, UINT8 DevFunc, UINT8 CapId); +VOID PEI8259WriteMask(UINT16 Mask, UINT16 EdgeLevel); +VOID PEI8259SetVectorBase (UINT8 MasterBase, UINT8 SlaveBase); +VOID Program8254Timer0(UINT16 Count); + +//Macros for Mmio Read/Write + +#define Mmio32(Address) (*(volatile UINT32*)(UINTN)(Address)) +#define MmioOr32(Address, Value) (*(volatile UINT32*)(UINTN)(Address) |= (Value)) +#define MmioAnd32(Address, Value) (*(volatile UINT32*)(UINTN)(Address) &= (Value)) + +#define R_PCH_SMBUS_BASE 0x20 +#define R_PCH_SMBUS_PCICMD 0x04 +#define B_PCH_SMBUS_PCICMD_IOSE BIT0 + +#define R_PCH_SMBUS_HOSTC 0x40 +#define B_PCH_SMBUS_HOSTC_SSRESET BIT3 +#define B_PCH_SMBUS_HOSTC_I2C_EN BIT2 +#define B_PCH_SMBUS_HOSTC_SMI_EN BIT1 +#define B_PCH_SMBUS_HOSTC_HST_EN BIT0 + + +// +// SMBus I/O Registers +// +#define R_PCH_SMBUS_HSTS 0x00 // Host Status Register R/W +#define B_PCH_SMBUS_HBSY 0x01 +#define B_PCH_SMBUS_INTR 0x02 +#define B_PCH_SMBUS_DERR 0x04 +#define B_PCH_SMBUS_BERR 0x08 +#define B_PCH_SMBUS_FAIL 0x10 +#define B_PCH_SMBUS_SMBALERT_STS 0x20 +#define B_PCH_SMBUS_IUS 0x40 +#define B_PCH_SMBUS_BYTE_DONE_STS 0x80 +#define B_PCH_SMBUS_HSTS_ALL 0xFF +#define R_PCH_SMBUS_HCTL 0x02 // Host Control Register R/W +#define B_PCH_SMBUS_INTREN 0x01 +#define B_PCH_SMBUS_KILL 0x02 + +#define STALL_PERIOD 10 // 10 microseconds +#define STALL_TIME 1000000 // 1,000,000 microseconds = 1 second +#define BUS_TRIES 3 // How many times to retry on Bus Errors + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmbusGetIoBase +// +// Description: Get SMBUS IO Base address +// +// Input: None +// +// Output: Rerturn SMBUS IO Base Address +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 +SmbusGetIoBase (VOID) +{ + return SMBUS_BASE_ADDRESS; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmbusIoRead +// +// Description: This function provides a standard way to read PCH Smbus IO registers. +// +// Input: Offset - Register offset from Smbus base IO address. +// +// Output: Returns data read from IO. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +SmbusIoRead (IN UINT8 Offset) +{ + return IoRead8 ((UINT16)(SmbusGetIoBase () + Offset)); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmbusIoWrite +// +// Description: This function provides a standard way to write PCH Smbus IO registers. +// +// Input: Offset - Register offset from Smbus base IO address. +// Data - Data to write to register. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +SmbusIoWrite ( + IN UINT8 Offset, + IN UINT8 Data +) +{ + // + // Write New Value + // + IoWrite8 ((UINT16)(SmbusGetIoBase () + Offset), Data); + return ; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PchPmTimerStall +// +// Description: Delay for at least the request number of microseconds. +// +// Input: Usec - Number of microseconds to delay. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID PchPmTimerStall (IN UINTN Usec) +{ + UINTN Counter = Usec * 3; + UINTN i; + UINT32 Data32; + UINT32 PrevData; + + PrevData = IoRead32(PM_BASE_ADDRESS + 8); + for (i=0; i < Counter; ) { + Data32 = IoRead32(PM_BASE_ADDRESS + 8); + if (Data32 < PrevData) { // Reset if there is a overlap + PrevData=Data32; + continue; + } + i += (Data32 - PrevData); + PrevData=Data32; + } + + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: IoDone +// +// Description: This function provides a standard way to write PCH Smbus IO registers. +// +// Input: *StsReg - Not used for input. +// +// Output: On return, contains the value of the SMBus status register. +// Returns TRUE if transaction is complete, FALSE otherwise. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN IoDone (IN OUT UINT8 *StsReg) +{ + // + // Wait for IO to complete + // + UINTN StallIndex; + UINTN StallTries; + + StallTries = STALL_TIME / STALL_PERIOD; + + for (StallIndex = 0; StallIndex < StallTries; StallIndex++) { + *StsReg = SmbusIoRead (R_PCH_SMBUS_HSTS); + if (*StsReg & (B_PCH_SMBUS_INTR | B_PCH_SMBUS_BYTE_DONE_STS | B_PCH_SMBUS_DERR | B_PCH_SMBUS_BERR)) { + return TRUE; + } else { + PchPmTimerStall (STALL_PERIOD); + } + } + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: AcquireBus +// +// Description: Check if it's ok to use the bus. +// +// Input: None +// +// Output: EFI_TIMEOUT - SmBus is busy, it's not safe to send commands. +// EFI_SUCCESS - SmBus is acquired and it's safe to send commands. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS AcquireBus (VOID) +{ + UINT8 StsReg; + + StsReg = 0; + StsReg = SmbusIoRead (R_PCH_SMBUS_HSTS); + if (StsReg & B_PCH_SMBUS_IUS) { + return EFI_TIMEOUT; + } else if (StsReg & B_PCH_SMBUS_HBSY) { + // + // Clear Status Register and exit + // + SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL); + return EFI_TIMEOUT; + } else { + // + // Clear out any odd status information (Will Not Clear In Use) + // + SmbusIoWrite (R_PCH_SMBUS_HSTS, StsReg); + return EFI_SUCCESS; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmbusExec +// +// Description: This function provides a standard way to execute Smbus protocols +// as defined in the SMBus Specification. +// +// Input: *Length - How many bytes to read. Must be 0 <= Length <= 32 depending on Operation +// It will contain the actual number of bytes read/written. +// *Buffer - Contain the data read/written. +// +// Output: EFI_SUCCESS - The operation completed successfully. +// EFI_INVALID_PARAMETER - Length or Buffer is NULL for any operation besides +// quick read or quick write. +// EFI_CRC_ERROR - Failed due to CRC error. +// EFI_DEVICE_ERROR - There was an Smbus error (NACK) during the operation. +// This could indicate the slave device is not present +// or is in a hung condition. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +SmbusExec ( + IN OUT UINTN *Length, + IN OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 AuxcReg; + UINT8 AuxStsReg; + UINT8 SmbusOperation; + UINT8 StsReg; + UINT8 SlvAddrReg; + UINT8 HostCmdReg; + UINT8 BlockCount; + UINTN Index; + UINTN BusIndex; + UINT8 *CallBuffer; + UINT8 ClockAddress = CLOCK_GENERATOR_ADDRESS; + + + CallBuffer = Buffer; + BlockCount = 0; + + // + // See if its ok to use the bus based upon INUSE_STS bit. + // + Status = AcquireBus (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // This is the main operation loop. If the operation results in a Smbus + // collision with another master on the bus, it attempts the requested + // transaction again at least BUS_TRIES attempts. + // + for (BusIndex = 0; BusIndex < BUS_TRIES; BusIndex++) { + // + // Operation Specifics (pre-execution) + // + Status = EFI_SUCCESS; + SmbusOperation = V_PCH_SMBUS_SMB_CMD_QUICK; + SlvAddrReg = (UINT8) (ClockAddress | 1); + HostCmdReg = 0; + AuxcReg = 0; + + SmbusIoWrite (R_PCH_SMBUS_HD0, *(UINT8 *) Length); + SlvAddrReg--; + BlockCount = (UINT8) (*Length); + + // The "break;" command is not present here to allow code execution + // do drop into the next case, which contains common code to this case. + SmbusOperation = V_PCH_SMBUS_SMB_CMD_BLOCK; + if ((*Length < 1) || (*Length > 32)) { + Status = EFI_INVALID_PARAMETER; + } + + AuxcReg |= B_PCH_SMBUS_E32B; + + // + // Set Auxiliary Control register + // + SmbusIoWrite (R_PCH_SMBUS_AUXC, AuxcReg); + + // + // Reset the pointer of the internal buffer + // + SmbusIoRead (R_PCH_SMBUS_HCTL); + + // + // Now that the 32 byte buffer is turned on, we can write th block data + // into it + // + for (Index = 0; Index < BlockCount; Index++) { + // + // Write next byte + // + SmbusIoWrite (R_PCH_SMBUS_HBD, CallBuffer[Index]); + } + // + // Set SMBus slave address for the device to send/receive from + // + SmbusIoWrite (R_PCH_SMBUS_TSA, SlvAddrReg); + + // + // Set Command register + // + SmbusIoWrite (R_PCH_SMBUS_HCMD, HostCmdReg); + + // + // Set Control Register (Initiate Operation, Interrupt disabled) + // + SmbusIoWrite (R_PCH_SMBUS_HCTL, (UINT8) (SmbusOperation + B_PCH_SMBUS_START)); + + // + // Wait for IO to complete + // + if (!IoDone (&StsReg)) { + Status = EFI_TIMEOUT; + break; + } else if (StsReg & B_PCH_SMBUS_DERR) { + AuxStsReg = SmbusIoRead (R_PCH_SMBUS_AUXS); + if (AuxStsReg & B_PCH_SMBUS_CRCE) { + Status = EFI_CRC_ERROR; + } else { + Status = EFI_DEVICE_ERROR; + } + break; + } else if (StsReg & B_PCH_SMBUS_BERR) { + // + // Clear the Bus Error for another try + // + Status = EFI_DEVICE_ERROR; + SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR); + // + // Clear Status Registers + // + SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL); + SmbusIoWrite (R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE); + // + // If bus collision happens, stall some time, then try again + // Here we choose 10 milliseconds to avoid MTCP transfer. + // + PchPmTimerStall (STALL_PERIOD); + continue; + } + + // + // successfull completion + // Operation Specifics (post-execution) + // + SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BYTE_DONE_STS); + + if ((StsReg & B_PCH_SMBUS_BERR) && (Status != EFI_BUFFER_TOO_SMALL)) { + // + // Clear the Bus Error for another try + // + Status = EFI_DEVICE_ERROR; + SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_BERR); + // + // If bus collision happens, stall some time, then try again + // Here we choose 10 milliseconds to avoid MTCP transfer. + // + PchPmTimerStall (STALL_PERIOD); + continue; + } else { + break; + } + } + + // + // Clear Status Registers and exit + // + SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL); + SmbusIoWrite (R_PCH_SMBUS_AUXS, B_PCH_SMBUS_CRCE); + SmbusIoWrite (R_PCH_SMBUS_AUXC, 0); + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmbusInit +// +// Description: Initialize SMBUS. +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SmbusInit(VOID) +{ + UINT8 ConfigurationTableDefault[] = CLOCK_GENERATOR_SETTINGS; + UINTN Length = sizeof (ConfigurationTableDefault); + // + // set the BAR & I/O space enable ourselves + // + WritePCIRegDWord(R_PCH_SMBUS_BASE, 0, SMBUS_DEV_FUN,(UINT32)SMBUS_BASE_ADDRESS); + OrWritePCIRegByte(R_PCH_SMBUS_PCICMD, 0, SMBUS_DEV_FUN,(UINT8) B_PCH_SMBUS_PCICMD_IOSE); + + // + // Reset the SMBus host controller + // + OrWritePCIRegByte(B_PCH_SMBUS_HOSTC_SSRESET, 0, SMBUS_DEV_FUN,(UINT8) R_PCH_SMBUS_HOSTC); + + // + // Enable the SMBus host controller + // + ANDPCIRegByte(R_PCH_SMBUS_HOSTC, 0, SMBUS_DEV_FUN,(UINT8)((B_PCH_SMBUS_HOSTC_SMI_EN | B_PCH_SMBUS_HOSTC_I2C_EN))); + OrWritePCIRegByte(R_PCH_SMBUS_HOSTC, 0, SMBUS_DEV_FUN,(UINT8) B_PCH_SMBUS_HOSTC_HST_EN); + + // + // Clear Status Register before anyone uses the interfaces + // + SmbusIoWrite (R_PCH_SMBUS_HSTS, B_PCH_SMBUS_HSTS_ALL); + + // + //Do the RedFort CRB Clock Programming + // + SmbusExec(&Length, ConfigurationTableDefault); + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InitEhciDebugPort +// +// Description: Initialize PCH EHCI. +// +// Input: None +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID InitEhciDebugPort(VOID) +{ + UINT32 Rcba = SB_RCBA; + + MmioOr32 ((UINTN)(Rcba + 0x3598), BIT0); + Mmio32 ((UINTN)(Rcba + 0x3598)); + OrPCIRegDWord(0xF4, 0, EHCI_DEV_FUN_1D_7,(UINT32)(BIT31) ); + OrPCIRegDWord(0xF4, 0, EHCI_DEV_FUN_1D_7,(UINT32) (BIT16 | BIT17 | BIT18 | BIT19)); + ANDPCIRegDWord(0xF4, 0, EHCI_DEV_FUN_1D_7,(UINT32) (BIT31)); + OrPCIRegDWord(0xF4, 0, EHCI_DEV_FUN_1A_7,(UINT32) (BIT31) ); + OrPCIRegDWord(0xF4, 0, EHCI_DEV_FUN_1A_7,(UINT32) (BIT16 | BIT17 | BIT18 | BIT19)); + ANDPCIRegDWord(0xF4, 0, EHCI_DEV_FUN_1A_7,(UINT32) (BIT31)); + // + //Enable RMH + // + MmioAnd32 ((UINTN)(Rcba + 0x3598), (UINT32)(~BIT0)); + Mmio32 ((UINTN)(Rcba + 0x3598)); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBPEIDBG_InitUsbEhci +// +// Description: This eLink function is used to initialize the EHCI controller +// debug port for USB PEI Debugging. It also fills the transport +// interface structure with appropriate information +// +// Input: DebugPort Debug transport interface structure +// +// Output: EFI_STATUS +// +// Notes: PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +#ifdef USB_DEBUGGER + +EFI_STATUS +SBPEIDBG_InitUsbEhci ( + IN OUT PEI_DBG_PORT_INFO *DebugPort +) +{ + UINT8 PwrMgtCapReg; + UINT8 DbgPrtCapReg; + UINT16 CmdReg; + UINT16 DbgPrtBaseOffset; + UINT32 EhciBaseAddress = 0; + + if (DebugPort->UsbDebugPort.USBBaseAddr) + EhciBaseAddress = DebugPort->UsbDebugPort.USBBaseAddr; + else + EhciBaseAddress = EHCI_MMIO_BASE_ADDRESS; + + InitEhciDebugPort(); + + //Clear Thermal Base + WritePCIRegDWord(R_PCH_THERMAL_TBARB, 0, THERMAL_DEV_FUN_1F_6, 0); + WritePCIRegDWord(R_PCH_THERMAL_TBARBH, 0, THERMAL_DEV_FUN_1F_6, 0); + + SmbusInit(); + + //First disable the EHCI device by programming PCI command register + CmdReg = ReadPCIRegWord(0x4, PCI_EHCI_BUS_NUMBER, PCI_EHCI_DEV_FUNC_NUMBER); + + if(CmdReg & 2) { + WritePCIRegWord(0x4, PCI_EHCI_BUS_NUMBER, PCI_EHCI_DEV_FUNC_NUMBER, 0); + } + + // Assign MMIO base address register in appropriate PCI register + WritePCIRegDWord(0x10, PCI_EHCI_BUS_NUMBER, PCI_EHCI_DEV_FUNC_NUMBER, EhciBaseAddress); + + //Set the Power state of the device to D0 + PwrMgtCapReg = FindCapPtr(PCI_EHCI_BUS_NUMBER, PCI_EHCI_DEV_FUNC_NUMBER, PWR_MGT_CAP_ID); + + WritePCIRegWord(PwrMgtCapReg + 4, PCI_EHCI_BUS_NUMBER, PCI_EHCI_DEV_FUNC_NUMBER, ICH5_PMCSR); + + // Enable ICH5 EHCI register & make it Bus master + CmdReg = CmdReg | 0x06; + WritePCIRegWord(0x4, PCI_EHCI_BUS_NUMBER, PCI_EHCI_DEV_FUNC_NUMBER, CmdReg); + + // Locate the Debug port register Interface location + DbgPrtCapReg = FindCapPtr(PCI_EHCI_BUS_NUMBER, PCI_EHCI_DEV_FUNC_NUMBER, DBG_PRT_CAP_ID); + DbgPrtBaseOffset = ReadPCIRegWord(DbgPrtCapReg + 2, PCI_EHCI_BUS_NUMBER, PCI_EHCI_DEV_FUNC_NUMBER); + DbgPrtBaseOffset &= 0x1fff; + + if (DebugPort->UsbDebugPort.USBBaseAddr == 0) { + DebugPort->UsbDebugPort.USBBaseAddr = EHCI_MMIO_BASE_ADDRESS; + DebugPort->UsbDebugPort.MemoryMappedIoSpaceSize = EHCI_MMIO_SIZE; + } + DebugPort->UsbDebugPort.USBDebugPortStartAddr = EhciBaseAddress + DbgPrtBaseOffset; + DebugPort->UsbDebugPort.PciBusNumber = PCI_EHCI_BUS_NUMBER; + DebugPort->UsbDebugPort.PciDeviceNumber = (PCI_EHCI_DEV_FUNC_NUMBER >> 3); + DebugPort->UsbDebugPort.PciFunctionNumber = PCI_EHCI_DEV_FUNC_NUMBER & 0x7; + DebugPort->UsbDebugPort.PciBAROffset = PCI_EHCI_BAR_OFFSET; + DebugPort->UsbDebugPort.InitUSBEHCI = SBPEIDBG_InitUsbEhci; + + return EFI_SUCCESS; +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: EnableSerialIRQ +// +// Description: This function programs the SB register to enable the serial +// IRQ +// +// Input: None +// +// Output: None +// +// Notes: PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +EnableSerialIRQ (VOID) +{ + WritePCIRegByte (R_PCH_LPC_SERIRQ_CNT,0x00, 0xf8, 0xD0); // Device 31 , Function 0 , Bus 0 , Reg 64h, Value d0 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: Enable_LPC_IO_Decode +// +// Description: This function programs the SB register to enable the LPC IO +// Decoding ranges to enable the programming of SIO and Serial Port. +// +// Input: None +// +// Output: None +// +// Notes: PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +Enable_LPC_IO_Decode (VOID) +{ + UINT32 GEN1_DEC = 0,GEN2_DEC = 0; + UINT16 LPC_EN = 0, LPC_IO_DEC = 0; + +#if SIO_SUPPORT && Smsc1007_PME_BASE_ADDRESS +// Enable SIO Runtime Register decode + GEN1_DEC = ReadPCIRegDWord(R_PCH_LPC_GEN1_DEC, 0x00, 0xf8); + GEN1_DEC |= 0xFFFFFFFF & ((0x7C << 16) | ((Smsc1007_PME_BASE_ADDRESS & 0xFFF0) + 1)); + WritePCIRegDWord (R_PCH_LPC_GEN1_DEC, 0x00, 0xf8, GEN1_DEC); +#endif + +// Enables SIO Configuration Ports decode + GEN2_DEC = ReadPCIRegDWord (R_PCH_LPC_GEN2_DEC, 0x00, 0xf8); + GEN2_DEC |= 0xFFFFFFFF & ((0x0C << 16) | ((0x16 << 8) | 0x41)); + WritePCIRegDWord (R_PCH_LPC_GEN2_DEC, 0x00, 0xf8, GEN2_DEC); + + +// Enable COMA decode + LPC_EN = ReadPCIRegWord (R_PCH_LPC_ENABLES, 0x00, 0xf8); //82h + LPC_EN |= 0x0001; + WritePCIRegWord (R_PCH_LPC_ENABLES, 0x00, 0xf8, LPC_EN); + + LPC_IO_DEC = ReadPCIRegWord (R_PCH_LPC_IO_DEC, 0x00, 0xf8); //80h + LPC_IO_DEC &= 0xFF00; + WritePCIRegWord (R_PCH_LPC_IO_DEC, 0x00, 0xf8, LPC_IO_DEC); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ProgramACPIBaseToDisableTCO +// +// Description: This function programs the SB register to disable +// the TCO timer. If this timer is not disabled the system +// will shutdown or reset as soon as the timer is expired +// +// Input: None +// +// Output: None +// +// Notes: PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ProgramACPIBaseToDisableTCO (VOID) +{ + UINT32 dData; + UINT16 TCOBASE; + + dData = PM_BASE_ADDRESS; //Port base addr Value of SDL token + + WritePCIRegDWord(0x40, //ACPI Base Addr (LPC I/F D31:F0) + 0, //bus # + (UINT8)((31 << 3) | 0), //dev & func # + dData); + + TCOBASE = (UINT16)(dData + 0x60); //TCO base addr = 0xFF80 + 0x60 + + // + //Now! Enable the decode of IO range pointed by ACPI base address. + // (Note: ACPI power management function is also enabled) + dData = 0x00000080; //bit 4 = 1 to enable ACPI + + WritePCIRegDWord(0x44, //ACPI_CNTL - ACPI control (LPC I/F D31:F0) + 0, //bus # + (UINT8)((31 << 3) | 0), //dev & func # + dData); + + // Halt the TCO timer + IoWrite16(TCOBASE + 8, IoRead16(TCOBASE + 8) | 0x0800); //TCOBASE+8 = TCO1 control register + IoWrite16(TCOBASE + 6, IoRead16(TCOBASE + 6) | 0x0002); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SBPEIDBG_Initialize +// +// Description: This eLink function is used to initialize the South Bridge +// for PEI Debugger support +// +// Input: DebugPort Debug transport interface structure +// +// Output: EFI_STATUS +// +// Notes: Normally no PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +SBPEIDBG_Initialize ( + IN OUT PEI_DBG_PORT_INFO *DebugPort +) +{ + //Program the TCO IO to avoid rebooting of the hardware + ProgramACPIBaseToDisableTCO(); + + // Init 8259 Controller + PEI8259SetVectorBase (LEGACY_MODE_BASE_VECTOR_MASTER, LEGACY_MODE_BASE_VECTOR_SLAVE ); //testing + + // Set all 8259 Interrupts to edge triggered and disabled + PEI8259WriteMask (0xffff , 0x0000); + + Enable_LPC_IO_Decode(); + + EnableSerialIRQ(); + Program8254Timer0(0); + return EFI_SUCCESS; +} + +/** +//---------------------------------------------------------------------------- + NO PORTING IS GENERALLY REQUIRED FOR THE ROUTINES BELOW. +//---------------------------------------------------------------------------- + **/ + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetPCIAddrFormat +// +// Description: Converts the provided bus, device, function and register +// number of a PCI register into 32bit PCI access format +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// +// Output: Converted 32 bit PCI register access value +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 +GetPCIAddrFormat( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc +) +{ + UINT32 addr; + + addr = ((UINT32) (( (UINT16) BusNum ) << 8) + DevFunc) << 8; + addr += (RegNum & 0xfc); + addr |= 0x80000000; + return addr; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ReadPCIRegByte +// +// Description: Reads a byte value from the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// +// Output: Byte read +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 +ReadPCIRegByte( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + + IoWrite32(0xcf8, PciAddr); + return IoRead8(0xcfc +(RegNum & 0x3)); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ReadPCIRegWord +// +// Description: Reads a word value from the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// +// Output: Word read +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT16 +ReadPCIRegWord( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + + IoWrite32(0xcf8, PciAddr); + return IoRead16(0xcfc +(RegNum & 0x3)); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ReadPCIRegDWord +// +// Description: Reads a double word value from the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// +// Output: Double word read +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 +ReadPCIRegDWord( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + + IoWrite32(0xcf8, PciAddr); + return IoRead32(0xcfc +(RegNum & 0x3)); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: WritePCIRegByte +// +// Description: Writes a byte value to the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// Val Value to write to the PCI address space +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +WritePCIRegByte( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc, + IN UINT8 val +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + + IoWrite32(0xcf8, PciAddr); + IoWrite8(0xcfc +(RegNum & 0x3), val); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: OrWritePCIRegByte +// +// Description: Or a byte value to the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// Val Value to write to the PCI address space +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +OrWritePCIRegByte( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc, + IN UINT8 val +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + UINT8 Value; + + IoWrite32(0xcf8, PciAddr); + Value=IoRead8(0xcfc +(RegNum & 0x3)); + Value|=val; + IoWrite32(0xcf8, PciAddr); + IoWrite8(0xcfc +(RegNum & 0x3), Value); + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: OrPCIRegByte +// +// Description: Or a byte value to the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// Val Value to write to the PCI address space +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +OrPCIRegByte( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc, + IN UINT8 val +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + UINT8 Value; + + + IoWrite32(0xcf8, PciAddr); + Value=IoRead8(0xcfc +(RegNum & 0x3)); + Value |=val; + IoWrite32(0xcf8, PciAddr); + IoWrite8(0xcfc +(RegNum & 0x3), Value); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ANDPCIRegByte +// +// Description: And a byte value to the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// Val Value to write to the PCI address space +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +ANDPCIRegByte( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc, + IN UINT8 val +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + UINT8 Value; + + + IoWrite32(0xcf8, PciAddr); + Value=IoRead8(0xcfc +(RegNum & 0x3)); + Value &=~val; + IoWrite32(0xcf8, PciAddr); + IoWrite8(0xcfc +(RegNum & 0x3), Value); +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: WritePCIRegWord +// +// Description: Writes a word value to the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// Val Value to write to the PCI address space +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +WritePCIRegWord( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc, + IN UINT16 val +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + + IoWrite32(0xcf8, PciAddr); + IoWrite16(0xcfc +(RegNum & 0x3), val); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: WritePCIRegDword +// +// Description: Writes a double word value to the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// Val Value to write to the PCI address space +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +WritePCIRegDWord( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc, + IN UINT32 val +) +{ + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + + IoWrite32(0xcf8, PciAddr); + IoWrite32(0xcfc +(RegNum & 0x3), val); +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// Procedure: OrPCIRegDWord +// +// Description: Or a double word value to the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// Val Value to write to the PCI address space +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +OrPCIRegDWord( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc, + IN UINT32 val +) +{ + UINT32 Value; + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + + IoWrite32(0xcf8, PciAddr); + Value=IoRead32(0xcfc +(RegNum & 0x3)); + Value|=val; + IoWrite32(0xcf8, PciAddr); + IoWrite32(0xcfc +(RegNum & 0x3), Value); + + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ANDPCIRegDWord +// +// Description: AND a double word value to the PCI address space +// +// Input: RegNum PCI Register number +// BusNum PCI Bus number +// DevFunc PCI Device and function number +// Val Value to write to the PCI address space +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +ANDPCIRegDWord( + IN UINT8 RegNum, + IN UINT8 BusNum, + IN UINT8 DevFunc, + IN UINT32 val +) +{ + UINT32 Value; + UINT32 PciAddr = GetPCIAddrFormat(RegNum,BusNum,DevFunc); + + IoWrite32(0xcf8, PciAddr); + Value=IoRead32(0xcfc +(RegNum & 0x3)); + Value &=~val; + IoWrite32(0xcf8, PciAddr); + IoWrite32(0xcfc +(RegNum & 0x3), Value); + + return; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: FindCapPtr +// +// Description: This function searches the PCI address space for the PCI +// device specified for a particular capability ID and returns +// the offset in the PCI address space if one found +// +// Input: Bus PCI Bus number +// DevFunc PCI Device and function number +// CapId Capability ID to look for +// +// Output: Capability ID location if one found +// Otherwise returns 0 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 +FindCapPtr( + IN UINT8 Bus, + IN UINT8 DevFunc, + IN UINT8 CapId +) +{ + UINT8 Value; + UINT8 Reg; + + Value = ReadPCIRegByte(6, Bus, DevFunc); + + if (Value == 0xff) return 0; //No device. + if (!(Value & (1 << 4))) return 0; // Check if capabilities list. + + Reg = 0x34; // Register to First capabilities pointer + //if 0, then capabilities + for(;;) + { + Value = ReadPCIRegByte(Reg, Bus, DevFunc); + if (!Value) return 0; + + Reg = Value; // ptr to CapID + Value = ReadPCIRegByte(Reg, Bus, DevFunc); //If capablity ID, return register that points to it. + if (Value == CapId) return (UINT8)Reg; + + ++Reg; //equals to next capability pointer. + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PEI8259WriteMask +// +// Description: Writes PC 8259 interrupt Controller mask register +// +// Input: Mask Mask to write +// EdgeLevel Edge/level trigger to be programmed +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +PEI8259WriteMask ( + IN UINT16 Mask, + IN UINT16 EdgeLevel) +{ + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8)Mask); + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8)(Mask >> 8)); + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8)EdgeLevel); + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8)(EdgeLevel >> 8)); +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: PEI8259SetVectorBase +// +// Description: Set up the 8259 interrupt controller master and slave +// base values +// +// Input: MasterBase Master base to be programmed +// SlaveBase Slave base to be programmed +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +PEI8259SetVectorBase ( + IN UINT8 MasterBase, + IN UINT8 SlaveBase +) +{ + UINT8 Mask; + + // Initialize Slave interrupt controller. + Mask = IoRead8 (LEGACY_8259_MASK_REGISTER_SLAVE); + IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, 0x11); + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, SlaveBase); + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0x02); + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, 0x01); + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, Mask); + + // Initialize Master interrupt controller. + Mask = IoRead8 (LEGACY_8259_MASK_REGISTER_MASTER); + IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, 0x11); + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, MasterBase); + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0x04); + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, 0x01); + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, Mask); + + IoWrite8 (LEGACY_8259_CONTROL_REGISTER_SLAVE, LEGACY_8259_EOI); + IoWrite8 (LEGACY_8259_CONTROL_REGISTER_MASTER, LEGACY_8259_EOI); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: Program8254Timer0 +// +// Description: Programs the 8254 Timer channel 0 +// +// Input: Count Timer tick count +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID +Program8254Timer0( + IN UINT16 Count +) +{ + UINT8 LCntbyte,HCntbyte; + + LCntbyte = (UINT8)Count; + HCntbyte = (UINT8)(Count >> 8); + + //Write the timer control port to select timer 0 and set to mode 3 + IoWrite8(TIMER_CONTROL_PORT, 0x36); + + //Write the Counter 0 with initial count value + IoWrite8(TIMER0_COUNT_PORT, LCntbyte); + IoWrite8(TIMER0_COUNT_PORT, HCntbyte); + + //Enable the IRQ0 interrupt for this timer 0 in USB Xport module + //...... + +} + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Board/SB/SBRun.dxs b/Board/SB/SBRun.dxs new file mode 100644 index 0000000..390884a --- /dev/null +++ b/Board/SB/SBRun.dxs @@ -0,0 +1,55 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBRun.dxs 1 2/08/12 8:22a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:22a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBRun.dxs $ +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBRun.DXS +// +// Description: Dependency expression file for SBRun DXE driver +// +//<AMI_FHDR_END> +//************************************************************************* + +DEPENDENCY_START + TRUE +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/SBSECInit.asm b/Board/SB/SBSECInit.asm new file mode 100644 index 0000000..a65a50e --- /dev/null +++ b/Board/SB/SBSECInit.asm @@ -0,0 +1,389 @@ + TITLE SBSECInit.ASM -- South Bridge SEC initialization +;************************************************************************* +;************************************************************************* +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone: (770)-246-8600 ** +;** ** +;************************************************************************* +;************************************************************************* + +;************************************************************************* +; $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSECInit.asm 2 10/23/12 8:18a Scottyang $ +; +; $Revision: 2 $ +; +; $Date: 10/23/12 8:18a $ +;************************************************************************* +; Revision History +; ---------------- +; $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSECInit.asm $ +; +; 2 10/23/12 8:18a Scottyang +; [TAG] EIP73607 +; [Category] Bug Fix +; [Severity] Normal +; [Symptom] Intruder Detect state is cleaned by BIOS POST. +; [Files] SBDXE.c; SBSECInit.asm +; +; 1 2/08/12 8:22a Yurenlai +; Intel Lynx Point/SB eChipset initially releases. +; +;************************************************************************* +;<AMI_FHDR_START> +; +; Name: SBSECInit.ASM +; +; Description: Program any workaround or initialization needed before +; enabling Cache as memory in the SEC stage +; +;<AMI_FHDR_END> +;************************************************************************* + +;---------------------------------------------------------------------------- + INCLUDE token.equ +;---------------------------------------------------------------------------- + +.586P +.XMM +.MODEL SMALL + +; Externs +EXTERN SECSB_EarlyInitEnd:NEAR32 + +IFDEF MKF_ENABLE_NB_DMI_GEN2_IN_SEC +IF MKF_ENABLE_NB_DMI_GEN2_IN_SEC +EXTERN SECNB_DmiGen2Link:NEAR32 +ENDIF +ENDIF + +; Define the equates here +SB_BUS EQU 0 +SB_DEV_FUN EQU 0F8h + +SB_REG_RCBA EQU 0F0h + +RCRB_MMIO_GCS EQU 3410h ; General Control and Status +RCRB_RTC_CONF EQU 3400h ; RTC Configuration register + +TCO_IOREG_STS2 EQU 6 ; TCO Status 2 Register +TCO_IOREG_CNT1 EQU 8 ; TCO Control 1 Register + +;---------------------------------------------------------------------------- +; STARTUP_SEG S E G M E N T STARTS +;---------------------------------------------------------------------------- +STARTUP_SEG SEGMENT PARA PUBLIC 'CODE' USE32 + +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: SECSB_EarlyInit +; +; Description: This routine initializes South bridge for PEI preparation +; +; Input: ESP BIST Info +; EBP Reset ID (EDX at reset) +; Stack not available +; +; Output: None +; +; Modified: All, except EBP and ESP +; +; Notes: None of the chipset initialization is done at this point. +; System is exactly as if came out of RESET. +; 1. Enable Top of 4GB flash ROM access +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +SECSB_EarlyInit PROC PUBLIC + + mov al, 004h + out 80h, al +; Program 8259 Interrupt Controller to disable all interrupts + + mov al, 0FFh + out 021h, al + out 0EDh, al ; I/O Delay + out 0A1h, al + out 0EDh, al ; I/O Delay + mov al, 00h + out 92h, al + +; Determine if INIT or Hard Reset + +; mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 44h +; mov dx, 0CF8h +; out dx, eax +; mov dl, 0FCh +; in al, dx +; and al, 87h ; PM Base address had been enabled? +; jz isPowerOn ; No, is Power on. + +; Do a hard Reset if INIT. + +; mov dx, 0CF9h ; load dx with reset control reg +; in al, dx ; read its content +; or al, 02h ; set bit 1 +; out dx, al ; write it +; out 0edh, al ; I/O delay +; out 0edh, al ; I/O delay +; or al, 04h ; for HRST set bit 2 +; out dx, al ; write it +; jmp $ + +;isPowerOn: + +; Program PCH RCBA Base + + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 0F0h + out dx, eax + mov dl, 0FCh + mov eax, MKF_SB_RCRB_BASE_ADDRESS or 1 + out dx, eax + +; Program SPI prefetching and caching + mov dl, 0F8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 0DCh + out dx, eax + mov dl, 0FCh + in eax, dx + or eax, (MKF_SPI_READ_CONFIG shl 2) + out dx, eax + +; Program PM I/O Base Address + mov dl, 0F8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 040h + out dx, eax + mov dl, 0FCh + mov ax, MKF_PM_BASE_ADDRESS + out dx, ax + + mov dl, 0F8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 044h + out dx, eax + mov dl, 0FCh + mov al, 80h + out dx, al + +; Enable ROM Decode for SEC stage. + mov dl, 0F8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 0D8h + out dx, eax + mov dl, 0FDh + mov al, 0FFh ; Decode 4MB Always + out dx, al + +; Disable Auto-Reset Function + mov dx, MKF_TCO_BASE_ADDRESS + TCO_IOREG_CNT1 + in ax, dx + out 0edh, al ; I/O delay + or ah, 08t ; Set Bit[11] to disable TCO timer + out dx, ax + out 0edh, al ; I/O delay + + mov dx, MKF_TCO_BASE_ADDRESS + TCO_IOREG_STS2 + in ax, dx + out 0edh, al ; I/O delay + and al, 0FEh ; Skip Intrusion, [EIP73607] + or al, 02t ; Set Bit[1] to clear SECOND_TO_STS + out dx, ax + out 0edh, al ; I/O delay + + mov esi, MKF_SB_RCRB_BASE_ADDRESS + RCRB_RTC_CONF ; Enable Upper CMOS + mov byte ptr [esi], 04h + + mov esi, MKF_SB_RCRB_BASE_ADDRESS + RCRB_MMIO_GCS + mov byte ptr [esi], 60h or (MKF_RESERVED_PAGE_ROUTE shl 2) + +; Intel 6 Series Chipset/Intelr C200 Series Chipset/Patsburg Platform Controller Hub(PCH) +; BIOS Specification Update +; Revision 1.0.1 +; The System BIOS must perform the steps below early in the POST before +; generating any I/O or MMIO cycles that could be decoded by the PCI bridge +; device. +; 1. System BIOS must determine if the PCH supports the PCI Bridge device +; via the FVEC0 - Feature Vector Register 0 by following the steps below: +; a. Set D31:F0:Reg E4h[5:2] (Feature Vector Index) to "0". +; b. Read D31:F0:Reg E8h[31:0] (Feature Vector Data) +; c. If +; FVEC0[1] = 0b, PCI bridge device is enabled. +; else +; FVEC0[1] = 1b, PCI bridge device is disabled. + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 0E4h + out dx, eax + mov dl, 0FCh + mov eax, 0 ; Set the Enable bit. + out dx, eax + + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 0E8h + out dx, eax + mov dl, 0FCh + in eax, dx ; Read 0:1F:0:E8 + and eax, 02h ; Check if FVECT[1] == 1 + jz SkipDisableP2P ; No then leave PCI bridge + ; device enabled + +; 2. System BIOS must set the FD - Function disable register offset RCBA + +; 3418h bit 1 PCI Bridge Disable to 1b if the PCI bridge device is not +; supported by the PCH. + mov edi, MKF_SB_RCRB_BASE_ADDRESS + 3418h + or DWORD PTR [edi], 02h ; Else disabled the PCI + ; bridge device +SkipDisableP2P: + + +; Enable IO Decode range in SEC. +IF MKF_SB_IO_DECODE_IN_SEC + ;Enable LPC IO decoding + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 80h + out dx, eax + add dx, 04h + mov eax, 370F0010h + IFDEF MKF_EC_SUPPORT + or eax, (MKF_EC_SUPPORT shl 27t) ; Enable MC_LPC_EN + ENDIF + out dx, eax + + IFDEF MKF_SIO1_CONFIG_INDEX + IF ((MKF_SIO1_CONFIG_INDEX NE 2Eh) AND (MKF_SIO1_CONFIG_INDEX NE 4Eh)) + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 88h + out dx, eax + add dx, 04h + mov eax, (MKF_SIO1_CONFIG_INDEX and 0FFFCh) or 1; + out dx, eax + ENDIF + ENDIF + + IF MKF_SB_GEN_DECODE_RANGE_1 +; Enable decoding of PME & GPIO Runtime Registers as Generic Decode Range 1 + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 84h + out dx, eax + add dx, 04h + mov eax, ((MKF_SB_GEN_DECODE_RANGE_1 AND 0FFFFh) OR (0FCh SHL 16)) + bts eax, 0 + out dx, eax + ENDIF + + IF MKF_SB_GEN_DECODE_RANGE_2 +; Enable decoding of PME & GPIO Runtime Registers as Generic Decode Range 2 + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 88h + out dx, eax + add dx, 04h + mov eax, ((MKF_SB_GEN_DECODE_RANGE_2 AND 0FFFFh) OR (0FCh SHL 16)) + bts eax, 0 + out dx, eax + ENDIF + + IF MKF_SB_GEN_DECODE_RANGE_3 +; Enable decoding of PME & GPIO Runtime Registers as Generic Decode Range 3 + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 8Ch + out dx, eax + add dx, 04h + mov eax, ((MKF_SB_GEN_DECODE_RANGE_3 AND 0FFFFh) OR (0FCh SHL 16)) + bts eax, 0 + out dx, eax + ENDIF + + IF MKF_SB_GEN_DECODE_RANGE_4 +; Enable decoding of PME & GPIO Runtime Registers as Generic Decode Range 4 + mov dx, 0CF8h + mov eax, (1 shl 31t) + (SB_BUS shl 16t) + (SB_DEV_FUN shl 8) + 90h + out dx, eax + add dx, 04h + mov eax, ((MKF_SB_GEN_DECODE_RANGE_4 AND 0FFFFh) OR (0FCh SHL 16)) + bts eax, 0 + out dx, eax + ENDIF + +ENDIF ; IF MKF_SB_IO_DECODE_IN_SEC + + + jmp SECSB_EarlyInitEnd +SECSB_EarlyInit ENDP + +IFDEF MKF_ENABLE_NB_DMI_GEN2_IN_SEC +IF MKF_ENABLE_NB_DMI_GEN2_IN_SEC +;<AMI_PHDR_START> +;---------------------------------------------------------------------------- +; +; Procedure: SECSB_DmiGen2Init +; +; Description: This routine initializes South bridge DMI for PEI preparation +; +; Input: ESP BIST Info +; EBP Reset ID (EDX at reset) +; Stack not available +; +; Output: None +; +; Modified: All, except EBP and ESP +; +; Notes: None of the chipset initialization is done at this point. +; System is exactly as if came out of RESET. +; 1. Enable Top of 4GB flash ROM access +;---------------------------------------------------------------------------- +;<AMI_PHDR_END> + +SECSB_DmiGen2Init PROC PUBLIC + + ; Step 1 + ; RCBA + Offset 21A4h[3:0] = 0010b + mov esi, MKF_SB_RCRB_BASE_ADDRESS + 21A4h + mov al, byte ptr [esi] + and al, 0Fh + cmp al, 02h + jne SECSB_DmiGen2_Exit ; if SB DMI Gen != 0010b, jmp SECSB_DmiGen2_Exit + + ; Step 1.2.1 + ; Set RCBA + Offset 2340h[23:16] = 3Ah, Set Gen 2 Common Clock N_FTS + mov esi, MKF_SB_RCRB_BASE_ADDRESS + 2340h + mov eax, dword ptr [esi] + and eax, 0FF00FFFFh + or eax, (3ah SHL 16) + mov dword ptr [esi], eax + + ; Step 1.2.2 + ; Set RCBA + Offset 21B0h[3:0] = 0010b, Set target link speed as DMI Gen 2 + mov esi, MKF_SB_RCRB_BASE_ADDRESS + 21B0h + mov al, byte ptr [esi] + and al, NOT (0Fh) + or al, (1 SHL 1) + mov byte ptr [esi], al + +SECSB_DmiGen2_Exit: + jmp SECNB_DmiGen2Link +SECSB_DmiGen2Init ENDP +ENDIF +ENDIF +;---------------------------------------------------------------------------- +; STARTUP_SEG S E G M E N T ENDS +;---------------------------------------------------------------------------- +STARTUP_SEG ENDS +END + +;************************************************************************* +;************************************************************************* +;** ** +;** (C)Copyright 1985-2011, American Megatrends, Inc. ** +;** ** +;** All Rights Reserved. ** +;** ** +;** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +;** ** +;** Phone: (770)-246-8600 ** +;** ** +;************************************************************************* +;************************************************************************* diff --git a/Board/SB/SBSetup/SB.sd b/Board/SB/SBSetup/SB.sd new file mode 100644 index 0000000..521e9cc --- /dev/null +++ b/Board/SB/SBSetup/SB.sd @@ -0,0 +1,7876 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSetup/SB.sd 56 5/14/14 1:05p Barretlin $ +// +// $Revision: 56 $ +// +// $Date: 5/14/14 1:05p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSetup/SB.sd $ +// +// 56 5/14/14 1:05p Barretlin +// [TAG] EIP167028 +// [Category] Improvement +// [Description] Variable attribute improvement +// [Files] SB.sd SBDxe.c WdtAppDxe.c +// +// 55 3/24/14 9:04a Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] fix build error with old label thunderbolt module +// [Files] Sb.sd +// +// 54 3/13/14 10:59a Barretlin +// [TAG] EIP153695 +// [Category] Improvement +// [Description] USB Per port control is not reasonable when +// OEM_USBPREPORT_DISABLE_SUPPORT token is Enabled and USB devices are +// behind hubs +// [Files] Sb.sdl Sb.sd Sb.uni GetSetupData.c SbDxe.c PchUsbCommon.c +// PchRegsUsb.h +// +// 53 12/30/13 5:21a Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] Follow Intel BIOS rev.135 to change I2C device default +// value +// [Files] SB.sd SB.uni +// +// 52 12/30/13 3:23a Barretlin +// [TAG] EIP N/A +// [Category] Improvement +// [Description] Support Thunderbolt new feature - Change Thunderbolt AIC +// location in run time +// [Files] SB.sd +// +// 51 8/08/13 2:26a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove setup item which already has. +// [Files] SB.sd +// +// 50 8/01/13 4:35a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add PCIE LTR setup items. +// [Files] SB.sd, SB.uni, SBDxe.c, GetSetupData.c, SbSetupData.h +// +// 49 8/01/13 2:21a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Hidden and disable "SLP_LAN# low on DC power" for DT or +// sever platform. +// [Files] SB.sd +// +// 48 7/09/13 5:21a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create "PCH Cross Throttling" setup item.(Only ULT +// support) +// [Files] SBDxe.c, SB.sd, SB.uni, GetSetupData.c, SB.sd +// +// 47 7/03/13 8:04a Scottyang +// [TAG] EIP124410 +// [Category] Improvement +// [Description] Implement SMBIOS type 88h for CRID. +// [Files] SBDxe.c, SB.sdl, SB.sd, SBSetup.c, SBSetup.sdl +// +// 46 6/24/13 6:31a Scottyang +// [TAG] EIP127297 +// [Category] Improvement +// [Description] Update PCH RC 1.6.0. +// [Files] SB.sd, SBDxe.c, ..\ReferenceCode\Chipset\LynxPoint\*.* +// +// 45 6/19/13 3:48a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Support Lava Canyon CRB +// [Files] SB.sd +// +// 44 6/13/13 11:55p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Update RC 150 GNVS. +// [Files] SBDxe.c, SB.uni, SB.sd +// +// 43 6/03/13 3:47a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove some code that move to Thunder Bolt module. +// [Files] SB.sd +// +// 42 5/30/13 9:14a Scottyang +// [TAG] EIP122981 +// [Category] Improvement +// [Description] Support HarrisBeach CRB. +// [Files] SB.sd, ACPI.sd, CRB.sdl +// +// 41 5/13/13 9:27a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Set LpssIntMode default to ACPI. +// [Files] SB.sd +// +// 40 5/13/13 8:59a Scottyang +// [TAG] EIP123496 +// [Category] Improvement +// [Description] Update PCH RC 1.5.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.* , SBDxe.C, SBPEI.c, +// SB.sd, SB.uni, SbSetupData.h, GetSetupData.c +// +// 39 4/24/13 6:49a Scottyang +// [TAG] EIP82149 +// [Category] Improvement +// [Description] Intel(R) 8 Series Chipset Family Deep Sx and CPU +// Soft-Strap BIOS Override Co-Existence Issue. If the soft-strap override +// feature is required and enabled, BIOS must disable Deep Sx +// functionality. +// [Files] SBDxe.c, SB.sd, SBPlatformData.h +// +// 38 3/26/13 5:56a Wesleychen +// [TAG] None +// [Category] Improvement +// [Description] To Hide HPET setup option. +// [Files] SB.sd +// +// 37 3/21/13 1:43a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Fixed remove wrong setup item. +// [Files] SB.sd +// +// 36 3/15/13 3:42a Scottyang +// [TAG] EIP118121 +// [Category] Improvement +// [Description] Update PCH RC 1.3.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupData.h +// +// 35 3/14/13 4:19a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove unuse item. +// [Files] SB.sd +// +// 34 3/06/13 2:26a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove one BIOS lock marco. +// [Files] SB.sd +// +// 33 3/04/13 10:08p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add Solid State Drive item to port 6. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd +// +// 32 2/18/13 2:52a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Set PCIE root port function swapping default is +// disable. +// [Files] SB.sd, SB.uni, SB.sdl +// +// 31 2/09/13 12:16a Scottyang +// [TAG] EIP114922 +// [Category] Improvement +// [Description] Update PCH RC 1.1.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupDara.h +// +// 30 1/31/13 10:55a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add Serial IO GNVS setup option. +// [Files] SBDxe.c, SB.sd, SB.uni, SbSetupData.h, GetSetupData.c +// +// 29 1/30/13 12:55a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Update for 4.6.5.3_TBT_002. +// [Files] SB.sd, SB.sdl +// +// 28 1/25/13 7:47a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Use token to set "BIOS Lock", "SMI Lock", BIOS +// Interface Lock", "GPIO Lock" and "RTC RAM Lock". +// [Files] SB.sd, SB.sdl +// +// 27 1/10/13 4:45a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create DTIO value and DM value option +// [Files] SB.sd, SB.uni, SbSetupData.h, GetSetupData.c, SBDxe.c +// +// 26 1/03/13 10:59p Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Minor +// [Symptom] Azalia option not show at setup menu at 2 chip +// [RootCause] Azalia option will hide when Audio DSP enable at ULT but +// 2 chip do no need. +// [Solution] Hide Azalia only when is ULT platform. +// [Files] SB.sd +// +// 25 1/03/13 4:54a Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Build error when set IDE mode as default. +// [RootCause] The ULT did not support IDE mode that made the value +// redefine. +// [Solution] Separate Sata inter face for 2 Chip and ULT. +// [Files] SB.sd, GetSetupData.c, SbSetupData.h +// +// 24 12/26/12 7:43a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Show EHCI option when XHCI is disable. +// [Files] SB.sd +// +// 23 12/24/12 5:49a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add option for XHCI Idel L1 workaroung. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c, +// SBPEI.c +// +// 22 12/22/12 2:06a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add PCIE "L1 Substates"setup option. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c +// +// 21 12/18/12 6:12a Scottyang +// [TAG] EIP109697 +// [Category] Improvement +// [Description] Update PCH RC 0.8.1 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// +// 20 12/17/12 6:42a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add setup menu for LPSS and ECTG. +// [Files] GetSetupData.c +// SbSetupData.h +// SB.sd +// SB.uni +// SBDxe.c +// +// 19 12/13/12 10:35a Scottyang +// [TAG] EIP106687 +// [Category] Improvement +// [Description] Add option for delay to detect PCIE card. +// [Files] SBPEI.c, SB.sd, SB.uni, GetSetupData.c, SbSetupData.h, +// PciBus.c +// +// 18 12/10/12 10:42p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Follow IBIOS remove EHCI1 and EHCI2 setup menu. +// +// 17 11/21/12 12:50a Scottyang +// [TAG] None +// +// [Category] Improvement +// +// [Description] Add String at help for USB +// +// [Files] SB.sd, SB.uni +// +// 16 11/20/12 9:43a Scottyang +// [TAG] EIP107014 +// [Category] Improvement +// [Description] Update RC 0.8.0 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SbSetupData.c, GetSetupDate.c +// +// 15 11/08/12 8:37a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add device item that connect LPSS. +// [Files] GetSetupData.c, SbSetupData.h, SBDxe.c, SB.sd, SB.uni +// +// 14 11/07/12 6:04a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove HDMI item. +// [Files] SB.sd, SB.uni, GetSetupData.c, SbSetupData.h +// +// 13 10/25/12 7:17a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create NFC item at setup +// [Files] SB.sd, SB.uni, SbSetupData.h +// +// 12 10/23/12 8:25a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create Device Sleep at setup menu +// [Files] SB.sd, SB.uni, SBDxe.c, GetSetupData.c, SbSetupData.h +// +// 11 10/16/12 2:18a Scottyang +// [TAG] EIP103924 +// [Category] Improvement +// [Description] Update RC 0.7.1 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// +// 10 10/14/12 8:27a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] One rom for two chip and one chip. +// [Files] SPPEIBoard.c, SB.sd, SBDxe.c, SBPEI.c, PCH.asl +// +// 9 9/26/12 3:51a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update for Intel PCH LPT RC070. +// [Files] SB.sdl, SBDXE.c, SBPEI.c, Pch.sdl, SB.sd, SB.uni +// +// [TAG] None +// [Category] Improvement +// [Description] Update for generic Thunderbolt support. +// [Files] SB.sd +// +// [TAG] None +// [Category] Improvement +// [Description] Implement ULT platform LPSS and ADSP setup option. +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SB.sdl +// +// 8 9/12/12 5:06a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Modify for Thunderbolt support. +// [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +// PciHotPlug.c +// +// [TAG] None +// [Category] Improvement +// [Description] Force HPET enabled for MRC initialization. +// [Files] SB.sd, SBPEI.c +// +// 7 8/24/12 6:47a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update RC_PORT_x for PCIe. +// [Files] SB.sdl, SB.sd, SBDxe.c +// +// 6 8/13/12 10:09a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove useless Dppm items. +// [Files] GetSetupData.c, SB.sd, SbSetupData.h, SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Implement USB Precondition option for policy +// "UsbPrecondition". +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SBPEI.c +// +// 5 7/27/12 6:07a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update setup items and policies. +// [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +// SBPEI.c, SBDXE.c +// +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 4 7/02/12 10:20a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement the setup option S3_S4_S5/Battery of DeepSx. +// [Files] SB.sd, SB.uni +// +// [TAG] None +// [Category] Improvement +// [Description] Change default setup of USB 3.0 mode and Pre-Boot +// Support. +// [Files] GetSetupData.c, SB.sd +// +// 3 5/03/12 6:31a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Modify to support Thunderbolt. +// [Files] SB.sd; SB.uni; SB.sdl; SbSetupData.h; PciHotPlug.c +// +// 2 4/25/12 9:08a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Relayout PCH USB Setup. +// [Files] GetSetupData.c; SB.sd; SB.uni; SbSetupData.h; SBDxe.c +// +// 1 2/08/12 8:23a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SB.sd +// +// Description: South Bridge setup form +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef SATA_MODE_IDE +#define SATA_MODE_IDE 0 +#endif + +#ifndef SATA_MODE_AHCI +#define SATA_MODE_AHCI 1 +#endif + +#ifndef SATA_MODE_RAID +#define SATA_MODE_RAID 2 +#endif + +#ifdef SETUP_DATA_DEFINITION +//---------------------------------------------------------------------------- +// Put NVRAM data definitions here. +// For example: UINT8 Data1; +// These definitions will be converted by the build process +// to a definitions of SETUP_DATA fields. +//---------------------------------------------------------------------------- + UINT8 ECTG; + UINT8 PchLan; + UINT8 PchWakeOnLan; + UINT8 SlpLanLow; + UINT8 BoardCapability; + UINT8 DeepSxBattMode; + UINT8 DeepSxMode; + UINT8 Gp27Wake; + UINT8 PcieWake; + UINT8 PchAzalia; + UINT8 AzaliaDs; + UINT8 AzaliaPme; + UINT8 PchPciClockRun; + UINT8 SirqMode; + UINT8 PchDisplay; + UINT8 PchEnableCrid; + UINT8 SmiLock; + UINT8 BiosLock; + UINT8 GpioLock; + UINT8 BiosInterfaceLock; + UINT8 RtcLock; + // PCH DMI + UINT8 PchDmiAspm; + UINT8 PchDmiExtSync; + // PCI_EXPRESS_CONFIG, 8 ROOT PORTS + UINT8 PcieUsbWa; + UINT8 PcieClockGating; + UINT8 RootPortFunctionSwapping; + UINT8 PcieRootPortSBDE; + UINT8 PcieSBDEPort; + UINT8 PcieRootPortEn[8]; + UINT8 PcieRootPortAspm[8]; + UINT8 PcieRootPortURE[8]; + UINT8 PcieRootPortFEE[8]; + UINT8 PcieRootPortNFE[8]; + UINT8 PcieRootPortCEE[8]; + UINT8 PcieRootPortCTD[8]; + UINT8 PcieRootPortPIE[8]; + UINT8 PcieRootPortSFE[8]; + UINT8 PcieRootPortSNE[8]; + UINT8 PcieRootPortSCE[8]; + UINT8 PcieRootPortL1S[8]; + UINT8 PcieRootPortPMCE[8]; + UINT8 PcieRootPortHPE[8]; + UINT8 PcieRootPortSpeed[8]; + UINT8 PcieRPDetectNonComplaint[8]; + + UINT8 PcieLtrEnable[8]; + UINT8 PcieLtrConfigLock[8]; + UINT8 PcieSnoopLatencyOverrideMode[8]; + UINT8 PcieSnoopLatencyOverrideMultiplier[8]; + UINT8 PcieSnoopLatencyOverrideValue[8]; + UINT8 PcieNonSnoopLatencyOverrideMode[8]; + UINT8 PcieNonSnoopLatencyOverrideMultiplier[8]; + UINT8 PcieNonSnoopLatencyOverrideValue[8]; + + + // PCI Bridge Resources + UINT8 ExtraBusRsvd[8]; + UINT16 PcieMemRsvd[8]; + UINT8 PcieMemRsvdalig[8]; + UINT16 PciePFMemRsvd[8]; + UINT8 PciePFMemRsvdalig[8]; + UINT8 PcieIoRsvd[8]; +// UINT8 ExtraBusRsv2[8]; + +#if HPET_SUPPORT + UINT8 Hpet; +#endif + UINT8 SlpS4AssW; + UINT8 LastState; + UINT8 Port80Route; + // Usb Config + UINT8 UsbPrecondition; + UINT8 PchUsb30Mode; +// UINT8 PchUsb30HsPortSwitchable[4]; + UINT8 PchEnableRmh1; + UINT8 PchUsb20[2]; + UINT8 PchUsbPerPortCtl; + UINT8 EhciConDisConWakeUp; + UINT8 PchUsbPort[14]; + UINT8 PchUsb30Port[6]; + UINT8 PchUsb30PreBootSupport; + UINT8 PchUsb30IdleL1; + UINT8 PchUsb30Btcg; + UINT8 PchUsb20PinRoute; + UINT8 ManualModeUsb20PerPinRoute[14]; + UINT8 PchUsb30PinEnable; + UINT8 ManualModeUsb30PerPinEnable[6]; +// UINT8 XhciStreams; + // Sata CONFIG + UINT8 PchSata; + UINT8 SataInterfaceMode; + UINT8 ULTSataInterfaceMode; + UINT8 SataTestMode; +#if SataDriver_SUPPORT + UINT8 SataRaidRom; +#endif + UINT8 SalpSupport; + UINT8 SataControllerSpeed; + UINT8 SataPort[6]; + UINT8 SataHotPlug[6]; + UINT8 ExternalSata[6]; + UINT8 SataMechanicalSw[6]; + UINT8 SolidStateDrive[6]; + UINT8 SataSpinUp[6]; + UINT8 SataDevSlp[4]; + UINT8 SataEnableDitoConfig[4]; + UINT8 SataDmVal[4]; + UINT16 SataDitoVal[4]; + UINT8 SataRaidR0; + UINT8 SataRaidR1; + UINT8 SataRaidR10; + UINT8 SataRaidR5; + UINT8 SataRaidIrrt; + UINT8 SataRaidOub; + UINT8 SataHddlk; + UINT8 SataLedl; + UINT8 SataRaidIooe; + UINT8 SmartStorage; + UINT8 OromUiDelay; + UINT8 SataAlternateId; + + // PCH Thermal + UINT8 AutoThermalReport; + UINT8 Ac1TripPoint; + UINT8 Ac0TripPoint; + UINT8 Ac0FanSpeed; + UINT8 Ac1FanSpeed; + UINT8 PassiveThermalTripPoint; + UINT8 CriticalThermalTripPoint; + UINT8 PassiveTc1Value; + UINT8 PassiveTc2Value; + UINT8 PassiveTspValue; + + UINT8 CPUTempReadEnable; + UINT8 CPUEnergyReadEnable; + UINT8 ThermalDeviceEnable; + UINT8 PchCrossThrottling; + UINT8 PCHTempReadEnable; + UINT8 AlertEnableLock; + UINT8 PchAlert; + UINT8 DimmAlert; + + UINT8 PchHotLevel; + UINT8 TPV_Restrict_Enable; + + UINT8 TrEnabled; + UINT8 TsOnDimm1; + UINT8 TsOnDimm2; + UINT8 TsOnDimm3; + UINT8 TsOnDimm4; + UINT8 SMBusECMsgLen; + UINT8 SMBusECMsgPEC; + // EC turbo control test mode + UINT8 ECTurboControlMode; + UINT8 ACBrickCapacity; + UINT8 ECPollingPeriod; + UINT8 ECGuardBandValue; + UINT8 ECAlgorithmSel; + UINT8 ECHybridPowerBoost; + UINT16 ECHybridCurrent; + // PchLp LPSS + UINT8 LpssDmaEnable; + UINT8 LpssI2c0Enable; + UINT8 LpssI2c1Enable; + UINT8 LpssSpi0Enable; + UINT8 LpssSpi1Enable; + UINT8 LpssUart0Enable; + UINT8 LpssUart1Enable; + UINT8 LpssSdioEnable; + UINT8 LpssMode; + UINT8 LpssIntMode; + UINT8 I2C0VoltageSelect; + UINT8 I2C1VoltageSelect; + UINT8 SensorHub; + UINT8 TPD4; + UINT8 AtmelTPL; + UINT8 ElanTPL; + UINT8 ElanTPD; + UINT8 SynaTPD; + UINT8 NtriTPL; + UINT8 EetiTPL; + UINT8 AlpsTPD; + UINT8 CyprTPD; + UINT8 Bluetooth0; + UINT8 Bluetooth1; + + UINT16 I2C0SSH; + UINT16 I2C0SSL; + UINT16 I2C0SSD; + UINT16 I2C0FMH; + UINT16 I2C0FML; + UINT16 I2C0FMD; + UINT16 I2C0FPH; + UINT16 I2C0FPL; + UINT16 I2C0FPD; + UINT16 I2C0M0C0; + UINT16 I2C0M1C0; + UINT16 I2C0M2C0; + + UINT16 I2C1SSH; + UINT16 I2C1SSL; + UINT16 I2C1SSD; + UINT16 I2C1FMH; + UINT16 I2C1FML; + UINT16 I2C1FMD; + UINT16 I2C1FPH; + UINT16 I2C1FPL; + UINT16 I2C1FPD; + UINT16 I2C1M0C1; + UINT16 I2C1M1C1; + UINT16 I2C1M2C1; + + UINT16 SPI0M0C2; + UINT16 SPI0M1C2; + + UINT16 SPI1M0C3; + UINT16 SPI1M1C3; + + UINT16 UAR0M0C4; + UINT16 UAR0M1C4; + + UINT16 UAR1M0C5; + UINT16 UAR1M1C5; + // PchLp Audio DSP + UINT8 ADspEnable; + UINT8 ADspD3PG; + UINT8 ADspCodecSelect; + UINT8 ADspBluetooth; + UINT8 ADspMode; + + UINT8 NFCE; +#endif + +#ifdef FORM_SET_TYPEDEF + #include "Board\EM\Platform\PlatformSetup.h" + #include "Protocol\SBPlatformData.h" +#endif + + + +//--------------------------------------------------------------------------- +#if defined(VFRCOMPILE) && !defined(CONTROLS_ARE_DEFINED) +#define CONTROL_DEFINITION +#endif +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +#ifdef CONTROL_DEFINITION + +#define SB_ONEOF_ECTG\ + oneof varid = SETUP_DATA.ECTG,\ + prompt = STRING_TOKEN (STR_ECTG),\ + help = STRING_TOKEN (STR_ECTG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHLAN\ + oneof varid = SETUP_DATA.PchLan,\ + prompt = STRING_TOKEN (STR_PCH_LAN_CONTROLLER),\ + help = STRING_TOKEN (STR_PCH_LAN_CONTROLLER_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHWAKEONLAN\ + oneof varid = SETUP_DATA.PchWakeOnLan,\ + prompt = STRING_TOKEN (STR_PCH_LAN_WOL_PROMPT),\ + help = STRING_TOKEN (STR_PCH_LAN_WOL_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#if defined (PCH_SKU) && (PCH_SKU == 1) +#define SB_ONEOF_PCHSLPLANLOW\ + oneof varid = SETUP_DATA.SlpLanLow,\ + prompt = STRING_TOKEN (STR_PCH_SLP_LAN_LOW_PROMPT),\ + help = STRING_TOKEN (STR_PCH_SLP_LAN_LOW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; +#else +#define SB_ONEOF_PCHSLPLANLOW\ + oneof varid = SETUP_DATA.SlpLanLow,\ + prompt = STRING_TOKEN (STR_PCH_SLP_LAN_LOW_PROMPT),\ + help = STRING_TOKEN (STR_PCH_SLP_LAN_LOW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; +#endif + +#define SB_ONEOF_BOARDCAPABILITY\ + oneof varid = SETUP_DATA.BoardCapability,\ + prompt = STRING_TOKEN (STR_BOARD_CAPABILITY),\ + help = STRING_TOKEN (STR_BOARD_CAPABILITY_HELP),\ + option text = STRING_TOKEN (STR_SUS_PWR_DN_ACK_STRING), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_DEEP_SX_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_DEEPSXBATTMODE\ + oneof varid = SETUP_DATA.DeepSxBattMode,\ + prompt = STRING_TOKEN (STR_DEEP_SX_POWER_POLICIES_PROMPT),\ + help = STRING_TOKEN (STR_DEEP_SX_POWER_POLICIES_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_DEEPSX_S5_BATT_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_DEEPSX_S4_S5_BATT_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_DEEPSX_S3_S4_S5_BATT_STRING), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_DEEPSXMODE\ + oneof varid = SETUP_DATA.DeepSxMode,\ + prompt = STRING_TOKEN (STR_DEEP_SX_POWER_POLICIES_PROMPT),\ + help = STRING_TOKEN (STR_DEEP_SX_POWER_POLICIES_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_DEEPSX_S5_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_DEEPSX_S4_S5_STRING), value = 4, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_GP27WAKE\ + oneof varid = SETUP_DATA.Gp27Wake,\ + prompt = STRING_TOKEN (STR_DEEP_SX_GP27_WAKE_PROMPT),\ + help = STRING_TOKEN (STR_DEEP_SX_GP27_WAKE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEWAKE\ + oneof varid = SETUP_DATA.PcieWake,\ + prompt = STRING_TOKEN (STR_DEEP_SX_PCIE_WAKE_PROMPT),\ + help = STRING_TOKEN (STR_DEEP_SX_PCIE_WAKE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + // EC turbo control test mode +#define SB_ONEOF_ECTURBOCONTROLMODE\ + oneof varid = SETUP_DATA.ECTurboControlMode,\ + prompt = STRING_TOKEN (STR_EC_TURBO_CONTROL_MODE),\ + help = STRING_TOKEN (STR_EC_TURBO_CONTROL_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ACBRICKCAPACITY\ + oneof varid = SETUP_DATA.ACBrickCapacity,\ + prompt = STRING_TOKEN (STR_AC_BRICK_CAPACITY),\ + help = STRING_TOKEN (STR_AC_BRICK_CAPACITY_HELP),\ + option text = STRING_TOKEN (STR_90W_AC_BRICK), value = 1, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_65W_AC_BRICK), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_75W_AC_BRICK), value = 3, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ECPOLLINGPERIOD\ + numeric varid = SETUP_DATA.ECPollingPeriod,\ + prompt = STRING_TOKEN (STR_EC_POLLING_PERIOD),\ + help = STRING_TOKEN (STR_EC_POLLING_PERIOD_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 255,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_EC_POLLING_PERIOD), value = 1, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_ECGUARDBANDVALUE\ + numeric varid = SETUP_DATA.ECGuardBandValue,\ + prompt = STRING_TOKEN (STR_EC_GUARD_BAND),\ + help = STRING_TOKEN (STR_EC_GUARD_BAND_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 20,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_EC_GUARD_BAND), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_ECALGORITHMSEL\ + numeric varid = SETUP_DATA.ECAlgorithmSel,\ + prompt = STRING_TOKEN (STR_EC_ALGORITHM_SEL),\ + help = STRING_TOKEN (STR_EC_ALGORITHM_SEL_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 10,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_EC_ALGORITHM_SEL), value = 1, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_ECHYBRIDPOWERBOOST\ + oneof varid = SETUP_DATA.ECHybridPowerBoost,\ + prompt = STRING_TOKEN(STR_HYBRID_POWER_BOOST_PROMPT),\ + help = STRING_TOKEN(STR_HYBRID_POWER_BOOST_HELP),\ + option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ECHYBRIDCURRENT\ + numeric varid = SETUP_DATA.ECHybridCurrent,\ + prompt = STRING_TOKEN(STR_HYBRID_CURRENT_PROMPT),\ + help = STRING_TOKEN(STR_HYBRID_CURRENT_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 0xffff,\ + step = 1,\ + default = 0x1284,\ + option text = STRING_TOKEN (STR_HYBRID_CURRENT_PROMPT), value = 0x1284, flags = MANUFACTURING; \ + endnumeric; + +// EC turbo control test mode *** end + +#define SB_ONEOF_PCHAZALIA\ + oneof varid = SETUP_DATA.PchAzalia,\ + prompt = STRING_TOKEN (STR_PCH_AZALIA_PROMPT),\ + help = STRING_TOKEN (STR_PCH_AZALIA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + + +#define SB_ONEOF_AZALIADS\ + oneof varid = SETUP_DATA.AzaliaDs,\ + prompt = STRING_TOKEN (STR_AZALIA_DS_PROMPT),\ + help = STRING_TOKEN (STR_AZALIA_DS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_AZALIAPME\ + oneof varid = SETUP_DATA.AzaliaPme,\ + prompt = STRING_TOKEN (STR_AZALIA_PME_PROMPT),\ + help = STRING_TOKEN (STR_AZALIA_PME_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHDISPLAY\ + oneof varid = SETUP_DATA.PchDisplay,\ + prompt = STRING_TOKEN (STR_PCH_DISPLAY_PROMPT),\ + help = STRING_TOKEN (STR_PCH_DISPLAY_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHPCICLOCKRUN\ + oneof varid = SETUP_DATA.PchPciClockRun,\ + prompt = STRING_TOKEN (STR_PCH_PCICLOCKRUN_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCICLOCKRUN_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#if defined (LVC_BOARD) && (LVC_BOARD == 1) +#define SB_ONEOF_IRQMODE\ + oneof varid = SETUP_DATA.SirqMode,\ + prompt = STRING_TOKEN (STR_PCH_IRQMODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_IRQMODE_HELP),\ + option text = STRING_TOKEN (STR_IRQ_QUIET), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_IRQ_CONTINUOUS), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; +#else +#define SB_ONEOF_IRQMODE\ + oneof varid = SETUP_DATA.SirqMode,\ + prompt = STRING_TOKEN (STR_PCH_IRQMODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_IRQMODE_HELP),\ + option text = STRING_TOKEN (STR_IRQ_QUIET), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_IRQ_CONTINUOUS), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; +#endif + //(EIP124410)>> +#define SB_ONEOF_PCHENABLECRID\ + oneof varid = SETUP_DATA.PchEnableCrid,\ + questionid = AUTO_ID(SB_CRID_KEY),\ + prompt = STRING_TOKEN (STR_SB_CRID_ENABLE),\ + help = STRING_TOKEN (STR_SB_CRID_ENABLE_HELP),\ + default = DEFAULT_CRID_ENABLE,\ + option text = STRING_TOKEN(STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED | INTERACTIVE;\ + option text = STRING_TOKEN(STR_COMMON_ENABLED), value = 1, flags = MANUFACTURING | RESET_REQUIRED | INTERACTIVE;\ + endoneof; + //(EIP124410)>> +#define SB_ONEOF_SMILOCK\ + oneof varid = SETUP_DATA.SmiLock,\ + prompt = STRING_TOKEN (STR_SB_SMI_LOCK_ENABLE),\ + help = STRING_TOKEN (STR_SB_SMI_LOCK_ENABLE_HELP),\ + default = SMI_LOCK_ENABLE,\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_BIOSINTERFACELOCK\ + oneof varid = SETUP_DATA.BiosInterfaceLock,\ + prompt = STRING_TOKEN (STR_SB_BIOS_INTERFACE_LOCK_ENABLE),\ + help = STRING_TOKEN (STR_SB_BIOS_INTERFACE_LOCK_ENABLE_HELP),\ + default = BIOS_INTERFACE_LOCKDOWN,\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_GPIOLOCK\ + oneof varid = SETUP_DATA.GpioLock,\ + prompt = STRING_TOKEN (STR_SB_GPIO_LOCK_ENABLE),\ + help = STRING_TOKEN (STR_SB_GPIO_LOCK_ENABLE_HELP),\ + default = GPIO_LOCKDOWN_ENABLE,\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_BIOSLOCK\ + oneof varid = SETUP_DATA.BiosLock,\ + prompt = STRING_TOKEN (STR_SB_BIOS_LOCK_ENABLE),\ + help = STRING_TOKEN (STR_SB_BIOS_LOCK_ENABLE_HELP),\ + default = BIOS_LOCK_ENABLE,\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_RTCLOCK\ + oneof varid = SETUP_DATA.RtcLock,\ + prompt = STRING_TOKEN (STR_SB_RTC_LOCK_ENABLE),\ + help = STRING_TOKEN (STR_SB_RTC_LOCK_ENABLE_HELP),\ + default = RTC_LOCK_ENABLE,\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#if HPET_SUPPORT +#define SB_ONEOF_HPET\ + oneof varid = SETUP_DATA.Hpet,\ + prompt = STRING_TOKEN (STR_HPET_PROMPT),\ + help = STRING_TOKEN (STR_HPET_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; +#endif + +#define SB_ONEOF_SLPS4ASSW\ + oneof varid = SETUP_DATA.SlpS4AssW,\ + prompt = STRING_TOKEN (STR_SLP_S4_ASSW_PROMPT),\ + help = STRING_TOKEN (STR_SLP_S4_ASSW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ONE_SECOND), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_TWO_SECOND), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_THREE_SECOND), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_FOUR_SECOND), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LASTSTATE\ + oneof varid = SETUP_DATA.LastState,\ + prompt = STRING_TOKEN (STR_LAST_STATE_PROMPT),\ + help = STRING_TOKEN (STR_LAST_STATE_HELP),\ + option text = STRING_TOKEN (STR_POWER_OFF), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_POWER_ON), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_LAST_STATE), value = 2, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING, key = 0;\ + endoneof; + +#define SB_ONEOF_PORT80\ + oneof varid = SETUP_DATA.Port80Route,\ + prompt = STRING_TOKEN (STR_PORT_80_PROMPT),\ + help = STRING_TOKEN (STR_PORT_80_HELP),\ + option text = STRING_TOKEN (STR_LPC_BUS), value = 0, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING, key = 0;\ + option text = STRING_TOKEN (STR_PCI_BUS), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPRECONDITION\ + oneof varid = SETUP_DATA.UsbPrecondition,\ + prompt = STRING_TOKEN (STR_PCH_USB_PRECONDITION_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PRECONDITION_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30MODE\ + oneof varid = SETUP_DATA.PchUsb30Mode,\ + prompt = STRING_TOKEN (STR_PCH_USB30_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_SMART_AUTO), value = 3, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 4, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHENABLERMH1\ + oneof varid = SETUP_DATA.PchEnableRmh1,\ + prompt = STRING_TOKEN (STR_PCH_USB_RMH1_EN_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_RMH1_EN_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30PREBOOTSUPPORT\ + oneof varid = SETUP_DATA.PchUsb30PreBootSupport,\ + prompt = STRING_TOKEN (STR_PCH_USB30_PBOOT_SUPPORT_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_PBOOT_SUPPORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30IDLEL1\ + oneof varid = SETUP_DATA.PchUsb30IdleL1,\ + prompt = STRING_TOKEN (STR_PCH_USB30_IDLEL1_SUPPORT_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_IDLEL1_SUPPORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30BTCG\ + oneof varid = SETUP_DATA.PchUsb30Btcg,\ + prompt = STRING_TOKEN (STR_PCH_USB30_BTCG_SUPPORT_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_BTCG_SUPPORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB20PINROUTE\ + oneof varid = SETUP_DATA.PchUsb20PinRoute,\ + prompt = STRING_TOKEN (STR_PCH_ROUTE_USB20_PIN_TO_HC),\ + help = STRING_TOKEN (STR_PCH_ROUTE_USB20_PIN_TO_HC_HELP),\ + option text = STRING_TOKEN (STR_ROUTE_PER_PIN), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_ALL_PIN_EHCI), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_ALL_PIN_XHCI), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30PINENABLE\ + oneof varid = SETUP_DATA.PchUsb30PinEnable,\ + prompt = STRING_TOKEN (STR_PCH_ENABLE_USB30_PIN),\ + help = STRING_TOKEN (STR_PCH_ENABLE_USB30_PIN_HELP),\ + option text = STRING_TOKEN (STR_SELECT_PER_PIN), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SELECT_ALL_PIN_DISABLE), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SELECT_ALL_PIN_ENABLE), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE00\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN0),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE01\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN1),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE02\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN2),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE03\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN3),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE04\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN4),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE05\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN5),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE06\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN6),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE07\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN7),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE08\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_8],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN8),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE09\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_9],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN9),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE10\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_10],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN10),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE11\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_11],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN11),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE12\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_12],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN12),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB20PERPINROUTE13\ + oneof varid = SETUP_DATA.ManualModeUsb20PerPinRoute[OFFSET_13],\ + prompt = STRING_TOKEN (STR_PCH_USB_20_PIN13),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_ROUTE_TO_EHCI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ROUTE_TO_XHCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB30PERPINENABLE1\ + oneof varid = SETUP_DATA.ManualModeUsb30PerPinEnable[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_USB_30_PIN1),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB30PERPINENABLE2\ + oneof varid = SETUP_DATA.ManualModeUsb30PerPinEnable[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_USB_30_PIN2),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB30PERPINENABLE3\ + oneof varid = SETUP_DATA.ManualModeUsb30PerPinEnable[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_USB_30_PIN3),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB30PERPINENABLE4\ + oneof varid = SETUP_DATA.ManualModeUsb30PerPinEnable[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_USB_30_PIN4),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB30PERPINENABLE5\ + oneof varid = SETUP_DATA.ManualModeUsb30PerPinEnable[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_USB_30_PIN5),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_USB30PERPINENABLE6\ + oneof varid = SETUP_DATA.ManualModeUsb30PerPinEnable[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_USB_30_PIN6),\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +//#define SB_ONEOF_XHCISTREAMS\ +// oneof varid = SETUP_DATA.XhciStreams,\ +// prompt = STRING_TOKEN (STR_PCH_USB_XHCISTREAMS_PROMPT),\ +// help = STRING_TOKEN (STR_PCH_USB_XHCISTREAMS_HELP),\ +// option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ +// option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ +// endoneof; + +//#define SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_00\ +// oneof varid = SETUP_DATA.PchUsb30HsPortSwitchable[OFFSET_0],\ +// prompt = STRING_TOKEN (STR_PCH_USB30_HSPORT0_PROMPT),\ +// help = STRING_TOKEN (STR_PCH_USB30_PER_HSPORT_HELP),\ +// option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ +// option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ +// endoneof; + +//#define SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_01\ +// oneof varid = SETUP_DATA.PchUsb30HsPortSwitchable[OFFSET_1],\ +// prompt = STRING_TOKEN (STR_PCH_USB30_HSPORT1_PROMPT),\ +// help = STRING_TOKEN (STR_PCH_USB30_PER_HSPORT_HELP),\ +// option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ +// option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ +// endoneof; + +//#define SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_02\ +// oneof varid = SETUP_DATA.PchUsb30HsPortSwitchable[OFFSET_2],\ +// prompt = STRING_TOKEN (STR_PCH_USB30_HSPORT2_PROMPT),\ +// help = STRING_TOKEN (STR_PCH_USB30_PER_HSPORT_HELP),\ +// option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ +// option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ +// endoneof; + +//#define SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_03\ +// oneof varid = SETUP_DATA.PchUsb30HsPortSwitchable[OFFSET_3],\ +// prompt = STRING_TOKEN (STR_PCH_USB30_HSPORT3_PROMPT),\ +// help = STRING_TOKEN (STR_PCH_USB30_PER_HSPORT_HELP),\ +// option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ +// option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ +// endoneof; + +#define SB_ONEOF_PCHUSB20OFF0\ + oneof varid = SETUP_DATA.PchUsb20[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_USB21_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB2_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB20OFF1\ + oneof varid = SETUP_DATA.PchUsb20[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_USB22_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB2_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPERPORTCTL\ + oneof varid = SETUP_DATA.PchUsbPerPortCtl,\ + prompt = STRING_TOKEN (STR_PCH_USB_PER_PORT_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PER_PORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#if EHCI_CON_DISCON_WAKE_UP_SUPPORT +#define SB_ONEOF_EHCICONDISCONWAKEUP\ + oneof varid = SETUP_DATA.EhciConDisConWakeUp,\ + prompt = STRING_TOKEN (STR_PCH_USB_CON_DISCON_WAKEUP_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_CON_DISCON_WAKEUP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; +#endif + +#define SB_ONEOF_PCHUSBPORT00\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT0_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT01\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT1_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT02\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT2_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT03\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT3_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT04\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT4_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT05\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT5_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT06\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT6_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT07\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT7_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT08\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_8],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT8_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT09\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_9],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT9_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT10\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_10],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT10_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT11\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_11],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT11_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT12\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_12],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT12_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSBPORT13\ + oneof varid = SETUP_DATA.PchUsbPort[OFFSET_13],\ + prompt = STRING_TOKEN (STR_PCH_USB_PORT13_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30PORT00\ + oneof varid = SETUP_DATA.PchUsb30Port[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_USB30_PORT0_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30PORT01\ + oneof varid = SETUP_DATA.PchUsb30Port[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_USB30_PORT1_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30PORT02\ + oneof varid = SETUP_DATA.PchUsb30Port[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_USB30_PORT2_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30PORT03\ + oneof varid = SETUP_DATA.PchUsb30Port[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_USB30_PORT3_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30PORT04\ + oneof varid = SETUP_DATA.PchUsb30Port[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_USB30_PORT4_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHUSB30PORT05\ + oneof varid = SETUP_DATA.PchUsb30Port[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_USB30_PORT5_PROMPT),\ + help = STRING_TOKEN (STR_PCH_USB30_PORT_DIS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIECLOCKGATING\ + oneof varid = SETUP_DATA.PcieClockGating,\ + prompt = STRING_TOKEN (STR_PCIE_CKG_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_CKG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ROOTPORTFUNCTIONSWAPPING\ + oneof varid = SETUP_DATA.RootPortFunctionSwapping,\ + prompt = STRING_TOKEN (STR_PCIE_PORT_SWAP_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_PORT_SWAP_HELP),\ + default = ROOT_PORT_FUN_SWAP_ENABLE,\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHDMIASPM\ + oneof varid = SETUP_DATA.PchDmiAspm,\ + prompt = STRING_TOKEN (STR_PCH_DMI_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_DMI_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHDMIEXTSYNC\ + oneof varid = SETUP_DATA.PchDmiExtSync,\ + prompt = STRING_TOKEN (STR_PCH_DMI_ES_PROMPT),\ + help = STRING_TOKEN (STR_PCH_DMI_ES_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key=0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEUSBWA\ + oneof varid = SETUP_DATA.PcieUsbWa,\ + prompt = STRING_TOKEN (STR_PCH_PCIE_USB_WA_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_USB_WA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key=0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSBDE\ + oneof varid = SETUP_DATA.PcieRootPortSBDE,\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SBDE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SBDE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESBDEPORT\ + numeric varid = SETUP_DATA.PcieSBDEPort,\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SBDE_PORT_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SBDE_PORT_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 7,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SBDE_PORT_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_LANRP1\ + text\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + text = STRING_TOKEN (STR_PCIE_LANRP1_PROMPT),\ + text = STRING_TOKEN (STR_EMPTY_STRING),\ + flags = 0,\ + key = 0; + +#define SB_ONEOF_LANRP2\ + text\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + text = STRING_TOKEN (STR_PCIE_LANRP2_PROMPT),\ + text = STRING_TOKEN (STR_EMPTY_STRING),\ + flags = 0,\ + key = 0; + +#define SB_ONEOF_LANRP3\ + text\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + text = STRING_TOKEN (STR_PCIE_LANRP3_PROMPT),\ + text = STRING_TOKEN (STR_EMPTY_STRING),\ + flags = 0,\ + key = 0; + +#define SB_ONEOF_LANRP4\ + text\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + text = STRING_TOKEN (STR_PCIE_LANRP4_PROMPT),\ + text = STRING_TOKEN (STR_EMPTY_STRING),\ + flags = 0,\ + key = 0; + +#define SB_ONEOF_LANRP5\ + text\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + text = STRING_TOKEN (STR_PCIE_LANRP5_PROMPT),\ + text = STRING_TOKEN (STR_EMPTY_STRING),\ + flags = 0,\ + key = 0; + +#define SB_ONEOF_LANRP6\ + text\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + text = STRING_TOKEN (STR_PCIE_LANRP6_PROMPT),\ + text = STRING_TOKEN (STR_EMPTY_STRING),\ + flags = 0,\ + key = 0; + +#define SB_ONEOF_LANRP7\ + text\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + text = STRING_TOKEN (STR_PCIE_LANRP7_PROMPT),\ + text = STRING_TOKEN (STR_EMPTY_STRING),\ + flags = 0,\ + key = 0; + +#define SB_ONEOF_LANRP8\ + text\ + help = STRING_TOKEN (STR_EMPTY_STRING),\ + text = STRING_TOKEN (STR_PCIE_LANRP8_PROMPT),\ + text = STRING_TOKEN (STR_EMPTY_STRING),\ + flags = 0,\ + key = 0; + +#define SB_ONEOF_PCIEROOTPORTEN00\ + oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIERP1_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTASPM00\ + oneof varid = SETUP_DATA.PcieRootPortAspm[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCIE_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0S_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L1_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0SL1_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTL1S00\ + oneof varid = SETUP_DATA.PcieRootPortL1S[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCIE_L1S_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_L1S_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L12_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_L12_STRING), value = 3, flags =DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTURE00\ + oneof varid = SETUP_DATA.PcieRootPortURE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_URE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_URE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTFEE00\ + oneof varid = SETUP_DATA.PcieRootPortFEE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_FEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_FEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTNFE00\ + oneof varid = SETUP_DATA.PcieRootPortNFE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCEE00\ + oneof varid = SETUP_DATA.PcieRootPortCEE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCTD00\ + oneof varid = SETUP_DATA.PcieRootPortCTD[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CTD_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CTD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSFE00\ + oneof varid = SETUP_DATA.PcieRootPortSFE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSNE00\ + oneof varid = SETUP_DATA.PcieRootPortSNE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSCE00\ + oneof varid = SETUP_DATA.PcieRootPortSCE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTPMCE00\ + oneof varid = SETUP_DATA.PcieRootPortPMCE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PMCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PMCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTHPE00\ + oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSPEED00\ + oneof varid = SETUP_DATA.PcieRootPortSpeed[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SPEED_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SPEED_HELP),\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTDNCD00\ + oneof varid = SETUP_DATA.PcieRPDetectNonComplaint[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTRABUSRSVD00\ + numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_EXTRA_BUS_RESERVED,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVD00\ + numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVDALIG00\ + numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVD00\ + numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_PF_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVDALIG00\ + numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEIORSVD00\ + numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_PCIE_IO_RESERVED,\ + step = 4,\ + default = 4,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIELTRENABLE00\ + oneof varid = SETUP_DATA.PcieLtrEnable[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIELTRCONFIGLOCK00\ + oneof varid = SETUP_DATA.PcieLtrConfigLock[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE00\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER00\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMultiplier[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE00\ + numeric varid = SETUP_DATA.PcieSnoopLatencyOverrideValue[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1020,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE00\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER00\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMultiplier[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE00\ + numeric varid = SETUP_DATA.PcieNonSnoopLatencyOverrideValue[OFFSET_0],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +//------------------------------------------------------------------------------------ + +#define SB_ONEOF_PCIEROOTPORTEN01\ + oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIERP2_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTASPM01\ + oneof varid = SETUP_DATA.PcieRootPortAspm[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCIE_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0S_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L1_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0SL1_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTL1S01\ + oneof varid = SETUP_DATA.PcieRootPortL1S[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCIE_L1S_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_L1S_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L12_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_L12_STRING), value = 3, flags =DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTURE01\ + oneof varid = SETUP_DATA.PcieRootPortURE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_URE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_URE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTFEE01\ + oneof varid = SETUP_DATA.PcieRootPortFEE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_FEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_FEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTNFE01\ + oneof varid = SETUP_DATA.PcieRootPortNFE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCEE01\ + oneof varid = SETUP_DATA.PcieRootPortCEE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCTD01\ + oneof varid = SETUP_DATA.PcieRootPortCTD[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CTD_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CTD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSFE01\ + oneof varid = SETUP_DATA.PcieRootPortSFE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSNE01\ + oneof varid = SETUP_DATA.PcieRootPortSNE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSCE01\ + oneof varid = SETUP_DATA.PcieRootPortSCE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTPMCE01\ + oneof varid = SETUP_DATA.PcieRootPortPMCE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PMCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PMCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTHPE01\ + oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSPEED01\ + oneof varid = SETUP_DATA.PcieRootPortSpeed[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SPEED_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SPEED_HELP),\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTDNCD01\ + oneof varid = SETUP_DATA.PcieRPDetectNonComplaint[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTRABUSRSVD01\ + numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_EXTRA_BUS_RESERVED,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVD01\ + numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVDALIG01\ + numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVD01\ + numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_PF_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVDALIG01\ + numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEIORSVD01\ + numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_PCIE_IO_RESERVED,\ + step = 4,\ + default = 4,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIELTRENABLE01\ + oneof varid = SETUP_DATA.PcieLtrEnable[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIELTRCONFIGLOCK01\ + oneof varid = SETUP_DATA.PcieLtrConfigLock[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE01\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER01\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMultiplier[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE01\ + numeric varid = SETUP_DATA.PcieSnoopLatencyOverrideValue[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1020,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE01\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER01\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMultiplier[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE01\ + numeric varid = SETUP_DATA.PcieNonSnoopLatencyOverrideValue[OFFSET_1],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; +//------------------------------------------------------------------------------------ + +#define SB_ONEOF_PCIEROOTPORTEN02\ + oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIERP3_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTASPM02\ + oneof varid = SETUP_DATA.PcieRootPortAspm[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCIE_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0S_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L1_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0SL1_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTL1S02\ + oneof varid = SETUP_DATA.PcieRootPortL1S[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCIE_L1S_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_L1S_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L12_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_L12_STRING), value = 3, flags =DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTURE02\ + oneof varid = SETUP_DATA.PcieRootPortURE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_URE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_URE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTFEE02\ + oneof varid = SETUP_DATA.PcieRootPortFEE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_FEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_FEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTNFE02\ + oneof varid = SETUP_DATA.PcieRootPortNFE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCEE02\ + oneof varid = SETUP_DATA.PcieRootPortCEE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCTD02\ + oneof varid = SETUP_DATA.PcieRootPortCTD[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CTD_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CTD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSFE02\ + oneof varid = SETUP_DATA.PcieRootPortSFE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSNE02\ + oneof varid = SETUP_DATA.PcieRootPortSNE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSCE02\ + oneof varid = SETUP_DATA.PcieRootPortSCE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTPMCE02\ + oneof varid = SETUP_DATA.PcieRootPortPMCE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PMCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PMCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTHPE02\ + oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSPEED02\ + oneof varid = SETUP_DATA.PcieRootPortSpeed[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SPEED_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SPEED_HELP),\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTDNCD02\ + oneof varid = SETUP_DATA.PcieRPDetectNonComplaint[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTRABUSRSVD02\ + numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_EXTRA_BUS_RESERVED,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVD02\ + numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVDALIG02\ + numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVD02\ + numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_PF_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVDALIG02\ + numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEIORSVD02\ + numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_PCIE_IO_RESERVED,\ + step = 4,\ + default = 4,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIELTRENABLE02\ + oneof varid = SETUP_DATA.PcieLtrEnable[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIELTRCONFIGLOCK02\ + oneof varid = SETUP_DATA.PcieLtrConfigLock[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE02\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER02\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMultiplier[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE02\ + numeric varid = SETUP_DATA.PcieSnoopLatencyOverrideValue[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1020,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE02\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER02\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMultiplier[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE02\ + numeric varid = SETUP_DATA.PcieNonSnoopLatencyOverrideValue[OFFSET_2],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; +//------------------------------------------------------------------------------------ + +#define SB_ONEOF_PCIEROOTPORTEN03\ + oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIERP4_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTASPM03\ + oneof varid = SETUP_DATA.PcieRootPortAspm[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCIE_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0S_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L1_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0SL1_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTL1S03\ + oneof varid = SETUP_DATA.PcieRootPortL1S[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCIE_L1S_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_L1S_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L12_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_L12_STRING), value = 3, flags =DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTURE03\ + oneof varid = SETUP_DATA.PcieRootPortURE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_URE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_URE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTFEE03\ + oneof varid = SETUP_DATA.PcieRootPortFEE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_FEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_FEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTNFE03\ + oneof varid = SETUP_DATA.PcieRootPortNFE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCEE03\ + oneof varid = SETUP_DATA.PcieRootPortCEE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCTD03\ + oneof varid = SETUP_DATA.PcieRootPortCTD[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CTD_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CTD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSFE03\ + oneof varid = SETUP_DATA.PcieRootPortSFE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSNE03\ + oneof varid = SETUP_DATA.PcieRootPortSNE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSCE03\ + oneof varid = SETUP_DATA.PcieRootPortSCE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTPMCE03\ + oneof varid = SETUP_DATA.PcieRootPortPMCE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PMCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PMCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTHPE03\ + oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSPEED03\ + oneof varid = SETUP_DATA.PcieRootPortSpeed[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SPEED_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SPEED_HELP),\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTDNCD03\ + oneof varid = SETUP_DATA.PcieRPDetectNonComplaint[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTRABUSRSVD03\ + numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_EXTRA_BUS_RESERVED,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVD03\ + numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVDALIG03\ + numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVD03\ + numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_PF_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVDALIG03\ + numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEIORSVD03\ + numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_PCIE_IO_RESERVED,\ + step = 4,\ + default = 4,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIELTRENABLE03\ + oneof varid = SETUP_DATA.PcieLtrEnable[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIELTRCONFIGLOCK03\ + oneof varid = SETUP_DATA.PcieLtrConfigLock[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE03\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER03\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMultiplier[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE03\ + numeric varid = SETUP_DATA.PcieSnoopLatencyOverrideValue[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1020,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE03\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER03\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMultiplier[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE03\ + numeric varid = SETUP_DATA.PcieNonSnoopLatencyOverrideValue[OFFSET_3],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; +//------------------------------------------------------------------------------------ + +#define SB_ONEOF_PCIEROOTPORTEN04\ + oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIERP5_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTASPM04\ + oneof varid = SETUP_DATA.PcieRootPortAspm[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCIE_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0S_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L1_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0SL1_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTL1S04\ + oneof varid = SETUP_DATA.PcieRootPortL1S[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCIE_L1S_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_L1S_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L12_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_L12_STRING), value = 3, flags =DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTURE04\ + oneof varid = SETUP_DATA.PcieRootPortURE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_URE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_URE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTFEE04\ + oneof varid = SETUP_DATA.PcieRootPortFEE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_FEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_FEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTNFE04\ + oneof varid = SETUP_DATA.PcieRootPortNFE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCEE04\ + oneof varid = SETUP_DATA.PcieRootPortCEE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCTD04\ + oneof varid = SETUP_DATA.PcieRootPortCTD[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CTD_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CTD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSFE04\ + oneof varid = SETUP_DATA.PcieRootPortSFE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSNE04\ + oneof varid = SETUP_DATA.PcieRootPortSNE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSCE04\ + oneof varid = SETUP_DATA.PcieRootPortSCE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTPMCE04\ + oneof varid = SETUP_DATA.PcieRootPortPMCE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PMCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PMCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTHPE04\ + oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSPEED04\ + oneof varid = SETUP_DATA.PcieRootPortSpeed[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SPEED_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SPEED_HELP),\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTDNCD04\ + oneof varid = SETUP_DATA.PcieRPDetectNonComplaint[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTRABUSRSVD04\ + numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_EXTRA_BUS_RESERVED,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVD04\ + numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVDALIG04\ + numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVD04\ + numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_PF_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVDALIG04\ + numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEIORSVD04\ + numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_PCIE_IO_RESERVED,\ + step = 4,\ + default = 4,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIELTRENABLE04\ + oneof varid = SETUP_DATA.PcieLtrEnable[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIELTRCONFIGLOCK04\ + oneof varid = SETUP_DATA.PcieLtrConfigLock[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE04\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER04\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMultiplier[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE04\ + numeric varid = SETUP_DATA.PcieSnoopLatencyOverrideValue[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1020,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE04\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER04\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMultiplier[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE04\ + numeric varid = SETUP_DATA.PcieNonSnoopLatencyOverrideValue[OFFSET_4],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; +//------------------------------------------------------------------------------------ + +#define SB_ONEOF_PCIEROOTPORTEN05\ + oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIERP6_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTASPM05\ + oneof varid = SETUP_DATA.PcieRootPortAspm[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCIE_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0S_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L1_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0SL1_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTL1S05\ + oneof varid = SETUP_DATA.PcieRootPortL1S[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCIE_L1S_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_L1S_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L12_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_L12_STRING), value = 3, flags =DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTURE05\ + oneof varid = SETUP_DATA.PcieRootPortURE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_URE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_URE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTFEE05\ + oneof varid = SETUP_DATA.PcieRootPortFEE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_FEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_FEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTNFE05\ + oneof varid = SETUP_DATA.PcieRootPortNFE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCEE05\ + oneof varid = SETUP_DATA.PcieRootPortCEE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCTD05\ + oneof varid = SETUP_DATA.PcieRootPortCTD[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CTD_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CTD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSFE05\ + oneof varid = SETUP_DATA.PcieRootPortSFE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSNE05\ + oneof varid = SETUP_DATA.PcieRootPortSNE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSCE05\ + oneof varid = SETUP_DATA.PcieRootPortSCE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTPMCE05\ + oneof varid = SETUP_DATA.PcieRootPortPMCE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PMCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PMCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTHPE05\ + oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSPEED05\ + oneof varid = SETUP_DATA.PcieRootPortSpeed[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SPEED_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SPEED_HELP),\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTDNCD05\ + oneof varid = SETUP_DATA.PcieRPDetectNonComplaint[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTRABUSRSVD05\ + numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_EXTRA_BUS_RESERVED,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVD05\ + numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVDALIG05\ + numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVD05\ + numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_PF_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVDALIG05\ + numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEIORSVD05\ + numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_PCIE_IO_RESERVED,\ + step = 4,\ + default = 4,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 4, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIELTRENABLE05\ + oneof varid = SETUP_DATA.PcieLtrEnable[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIELTRCONFIGLOCK05\ + oneof varid = SETUP_DATA.PcieLtrConfigLock[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE05\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER05\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMultiplier[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE05\ + numeric varid = SETUP_DATA.PcieSnoopLatencyOverrideValue[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1020,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE05\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER05\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMultiplier[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE05\ + numeric varid = SETUP_DATA.PcieNonSnoopLatencyOverrideValue[OFFSET_5],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; +//------------------------------------------------------------------------------------ + +#define SB_ONEOF_PCIEROOTPORTEN06\ + oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIERP7_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTASPM06\ + oneof varid = SETUP_DATA.PcieRootPortAspm[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCIE_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0S_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L1_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0SL1_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTL1S06\ + oneof varid = SETUP_DATA.PcieRootPortL1S[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCIE_L1S_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_L1S_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L12_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_L12_STRING), value = 3, flags =DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTURE06\ + oneof varid = SETUP_DATA.PcieRootPortURE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_URE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_URE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTFEE06\ + oneof varid = SETUP_DATA.PcieRootPortFEE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_FEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_FEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTNFE06\ + oneof varid = SETUP_DATA.PcieRootPortNFE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCEE06\ + oneof varid = SETUP_DATA.PcieRootPortCEE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCTD06\ + oneof varid = SETUP_DATA.PcieRootPortCTD[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CTD_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CTD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSFE06\ + oneof varid = SETUP_DATA.PcieRootPortSFE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSNE06\ + oneof varid = SETUP_DATA.PcieRootPortSNE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSCE06\ + oneof varid = SETUP_DATA.PcieRootPortSCE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTPMCE06\ + oneof varid = SETUP_DATA.PcieRootPortPMCE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PMCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PMCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTHPE06\ + oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSPEED06\ + oneof varid = SETUP_DATA.PcieRootPortSpeed[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SPEED_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SPEED_HELP),\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTDNCD06\ + oneof varid = SETUP_DATA.PcieRPDetectNonComplaint[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTRABUSRSVD06\ + numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_EXTRA_BUS_RESERVED,\ + step = 1,\ + default = 7,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 7, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVD06\ + numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVDALIG06\ + numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVD06\ + numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_PF_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVDALIG06\ + numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEIORSVD06\ + numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_PCIE_IO_RESERVED,\ + step = 4,\ + default = 8,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 8, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIELTRENABLE06\ + oneof varid = SETUP_DATA.PcieLtrEnable[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIELTRCONFIGLOCK06\ + oneof varid = SETUP_DATA.PcieLtrConfigLock[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE06\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER06\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMultiplier[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE06\ + numeric varid = SETUP_DATA.PcieSnoopLatencyOverrideValue[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1020,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE06\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER06\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMultiplier[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE06\ + numeric varid = SETUP_DATA.PcieNonSnoopLatencyOverrideValue[OFFSET_6],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; +//------------------------------------------------------------------------------------ + +#define SB_ONEOF_PCIEROOTPORTEN07\ + oneof varid = SETUP_DATA.PcieRootPortEn[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIERP8_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIERP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTASPM07\ + oneof varid = SETUP_DATA.PcieRootPortAspm[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCIE_ASPM_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_ASPM_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0S_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L1_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_ASPM_L0SL1_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 4, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTL1S07\ + oneof varid = SETUP_DATA.PcieRootPortL1S[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCIE_L1S_PROMPT),\ + help = STRING_TOKEN (STR_PCIE_L1S_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L12_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCIE_L1S_L11_L12_STRING), value = 3, flags =DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTURE07\ + oneof varid = SETUP_DATA.PcieRootPortURE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_URE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_URE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTFEE07\ + oneof varid = SETUP_DATA.PcieRootPortFEE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_FEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_FEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTNFE07\ + oneof varid = SETUP_DATA.PcieRootPortNFE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCEE07\ + oneof varid = SETUP_DATA.PcieRootPortCEE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CEE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CEE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTCTD07\ + oneof varid = SETUP_DATA.PcieRootPortCTD[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_CTD_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_CTD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSFE07\ + oneof varid = SETUP_DATA.PcieRootPortSFE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SFE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SFE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSNE07\ + oneof varid = SETUP_DATA.PcieRootPortSNE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSCE07\ + oneof varid = SETUP_DATA.PcieRootPortSCE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTPMCE07\ + oneof varid = SETUP_DATA.PcieRootPortPMCE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PMCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PMCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTHPE07\ + oneof varid = SETUP_DATA.PcieRootPortHPE[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_HPE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_HPE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTSPEED07\ + oneof varid = SETUP_DATA.PcieRootPortSpeed[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SPEED_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SPEED_HELP),\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_PCH_PCIE_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIEROOTPORTDNCD07\ + oneof varid = SETUP_DATA.PcieRPDetectNonComplaint[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_COMPLIANCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTRABUSRSVD07\ + numeric varid = SETUP_DATA.ExtraBusRsvd[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RBUS_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_EXTRA_BUS_RESERVED,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RBUS_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVD07\ + numeric varid = SETUP_DATA.PcieMemRsvd[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEMEMRSVDALIG07\ + numeric varid = SETUP_DATA.PcieMemRsvdalig[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVD07\ + numeric varid = SETUP_DATA.PciePFMemRsvd[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = MAX_PCIE_PF_MEM_RESERVED,\ + step = 1,\ + default = 10,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_PROMPT), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEPFMEMRSVDALIG07\ + numeric varid = SETUP_DATA.PciePFMemRsvdalig[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 31,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_PCH_PCIE_PF_RMEM_ALIG_PROMPT), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIEIORSVD07\ + numeric varid = SETUP_DATA.PcieIoRsvd[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_RVIO_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = MAX_PCIE_IO_RESERVED,\ + step = 4,\ + default = 8,\ + option text = STRING_TOKEN (STR_PCH_PCIE_RVIO_PROMPT), value = 8, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIELTRENABLE07\ + oneof varid = SETUP_DATA.PcieLtrEnable[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIELTRCONFIGLOCK07\ + oneof varid = SETUP_DATA.PcieLtrConfigLock[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_LTR_CONFIGLOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE07\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER07\ + oneof varid = SETUP_DATA.PcieSnoopLatencyOverrideMultiplier[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE07\ + numeric varid = SETUP_DATA.PcieSnoopLatencyOverrideValue[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1020,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE07\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_MANUAL), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_AUTO), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER07\ + oneof varid = SETUP_DATA.PcieNonSnoopLatencyOverrideMultiplier[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_MULITIPLIER_HELP),\ + option text = STRING_TOKEN (STR_1_NS), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32_NS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1024_NS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_32768_NS), value = 3, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_1048576_NS), value = 4, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_33554432_NS), value = 5, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE07\ + numeric varid = SETUP_DATA.PcieNonSnoopLatencyOverrideValue[OFFSET_7],\ + prompt = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1023,\ + step = 1,\ + default = 60,\ + option text = STRING_TOKEN (STR_PCH_PCIE_NON_SNOOP_LATENCY_OVERRIDE_VALUE_PROMPT), value = 60, flags = MANUFACTURING; \ + endnumeric; +//---------------------------------------------------------------------------- +// ADVANCED - Atapi Configuration Form +//---------------------------------------------------------------------------- + +#define SB_ONEOF_AUTOTHERMALREPORT\ + checkbox varid = SETUP_DATA.AutoThermalReport,\ + prompt = STRING_TOKEN (STR_THERMAL_REPORTING_PROMPT),\ + help = STRING_TOKEN (STR_THERMAL_REPORTING_HELP),\ + flags = 1 | RESET_REQUIRED | MANUFACTURING,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_CRITICALTHERMALTRIPPOINT\ + oneof varid = SETUP_DATA.CriticalThermalTripPoint,\ + prompt = STRING_TOKEN (STR_ACPI_CRITICAL_THERMAL_TRIP_POINT),\ + help = STRING_TOKEN (STR_ACPI_CRITICAL_THERMAL_TRIP_POINT_HELP),\ + option text = STRING_TOKEN (STR_POR), value = 105, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING, key = 0;\ + option text = STRING_TOKEN (STR_15_C), value = 15, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_23_C), value = 23, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_31_C), value = 31, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_39_C), value = 39, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_47_C), value = 47, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_55_C), value = 55, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_63_C), value = 63, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_71_C), value = 71, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_79_C), value = 79, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_87_C), value = 87, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_95_C), value = 95, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_103_C), value = 103, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_111_C), value = 111, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_119_C), value = 119, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_127_C), value = 127, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_AC0TRIPPOINT\ + oneof varid = SETUP_DATA.Ac0TripPoint,\ + prompt = STRING_TOKEN (STR_ACPI_ACTIVE_THERMAL_TRIP_POINT_HIGH),\ + help = STRING_TOKEN (STR_ACPI_ACTIVE_THERMAL_TRIP_POINT_HELP_HIGH),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 127, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_15_C), value = 15, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_23_C), value = 23, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_31_C), value = 31, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_39_C), value = 39, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_47_C), value = 47, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_55_C), value = 55, flags = RESET_REQUIRED ,key = 0;\ + option text = STRING_TOKEN (STR_63_C), value = 63, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_71_C), value = 71, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING, key = 0;\ + option text = STRING_TOKEN (STR_79_C), value = 79, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_87_C), value = 87, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_95_C), value = 95, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_103_C), value = 103, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_111_C), value = 111, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_119_C), value = 119, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_AC0FANSPEED\ + numeric varid = SETUP_DATA.Ac0FanSpeed,\ + prompt = STRING_TOKEN (STR_AC0_FAN_SPEED),\ + help = STRING_TOKEN (STR_AC0_FAN_SPEED_HELP),\ + minimum = 0,\ + maximum = 100,\ + step = 1,\ + default = 100,\ + option text = STRING_TOKEN (STR_AC0_FAN_SPEED), value = 100, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_AC1TRIPPOINT\ + oneof varid = SETUP_DATA.Ac1TripPoint,\ + prompt = STRING_TOKEN (STR_ACPI_ACTIVE_THERMAL_TRIP_POINT_LOW),\ + help = STRING_TOKEN (STR_ACPI_ACTIVE_THERMAL_TRIP_POINT_HELP_LOW),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 127, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_15_C), value = 15, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_23_C), value = 23, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_31_C), value = 31, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_39_C), value = 39, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_47_C), value = 47, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_55_C), value = 55, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING, key = 0;\ + option text = STRING_TOKEN (STR_63_C), value = 63, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_71_C), value = 71, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_79_C), value = 79, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_87_C), value = 87, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_95_C), value = 95, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_103_C), value = 103, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_111_C), value = 111, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_119_C), value = 119, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_AC1FANSPEED\ + numeric varid = SETUP_DATA.Ac1FanSpeed,\ + prompt = STRING_TOKEN (STR_AC1_FAN_SPEED),\ + help = STRING_TOKEN (STR_AC1_FAN_SPEED_HELP),\ + minimum = 0,\ + maximum = 100,\ + step = 1,\ + default = 75,\ + option text = STRING_TOKEN (STR_AC1_FAN_SPEED), value = 75, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PASSIVETHERMALTRIPPOINT\ + oneof varid = SETUP_DATA.PassiveThermalTripPoint,\ + prompt = STRING_TOKEN (STR_ACPI_PASSIVE_THERMAL_TRIP_POINT),\ + help = STRING_TOKEN (STR_ACPI_PASSIVE_THERMAL_TRIP_POINT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 127, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_15_C), value = 15, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_23_C), value = 23, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_31_C), value = 31, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_39_C), value = 39, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_47_C), value = 47, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_55_C), value = 55, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_63_C), value = 63, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_71_C), value = 71, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_79_C), value = 79, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_87_C), value = 87, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_95_C), value = 95, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING, key = 0;\ + option text = STRING_TOKEN (STR_103_C), value = 103, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_111_C), value = 111, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_119_C), value = 119, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PASSIVETC1VALUE\ + numeric varid = SETUP_DATA.PassiveTc1Value,\ + prompt = STRING_TOKEN (STR_ACPI_PASSIVE_TC1_VALUE),\ + help = STRING_TOKEN (STR_ACPI_PASSIVE_TC1_VALUE_HELP),\ + minimum = 1,\ + maximum = 16,\ + step = 1,\ + default = 1,\ + option text = STRING_TOKEN (STR_ACPI_PASSIVE_TC1_VALUE), value = 1, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PASSIVETC2VALUE\ + numeric varid = SETUP_DATA.PassiveTc2Value,\ + prompt = STRING_TOKEN (STR_ACPI_PASSIVE_TC2_VALUE),\ + help = STRING_TOKEN (STR_ACPI_PASSIVE_TC2_VALUE_HELP),\ + minimum = 1,\ + maximum = 16,\ + step = 1,\ + default = 5,\ + option text = STRING_TOKEN (STR_ACPI_PASSIVE_TC2_VALUE), value = 5, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PASSIVETSPVALUE\ + numeric varid = SETUP_DATA.PassiveTspValue,\ + prompt = STRING_TOKEN (STR_ACPI_PASSIVE_TSP_VALUE),\ + help = STRING_TOKEN (STR_ACPI_PASSIVE_TSP_VALUE_HELP),\ + minimum = 2,\ + maximum = 32,\ + step = 2,\ + default = 10,\ + option text = STRING_TOKEN (STR_ACPI_PASSIVE_TSP_VALUE), value = 10, flags = MANUFACTURING; \ + endnumeric; + +#if defined iME_SUPPORT && iME_SUPPORT +#define SB_ONEOF_TRENABLED\ + checkbox varid = SETUP_DATA.TrEnabled,\ + prompt = STRING_TOKEN (STR_ME_TR_ENABLED_PROMPT),\ + help = STRING_TOKEN (STR_ME_TR_ENABLED_HELP),\ + flags = 0 | MANUFACTURING,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_SMBUSECMSGLEN\ + oneof varid = SETUP_DATA.SMBusECMsgLen,\ + prompt = STRING_TOKEN (STR_TR_SMBUS_EC_LEN_PROMPT),\ + help = STRING_TOKEN (STR_TR_SMBUS_EC_LEN_HELP),\ + option text = STRING_TOKEN (STR_SMBUS_EC_MSG_LEN_1_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SMBUS_EC_MSG_LEN_2_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SMBUS_EC_MSG_LEN_5_STRING), value = 5, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SMBUS_EC_MSG_LEN_9_STRING), value = 9, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SMBUS_EC_MSG_LEN_10_STRING), value = 10, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SMBUS_EC_MSG_LEN_14_STRING), value = 14, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SMBUS_EC_MSG_LEN_20_STRING), value = 20, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SMBUSECMSGPEC\ + checkbox varid = SETUP_DATA.SMBusECMsgPEC,\ + prompt = STRING_TOKEN (STR_TR_SMBUS_EC_PEC_PROMPT),\ + help = STRING_TOKEN (STR_TR_SMBUS_EC_PEC_HELP),\ + flags = 0 | RESET_REQUIRED,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_TSONDIMM1\ + checkbox varid = SETUP_DATA.TsOnDimm1,\ + prompt = STRING_TOKEN (STR_DIMM1_TS_READ),\ + help = STRING_TOKEN (STR_DIMM1_TS_READ_HELP),\ + flags = 0 | RESET_REQUIRED,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_TSONDIMM2\ + checkbox varid = SETUP_DATA.TsOnDimm2,\ + prompt = STRING_TOKEN (STR_DIMM2_TS_READ),\ + help = STRING_TOKEN (STR_DIMM2_TS_READ_HELP),\ + flags = 0 | RESET_REQUIRED,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_TSONDIMM3\ + checkbox varid = SETUP_DATA.TsOnDimm3,\ + prompt = STRING_TOKEN (STR_DIMM3_TS_READ),\ + help = STRING_TOKEN (STR_DIMM3_TS_READ_HELP),\ + flags = 0 | RESET_REQUIRED,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_TSONDIMM4\ + checkbox varid = SETUP_DATA.TsOnDimm4,\ + prompt = STRING_TOKEN (STR_DIMM4_TS_READ),\ + help = STRING_TOKEN (STR_DIMM4_TS_READ_HELP),\ + flags = 0 | RESET_REQUIRED,\ + key = 0,\ + endcheckbox; + +#endif + + +#define SB_ONEOF_THERMALDEVICEENABLE\ + checkbox varid = SETUP_DATA.ThermalDeviceEnable,\ + prompt = STRING_TOKEN (STR_THERMAL_DEVICE_ENABLE),\ + help = STRING_TOKEN (STR_THERMAL_DEVICE_ENABLE_HELP),\ + flags = 0 | RESET_REQUIRED,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_PCHCROSSTHROTTLING\ + checkbox varid = SETUP_DATA.PchCrossThrottling,\ + prompt = STRING_TOKEN (STR_PCH_CROSS_THROTTLING_ENABLE),\ + help = STRING_TOKEN (STR_PCH_CROSS_THROTTLING_ENABLE_HELP),\ + flags = 0 | RESET_REQUIRED,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_PCHTEMPREADENABLE\ + checkbox varid = SETUP_DATA.PCHTempReadEnable,\ + prompt = STRING_TOKEN (STR_PCH_TEMP_READ),\ + help = STRING_TOKEN (STR_PCH_TEMP_READ_HELP),\ + flags = 1 | RESET_REQUIRED | MANUFACTURING,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_CPUENERGYREADENABLE\ + checkbox varid = SETUP_DATA.CPUEnergyReadEnable,\ + prompt = STRING_TOKEN (STR_CPU_ENERGY_READ),\ + help = STRING_TOKEN (STR_CPU_ENERGY_READ_HELP),\ + flags = 1 | RESET_REQUIRED | MANUFACTURING,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_CPUTEMPREADENABLE\ + checkbox varid = SETUP_DATA.CPUTempReadEnable,\ + prompt = STRING_TOKEN (STR_CPU_TEMP_READ),\ + help = STRING_TOKEN (STR_CPU_TEMP_READ_HELP),\ + flags = 1 | RESET_REQUIRED | MANUFACTURING,\ + key = 0,\ + endcheckbox; + +#define SB_ONEOF_ALERTENABLELOCK\ + oneof varid = SETUP_DATA.AlertEnableLock,\ + prompt = STRING_TOKEN (STR_ALERT_ENABLE_LOCK),\ + help = STRING_TOKEN (STR_ALERT_ENABLE_LOCK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHALERT\ + oneof varid = SETUP_DATA.PchAlert,\ + prompt = STRING_TOKEN (STR_PCH_ALERT),\ + help = STRING_TOKEN (STR_PCH_ALERT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_DIMMALERT\ + oneof varid = SETUP_DATA.DimmAlert,\ + prompt = STRING_TOKEN (STR_DIMM_ALERT),\ + help = STRING_TOKEN (STR_DIMM_ALERT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_PCHHOTLEVEL\ + numeric varid = SETUP_DATA.PchHotLevel,\ + prompt = STRING_TOKEN (STR_PCH_HOT_LEVEL),\ + help = STRING_TOKEN (STR_STR_PCH_HOT_LVL_HELP),\ + minimum = 0,\ + maximum = 127,\ + step = 1,\ + default = 0, \ + option text = STRING_TOKEN (STR_PCH_HOT_LEVEL), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_PCHSATA\ + oneof varid = SETUP_DATA.PchSata,\ + prompt = STRING_TOKEN (STR_PCH_SATA_PROMPT),\ + help = STRING_TOKEN (STR_PCH_SATA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAINTERFACEMODE\ + oneof varid = SETUP_DATA.SataInterfaceMode,\ + prompt = STRING_TOKEN (STR_SATA_MODE_SELECTION_PROMPT),\ + help = STRING_TOKEN (STR_SATA_MODE_SELECTION_HELP),\ + option text = STRING_TOKEN (STR_SATA_IDE), value = SATA_MODE_IDE, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_AHCI), value = SATA_MODE_AHCI, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_RAID), value = SATA_MODE_RAID, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ULTSATAINTERFACEMODE\ + oneof varid = SETUP_DATA.ULTSataInterfaceMode,\ + prompt = STRING_TOKEN (STR_SATA_MODE_SELECTION_PROMPT),\ + help = STRING_TOKEN (STR_SATA_MODE_SELECTION_HELP),\ + option text = STRING_TOKEN (STR_SATA_AHCI), value = SATA_MODE_AHCI, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_RAID), value = SATA_MODE_RAID, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATATESTMODE\ + oneof varid = SETUP_DATA.SataTestMode,\ + prompt = STRING_TOKEN (STR_SATA_TEST_MODE_PROMPT),\ + help = STRING_TOKEN (STR_SATA_TEST_MODE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#if SataDriver_SUPPORT +#define SB_ONEOF_SATARAIDROM\ + oneof varid = SETUP_DATA.SataRaidRom,\ + prompt = STRING_TOKEN (STR_SATA_ROM_PROMPT),\ + help = STRING_TOKEN (STR_SATA_ROM_HELP),\ + option text = STRING_TOKEN (STR_SATA_LEGACYROM), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_UEFIRAID), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_BOTH), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; +#endif + +#define SB_ONEOF_SALPSUPPORT\ + oneof varid = SETUP_DATA.SalpSupport,\ + prompt = STRING_TOKEN (STR_SATA_AHCI_SALP),\ + help = STRING_TOKEN (STR_SATA_AHCI_SALP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATACONTROLLERSPEED\ + oneof varid = SETUP_DATA.SataControllerSpeed,\ + prompt = STRING_TOKEN (STR_SATA_SPEED),\ + help = STRING_TOKEN (STR_SATA_SPEED_HELP),\ + option text = STRING_TOKEN (STR_SATA_SPEED_DEFAULT), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_SPEED_GEN1), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_SPEED_GEN2), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_SPEED_GEN3), value = 3, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAALTERNATEID\ + oneof varid = SETUP_DATA.SataAlternateId,\ + prompt = STRING_TOKEN (STR_SATA_ALTERNATE_ID_PROMPT),\ + help = STRING_TOKEN (STR_SATA_ALTERNATE_ID_HELP),\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAPORT0\ + oneof varid = SETUP_DATA.SataPort[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_PORT_0),\ + help = STRING_TOKEN (STR_SATA_PORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAHOTPLUG0\ + oneof varid = SETUP_DATA.SataHotPlug[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_HOTPLUG),\ + help = STRING_TOKEN (STR_SATA_PORT_HOTPLUG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAMECHANICALSW0\ + oneof varid = SETUP_DATA.SataMechanicalSw[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_MECHANICAL_SW),\ + help = STRING_TOKEN (STR_SATA_MECHANICAL_SW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTERNALSATA0\ + oneof varid = SETUP_DATA.ExternalSata[OFFSET_0],\ + prompt = STRING_TOKEN (STR_EXTERNAL_SATA),\ + help = STRING_TOKEN (STR_EXTERNAL_SATA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SOLIDSTATEDRIVE0\ + oneof varid = SETUP_DATA.SolidStateDrive[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_DEVICE_TYPE),\ + help = STRING_TOKEN (STR_SATA_DEVICE_TYPE_HELP),\ + option text = STRING_TOKEN (STR_SATA_DEVICE_HDD), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_DEVICE_SSD), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATASPINUP0\ + oneof varid = SETUP_DATA.SataSpinUp[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_SPIN_UP),\ + help = STRING_TOKEN (STR_SATA_SPIN_UP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATADEVSLP0\ + oneof varid = SETUP_DATA.SataDevSlp[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_DEV_SLP),\ + help = STRING_TOKEN (STR_SATA_DEV_SLP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAENABLEDITOCONFIGP0\ + oneof varid = SETUP_DATA.SataEnableDitoConfig[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_DITO_CONF),\ + help = STRING_TOKEN (STR_SATA_DITO_CONF_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATADITOVALP0\ + numeric varid = SETUP_DATA.SataDitoVal[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_DITOVAL_CONF),\ + help = STRING_TOKEN (STR_SATA_DITOVAL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1000,\ + step = 1,\ + default = 625,\ + option text = STRING_TOKEN (STR_SATA_DITOVAL_CONF), value = 625, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SATADMVALP0\ + numeric varid = SETUP_DATA.SataDmVal[OFFSET_0],\ + prompt = STRING_TOKEN (STR_SATA_DMVAL_CONF),\ + help = STRING_TOKEN (STR_SATA_DMVAL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 15,\ + step = 1,\ + default = 15,\ + option text = STRING_TOKEN (STR_SATA_DMVAL_CONF), value = 15, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SATAPORT1\ + oneof varid = SETUP_DATA.SataPort[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_PORT_1),\ + help = STRING_TOKEN (STR_SATA_PORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAHOTPLUG1\ + oneof varid = SETUP_DATA.SataHotPlug[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_HOTPLUG),\ + help = STRING_TOKEN (STR_SATA_PORT_HOTPLUG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAMECHANICALSW1\ + oneof varid = SETUP_DATA.SataMechanicalSw[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_MECHANICAL_SW),\ + help = STRING_TOKEN (STR_SATA_MECHANICAL_SW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTERNALSATA1\ + oneof varid = SETUP_DATA.ExternalSata[OFFSET_1],\ + prompt = STRING_TOKEN (STR_EXTERNAL_SATA),\ + help = STRING_TOKEN (STR_EXTERNAL_SATA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SOLIDSTATEDRIVE1\ + oneof varid = SETUP_DATA.SolidStateDrive[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_DEVICE_TYPE),\ + help = STRING_TOKEN (STR_SATA_DEVICE_TYPE_HELP),\ + option text = STRING_TOKEN (STR_SATA_DEVICE_HDD), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_DEVICE_SSD), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATASPINUP1\ + oneof varid = SETUP_DATA.SataSpinUp[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_SPIN_UP),\ + help = STRING_TOKEN (STR_SATA_SPIN_UP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATADEVSLP1\ + oneof varid = SETUP_DATA.SataDevSlp[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_DEV_SLP),\ + help = STRING_TOKEN (STR_SATA_DEV_SLP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAENABLEDITOCONFIGP1\ + oneof varid = SETUP_DATA.SataEnableDitoConfig[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_DITO_CONF),\ + help = STRING_TOKEN (STR_SATA_DITO_CONF_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATADITOVALP1\ + numeric varid = SETUP_DATA.SataDitoVal[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_DITOVAL_CONF),\ + help = STRING_TOKEN (STR_SATA_DITOVAL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1000,\ + step = 1,\ + default = 625,\ + option text = STRING_TOKEN (STR_SATA_DITOVAL_CONF), value = 625, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SATADMVALP1\ + numeric varid = SETUP_DATA.SataDmVal[OFFSET_1],\ + prompt = STRING_TOKEN (STR_SATA_DMVAL_CONF),\ + help = STRING_TOKEN (STR_SATA_DMVAL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 15,\ + step = 1,\ + default = 15,\ + option text = STRING_TOKEN (STR_SATA_DMVAL_CONF), value = 15, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SATAPORT2\ + oneof varid = SETUP_DATA.SataPort[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_PORT_2),\ + help = STRING_TOKEN (STR_SATA_PORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAHOTPLUG2\ + oneof varid = SETUP_DATA.SataHotPlug[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_HOTPLUG),\ + help = STRING_TOKEN (STR_SATA_PORT_HOTPLUG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAMECHANICALSW2\ + oneof varid = SETUP_DATA.SataMechanicalSw[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_MECHANICAL_SW),\ + help = STRING_TOKEN (STR_SATA_MECHANICAL_SW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTERNALSATA2\ + oneof varid = SETUP_DATA.ExternalSata[OFFSET_2],\ + prompt = STRING_TOKEN (STR_EXTERNAL_SATA),\ + help = STRING_TOKEN (STR_EXTERNAL_SATA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SOLIDSTATEDRIVE2\ + oneof varid = SETUP_DATA.SolidStateDrive[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_DEVICE_TYPE),\ + help = STRING_TOKEN (STR_SATA_DEVICE_TYPE_HELP),\ + option text = STRING_TOKEN (STR_SATA_DEVICE_HDD), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_DEVICE_SSD), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATASPINUP2\ + oneof varid = SETUP_DATA.SataSpinUp[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_SPIN_UP),\ + help = STRING_TOKEN (STR_SATA_SPIN_UP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATADEVSLP2\ + oneof varid = SETUP_DATA.SataDevSlp[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_DEV_SLP),\ + help = STRING_TOKEN (STR_SATA_DEV_SLP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAENABLEDITOCONFIGP2\ + oneof varid = SETUP_DATA.SataEnableDitoConfig[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_DITO_CONF),\ + help = STRING_TOKEN (STR_SATA_DITO_CONF_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATADITOVALP2\ + numeric varid = SETUP_DATA.SataDitoVal[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_DITOVAL_CONF),\ + help = STRING_TOKEN (STR_SATA_DITOVAL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 1000,\ + step = 1,\ + default = 625,\ + option text = STRING_TOKEN (STR_SATA_DITOVAL_CONF), value = 625, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SATADMVALP2\ + numeric varid = SETUP_DATA.SataDmVal[OFFSET_2],\ + prompt = STRING_TOKEN (STR_SATA_DMVAL_CONF),\ + help = STRING_TOKEN (STR_SATA_DMVAL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 15,\ + step = 1,\ + default = 15,\ + option text = STRING_TOKEN (STR_SATA_DMVAL_CONF), value = 15, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SATAPORT3\ + oneof varid = SETUP_DATA.SataPort[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_PORT_3),\ + help = STRING_TOKEN (STR_SATA_PORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAHOTPLUG3\ + oneof varid = SETUP_DATA.SataHotPlug[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_HOTPLUG),\ + help = STRING_TOKEN (STR_SATA_PORT_HOTPLUG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAMECHANICALSW3\ + oneof varid = SETUP_DATA.SataMechanicalSw[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_MECHANICAL_SW),\ + help = STRING_TOKEN (STR_SATA_MECHANICAL_SW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTERNALSATA3\ + oneof varid = SETUP_DATA.ExternalSata[OFFSET_3],\ + prompt = STRING_TOKEN (STR_EXTERNAL_SATA),\ + help = STRING_TOKEN (STR_EXTERNAL_SATA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SOLIDSTATEDRIVE3\ + oneof varid = SETUP_DATA.SolidStateDrive[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_DEVICE_TYPE),\ + help = STRING_TOKEN (STR_SATA_DEVICE_TYPE_HELP),\ + option text = STRING_TOKEN (STR_SATA_DEVICE_HDD), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_DEVICE_SSD), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATASPINUP3\ + oneof varid = SETUP_DATA.SataSpinUp[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_SPIN_UP),\ + help = STRING_TOKEN (STR_SATA_SPIN_UP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATADEVSLP3\ + oneof varid = SETUP_DATA.SataDevSlp[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_DEV_SLP),\ + help = STRING_TOKEN (STR_SATA_DEV_SLP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAENABLEDITOCONFIGP3\ + oneof varid = SETUP_DATA.SataEnableDitoConfig[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_DITO_CONF),\ + help = STRING_TOKEN (STR_SATA_DITO_CONF_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATADITOVALP3\ + numeric varid = SETUP_DATA.SataDitoVal[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_DITOVAL_CONF),\ + help = STRING_TOKEN (STR_SATA_DITOVAL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 1000,\ + step = 1,\ + default = 625,\ + option text = STRING_TOKEN (STR_SATA_DITOVAL_CONF), value = 625, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SATADMVALP3\ + numeric varid = SETUP_DATA.SataDmVal[OFFSET_3],\ + prompt = STRING_TOKEN (STR_SATA_DMVAL_CONF),\ + help = STRING_TOKEN (STR_SATA_DMVAL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 15,\ + step = 1,\ + default = 15,\ + option text = STRING_TOKEN (STR_SATA_DMVAL_CONF), value = 15, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SATAPORT4\ + oneof varid = SETUP_DATA.SataPort[OFFSET_4],\ + prompt = STRING_TOKEN (STR_SATA_PORT_4),\ + help = STRING_TOKEN (STR_SATA_PORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAHOTPLUG4\ + oneof varid = SETUP_DATA.SataHotPlug[OFFSET_4],\ + prompt = STRING_TOKEN (STR_SATA_HOTPLUG),\ + help = STRING_TOKEN (STR_SATA_PORT_HOTPLUG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAMECHANICALSW4\ + oneof varid = SETUP_DATA.SataMechanicalSw[OFFSET_4],\ + prompt = STRING_TOKEN (STR_SATA_MECHANICAL_SW),\ + help = STRING_TOKEN (STR_SATA_MECHANICAL_SW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTERNALSATA4\ + oneof varid = SETUP_DATA.ExternalSata[OFFSET_4],\ + prompt = STRING_TOKEN (STR_EXTERNAL_SATA),\ + help = STRING_TOKEN (STR_EXTERNAL_SATA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SOLIDSTATEDRIVE4\ + oneof varid = SETUP_DATA.SolidStateDrive[OFFSET_4],\ + prompt = STRING_TOKEN (STR_SATA_DEVICE_TYPE),\ + help = STRING_TOKEN (STR_SATA_DEVICE_TYPE_HELP),\ + option text = STRING_TOKEN (STR_SATA_DEVICE_HDD), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_DEVICE_SSD), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATASPINUP4\ + oneof varid = SETUP_DATA.SataSpinUp[OFFSET_4],\ + prompt = STRING_TOKEN (STR_SATA_SPIN_UP),\ + help = STRING_TOKEN (STR_SATA_SPIN_UP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAPORT5\ + oneof varid = SETUP_DATA.SataPort[OFFSET_5],\ + prompt = STRING_TOKEN (STR_SATA_PORT_5),\ + help = STRING_TOKEN (STR_SATA_PORT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAHOTPLUG5\ + oneof varid = SETUP_DATA.SataHotPlug[OFFSET_5],\ + prompt = STRING_TOKEN (STR_SATA_HOTPLUG),\ + help = STRING_TOKEN (STR_SATA_PORT_HOTPLUG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAMECHANICALSW5\ + oneof varid = SETUP_DATA.SataMechanicalSw[OFFSET_5],\ + prompt = STRING_TOKEN (STR_SATA_MECHANICAL_SW),\ + help = STRING_TOKEN (STR_SATA_MECHANICAL_SW_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EXTERNALSATA5\ + oneof varid = SETUP_DATA.ExternalSata[OFFSET_5],\ + prompt = STRING_TOKEN (STR_EXTERNAL_SATA),\ + help = STRING_TOKEN (STR_EXTERNAL_SATA_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SOLIDSTATEDRIVE5\ + oneof varid = SETUP_DATA.SolidStateDrive[OFFSET_5],\ + prompt = STRING_TOKEN (STR_SATA_DEVICE_TYPE),\ + help = STRING_TOKEN (STR_SATA_DEVICE_TYPE_HELP),\ + option text = STRING_TOKEN (STR_SATA_DEVICE_HDD), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_SATA_DEVICE_SSD), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATASPINUP5\ + oneof varid = SETUP_DATA.SataSpinUp[OFFSET_5],\ + prompt = STRING_TOKEN (STR_SATA_SPIN_UP),\ + help = STRING_TOKEN (STR_SATA_SPIN_UP_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATARAIDR0\ + oneof varid = SETUP_DATA.SataRaidR0,\ + prompt = STRING_TOKEN (STR_PCH_RAID0_PROMPT),\ + help = STRING_TOKEN (STR_PCH_RAID0_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATARAIDR1\ + oneof varid = SETUP_DATA.SataRaidR1,\ + prompt = STRING_TOKEN (STR_PCH_RAID1_PROMPT),\ + help = STRING_TOKEN (STR_PCH_RAID1_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATARAIDR10\ + oneof varid = SETUP_DATA.SataRaidR10,\ + prompt = STRING_TOKEN (STR_PCH_RAID10_PROMPT),\ + help = STRING_TOKEN (STR_PCH_RAID10_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATARAIDR5\ + oneof varid = SETUP_DATA.SataRaidR5,\ + prompt = STRING_TOKEN (STR_PCH_RAID5_PROMPT),\ + help = STRING_TOKEN (STR_PCH_RAID5_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATARAIDIRRT\ + oneof varid = SETUP_DATA.SataRaidIrrt,\ + prompt = STRING_TOKEN (STR_PCH_IRRT_PROMPT),\ + help = STRING_TOKEN (STR_PCH_IRRT_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATARAIDOUB\ + oneof varid = SETUP_DATA.SataRaidOub,\ + prompt = STRING_TOKEN (STR_PCH_OUB_PROMPT),\ + help = STRING_TOKEN (STR_PCH_OUB_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATAHDDLK\ + oneof varid = SETUP_DATA.SataHddlk,\ + prompt = STRING_TOKEN (STR_PCH_HDDLK_PROMPT),\ + help = STRING_TOKEN (STR_PCH_HDDLK_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATALEDL\ + oneof varid = SETUP_DATA.SataLedl,\ + prompt = STRING_TOKEN (STR_PCH_LEDL_PROMPT),\ + help = STRING_TOKEN (STR_PCH_LEDL_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SATARAIDIOOE\ + oneof varid = SETUP_DATA.SataRaidIooe,\ + prompt = STRING_TOKEN (STR_PCH_IOOE_PROMPT),\ + help = STRING_TOKEN (STR_PCH_IOOE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SMARTSTORAGE\ + oneof varid = SETUP_DATA.SmartStorage,\ + prompt = STRING_TOKEN (STR_PCH_SMARTS_PROMPT),\ + help = STRING_TOKEN (STR_PCH_SMARTS_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_OROMUIDELAY\ + oneof varid = SETUP_DATA.OromUiDelay,\ + prompt = STRING_TOKEN (STR_PCH_OROM_DELAL_PROMPT),\ + help = STRING_TOKEN (STR_PCH_OROM_DELAL_HELP),\ + option text = STRING_TOKEN (STR_2_SECS_DELAY_STRING), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_4_SECS_DELAY_STRING), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_6_SECS_DELAY_STRING), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_8_SECS_DELAY_STRING), value = 3, flags = RESET_REQUIRED, key = 0;\ + endoneof; +//---------------------------------------------------------------------------- +// PCH LP LPSS +//---------------------------------------------------------------------------- + +#define SB_ONEOF_LPSSDMAENABLE\ + oneof varid = SETUP_DATA.LpssDmaEnable,\ + prompt = STRING_TOKEN (STR_LPSS_DMA_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_DEVICE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_AUTO_BY_OS), value = 2, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSI2C0ENABLE\ + oneof varid = SETUP_DATA.LpssI2c0Enable,\ + prompt = STRING_TOKEN (STR_LPSS_I2C0_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_DEVICE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSI2C1ENABLE\ + oneof varid = SETUP_DATA.LpssI2c1Enable,\ + prompt = STRING_TOKEN (STR_LPSS_I2C1_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_DEVICE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSSPI0ENABLE\ + oneof varid = SETUP_DATA.LpssSpi0Enable,\ + prompt = STRING_TOKEN (STR_LPSS_SPI0_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_DEVICE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSSPI1ENABLE\ + oneof varid = SETUP_DATA.LpssSpi1Enable,\ + prompt = STRING_TOKEN (STR_LPSS_SPI1_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_DEVICE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSUART0ENABLE\ + oneof varid = SETUP_DATA.LpssUart0Enable,\ + prompt = STRING_TOKEN (STR_LPSS_UART0_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_DEVICE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSUART1ENABLE\ + oneof varid = SETUP_DATA.LpssUart1Enable,\ + prompt = STRING_TOKEN (STR_LPSS_UART1_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_DEVICE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSSDIOENABLE\ + oneof varid = SETUP_DATA.LpssSdioEnable,\ + prompt = STRING_TOKEN (STR_LPSS_SDIO_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_DEVICE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSMODE\ + oneof varid = SETUP_DATA.LpssMode,\ + prompt = STRING_TOKEN (STR_LPSS_MODE_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_MODE_HELP),\ + option text = STRING_TOKEN (STR_LPSS_ADSP_MODE_ACPI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_LPSS_ADSP_MODE_PCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSINTMODE\ + oneof varid = SETUP_DATA.LpssIntMode,\ + prompt = STRING_TOKEN (STR_LPSS_INTMODE_PROMPT),\ + help = STRING_TOKEN (STR_LPSS_MODE_HELP),\ + option text = STRING_TOKEN (STR_LPSS_ADSP_MODE_ACPI), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_LPSS_ADSP_MODE_PCI), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSI2C0VOLSELECT\ + oneof varid = SETUP_DATA.I2C0VoltageSelect,\ + prompt = STRING_TOKEN (STR_I2C_VOL_PROMPT),\ + help = STRING_TOKEN (STR_I2C_VOL_HELP),\ + option text = STRING_TOKEN (STR_I2C_VOL_33V), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_I2C_VOL_18V), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_LPSSI2C1VOLSELECT\ + oneof varid = SETUP_DATA.I2C1VoltageSelect,\ + prompt = STRING_TOKEN (STR_I2C_VOL_PROMPT),\ + help = STRING_TOKEN (STR_I2C_VOL_HELP),\ + option text = STRING_TOKEN (STR_I2C_VOL_33V), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_I2C_VOL_18V), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_SENSORHUB\ + oneof varid = SETUP_DATA.SensorHub,\ + prompt = STRING_TOKEN (STR_I2C_SEN_HUB_PROMPT),\ + help = STRING_TOKEN (STR_I2C_SEN_HUB_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_TPD4\ + oneof varid = SETUP_DATA.TPD4,\ + prompt = STRING_TOKEN (STR_I2C_TPD4_PROMPT),\ + help = STRING_TOKEN (STR_I2C_TPD4_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + + #if BHB_BOARD == 1 +#define SB_ONEOF_ATMELTPL\ + oneof varid = SETUP_DATA.AtmelTPL,\ + prompt = STRING_TOKEN (STR_I2C_ATMTPL_PROMPT),\ + help = STRING_TOKEN (STR_I2C_ATMTPL_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + #else //BHB_BOARD == 0 +#define SB_ONEOF_ATMELTPL\ + oneof varid = SETUP_DATA.AtmelTPL,\ + prompt = STRING_TOKEN (STR_I2C_ATMTPL_PROMPT),\ + help = STRING_TOKEN (STR_I2C_ATMTPL_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + #endif //BHB_BOARD + +#define SB_ONEOF_ELANTPL\ + oneof varid = SETUP_DATA.ElanTPL,\ + prompt = STRING_TOKEN (STR_I2C_ELATPL_PROMPT),\ + help = STRING_TOKEN (STR_I2C_ELATPL_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ELANTPD\ + oneof varid = SETUP_DATA.ElanTPD,\ + prompt = STRING_TOKEN (STR_I2C_ELANTPD_PROMPT),\ + help = STRING_TOKEN (STR_I2C_ELANTPD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + + #if BHB_BOARD == 1 +#define SB_ONEOF_SYNATPD\ + oneof varid = SETUP_DATA.SynaTPD,\ + prompt = STRING_TOKEN (STR_I2C_SYNATPD_PROMPT),\ + help = STRING_TOKEN (STR_I2C_SYNATPD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + #else //BHB_BOARD == 0 +#define SB_ONEOF_SYNATPD\ + oneof varid = SETUP_DATA.SynaTPD,\ + prompt = STRING_TOKEN (STR_I2C_SYNATPD_PROMPT),\ + help = STRING_TOKEN (STR_I2C_SYNATPD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + #endif //BHB_BOARD + +#define SB_ONEOF_NTRITPL\ + oneof varid = SETUP_DATA.NtriTPL,\ + prompt = STRING_TOKEN (STR_I2C_NTRITPL_PROMPT),\ + help = STRING_TOKEN (STR_I2C_NTRITPL_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_EETITPL\ + oneof varid = SETUP_DATA.EetiTPL,\ + prompt = STRING_TOKEN (STR_I2C_EETITPL_PROMPT),\ + help = STRING_TOKEN (STR_I2C_EETITPL_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ALPSTPD\ + oneof varid = SETUP_DATA.AlpsTPD,\ + prompt = STRING_TOKEN (STR_I2C_ALPSTPD_PROMPT),\ + help = STRING_TOKEN (STR_I2C_ALPSTPD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_CYPRTPD\ + oneof varid = SETUP_DATA.CyprTPD,\ + prompt = STRING_TOKEN (STR_I2C_CYPRTPD_PROMPT),\ + help = STRING_TOKEN (STR_I2C_CYPRTPD_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_BLUETOOTH0\ + oneof varid = SETUP_DATA.Bluetooth0,\ + prompt = STRING_TOKEN (STR_UART_BLUETOOTH_PROMPT),\ + help = STRING_TOKEN (STR_UART_BLUETOOTH_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_BLUETOOTH1\ + oneof varid = SETUP_DATA.Bluetooth1,\ + prompt = STRING_TOKEN (STR_UART_BLUETOOTH_PROMPT),\ + help = STRING_TOKEN (STR_UART_BLUETOOTH_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_I2C0SSH\ + numeric varid = SETUP_DATA.I2C0SSH,\ + prompt = STRING_TOKEN (STR_I2C_I2C0SSH_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0SSH_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 6,\ + maximum = 65525,\ + step = 1,\ + default = 432,\ + option text = STRING_TOKEN (STR_I2C_I2C0SSH_CONF), value = 432, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0SSL\ + numeric varid = SETUP_DATA.I2C0SSL,\ + prompt = STRING_TOKEN (STR_I2C_I2C0SSL_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0SSL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 8,\ + maximum = 65535,\ + step = 1,\ + default = 507,\ + option text = STRING_TOKEN (STR_I2C_I2C0SSL_CONF), value = 507, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0SSD\ + numeric varid = SETUP_DATA.I2C0SSD,\ + prompt = STRING_TOKEN (STR_I2C_I2C0SSD_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0SSD_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 65535,\ + step = 1,\ + default = 9,\ + option text = STRING_TOKEN (STR_I2C_I2C0SSD_CONF), value = 9, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0FMH\ + numeric varid = SETUP_DATA.I2C0FMH,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FMH_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FMH_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 6,\ + maximum = 65535,\ + step = 1,\ + default = 72,\ + option text = STRING_TOKEN (STR_I2C_I2C0FMH_CONF), value = 72, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0FML\ + numeric varid = SETUP_DATA.I2C0FML,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FML_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FML_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 8,\ + maximum = 65535,\ + step = 1,\ + default = 160,\ + option text = STRING_TOKEN (STR_I2C_I2C0FML_CONF), value = 160, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0FMD\ + numeric varid = SETUP_DATA.I2C0FMD,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FMD_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FMD_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 65535,\ + step = 1,\ + default = 9,\ + option text = STRING_TOKEN (STR_I2C_I2C0FMD_CONF), value = 9, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0FPH\ + numeric varid = SETUP_DATA.I2C0FPH,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FPH_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FPH_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 6,\ + maximum = 65525,\ + step = 1,\ + default = 29,\ + option text = STRING_TOKEN (STR_I2C_I2C0FPH_CONF), value = 29, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0FPL\ + numeric varid = SETUP_DATA.I2C0FPL,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FPL_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FPL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 8,\ + maximum = 65535,\ + step = 1,\ + default = 50,\ + option text = STRING_TOKEN (STR_I2C_I2C0FPL_CONF), value = 50, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0FPD\ + numeric varid = SETUP_DATA.I2C0FPD,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FPD_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FPD_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 65535,\ + step = 1,\ + default = 5,\ + option text = STRING_TOKEN (STR_I2C_I2C0FPD_CONF), value = 5, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0M0C0\ + numeric varid = SETUP_DATA.I2C0M0C0,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 200,\ + option text = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF), value = 200, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0M1C0\ + numeric varid = SETUP_DATA.I2C0M1C0,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 2000,\ + option text = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF), value = 2000, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C0M2C0\ + numeric varid = SETUP_DATA.I2C0M2C0,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M2C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M2C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_I2C_I2C0M2C0_CONF), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1SSH\ + numeric varid = SETUP_DATA.I2C1SSH,\ + prompt = STRING_TOKEN (STR_I2C_I2C0SSH_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0SSH_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 6,\ + maximum = 65525,\ + step = 1,\ + default = 432,\ + option text = STRING_TOKEN (STR_I2C_I2C0SSH_CONF), value = 432, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1SSL\ + numeric varid = SETUP_DATA.I2C1SSL,\ + prompt = STRING_TOKEN (STR_I2C_I2C0SSL_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0SSL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 8,\ + maximum = 65535,\ + step = 1,\ + default = 507,\ + option text = STRING_TOKEN (STR_I2C_I2C0SSL_CONF), value = 507, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1SSD\ + numeric varid = SETUP_DATA.I2C1SSD,\ + prompt = STRING_TOKEN (STR_I2C_I2C0SSD_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0SSD_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 65535,\ + step = 1,\ + default = 9,\ + option text = STRING_TOKEN (STR_I2C_I2C0SSD_CONF), value = 9, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1FMH\ + numeric varid = SETUP_DATA.I2C1FMH,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FMH_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FMH_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 6,\ + maximum = 65535,\ + step = 1,\ + default = 72,\ + option text = STRING_TOKEN (STR_I2C_I2C0FMH_CONF), value = 72, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1FML\ + numeric varid = SETUP_DATA.I2C1FML,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FML_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FML_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 8,\ + maximum = 65535,\ + step = 1,\ + default = 160,\ + option text = STRING_TOKEN (STR_I2C_I2C0FML_CONF), value = 160, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1FMD\ + numeric varid = SETUP_DATA.I2C1FMD,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FMD_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FMD_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 65535,\ + step = 1,\ + default = 9,\ + option text = STRING_TOKEN (STR_I2C_I2C0FMD_CONF), value = 9, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1FPH\ + numeric varid = SETUP_DATA.I2C1FPH,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FPH_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FPH_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 6,\ + maximum = 65525,\ + step = 1,\ + default = 26,\ + option text = STRING_TOKEN (STR_I2C_I2C0FPH_CONF), value = 26, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1FPL\ + numeric varid = SETUP_DATA.I2C1FPL,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FPL_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FPL_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 8,\ + maximum = 65535,\ + step = 1,\ + default = 50,\ + option text = STRING_TOKEN (STR_I2C_I2C0FPL_CONF), value = 50, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1FPD\ + numeric varid = SETUP_DATA.I2C1FPD,\ + prompt = STRING_TOKEN (STR_I2C_I2C0FPD_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0FPD_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 1,\ + maximum = 65535,\ + step = 1,\ + default = 5,\ + option text = STRING_TOKEN (STR_I2C_I2C0FPD_CONF), value = 5, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1M0C1\ + numeric varid = SETUP_DATA.I2C1M0C1,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 200,\ + option text = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF), value = 200, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1M1C1\ + numeric varid = SETUP_DATA.I2C1M1C1,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 2000,\ + option text = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF), value = 2000, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_I2C1M2C1\ + numeric varid = SETUP_DATA.I2C1M2C1,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M2C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M2C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 0,\ + option text = STRING_TOKEN (STR_I2C_I2C0M2C0_CONF), value = 0, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SPI0M0C2\ + numeric varid = SETUP_DATA.SPI0M0C2,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 200,\ + option text = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF), value = 200, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SPI0M1C2\ + numeric varid = SETUP_DATA.SPI0M1C2,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 2000,\ + option text = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF), value = 2000, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SPI1M0C3\ + numeric varid = SETUP_DATA.SPI1M0C3,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 200,\ + option text = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF), value = 5200, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_SPI1M1C3\ + numeric varid = SETUP_DATA.SPI1M1C3,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 2000,\ + option text = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF), value = 2000, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_UAR0M0C4\ + numeric varid = SETUP_DATA.UAR0M0C4,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 200,\ + option text = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF), value = 200, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_UAR0M1C4\ + numeric varid = SETUP_DATA.UAR0M1C4,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 200,\ + option text = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF), value = 200, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_UAR1M0C5\ + numeric varid = SETUP_DATA.UAR1M0C5,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 200,\ + option text = STRING_TOKEN (STR_I2C_I2C0M0C0_CONF), value = 200, flags = MANUFACTURING; \ + endnumeric; + +#define SB_ONEOF_UAR1M1C5\ + numeric varid = SETUP_DATA.UAR1M1C5,\ + prompt = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF),\ + help = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF_HELP),\ + flags = RESET_REQUIRED,\ + minimum = 0,\ + maximum = 10000,\ + step = 1,\ + default = 200,\ + option text = STRING_TOKEN (STR_I2C_I2C0M1C0_CONF), value = 200, flags = MANUFACTURING; \ + endnumeric; +//---------------------------------------------------------------------------- +// PCH LP ADSP +//---------------------------------------------------------------------------- + +#define SB_ONEOF_ADSPENABLE\ + oneof varid = SETUP_DATA.ADspEnable,\ + prompt = STRING_TOKEN (STR_ADSP_ENABLE_PROMPT),\ + help = STRING_TOKEN (STR_ADSP_ENABLE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ADSPD3PG\ + oneof varid = SETUP_DATA.ADspD3PG,\ + prompt = STRING_TOKEN (STR_ADSP_D3PG_PROMPT),\ + help = STRING_TOKEN (STR_ADSP_D3PG_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ADSPCODECSELECT\ + oneof varid = SETUP_DATA.ADspCodecSelect,\ + prompt = STRING_TOKEN (STR_ADSP_CODECSELECT_PROMPT),\ + help = STRING_TOKEN (STR_ADSP_CODECSELECT_HELP),\ + option text = STRING_TOKEN (STR_ADSP_CODECSELECT_REALTEK), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ADSP_CODECSELECT_CIRRUS), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_ADSP_CODECSELECT_IDT), value = 2, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ADSPBLUETOOTH\ + oneof varid = SETUP_DATA.ADspBluetooth,\ + prompt = STRING_TOKEN (STR_ADSP_BLUETOOTH_PROMPT),\ + help = STRING_TOKEN (STR_ADSP_BLUETOOTH_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_ADSPMODE\ + oneof varid = SETUP_DATA.ADspMode,\ + prompt = STRING_TOKEN (STR_ADSP_MODE_PROMPT),\ + help = STRING_TOKEN (STR_ADSP_MODE_HELP),\ + option text = STRING_TOKEN (STR_LPSS_ADSP_MODE_PCI), value = 0, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_LPSS_ADSP_MODE_ACPI), value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + endoneof; + +#define SB_ONEOF_NFCE\ + oneof varid = SETUP_DATA.NFCE,\ + prompt = STRING_TOKEN (STR_NFCE_PROMPT),\ + help = STRING_TOKEN (STR_NFCE_HELP),\ + option text = STRING_TOKEN (STR_COMMON_DISABLED), value = 0, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_NFCE_SKTD000), value = 1, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_NFCE_NXP5442), value = 2, flags = RESET_REQUIRED, key = 0;\ + option text = STRING_TOKEN (STR_NFCE_ICV0A12), value = 3, flags = RESET_REQUIRED, key = 0;\ + endoneof; + +#endif // CONTROL_DEFINITION +//--------------------------------------------------------------------------- + +//--------------------------------------------------------------------------- +#ifdef CONTROLS_WITH_DEFAULTS + + SB_ONEOF_ECTG + SB_ONEOF_PCHLAN + SB_ONEOF_PCHWAKEONLAN + SB_ONEOF_PCHSLPLANLOW + SB_ONEOF_BOARDCAPABILITY + SB_ONEOF_DEEPSXBATTMODE + SB_ONEOF_DEEPSXMODE + SB_ONEOF_GP27WAKE + SB_ONEOF_PCIEWAKE + SB_ONEOF_ECTURBOCONTROLMODE + SB_ONEOF_ACBRICKCAPACITY + SB_ONEOF_ECPOLLINGPERIOD + SB_ONEOF_ECGUARDBANDVALUE + SB_ONEOF_ECALGORITHMSEL + SB_ONEOF_ECHYBRIDPOWERBOOST + SB_ONEOF_ECHYBRIDCURRENT + SB_ONEOF_PCHAZALIA + SB_ONEOF_AZALIADS + SB_ONEOF_AZALIAPME + SB_ONEOF_PCHDISPLAY + SB_ONEOF_PCHPCICLOCKRUN + SB_ONEOF_IRQMODE + SB_ONEOF_PCHENABLECRID + SB_ONEOF_SMILOCK + SB_ONEOF_BIOSLOCK + SB_ONEOF_GPIOLOCK + SB_ONEOF_BIOSINTERFACELOCK + SB_ONEOF_RTCLOCK +#if HPET_SUPPORT + SB_ONEOF_HPET +#endif + SB_ONEOF_SLPS4ASSW + SB_ONEOF_LASTSTATE + SB_ONEOF_PORT80 + SB_ONEOF_PCHUSBPRECONDITION + SB_ONEOF_PCHUSB30MODE +// SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_00 +// SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_01 +// SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_02 +// SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_03 + SB_ONEOF_PCHENABLERMH1 + SB_ONEOF_PCHUSB30PREBOOTSUPPORT + SB_ONEOF_PCHUSB30IDLEL1 + SB_ONEOF_PCHUSB30BTCG + SB_ONEOF_PCHUSB20PINROUTE + SB_ONEOF_USB20PERPINROUTE00 + SB_ONEOF_USB20PERPINROUTE01 + SB_ONEOF_USB20PERPINROUTE02 + SB_ONEOF_USB20PERPINROUTE03 + SB_ONEOF_USB20PERPINROUTE04 + SB_ONEOF_USB20PERPINROUTE05 + SB_ONEOF_USB20PERPINROUTE06 + SB_ONEOF_USB20PERPINROUTE07 + SB_ONEOF_USB20PERPINROUTE08 + SB_ONEOF_USB20PERPINROUTE09 + SB_ONEOF_USB20PERPINROUTE10 + SB_ONEOF_USB20PERPINROUTE11 + SB_ONEOF_USB20PERPINROUTE12 + SB_ONEOF_USB20PERPINROUTE13 + SB_ONEOF_PCHUSB30PINENABLE + SB_ONEOF_USB30PERPINENABLE1 + SB_ONEOF_USB30PERPINENABLE2 + SB_ONEOF_USB30PERPINENABLE3 + SB_ONEOF_USB30PERPINENABLE4 + SB_ONEOF_USB30PERPINENABLE5 + SB_ONEOF_USB30PERPINENABLE6 +// SB_ONEOF_XHCISTREAMS + SB_ONEOF_PCHUSB20OFF0 + SB_ONEOF_PCHUSB20OFF1 + SB_ONEOF_PCHUSBPERPORTCTL +#if EHCI_CON_DISCON_WAKE_UP_SUPPORT + SB_ONEOF_EHCICONDISCONWAKEUP +#endif + SB_ONEOF_PCHUSBPORT00 + SB_ONEOF_PCHUSBPORT01 + SB_ONEOF_PCHUSBPORT02 + SB_ONEOF_PCHUSBPORT03 + SB_ONEOF_PCHUSBPORT04 + SB_ONEOF_PCHUSBPORT05 + SB_ONEOF_PCHUSBPORT06 + SB_ONEOF_PCHUSBPORT07 + SB_ONEOF_PCHUSBPORT08 + SB_ONEOF_PCHUSBPORT09 + SB_ONEOF_PCHUSBPORT10 + SB_ONEOF_PCHUSBPORT11 + SB_ONEOF_PCHUSBPORT12 + SB_ONEOF_PCHUSBPORT13 + SB_ONEOF_PCHUSB30PORT00 + SB_ONEOF_PCHUSB30PORT01 + SB_ONEOF_PCHUSB30PORT02 + SB_ONEOF_PCHUSB30PORT03 + SB_ONEOF_PCHUSB30PORT04 + SB_ONEOF_PCHUSB30PORT05 + SB_ONEOF_PCIECLOCKGATING + SB_ONEOF_ROOTPORTFUNCTIONSWAPPING + SB_ONEOF_PCHDMIASPM + SB_ONEOF_PCHDMIEXTSYNC + SB_ONEOF_PCIEUSBWA + SB_ONEOF_PCIEROOTPORTSBDE + SB_ONEOF_PCIESBDEPORT + SB_ONEOF_LANRP1 + SB_ONEOF_LANRP2 + SB_ONEOF_LANRP3 + SB_ONEOF_LANRP4 + SB_ONEOF_LANRP5 + SB_ONEOF_LANRP6 + SB_ONEOF_LANRP7 + SB_ONEOF_LANRP8 + SB_ONEOF_PCIEROOTPORTEN00 + SB_ONEOF_PCIEROOTPORTASPM00 + SB_ONEOF_PCIEROOTPORTL1S00 + SB_ONEOF_PCIEROOTPORTURE00 + SB_ONEOF_PCIEROOTPORTFEE00 + SB_ONEOF_PCIEROOTPORTNFE00 + SB_ONEOF_PCIEROOTPORTCEE00 + SB_ONEOF_PCIEROOTPORTCTD00 + SB_ONEOF_PCIEROOTPORTSFE00 + SB_ONEOF_PCIEROOTPORTSNE00 + SB_ONEOF_PCIEROOTPORTSCE00 + SB_ONEOF_PCIEROOTPORTPMCE00 + SB_ONEOF_PCIEROOTPORTHPE00 + SB_ONEOF_PCIEROOTPORTSPEED00 + SB_ONEOF_PCIEROOTPORTDNCD00 + SB_ONEOF_EXTRABUSRSVD00 + SB_ONEOF_PCIEMEMRSVD00 + SB_ONEOF_PCIEMEMRSVDALIG00 + SB_ONEOF_PCIEPFMEMRSVD00 + SB_ONEOF_PCIEPFMEMRSVDALIG00 + SB_ONEOF_PCIEIORSVD00 + SB_ONEOF_PCIELTRENABLE00 + SB_ONEOF_PCIELTRCONFIGLOCK00 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE00 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER00 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE00 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE00 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER00 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE00 + SB_ONEOF_PCIEROOTPORTEN01 + SB_ONEOF_PCIEROOTPORTASPM01 + SB_ONEOF_PCIEROOTPORTL1S01 + SB_ONEOF_PCIEROOTPORTURE01 + SB_ONEOF_PCIEROOTPORTFEE01 + SB_ONEOF_PCIEROOTPORTNFE01 + SB_ONEOF_PCIEROOTPORTCEE01 + SB_ONEOF_PCIEROOTPORTCTD01 + SB_ONEOF_PCIEROOTPORTSFE01 + SB_ONEOF_PCIEROOTPORTSNE01 + SB_ONEOF_PCIEROOTPORTSCE01 + SB_ONEOF_PCIEROOTPORTPMCE01 + SB_ONEOF_PCIEROOTPORTHPE01 + SB_ONEOF_PCIEROOTPORTSPEED01 + SB_ONEOF_PCIEROOTPORTDNCD01 + SB_ONEOF_EXTRABUSRSVD01 + SB_ONEOF_PCIEMEMRSVD01 + SB_ONEOF_PCIEMEMRSVDALIG01 + SB_ONEOF_PCIEPFMEMRSVD01 + SB_ONEOF_PCIEPFMEMRSVDALIG01 + SB_ONEOF_PCIEIORSVD01 + SB_ONEOF_PCIELTRENABLE01 + SB_ONEOF_PCIELTRCONFIGLOCK01 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE01 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER01 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE01 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE01 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER01 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE01 + SB_ONEOF_PCIEROOTPORTEN02 + SB_ONEOF_PCIEROOTPORTASPM02 + SB_ONEOF_PCIEROOTPORTL1S02 + SB_ONEOF_PCIEROOTPORTURE02 + SB_ONEOF_PCIEROOTPORTFEE02 + SB_ONEOF_PCIEROOTPORTNFE02 + SB_ONEOF_PCIEROOTPORTCEE02 + SB_ONEOF_PCIEROOTPORTCTD02 + SB_ONEOF_PCIEROOTPORTSFE02 + SB_ONEOF_PCIEROOTPORTSNE02 + SB_ONEOF_PCIEROOTPORTSCE02 + SB_ONEOF_PCIEROOTPORTPMCE02 + SB_ONEOF_PCIEROOTPORTHPE02 + SB_ONEOF_PCIEROOTPORTSPEED02 + SB_ONEOF_PCIEROOTPORTDNCD02 + SB_ONEOF_EXTRABUSRSVD02 + SB_ONEOF_PCIEMEMRSVD02 + SB_ONEOF_PCIEMEMRSVDALIG02 + SB_ONEOF_PCIEPFMEMRSVD02 + SB_ONEOF_PCIEPFMEMRSVDALIG02 + SB_ONEOF_PCIEIORSVD02 + SB_ONEOF_PCIELTRENABLE02 + SB_ONEOF_PCIELTRCONFIGLOCK02 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE02 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER02 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE02 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE02 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER02 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE02 + SB_ONEOF_PCIEROOTPORTEN03 + SB_ONEOF_PCIEROOTPORTASPM03 + SB_ONEOF_PCIEROOTPORTL1S03 + SB_ONEOF_PCIEROOTPORTURE03 + SB_ONEOF_PCIEROOTPORTFEE03 + SB_ONEOF_PCIEROOTPORTNFE03 + SB_ONEOF_PCIEROOTPORTCEE03 + SB_ONEOF_PCIEROOTPORTCTD03 + SB_ONEOF_PCIEROOTPORTSFE03 + SB_ONEOF_PCIEROOTPORTSNE03 + SB_ONEOF_PCIEROOTPORTSCE03 + SB_ONEOF_PCIEROOTPORTPMCE03 + SB_ONEOF_PCIEROOTPORTHPE03 + SB_ONEOF_PCIEROOTPORTSPEED03 + SB_ONEOF_PCIEROOTPORTDNCD03 + SB_ONEOF_EXTRABUSRSVD03 + SB_ONEOF_PCIEMEMRSVD03 + SB_ONEOF_PCIEMEMRSVDALIG03 + SB_ONEOF_PCIEPFMEMRSVD03 + SB_ONEOF_PCIEPFMEMRSVDALIG03 + SB_ONEOF_PCIEIORSVD03 + SB_ONEOF_PCIELTRENABLE03 + SB_ONEOF_PCIELTRCONFIGLOCK03 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE03 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER03 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE03 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE03 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER03 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE03 + SB_ONEOF_PCIEROOTPORTEN04 + SB_ONEOF_PCIEROOTPORTASPM04 + SB_ONEOF_PCIEROOTPORTL1S04 + SB_ONEOF_PCIEROOTPORTURE04 + SB_ONEOF_PCIEROOTPORTFEE04 + SB_ONEOF_PCIEROOTPORTNFE04 + SB_ONEOF_PCIEROOTPORTCEE04 + SB_ONEOF_PCIEROOTPORTCTD04 + SB_ONEOF_PCIEROOTPORTSFE04 + SB_ONEOF_PCIEROOTPORTSNE04 + SB_ONEOF_PCIEROOTPORTSCE04 + SB_ONEOF_PCIEROOTPORTPMCE04 + SB_ONEOF_PCIEROOTPORTHPE04 + SB_ONEOF_PCIEROOTPORTSPEED04 + SB_ONEOF_PCIEROOTPORTDNCD04 + SB_ONEOF_EXTRABUSRSVD04 + SB_ONEOF_PCIEMEMRSVD04 + SB_ONEOF_PCIEMEMRSVDALIG04 + SB_ONEOF_PCIEPFMEMRSVD04 + SB_ONEOF_PCIEPFMEMRSVDALIG04 + SB_ONEOF_PCIEIORSVD04 + SB_ONEOF_PCIELTRENABLE04 + SB_ONEOF_PCIELTRCONFIGLOCK04 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE04 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER04 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE04 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE04 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER04 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE04 + SB_ONEOF_PCIEROOTPORTEN05 + SB_ONEOF_PCIEROOTPORTASPM05 + SB_ONEOF_PCIEROOTPORTL1S05 + SB_ONEOF_PCIEROOTPORTURE05 + SB_ONEOF_PCIEROOTPORTFEE05 + SB_ONEOF_PCIEROOTPORTNFE05 + SB_ONEOF_PCIEROOTPORTCEE05 + SB_ONEOF_PCIEROOTPORTCTD05 + SB_ONEOF_PCIEROOTPORTSFE05 + SB_ONEOF_PCIEROOTPORTSNE05 + SB_ONEOF_PCIEROOTPORTSCE05 + SB_ONEOF_PCIEROOTPORTPMCE05 + SB_ONEOF_PCIEROOTPORTHPE05 + SB_ONEOF_PCIEROOTPORTSPEED05 + SB_ONEOF_PCIEROOTPORTDNCD05 + SB_ONEOF_EXTRABUSRSVD05 + SB_ONEOF_PCIEMEMRSVD05 + SB_ONEOF_PCIEMEMRSVDALIG05 + SB_ONEOF_PCIEPFMEMRSVD05 + SB_ONEOF_PCIEPFMEMRSVDALIG05 + SB_ONEOF_PCIEIORSVD05 + SB_ONEOF_PCIELTRENABLE05 + SB_ONEOF_PCIELTRCONFIGLOCK05 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE05 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER05 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE05 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE05 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER05 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE05 + SB_ONEOF_PCIEROOTPORTEN06 + SB_ONEOF_PCIEROOTPORTASPM06 + SB_ONEOF_PCIEROOTPORTL1S06 + SB_ONEOF_PCIEROOTPORTURE06 + SB_ONEOF_PCIEROOTPORTFEE06 + SB_ONEOF_PCIEROOTPORTNFE06 + SB_ONEOF_PCIEROOTPORTCEE06 + SB_ONEOF_PCIEROOTPORTCTD06 + SB_ONEOF_PCIEROOTPORTSFE06 + SB_ONEOF_PCIEROOTPORTSNE06 + SB_ONEOF_PCIEROOTPORTSCE06 + SB_ONEOF_PCIEROOTPORTPMCE06 + SB_ONEOF_PCIEROOTPORTHPE06 + SB_ONEOF_PCIEROOTPORTSPEED06 + SB_ONEOF_PCIEROOTPORTDNCD06 + SB_ONEOF_EXTRABUSRSVD06 + SB_ONEOF_PCIEMEMRSVD06 + SB_ONEOF_PCIEMEMRSVDALIG06 + SB_ONEOF_PCIEPFMEMRSVD06 + SB_ONEOF_PCIEPFMEMRSVDALIG06 + SB_ONEOF_PCIEIORSVD06 + SB_ONEOF_PCIELTRENABLE06 + SB_ONEOF_PCIELTRCONFIGLOCK06 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE06 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER06 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE06 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE06 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER06 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE06 + SB_ONEOF_PCIEROOTPORTEN07 + SB_ONEOF_PCIEROOTPORTASPM07 + SB_ONEOF_PCIEROOTPORTL1S07 + SB_ONEOF_PCIEROOTPORTURE07 + SB_ONEOF_PCIEROOTPORTFEE07 + SB_ONEOF_PCIEROOTPORTNFE07 + SB_ONEOF_PCIEROOTPORTCEE07 + SB_ONEOF_PCIEROOTPORTCTD07 + SB_ONEOF_PCIEROOTPORTSFE07 + SB_ONEOF_PCIEROOTPORTSNE07 + SB_ONEOF_PCIEROOTPORTSCE07 + SB_ONEOF_PCIEROOTPORTPMCE07 + SB_ONEOF_PCIEROOTPORTHPE07 + SB_ONEOF_PCIEROOTPORTSPEED07 + SB_ONEOF_PCIEROOTPORTDNCD07 + SB_ONEOF_EXTRABUSRSVD07 + SB_ONEOF_PCIEMEMRSVD07 + SB_ONEOF_PCIEMEMRSVDALIG07 + SB_ONEOF_PCIEPFMEMRSVD07 + SB_ONEOF_PCIEPFMEMRSVDALIG07 + SB_ONEOF_PCIEIORSVD07 + SB_ONEOF_PCIELTRENABLE07 + SB_ONEOF_PCIELTRCONFIGLOCK07 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE07 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER07 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE07 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE07 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER07 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE07 + SB_ONEOF_AUTOTHERMALREPORT + SB_ONEOF_CRITICALTHERMALTRIPPOINT + SB_ONEOF_AC0TRIPPOINT + SB_ONEOF_AC0FANSPEED + SB_ONEOF_AC1TRIPPOINT + SB_ONEOF_AC1FANSPEED + SB_ONEOF_PASSIVETHERMALTRIPPOINT + SB_ONEOF_PASSIVETC1VALUE + SB_ONEOF_PASSIVETC2VALUE + SB_ONEOF_PASSIVETSPVALUE +#if defined iME_SUPPORT && iME_SUPPORT + SB_ONEOF_TRENABLED + SB_ONEOF_SMBUSECMSGLEN + SB_ONEOF_SMBUSECMSGPEC + SB_ONEOF_TSONDIMM1 + SB_ONEOF_TSONDIMM2 + SB_ONEOF_TSONDIMM3 + SB_ONEOF_TSONDIMM4 +#endif + SB_ONEOF_THERMALDEVICEENABLE + SB_ONEOF_PCHCROSSTHROTTLING + SB_ONEOF_PCHTEMPREADENABLE + SB_ONEOF_CPUENERGYREADENABLE + SB_ONEOF_CPUTEMPREADENABLE + SB_ONEOF_ALERTENABLELOCK + SB_ONEOF_PCHALERT + SB_ONEOF_DIMMALERT + SB_ONEOF_PCHHOTLEVEL + SB_ONEOF_PCHSATA + SB_ONEOF_SATAINTERFACEMODE + SB_ONEOF_ULTSATAINTERFACEMODE + SB_ONEOF_SATATESTMODE +#if SataDriver_SUPPORT + SB_ONEOF_SATARAIDROM +#endif + SB_ONEOF_SALPSUPPORT + SB_ONEOF_SATACONTROLLERSPEED + SB_ONEOF_SATAALTERNATEID + SB_ONEOF_SATAPORT0 + SB_ONEOF_SATAHOTPLUG0 + SB_ONEOF_SATAMECHANICALSW0 + SB_ONEOF_EXTERNALSATA0 + SB_ONEOF_SOLIDSTATEDRIVE0 + SB_ONEOF_SATASPINUP0 + SB_ONEOF_SATADEVSLP0 + SB_ONEOF_SATAENABLEDITOCONFIGP0 + SB_ONEOF_SATADITOVALP0 + SB_ONEOF_SATADMVALP0 + SB_ONEOF_SATAPORT1 + SB_ONEOF_SATAHOTPLUG1 + SB_ONEOF_SATAMECHANICALSW1 + SB_ONEOF_EXTERNALSATA1 + SB_ONEOF_SOLIDSTATEDRIVE1 + SB_ONEOF_SATASPINUP1 + SB_ONEOF_SATADEVSLP1 + SB_ONEOF_SATAENABLEDITOCONFIGP1 + SB_ONEOF_SATADITOVALP1 + SB_ONEOF_SATADMVALP1 + SB_ONEOF_SATAPORT2 + SB_ONEOF_SATAHOTPLUG2 + SB_ONEOF_SATAMECHANICALSW2 + SB_ONEOF_EXTERNALSATA2 + SB_ONEOF_SOLIDSTATEDRIVE2 + SB_ONEOF_SATASPINUP2 + SB_ONEOF_SATADEVSLP2 + SB_ONEOF_SATAENABLEDITOCONFIGP2 + SB_ONEOF_SATADITOVALP2 + SB_ONEOF_SATADMVALP2 + SB_ONEOF_SATAPORT3 + SB_ONEOF_SATAHOTPLUG3 + SB_ONEOF_SATAMECHANICALSW3 + SB_ONEOF_EXTERNALSATA3 + SB_ONEOF_SOLIDSTATEDRIVE3 + SB_ONEOF_SATASPINUP3 + SB_ONEOF_SATADEVSLP3 + SB_ONEOF_SATAENABLEDITOCONFIGP3 + SB_ONEOF_SATADITOVALP3 + SB_ONEOF_SATADMVALP3 + SB_ONEOF_SATAPORT4 + SB_ONEOF_SATAHOTPLUG4 + SB_ONEOF_SATAMECHANICALSW4 + SB_ONEOF_EXTERNALSATA4 + SB_ONEOF_SOLIDSTATEDRIVE4 + SB_ONEOF_SATASPINUP4 + SB_ONEOF_SATAPORT5 + SB_ONEOF_SATAHOTPLUG5 + SB_ONEOF_SATAMECHANICALSW5 + SB_ONEOF_EXTERNALSATA5 + SB_ONEOF_SOLIDSTATEDRIVE5 + SB_ONEOF_SATASPINUP5 + SB_ONEOF_SATARAIDR0 + SB_ONEOF_SATARAIDR1 + SB_ONEOF_SATARAIDR10 + SB_ONEOF_SATARAIDR5 + SB_ONEOF_SATARAIDIRRT + SB_ONEOF_SATARAIDOUB + SB_ONEOF_SATAHDDLK + SB_ONEOF_SATALEDL + SB_ONEOF_SATARAIDIOOE + SB_ONEOF_SMARTSTORAGE + SB_ONEOF_OROMUIDELAY + // PchLp LPSS + SB_ONEOF_LPSSDMAENABLE + SB_ONEOF_LPSSI2C0ENABLE + SB_ONEOF_LPSSI2C1ENABLE + SB_ONEOF_LPSSSPI0ENABLE + SB_ONEOF_LPSSSPI1ENABLE + SB_ONEOF_LPSSUART0ENABLE + SB_ONEOF_LPSSUART1ENABLE + SB_ONEOF_LPSSSDIOENABLE + SB_ONEOF_LPSSMODE + SB_ONEOF_LPSSINTMODE + SB_ONEOF_LPSSI2C0VOLSELECT + SB_ONEOF_LPSSI2C1VOLSELECT + SB_ONEOF_SENSORHUB + SB_ONEOF_TPD4 + SB_ONEOF_ATMELTPL + SB_ONEOF_ELANTPL + SB_ONEOF_ELANTPD + SB_ONEOF_SYNATPD + SB_ONEOF_NTRITPL + SB_ONEOF_EETITPL + SB_ONEOF_ALPSTPD + SB_ONEOF_CYPRTPD + SB_ONEOF_BLUETOOTH0 + SB_ONEOF_BLUETOOTH1 + SB_ONEOF_I2C0SSH + SB_ONEOF_I2C0SSL + SB_ONEOF_I2C0SSD + SB_ONEOF_I2C0FMH + SB_ONEOF_I2C0FML + SB_ONEOF_I2C0FMD + SB_ONEOF_I2C0FPH + SB_ONEOF_I2C0FPL + SB_ONEOF_I2C0FPD + SB_ONEOF_I2C0M0C0 + SB_ONEOF_I2C0M1C0 + SB_ONEOF_I2C0M2C0 + SB_ONEOF_I2C1SSH + SB_ONEOF_I2C1SSL + SB_ONEOF_I2C1SSD + SB_ONEOF_I2C1FMH + SB_ONEOF_I2C1FML + SB_ONEOF_I2C1FMD + SB_ONEOF_I2C1FPH + SB_ONEOF_I2C1FPL + SB_ONEOF_I2C1FPD + SB_ONEOF_I2C1M0C1 + SB_ONEOF_I2C1M1C1 + SB_ONEOF_I2C1M2C1 + SB_ONEOF_SPI0M0C2 + SB_ONEOF_SPI0M1C2 + SB_ONEOF_SPI1M0C3 + SB_ONEOF_SPI1M1C3 + SB_ONEOF_UAR0M0C4 + SB_ONEOF_UAR0M1C4 + SB_ONEOF_UAR1M0C5 + SB_ONEOF_UAR1M1C5 + // PchLp Audio DSP + SB_ONEOF_ADSPENABLE + SB_ONEOF_ADSPD3PG + SB_ONEOF_ADSPCODECSELECT + SB_ONEOF_ADSPBLUETOOTH + SB_ONEOF_ADSPMODE + SB_ONEOF_NFCE + +#endif // CONTROLS_WITH_DEFAULTS +//--------------------------------------------------------------------------- + + +//---------------------------------------------------------------------------- +// CHIPSET - South Bridge Form +//---------------------------------------------------------------------------- + +#ifdef CHIPSET_FORM_SET + #ifndef SUPPRESS_GRAYOUT_ENDIF //old Core + #define SUPPRESS_GRAYOUT_ENDIF endif; + #endif + + #ifdef FORM_SET_VARSTORE + varstore SETUP_PLATFORM_DATA, + key = AUTO_ID(PLATFORM_FEATURES_ID), + name = SetupPlatformData, + guid = SETUP_GUID; + #endif + + #ifdef FORM_SET_VARSTORE + varstore SB_PLATFORM_DATA, + key = AUTO_ID(SB_PLATFORM_DATA_ID), + name = SbPlatformData, + guid = SETUP_GUID; + #endif + + #ifdef FORM_SET_ITEM + // Define controls to be added to the main page of the formset + #endif + + #ifdef FORM_SET_GOTO + // Define goto commands for the forms defined in this file + goto SB_FORM_ID, + prompt = STRING_TOKEN (STR_SB_FORM), + help = STRING_TOKEN (STR_SB_FORM_HELP); + #endif + + #ifdef FORM_SET_FORM + + // Define forms + #ifndef SB_FORM_MAIN + #define SB_FORM_MAIN + + form formid = AUTO_ID(SB_FORM_ID), + title = STRING_TOKEN (STR_SB_FORM); + + text + help = STRING_TOKEN (STR_PCH_RC_VER_HELP), + text = STRING_TOKEN (STR_PCH_RC_VER_NAME), + text = STRING_TOKEN (STR_PCH_RC_VER_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN (STR_PCH_SKU_HELP), + text = STRING_TOKEN (STR_PCH_SKU_NAME), + text = STRING_TOKEN (STR_PCH_SKU_VALUE), + flags = 0, key = 0; + + text + help = STRING_TOKEN (STR_PCH_REVID_HELP), + text = STRING_TOKEN (STR_PCH_REVID_NAME), + text = STRING_TOKEN (STR_PCH_REVID_VALUE), + flags = 0, key = 0; + + SEPARATOR + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + goto PCIE_DEVICE_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIE_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIE_OPTIONS_FORM_HELP); + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + goto USB_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_USB_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_USB_OPTIONS_FORM_HELP); + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + goto PCH_AZALIA_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCH_AZALIA_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCH_AZALIA_OPTIONS_FORM_HELP); + endif; + +#if !defined HIDE_BIOS_SECURITY_PAGE || HIDE_BIOS_SECURITY_PAGE == 0 + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + goto PCH_BIOS_SECURITY_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCH_BIOS_SECURITY_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCH_BIOS_SECURITY_OPTIONS_FORM_HELP); + endif; +#endif + +#if defined(SERIAL_IO_SUPPORT) && (SERIAL_IO_SUPPORT == 1) + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + goto PCH_LPSS_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_LPSS_CONFIGURATION_TITLE), + help = STRING_TOKEN (STR_LPSS_CONFIGURATION_HELP); + endif; +#endif +#if defined(ADSP_SUPPORT) && (ADSP_SUPPORT == 1) + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + goto PCH_ADSP_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_ADSP_CONFIGURATION_TITLE), + help = STRING_TOKEN (STR_ADSP_CONFIGURATION_HELP); + endif; +#endif + + SEPARATOR + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_ECTG + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_PCHLAN + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.PchLan == 0; + SB_ONEOF_PCHWAKEONLAN +#if defined (PCH_SKU) && (PCH_SKU == 1) + SB_ONEOF_PCHSLPLANLOW +#endif + SUPPRESS_GRAYOUT_ENDIF + + // [EIP82149]> + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif PlatformInfo_PlatformFlavor != FlavorMobile OR + ideqval SB_PLATFORM_DATA.HideDeepSx == 1; + SB_ONEOF_BOARDCAPABILITY + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif PlatformInfo_PlatformFlavor != FlavorMobile OR + ideqval SB_PLATFORM_DATA.HideDeepSx == 1 OR + ideqval SETUP_DATA.BoardCapability == 0; + SB_ONEOF_DEEPSXBATTMODE + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif PlatformInfo_PlatformFlavor == FlavorMobile OR + ideqval SB_PLATFORM_DATA.HideDeepSx == 1; + SB_ONEOF_DEEPSXMODE + SUPPRESS_GRAYOUT_ENDIF + // <[EIP82149] + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_GP27WAKE + SB_ONEOF_PCIEWAKE + endif; + + // EC turbo control test mode + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif PlatformInfo_PlatformFlavor != FlavorMobile OR + ideqval SETUP_DATA.TurboMode == 0; + SB_ONEOF_ECTURBOCONTROLMODE + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.ECTurboControlMode == 0; + SB_ONEOF_ACBRICKCAPACITY + SB_ONEOF_ECPOLLINGPERIOD + SB_ONEOF_ECGUARDBANDVALUE + SB_ONEOF_ECALGORITHMSEL + SB_ONEOF_ECHYBRIDPOWERBOOST + suppressif ideqval SETUP_DATA.ECHybridPowerBoost == 0; + SB_ONEOF_ECHYBRIDCURRENT + endif; + SUPPRESS_GRAYOUT_ENDIF // suppressif ideqval SETUP_DATA.ECTurboControlMode == 0; + +// EC turbo control test mode *** end + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_PCHDISPLAY + SB_ONEOF_PCHPCICLOCKRUN + SB_ONEOF_IRQMODE + SB_ONEOF_PCHENABLECRID + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_PCHCROSSTHROTTLING + endif; + endif; + +//#if HPET_SUPPORT +// +// SEPARATOR +// +// SUBTITLE(STRING_TOKEN (STR_HPET_SUBTITLE)) +// +// grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; +// SB_ONEOF_HPET // Force HPET enabled for MRC initialization. +// endif; +//#endif + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_SLPS4ASSW + SB_ONEOF_LASTSTATE + SB_ONEOF_PORT80 + endif; + + SB_ONEOF_NFCE + + endform; // End of STR_SB_FORM + #endif // End of SB_FORM_MAIN + #endif + +//---------------------------------------------------------------------------- +// CHIPSET - SB USB Form +//---------------------------------------------------------------------------- + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_USB_OPTIONS + #define SB_FORM_USB_OPTIONS + + form formid = AUTO_ID(USB_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_USB_OPTIONS_FORM_TITLE); + + SUBTITLE(STRING_TOKEN (STR_USB_OPTIONS_FORM_TITLE)) + + SEPARATOR + + SB_ONEOF_PCHUSBPRECONDITION + SB_ONEOF_PCHUSB30MODE + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_PCHUSB30IDLEL1 + endif; + + SB_ONEOF_PCHUSB30BTCG + + suppressif NOT ideqval SETUP_DATA.PchUsb30Mode == 4; + SEPARATOR + + SB_ONEOF_PCHUSB30PREBOOTSUPPORT + + SEPARATOR + + SB_ONEOF_PCHUSB20PINROUTE + + suppressif NOT ideqval SETUP_DATA.PchUsb20PinRoute == 0; + SB_ONEOF_USB20PERPINROUTE00 + SB_ONEOF_USB20PERPINROUTE01 + SB_ONEOF_USB20PERPINROUTE02 + SB_ONEOF_USB20PERPINROUTE03 + SB_ONEOF_USB20PERPINROUTE04 + SB_ONEOF_USB20PERPINROUTE05 + SB_ONEOF_USB20PERPINROUTE06 + SB_ONEOF_USB20PERPINROUTE07 + SB_ONEOF_USB20PERPINROUTE08 + SB_ONEOF_USB20PERPINROUTE09 + SB_ONEOF_USB20PERPINROUTE10 + SB_ONEOF_USB20PERPINROUTE11 + SB_ONEOF_USB20PERPINROUTE12 + SB_ONEOF_USB20PERPINROUTE13 + endif; + + SEPARATOR + + SB_ONEOF_PCHUSB30PINENABLE + + suppressif NOT ideqval SETUP_DATA.PchUsb30PinEnable == 0; + SB_ONEOF_USB30PERPINENABLE1 + SB_ONEOF_USB30PERPINENABLE2 + SB_ONEOF_USB30PERPINENABLE3 + SB_ONEOF_USB30PERPINENABLE4 + SB_ONEOF_USB30PERPINENABLE5 + SB_ONEOF_USB30PERPINENABLE6 + endif; + endif; + +// suppressif ideqval SETUP_DATA.PchUsb30Mode == 0 OR +// ideqval SETUP_DATA.PchUsb30PBootMode == 0; + +// SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_00 +// SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_01 +// SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_02 +// SB_ONEOF_PCHUSB30HSPORTSWITCHABLE_03 +// SB_ONEOF_XHCISTREAMS + +// endif; + + suppressif NOT ideqval SETUP_DATA.PchUsb30Mode == 0; + SEPARATOR + + SB_ONEOF_PCHUSB20OFF0 + suppressif ideqval SB_PLATFORM_DATA.LPTType == 1; + SB_ONEOF_PCHUSB20OFF1 + endif; + endif; + + SEPARATOR + // + // Usb ports per-port disable control enable + // + SB_ONEOF_PCHUSBPERPORTCTL + + suppressif ideqval SETUP_DATA.PchUsbPerPortCtl == 0x0; + SB_ONEOF_PCHUSBPORT00 + SB_ONEOF_PCHUSBPORT01 + SB_ONEOF_PCHUSBPORT02 + SB_ONEOF_PCHUSBPORT03 + SB_ONEOF_PCHUSBPORT04 + SB_ONEOF_PCHUSBPORT05 + SB_ONEOF_PCHUSBPORT06 + SB_ONEOF_PCHUSBPORT07 + suppressif ideqval SB_PLATFORM_DATA.LPTType == 1; + SB_ONEOF_PCHUSBPORT08 + SB_ONEOF_PCHUSBPORT09 + SB_ONEOF_PCHUSBPORT10 + SB_ONEOF_PCHUSBPORT11 + SB_ONEOF_PCHUSBPORT12 + SB_ONEOF_PCHUSBPORT13 + endif; + +// SEPARATOR + +// SB_ONEOF_PCHUSB30PORT00 +// SB_ONEOF_PCHUSB30PORT01 +// SB_ONEOF_PCHUSB30PORT02 +// SB_ONEOF_PCHUSB30PORT03 +// SB_ONEOF_PCHUSB30PORT04 +// SB_ONEOF_PCHUSB30PORT05 + endif; + +#if EHCI_CON_DISCON_WAKE_UP_SUPPORT + SEPARATOR + + SB_ONEOF_EHCICONDISCONWAKEUP +#endif + + SEPARATOR + +// SB_ONEOF_PCHENABLERMH1 + + endform; // End of USB_OPTIONS_FORM_ID + #endif // End of SB_FORM_USB_OPTIONS + #endif +//---------------------------------------------------------------------------- +// CHIPSET - SB AZALIA Form +//---------------------------------------------------------------------------- + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCH_AZALIA_OPTIONS + #define SB_FORM_PCH_AZALIA_OPTIONS + + form formid = AUTO_ID(PCH_AZALIA_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCH_AZALIA_OPTIONS_FORM_TITLE); + + SUBTITLE(STRING_TOKEN (STR_PCH_AZALIA_OPTIONS_FORM_TITLE)) + + SEPARATOR + suppressif ideqval SETUP_DATA.ADspEnable == 1 AND ideqval SB_PLATFORM_DATA.LPTType == 1; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_PCHAZALIA + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.PchAzalia == 0x0; + SB_ONEOF_AZALIADS + SB_ONEOF_AZALIAPME + SUPPRESS_GRAYOUT_ENDIF // suppressif ideqval SETUP_DATA.PchAzalia == 0x0 + endif; + endform; //End of PCH_AZALIA_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCH_AZALIA_OPTIONS + + #endif +//---------------------------------------------------------------------------- +// CHIPSET - SB BIOS Security Form +//---------------------------------------------------------------------------- + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCH_BIOS_SECURITY_OPTIONS + #define SB_FORM_PCH_BIOS_SECURITY_OPTIONS + + form formid = AUTO_ID(PCH_BIOS_SECURITY_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCH_BIOS_SECURITY_OPTIONS_FORM_TITLE); + + SUBTITLE(STRING_TOKEN (STR_PCH_BIOS_SECURITY_OPTIONS_FORM_TITLE)) + + SEPARATOR + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_SMILOCK +#if defined(PfatServices_SUPPORT) && (PfatServices_SUPPORT == 1) + suppressif ideqval SETUP_DATA.Pfatstate == 1; + SB_ONEOF_BIOSLOCK + endif; +#else + SB_ONEOF_BIOSLOCK +#endif + SB_ONEOF_GPIOLOCK + SB_ONEOF_BIOSINTERFACELOCK + SB_ONEOF_RTCLOCK + endif; + + endform; //End of PCH_BIOS_SECURITY_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCH_BIOS_SECURITY_OPTIONS + + #endif +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Form +//---------------------------------------------------------------------------- + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIE_OPTIONS + #define SB_FORM_PCIE_OPTIONS + + form formid = AUTO_ID(PCIE_DEVICE_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIE_OPTIONS_FORM_TITLE); + + SUBTITLE(STRING_TOKEN (STR_PCIE_OPTIONS_FORM_TITLE)) + + SEPARATOR + + SB_ONEOF_PCIECLOCKGATING + SB_ONEOF_PCHDMIASPM + SB_ONEOF_PCHDMIEXTSYNC + SB_ONEOF_PCIEUSBWA + SB_ONEOF_ROOTPORTFUNCTIONSWAPPING + + grayoutif ideqval SB_PLATFORM_DATA.PcieSBDE == 0; + SB_ONEOF_PCIEROOTPORTSBDE + endif; + + suppressif ideqval SETUP_DATA.PcieRootPortSBDE == 0 OR ideqval SB_PLATFORM_DATA.PcieSBDE == 0; + SB_ONEOF_PCIESBDEPORT + endif; + + SEPARATOR + +#if defined RC_PORT_0 && RC_PORT_0 + suppressif ideqval SB_PLATFORM_DATA.GbePciePortNum == 0; + goto PCH_PCIERP1_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIERP1_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIERP1_OPTIONS_FORM_HELP); + endif; + + suppressif NOT ideqval SB_PLATFORM_DATA.GbePciePortNum == 00; + SB_ONEOF_LANRP1 + endif; + +#if defined RC_PORT_1 && RC_PORT_1 + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR ideqval SB_PLATFORM_DATA.GbePciePortNum == 1; + goto PCH_PCIERP2_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIERP2_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIERP2_OPTIONS_FORM_HELP); + endif; + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR NOT ideqval SB_PLATFORM_DATA.GbePciePortNum == 1; + SB_ONEOF_LANRP2 + endif; +#endif + +#if defined RC_PORT_2 && RC_PORT_2 + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR ideqval SB_PLATFORM_DATA.GbePciePortNum == 2; + goto PCH_PCIERP3_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIERP3_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIERP3_OPTIONS_FORM_HELP); + endif; + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR NOT ideqval SB_PLATFORM_DATA.GbePciePortNum == 2; + SB_ONEOF_LANRP3 + endif; +#endif + +#if defined RC_PORT_3 && RC_PORT_3 + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR ideqval SB_PLATFORM_DATA.GbePciePortNum == 3; + goto PCH_PCIERP4_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIERP4_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIERP4_OPTIONS_FORM_HELP); + endif; + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR NOT ideqval SB_PLATFORM_DATA.GbePciePortNum == 3; + SB_ONEOF_LANRP4 + endif; +#endif + +#if defined RC_PORT_4 && RC_PORT_4 + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR ideqval SB_PLATFORM_DATA.GbePciePortNum == 4; + goto PCH_PCIERP5_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIERP5_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIERP5_OPTIONS_FORM_HELP); + endif; + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR NOT ideqval SB_PLATFORM_DATA.GbePciePortNum == 4; + SB_ONEOF_LANRP5 + endif; +#endif + +#if defined RC_PORT_5 && RC_PORT_5 + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR ideqval SB_PLATFORM_DATA.GbePciePortNum == 5; + goto PCH_PCIERP6_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIERP6_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIERP6_OPTIONS_FORM_HELP); + endif; + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR NOT ideqval SB_PLATFORM_DATA.GbePciePortNum == 5; + SB_ONEOF_LANRP6 + endif; +#endif + +#if defined RC_PORT_6 && RC_PORT_6 + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR ideqval SB_PLATFORM_DATA.GbePciePortNum == 6 OR ideqval SB_PLATFORM_DATA.LPTType == 1; + goto PCH_PCIERP7_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIERP7_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIERP7_OPTIONS_FORM_HELP); + endif; + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR NOT ideqval SB_PLATFORM_DATA.GbePciePortNum == 6; + SB_ONEOF_LANRP7 + endif; +#endif + +#if defined RC_PORT_7 && RC_PORT_7 + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR ideqval SB_PLATFORM_DATA.GbePciePortNum == 7 OR ideqval SB_PLATFORM_DATA.LPTType == 1; + goto PCH_PCIERP8_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_PCIERP8_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_PCIERP8_OPTIONS_FORM_HELP); + endif; + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0 OR NOT ideqval SB_PLATFORM_DATA.GbePciePortNum == 7; + SB_ONEOF_LANRP8 + endif; +#endif +#endif // End of RC_PORT_0 + + endform; //End of PCIE_DEVICE_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIE_OPTIONS + + #endif + +#if defined RC_PORT_0 && RC_PORT_0 +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Root Port#1 Form +//---------------------------------------------------------------------------- + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIERP1_OPTIONS + #define SB_FORM_PCIERP1_OPTIONS + + form formid = AUTO_ID(PCH_PCIERP1_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIERP1_OPTIONS_FORM_TITLE); + + SB_ONEOF_PCIEROOTPORTEN00 + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_0] == 0x0; + SB_ONEOF_PCIEROOTPORTASPM00 + SB_ONEOF_PCIEROOTPORTL1S00 + SB_ONEOF_PCIEROOTPORTURE00 + SB_ONEOF_PCIEROOTPORTFEE00 + SB_ONEOF_PCIEROOTPORTNFE00 + SB_ONEOF_PCIEROOTPORTCEE00 + SB_ONEOF_PCIEROOTPORTCTD00 + SB_ONEOF_PCIEROOTPORTSFE00 + SB_ONEOF_PCIEROOTPORTSNE00 + SB_ONEOF_PCIEROOTPORTSCE00 + SB_ONEOF_PCIEROOTPORTPMCE00 + SB_ONEOF_PCIEROOTPORTHPE00 + SB_ONEOF_PCIEROOTPORTSPEED00 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 && Thunderbolt_FR_VERSION > 10 + suppressif ideqval SETUP_DATA.TbtHostLocation == 0 OR \ + NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_0] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD00 + endif; + #else + #if !defined TBT_UP_PORT_FUNC || TBT_UP_PORT_FUNC != 0 + suppressif NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_0] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD00 + endif; + #endif + #endif + SB_ONEOF_EXTRABUSRSVD00 + SB_ONEOF_PCIEMEMRSVD00 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 0 + SB_ONEOF_PCIEMEMRSVDALIG00 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 0; + SB_ONEOF_PCIEMEMRSVDALIG00 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEPFMEMRSVD00 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 0 + SB_ONEOF_PCIEPFMEMRSVDALIG00 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 0; + SB_ONEOF_PCIEPFMEMRSVDALIG00 + endif; + #endif + #else + #endif + + SB_ONEOF_PCIEIORSVD00 + SB_ONEOF_PCIELTRENABLE00 + SB_ONEOF_PCIELTRCONFIGLOCK00 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE00 + suppressif NOT ideqval SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_0] == 1; + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER00 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE00 + endif; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE00 + suppressif NOT ideqval SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_0] == 1; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER00 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE00 + endif; + endif; + + endform; //End of PCH_PCIERP1_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIERP1_OPTIONS + + #endif +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Root Port#2 Form +//---------------------------------------------------------------------------- +#if defined RC_PORT_1 && RC_PORT_1 + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIERP2_OPTIONS + #define SB_FORM_PCIERP2_OPTIONS + + form formid = AUTO_ID(PCH_PCIERP2_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIERP2_OPTIONS_FORM_TITLE); + + SB_ONEOF_PCIEROOTPORTEN01 + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_1] == 0x0; + SB_ONEOF_PCIEROOTPORTASPM01 + SB_ONEOF_PCIEROOTPORTL1S01 + SB_ONEOF_PCIEROOTPORTURE01 + SB_ONEOF_PCIEROOTPORTFEE01 + SB_ONEOF_PCIEROOTPORTNFE01 + SB_ONEOF_PCIEROOTPORTCEE01 + SB_ONEOF_PCIEROOTPORTCTD01 + SB_ONEOF_PCIEROOTPORTSFE01 + SB_ONEOF_PCIEROOTPORTSNE01 + SB_ONEOF_PCIEROOTPORTSCE01 + SB_ONEOF_PCIEROOTPORTPMCE01 + SB_ONEOF_PCIEROOTPORTHPE01 + SB_ONEOF_PCIEROOTPORTSPEED01 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 && Thunderbolt_FR_VERSION > 10 + suppressif ideqval SETUP_DATA.TbtHostLocation == 1 OR \ + NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_1] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD01 + endif; + #else + #if !defined TBT_UP_PORT_FUNC || TBT_UP_PORT_FUNC != 1 + suppressif NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_1] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD01 + endif; + #endif + #endif + SB_ONEOF_EXTRABUSRSVD01 + SB_ONEOF_PCIEMEMRSVD01 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 1 + SB_ONEOF_PCIEMEMRSVDALIG01 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 1; + SB_ONEOF_PCIEMEMRSVDALIG01 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEPFMEMRSVD01 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 1 + SB_ONEOF_PCIEPFMEMRSVDALIG01 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 1; + SB_ONEOF_PCIEPFMEMRSVDALIG01 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEIORSVD01 + + SB_ONEOF_PCIELTRENABLE01 + SB_ONEOF_PCIELTRCONFIGLOCK01 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE01 + suppressif NOT ideqval SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_1] == 1; + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER01 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE01 + endif; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE01 + suppressif NOT ideqval SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_1] == 1; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER01 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE01 + endif; + endif; + + endform; //End of PCH_PCIERP2_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIERP2_OPTIONS + + #endif +#endif +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Root Port#3 Form +//---------------------------------------------------------------------------- +#if defined RC_PORT_2 && RC_PORT_2 + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIERP3_OPTIONS + #define SB_FORM_PCIERP3_OPTIONS + + form formid = AUTO_ID(PCH_PCIERP3_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIERP3_OPTIONS_FORM_TITLE); + + SB_ONEOF_PCIEROOTPORTEN02 + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_2] == 0x0; + SB_ONEOF_PCIEROOTPORTASPM02 + SB_ONEOF_PCIEROOTPORTL1S02 + SB_ONEOF_PCIEROOTPORTURE02 + SB_ONEOF_PCIEROOTPORTFEE02 + SB_ONEOF_PCIEROOTPORTNFE02 + SB_ONEOF_PCIEROOTPORTCEE02 + SB_ONEOF_PCIEROOTPORTCTD02 + SB_ONEOF_PCIEROOTPORTSFE02 + SB_ONEOF_PCIEROOTPORTSNE02 + SB_ONEOF_PCIEROOTPORTSCE02 + SB_ONEOF_PCIEROOTPORTPMCE02 + SB_ONEOF_PCIEROOTPORTHPE02 + SB_ONEOF_PCIEROOTPORTSPEED02 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 && Thunderbolt_FR_VERSION > 10 + suppressif ideqval SETUP_DATA.TbtHostLocation == 2 OR \ + NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_2] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD02 + endif; + #else + #if !defined TBT_UP_PORT_FUNC || TBT_UP_PORT_FUNC != 2 + suppressif NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_2] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD02 + endif; + #endif + #endif + SB_ONEOF_EXTRABUSRSVD02 + SB_ONEOF_PCIEMEMRSVD02 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 2 + SB_ONEOF_PCIEMEMRSVDALIG02 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 2; + SB_ONEOF_PCIEMEMRSVDALIG02 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEPFMEMRSVD02 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 2 + SB_ONEOF_PCIEPFMEMRSVDALIG02 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 2; + SB_ONEOF_PCIEPFMEMRSVDALIG02 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEIORSVD02 + + SB_ONEOF_PCIELTRENABLE02 + SB_ONEOF_PCIELTRCONFIGLOCK02 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE02 + suppressif NOT ideqval SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_2] == 1; + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER02 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE02 + endif; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE02 + suppressif NOT ideqval SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_2] == 1; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER02 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE02 + endif; + endif; + + endform; //End of PCH_PCIERP3_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIERP3_OPTIONS + + #endif +#endif +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Root Port#4 Form +//---------------------------------------------------------------------------- +#if defined RC_PORT_3 && RC_PORT_3 + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIERP4_OPTIONS + #define SB_FORM_PCIERP4_OPTIONS + + form formid = AUTO_ID(PCH_PCIERP4_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIERP4_OPTIONS_FORM_TITLE); + + SB_ONEOF_PCIEROOTPORTEN03 + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_3] == 0x0; + SB_ONEOF_PCIEROOTPORTASPM03 + SB_ONEOF_PCIEROOTPORTL1S03 + SB_ONEOF_PCIEROOTPORTURE03 + SB_ONEOF_PCIEROOTPORTFEE03 + SB_ONEOF_PCIEROOTPORTNFE03 + SB_ONEOF_PCIEROOTPORTCEE03 + SB_ONEOF_PCIEROOTPORTCTD03 + SB_ONEOF_PCIEROOTPORTSFE03 + SB_ONEOF_PCIEROOTPORTSNE03 + SB_ONEOF_PCIEROOTPORTSCE03 + SB_ONEOF_PCIEROOTPORTPMCE03 + SB_ONEOF_PCIEROOTPORTHPE03 + SB_ONEOF_PCIEROOTPORTSPEED03 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 && Thunderbolt_FR_VERSION > 10 + suppressif ideqval SETUP_DATA.TbtHostLocation == 3 OR \ + NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_3] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD03 + endif; + #else + #if !defined TBT_UP_PORT_FUNC || TBT_UP_PORT_FUNC != 3 + suppressif NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_3] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD03 + endif; + #endif + #endif + SB_ONEOF_EXTRABUSRSVD03 + SB_ONEOF_PCIEMEMRSVD03 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 3 + SB_ONEOF_PCIEMEMRSVDALIG03 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 3; + SB_ONEOF_PCIEMEMRSVDALIG03 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEPFMEMRSVD03 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 3 + SB_ONEOF_PCIEPFMEMRSVDALIG03 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 3; + SB_ONEOF_PCIEPFMEMRSVDALIG03 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEIORSVD03 + + SB_ONEOF_PCIELTRENABLE03 + SB_ONEOF_PCIELTRCONFIGLOCK03 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE03 + suppressif NOT ideqval SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_3] == 1; + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER03 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE03 + endif; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE03 + suppressif NOT ideqval SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_3] == 1; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER03 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE03 + endif; + endif; + + endform; //End of PCH_PCIERP4_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIERP4_OPTIONS + + #endif +#endif +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Root Port#5 Form +//---------------------------------------------------------------------------- +#if defined RC_PORT_4 && RC_PORT_4 + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIERP5_OPTIONS + #define SB_FORM_PCIERP5_OPTIONS + + form formid = AUTO_ID(PCH_PCIERP5_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIERP5_OPTIONS_FORM_TITLE); + + SB_ONEOF_PCIEROOTPORTEN04 + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_4] == 0x0; + SB_ONEOF_PCIEROOTPORTASPM04 + SB_ONEOF_PCIEROOTPORTL1S04 + SB_ONEOF_PCIEROOTPORTURE04 + SB_ONEOF_PCIEROOTPORTFEE04 + SB_ONEOF_PCIEROOTPORTNFE04 + SB_ONEOF_PCIEROOTPORTCEE04 + SB_ONEOF_PCIEROOTPORTCTD04 + SB_ONEOF_PCIEROOTPORTSFE04 + SB_ONEOF_PCIEROOTPORTSNE04 + SB_ONEOF_PCIEROOTPORTSCE04 + SB_ONEOF_PCIEROOTPORTPMCE04 + SB_ONEOF_PCIEROOTPORTHPE04 + SB_ONEOF_PCIEROOTPORTSPEED04 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 && Thunderbolt_FR_VERSION > 10 + suppressif ideqval SETUP_DATA.TbtHostLocation == 4 OR \ + NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_4] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD04 + endif; + #else + #if !defined TBT_UP_PORT_FUNC || TBT_UP_PORT_FUNC != 4 + suppressif NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_4] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD04 + endif; + #endif + #endif + SB_ONEOF_EXTRABUSRSVD04 + SB_ONEOF_PCIEMEMRSVD04 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 4 + SB_ONEOF_PCIEMEMRSVDALIG04 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 4; + SB_ONEOF_PCIEMEMRSVDALIG04 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEPFMEMRSVD04 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 4 + SB_ONEOF_PCIEPFMEMRSVDALIG04 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 4; + SB_ONEOF_PCIEPFMEMRSVDALIG04 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEIORSVD04 + + SB_ONEOF_PCIELTRENABLE04 + SB_ONEOF_PCIELTRCONFIGLOCK04 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE04 + suppressif NOT ideqval SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_4] == 1; + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER04 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE04 + endif; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE04 + suppressif NOT ideqval SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_4] == 1; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER04 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE04 + endif; + endif; + + endform; //End of PCH_PCIERP5_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIERP5_OPTIONS + + #endif +#endif +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Root Port#6 Form +//---------------------------------------------------------------------------- +#if defined RC_PORT_5 && RC_PORT_5 + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIERP6_OPTIONS + #define SB_FORM_PCIERP6_OPTIONS + + form formid = AUTO_ID(PCH_PCIERP6_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIERP6_OPTIONS_FORM_TITLE); + + SB_ONEOF_PCIEROOTPORTEN05 + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_5] == 0x0; + SB_ONEOF_PCIEROOTPORTASPM05 + SB_ONEOF_PCIEROOTPORTL1S05 + SB_ONEOF_PCIEROOTPORTURE05 + SB_ONEOF_PCIEROOTPORTFEE05 + SB_ONEOF_PCIEROOTPORTNFE05 + SB_ONEOF_PCIEROOTPORTCEE05 + SB_ONEOF_PCIEROOTPORTCTD05 + SB_ONEOF_PCIEROOTPORTSFE05 + SB_ONEOF_PCIEROOTPORTSNE05 + SB_ONEOF_PCIEROOTPORTSCE05 + SB_ONEOF_PCIEROOTPORTPMCE05 + SB_ONEOF_PCIEROOTPORTHPE05 + SB_ONEOF_PCIEROOTPORTSPEED05 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 && Thunderbolt_FR_VERSION > 10 + suppressif ideqval SETUP_DATA.TbtHostLocation == 5 OR \ + NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_5] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD05 + endif; + #else + #if !defined TBT_UP_PORT_FUNC || TBT_UP_PORT_FUNC != 5 + suppressif NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_5] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD05 + endif; + #endif + #endif + SB_ONEOF_EXTRABUSRSVD05 + SB_ONEOF_PCIEMEMRSVD05 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 5 + SB_ONEOF_PCIEMEMRSVDALIG05 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 5; + SB_ONEOF_PCIEMEMRSVDALIG05 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEPFMEMRSVD05 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 5 + SB_ONEOF_PCIEPFMEMRSVDALIG05 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 5; + SB_ONEOF_PCIEPFMEMRSVDALIG05 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEIORSVD05 + + SB_ONEOF_PCIELTRENABLE05 + SB_ONEOF_PCIELTRCONFIGLOCK05 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE05 + suppressif NOT ideqval SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_5] == 1; + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER05 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE05 + endif; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE05 + suppressif NOT ideqval SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_5] == 1; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER05 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE05 + endif; + endif; + + endform; //End of PCH_PCIERP6_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIERP6_OPTIONS + + #endif +#endif +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Root Port#7 Form +//---------------------------------------------------------------------------- +#if defined RC_PORT_6 && RC_PORT_6 + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIERP7_OPTIONS + #define SB_FORM_PCIERP7_OPTIONS + + form formid = AUTO_ID(PCH_PCIERP7_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIERP7_OPTIONS_FORM_TITLE); + + SB_ONEOF_PCIEROOTPORTEN06 + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_6] == 0x0; + SB_ONEOF_PCIEROOTPORTASPM06 + SB_ONEOF_PCIEROOTPORTL1S06 + SB_ONEOF_PCIEROOTPORTURE06 + SB_ONEOF_PCIEROOTPORTFEE06 + SB_ONEOF_PCIEROOTPORTNFE06 + SB_ONEOF_PCIEROOTPORTCEE06 + SB_ONEOF_PCIEROOTPORTCTD06 + SB_ONEOF_PCIEROOTPORTSFE06 + SB_ONEOF_PCIEROOTPORTSNE06 + SB_ONEOF_PCIEROOTPORTSCE06 + SB_ONEOF_PCIEROOTPORTPMCE06 + SB_ONEOF_PCIEROOTPORTHPE06 + SB_ONEOF_PCIEROOTPORTSPEED06 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 && Thunderbolt_FR_VERSION > 10 + suppressif ideqval SETUP_DATA.TbtHostLocation == 6 OR \ + NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_6] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD06 + endif; + #else + #if !defined TBT_UP_PORT_FUNC || TBT_UP_PORT_FUNC != 6 + suppressif NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_6] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD06 + endif; + #endif + #endif + SB_ONEOF_EXTRABUSRSVD06 + SB_ONEOF_PCIEMEMRSVD06 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 6 + SB_ONEOF_PCIEMEMRSVDALIG06 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 6; + SB_ONEOF_PCIEMEMRSVDALIG06 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEPFMEMRSVD06 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 6 + SB_ONEOF_PCIEPFMEMRSVDALIG06 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 6; + SB_ONEOF_PCIEPFMEMRSVDALIG06 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEIORSVD06 + + SB_ONEOF_PCIELTRENABLE06 + SB_ONEOF_PCIELTRCONFIGLOCK06 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE06 + suppressif NOT ideqval SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_6] == 1; + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER06 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE06 + endif; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE06 + suppressif NOT ideqval SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_6] == 1; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER06 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE06 + endif; + endif; + + endform; //End of PCH_PCIERP7_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIERP7_OPTIONS + + #endif +#endif +//---------------------------------------------------------------------------- +// CHIPSET - SB PCI-E Root Port#8 Form +//---------------------------------------------------------------------------- +#if defined RC_PORT_7 && RC_PORT_7 + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCIERP8_OPTIONS + #define SB_FORM_PCIERP8_OPTIONS + + form formid = AUTO_ID(PCH_PCIERP8_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_PCIERP8_OPTIONS_FORM_TITLE); + + SB_ONEOF_PCIEROOTPORTEN07 + + suppressif ideqval SETUP_DATA.PcieRootPortEn[OFFSET_7] == 0x0; + SB_ONEOF_PCIEROOTPORTASPM07 + SB_ONEOF_PCIEROOTPORTL1S07 + SB_ONEOF_PCIEROOTPORTURE07 + SB_ONEOF_PCIEROOTPORTFEE07 + SB_ONEOF_PCIEROOTPORTNFE07 + SB_ONEOF_PCIEROOTPORTCEE07 + SB_ONEOF_PCIEROOTPORTCTD07 + SB_ONEOF_PCIEROOTPORTSFE07 + SB_ONEOF_PCIEROOTPORTSNE07 + SB_ONEOF_PCIEROOTPORTSCE07 + SB_ONEOF_PCIEROOTPORTPMCE07 + SB_ONEOF_PCIEROOTPORTHPE07 + SB_ONEOF_PCIEROOTPORTSPEED07 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 && Thunderbolt_FR_VERSION > 10 + suppressif ideqval SETUP_DATA.TbtHostLocation == 7 OR \ + NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_7] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD07 + endif; + #else + #if !defined TBT_UP_PORT_FUNC || TBT_UP_PORT_FUNC != 7 + suppressif NOT ideqval SETUP_DATA.PcieRootPortSpeed[OFFSET_7] == 0x0; + SB_ONEOF_PCIEROOTPORTDNCD07 + endif; + #endif + #endif + SB_ONEOF_EXTRABUSRSVD07 + SB_ONEOF_PCIEMEMRSVD07 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 7 + SB_ONEOF_PCIEMEMRSVDALIG07 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 7; + SB_ONEOF_PCIEMEMRSVDALIG07 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEPFMEMRSVD07 + #if defined Thunderbolt_SUPPORT && Thunderbolt_SUPPORT == 1 + #if defined Thunderbolt_FR_VERSION && Thunderbolt_FR_VERSION < 11 + #if defined TBT_UP_PORT_FUNC && TBT_UP_PORT_FUNC == 7 + SB_ONEOF_PCIEPFMEMRSVDALIG07 + #endif + #else + suppressif NOT ideqval SETUP_DATA.TbtHostLocation == 7; + SB_ONEOF_PCIEPFMEMRSVDALIG07 + endif; + #endif + #else + #endif + SB_ONEOF_PCIEIORSVD07 + + SB_ONEOF_PCIELTRENABLE07 + SB_ONEOF_PCIELTRCONFIGLOCK07 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMODE07 + suppressif NOT ideqval SETUP_DATA.PcieSnoopLatencyOverrideMode[OFFSET_7] == 1; + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEMULITIPLIER07 + SB_ONEOF_PCIESNOOPLATENCYOVERRIDEVALUE07 + endif; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMODE07 + suppressif NOT ideqval SETUP_DATA.PcieNonSnoopLatencyOverrideMode[OFFSET_7] == 1; + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEMULITIPLIER07 + SB_ONEOF_PCIENONSNOOPLATENCYOVERRIDEVALUE07 + endif; + endif; + + endform; //End of PCH_PCIERP8_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCIERP8_OPTIONS + + #endif +#endif +#endif // End of RC_PORT_0 +//---------------------------------------------------------------------------- +// CHIPSET - SB LPSS CONFIGURATION Form +//---------------------------------------------------------------------------- +#if defined(SERIAL_IO_SUPPORT) && (SERIAL_IO_SUPPORT == 1) + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCH_LPSS_CONFIG_OPTIONS + #define SB_FORM_PCH_LPSS_CONFIG_OPTIONS + + form formid = AUTO_ID(PCH_LPSS_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_LPSS_CONFIGURATION_TITLE); + + SUBTITLE(STRING_TOKEN (STR_LPSS_CONFIGURATION_TITLE)) + + SEPARATOR + + SB_ONEOF_LPSSDMAENABLE + SEPARATOR + suppressif ideqval SETUP_DATA.LpssDmaEnable == 0; + SB_ONEOF_LPSSI2C0ENABLE + suppressif ideqval SETUP_DATA.LpssI2c0Enable == 0; + SB_ONEOF_LPSSI2C0VOLSELECT + SB_ONEOF_SENSORHUB + SB_ONEOF_TPD4 + SEPARATOR + SB_ONEOF_I2C0SSL + SB_ONEOF_I2C0SSH + SB_ONEOF_I2C0SSD + SB_ONEOF_I2C0FML + SB_ONEOF_I2C0FMH + SB_ONEOF_I2C0FMD + SB_ONEOF_I2C0FPL + SB_ONEOF_I2C0FPH + SB_ONEOF_I2C0FPD + SB_ONEOF_I2C0M0C0 + SB_ONEOF_I2C0M1C0 + SB_ONEOF_I2C0M2C0 + endif; + SEPARATOR + SB_ONEOF_LPSSI2C1ENABLE + suppressif ideqval SETUP_DATA.LpssI2c1Enable == 0; + SB_ONEOF_LPSSI2C1VOLSELECT + SB_ONEOF_ATMELTPL + SB_ONEOF_ELANTPL + SB_ONEOF_NTRITPL + SB_ONEOF_EETITPL + SEPARATOR + SB_ONEOF_ELANTPD + SB_ONEOF_SYNATPD + SB_ONEOF_ALPSTPD + SB_ONEOF_CYPRTPD + SEPARATOR + SB_ONEOF_I2C1SSL + SB_ONEOF_I2C1SSH + SB_ONEOF_I2C1SSD + SB_ONEOF_I2C1FML + SB_ONEOF_I2C1FMH + SB_ONEOF_I2C1FMD + SB_ONEOF_I2C1FPL + SB_ONEOF_I2C1FPH + SB_ONEOF_I2C1FPD + SB_ONEOF_I2C1M0C1 + SB_ONEOF_I2C1M1C1 + SB_ONEOF_I2C1M2C1 + endif; + SEPARATOR + SB_ONEOF_LPSSSPI0ENABLE + suppressif ideqval SETUP_DATA.LpssSpi0Enable == 0; + SB_ONEOF_SPI0M0C2 + SB_ONEOF_SPI0M1C2 + endif; + SEPARATOR + SB_ONEOF_LPSSSPI1ENABLE + suppressif ideqval SETUP_DATA.LpssSpi1Enable == 0; + SB_ONEOF_SPI1M0C3 + SB_ONEOF_SPI1M1C3 + endif; + SEPARATOR + SB_ONEOF_LPSSUART0ENABLE + suppressif ideqval SETUP_DATA.LpssUart0Enable == 0; + SB_ONEOF_BLUETOOTH0 + SEPARATOR + SB_ONEOF_UAR0M0C4 + SB_ONEOF_UAR0M1C4 + endif; + SEPARATOR + SB_ONEOF_LPSSUART1ENABLE + suppressif ideqval SETUP_DATA.LpssUart1Enable == 0; + SB_ONEOF_BLUETOOTH1 + SEPARATOR + SB_ONEOF_UAR1M0C5 + SB_ONEOF_UAR1M1C5 + endif; + endif; + SEPARATOR + SB_ONEOF_LPSSSDIOENABLE + SEPARATOR + SB_ONEOF_LPSSMODE + SB_ONEOF_LPSSINTMODE + + endform; //End of PCH_LPSS_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCH_LPSS_CONFIG_OPTIONS + + #endif +#endif // End of SERIAL_IO_SUPPORT +//---------------------------------------------------------------------------- +// CHIPSET - SB ADSP CONFIGURATION Form +//---------------------------------------------------------------------------- +#if defined(ADSP_SUPPORT) && (ADSP_SUPPORT == 1) + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_PCH_ADSP_CONFIG_OPTIONS + #define SB_FORM_PCH_ADSP_CONFIG_OPTIONS + + form formid = AUTO_ID(PCH_ADSP_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_ADSP_CONFIGURATION_TITLE); + + SUBTITLE(STRING_TOKEN (STR_ADSP_CONFIGURATION_TITLE)) + + SEPARATOR + + SB_ONEOF_ADSPENABLE + suppressif ideqval SETUP_DATA.ADspEnable == 0; + SB_ONEOF_ADSPD3PG + SB_ONEOF_ADSPCODECSELECT + SB_ONEOF_ADSPBLUETOOTH + SB_ONEOF_ADSPMODE + endif; + + endform; //End of PCH_ADSP_OPTIONS_FORM_ID + + #endif // End of SB_FORM_PCH_ADSP_CONFIG_OPTIONS + + #endif +#endif // End of ADSP_SUPPORT +//---------------------------------------------------------------------------- +// +//---------------------------------------------------------------------------- +#endif // End of CHIPSET_FORM_SET + + + +//---------------------------------------------------------------------------- +// ADVANCED - Atapi Configuration Form +//---------------------------------------------------------------------------- +#ifdef ADVANCED_FORM_SET + + #ifndef SUPPRESS_GRAYOUT_ENDIF //old Core + #define SUPPRESS_GRAYOUT_ENDIF endif; + #endif + + #ifdef FORM_SET_VARSTORE + varstore SETUP_PLATFORM_DATA, + key = PLATFORM_FEATURES_ID, + name = SetupPlatformData, + guid = SETUP_GUID; + #endif + + #ifdef FORM_SET_VARSTORE + varstore SB_PLATFORM_DATA, + key = SB_PLATFORM_DATA_ID, + name = SbPlatformData, + guid = SETUP_GUID; + #endif + + #ifdef FORM_SET_ITEM + // Define controls to be added to the main page of the formset + #endif + + #ifdef FORM_SET_GOTO + // Define goto commands for the forms defined in this file + goto SATA_CONFIG_FORM_ID, + prompt = STRING_TOKEN (STR_SATA_CONFIG_FORM), + help = STRING_TOKEN (STR_SATA_CONFIG_FORM_HELP); + + goto THERMAL_CONFIG_FORM_ID, + prompt = STRING_TOKEN (STR_THERMAL_CONFIGURATION), + help = STRING_TOKEN (STR_THERMAL_CONFIGURATION_HELP); + #endif + +//---------------------------------------------------------------------------- +// ADVANCED - Thermal Configuration Form +//---------------------------------------------------------------------------- + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_THERMAL_CONFIGURATION + #define SB_FORM_THERMAL_CONFIGURATION + + form formid = AUTO_ID(THERMAL_CONFIG_FORM_ID), + title = STRING_TOKEN (STR_THERMAL_CONFIGURATION); + + goto PLATFORM_THERMAL_CONFIG_FORM_ID, + prompt = STRING_TOKEN (STR_PLATFORM_THERMAL_CONFIG_FORM_TITLE), + help = STRING_TOKEN (STR_PLATFORM_THERMAL_CONFIG_FORM_HELP); + + endform; // End of THERMAL_CONFIG_FORM_ID + + #endif // End of SB_FORM_THERMAL_CONFIGURATION + +//---------------------------------------------------------------------------- +// ADVANCED - Platform Thermal Configuration Form +//---------------------------------------------------------------------------- + + #ifndef SB_FORM_PLATFORM_THERMAL_CONFIG + #define SB_FORM_PLATFORM_THERMAL_CONFIG + + form formid = AUTO_ID(PLATFORM_THERMAL_CONFIG_FORM_ID), + title = STRING_TOKEN (STR_PLATFORM_THERMAL_CONFIG_FORM_TITLE); + + SUBTITLE(STRING_TOKEN (STR_PLATFORM_THERMAL_CONFIG_FORM_TITLE)) + + SEPARATOR + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_AUTOTHERMALREPORT + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.AutoThermalReport == 1; + SB_ONEOF_CRITICALTHERMALTRIPPOINT + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.AutoThermalReport == 1; + SB_ONEOF_AC0TRIPPOINT + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_AC0FANSPEED + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_AC1TRIPPOINT + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_AC1FANSPEED + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.AutoThermalReport == 1; + SB_ONEOF_PASSIVETHERMALTRIPPOINT + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_PASSIVETC1VALUE + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_PASSIVETC2VALUE + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_PASSIVETSPVALUE + endif; + +#if defined iME_SUPPORT && iME_SUPPORT + + SEPARATOR + + // The grayout below is always true. TrEnabled value is set according to softstraps. + // It can no longer be toggled from setup, but is left here as information for user. +/* grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER OR + ideqval SETUP_DATA.TrEnabled == 0 OR + ideqval SETUP_DATA.TrEnabled == 1; + SB_ONEOF_TRENABLED + endif;*/ + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.TrEnabled == 0; + SB_ONEOF_SMBUSECMSGLEN + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.TrEnabled == 0; + SB_ONEOF_SMBUSECMSGPEC + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.TrEnabled == 0; + SB_ONEOF_TSONDIMM1 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.TrEnabled == 0; + SB_ONEOF_TSONDIMM2 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.TrEnabled == 0; + SB_ONEOF_TSONDIMM3 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.TrEnabled == 0; + SB_ONEOF_TSONDIMM4 + SUPPRESS_GRAYOUT_ENDIF +#endif // Ena of iME_SUPPORT + + SEPARATOR + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_THERMALDEVICEENABLE + endif; + +/* grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + //SB_ONEOF_PCHTEMPREADENABLE + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + //SB_ONEOF_CPUENERGYREADENABLE + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + //SB_ONEOF_CPUTEMPREADENABLE + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + //SB_ONEOF_ALERTENABLELOCK + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.AlertEnableLock == 0x0; + //SB_ONEOF_PCHALERT + //SB_ONEOF_DIMMALERT + SUPPRESS_GRAYOUT_ENDIF // suppressif ideqval SETUP_DATA.AlertEnableLock == 0x0;*/ + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SB_PLATFORM_DATA.PchHotLevelPresent == 0; + SB_ONEOF_PCHHOTLEVEL + SUPPRESS_GRAYOUT_ENDIF // suppressif ideqval SETUP_DATA.HidePchHotLevel == 1; + + endform;//End of PLATFORM_THERMAL_CONFIG_FORM_ID + + #endif // End of SB_FORM_PLATFORM_THERMAL_CONFIG + +//---------------------------------------------------------------------------- +// ADVANCED - SATA Configuration Form +//---------------------------------------------------------------------------- + // Define forms + #ifndef SB_FORM_SATA_CONFIG + #define SB_FORM_SATA_CONFIG + + form formid = AUTO_ID(SATA_CONFIG_FORM_ID), + title = STRING_TOKEN (STR_SATA_CONFIG_FORM); + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_PCHSATA + endif; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.PchSata == 0; + suppressif ideqval SB_PLATFORM_DATA.LPTType == 1; + SB_ONEOF_SATAINTERFACEMODE + endif; + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_ULTSATAINTERFACEMODE + endif; + SB_ONEOF_SATATESTMODE + SUPPRESS_GRAYOUT_ENDIF // suppressif ideqval SETUP_DATA.PchSata == 0; + +#if SataDriver_SUPPORT +#if !defined (CsmOptOut_SUPPORT) || (CsmOptOut_SUPPORT == 0) + suppressif ideqval SB_PLATFORM_DATA.LPTType == 1; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif NOT ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_RAID OR \ + ideqval SETUP_DATA.PchSata == 0; + SB_ONEOF_SATARAIDROM + SUPPRESS_GRAYOUT_ENDIF // suppressif ideqval SETUP_DATA.PchSata == 0; + endif; + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif NOT ideqval SETUP_DATA.ULTSataInterfaceMode == SATA_MODE_RAID OR \ + ideqval SETUP_DATA.PchSata == 0; + SB_ONEOF_SATARAIDROM + SUPPRESS_GRAYOUT_ENDIF // suppressif ideqval SETUP_DATA.PchSata == 0; + endif; +#endif +#endif + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0 OR ideqval SETUP_DATA.PchSata == 0; + SB_ONEOF_SALPSUPPORT + SB_ONEOF_SATACONTROLLERSPEED + SUPPRESS_GRAYOUT_ENDIF // suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE OR ideqval SETUP_DATA.PchSata == 0; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + goto PCH_SATA_SFMS_OPTIONS_FORM_ID, + prompt = STRING_TOKEN (STR_SATA_SFMS_OPTIONS_FORM_TITLE), + help = STRING_TOKEN (STR_SATA_SFMS_OPTIONS_FORM_HELP); + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 1; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif NOT ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_RAID; + SB_ONEOF_SATAALTERNATEID + SUPPRESS_GRAYOUT_ENDIF + endif; + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif NOT ideqval SETUP_DATA.ULTSataInterfaceMode == SATA_MODE_RAID; + SB_ONEOF_SATAALTERNATEID + SUPPRESS_GRAYOUT_ENDIF + endif; + +// subtitle text = STRING_TOKEN (STR_EMPTY_STRING); + SEPARATOR + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SATA0_STRING), + text = STRING_TOKEN (STR_SATA0_NAME), + flags = 0, + key = 0; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SOFT_PRESERVE), + text = STRING_TOKEN (STR_SATA0_SOFT_PRESERVE_STATUS), + flags = 0, + key = 0; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATAPORT0 + SB_ONEOF_SATAHOTPLUG0 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0 OR ideqval SETUP_DATA.SataHotPlug[OFFSET_0] == 0; + SB_ONEOF_SATAMECHANICALSW0 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_EXTERNALSATA0 + SB_ONEOF_SOLIDSTATEDRIVE0 + SB_ONEOF_SATASPINUP0 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATADEVSLP0 + SB_ONEOF_SATAENABLEDITOCONFIGP0 + suppressif ideqval SETUP_DATA.SataEnableDitoConfig[OFFSET_0] == 0; + SB_ONEOF_SATADITOVALP0 + SB_ONEOF_SATADMVALP0 + endif; + endif; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SATA1_STRING), + text = STRING_TOKEN (STR_SATA1_NAME), + flags = 0, + key = 0; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SOFT_PRESERVE), + text = STRING_TOKEN (STR_SATA1_SOFT_PRESERVE_STATUS), + flags = 0, + key = 0; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATAPORT1 + SB_ONEOF_SATAHOTPLUG1 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0 OR ideqval SETUP_DATA.SataHotPlug[OFFSET_1] == 0; + SB_ONEOF_SATAMECHANICALSW1 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_EXTERNALSATA1 + SB_ONEOF_SOLIDSTATEDRIVE1 + SB_ONEOF_SATASPINUP1 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATADEVSLP1 + SB_ONEOF_SATAENABLEDITOCONFIGP1 + suppressif ideqval SETUP_DATA.SataEnableDitoConfig[OFFSET_1] == 0; + SB_ONEOF_SATADITOVALP1 + SB_ONEOF_SATADMVALP1 + endif; + endif; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SATA2_STRING), + text = STRING_TOKEN (STR_SATA2_NAME), + flags = 0, + key = 0; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SOFT_PRESERVE), + text = STRING_TOKEN (STR_SATA2_SOFT_PRESERVE_STATUS), + flags = 0, + key = 0; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATAPORT2 + SB_ONEOF_SATAHOTPLUG2 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0 OR ideqval SETUP_DATA.SataHotPlug[OFFSET_2] == 0; + SB_ONEOF_SATAMECHANICALSW2 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_EXTERNALSATA2 + SB_ONEOF_SOLIDSTATEDRIVE2 + SB_ONEOF_SATASPINUP2 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATADEVSLP2 + SB_ONEOF_SATAENABLEDITOCONFIGP2 + suppressif ideqval SETUP_DATA.SataEnableDitoConfig[OFFSET_2] == 0; + SB_ONEOF_SATADITOVALP2 + SB_ONEOF_SATADMVALP2 + endif; + endif; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SATA3_STRING), + text = STRING_TOKEN (STR_SATA3_NAME), + flags = 0, + key = 0; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SOFT_PRESERVE), + text = STRING_TOKEN (STR_SATA3_SOFT_PRESERVE_STATUS), + flags = 0, + key = 0; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATAPORT3 + SB_ONEOF_SATAHOTPLUG3 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0 OR ideqval SETUP_DATA.SataHotPlug[OFFSET_3] == 0; + SB_ONEOF_SATAMECHANICALSW3 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_EXTERNALSATA3 + SB_ONEOF_SOLIDSTATEDRIVE3 + SB_ONEOF_SATASPINUP3 + SUPPRESS_GRAYOUT_ENDIF + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATADEVSLP3 + SB_ONEOF_SATAENABLEDITOCONFIGP3 + suppressif ideqval SETUP_DATA.SataEnableDitoConfig[OFFSET_3] == 0; + SB_ONEOF_SATADITOVALP3 + SB_ONEOF_SATADMVALP3 + endif; + endif; + + suppressif ideqval SB_PLATFORM_DATA.LPTType == 1; + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SATA4_STRING), + text = STRING_TOKEN (STR_SATA4_NAME), + flags = 0, + key = 0; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SOFT_PRESERVE), + text = STRING_TOKEN (STR_SATA4_SOFT_PRESERVE_STATUS), + flags = 0, + key = 0; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATAPORT4 + SB_ONEOF_SATAHOTPLUG4 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0 OR ideqval SETUP_DATA.SataHotPlug[OFFSET_4] == 0; + SB_ONEOF_SATAMECHANICALSW4 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_EXTERNALSATA4 + SB_ONEOF_SOLIDSTATEDRIVE4 + SB_ONEOF_SATASPINUP4 + SUPPRESS_GRAYOUT_ENDIF + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SATA5_STRING), + text = STRING_TOKEN (STR_SATA5_NAME), + flags = 0, + key = 0; + + text + help = STRING_TOKEN (STR_EMPTY_STRING), + text = STRING_TOKEN (STR_SOFT_PRESERVE), + text = STRING_TOKEN (STR_SATA5_SOFT_PRESERVE_STATUS), + flags = 0, + key = 0; + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_SATAPORT5 + SB_ONEOF_SATAHOTPLUG5 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0 OR ideqval SETUP_DATA.SataHotPlug[OFFSET_5] == 0; + SB_ONEOF_SATAMECHANICALSW5 + SUPPRESS_GRAYOUT_ENDIF + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + suppressif ideqval SETUP_DATA.SataInterfaceMode == SATA_MODE_IDE AND ideqval SB_PLATFORM_DATA.LPTType == 0; + SB_ONEOF_EXTERNALSATA5 + SB_ONEOF_SOLIDSTATEDRIVE5 + SB_ONEOF_SATASPINUP5 + SUPPRESS_GRAYOUT_ENDIF + + endif; + + endform; // End of SATA_CONFIG_FORM_ID + + #endif // End of SB_FORM_SATA_CONFIG + + #endif +//---------------------------------------------------------------------------- +// +//---------------------------------------------------------------------------- + + +//---------------------------------------------------------------------------- +// ADVANCED - SATA SFMS Options Form +//---------------------------------------------------------------------------- + #ifdef FORM_SET_FORM + + #ifndef SB_FORM_SATA_SFMS_OPTIONS + #define SB_FORM_SATA_SFMS_OPTIONS + + form formid = AUTO_ID(PCH_SATA_SFMS_OPTIONS_FORM_ID), + title = STRING_TOKEN (STR_SATA_SFMS_OPTIONS_FORM_TITLE); + + grayoutif ideqval SYSTEM_ACCESS.Access == SYSTEM_PASSWORD_USER; + SB_ONEOF_SATARAIDR0 + SB_ONEOF_SATARAIDR1 + SB_ONEOF_SATARAIDR10 + SB_ONEOF_SATARAIDR5 + SB_ONEOF_SATARAIDIRRT + SB_ONEOF_SATARAIDOUB + SB_ONEOF_SATAHDDLK + SB_ONEOF_SATALEDL + SB_ONEOF_SATARAIDIOOE + SB_ONEOF_SMARTSTORAGE + SB_ONEOF_OROMUIDELAY + endif; + + endform; //End of PCH_RAID_SFMS_OPTIONS_FORM_ID + + #endif // End of SB_FORM_SATA_SFMS_OPTIONS + + #endif +//---------------------------------------------------------------------------- +// +//---------------------------------------------------------------------------- + +#endif // ADVANCED_FORM_SET + + +//------------------------------------------------------------------------------------ + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/SBSetup/SB.uni b/Board/SB/SBSetup/SB.uni Binary files differnew file mode 100644 index 0000000..ceb801a --- /dev/null +++ b/Board/SB/SBSetup/SB.uni diff --git a/Board/SB/SBSetup/SBSetup.c b/Board/SB/SBSetup/SBSetup.c new file mode 100644 index 0000000..5a7668e --- /dev/null +++ b/Board/SB/SBSetup/SBSetup.c @@ -0,0 +1,787 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSetup/SBSetup.c 13 1/29/15 4:47a Mirayang $ +// +// $Revision: 13 $ +// +// $Date: 1/29/15 4:47a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSetup/SBSetup.c $ +// +// 13 1/29/15 4:47a Mirayang +// [TAG] EIP20069 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Add JMB36X module SATA setup status error +// [RootCause] SBSetup.c is incomplete to difference betwenn device 28 +// and 31. +// [Solution] Determine device 28 and 31. +// +// 12 7/10/14 7:09a Mirayang +// [TAG] EIP176980 +// [Category] Improvement +// [Description] Change "#else if" to "#elif" +// +// 11 7/15/13 3:59a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Update LPT-LP steeping. +// [Files] SBSetup.c +// +// 10 7/03/13 8:04a Scottyang +// [TAG] EIP124410 +// [Category] Improvement +// [Description] Implement SMBIOS type 88h for CRID. +// [Files] SBDxe.c, SB.sdl, SB.sd, SBSetup.c, SBSetup.sdl +// +// 9 4/25/13 5:59a Scottyang +// [TAG] EIP121889 +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Sata device will show at wrong port. +// [RootCause] The RC will disable sata controller when no device +// connect. +// [Solution] If Sata controller D31:F2 is disable then read data form +// sata controller D31:F5. +// [Files] SBSetup.c +// +// 8 4/25/13 2:30a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Update LPT C0 stepping and separate stepping between +// LPT and LPT-LP. +// [Files] SBSetup.c +// +// 7 2/27/13 1:39a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Correct PCH LP B1 stepping. +// [Files] SBSetup.c +// +// 6 1/28/13 3:03a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create PCH Sku fot LPT-LP at setup. +// +// 5 12/12/12 9:19a Scottyang +// Update C0 stepping +// +// 4 7/27/12 6:06a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Support Server/Workstation PCH ID. Please set +// "PCH_SVR_WS_ID_SUPPORT". +// [Files] SBSetup.c, PchRegs.h, Pch.sdl +// +// [TAG] None +// [Category] Improvement +// [Description] Update to support ULT Platform. +// [Files] SB.H, SB.mak, SB.sdl, SB.sd, SBSetup.c, +// AcpiModeEnable.c, SBDxe.c, SBPEI.c, SBSMI.c, SleepSmi.c, +// SmiHandlerPorting.c, SmiHandlerPorting2.c, SBPPI.h, Pch.sdl +// +// 3 5/14/12 6:00a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Add PCH Device ID 0x8C40 to support WorkStation C228. +// [Files] SBSetup.c +// +// 2 2/20/12 4:19a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Update PCH divice IDs by LPT RefCode rev.0.5.1. +// [Files] SBSetup.c +// +// 1 2/08/12 8:23a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SBSetup.c +// +// Description: South Bridge Setup Routines +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include "Sb.h" +#include <Setup.h> +#include <SetupStrTokens.h> +#include <Protocol\PciIo.h> +#include <Protocol\DevicePath.h> +#include <protocol\BlockIo.h> +#include <Protocol\PDiskInfo.h> +#include <Protocol\PIDEController.h> +#include <Protocol\PIDEBus.h> +#include <Protocol\PciRootBridgeIo.h> +#include <PchInfo\PchInfo.h> +#include <Protocol\SBPlatformData.h> + +#define LEFT_JUSTIFY 0x01 +#define PREFIX_SIGN 0x02 +#define PREFIX_BLANK 0x04 +#define COMMA_TYPE 0x08 +#define LONG_TYPE 0x10 +#define PREFIX_ZERO 0x20 + +#define DXE_DEVICE_DISABLED 0 +#define DXE_DEVICE_ENABLED 1 + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +#define CHARACTER_NUMBER_FOR_VALUE 30 +#define _48_BIT_ADDRESS_FEATURE_SET_SUPPORTED 0x0400 +#define ATAPI_DEVICE 0x8000 +typedef enum { + EfiCompatibility, + EfiEnhancedMode + } EFI_SATA_MODE; + +typedef struct { + UINT16 DeviceId; + CHAR8 *SkuName; +} AMI_PCH_DID_SKUNAME; + +EFI_GUID gEfiDevicePathProtocolGuid = EFI_DEVICE_PATH_PROTOCOL_GUID; +EFI_GUID gEfiPciRootBridgeIoProtocolGuid = EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID; +EFI_GUID gEfiDiskInfoProtocolGuid = EFI_DISK_INFO_PROTOCOL_GUID; +EFI_GUID gEfiPchInfoProtocolGuid = EFI_PCH_INFO_PROTOCOL_GUID; + +STRING_REF gSATA[6] = { + STRING_TOKEN(STR_SATA0_NAME), + STRING_TOKEN(STR_SATA1_NAME), + STRING_TOKEN(STR_SATA2_NAME), + STRING_TOKEN(STR_SATA3_NAME), + STRING_TOKEN(STR_SATA4_NAME), + STRING_TOKEN(STR_SATA5_NAME) +}; +STRING_REF gSOFTPRES[6] = { + STRING_TOKEN(STR_SATA0_SOFT_PRESERVE_STATUS), + STRING_TOKEN(STR_SATA1_SOFT_PRESERVE_STATUS), + STRING_TOKEN(STR_SATA2_SOFT_PRESERVE_STATUS), + STRING_TOKEN(STR_SATA3_SOFT_PRESERVE_STATUS), + STRING_TOKEN(STR_SATA4_SOFT_PRESERVE_STATUS), + STRING_TOKEN(STR_SATA5_SOFT_PRESERVE_STATUS) +}; + +UINT32 +GetNumTenthsOfGB ( + UINT32 RemainderBytesOfGB + ); + + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AsciiToUnicode +// +// Description: +// +// Inpuut: IN CHAR8 *AsciiString, +// OUT CHAR16 *UnicodeString +// +// Output: None +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID AsciiToUnicode ( + IN CHAR8 *AsciiString, + OUT CHAR16 *UnicodeString + ) +{ + UINT8 Index = 0; + + while (AsciiString[Index] != 0) { + UnicodeString[Index] = (CHAR16) AsciiString[Index]; + Index++; + } +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: SwapEntries +// +// Description: +// +// Inpuut: IN CHAR8 *Data, +// IN UINT16 Size +// +// Output: None +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID SwapEntries ( + IN CHAR8 *Data, + IN UINT16 Size +) +{ + UINT16 Index; + CHAR8 Temp8; + + for (Index = 0; (Index+1) < Size; Index+=2) { + Temp8 = Data[Index]; + Data[Index] = Data[Index + 1]; + Data[Index + 1] = Temp8; + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitSBStrings +// +// Description: Initializes South Bridge Setup String +// +// Inpuut: HiiHandle - Handle to HII database +// Class - Indicates the setup class +// +// Output: None +// +// Notes: PORTING REQUIRED +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID InitSBStrings(IN EFI_HII_HANDLE HiiHandle, IN UINT16 Class) +{ + EFI_STATUS Status; + PCI_DEVICE_PATH *PciDevicePath; + CHAR8 *NewString; + CHAR8 *SoftPres; + UINT8 Index; + volatile UINT16 *pAddress; + UINT16 SataP0P1Status; + UINT16 SataP4P5Status; + UINT16 AhciModePortStatus; + UINT16 SataMode; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_DEVICE_PATH_PROTOCOL *DevicePathNode; + EFI_DISK_INFO_PROTOCOL *DiskInfo; + UINT32 SataPortIndex, IdeChannel; + IDENTIFY_DATA *IdentifyDriveInfo = NULL; + UINT32 BufferSize = 0; + STRING_REF Token; + STRING_REF SoftPresStatus; + CHAR8 ModelNumber[42]; + UINT64 NumSectors = 0; + UINT64 DriveSizeInBytes = 0; + UINTN RemainderInBytes = 0; + UINT32 DriveSizeInGB = 0; + UINT32 NumTenthsOfGB = 0; + UINT32 SectorSize = 512; // Default Sector Size + UINT8 w; + UINT8 x; + UINT8 y; + UINT8 z; + EFI_PCH_INFO_PROTOCOL *PchInfo; + UINT16 Data16; + UINT32 SataController02; + UINT32 SataController05; + UINT8 i; + CHAR8 *RevId; + AMI_PCH_DID_SKUNAME PchDeviceId[] = { + { 0x8C42, "DT Full Sku" }, + { 0x8C44, "Z87" }, + { 0x8C46, "Z85" }, + { 0x8C4A, "H87" }, + { 0x8C4C, "Q85" }, + { 0x8C4E, "Q87" }, + { 0x8C50, "B85" }, + { 0x8C5C, "H81" }, + { 0x8C41, "MB Full Sku" }, + { 0x8C49, "HM86" }, + { 0x8C4B, "HM87" }, + { 0x8C4F, "QM87" }, + { 0x8C52, "C222" }, + { 0x8C54, "C224" }, + { 0x8C56, "C226" }, + { 0x9C41, "MB LP Full SKU" }, // LynxPoint-LP + { 0x9C43, "Premium SKU"}, + { 0x9C45, "Mainstream SKU"}, + { 0x9C47, "Value SKU"} + }; + UINTN VariableSize; + EFI_GUID SetupGuid = SETUP_GUID; + SB_PLATFORM_DATA SbPlatformData; + + Data16 = READ_PCI16_SB(PCI_DID); + + if (Class == ADVANCED_FORM_SET_CLASS) { + + // Assume no line strings is longer than 256 bytes. + + Status = pBS->AllocatePool(EfiBootServicesData, 0x100, &NewString); + ASSERT_EFI_ERROR(Status); + + Status = pBS->AllocatePool(EfiBootServicesData, 0x40, &SoftPres); + ASSERT_EFI_ERROR(Status); + + + PciDevicePath = NULL; + + SataMode = *((volatile UINT16 *)(UINTN)SATA_PCIE_REG(SATA_REG_MAP)); + //(EIP121889) >> + if((Data16 & 0xFF00) != 0x9C00 ){ + if(SataMode == 0xFFFF) //If Ide Controller F2 is disabled, check Ide Controller F5 + SataMode = *((volatile UINT16 *)(UINTN)SATA2_PCIE_REG(SATA_REG_MAP)); + } + //(EIP121889) << + if ((SataMode & (BIT07 | BIT06)) == 0) { // IDE + pAddress = (volatile UINT16 *)(UINTN)SATA_PCIE_REG(SATA_REG_PCS); + SataP0P1Status = *(volatile UINT16 *)pAddress; + pAddress = (volatile UINT16 *)(UINTN)SATA2_PCIE_REG(SATA_REG_PCS); + SataP4P5Status = *(volatile UINT16 *)pAddress; + } else { // AHCI or Raid + pAddress = (volatile UINT16 *)(UINTN)SATA_PCIE_REG(SATA_REG_PCS); + AhciModePortStatus = *(volatile UINT16 *)pAddress; + } + + Status = pBS->LocateHandleBuffer ( + ByProtocol, + &gEfiDiskInfoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR(Status)) HandleCount = 0; + + for (Index = 0; Index < HandleCount; Index++) { + Status = pBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiDevicePathProtocolGuid, + (VOID *) &DevicePath + ); + ASSERT_EFI_ERROR(Status); + + DevicePathNode = DevicePath; + while (!isEndNode (DevicePathNode)) { + if ((DevicePathNode->Type == HARDWARE_DEVICE_PATH) && + (DevicePathNode->SubType == HW_PCI_DP)) + { + PciDevicePath = (PCI_DEVICE_PATH *) DevicePathNode; + break; + } + + DevicePathNode = NEXT_NODE (DevicePathNode); + } + + if (PciDevicePath == NULL) continue; + + SataController02 = READ_PCI32(0x00, 0x1F, 0x02, 0x00); + SataController05 = READ_PCI32(0x00, 0x1F, 0x05, 0x00); + + if (PciDevicePath->Device != 0x1C && (SataController02!=0xffffffff || SataController05!=0xffffffff)) { + + Status = pBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiDiskInfoProtocolGuid, + &DiskInfo + ); + ASSERT_EFI_ERROR (Status); + + if ((SataMode & (BIT07 | BIT06)) == 0) { // IDE MODE + Status = DiskInfo->WhichIde ( + DiskInfo, + &IdeChannel, + &SataPortIndex + ); + SataPortIndex = (IdeChannel * 2) + SataPortIndex; + + if (SataPortIndex == 1 || SataPortIndex == 2) // SINDX ¡V Serial ATA Index (D31:F2) + SataPortIndex ^= 3; // Port 0 = Primary Master + // Port 2 = Primary Slave + // Port 1 = Secondary Master + // Port 3 = Secondary Slave + if (PciDevicePath->Function == SATA2_FUN) // Port 4, 5 in SATA2 + SataPortIndex += 4; + Token = gSATA[SataPortIndex]; + SoftPresStatus = gSOFTPRES[SataPortIndex]; + } else { // AHCI or Raid // SATA MODE + Status = DiskInfo->WhichIde ( + DiskInfo, + &IdeChannel, + &SataPortIndex + ); + Token = gSATA[IdeChannel]; + SoftPresStatus = gSOFTPRES[IdeChannel]; + } + + Status = pBS->AllocatePool(EfiBootServicesData, sizeof (IDENTIFY_DATA), &IdentifyDriveInfo); + ASSERT_EFI_ERROR (Status); + + pBS->SetMem(IdentifyDriveInfo, sizeof (IDENTIFY_DATA), 0); + + BufferSize = sizeof (IDENTIFY_DATA); + Status = DiskInfo->Identify ( + DiskInfo, + IdentifyDriveInfo, + &BufferSize + ); + ASSERT_EFI_ERROR (Status); + + } else { + // + // Off board + // + continue; + } + pBS->SetMem(ModelNumber, 42, 0); + pBS->CopyMem (ModelNumber, IdentifyDriveInfo->Model_Number_27, 40); + SwapEntries (ModelNumber, 40); + // Truncate it at DEVICE_NAME_LENGTH characters + ModelNumber[DEVICE_NAME_LENGTH] = '\0'; + + // + // For HardDisk append the size. Otherwise display atapi + // + if (!(IdentifyDriveInfo->General_Config_0 & ATAPI_DEVICE)) { + if (IdentifyDriveInfo->Command_Set_Supported_83 & _48_BIT_ADDRESS_FEATURE_SET_SUPPORTED) { + NumSectors = IdentifyDriveInfo->LBA_48; + if((IdentifyDriveInfo->Reserved_104_126[2] & 0x4000) && // WORD 106 valid? - BIT 14 - 1 + (!(IdentifyDriveInfo->Reserved_104_126[2] & 0x8000)) && // WORD 106 valid? - BIT 15 - 0 + (IdentifyDriveInfo->Reserved_104_126[2] & 0x1000)) { // WORD 106 bit 12 - Sectorsize > 256 words + // The sector size is in words 117-118. + SectorSize = (UINT32)(IdentifyDriveInfo->Reserved_104_126[13] + \ + (IdentifyDriveInfo->Reserved_104_126[14] << 16)) * 2; + } + } else { + NumSectors = IdentifyDriveInfo->Addressable_Sector_60; + } + DriveSizeInBytes = Mul64(NumSectors, SectorSize); + + //DriveSizeInGB is DriveSizeInBytes / 1 GB (1 Binary GB = 2^30 bytes) +//#### DriveSizeInGB = (UINT32) Div64(DriveSizeInBytes, (1 << 30), &RemainderInBytes); + //Convert the Remainder, which is in bytes, to number of tenths of a Binary GB. +//#### NumTenthsOfGB = GetNumTenthsOfGB(RemainderInBytes); + + //DriveSizeInGB is DriveSizeInBytes / 1 GB (1 Decimal GB = 10^9 bytes) + DriveSizeInGB = (UINT32) Div64(DriveSizeInBytes, 1000000000, &RemainderInBytes); + //Convert the Remainder, which is in bytes, to number of tenths of a Decimal GB. + NumTenthsOfGB = (UINT32)(RemainderInBytes / 100000000); + + Sprintf(NewString, "%s (%d.%dGB)", ModelNumber, DriveSizeInGB, NumTenthsOfGB); + if ((IdentifyDriveInfo->Reserved_76_79[0] != 0xFFFF ) && (IdentifyDriveInfo->Reserved_76_79[2] & 0x0040)) + Sprintf(SoftPres, "SUPPORTED"); + else + Sprintf(SoftPres, "NOT SUPPORTED"); + + } else { + Sprintf(NewString, "%s ATAPI", ModelNumber); + Sprintf(SoftPres, " N/A "); + } + InitString( + HiiHandle, + Token, + L"%S", + NewString + ); + + InitString( + HiiHandle, + SoftPresStatus, + L"%S", + SoftPres + ); + + if (IdentifyDriveInfo) { + pBS->FreePool (IdentifyDriveInfo); + IdentifyDriveInfo = NULL; + } + } + if (HandleBuffer) + pBS->FreePool (HandleBuffer); + pBS->FreePool (NewString); + } + + Status = pBS->LocateProtocol( &gEfiPchInfoProtocolGuid, \ + NULL, \ + &PchInfo ); + if (!EFI_ERROR (Status)) { + x = (UINT8) ((PchInfo->RCVersion & 0xFF000000) >> 24); + y = (UINT8) ((PchInfo->RCVersion & 0xFF0000) >> 16); + z = (UINT8) ((PchInfo->RCVersion & 0xFF00) >> 8); + w = (UINT8) ((PchInfo->RCVersion & 0xFF)); + + InitString ( HiiHandle, + STRING_TOKEN (STR_PCH_RC_VER_VALUE), + L"%d.%d.%d.%d", + x, y, z, w); + } + + for (i = 0; i < sizeof(PchDeviceId) / sizeof(AMI_PCH_DID_SKUNAME); i++) { + if (Data16 == PchDeviceId[i].DeviceId) { + InitString( + HiiHandle, + STRING_TOKEN (STR_PCH_SKU_VALUE), + L"%S", + PchDeviceId[i].SkuName + ); + break; + } + } + + // Read the SB Platform Data + VariableSize = sizeof (SB_PLATFORM_DATA); + Status = pRS->GetVariable ( + L"SbPlatformData", + &SetupGuid, + NULL, + &VariableSize, + &SbPlatformData ); + if( EFI_ERROR (Status)) i = 0xff; + else i = SbPlatformData.PchRid; + if((Data16 & 0xFF00) == 0x9C00 ){ //LPT-LP stepping + switch (i) + { + case 0x00: + RevId = "00/A0"; + break; + + case 0x01: + RevId = "01/A1"; + break; + + case 0x02: + RevId = "02/B0"; + break; + + case 0x03: + RevId = "03/B1"; + break; + + case 0x04: + RevId = "04/B2"; + break; + + case 0x05: + RevId = "05/C0"; + break; + + default: + RevId = "Unknown"; + break; + } + }else{ //LPT stepping + switch (i) + { + case 0x00: + RevId = "00/A0"; + break; + + case 0x01: + RevId = "01/A1"; + break; + + case 0x02: + RevId = "02/B0"; + break; + + case 0x03: + RevId = "03/C0"; + break; + + case 0x04: + RevId = "04/C1"; + break; + + case 0x05: + RevId = "05/C2"; + break; + + default: + RevId = "Unknown"; + break; + } + } + InitString( + HiiHandle, + STRING_TOKEN (STR_PCH_REVID_VALUE), + L"%S", + RevId + ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetNumTenthsOfGB +// +// Description: +// x x/16 num tenths +// - ---- ---------- +// 0 0 0 +// 1 .0625 1 +// 2 .125 1 +// 3 .1875 2 +// 4 .25 2 +// 5 .3125 3 +// 6 .375 4 +// 7 .4375 4 +// 8 .5 5 +// 9 .5625 6 +// 10 .625 6 +// 11 .6875 7 +// 12 .75 7 +// 13 .8125 8 +// 14 .875 9 +// 15 .9375 9 +// +// Inpuut: IN UINT32 RemainderBytesOfGB +// +// Output: UINT32 +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 +GetNumTenthsOfGB ( IN UINT32 RemainderBytesOfGB ) +{ + UINT32 Tenths = 0; //num tenths of of a GB + UINT32 Sixteenths = RemainderBytesOfGB / (1 << 26); //num sixteenths of a Binary GB + + switch (Sixteenths) { + case 0: + Tenths = 0; break; + case 1: + case 2: + Tenths = 1; break; + case 3: + case 4: + Tenths = 2; break; + case 5: + Tenths = 3; break; + case 6: + case 7: + Tenths = 4; break; + case 8: + Tenths = 5; break; + case 9: + case 10: + Tenths = 6; break; + case 11: + case 12: + Tenths = 7; break; + case 13: + Tenths = 8; break; + case 14: + case 15: + Tenths = 9; break; + default: + Tenths = 0; break; + } + + return Tenths; +} + //(EIP124410)>> +EFI_STATUS +EFIAPI +SB_CRID_CALLBACK ( + IN EFI_HII_HANDLE HiiHandle, + IN UINT16 Class, + IN UINT16 SubClass, + IN UINT16 Key +) +{ + EFI_STATUS Status = EFI_SUCCESS; + SETUP_DATA *SetupData = NULL; + CALLBACK_PARAMETERS *pCallbackData = NULL; +#if EFI_SPECIFICATION_VERSION > 0x20000 + UINTN BufferSize = sizeof(SETUP_DATA); + EFI_GUID SetupGuid = SETUP_GUID; +#else + UINT8 *pNvRamMap; +#endif + + pCallbackData = GetCallbackParameters(); + if(pCallbackData == NULL) return Status; + +#if ((TSE_BUILD >= 0x1224) && (EFI_SPECIFICATION_VERSION >= 0x2000A)) + if (pCallbackData->Action != EFI_BROWSER_ACTION_CHANGED) + return Status; +#elif ((TSE_BUILD > 0x1208) && (EFI_SPECIFICATION_VERSION >= 0x2000A)) + // Check callback action + if (pCallbackData->Action != EFI_BROWSER_ACTION_CHANGING) + return Status; +#endif + +#if EFI_SPECIFICATION_VERSION > 0x20000 + Status = pBS->AllocatePool(EfiBootServicesData, BufferSize, &SetupData); + if(EFI_ERROR(Status)) return Status; + + Status = HiiLibGetBrowserData( + &BufferSize, SetupData, + &SetupGuid, L"Setup"); + ASSERT_EFI_ERROR(Status); +#else + pNvRamMap = pCallbackData->Data->NvRamMap; + SetupData = (SETUP_DATA*)pNvRamMap; +#endif + + switch (Key) + { + case SB_CRID_KEY: + SetupData->EnableNbCrid = SetupData->PchEnableCrid; + break; + } + +#if EFI_SPECIFICATION_VERSION > 0x20000 + Status = HiiLibSetBrowserData( + BufferSize, SetupData, + &SetupGuid, L"Setup"); + ASSERT_EFI_ERROR(Status); + + pBS->FreePool(SetupData); +#endif; + + return EFI_SUCCESS; +} + //(EIP124410)<< +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/SBSetup/SBSetup.cif b/Board/SB/SBSetup/SBSetup.cif new file mode 100644 index 0000000..c1f86e6 --- /dev/null +++ b/Board/SB/SBSetup/SBSetup.cif @@ -0,0 +1,12 @@ +<component> + name = "SBSetup" + category = ModulePart + LocalRoot = "Board\SB\SBSetup" + RefName = "SBSetup" +[files] +"SBSetup.sdl" +"SBSetup.mak" +"SB.sd" +"SB.uni" +"SBSetup.c" +<endComponent> diff --git a/Board/SB/SBSetup/SBSetup.mak b/Board/SB/SBSetup/SBSetup.mak new file mode 100644 index 0000000..7578759 --- /dev/null +++ b/Board/SB/SBSetup/SBSetup.mak @@ -0,0 +1,68 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSetup/SBSetup.mak 1 2/08/12 8:23a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 8:23a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSetup/SBSetup.mak $ +# +# 1 2/08/12 8:23a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: SBSetup.mak +# +# Description: This make file builds north bridge Setup +# components and link them to respective binary +# +#<AMI_FHDR_END> +#************************************************************************* +All : SBSetup + +SBSetup : $(BUILD_DIR)\SBSetup.mak + +SetupSdbs : $(BUILD_DIR)\SB.sdb + +$(BUILD_DIR)\SB.sdb : $(SBSetup_DIR)\$(@B).sd $(SBSetup_DIR)\$(@B).uni + $(STRGATHER) -i INCLUDE -parse -newdb -db $(BUILD_DIR)\$(@B).sdb $(SBSetup_DIR)\$(@B).uni + $(STRGATHER) -scan -db $(BUILD_DIR)\$(@B).sdb -od $(BUILD_DIR)\$(@B).sdb $(SBSetup_DIR)\$(@B).sd + +$(BUILD_DIR)\SBSetup.mak : $(SBSetup_DIR)\$(@B).cif $(SBSetup_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(SBSetup_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +SetupBin : $(BUILD_DIR)\SBSetup.obj + +$(BUILD_DIR)\SBSetup.obj : $(PROJECT_DIR)\$(SBSetup_DIR)\SBSetup.c $(BUILD_DIR)\SetupStrTokens.h + $(CC) $(CFLAGS) $(INTEL_PCH_INCLUDES) /Fo$(BUILD_DIR)\ $(SBSetup_DIR)\SBSetup.c +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Board/SB/SBSetup/SBSetup.sdl b/Board/SB/SBSetup/SBSetup.sdl new file mode 100644 index 0000000..353242f --- /dev/null +++ b/Board/SB/SBSetup/SBSetup.sdl @@ -0,0 +1,98 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSetup/SBSetup.sdl 2 7/03/13 8:04a Scottyang $ +# +# $Revision: 2 $ +# +# $Date: 7/03/13 8:04a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SBSetup/SBSetup.sdl $ +# +# 2 7/03/13 8:04a Scottyang +# [TAG] EIP124410 +# [Category] Improvement +# [Description] Implement SMBIOS type 88h for CRID. +# [Files] SBDxe.c, SB.sdl, SB.sd, SBSetup.c, SBSetup.sdl +# +# 1 2/08/12 8:23a Yurenlai +# Intel Lynx Point/SB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "SB_SETUP_SUPPORT" + Value = "1" + Help = "Main switch to enable SBSetup support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes +End + +PATH + Name = "SBSetup_DIR" +End + +MODULE + Help = "Includes SBSetup.mak to Project" + File = "SBSetup.mak" +End + +ELINK + Name = "SbSetupCallbacks," + Parent = "SbConfigurationList" + InvokeOrder = AfterParent +End + +ELINK + Name = "InitSBStrings," + Parent = "SetupStringInit" + InvokeOrder = AfterParent +End + +ELINK + Name = "$(BUILD_DIR)\SB.sdb" + Parent = "SETUP_SDBS" + Priority = 20 + InvokeOrder = AfterParent +End + +ELINK + Name = "$(SBSetup_DIR)\SB.sd" + Parent = "SETUP_DEFINITIONS" + Priority = 20 + InvokeOrder = AfterParent +End + +ELINK + Name = "ITEM_CALLBACK(CHIPSET_FORM_SET_CLASS, 0, SB_CRID_KEY, SB_CRID_CALLBACK)," + Parent = "SetupItemCallbacks" + InvokeOrder = AfterParent +End +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Board/SB/Sb.ssp b/Board/SB/Sb.ssp new file mode 100644 index 0000000..3b006ae --- /dev/null +++ b/Board/SB/Sb.ssp @@ -0,0 +1,79 @@ +// This AMI Setup Script Processor (SSP) file contains setup items that +// are related to the CMOS Manager. +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/Sb.ssp 1 2/08/12 8:23a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 8:23a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/Sb.ssp $ +// +// 1 2/08/12 8:23a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* + +//--------------------------------------------------------------------------- +// CMOS manager starts auto-assigning at 0x40 +// +// This is a typical CMOS usage arrangement. +// (Note: these locations are not currently reserverd by default.) +//--------------------------------------------------------------------------- +// +// 0x00..0x3F Legacy CMOS area, used by CSM +// 0x40..0x7F OEM/ODM +// 0x80..0xBF Chipset +// 0xC0..0xFF Core+Technologies +// +// This is the format of a CMOS token defintion: +//--------------------------------------------------------------------------- +// NvramField (TOKEN_NAME) +// OptionBits = integer // how many bits to use +// [Default = integer] // assembler format "xxxh" +// [CheckSum = YES | NO] // include=YES | exclude=NO +// [Location = cmos address, clobber mask] // CMOS register, size/offset +// EndNvramField + + +//----------------------------------------------------------------- +// TODO: Check if all 8 bits are needed for each of these locations +//----------------------------------------------------------------- + +NvramField (SB_SSP_NMI_CONTROL_BITS) + OptionBits = 8 + Default = 00h + CheckSum = NO + Location = MKF_SB_CMOS_MISC_FLAG_REG, 003h +EndNvramField + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Board/SB/SbSetupData.h b/Board/SB/SbSetupData.h new file mode 100644 index 0000000..ff1a3c1 --- /dev/null +++ b/Board/SB/SbSetupData.h @@ -0,0 +1,503 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SbSetupData.h 27 8/01/13 4:32a Scottyang $ +// +// $Revision: 27 $ +// +// $Date: 8/01/13 4:32a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/SouthBridge/LynxPoint/Intel Pch SB Board/SbSetupData.h $ +// +// 27 8/01/13 4:32a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add PCIE LTR setup items. +// [Files] SB.sd, SB.uni, SBDxe.c, GetSetupData.c, SbSetupData.h +// +// 26 7/09/13 5:16a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create "PCH Cross Throttling" setup item.(Only ULT +// support) +// [Files] SBDxe.c, SB.sd, SB.uni, GetSetupData.c, SB.sd +// +// 25 5/13/13 8:58a Scottyang +// [TAG] EIP123496 +// [Category] Improvement +// [Description] Update PCH RC 1.5.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.* , SBDxe.C, SBPEI.c, +// SB.sd, SB.uni, SbSetupData.h, GetSetupData.c +// +// 24 3/15/13 3:40a Scottyang +// [TAG] EIP118121 +// [Category] Improvement +// [Description] Update PCH RC 1.3.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupData.h +// +// 23 3/04/13 10:08p Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add Solid State Drive item to port 6. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd +// +// 22 2/09/13 12:13a Scottyang +// [TAG] EIP114922 +// [Category] Improvement +// [Description] Update PCH RC 1.1.0. +// [Files] ..\ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SB.uni, GetSetupData.c, SbSetupDara.h +// +// 21 1/31/13 10:56a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add Serial IO GNVS setup option. +// [Files] SBDxe.c, SB.sd, SB.uni, SbSetupData.h, GetSetupData.c +// +// 20 1/10/13 4:49a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create DTIO value and DM value option +// [Files] SB.sd, SB.uni, SbSetupData.h, GetSetupData.c, SBDxe.c +// +// 19 1/03/13 4:56a Scottyang +// [TAG] None +// [Category] Bug Fix +// [Severity] Normal +// [Symptom] Build error when set IDE mode as default. +// [RootCause] The ULT did not support IDE mode that made the value +// redefine. +// [Solution] Separate Sata inter face for 2 Chip and ULT. +// [Files] SB.sd, GetSetupData.c, SbSetupData.h +// +// 18 12/24/12 5:42a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add option for XHCI Idel L1 workaroung. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c, +// SBPEI.c +// +// 17 12/22/12 2:05a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add PCIE "L1 Substates"setup option. +// [Files] GetSetupData.c, SbSetupData.h, SB.sd, SB.uni, SBDxe.c +// +// 16 12/18/12 6:03a Scottyang +// [TAG] EIP109697 +// [Category] Improvement +// [Description] Update PCH RC 0.8.1 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// +// 15 12/17/12 6:41a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add setup menu for LPSS and ECTG. +// [Files] GetSetupData.c +// SbSetupData.h +// SB.sd +// SB.uni +// SBDxe.c +// +// 14 12/13/12 10:34a Scottyang +// [TAG] EIP106687 +// [Category] Improvement +// [Description] Add option for delay to detect PCIE card. +// [Files] SBPEI.c, SB.sd, SB.uni, GetSetupData.c, SbSetupData.h, +// PciBus.c +// +// 13 11/20/12 9:45a Scottyang +// [TAG] EIP107014 +// [Category] Improvement +// [Description] Update RC 0.8.0 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SBPEI.c, +// SB.sd, SbSetupData.c, GetSetupDate.c +// +// 12 11/08/12 8:33a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Add device item that connect LPSS. +// [Files] GetSetupData.c, SbSetupData.h, SBDxe.c, SB.sd, SB.uni +// +// 11 11/07/12 6:09a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Remove HDMI item. +// [Files] SB.sd, SB.uni, GetSetupData.c, SbSetupData.h +// +// 10 10/25/12 7:18a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create NFC item at setup +// [Files] SB.sd, SB.uni, SbSetupData.h +// +// 9 10/23/12 8:27a Scottyang +// [TAG] None +// [Category] Improvement +// [Description] Create Device Sleep at setup menu +// [Files] SB.sd, SB.uni, SBDxe.c, GetSetupData.c, SbSetupData.h +// +// 8 10/16/12 2:15a Scottyang +// [TAG] EIP103924 +// [Category] Improvement +// [Description] Update RC 0.7.1 +// [Files] ReferenceCode\Chipset\LynxPoint\*.*, SBDxe.c, SB.sd, +// SbSetupData.c, GetSetupDate.c +// +// 7 9/26/12 3:50a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Implement ULT platform LPSS and ADSP setup option. +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SB.sdl +// +// 6 9/12/12 5:13a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Modify for Thunderbolt support. +// [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +// PciHotPlug.c +// +// 5 8/13/12 10:15a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Remove useless Dppm items. +// [Files] GetSetupData.c, SB.sd, SbSetupData.h, SBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Implement USB Precondition option for policy +// "UsbPrecondition". +// [Files] GetSetupData.c, SB.sd, SB.uni, SbSetupData.h, SBDxe.c, +// SBPEI.c +// +// 4 7/27/12 6:05a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Update setup items and policies. +// [Files] GetSetupData.c, SB.sdl, SB.sd, SB.uni, SbSetupData.h, +// SBPEI.c, SBDXE.c +// +// 3 5/03/12 6:33a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Modify to support Thunderbolt. +// [Files] SB.sd; SB.uni; SB.sdl; SbSetupData.h; PciHotPlug.c +// +// 2 4/25/12 9:06a Victortu +// [TAG] None +// [Category] Improvement +// [Description] Relayout PCH USB Setup. +// [Files] GetSetupData.c; SB.sd; SB.uni; SbSetupData.h; SBDxe.c +// +// 1 2/08/12 8:22a Yurenlai +// Intel Lynx Point/SB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: SbSetupData.h +// +// Description: South Bridge setup data header file, define all the South +// Bridge setup items and a structures in this file. +// +// Notes: The context of the SB_SETUP_DATA may be able to copy from +// SB.SD directly +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __SB_SETUP_DATA_H__ // To Avoid this header get compiled twice +#define __SB_SETUP_DATA_H__ + +#include <Efi.h> + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct _SB_SETUP_DATA SB_SETUP_DATA; + +#pragma pack(push, 1) + +typedef struct _SB_SETUP_DATA { + UINT8 PchLan; + UINT8 PchWakeOnLan; + UINT8 SlpLanLow; + UINT8 BoardCapability; + UINT8 DeepSxBattMode; + UINT8 DeepSxMode; + UINT8 Gp27Wake; + UINT8 PcieWake; + UINT8 PchAzalia; + UINT8 AzaliaDs; + UINT8 AzaliaPme; + UINT8 PchPciClockRun; + UINT8 SirqMode; + UINT8 PchDisplay; + UINT8 PchEnableCrid; + UINT8 SmiLock; + UINT8 BiosLock; + UINT8 GpioLock; + UINT8 BiosInterfaceLock; + UINT8 RtcLock; + // PCH DMI + UINT8 PchDmiAspm; + UINT8 PchDmiExtSync; + // PCI_EXPRESS_CONFIG, 8 ROOT PORTS + UINT8 PcieUsbWa; + UINT8 PcieClockGating; + UINT8 PcieRootPortSBDE; + UINT8 PcieSBDEPort; + UINT8 RootPortFunctionSwapping; + UINT8 PcieRootPortEn[8]; + UINT8 PcieRootPortAspm[8]; + UINT8 PcieRootPortURE[8]; + UINT8 PcieRootPortFEE[8]; + UINT8 PcieRootPortNFE[8]; + UINT8 PcieRootPortCEE[8]; + UINT8 PcieRootPortCTD[8]; + UINT8 PcieRootPortPIE[8]; + UINT8 PcieRootPortSFE[8]; + UINT8 PcieRootPortSNE[8]; + UINT8 PcieRootPortSCE[8]; + UINT8 PcieRootPortL1S[8]; + UINT8 PcieRootPortPMCE[8]; + UINT8 PcieRootPortHPE[8]; + UINT8 PcieRootPortSpeed[8]; + UINT8 PcieRPDetectNonComplaint[8]; + + UINT8 PcieLtrEnable[8]; + UINT8 PcieLtrConfigLock[8]; + UINT8 PcieSnoopLatencyOverrideMode[8]; + UINT8 PcieSnoopLatencyOverrideMultiplier[8]; + UINT8 PcieSnoopLatencyOverrideValue[8]; + UINT8 PcieNonSnoopLatencyOverrideMode[8]; + UINT8 PcieNonSnoopLatencyOverrideMultiplier[8]; + UINT8 PcieNonSnoopLatencyOverrideValue[8]; + + // PCI Bridge Resources + UINT8 ExtraBusRsvd[8]; + UINT16 PcieMemRsvd[8]; + UINT8 PcieMemRsvdalig[8]; + UINT16 PciePFMemRsvd[8]; + UINT8 PciePFMemRsvdalig[8]; + UINT8 PcieIoRsvd[8]; +// UINT8 ExtraBusRsv2[8]; + +#if HPET_SUPPORT + UINT8 Hpet; +#endif + UINT8 SlpS4AssW; + UINT8 LastState; + UINT8 Port80Route; + // Usb Config + UINT8 UsbPrecondition; + UINT8 PchUsb30Mode; +// UINT8 PchUsb30HsPortSwitchable[4]; + UINT8 PchEnableRmh1; + UINT8 PchUsb20[2]; + UINT8 PchUsbPerPortCtl; + UINT8 EhciConDisConWakeUp; + UINT8 PchUsbPort[14]; + UINT8 PchUsb30Port[6]; + UINT8 PchUsb30PreBootSupport; + UINT8 PchUsb30IdleL1; + UINT8 PchUsb30Btcg; + UINT8 PchUsb20PinRoute; + UINT8 ManualModeUsb20PerPinRoute[14]; + UINT8 PchUsb30PinEnable; + UINT8 ManualModeUsb30PerPinEnable[6]; +// UINT8 XhciStreams; + // Sata CONFIG + UINT8 PchSata; + UINT8 SataInterfaceMode; + UINT8 ULTSataInterfaceMode; + UINT8 SataTestMode; +#if SataDriver_SUPPORT + UINT8 SataRaidRom; +#endif + UINT8 SalpSupport; + UINT8 SataControllerSpeed; + UINT8 SataPort[6]; + UINT8 SataHotPlug[6]; + UINT8 ExternalSata[6]; + UINT8 SataMechanicalSw[6]; + UINT8 SolidStateDrive[6]; + UINT8 SataSpinUp[6]; + UINT8 SataDevSlp[4]; + UINT8 EnableDitoConfig[4]; + UINT8 DmVal[4]; + UINT16 DitoVal[4]; + UINT8 SataRaidR0; + UINT8 SataRaidR1; + UINT8 SataRaidR10; + UINT8 SataRaidR5; + UINT8 SataRaidIrrt; + UINT8 SataRaidOub; + UINT8 SataHddlk; + UINT8 SataLedl; + UINT8 SataRaidIooe; + UINT8 SmartStorage; + UINT8 OromUiDelay; + UINT8 SataAlternateId; + + // PCH Thermal + UINT8 AutoThermalReport; + UINT8 Ac1TripPoint; + UINT8 Ac0TripPoint; + UINT8 Ac0FanSpeed; + UINT8 Ac1FanSpeed; + UINT8 PassiveThermalTripPoint; + UINT8 CriticalThermalTripPoint; + UINT8 PassiveTc1Value; + UINT8 PassiveTc2Value; + UINT8 PassiveTspValue; + + UINT8 CPUTempReadEnable; + UINT8 CPUEnergyReadEnable; + UINT8 ThermalDeviceEnable; + UINT8 PchCrossThrottling; + UINT8 PCHTempReadEnable; + UINT8 AlertEnableLock; + UINT8 PchAlert; + UINT8 DimmAlert; + + UINT8 PchHotLevel; + UINT8 TPV_Restrict_Enable; + + UINT8 TrEnabled; + UINT8 TsOnDimm1; + UINT8 TsOnDimm2; + UINT8 TsOnDimm3; + UINT8 TsOnDimm4; + UINT8 SMBusECMsgLen; + UINT8 SMBusECMsgPEC; + // EC turbo control test mode + UINT8 ECTurboControlMode; + UINT8 ACBrickCapacity; + UINT8 ECPollingPeriod; + UINT8 ECGuardBandValue; + UINT8 ECAlgorithmSel; + UINT8 ECHybridPowerBoost; + UINT16 ECHybridCurrent; + UINT8 ECTG; + // CORE Setup + UINT8 AspmMode; + // PchLp LPSS + UINT8 LpssDmaEnable; + UINT8 LpssI2c0Enable; + UINT8 LpssI2c1Enable; + UINT8 LpssSpi0Enable; + UINT8 LpssSpi1Enable; + UINT8 LpssUart0Enable; + UINT8 LpssUart1Enable; + UINT8 LpssSdioEnable; + UINT8 LpssMode; + UINT8 LpssIntMode; + UINT8 I2C0VoltageSelect; + UINT8 I2C1VoltageSelect; + UINT8 SensorHub; + UINT8 TPD4; + UINT8 AtmelTPL; + UINT8 ElanTPL; + UINT8 ElanTPD; + UINT8 SynaTPD; + UINT8 NtriTPL; + UINT8 EetiTPL; + UINT8 AlpsTPD; + UINT8 CyprTPD; + UINT8 Bluetooth0; + UINT8 Bluetooth1; + + UINT16 I2C0SSH; + UINT16 I2C0SSL; + UINT16 I2C0SSD; + UINT16 I2C0FMH; + UINT16 I2C0FML; + UINT16 I2C0FMD; + UINT16 I2C0FPH; + UINT16 I2C0FPL; + UINT16 I2C0FPD; + UINT16 I2C0M0C0; + UINT16 I2C0M1C0; + UINT16 I2C0M2C0; + + UINT16 I2C1SSH; + UINT16 I2C1SSL; + UINT16 I2C1SSD; + UINT16 I2C1FMH; + UINT16 I2C1FML; + UINT16 I2C1FMD; + UINT16 I2C1FPH; + UINT16 I2C1FPL; + UINT16 I2C1FPD; + UINT16 I2C1M0C1; + UINT16 I2C1M1C1; + UINT16 I2C1M2C1; + + UINT16 SPI0M0C2; + UINT16 SPI0M1C2; + + UINT16 SPI1M0C3; + UINT16 SPI1M1C3; + + UINT16 UAR0M0C4; + UINT16 UAR0M1C4; + + UINT16 UAR1M0C5; + UINT16 UAR1M1C5; + + // PchLp Audio DSP + UINT8 ADspEnable; + UINT8 ADspD3PG; + UINT8 ADspCodecSelect; + UINT8 ADspBluetooth; + UINT8 ADspMode; + + UINT8 NFCE; +} SB_SETUP_DATA; + +#pragma pack(pop) + +VOID GetSbSetupData ( + IN VOID *Service, + IN OUT SB_SETUP_DATA *SbSetupData, + IN BOOLEAN Pei +); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Board/SB/sbBOARD.CIF b/Board/SB/sbBOARD.CIF new file mode 100644 index 0000000..891dbed --- /dev/null +++ b/Board/SB/sbBOARD.CIF @@ -0,0 +1,23 @@ +<component> + name = "Intel Pch SB Board" + category = ModulePart + LocalRoot = "Board\SB\" + RefName = "Intel Pch SB Board" +[files] +"SB.sdl" +"SB.mak" +"SBSECInit.asm" +"SBPEIBoard.c" +"SBDXEBoard.c" +"SB.H" +"HDAVBTBL.h" +"SBPEI.dxs" +"SBDXE.dxs" +"SBRun.dxs" +"SBPeiDebugger.c" +"GetSetupData.c" +"SbSetupData.h" +"Sb.ssp" +[parts] +"SBSetup" +<endComponent> |