init. 1AQQW051HEAD master

author: raywu <raywu0301@gmail.com> 2018-06-15 00:00:50 +0800
committer: raywu <raywu0301@gmail.com> 2018-06-15 00:00:50 +0800
commit: b7c51c9cf4864df6aabb99a1ae843becd577237c (patch)
tree: eebe9b0d0ca03062955223097e57da84dd618b9a /CRB
download: zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz
19 files changed, 6474 insertions, 0 deletions
diff --git a/CRB/CRB.mak b/CRB/CRB.mak
new file mode 100644
index 0000000..1531cb5
--- /dev/null
+++ b/CRB/CRB.mak
@@ -0,0 +1,267 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRB.mak 7     3/17/14 2:45a Chaseliu $
+#
+# $Revision: 7 $
+#
+# $Date: 3/17/14 2:45a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRB.mak $
+# 
+# 7     3/17/14 2:45a Chaseliu
+# Add CRBTse for EIP151535
+# 
+# 6     6/05/13 4:42a Thomaschen
+# Removing AMI_SEC_ROM before compile.
+# 
+# 4     4/16/13 5:19a Thomaschen
+# Modify for compile order.
+# 
+# 3     8/25/12 4:49a Wesleychen
+# Clear temp files by NMAKE-generated to avoid files overflow.
+# 
+# 2     2/24/12 8:54a Victortu
+# Use SharkBay RomImage module.
+# 
+# 1     2/12/12 10:38p Victortu
+# Intel SharkBay CRB initially releases.
+#
+#*************************************************************************
+#<AMI_FHDR_START>
+#
+# Name:         CRB.mak
+#
+# Description:  This make file builds Chipset Reference Board SEC,PEI & DXE
+#               components and link them to respective binary
+#
+#<AMI_FHDR_END>
+#*************************************************************************
+!IFNDEF PI_SPECIFICATION_VERSION
+PI_SPECIFICATION_VERSION = 0
+!ENDIF
+
+PREPARE : RemoveSecRom
+
+RemoveSecRom :
+  if exist $(AMI_SEC_ROM) del $(AMI_SEC_ROM)
+
+all : CRBPEI CRBDXE CRBSMI CRBCSPLibBin
+#following definitions moved in CRB.sdl as a Path Tokens
+BUILD_CRB_DIR = $(BUILD_DIR)\$(CRB_DIR)
+
+#----------------------------------------------------------------------------
+#           Generic CRB dependencies
+#----------------------------------------------------------------------------
+$(BUILD_DIR)\CRB.mak : $(CRB_DIR)\CRBoard.cif $(BUILD_RULES)
+    $(CIF2MAK) $(CRB_DIR)\CRBoard.cif $(CIF2MAK_DEFAULTS)
+
+#----------------------------------------------------------------------------
+#           Add files into CSP Library
+#----------------------------------------------------------------------------
+$(BUILD_DIR)\AMICSPLIBInc.H : $(CRB_DIR)\CRBLib.h
+AMICSPLibBin : $(CRBCSPLib)
+
+CRB_LIB_OBJECTS = $$(BUILD_DIR)\$(CRB_DIR)\CRBLib.obj
+
+$(CRBCSPLib) : $(BUILD_DIR)\Crb.mak CRBCSPLibBin
+
+CRBCSPLibBin :
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+        /f $(BUILD_DIR)\Crb.mak all\
+        NAME=AMICRBCSPLib\
+        MAKEFILE=$(BUILD_DIR)\Crb.mak\
+        OBJECTS="$(CRB_LIB_OBJECTS)"\
+        TYPE=LIBRARY
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+        /f $(BUILD_DIR)\Crb.mak all\
+        BUILD_DIR=$(BUILD_DIR)\IA32\
+        NAME=AMICRBCSPLib\
+        MAKEFILE=$(BUILD_DIR)\Crb.mak\
+        OBJECTS="$(CRB_LIB_OBJECTS)"\
+        TYPE=PEI_LIBRARY
+
+#----------------------------------------------------------------------------
+#           Add files for CRB SEC code
+#----------------------------------------------------------------------------
+CREATE_CRB_SEC : $(BUILD_DIR)\CRBSEC.OBJ
+
+CRB_SEC_ASM_FLAGS = /c /nologo /Sa
+!if "$(SEC_CREATE_PE32)" == "1"
+CRB_SEC_ASM_FLAGS = $(CRB_SEC_ASM_FLAGS) /coff
+!endif
+
+$(BUILD_DIR)\CRBSEC.OBJ : $(CRB_DIR)\CRBSEC.asm
+  $(ASM) $(CRB_SEC_ASM_FLAGS) /I$(CRB_DIR) /Fo$(BUILD_DIR)\CRBSEC.obj $(CRB_DIR)\CRBSEC.asm
+
+#----------------------------------------------------------------------------
+#       Create CRB PEI Component
+#----------------------------------------------------------------------------
+CRBPEI : $(BUILD_DIR)\CRB.mak CRBPEIBin
+
+CRB_PEI_OBJECTS = $(BUILD_CRB_DIR)\CRBPEI.obj
+
+CRBPEIBin : $(AMIPEILIB) $(AMICSPLib)
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+        /f $(BUILD_DIR)\CRB.mak all\
+        NAME=CRBPEI\
+        MAKEFILE=$(BUILD_DIR)\CRB.mak \
+        OBJECTS="$(CRB_PEI_OBJECTS)" \
+        GUID=0D1ED2F7-E92B-4562-92DD-5C82EC917EAE \
+        ENTRY_POINT=CRBPEI_Init \
+        TYPE=PEIM \
+        "CFLAGS=$(CFLAGS) /I$(NB_CHIPSET_DIR) /I$(NB_BOARD_DIR) /I$(SB_CHIPSET_DIR) /I$(SB_BOARD_DIR) $(INTEL_PCH_INCLUDES)"\
+        "EXT_HEADERS=$(BUILD_DIR)\token.h"\
+        DEPEX1=$(CRB_DIR)\CRBPEI.DXS DEPEX1_TYPE=EFI_SECTION_PEI_DEPEX \
+        COMPRESS=0
+
+# FILE GUID for CRBPEI BIN
+#// {0D1ED2F7-E92B-4562-92DD-5C82EC917EAE}
+#DEFINE_GUID(<<name>>, 
+#0xd1ed2f7, 0xe92b, 0x4562, 0x92, 0xdd, 0x5c, 0x82, 0xec, 0x91, 0x7e, 0xae);
+
+#----------------------------------------------------------------------------
+#       Create CRB DXE Component
+#----------------------------------------------------------------------------
+CRBDXE : $(BUILD_DIR)\CRB.MAK CRBDXEBin
+
+CRB_DXE_OBJECTS = $(BUILD_CRB_DIR)\CRBDXE.obj \
+
+CRBDXEBin : $(AMICSPLib) $(AMIDXELIB)
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+        /f $(BUILD_DIR)\CRB.mak all\
+        NAME=CRBDXE\
+        MAKEFILE=$(BUILD_DIR)\CRB.mak \
+        OBJECTS="$(CRB_DXE_OBJECTS)" \
+        GUID=16271FCA-55D9-4a33-93FC-5A3EB128DEB6 \
+        ENTRY_POINT=CRBDXE_Init \
+        "CFLAGS=$(CFLAGS) /I$(NB_CHIPSET_DIR) /I$(NB_BOARD_DIR) /I$(SB_CHIPSET_DIR) /I$(SB_BOARD_DIR)"\
+        "EXT_HEADERS=$(BUILD_DIR)\token.h"\
+        TYPE=BS_DRIVER \
+        DEPEX1=$(CRB_DIR)\CRBDXE.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \
+        COMPRESS=1
+
+# FILE GUID for CRBDXE BIN
+#// {16271FCA-55D9-4a33-93FC-5A3EB128DEB6}
+#DEFINE_GUID(<<name>>, 
+#0x16271fca, 0x55d9, 0x4a33, 0x93, 0xfc, 0x5a, 0x3e, 0xb1, 0x28, 0xde, 0xb6);
+
+#----------------------------------------------------------------------------
+#       Create CRB SMI Component
+#----------------------------------------------------------------------------
+CRBSMI : $(BUILD_DIR)\CRB.MAK CRBSMIBin
+
+CRB_SMI_OBJECTS = $(BUILD_CRB_DIR)\CRBSMI.obj
+
+CRBSMIBin : $(AMICSPLib) $(AMIDXELIB)
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+        /f $(BUILD_DIR)\CRB.mak all\
+        NAME=CRBSMI\
+        MAKEFILE=$(BUILD_DIR)\CRB.mak \
+        OBJECTS="$(CRB_SMI_OBJECTS)" \
+        GUID=221F1D4F-034C-4bea-B2BB-B7A9672B06D7 \
+        ENTRY_POINT=InitializeCRBSmm \
+        "CFLAGS=$(CFLAGS) /I$(NB_CHIPSET_DIR) /I$(NB_BOARD_DIR) /I$(SB_CHIPSET_DIR) /I$(SB_BOARD_DIR)"\
+        "EXT_HEADERS=$(BUILD_DIR)\token.h"\
+!IF $(PI_SPECIFICATION_VERSION) >= 0x1000A
+        TYPE=SMM_DRIVER \
+        DEPEX1=$(CRB_DIR)\CRBSMI.DXS \
+!ELSE
+        TYPE=BS_DRIVER \
+        DEPEX1=$(CRB_DIR)\CRBSMI.DXS DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \
+!ENDIF
+        COMPRESS=1
+
+# FILE GUID for CRBSMI BIN
+#// {221F1D4F-034C-4bea-B2BB-B7A9672B06D7}
+#DEFINE_GUID(<<name>>, 
+#0x221f1d4f, 0x34c, 0x4bea, 0xb2, 0xbb, 0xb7, 0xa9, 0x67, 0x2b, 0x6, 0xd7);
+
+#----------------------------------------------------------------------------
+#       Create CRB TSE Component
+#----------------------------------------------------------------------------
+AMITSEBin :  $(BUILD_DIR)\CRBTSE.obj
+
+CRBTSE_CFLAGS=$(CFLAGS) \
+	-I $(TSEBIN_DIR)\Inc \
+	-I $(TSEBIN_DIR)
+
+$(BUILD_DIR)\CRBTSE.obj : $(CRB_DIR)\CRBTse.c
+  	$(CC) $(CRBTSE_CFLAGS) /Fo$(BUILD_DIR)\CRBTSE.obj $(CRB_DIR)\CRBTse.c
+#----------------------------------------------------------------------------
+#		Create CRB ACPI Object
+#----------------------------------------------------------------------------
+$(BUILD_DIR)\CrbAcpi.obj: $(CRB_DIR)\CrbAcpi.c
+	$(CC) $(CFLAGS) /Fo$(BUILD_DIR)\ $(CRB_DIR)\CrbAcpi.c /I$(NB_CHIPSET_DIR) /I$(NB_BOARD_DIR) /I$(SB_CHIPSET_DIR) /I$(SB_BOARD_DIR)
+
+AcpiModeEnableBin: $(BUILD_DIR)\CrbAcpi.obj
+
+#----------------------------------------------------------------------------
+#       Create CRB Setup Screens
+#----------------------------------------------------------------------------
+SetupSdbs : $(BUILD_DIR)\CRB.mak CRBSDB
+SetupBin : $(BUILD_DIR)\CRBSetup.obj
+
+CRBSDB :
+    $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\
+        /f $(BUILD_DIR)\CRB.mak all\
+        TYPE=SDB NAME=CRB STRING_CONSUMERS=$(CRB_DIR)\CRB.sd
+
+$(BUILD_DIR)\CRBSetup.obj : $(CRB_DIR)\CRBSetup.c $(BUILD_DIR)\SetupStrTokens.h
+    $(CC) $(CFLAGS) /Fo$(BUILD_DIR)\ $(CRB_DIR)\CRBSetup.c
+
+#----------------------------------------------------------------------------
+#       Nested FV
+#----------------------------------------------------------------------------
+BEFORE_FV:
+	del $(BUILD_DIR)\FV_MAIN_NESTED__.ffs
+
+!IF $(LZMA_SUPPORT)
+FV_MAIN_CRB_DESCRIPTOR=FV(\
+name=FV_MAIN, address=$(FV_MAIN_BASE),\
+offset=$(FV_MAIN_BASE)-$(FLASH_BASE),\
+size=$(FV_MAIN_BLOCKS)*$(FLASH_BLOCK_SIZE),\
+!IF "$(FV_MAIN_NESTED)"!=""
+file_list=$(BUILD_DIR)\FV_MAIN_NESTED.ffs $(FV_MAIN_OUTSIDE_NESTED),\
+attr=ROM_AREA_FV_PEI+ROM_AREA_FV_DXE+ROM_AREA_FV_NFV_PRESENT+ROM_AREA_FV_SIGNED\
+!ELSE
+file_list=$(FV_MAIN),\
+attr=ROM_AREA_FV_PEI+ROM_AREA_FV_DXE+ROM_AREA_FV_SIGNED\
+!ENDIF
+)
+!ENDIF
+
+END: CLEAN_TEMP
+
+# Clean NMAKE-generated temporary files
+CLEAN_TEMP:
+    @if exist $(TEMP)\nm*.tmp del /F /S /Q $(TEMP)\nm*.tmp > NUL
+    @if exist $(TMP)\nm*.tmp del /F /S /Q $(TMP)\nm*.tmp > NUL  
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/CRB/CRB.sd b/CRB/CRB.sd
new file mode 100644
index 0000000..c89e7e1
--- /dev/null
+++ b/CRB/CRB.sd
@@ -0,0 +1,129 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRB.sd 2     1/11/13 3:23a Wesleychen $
+//
+// $Revision: 2 $
+//
+// $Date: 1/11/13 3:23a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRB.sd $
+// 
+// 2     1/11/13 3:23a Wesleychen
+// Clone  "SETUP_DATA.AcpiSleepState" and change its default value to "S3
+// only".
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:    CRB.sd
+//
+// Description: Chipset Reference Board setup form
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+#ifdef SETUP_DATA_DEFINITION
+//---------------------------------------------------------------------------
+// Put NVRAM data definitions here.
+// For example: UINT8 Data1;
+// These definitions will be converted by the build process
+// to a definitions of SETUP_DATA fields.
+//---------------------------------------------------------------------------
+    UINT8   CRBTest;
+
+#endif
+
+#if defined(VFRCOMPILE) && !defined(CONTROLS_ARE_DEFINED)
+#define CONTROL_DEFINITION
+#endif
+
+#ifdef CONTROL_DEFINITION
+
+#define CRB_CHECKBOX_CRBTEST\
+       checkbox varid  = SETUP_DATA.CRBTest,\
+         prompt = STRING_TOKEN(STR_CRBTEST_PROMPT),\
+         help = STRING_TOKEN(STR_CRBTEST_HELP),\
+         flags   = 1|RESET_REQUIRED,\
+       endcheckbox;
+
+#ifdef ACPI_ONEOF_ACPISLEEPSTATE
+#undef ACPI_ONEOF_ACPISLEEPSTATE
+#define ACPI_ONEOF_ACPISLEEPSTATE\
+       oneof varid  = SETUP_DATA.AcpiSleepState,\
+         prompt = STRING_TOKEN(STR_ACPI_SLEEP_PROMPT),\
+         help = STRING_TOKEN(STR_ACPI_SLEEP_HELP),\
+         option text = STRING_TOKEN(STR_ACPI_SLEEP_NO), value = 0, flags = RESET_REQUIRED;\
+         option text = STRING_TOKEN(STR_ACPI_SLEEP_S1), value = 1, flags = RESET_REQUIRED;\
+         option text = STRING_TOKEN(STR_ACPI_SLEEP_S3), value = 2, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;\
+         option text = STRING_TOKEN(STR_ACPI_SLEEP_AUTO), value = 3, flags = RESET_REQUIRED;\
+       endoneof;
+#endif // ACPI_ONEOF_ACPISLEEPSTATE
+
+#endif // CONTROL_DEFINITION
+
+#ifdef CONTROLS_WITH_DEFAULTS
+    CRB_CHECKBOX_CRBTEST
+#endif // CONTROLS_WITH_DEFAULTS
+//---------------------------------------------------------------------------
+//                ADVANCED - CRB Configuration Form
+//---------------------------------------------------------------------------
+#ifdef CRB_SETUP_DISPLAY
+#ifdef ADVANCED_FORM_SET
+    #ifdef FORM_SET_ITEM
+    // Define controls to be added to the main page of the formset
+    #endif
+
+
+
+    #ifdef FORM_SET_GOTO
+    // Define goto commands for the forms defined in this file
+        goto CRB_FORM_ID, 
+            prompt = STRING_TOKEN(STR_CRB_FORM),
+            help = STRING_TOKEN(STR_CRB_FORM_HELP);
+    #endif
+
+    #ifdef FORM_SET_FORM
+    // Define forms
+        form formid = AUTO_ID(CRB_FORM_ID),
+            title = STRING_TOKEN(STR_CRB_FORM);
+
+            CRB_CHECKBOX_CRBTEST
+
+        endform;  // CRB_FORM_ID
+
+    #endif  // FORM_SET_FORM
+
+#endif  // ADVANCED_FORM_SET
+#endif  // CRB_SETUP_DISPLAY
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRB.sdl b/CRB/CRB.sdl
new file mode 100644
index 0000000..a0cb143
--- /dev/null
+++ b/CRB/CRB.sdl
@@ -0,0 +1,3284 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRB.sdl 120   11/02/17 2:05a Chienhsieh $
+#
+# $Revision: 120 $
+#
+# $Date: 11/02/17 2:05a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRB.sdl $
+# 
+# 120   11/02/17 2:05a Chienhsieh
+# [TAG]  		EIP357568
+# [Description]  	[Aptio4][HSW series][SharkBay-DT] Modules
+# Update/Function implementation/Bug fixed on CRB051 project label
+# 
+# 119   7/31/17 4:51a Chienhsieh
+# [TAG]  		EIP344598
+# [Description]  	[HSW Series][SHB_DT] Modules Update/Function
+# implementation/Bug fixed on CRB050 project label
+# 
+# 118   2/10/17 1:43a Chienhsieh
+# [TAG]  		EIP316430
+# [Description]  	[Haswell Series] Modules Update/Function
+# implementation/Bug fixed on 'SharkBay DT' CRB049 project label
+# 
+# 117   8/08/16 4:19a Chienhsieh
+# 
+# 116   6/17/16 4:01a Chienhsieh
+# 
+# 115   4/20/16 1:47a Chienhsieh
+# 
+# 114   4/19/16 7:29a Chienhsieh
+# -Clone token, "RECOVERY_ROM"
+# -Clone token for ME capsule update support.
+# 
+# 113   10/02/15 4:28a Chienhsieh
+# 
+# 112   7/08/15 4:38a Chienhsieh
+# Enable tokan "SMM_COMMUNICATE_SUPPORT" for upgrade
+# 4.6.3_HddSecurity_029.
+# 
+# 111   2/02/15 12:01a Chienhsieh
+# 
+# 110   1/09/15 1:31a Chienhsieh
+# Set token "SMM_COMMUNICATE_SUPPORT" to Enable when NVMe module added.
+# 
+# 109   12/02/14 10:36p Chienhsieh
+# 
+# 108   11/18/14 5:10a Chienhsieh
+# -Clone token for EIP191080, "BootScriptHide_SUPPORT" and
+# "PchS3Support_SUPPORT".
+# -Add token "TRST" for "TCG2Support".
+# 
+# 107   7/15/14 9:57p Chienhsieh
+# 
+# 106   6/25/14 7:30a Chienhsieh
+# 
+# 105   4/16/14 6:35a Chaseliu
+# Update token "PROJECT_MINOR_VERSION" to "37".
+# Add TOKEN "MAX_CAPSULE_BLOCK_DESCRIPTOR_COUNT" for EIP163569.
+# 
+# 103   3/17/14 4:42a Chaseliu
+# Update token "PROJECT_MINOR_VERSION" to "36"
+# Add ELINK "GetSetupSataMode," for EIP151535
+# Add ELINK "CheckForChangeinSataMode," for EIP151535
+# Add ELINK "$(BUILD_DIR)\CRBTSE.obj" for EIP151535
+# 
+# 100   12/25/13 3:16a Chaseliu
+# [1AQQW035]
+# -Update token "PROJECT_MINOR_VERSION" to "35".
+# 
+# 99    11/08/13 1:31a Ireneyang
+# [1AQQW034]
+# -Update token "PROJECT_MINOR_VERSION" to "34".
+# 
+# 98    11/04/13 6:49a Ireneyang
+# [1AQQW033]
+# - Set token "POWERON_BUSY_CLEAR_TIMEOUT"
+#   to "30000" for EIP141871.
+# 
+# 97    10/30/13 7:15a Ireneyang
+# [1AWWQ033]
+# -Update GOP 5.0.1035.
+# 
+# 96    10/30/13 6:38a Ireneyang
+# [1AWWQ033]
+# -Modify token "CRB1_NB_PCI_DEVICES_SSID_TABLE" and 
+#  token "CRB2_NB_PCI_DEVICES_SSID_TABLE" for EIP140475
+# -Modify ELINK "UsbDevicePathTestSkip" to "MatchUefiFloppyDrive"
+#  for EIP139412. (Having same boot option in Setup Menu.)
+# -Set token "PTT_VER" to 16
+# -Set token "SUPPORT_RAID_DRIVER" to 0 as default.
+# 
+# 95    10/24/13 3:55a Ireneyang
+# -Fix EIP140411, USB and PS2 Keyboard can't work under Dos when
+#  including SIO module. Modify Token "KBC_SUPPORT" and 
+#  "ISA_IRQ_MASK" condition.
+# 
+# 94    9/17/13 10:42p Thomaschen
+# -Clone token "SSP5_PLD", "SSP6_PLD" and 
+#  mapping to "HS09_PLD" and "HS10_PLD".
+# 
+# 93    9/17/13 10:29p Thomaschen
+# [1AWWQ032]
+# -Remove condition of Token "KBC_SUPPORT" and "ISA_IRQ_MASK".
+# -Add token "SUPPORT_RAID_DRIVER" and set to 1.
+# -Remove token "CONNECT_ALL_DATA_DEVICE_IN_FASTBOOT".
+# -Add token "MAXIMUM_TIMEOUT_FOR_IBFREE".
+# -Add token "MATCH_BOOT_OPTION_BY_LOCATION" and set to 0.
+# -Add elink "IsbDevicePathTestSkip" for EIP109955.
+# 
+# 92    8/28/13 10:37p Thomaschen
+# -Remove token "FWpub", "FWpriv".
+# 
+# 91    8/26/13 2:41a Thomaschen
+# [1AQQW031]
+# 
+# 90    8/22/13 10:46p Thomaschen
+# [1AQQW030QARelease]
+# -Clone token "PRESERVE_SECURE_VARIABLES" and set it to enable.
+# 
+# 88    8/06/13 11:10p Thomaschen
+# -Clone token "TSE_ROMHOLE_SUPPORT" and set to 1 
+#  for BQA change logo test.
+# 
+# 87    8/02/13 3:54a Thomaschen
+# [1AQQW029]
+# -Add Token "FWpub", "FWpriv" for default platform FW signing key.
+# -Clone Elink "$(BUILD_DIR)\ROMHOLE.ffs" and set to 
+#  FV_MAIN_OUTSIDE_NESTED for BQA-Change Logo Test.
+# -Modify token "CRB2_SB_PCI_DEVICES_SSID_TABLE"(EIP129359).
+# -Modify condition of ELINK "$(BUILD_DIR)\FwCapsuleHdr.ffs".
+# -Add "XHCI_BUS_DEV_FUN" in token "CRB2_SB_PCI_DEVICES_SSID_TABLE"
+# -Follow SA 4.6.5.3_Intel_SA-RC_161_032b 
+#  update "OEM_INTEL_GOP_VBT_BIN_FILE" to 5.0.1033.
+# -Remove ELNIK of HSW C0 uCode "M32306C3_00000012.PDB".
+# 
+# 86    7/19/13 4:48a Thomaschen
+# -Add HSW C0 uCode: M32306C3_00000012.PDB.
+# -Remove Elink "CrbSetupCallbacks".
+# -Add Token "FIT_ENABLE" and modify
+#  Elink "$(BUILD_DIR)\FwCapsuleHdr.ffs" for EIP129437.
+# 
+# 85    7/16/13 8:01a Thomaschen
+# [1AQQW028]
+# 
+# 84    6/28/13 6:40a Thomaschen
+# Clone Token "REFLASH_UPDATE_BOOT_BLOCK" and set to 1.
+# Clone Token "SUPPORT_WIN8_STYLE_FW_UPDATE" and set to 1.
+# 
+# 82    6/25/13 8:15a Thomaschen
+# [1AQQW027]
+# 
+# 81    6/05/13 4:44a Thomaschen
+# [1AQQW026]
+#  -Add token "AMI_SEC_ROM".
+# 
+# 80    5/30/13 11:03p Thomaschen
+# -Add elink "CrbSetupCallbacks" for NB verb table modification.
+# 
+# 79    5/17/13 7:57a Thomaschen
+# -Update value of token "ACPI_ASL_COMPILER".
+# 
+# 78    5/13/13 11:27p Thomaschen
+# [1AQQW025]
+# 
+# 77    4/29/13 8:42a Thomaschen
+# -Clone token "AMI_DEBUG_RX_IN_S3_SUPPORT" and set to 1.
+# -Set "S3_BASE_MEMORY_SIZE" to 0x100000
+# -remove elink "ULT_FLAG"
+# For unique FW_VERSION_GUID
+#  -add Token "CRBCSPLib"
+#  -remove elink "$(BUILD_DIR)\CRBAcpi.obj" 
+# 
+# 74    4/17/13 2:38a Thomaschen
+# -Clone elink "ULT_FLAG" and remove the dependency.
+# 
+# 72    4/16/13 5:16a Thomaschen
+# [1AQQW024]
+# - Clone token "FW_VERSION_GUID" and set a unique one.
+# 
+# 71    4/12/13 6:44a Thomaschen
+# Clone token "SX_NOTIFY_PWRB" and set it to enable.
+# 
+# 70    4/09/13 7:55a Thomaschen
+# [1AQQW023]
+# -remove HSW C0 uCode: M32306C3_00000008.PDB.
+# 
+# 69    3/27/13 2:05a Thomaschen
+# [1AQQW022a]
+# -Clone Token "USE_RECOVERY_IMAGE_ON_FLASH_UPDATE" 
+#   and set to "0".
+# 
+# 68    3/21/13 9:19a Thomaschen
+# -Add HSW C0 uCode: M32306C3_00000008.PDB.
+# -Clone Token "TSEG_SIZE" and set to 16MB.
+# 
+# 67    3/18/13 8:23a Thomaschen
+# [1AQQW022]
+#   -Clone IODEVICE "Math Coprocessor" and disable it.
+# 
+# 
+# 65    2/26/13 5:39a Wesleychen
+# [1AQQW021]
+# 
+# 64    2/14/13 11:22p Wesleychen
+# [1AQQW020]
+#  - Added new token "AMI_SA_PATCH_FOR_CRB":
+#    Fixed that system may stops at CKP 0x55 after resume from S4/S5,
+#    fixed it by roll back to SA RC 0.8.1 for CRB only.
+#  - Following SA 4.6.5.3_Intel_SA-RC_110_025 update 
+#    "OEM_INTEL_GOP_VBT_BIN_FILE" to 5.0.1022.
+#  - Removed M32306C3_00000006.PDB due to updated
+#    Intel Nehalem Microcode to 4.6.0_INTEL_MICROCODE_47.
+#  - Add eLink "ASL_PCI0_INI" for Thunderbolt support.
+# 
+# 63    1/31/13 2:58a Wesleychen
+# Add HSW C0 uCode: M32306C3_00000006.PDB.
+# 
+# 60    1/18/13 2:43a Wesleychen
+#  - Set "IntelPTT_SUPPORT" = "0", SKB-DT doen't support.
+#  - Set "Dptf_SUPPORT" = "0", it is not SKB-DT POR.
+#    User can enable it if necessary.
+#  - Set "HARDWARE_SECURITY_INFO" = "1" to enable SMBIOS type 24
+#    for iSCT suppsort.
+#  - EIP#109000: SHB DT: eDP Stops Responding After Changing CSM Video
+#    OpRom policy, default is disabled. (OEM_INTEL_GOP_VBT_BIN_FILE)
+#  - Sync up GPIO settings with Intel BIOS v106 for SKB-DT CRB
+#    (Flathead Creek FAB2).
+#  - Remove "SHELL_TEXT_MODE".
+# 
+# 55    12/24/12 12:25a Wesleychen
+#  - Default disable "PfatServices_SUPPORT".
+#  - Enable ACPI S1 support.
+#  - For OFBD ME update:
+#    1. Change "OFBD_VERSION" to "0x210.
+#    2. Added target to .H in "CSP_MEUD_SUPPORT".
+#    3. Added "LYNX_POINT_CHIP".
+#  - Set "SHELL_TEXT_MODE" = 0 to solve the UEFI shell screen
+#    corruption symptom.
+# 
+# 49    11/13/12 4:29a Wesleychen
+#  - Update Core to 4.6.5.4.
+#  - Remove "DETECT_PS2_KEYBOARD", "DETECT_PS2_MOUSE" and
+#    "INSTALL_KEYBOARD_MOUSE_ALWAYS"
+#  - Adjust "FV_DATA_BASE", "FV_DATA_SIZE", "FV_BB_BLOCKS"
+#    and "FV_MAIN_BLOCKS".
+#  - Remove iFFS related tokens.
+# 
+# 47    10/22/12 7:55a Wesleychen
+#  - Disable "EcPs2Kbd_SUPPORT" if "SIO_SUPPORT" = "1".
+#  - Adjusted FV_BB_BLOCKS.
+# 
+# 43    10/08/12 10:07p Wesleychen
+#  - Add "FV_DATA_BASE" & "FV_DATA_SIZE" for FIT support.
+# 
+# 42    9/28/12 11:03a Wesleychen
+#  - Clone token "USB_PORT_LOCATION_CONFIG".
+#  - Remove AMI_RAPID_START_WORKAROUND"
+#    CRB.SDL; CRB.PEI
+#  - Remove "TRIM_ON_RESUME"
+# 
+# 39    9/13/12 5:48a Wesleychen
+#  - Set "AMI_RAPID_START_WORKAROUND" = 1.
+#    Improve iFFSresuming performance and
+#    fix iFFS RTC wake up fail issue.
+# 
+# 38    9/06/12 11:34a Wesleychen
+#  - Enable 60/64 decode for AMT IDER function.
+#    Set "KBC_SUPPORT" = "1".
+#    Set "ISA_IRQ_MASK" = "0xE307".
+#  - Configure GPIO_013 and GPIO_016 for CRB.
+#  - Set "SERIAL_RECOVERY_SUPPORT" = 0.
+#  - Hiding "Windows Boot Managet" when
+#    "Boot option filter" = "Legacyonly".
+#    Change "NON_FW_ORPHAN_BOOT_OPTIONS_POLICY" to
+#    "ORPHAN_BOOT_OPTIONS_POLICY_HIDE".
+#  - Improve iFFS performance.
+#  - Set "IGNORE_IMAGE_ROLLBACK" = 1.
+#  - Clone and set "DISABLE_PWR_BUTTON" = 1.
+#  - Cloned token "USB_OVER_CURRENT_MAPPING_SETTINGS".
+#  - Enable SecureFlash support.
+#  - Change "FV_BB_BLOCKS".
+#  - Clone and modify "NB_PCI_DEVICES_SSID_TABLE".
+#  - Clone and modify "SB_PCI_DEVICES_SSID_TABLE".
+#  - Set "CRB_CUSTOM_PPI_SUPPORT" = "0".
+#  - Change the default flash size in 4MB.
+#  - Fixed system cannot wakeup via RTC if iFFS is enable.
+#    (AMI_RAPID_START_WORKAROUND)
+# 
+# 25    8/20/12 4:43a Wesleychen
+#  - Change "FV_BB_BLOCKS".
+# 
+# 24    8/17/12 1:02a Wesleychen
+#  - Set "PMLN" = "0x100"
+#  - Set "GPLN" = "0x400"
+# 23    8/15/12 8:58a Wesleychen
+#  - Added flag "MI_ORIGINAL_FOR_INTEL_4390302".
+# 
+# 21    7/31/12 4:24a Wesleychen
+#  - Increase "FV_BB_BLOCKS" size when DEBUG_MODE = 1.
+#  - Remove and enable "LEGACYSREDIR_SUPPORT" and 
+#    "Terminal_SUPPORT" for IDER support.
+# 
+# 20    7/12/12 1:45a Wesleychen
+# Configure PCIE slots clock settings for Intel Flathead Creek
+# CRB.
+# 
+# 19    7/05/12 11:21a Wesleychen
+#  - Support Intel FIT.
+#  - Set SSID/SVID = 7270:8086.
+# 
+# 17    6/27/12 5:43a Wesleychen
+# Change flash size to 3MB when DEBUG_MODE = 1.
+# 
+# 16    6/21/12 11:50p Wesleychen
+#  - Set "GC_MODE0" = "{ 0, 80, 25, 0 , 0 }" for LOGO resolution.
+# 
+# 14    5/20/12 11:22p Wesleychen
+# Clone and set "S3_BUSY_CLEAR_TIMEOUT" = "32000".
+# 
+# 12    5/15/12 4:17a Wesleychen
+# 
+# 8     5/14/12 8:18a Wesleychen
+# Support CRB recovery jumper.
+# CRB.SDL; CRBLib.c
+# 
+# 6     5/04/12 11:54a Victortu
+# Default set "Thunderbolt_SUPPORT" disable.
+# 
+# 5     4/26/12 4:59a Victortu
+# - Correctly terminate the CRB1_NB_PCI_DEVICES_SSID_TABLE and
+# CRB2_NB_PCI_DEVICES_SSID_TABLE definitions in CRB.SDL.
+# - Include Haswell Microcode.
+# 
+# 3     3/28/12 2:31a Victortu
+# - Disable "BOARD_LABEL_BELOW_25"
+# - Set "S3_BASE_MEMORY_SIZE" to 0x80000
+# - Update "NVRAM_SIZE" to 0x20000
+# 
+# 2     2/24/12 9:04a Victortu
+# - Remove unused Microcode token.
+# - Support RomImage.
+# 
+# 1     2/12/12 10:38p Victortu
+# Intel SharkBay CRB initially releases.
+# 
+#*************************************************************************
+TOKEN
+	Name  = "CRB_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable Chipset Reference Board support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Master = Yes
+End
+
+TOKEN
+	Name  = "CRB_SWSMI"
+	Value  = "0xBF"
+	Help  = "Value to write into SMI command register to generate software SMI for CRB"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0 - 0xff"
+End
+
+TOKEN
+	Name  = "INCLUDE_CRB_ASM_FILE_IN_SEC"
+	Value  = "1"
+	Help  = "Includes an ASM file and an eLink in SEC build process for CRB code modification."
+	TokenType = Boolean
+End
+
+TOKEN
+	Name  = "PROJECT_MAJOR_VERSION"
+	Value  = "0"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "PROJECT_MINOR_VERSION"
+	Value  = "51"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "PROJECT_BUILD"
+	Value  = "$(PROJECT_MAJOR_VERSION)$(PROJECT_MINOR_VERSION)"
+	Help  = "Build Number and should be incremented with any new release."
+	TokenType = Expression
+	TargetMAK = Yes
+	Range  = "Maximum 3 digits"
+End
+
+TOKEN
+	Name  = "AMI_ROM"
+	Value  = "$(PROJECT_TAG)$(PROJECT_BUILD).rom"
+	Help  = "File name of the BIOS rom image"
+	TokenType = Expression
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "valid file name"
+End
+
+TOKEN
+	Name  = "AMI_SEC_ROM"
+	Value  = "$(PROJECT_TAG).rom"
+	Help  = "File name of the BIOS rom image"
+	TokenType = Expression
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "valid file name"
+End
+
+TOKEN
+	Name  = "RECOVERY_ROM"
+	Value  = "$(FWCAPSULE_FILE_NAME)"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PROJECT_TAG"
+	Value  = "1AQQW"
+	TokenType = Expression
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "FW_VERSION_GUID"
+	Value  = "{0x21422878, 0x7748, 0x4972, {0xab, 0xd1, 0x7f, 0x56, 0x5e, 0xc0, 0xbd, 0x4e}}"
+	Help  = "FW Version GUID inserted into Firmware ID structure.\FW version has to be overridden for every project."
+	TokenType = Expression
+	TargetH = Yes
+	Range  = "GUID"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+IODEVICE
+	Name  = "Math Coprocessor"
+	ASLfile  = "core\em\acpi\MATHCO.asl"
+	ASLdeviceName  = "MATH"
+  Disable = Yes
+End
+
+TOKEN
+	Name  = "====== CRB Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "CRB_HDA_VERB_TABLE_PRESENT"
+	Value  = "1"
+	Help  = "0 = Remove all CRB verb tables.\1 = Build up CRB verb tables.\WARNING: Veb might building error if verb table is not exist."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "AMI_SA_PATCH_FOR_CRB"
+	Value  = "1"
+	Help  = "Fixed that system may stops at CKP 0x55 after resume from S4/S5, fixed it by roll back to SA RC 0.8.1 for CRB only."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "EFIMebx_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable IccOverClocking support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "EFI_SPECIFICATION_VERSION" "<" "0x2000A"
+End
+
+TOKEN
+	Name  = "MebxSetupBrowser_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable IccOverClocking support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "EFI_SPECIFICATION_VERSION" "<" "0x2000A"
+End
+
+TOKEN
+	Name  = "Thunderbolt_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable Thunderbolt support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "Thunderbolt_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable Thunderbolt support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Token = "PciHotPlug_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "SX_NOTIFY_PWRB"
+	Value  = "1"
+	Help  = "Enable/Disable report notify power button event when system resume form sleep state."
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== CORE/BOARD Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "EFI_SPECIFICATION_VERSION"
+	Value  = "0x2001F"
+	Help  = "version of the supported EFI/UEFI specification:\0x2000A - UEFI 2.1\0x20014 - UEFI 2.2\0x2001E - UEFI 2.3\0x2001F - UEFI 2.3.1"
+	TokenType = Integer
+	TargetMAK = Yes
+	Range  = "0x2000A, 0x20014, 0x2001E, 0x2001F"
+End
+
+TOKEN
+	Name  = "PI_SPECIFICATION_VERSION"
+	Value  = "0x10014"
+	Help  = "version of the PI specification supported:\0x0005B - PI 0.91\0x10000 - PI 1.0\0x1000A - PI 1.1\0x10014 - PI 1.2"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Range  = "0x0005B, 0x10000, 0x1000A, 0x10014"
+End
+
+
+TOKEN
+	Name  = "Recovery_Time_Delay"
+	Value  = "8"
+	Help  = "Loop count to calculate the delay for Atapi Recovery"
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SETUP_BBS_POPUP_ENABLE"
+	Value  = "1"
+	Help  = "Enable or disable the SETUP_BBS_POPUP_ENABLE. CAUTION This works only if complete TSE sources are present."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "POPUP_MENU_SHOW_ALL_BBS_DEVICES"
+	Value  = "1"
+	Help  = "1 => Shows all BBS devices in BBS POPup menu. 0 => Shows only the first device of a BBS type in BBS POPUP menu."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "FLOPPY_CTRL_SUPPORT"
+	Value  = "0"
+	Help  = "Switch to enable ISA Floppy Controller support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "BEEP_ENABLE"
+	Value  = "0"
+	Help  = "This flag enables/disables all firmware beeps"
+	TokenType = Boolean
+End
+
+TOKEN
+	Name  = "BOOT_OPTION_TAG_PRIORITIES"
+	Value  = "BoTagLegacyCdrom, BoTagLegacyHardDisk, BoTagLegacyFloppy, BoTagLegacyEmbedNetwork, BoTagUefi, BoTagEmbeddedShell"
+	Help  = "List of value of type BOOT_OPTION_TAG that define priorities of the boot option tags.\BOOT_OPTION_TAG is defined in BdsBoard.c\"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "MM_LEGACY_RESERVE_MEM"
+	Value  = "0x8000000"
+	Help  = "DXE memory manager will try to keep memory in the range 0 - MM_LEGACY_RESERVE_MEM unallocated. \The memory in the range may still get allocated if the addresses in the range are specifically requested by \the AllocatePages calls, or if there is not enough free memory outside of the region to satisfy the request.\"
+	TokenType = Integer
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "KBC_SUPPORT"
+	Value  = "1"
+	Help  = "Enable/Disable KBC support"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+        Token = "ACPI_IA_BOOT_ARCH" "&" "2"
+End
+
+TOKEN
+	Name  = "ISA_IRQ_MASK"
+	Value  = "0xE307"
+	Help  = "This is an IRQ mask which may be used by ISA devices\ If BIT == 0 IRQ Available BIT == 1 IRQ Used.\DEFAULT VALUE == 0xE305."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0...0FFFFh"
+        Token = "CRB_SIO_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "REFLASH_UPDATE_BOOT_BLOCK"
+	Value  = "1"
+	Help  = "Enables/Disables update of the boot block flash area.\When REFLASH_INTERACTIVE is on and REFLASH_UPDATE_BOOT_BLOCK_CONTROL is on\this value can be overriden by the user using setup option."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SUPPORT_WIN8_STYLE_FW_UPDATE"
+	Value  = "1"
+	Help  = "Enables/Disables support for Win8-style firmware update"
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "NO_MMIO_FLASH_ACCESS_DURING_UPDATE"
+	Value  = "1"
+	Help  = "This token should be set to 1 if flash part is not memory mapped while write enabled."
+	TokenType = Boolean
+	TargetH = Yes
+	Token = "MEUD_SUPPORT" "=" "1"
+	Token = "CSP_MEUD_SUPPORT" "=" "1"
+	Token = "OFBD_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "TSEG_SIZE"
+	Value  = "0x1000000"
+	Help  = "Size of SMM TSEG area used (in bytes) \Default size 1MB."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TRST"
+	Value  = "2"
+	Help  = "Platform transition for PPI request under O.S. 0: None 1: Shutdown 2: Reboot 3: OS Vendor Specific"
+	TokenType = Integer
+	TargetASL = Yes
+	TargetH = Yes
+	Range  = "0 - 4"
+	Token = "TCG_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "TRST"
+	Value  = "2"
+	Help  = "Platform transition for PPI request under O.S. 0: None 1: Shutdown 2: Reboot 3: OS Vendor Specific"
+	TokenType = Integer
+	TargetASL = Yes
+	TargetH = Yes
+	Range  = "0 - 4"
+	Token = "TCG2Support" "=" "1"
+End
+
+TOKEN
+	Name  = "BOARD_LABEL_BELOW_25"
+	Value  = "0"
+	Help  = "Enable/Disable above 4.6.4.0_Board_25 eBoard control"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "S3_BUSY_CLEAR_TIMEOUT"
+	Value  = "32000"
+	Help  = "Timeout value for S3 busy clear. Set to 10 sec."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "POWERON_BUSY_CLEAR_TIMEOUT"
+	Value  = "30000"
+	Help  = "The Poweron busy clear timeout value. Set to 10 sec."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SETUP_HIDE_DISABLE_BOOT_OPTIONS"
+	Value  = "1"
+	Help  = "1 => Hide the disabled boot options in boot override menu. 0 => Shows all boot options boot override menu."
+	TokenType = Boolean
+	TargetH = Yes
+End
+TOKEN
+	Name  = "POPUP_MENU_HIDE_DISABLE_BOOT_OPTIONS"
+	Value  = "1"
+	Help  = "1 => Hide the disabled boot options in BBS POPup menu. 0 => Shows all boot options in BBS POPup menu."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "START_IN_NATIVE_RESOLUTION"
+	Value  = "0"
+	Help  = "When this token is 'on', Graphics console will start in native resolution if available"
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "USE_RECOVERY_IMAGE_ON_FLASH_UPDATE"
+	Value  = "0"
+	Help  = "If set to 1 system will boot using image provided in recovery capsule"
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== PCIE ROOT BRIDGE Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "AMI_ROOT_BRIDGE_SUPPORT"
+	Value  = "0"
+	Help  = "The switch to include/exclude AMI Native PCI Root Bridge Implementation.\Set this switch to 'OFF' when using 3rd party PCI Root Bridgr Driver."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PCI_EXPRESS_GEN2_SUPPORT"
+	Value  = "0"
+	Help  = "Enables / Disables Pci Bus Driver Native PCI Express Gen2 support"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== ME Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "IntelPTT_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable Intel PTT support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== DPTF Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = Dptf_SUPPORT
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Main switch to enable Dptf support in Project"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== OFBD Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "OFBD_VERSION"
+	Value  = "0x0210"
+	Help  = "OFBD Version"
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = CSP_MEUD_SUPPORT
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Main switch to enable ME Firmware Update Chipset function in Project"
+End
+
+TOKEN
+	Name  = "LYNX_POINT_CHIP"
+	Value  = "1"
+	TokenType = Integer
+	TargetH = Yes
+	Help  = "For Caculating Flash Capacity."
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== TSE Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "SETUP_PASSWORD_NON_CASE_SENSITIVE"
+	Value  = "0"
+	Help  = "Allow to use of case sensitive password. Note:This token should be OFF with SETUP_STORE_KEYCODE_PASSWORD value 1 or 2."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "EDK_1_05_RETRIEVE_DATA"
+	Value  = "0"
+	Help  = "Modified code to return BrowserCallback String according to either EDK browser or spec. Please be careful when to change this to 0, May cause Addon Card to not to work."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "EFI_SPECIFICATION_VERSION" ">=" "0x2000A"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== Intel PFAT Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "PfatServices_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH   = Yes
+	Help  = "Main switch to enable Pfat support in Project, needs NvramSmiSupport Enabled"
+	Token = "NvramSmiSupport" "=" "1"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== Secure Boot and Flash Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "FWCAPSULE_FILE_FORMAT"
+	Value  = "0"
+	Help  = "0 - Include Aptio FW Signature Block inside the AMI.ROM as a ROM Hole Ffs file\1 - Generate Signed Aptio FW Capsule file. The file will be used for Protected Flash Updates and as default Recovery image"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "IGNORE_IMAGE_ROLLBACK"
+	Value  = "1"
+	Help  = "When set, FW Capsule Validate logic will skip image Revision check"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "FWSIG_SIGNHDR"
+	Value  = "0"
+	Help  = "Fw Signature Calculation scheme\0-Use in Secure Flash Module labels 000 to 008. Only Rom Image and RomMap are signed\1-Use in Secure Flash Module label 009 and onwards. Add FwCap hdr into a signature calculation"
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "FWSIG_SIGNHDR"
+	Value  = "1"
+	Help  = "Fw Signature Calculation scheme\0-Use in Secure Flash Module labels 000 to 008. Only Rom Image and RomMap are signed\1-Use in Secure Flash Module label 009 and onwards. Add FwCap hdr into a signature calculation"
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "FWCAPSULE_FILE_FORMAT" "=" "0"
+End
+
+TOKEN
+	Name  = "SERIAL_RECOVERY_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN   #[EIP163569]
+	Name  = "MAX_CAPSULE_BLOCK_DESCRIPTOR_COUNT"
+	Value  = "100"
+	Help  = "Maximum number of capsule block descriptors"
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== ACPI Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "S3_BASE_MEMORY_SIZE"
+	Value  = "0x100000"
+	Help  = "Number of bytes for S3 resume base memory."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0x40000 = 256K,, increase/decrease it in units of 0x1000 = 4K"
+End
+
+TOKEN
+	Name  = "S3_VIDEO_REPOST_SUPPORT"
+	Value  = "1"
+	Help  = "Switch to enable/disable S3 video repost support."
+	TokenType = Boolean
+	TargetH = Yes
+	Token = "CSM_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "ACPI_PM_PROFILE"
+	Value  = "1"
+	Help  = "Power Management Profile ACPI 2.0\See acpi20.h"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0-6 0 = Unspecified; 1 = Desktop; 2 = Modile; 3 = Workstation; 4 = Enterprise Server; 5 = SOHO Server; 6 = Application PC"
+	Token = "ACPI_BUILD_TABLES_2_0" "=" "1"
+End
+
+TOKEN
+	Name  = "MPS_TABLE_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable MPS V 1.4 Table support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "CSM_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "ACPI_IA_BOOT_ARCH"
+	Value  = "0003h"
+	Help  = "IA Boot Architecture\this token may be 'ored' see renge field for details"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "1 - IA_LEGACY; 2 - IA_8042; 4 - VGA Not Present; 8 - MSI Not Supported; 10h - PCIe ASPM Controls"
+	Token = "ACPI_BUILD_TABLES_2_0" "=" "1"
+End
+
+TOKEN
+	Name  = "ACPI_ASL_COMPILER"
+	Value  = "$(AcpiPlatform_DIR)\iasl.exe"
+	Help  = "ASL Optimizing Compiler version 20120711-32 [Jul 11 2012]"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "ACPI_INT_MODEL"
+	Value  = "0"
+	Help  = "Interrupt Model for the ACPI system"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0=Dual PIC; 1=Mult APIC; 2=Mult SAPIC "
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== Nested Firmware Volume Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "LZMA_SUPPORT"
+	Value  = "1"
+	Help  = "Enables/Disables LZMA compression support"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\Microcode.ffs"
+	Parent  = "FV_MAIN_OUTSIDE_NESTED"
+	Token = "LZMA_SUPPORT" "=" "1"
+	Token = "Microcode_SUPPORT" "=" "1"
+	InvokeOrder = BeforeParent
+End
+ 
+ELINK
+	Name  = "$(BUILD_DIR)\S3Restore.ffs"
+	Parent  = "FV_MAIN_OUTSIDE_NESTED"
+	Token = "LZMA_SUPPORT" "=" "1"
+	Token = "ACPI_SUPPORT" "=" "1"
+	Token = "S3Restore_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+ 
+ELINK
+	Name  = "$(FV_MAIN_CRB_DESCRIPTOR)"
+	Parent  = "$(FV_MAIN_DESCRIPTOR)"
+	Token = "LZMA_SUPPORT" "=" "1"
+	InvokeOrder = ReplaceParent
+End
+ 
+ELINK
+	Name  = "$(FV_MAIN)"
+	Parent  = "FV_MAIN_NESTED"
+	Token = "LZMA_SUPPORT" "=" "1"
+	InvokeOrder = AfterParent
+End
+ 
+ELINK
+	Name  = "FV_MAIN_OUTSIDE_NESTED"
+	InvokeOrder = ReplaceParent
+	Token = "LZMA_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== FLASH SIZE Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "FAULT_TOLERANT_NVRAM_UPDATE"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Lock = Yes
+End
+
+TOKEN
+	Name  = "NVRAM_RT_GARBAGE_COLLECTION_SUPPORT"
+	Value  = "1"
+	Help  = "This token enables/disables support of the NVRAM garbage collection at runtime."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "FLASH_SIZE_SELECTION"
+	Value  = "4"
+	Help  = "Flash size selection 0=1MB, 1=2MB, 2=2.5MB 3=3MB 4=4MB"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "0-4"
+End
+
+TOKEN
+	Name  = "FLASH_SIZE_SELECTION"
+	Value  = "4"
+	Help  = "Flash size selection 0=1MB, 1=2MB, 2=2.5MB 3=3MB 4=4MB"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "0-4"
+	Token = "DEBUG_MODE" "=" "1"
+End
+
+TOKEN
+	Name  = "FLASH_BLOCK_SIZE"
+	Value  = "0x1000"
+	Help  = "Size of the Flash Device Block"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "FLASH_SIZE"
+	Value  = "0x200000"
+	Help  = "Size of the Flash Device in bytes"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "FLASH_SIZE_SELECTION" "=" "1"
+End
+
+TOKEN
+	Name  = "FLASH_SIZE"
+	Value  = "0x280000"
+	Help  = "Size of the Flash Device in bytes"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "FLASH_SIZE_SELECTION" "=" "2"
+End
+
+TOKEN
+	Name  = "FLASH_SIZE"
+	Value  = "0x300000"
+	Help  = "Size of the Flash Device in bytes"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "FLASH_SIZE_SELECTION" "=" "3"
+End
+
+TOKEN
+	Name  = "FLASH_SIZE"
+	Value  = "0x400000"
+	Help  = "Size of the Flash Device in bytes"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "FLASH_SIZE_SELECTION" "=" "4"
+End
+
+TOKEN
+	Name  = "NVRAM_SIZE"
+	Value  = "0x20000"
+	Help  = "Size of NVRAM area"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 1 To: FLASH_SIZE - FV_MAIN_BLOCKS*FLASH_BLOCK_SIZE"
+End
+
+TOKEN
+	Name  = "NVRAM_BLOCKS"
+	Value  = "($(NVRAM_SIZE)/$(FLASH_BLOCK_SIZE))"
+	Help  = "Number of Blocks occupied by the NVRAM"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 1  To :FLASH_SIZE/FLASH_BLOCK_SIZE-1"
+End
+
+TOKEN
+	Name  = "NVRAM_ADDRESS"
+	Value  = "(0xFFFFFFFF-$(FLASH_SIZE)+1)"
+	Help  = "Starting address of the NVRAM flash area"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 4G - FLASH_SIZE To: 4G"
+End
+
+TOKEN
+	Name  = "NVRAM_BACKUP_ADDRESS"
+	Value  = "$(NVRAM_ADDRESS)+$(NVRAM_SIZE)"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "OEM_NCB_ADDRESS"
+	Value = "$(NVRAM_ADDRESS)+$(NVRAM_SIZE)*2"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "OEM_NCB_SIZE"
+	Value = "0x10000"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "OEM_NCB_BLOCKS"
+	Value  = "($(OEM_NCB_SIZE)/$(FLASH_BLOCK_SIZE))"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 1  To :FLASH_SIZE/FLASH_BLOCK_SIZE-1"
+End
+
+TOKEN
+	Name  = "FV_DATA_BASE"
+	Value  = "$(FV_BB_BASE)-$(FV_DATA_SIZE)"
+	Help  = "Base Address of the FV_DATA"	
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "INTEL_FIT_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "FV_DATA_SIZE"
+	Value = "0x20000"
+	Help  = "The size of FV_DATA is 64KB"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "INTEL_FIT_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "FV_BB_BLOCKS"
+	Value  = "12*(0x10000/$(FLASH_BLOCK_SIZE))"
+	Help  = "Number of Blocks occupied by the FV_BB"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 1  To :FLASH_SIZE/FLASH_BLOCK_SIZE-1"
+End
+
+TOKEN
+	Name  = "FV_BB_BLOCKS"
+	Value  = "18*(0x10000/$(FLASH_BLOCK_SIZE))"
+	Help  = "Number of Blocks occupied by the FV_BB"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 1  To :FLASH_SIZE/FLASH_BLOCK_SIZE-1"
+	Token = "DEBUG_MODE" "=" "1"
+End
+
+TOKEN
+	Name  = "FV_BB_BASE"
+	Value  = "(0xFFFFFFFF-$(FV_BB_BLOCKS)*$(FLASH_BLOCK_SIZE)+1)"
+	Help  = "Base Address of the FV_BB"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 4G - FLASH_SIZE To: 4G"
+End
+
+TOKEN
+	Name  = "FV_MAIN_BASE"
+	Value  = "$(OEM_NCB_ADDRESS)+$(OEM_NCB_SIZE)"
+	Help  = "Base Address of the FV_MAIN"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 4G - FLASH_SIZE To: 4G"
+End
+
+TOKEN
+	Name  = "FV_MAIN_BLOCKS"
+	Value  = "($(FV_BB_BASE)-$(FV_MAIN_BASE))/$(FLASH_BLOCK_SIZE)"
+	Help  = "Number of Blocks occupied by the FV_MAIN"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 1  To :FLASH_SIZE/FLASH_BLOCK_SIZE-1"
+End
+
+TOKEN
+	Name  = "FV_MAIN_BLOCKS"
+	Value  = "($(FV_DATA_BASE)-$(FV_MAIN_BASE))/$(FLASH_BLOCK_SIZE)"
+	Help  = "Number of Blocks occupied by the FV_MAIN"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "From: 1  To :FLASH_SIZE/FLASH_BLOCK_SIZE-1"
+	Token = "INTEL_FIT_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "OEM_ACTIVATION_TABLE_SIZE"
+	Value  = "$(OEM_NCB_SIZE)"
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "OEM_ACTIVATION_TABLE_LOCATION" "=" "1"
+End
+
+TOKEN
+	Name  = "OEM_ACTIVATION_TABLE_ADDRESS"
+	Value = "$(OEM_NCB_ADDRESS)"
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "OEM_ACTIVATION_TABLE_LOCATION" "=" "1"
+End
+
+TOKEN
+	Name  = "CAR_BASE_ADDRESS"
+	Value  = "0xFFFFFFFF - $(FLASH_SIZE) - 0x100000 + 1"
+	Help  = "DO NOT CHANGE THIS VALUE.\Cache-as-RAM physical base location"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SPI_INITIALIZE_WITH_VSCC"
+	Value  = "1"
+	Help  = "Program Host Lower/Upper Vendor Specific Component Capabilities Register."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== Status Code Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== North Bridge Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "ENABLE_FHC_EDP_SUPPORT"
+	Value  = "0"
+	Help  = "Enables/Disables CRB eDP support."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "OEM_INTEL_GOP_VBT_BIN_FILE"
+	Value  = "$(CRB_DIR)\VBT_5.0.1035_FC.BIN"
+	TokenType = Expression
+	TargetMAK = Yes
+	Token = "ENABLE_FHC_EDP_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== South Bridge Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "PCH_SKU"
+	Value  = "0"
+	Help  = "0:Desktop\1:Mobile"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CLOCK_GENERATOR_ADDRESS"
+	Value  = "0xFF"
+	Help  = "Clock generator address. Set to 0xFF to disable\clock generator programming."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "USB_OVER_CURRENT_MAPPING_SETTINGS"
+	Value  = "0, 0, 1, 8, 8, 2, 3, 3, 4, 4, 5, 5, 6, 6"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "USB_PORTS_LENGTH"
+	Value  = "0x80, 0x80, 0x100, 0x100, 0x80, 0x80, 0x80, 0x80, 0x100, 0x100, 0x140, 0x140, 0x80, 0x80"
+	Help  = "0x33 = 3.3 inch, 0x146 = 14.6 inch ...."
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "USB_PORT_LOCATION_CONFIG"
+	Value  = "1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1"
+	Help  = "BIT0 = Port0; BIT1 = Port1 ... ; BIT13 = Port13\0:BackPanel\1:FrontPanel\2:Dock\3:MiniPciE\4:Flex\5:InternalTopology\6:Skip\7:Max"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SERIAL_STATUS_SUPPORT"
+	Value  = "1"
+	Help  = "Enables/Disables serail port status code routine"
+	TokenType = Boolean
+	TargetH = Yes
+	Token = "STRING_STATUS_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "PMLN"
+	Value  = "0x100"
+	Help  = "Power Management registers block length"
+	TokenType = Integer
+	TargetASL = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "GPLN"
+	Value  = "0x400"
+	Help  = "GP I/O Registes Range"
+	TokenType = Integer
+	TargetASL = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== Fast Boot Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "SUPPORT_RAID_DRIVER"
+	Value  = "0"
+	Help  = "Check if support for raid driver."
+	TokenType = Boolean
+	TargetH = Yes
+	Token = "FAST_BOOT_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "FAST_BOOT_PCI_SKIP_LIST"
+	Value  = "{{0x01,0xFF},{0x03,0xFF},{0x06,0xFF}}"
+	Help  = "Help  = '(EIP85135)When enabled XHCI support difficult into setup menu in fastboot mode'\{ClassCode,SubClassCode}\{0x01,0xFF}  Storage\{0x02,0xFF}  NetWrok\{0x03,0xFF}  VGA\{0x06,0xFF}  Bridge"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== SMIFlash Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "DISABLE_PWR_BUTTON"
+	Value  = "1"
+	Help  = "1 - Disable PWR Button when flashing BIOS in DOS."
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== CPU Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "x64_BUILD"
+	Value  = "1"
+	Help  = "Main switch to enable x64 support in Project\DO REBUILD ALL AFTER CHANGING THIS SWITCH!!!"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "MICROCODE_SPLIT_BB_UPDATE"
+	Value  = "1"
+	Help  = "If enabled, \ a) Microcode added at build time is stored in boot block.\ b) Microcode updates by INT15h are stored in the main firmware volume.\If disabled, all microcode is in the main firmware volume.\\If enabled, microcode is more fault tolerant, but requires more flash space.\"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DESKTOP"
+	Value = "1"
+	Help  = "Master Desktop CPU uCode Enable"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Range  = "On-Off"
+End
+
+TOKEN
+	Name  = "NON_PRODUCTION_MICROCODE"
+	Value  = "1"
+	Help  = "Enable Non-production Microcode"
+	TokenType = Boolean
+End
+
+TOKEN
+	Name  = "DESKTOP_306CX"
+	Value = "1"
+	Help  = "Intel(R) Haswell"
+	TokenType = Boolean
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== SMBIOS Data Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "SMBIOS_PI_1_1"
+	Value  = "1"
+	Help  = "SMBIOS PI 1.1 Support"
+	TokenType = Boolean
+	TargetH = Yes
+	Token = "PI_SPECIFICATION_VERSION" ">=" "0x10000"
+End
+
+TOKEN
+	Name  = "CPU_MODULE_CREATE_SMBIOS_TABLES"
+	Value  = "1"
+	Help  = "Enable for CPU Module. Also, disable token PROCESSOR_INFO.\Disable for SMBIOS module.\\\"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PROCESSOR_INFO"
+	Value  = "0"
+	Help  = "ON  -> Processor Information (Type 4) structure will be present\OFF -> Processor Information (Type 4) structure will not be present\The number of CPU is defined in CPU.SDL as NCPU.\Total number of processors will be NCPU ( specified in CPU.SDL) \Currenty there is support for 4 Processors. \To support more processores modify in SMBDESC.DEF and SMBIOS.SDL"
+	TokenType = Boolean
+	TargetEQU = Yes
+	Lock = Yes
+	Token = "CPU_MODULE_CREATE_SMBIOS_TABLES" "=" "1"
+End
+
+TOKEN
+	Name  = "NUMBER_OF_PROC_CACHE"
+	Value  = "0"
+	Help  = "Number of Processor Cache Present.\NOTE: DO NOT CHANGE THE VALUE."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Lock = Yes
+	Range  = "1-8"
+	Token = "CPU_MODULE_CREATE_SMBIOS_TABLES" "=" "1"
+End
+
+TOKEN
+	Name  = "BIOS_SIZE"
+	Value  = "$(FLASH_SIZE)"
+	TokenType = Integer
+	TargetEQU = Yes
+End
+
+TOKEN
+	Name  = "BASE_BOARD_INFO"
+	Value  = "1"
+	Help  = "ON  -> BaseBoard Information (Type 2) structure will be present\OFF -> BaseBoard Information (Type 2) structure will not be present\"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "BASE_BOARD_MANUFACTURER"
+	Value  = "$(DEFAULT_STRING)"
+	Help  = "Specifies the Board Manufacturer."
+	TokenType = Expression
+	TargetEQU = Yes
+	Token = "BASE_BOARD_INFO" "=" "1"
+End
+
+TOKEN
+	Name  = "BASE_BOARD_PRODUCT_NAME"
+	Value  = "$(DEFAULT_STRING)"
+	Help  = "Specifies the Product Name"
+	TokenType = Expression
+	TargetEQU = Yes
+	Token = "BASE_BOARD_INFO" "=" "1"
+End
+
+TOKEN
+	Name  = "NO_OF_PHYSICAL_MEMORY_ARRAY"
+	Value  = "0"
+	Help  = "Specifies the Total number of Physical Arrays in the System."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+	Range  = "1 - 5"
+	Token = "UpdateMemoryRecord_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "MEMORY_DEVICE_INFO"
+	Value  = "0"
+	Help  = "ON   -> Memory Device Mapped Address Information (Type 20) structures will be present.\OFF  -> Memory Device Mapped Address Information (Type 20) structures will not be present."
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+	Token = "UpdateMemoryRecord_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "VOLTAGE_PROBE_INFO"
+	Value  = "1"
+	Help  = "ON  -> Voltage Probe Information (Type 26) structure will be present\OFF -> Voltage Probe Information (Type 26) structure will not be present"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "COOLING_DEVICE_INFO"
+	Value  = "1"
+	Help  = "ON  -> Cooling Device Information (Type 27) structure will be present\OFF -> Cooling Device Information (Type 27) structure will not be present"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TEMPERATURE_PROBE_INFO"
+	Value  = "1"
+	Help  = "ON  -> Temperature Probe Information (Type 28) structure will be present\OFF -> Temprature Probe Information (Type 28) structure will not be present"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "ELECTRICAL_PROBE_INFO"
+	Value  = "1"
+	Help  = "ON  -> Electrical Probe Information (Type 29) structure will be present\OFF -> Electrical Probe Information (Type 29) structure will not be present"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "MANAGEMENT_DEVICE_INFO"
+	Value  = "1"
+	Help  = "ON  -> Management Device Information (Type 34) structure will be present\OFF -> Management Device Information (Type 34) structure will not be present"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "NUMBER_OF_MANAGEMENT_DEVICES"
+	Value  = "1"
+	Help  = "Number of Management Devices in the System."
+	TokenType = Integer
+	TargetEQU = Yes
+End
+
+TOKEN
+	Name  = "SYSTEM_POWER_SUPPLY_INFO"
+	Value  = "1"
+	Help  = "Type 39 - System Power Supply\OFF -> System Power Supply will not be Present\ON  -> System Power Supply will be Present"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SMBIOS_TYPE_4_PROC_UPGRADE"
+	Value  = "0x24"
+	Help  = "0x21 - Mobile Sandy Bridge - Socket rPGA988B\0x22 - Mobile Sandy Bridge - Socket BGA1023\0x23 - Mobile Sandy Bridge - Socket LGA1224\0x24 - Sandy Bridge DT      - Socket LGA1155 \0x25 - Sandy Bridge-EN      - Socket LGA1356\0x26 - Sandy Bridge-EP      - Socket LGA2012"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0-ff"
+End
+
+TOKEN
+	Name  = "SMBIOS_TYPE_4_MAX_SPEED"
+	Value  = "3800"
+	Help  = "Value in MHz."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0-ffff"
+End
+
+TOKEN
+	Name  = "HARDWARE_SECURITY_INFO"
+	Value  = "1"
+	Help  = "ON  -> Hardware Security Information (Type 24) structure will be present\OFF -> Hardware Security Information (Type 24) structure will not be present"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+	Token = "ISCT_PLATFORM_SUPPORT" "=" "1"
+End
+
+TOKEN
+    Name  = "DEFAULT_STRING"
+    Value  = "Default string"
+    Help  = "Default unported strings in Smbios static table"
+    TokenType = Expression
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== Debug Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "RESERVED_PAGE_ROUTE"
+	Value  = "0"
+	Help  = "0 - Forward to LPC.\1 - Forward to PCI.\Please refer to RCBA#3410h[2]."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DEBUG_MODE"
+	Value  = "0"
+	Help  = "Main switch to control debugging features.\If this switch is set to off, all debugging capabilities are disabled.\If this switch is set to on, the following SDL tokens can be used to fine-tune debugging capabilities:\OPTIMIZATION, DEBUG_CODE, DEBUG_INFO."
+	TokenType = Boolean
+	TargetMAK = Yes
+	Range  = "0 - 1"
+End
+
+TOKEN
+	Name  = "OPTIMIZATION"
+	Value  = "1"
+	Help  = "Once DEBUG_MODE is on, this swtich is used to control compiler and linker optimization.\If DEBUG_MODE is set to off, this switch is ignored and optimization is enabled."
+	TokenType = Boolean
+	TargetMAK = Yes
+	Token = "DEBUG_MODE" "=" "1"
+End
+
+TOKEN
+	Name  = "DEBUG_SWITCH"
+	Value  = "0"
+	TokenType = Boolean
+	TargetH = Yes
+	Token = "DEBUG_MODE" "=" "1"
+End
+
+TOKEN
+	Name  = "MRC_DEBUG_PRINT_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "DEBUG_MODE" "=" "1"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== Debug Rx Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "AMIDEBUG_RX_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable Ami Debug Rx Module."
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "AMI_DEBUGGER_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable AMI Debugger support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "AMI_DEBUG_RX_IN_S3_SUPPORT"
+	Value  = "1"
+	Help  = "SDL token to have AMI Debug RX support in S3 Resume. "
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "AMI_DEBUGGER_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "S3_BASE_MEMORY_SIZE"
+	Value  = "0x400000"
+	Help  = "Number of bytes for S3 resume base memory."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0x40000 = 256K, increase/decrease it in units of 0x1000 = 4K"
+	Token = "AMIDEBUG_RX_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "S3_BASE_MEMORY_SIZE"
+	Value  = "0x400000"
+	Help  = "Number of bytes for S3 resume base memory."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0x40000 = 256K, increase/decrease it in units of 0x1000 = 4K"
+	Token = "DEBUG_MODE" "=" "1"
+End
+
+TOKEN
+	Name  = "DEBUG_RX_FFS_IN_FVMAIN_SUPPORT"
+	Value  = "0"
+	Help  = "SDL token to have Debugger related ffs in FV_MAIN or FV_BB. "
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "LZMA_SUPPORT" "=" "1"
+	Token = "AMI_DEBUGGER_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== SMM Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "SMM_COMMUNICATE_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable SmmBase support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Token = "PI_SPECIFICATION_VERSION" ">=" "0x1000A"
+End
+
+TOKEN
+	Name  = "SMM_COMMUNICATE_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable SmmBase support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Token = "PI_SPECIFICATION_VERSION" ">=" "0x1000A"
+	#Token = "NVMe_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "SMM_PAGING_MAX_ADDRESS_LINES"
+	Value  = "36"
+	Help  = "For x64, maximum number of address lines to page.\Each additional line doubles the page table size."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== RomImage Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "SELECT_BUILD_PLATFORM"
+	Value  = "1"
+        Help  = "0:User define\1:Desktop\2:Mobile\3:WorkStation\4:ULT"
+	TokenType = Integer
+	TargetMAK = Yes
+	Range  = "0-4"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== CSM Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "LegacyInterrupt_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable LegacyInterrupt support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Lock = Yes
+	Token = "IntelLegacyInterrupt_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "LegacyRegion_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable LegacyRegion support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Lock = Yes
+	Token = "SaInitDxe_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "PMM_EBDA_LOMEM_SIZE"
+	Value  = "0x40000"
+	Help  = "Amount of memory below 1MB in bytes to be allocated for EBDA and PMM. This size should be a multiple of 32K.\Value should not exceed 512 KB, the remaining part of 640K will be given to IVT, BDA, non-BBS compliant OpROMs. It can also be allocated by other EFI drivers, used for PCI3.0 OpROM execution, etc.\Recommended value is 128 KB."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PMM_LOMEM_SIZE"
+	Value  = "0x20000"
+	Help  = "The total amount of memory below 1MB available for PMM allocations, in bytes. This size should be a multiple of 32K.\Value should not exceed PMM_EBDA_LOMEM_SIZE as the remaining part of it will be given for EBDA."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== CsmOptOut Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "DEFAULT_PXE_OPROM_POLICY"
+	Value  = "0"
+	Help  = "Default value of Launch PXE OpROM policy setup control"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0 - Do not launch, 1 - Launch UEFI OpROM only, 2 - Launch Legacy OpROM only, 3 - Launch Legacy before UEFI, 4 - Launch Legacy after UEFI"
+End
+
+TOKEN
+	Name  = "DEFAULT_MASS_STORAGE_OPROM_POLICY"
+	Value  = "2"
+	Help  = "Default value of Launch Storage OpROM policy setup control"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0 - Do not launch, 1 - Launch UEFI OpROM only, 2 - Launch Legacy OpROM only, 3 - Launch Legacy before UEFI, 4 - Launch Legacy after UEFI"
+End
+
+TOKEN
+	Name  = "DEFAULT_VIDEO_OPROM_POLICY"
+	Value  = "2"
+	Help  = "Default value of Launch Video OpROM policy setup control"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0 - Do not launch, 1 - Launch UEFI OpROM only, 2 - Launch Legacy OpROM only, 3 - Launch Legacy before UEFI, 4 - Launch Legacy after UEFI"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== SIO Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "CRB_SIO_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CRB_SIO_SUPPORT"
+	Value  = "1"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "SIO_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "EcPs2Kbd_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "SIO_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== UEFI based Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "ENGLISH"
+	Value  = "en-US"
+	Help  = "RFC 4646 Language Identifier for UEFI2.1"
+	TokenType = Expression
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "EFI_SPECIFICATION_VERSION" ">" "0x20000"
+End
+
+TOKEN
+	Name  = "ENGLISH"
+	Value  = "eng"
+	Help  = "ISO 639-2 Language Identifier for UEFI2.0"
+	TokenType = Expression
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "EFI_SPECIFICATION_VERSION" "<=" "0x20000"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== Terminal Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "SerialIo_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "TOTAL_PCI_SERIAL_PORTS"
+	Value  = "1"
+	Help  = "**PORTING NEEDED** Total number of PCI serial ports present."
+	TokenType = Integer
+	TargetMAK = Yes
+	TargetH = Yes
+	Range  = "0-4"
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== WIN8 Feature Configuration ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = WIN8_FEATURE_SUPPORT
+	Value  = "1"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Help  = "Main switch to enable or disable WIN 8 feature"
+End
+
+TOKEN
+	Name  = SecureBoot_SUPPORT
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "SecureMod_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "ENABLE_RTC_ONE_SECOND_WAKEUP"
+	Value  = "1"
+	Help  = "1: Setups RTC 1 second alarm as well."
+	TokenType = Boolean
+	TargetH = Yes
+	Token = "SecureMod_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "CSLIB_WARM_RESET_SUPPORTED"
+	Value  = "1"
+	Help  = "1 - Chipset provides SBLib_ResetSystem(EfiResetWarm).\0 - Simulate Warm Reset via S3 & RTC resume."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "SecureMod_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "OEM_ACTIVATION_TABLE_LOCATION" 
+	Value = "1"
+	Help  = "OEM Activation Table location: \0 = FID Table.\1 = Non-Critical Block."
+	TokenType = Integer
+	TargetH   = Yes
+	TargetMAK = Yes
+	Token = "SecureMod_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "CryptoAPI_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable CryptoAPI support in Project"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "CryptLib_SUPPORT"
+	Value  = "0"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "OemActivation_SUPPORT"
+	Value = "0"
+	Help  = "Main switch to enable OemActivation support in Project"
+	TokenType = Boolean
+	TargetH   = Yes
+	TargetEQU = Yes
+	TargetMAK = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "SmmOemActivation_SUPPORT"
+	Value = "1"
+	Help  = "Switch to enable Update ACPI in the OS Runtime through the SW SMI for OEM Activation without rebooting the system."
+	TokenType = Boolean
+	TargetH   = Yes
+	TargetMAK = Yes
+	Token = "OemActivation_SUPPORT" "=" "1"
+	Token = "WIN8_FEATURE_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = OpalSecurity_SUPPORT
+	Value  = "0"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Help  = "Main switch to enable OpalSecurity support in Project"
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "UefiNetworkStackII"
+	Value  = "0"
+	Help  = "Main switch to enable netwwork stack drivers support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "IntelGigabitLan_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable Intel Gigabit Lan network chip support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "NvramSmiSupport"
+	Value  = "0"
+	Help  = "Main switch to enable NVRAM SMI support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "0"
+End
+
+TOKEN
+	Name  = "GC_MODE0"
+	Value  = "{ 0, 80, 25, 0, 0 }"
+	Help  = "Parameters of the graphica console text mode 0.\NOTE: Text resolution of the mode 0 must be 80 by 25\Format: {ModeNumber, TextColomns,TextRows, HorizontalPixels,VerticalPixels}"
+	TokenType = Expression
+	TargetH = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "DEFAULT_QUIET_BOOT"
+	Value  = "1"
+	Help  = "Default value of the Quiet Boot option"
+	TokenType = Boolean
+	TargetH = Yes
+	Token = "WIN8_FEATURE_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "OPTIMIZE_BOOT_FV_COPY"
+	Value  = "0"
+	Help  = "Switch to enable to optimize(Minimumize) Boot FV copy."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "PEI_RAM_BOOT_S3_SUPPORT" "=" "1"
+	Token = "AMIDEBUG_RX_SUPPORT" "=" "0"
+	Token = "AMI_DEBUGGER_SUPPORT" "=" "0"
+	Token = "DEBUG_MODE" "=" "0"
+End
+
+TOKEN
+        Name  = " "
+        TokenType = Integer
+End
+
+TOKEN
+        Name  = "====== CRB GPIO Configuration ======"
+        TokenType = Expression
+End
+
+TOKEN
+        Name  = "GPIO_SYNC_UP_WITH_INTEL_BIOS"
+        Value  = "0"
+        Help  = "Enable for debugging only"
+        TokenType = Boolean
+        TargetH = Yes
+End
+
+TOKEN
+        Name  = "GPIO_001"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)+$(GPI_INV)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_002"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)+$(GPI_INV)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_004"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_005"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_007"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)+$(GPI_INV)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_008"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)+$(GPI_INV)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_011"
+        Value  = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+	Name = "GPIO_013"
+	Value = "$(IS_GPIO) + $(IS_GPI) + $(GPI_INV)"
+	Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+        Name  = "GPIO_013"
+        Value  = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_014"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)+$(GPI_INV)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+	Name = "GPIO_016"
+	Value = "$(IS_NOT_GPIO)"
+	Help = "[0]:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\[1]:GPIO Input/Output Select.\[2]:GPIO Level Select.\[3]:GPIO Signal Invert(Only For GPIO_00~31).\[4]:GPIO Blink Enable(Only For GPIO_00~31).\[5]:GPIO Reset Select.\[15:6]:RESERVED"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+        Name  = "GPIO_017"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)+$(GPI_INV)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_018"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_019"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_021"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_022"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_024"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_025"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_026"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_028"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_032"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_033"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_035"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_036"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_037"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_038"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_039"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_044"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_045"
+        Value  = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_046"
+        Value  = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_047"
+        Value  = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_048"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_051"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_053"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_055"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_060"
+        Value  = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_LOW)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_070"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_071"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_072"
+        Value  = "$(IS_GPIO)+$(IS_GPO)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+TOKEN
+        Name  = "GPIO_074"
+        Value  = "$(IS_GPIO)+$(IS_GPI)+$(OUTPUT_HIGH)"
+        Help  = "BIT0:GPIO USE Select - 0:Native Mode/1:GPIO Mode.;\BIT1:GPIO Input/Output Select.\BIT2:GPIO Level Select.\BIT3:GPIO Signal Invert(Only For GPIO_00~31).\BIT4:GPIO Blink Enable(Only For GPIO_00~31).\BIT5:GPIO Reset Select."
+        TokenType = Integer
+        TargetEQU = Yes
+        TargetH = Yes
+        Token = "GPIO_SYNC_UP_WITH_INTEL_BIOS" "=" "1"
+End
+
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "====== CRB CUSTOM SSID TABLE ======"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "CRB_CUSTOM_PPI_SUPPORT"
+	Value  = "0"
+	Help  = "0 - Off .\1 - On.\Support CRB CUSTOM SSID Table."
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CRB1_SSID"
+	Value  = "0x72708086"
+	Help  = "This an example, Bit00-15: Vendor ID/Bit16-31:Device ID."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CRB2_SSID"
+	Value  = "0xEEEEEEEE"
+	Help  = "This an example.."
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CRB1_SB_PCI_DEVICES_SSID_TABLE"
+	Value  = "{HECI_BUS_DEV_FUN, CRB1_SSID}, {HECI2_BUS_DEV_FUN, CRB1_SSID}, {IDER_BUS_DEV_FUN, CRB1_SSID}, {KT_BUS_DEV_FUN, CRB1_SSID}, {LAN_BUS_DEV_FUN, CRB1_SSID}, {XHCI_BUS_DEV_FUN, CRB1_SSID}, {EHCI2_BUS_DEV_FUN, CRB1_SSID}, {HDA_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS2_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS3_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS4_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS5_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS6_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS7_BUS_DEV_FUN, CRB1_SSID}, {PCIEBRS8_BUS_DEV_FUN, CRB1_SSID}, {EHCI_BUS_DEV_FUN, CRB1_SSID}, {PCIBR_BUS_DEV_FUN, CRB1_SSID}, {SB_BUS_DEV_FUN, CRB1_SSID}, {SATA_BUS_DEV_FUN, CRB1_SSID}, {SMBUS_BUS_DEV_FUN, CRB1_SSID}, {SATA2_BUS_DEV_FUN, CRB1_SSID}, {THERMAL_BUS_DEV_FUN, CRB1_SSID}, {-1, -1}"
+	Help  = "List of PCI device's Sub-System ID in the following format:\{Device#1 Bus/Device/Function, Device#1 Sub-ID}, {Device#2 Bus/Device/Function, Device#2 Sub-ID}...\The format of the PCI bus/device/function is followed by EFI_PCI_CONFIGURATION_ADDRESS.\If the value of Sub-ID is -1, that means BIOS will use PCI Vendor-ID and Device-ID instead.\The last structure {-1, -1} is end of the table, don't remove it!"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CRB1_NB_PCI_DEVICES_SSID_TABLE"
+	Value  = "{NB_BUS_DEV_FUN, -1}, {NB_IGD_BUS_DEV_FUN, -1}, {NB_IGD_BUS_DEV_FUN1, -1}, {NB_HDA_BUS_DEV_FUN, -1}, {NB_PCIEBRNx16_BUS_DEV_FUN, -1}, {NB_PCIEBRNx8_BUS_DEV_FUN, -1}, {NB_PCIEBRNx4_BUS_DEV_FUN, -1}, {NB_PCIEBRN_BUS_DEV6_FUN, -1}, {-1, -1}"
+	Help  = "List of PCI device's Sub-System ID in the following format:\{Device#1 Bus/Device/Function, Device#1 Sub-ID}, {Device#2 Bus/Device/Function, Device#2 Sub-ID}...\The format of the PCI bus/device/function is followed by EFI_PCI_CONFIGURATION_ADDRESS.\If the value of Sub-ID is -1, that means BIOS will use PCI Vendor-ID and Device-ID instead.\The last structure {-1, -1} is end of the table, don't remove it!"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CRB2_SB_PCI_DEVICES_SSID_TABLE"
+	Value  = "{HECI_BUS_DEV_FUN, CRB2_SSID}, {HECI2_BUS_DEV_FUN, CRB2_SSID}, {IDER_BUS_DEV_FUN, CRB2_SSID}, {KT_BUS_DEV_FUN, CRB2_SSID}, {LAN_BUS_DEV_FUN, CRB2_SSID}, {XHCI_BUS_DEV_FUN, CRB2_SSID}, {EHCI2_BUS_DEV_FUN, CRB2_SSID}, {HDA_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS2_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS3_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS4_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS5_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS6_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS7_BUS_DEV_FUN, CRB2_SSID}, {PCIEBRS8_BUS_DEV_FUN, CRB2_SSID}, {EHCI_BUS_DEV_FUN, CRB2_SSID}, {PCIBR_BUS_DEV_FUN, CRB2_SSID}, {SB_BUS_DEV_FUN, CRB2_SSID}, {SATA_BUS_DEV_FUN, CRB2_SSID}, {SMBUS_BUS_DEV_FUN, CRB2_SSID}, {SATA2_BUS_DEV_FUN, CRB2_SSID}, {THERMAL_BUS_DEV_FUN, CRB2_SSID}, {-1, -1}"
+	Help  = "List of PCI device's Sub-System ID in the following format:\{Device#1 Bus/Device/Function, Device#1 Sub-ID}, {Device#2 Bus/Device/Function, Device#2 Sub-ID}...\The format of the PCI bus/device/function is followed by EFI_PCI_CONFIGURATION_ADDRESS.\If the value of Sub-ID is -1, that means BIOS will use PCI Vendor-ID and Device-ID instead.\The last structure {-1, -1} is end of the table, don't remove it!"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CRB2_NB_PCI_DEVICES_SSID_TABLE"
+	Value  = "{NB_BUS_DEV_FUN, CRB2_SSID}, {NB_IGD_BUS_DEV_FUN, CRB2_SSID}, {NB_IGD_BUS_DEV_FUN1, CRB2_SSID}, {NB_HDA_BUS_DEV_FUN, CRB2_SSID},{NB_PCIEBRNx16_BUS_DEV_FUN, CRB2_SSID}, {NB_PCIEBRNx8_BUS_DEV_FUN, CRB2_SSID}, {NB_PCIEBRNx4_BUS_DEV_FUN, CRB2_SSID}, {NB_PCIEBRN_BUS_DEV6_FUN, CRB2_SSID}, {-1, -1}"
+	Help  = "List of PCI device's Sub-System ID in the following format:\{Device#1 Bus/Device/Function, Device#1 Sub-ID}, {Device#2 Bus/Device/Function, Device#2 Sub-ID}...\The format of the PCI bus/device/function is followed by EFI_PCI_CONFIGURATION_ADDRESS.\If the value of Sub-ID is -1, that means BIOS will use PCI Vendor-ID and Device-ID instead.\The last structure {-1, -1} is end of the table, don't remove it!"
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "============================================"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "EMUL6064_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable KBC Emulation support in Project"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "AMIUSB_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "CRBCSPLib"
+	Value  = "$$(LIB_BUILD_DIR)\AmiCrbCSPLib.lib"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "PTT_VER"
+	Value  = "16"
+	Help  = "PTT module version"
+	TokenType = Integer
+	TargetH = Yes
+	Lock = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "============================================"
+	TokenType = Expression
+End
+
+PATH
+	Name  = "CRB_DIR"
+	Path  = "CRB"
+End
+
+MODULE
+	Help  = "Includes CRB.mak to Project"
+	File  = "CRB.mak"
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\CRB.sdb"
+	Parent  = "SETUP_SDBS"
+	Priority  = 40
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "$(CRB_DIR)\CRB.sd"
+	Parent  = "SETUP_DEFINITIONS"
+	Priority  = 40
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "ASL_PCI0_INI"
+	SrcFile  = "Core\EM\BoardInfo\AmiBoardInfo.mak"
+	InvokeOrder = ReplaceParent
+End
+
+ELINK
+	Name  = "SECCRB_EarlyInit"
+	Parent  = "SECCoreAtPowerOn"
+	Help  = "CRB Early Init in SEC (before Cache as memory enabling)"
+	SrcFile  = "CRB\SRBSEC.ASM"
+	Token = "INCLUDE_CRB_ASM_FILE_IN_SEC" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\CRBSEC.OBJ"
+	Parent  = "ADDON_SEC_CORE_OBJ_FILES"
+	Token = "INCLUDE_CRB_ASM_FILE_IN_SEC" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\CRBPEI.ffs"
+	Parent  = "FV_BB"
+	Help  = "CRB PEI component"
+	InvokeOrder = BeforeParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\CRBDXE.ffs"
+	Parent  = "FV_MAIN"
+	Help  = "CRB DXE component"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\CRBSMI.ffs"
+	Parent  = "FV_MAIN"
+	Help  = "CRB SMI component"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "InitCRBStrings,"
+	Parent  = "SetupStringInit"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "CRBAcpiEnabled,"
+	Parent  = "AcpiEnableCallbackList"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "CRBAcpiDisabled,"
+	Parent  = "AcpiDisableCallbackList"
+	InvokeOrder = AfterParent
+End
+
+ELINK   #[EIP151535]
+	Name  = "GetSetupSataMode,"
+	Parent  = "ProcessEnterSetup,"
+	InvokeOrder = AfterParent
+End
+
+ELINK   #[EIP151535]
+	Name  = "CheckForChangeinSataMode,"
+	Parent  = "PreSystemResetHook,"
+	InvokeOrder = AfterParent
+End
+
+ELINK   #[EIP151535]
+	Name  = "$(BUILD_DIR)\CRBTSE.obj"
+	Parent  = "AMITSE_Objects"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "{0x10EC0888, 0, 0xFF, TRUE, 11, 2, CrbHdaVerbTbl8},"
+	Parent  = "OEM_HDA_VERB_TABLE"
+	Help  = "CRB HDA Verb Table"
+	Token = "CRB_HDA_VERB_TABLE_PRESENT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "{0x10EC0885, 0, 0xFF, TRUE, 11, 2, CrbHdaVerbTbl9},"
+	Parent  = "OEM_HDA_VERB_TABLE"
+	Help  = "CRB HDA Verb Table"
+	Token = "CRB_HDA_VERB_TABLE_PRESENT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "{0x10EC0889, 0, 0xFF, TRUE, 11, 2, CrbHdaVerbTbl10},"
+	Parent  = "OEM_HDA_VERB_TABLE"
+	Help  = "CRB HDA Verb Table"
+	Token = "CRB_HDA_VERB_TABLE_PRESENT" "=" "1"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "IsRecoveryJumper,"
+	Parent  = "IsRecovery"
+	Help  = "CRB recovery jumper detection"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D __EDKII_GLUE_PCD_PcdDebugPrintErrorLevel__=0x80000000+0x00000004+0x00000040"
+	Parent  = "CFLAGS"
+	Help  = "EDKII Debug Mask = EFI_D_ERROR | EFI_D_LOAD | EFI_D_INFO"
+	InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "{ CLOCK_SRC7, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, 0 },"
+	Parent  = "PCIEClockConfig"
+	InvokeOrder = AfterParent
+	Help  = "Intel Flathead Creek, PCIE Slot#6(J13BU)"
+End
+
+ELINK
+	Name  = "{ CLOCK_SRC0, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, 0 },"
+	Parent  = "PCIEClockConfig"
+	InvokeOrder = AfterParent
+	Help  = "Intel Flathead Creek, PCIE Slot#5(J17BU)"
+End
+
+ELINK
+	Name  = "{ CLOCK_SRC6, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, 0 },"
+	Parent  = "PCIEClockConfig"
+	InvokeOrder = AfterParent
+	Help  = "Intel Flathead Creek, PCIE Slot#4(J4BU)"
+End
+
+ELINK
+    Name  = "NEHALEM_MICROCODE"
+    InvokeOrder = ReplaceParent
+End
+
+ELINK
+    Name  = "$(NEHALEM_MICROCODE)"
+    Parent  = "MICROCODE_FILES"
+    InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D AMI_ORIGINAL_FOR_INTEL_4390302"
+	Parent  = "GLOBAL_DEFINES"
+	InvokeOrder = AfterParent
+End
+
+TOKEN
+        Name  = "FIT_ENABLE"
+        Value  = "0"
+        TokenType = Boolean
+End
+
+TOKEN
+        Name  = "FIT_ENABLE"
+        Value  = "1"
+        TokenType = Boolean
+        Token = "INTEL_FIT_SUPPORT" "=" "1"
+End
+
+ELINK
+    Name  = "$(BUILD_DIR)\FwCapsuleHdr.ffs"
+    Parent  = "FV_MAIN"
+    Token = "CREATE_FWCAPSULE" "=" "1"
+    Token = "LZMA_SUPPORT" "=" "0"
+    Token = "FIT_ENABLE" "=" "0"
+    InvokeOrder = AfterParent
+End
+
+ELINK
+    Name  = "$(BUILD_DIR)\FwCapsuleHdr.ffs"
+    Parent  = "FV_MAIN_OUTSIDE_NESTED"
+    Token = "CREATE_FWCAPSULE" "=" "1"
+    Token = "LZMA_SUPPORT" "=" "1"
+    Token = "FIT_ENABLE" "=" "0"
+    InvokeOrder = AfterParent
+End
+
+ELINK
+    Name  = "$(BUILD_DIR)\FwCapsuleHdr.ffs"
+    Parent  = "FV_DATA"
+    Token = "CREATE_FWCAPSULE" "=" "1"
+    Token = "SecureMod_SUPPORT" "=" "1"
+    Token = "FIT_ENABLE" "=" "1"
+    InvokeOrder = AfterParent
+End
+
+ELINK
+	Name  = "/D AMI_SA_PATCH_FOR_CRB_FLAG"
+	Parent  = "GLOBAL_DEFINES"
+	InvokeOrder = AfterParent
+    Token = "AMI_SA_PATCH_FOR_CRB" "=" "1"
+End
+
+ELINK
+    Name = "$(BUILD_DIR)\ROMHOLE.ffs"
+    Parent = "FV_MAIN_OUTSIDE_NESTED"
+    Token = "TSE_ROMHOLE_SUPPORT" "=" "1"
+    InvokeOrder = AfterParent
+End 
+
+TOKEN
+	Name  = "TSE_ROMHOLE_SUPPORT"
+	Value  = "1"
+	Help  = "Enable to support ROMHOLE generation."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PRESERVE_SECURE_VARIABLES"
+	Value  = "1"
+	Help  = "0 - Do not preserve Secure Boot State across flash updates.\1 - Preserve secure boot state.\Note. Same functionality is implemented in SmiFlash eModule starting from Label 4.6.3.6_SMIFLASH_25"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "MAXIMUM_TIMEOUT_FOR_IBFREE"
+	Value  = "5000"
+	Help  = "Maximum Timeout (in miliseconds) used for the function IbFreeTimeout()"
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "MATCH_BOOT_OPTION_BY_LOCATION"
+	Value  = "0"
+	Help  = "When this option is on, the boot option is matched to the boot device using device location information. The device location is a specific connection point that the device is attached to. \For example: SATA Controller 1 Port 0,  IDE Primary Master,  USB Controller 1 Port 3\"
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+ELINK
+	Name  = "MatchUefiFloppyDrive,"
+	Parent  = "BootOptionMatchingFunctions"
+	InvokeOrder = AfterParent
+End
+
+TOKEN
+        Name      = "SSP5_PLD"
+        Value     = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x80, 0x04, 0x00, 0x00, 0x00, 0x00"
+        Help      = "SSP5's Physical Location Description"
+        TokenType = Expression
+        TargetH   = Yes
+End
+
+TOKEN
+        Name      = "SSP6_PLD"
+        Value     = "0x01, 0xC6, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x71, 0x0C, 0x00, 0x05, 0x00, 0x00, 0x00, 0x00"
+        Help      = "SSP6's Physical Location Description"
+        TokenType = Expression
+        TargetH   = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "============================================"
+	TokenType = Expression
+End
+
+TOKEN
+	Name  = "BootScriptHide_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable BootScriptHide support in Project"
+	TokenType = Boolean
+	TargetH = Yes
+        #Master = Yes
+End
+
+TOKEN
+        Name  = "PchS3Support_SUPPORT"
+        Value  = "1"
+        Help  = "Main switch to enable PchS3Support support in Project"
+        TokenType = Boolean
+        TargetEQU = Yes
+        TargetMAK = Yes
+	TargetH = Yes
+        #Master = Yes
+End
+
+TOKEN
+	Name  = " "
+	TokenType = Integer
+End
+
+TOKEN
+	Name  = "============================================"
+	TokenType = Expression
+End
+
+TOKEN
+    Name  = MEFwUpdLcl_SUPPORT
+    Value  = "0"
+    TokenType = Boolean
+    TargetEQU = Yes
+    TargetMAK = Yes
+    Help  = "Main switch to enable MEFwUpdLcl support in Project"
+End
+
+TOKEN
+    Name  = "MEFWUPDLCL_ON_SHARKBAY_PLATFORM"
+    Value  = "1"
+    TokenType = Boolean
+    TargetMAK = Yes
+    Token = "MEFwUpdLcl_SUPPORT" "=" "1"
+End
+
+TOKEN
+    Name  = "ME_BIN_FILE"
+    Value  = "$(ROM_IMAGE_DIR)\ME\ME9.1_1.5M_Production.BIN"
+    TokenType = Expression
+    TargetH = Yes
+    TargetMAK = Yes
+    Token = "MeFwCapsule_SUPPORT" "=" "1"
+End
+
+TOKEN
+    Name  = "ME_FW_IMAGE_VERSION"
+    Value  = "{0, 0, 0, 0}"
+    TokenType = Expression
+    TargetH = Yes
+    Token = "MeFwCapsule_SUPPORT" "=" "1"
+End
+
+TOKEN
+    Name  = "FWCAPSULE_IMAGE_SIZE"
+    Value  = "$(FLASH_SIZE)+$(FWCAPSULE_MAX_HDR_SIZE)+$(FV_MEFWCAP_SIZE)"
+    TokenType = Integer
+    TargetH = Yes
+    Token = "MeFwCapsule_SUPPORT" "=" "1"
+End
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/CRB/CRB.uni b/CRB/CRB.uni
new file mode 100644
index 0000000..1607fe0
--- /dev/null
+++ b/CRB/CRB.uni
diff --git a/CRB/CRBAcpi.c b/CRB/CRBAcpi.c
new file mode 100644
index 0000000..4fc1b45
--- /dev/null
+++ b/CRB/CRBAcpi.c
@@ -0,0 +1,140 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBAcpi.c 2     4/16/13 5:31a Thomaschen $
+//
+// $Revision: 2 $
+//
+// $Date: 4/16/13 5:31a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBAcpi.c $
+// 
+// 2     4/16/13 5:31a Thomaschen
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBAcpi.c
+//
+// Description: This file contains 2 eLinks for CRB ACPI Enabled/Disabled 
+//              event(s).
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+//----------------------------------------------------------------------------
+// Include(s)
+//----------------------------------------------------------------------------
+
+#include <Token.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+#include <Protocol\SmmSwDispatch2.h>
+#define CRB_SMM_SW_DISPATCH_CONTEXT  EFI_SMM_SW_REGISTER_CONTEXT
+#else
+#include <Protocol\SmmSwDispatch.h>
+#define CRB_SMM_SW_DISPATCH_CONTEXT  EFI_SMM_SW_DISPATCH_CONTEXT
+#endif
+
+//----------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//----------------------------------------------------------------------------
+// Constant Definition(s)
+
+// Macro Definition(s)
+
+// Type Definition(s)
+
+// Function Prototype(s)
+
+//----------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//----------------------------------------------------------------------------
+// Variable Declaration(s)
+
+// GUID Definition(s)
+
+// Protocol Definition(s)
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//----------------------------------------------------------------------------
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CRBAcpiEnabled
+//
+// Description: This routine will be called when ACPI enabled.
+//
+// Input:       DispatchHandle  - Handle to the Dispatcher
+//              DispatchContext - SW SMM dispatcher context
+//
+// Output:      None
+//
+// Notes:       Porting if needed.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID CRBAcpiEnabled (
+    IN EFI_HANDLE                   DispatchHandle,
+    IN CRB_SMM_SW_DISPATCH_CONTEXT  *DispatchContext )
+{
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CRBAcpiDisabled
+//
+// Description: This routine will be called when ACPI disabled.
+//
+// Input:       DispatchHandle  - Handle to the Dispatcher
+//              DispatchContext - SW SMM dispatcher context
+//
+// Output:      None
+//
+// Notes:       Porting if needed.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID CRBAcpiDisabled (
+    IN EFI_HANDLE                   DispatchHandle,
+    IN CRB_SMM_SW_DISPATCH_CONTEXT  *DispatchContext )
+{
+}
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBDxe.DXS b/CRB/CRBDxe.DXS
new file mode 100644
index 0000000..066fae0
--- /dev/null
+++ b/CRB/CRBDxe.DXS
@@ -0,0 +1,54 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBDxe.DXS 1     2/12/12 10:38p Victortu $
+//
+// $Revision: 1 $
+//
+// $Date: 2/12/12 10:38p $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBDxe.DXS $
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBDXE.DXS
+//
+// Description: This file is the dependency file for the CRB DXE driver.
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+DEPENDENCY_START
+BEFORE {0xe4ecd0b2, 0xe277, 0x4f2b, 0xbe, 0xcb, 0xe4, 0xd7, 0x5c, 0x9a, 0x81, 0x2e}
+DEPENDENCY_END
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBDxe.c b/CRB/CRBDxe.c
new file mode 100644
index 0000000..52298c1
--- /dev/null
+++ b/CRB/CRBDxe.c
@@ -0,0 +1,146 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBDxe.c 2     4/16/13 5:27a Thomaschen $
+//
+// $Revision: 2 $
+//
+// $Date: 4/16/13 5:27a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBDxe.c $
+// 
+// 2     4/16/13 5:27a Thomaschen
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBDXE.c
+//
+// Description: This file contains code for Chipset Reference Board Template
+//              initialization in the DXE stage
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+//---------------------------------------------------------------------------
+// Include(s)
+//---------------------------------------------------------------------------
+
+#include <Efi.h>
+#include <token.h>
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <Setup.h>
+#include <Dxe.h>
+#include <PCI.h>
+#include <AmiHobs.h>
+#include <AmiCspLib.h>
+
+// Produced Protocols
+
+// Consumed Protocols
+#include <Protocol\PciIO.h>
+#include <Protocol\PciRootBridgeIo.h>
+
+#if ACPI_SUPPORT
+ #if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+ #include <Protocol\S3SaveState.h>
+ #else
+ #include <Protocol\BootScriptSave.h>
+ #endif
+#endif
+
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+#if ACPI_SUPPORT
+ #if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+ #define CRB_S3_SAVE_PROTOCOL EFI_S3_SAVE_STATE_PROTOCOL
+ #define CRB_S3_SAVE_PROTOCOL_GUID gEfiS3SaveStateProtocolGuid
+ #else
+ #define CRB_S3_SAVE_PROTOCOL EFI_BOOT_SCRIPT_SAVE_PROTOCOL
+ #define CRB_S3_SAVE_PROTOCOL_GUID gEfiBootScriptSaveGuid
+ #endif
+#endif
+
+// Macro Definition(s)
+
+// Type Definition(s)
+
+// Function Prototype(s)
+
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+
+// GUID Definition(s)
+
+// Protocol Definition(s)
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//---------------------------------------------------------------------------
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CRBDXE_Init
+//
+// Description: This function is the entry point for CRB DXE driver.
+//              This function initializes the CRB in DXE phase.
+//
+// Input:       ImageHandle - Image handle
+//              SystemTable - Pointer to the system table
+//
+// Output:      EFI_SUCCESS
+//
+// Notes:       This routine is called very early, prior to SBDXE and NBDXE.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS CRBDXE_Init (
+    IN EFI_HANDLE       ImageHandle,
+    IN EFI_SYSTEM_TABLE *SystemTable )
+{
+    EFI_STATUS              Status = EFI_SUCCESS;
+
+    InitAmiLib(ImageHandle, SystemTable);
+
+    return EFI_SUCCESS;
+}
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBLib.c b/CRB/CRBLib.c
new file mode 100644
index 0000000..788031a
--- /dev/null
+++ b/CRB/CRBLib.c
@@ -0,0 +1,466 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBLib.c 3     5/30/13 11:19p Thomaschen $
+//
+// $Revision: 3 $
+//
+// $Date: 5/30/13 11:19p $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBLib.c $
+// 
+// 3     5/30/13 11:19p Thomaschen
+// [TAG]         EIP124808
+// [Category]    Bug Fix
+// [Severity]    Normal
+// [Symptom]     WHCK test fail(Class Driver Audio Logo Test (System)).
+// [RootCause]   NB Verb table error.
+// [Solution]    Modify NB Verb table port B.
+// [Files]       CRBLib.c; CRB.sdl;
+// 
+// 2     5/14/12 8:17a Wesleychen
+// Support CRB recovery jumper.
+// CRB.SDL; CRBLib.c
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBLib.c
+//
+// Description: This file contains Chipset Reference Board related code that
+//              is needed for both PEI & DXE stage. 
+//              To avoid code duplication this file is made as a library and
+//              linked both in PEI & DXE CRB FFS.
+//
+// Notes:       MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+//---------------------------------------------------------------------------
+// Include(s)
+//---------------------------------------------------------------------------
+
+#include <Efi.h>
+#include <Token.h>
+#include <Setup.h>
+#include <AmiPeiLib.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+// Produced Protocols
+
+// Consumed Protocols
+
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+// Macro Definition(s)
+
+// Type Definition(s)
+
+// Function Prototype(s)
+
+// Function Prototype(s)
+VOID CrbSetupCallbacks (
+    IN VOID              *Services,
+    IN OUT NB_SETUP_DATA *NbSetupData,
+    IN SETUP_DATA        *SetupData,
+    IN BOOLEAN           Pei 
+);
+
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+
+UINT32 CrbHdaVerbTbl8[] = {
+//
+// Rear Audio Verb Table 0x10EC0888
+//
+// (NID 01h)
+//===== HDA Codec Subsystem ID Verb-table =====
+//HDA Codec Subsystem ID  : 0x105B0CE3
+  0x001720E3,
+  0x0017210C, 
+  0x0017225B, 
+  0x00172310,
+//===== Pin Widget Verb-table =====
+  //Pin Complex 1     (NID 0x14 )
+  0x01471C10,
+  0x01471D44,
+  0x01471E01,
+  0x01471F01,
+
+  //Pin Complex 2     (NID 0x15 )
+  0x01571C12,
+  0x01571D14,
+  0x01571E01,
+  0x01571F01,
+
+  //Pin Complex 3     (NID 0x16 )
+  0x01671C11,
+  0x01671D64,
+  0x01671E01,
+  0x01671F01,
+
+  //Pin Complex 4     (NID 0x17 )
+  0x01771C14,
+  0x01771D24,
+  0x01771E01,
+  0x01771F01,
+
+  //Pin Complex 5     (NID 0x18 )
+  0x01871C40,
+  0x01871D9C,
+  0x01871EA1,
+  0x01871F01,
+
+  //Pin Complex 6     (NID 0x19 )
+  0x01971C50,
+  0x01971D9C,
+  0x01971EA1,
+  0x01971F02,
+
+  //Pin Complex 7     (NID 0x1A )
+  0x01A71C4F,
+  0x01A71D34,
+  0x01A71E81,
+  0x01A71F01,
+
+  //Pin Complex 8     (NID 0x1B )
+  0x01B71C20,
+  0x01B71D4C,
+  0x01B71E21,
+  0x01B71F02,
+
+  //Pin Complex 9     (NID 0x1C )
+  0x01C71CF0,
+  0x01C71D01,
+  0x01C71E33,
+  0x01C71F59,
+
+  //Pin Complex 10    (NID 0x1D )
+  0x01D71C01,
+  0x01D71DE6,
+  0x01D71E05,
+  0x01D71F40,
+
+  //Pin Complex 11    (NID 0x1E )
+  0x01E71C30,
+  0x01E71D61,
+  0x01E71E4B,
+  0x01E71F01,
+
+  //Pin Complex 12    (NID 0x1F )
+  0x01F71C60,
+  0x01F71D71,
+  0x01F71ECB,
+  0x01F71F01
+};
+
+UINT32 CrbHdaVerbTbl9[] = {
+//
+// Rear Audio Verb Table 0x10EC0885
+//
+// (NID 01h)
+//;===== HDA Codec Subsystem ID Verb-table =====
+//;HDA Codec Subsystem ID  : 0x80860021
+  0x00172021,
+  0x00172100,
+  0x00172286,
+  0x00172380,
+  //===== Pin Widget Verb-table =====
+  // Pin Complex 1       (NID 14h)
+  0x01471C10,
+  0x01471D44,
+  0x01471E01,
+  0x01471F01,
+  // Pin Complex 2       (NID 15h)
+  0x01571C20,
+  0x01571D44,
+  0x01571E21,
+  0x01571F02,
+  // Pin Complex 3       (NID 16h)
+  0x01671C11,
+  0x01671D60,
+  0x01671E01,
+  0x01671F01,
+  // Pin Complex 4       (NID 17h)
+  0x01771CF0,
+  0x01771D11,
+  0x01771E11,
+  0x01771F41,
+  // Pin Complex 5       (NID 18h)
+  0x01871C50,
+  0x01871D98,
+  0x01871EA1,
+  0x01871F02,
+  // Pin Complex 6       (NID 19h)
+  0x01971C12,
+  0x01971D10,
+  0x01971E01,
+  0x01971F01,
+  // Pin Complex 7       (NID 1Ah)
+  0x01A71C40,
+  0x01A71D34,
+  0x01A71E81,
+  0x01A71F01,
+  // Pin Complex 8       (NID 1Bh)
+  0x01B71C4F,
+  0x01B71D98,
+  0x01B71EA1,
+  0x01B71F01,
+  // Pin Complex 9       (NID 1Ch)
+  0x01C71CF0,
+  0x01C71D11,
+  0x01C71E11,
+  0x01C71E41,
+  // Pin Complex 10       (NID 1Dh)
+  0x01D71CF0,
+  0x01D71D01,
+  0x01D71E83,
+  0x01D71F59,
+  // Pin Complex 11       (NID 1Eh)
+  0x01E71C30,
+  0x01E71D11,
+  0x01E71E45,
+  0x01E71F01,
+  // Pin Complex 12       (NID 1Fh)
+  0x01F71CF0,
+  0x01F71D11,
+  0x01F71E11,
+  0x01F71F41
+};
+
+UINT32 CrbHdaVerbTbl10[] = {
+//
+// Rear Audio Verb Table 0x10EC0889
+//
+// (NID 01h)
+//===== HDA Codec Subsystem ID Verb-table =====
+//HDA Codec Subsystem ID  : 0x80860022
+  0x00172022,
+  0x00172100, 
+  0x00172286, 
+  0x00172380,
+//===== Pin Widget Verb-table =====
+  //Pin Complex 1     (NID 0x14 )
+  0x01471C10,
+  0x01471D44,
+  0x01471E01,
+  0x01471F01,
+
+  //Pin Complex 2     (NID 0x15 )
+  0x01571C20,
+  0x01571D40,
+  0x01571E21,
+  0x01571F02,
+
+  //Pin Complex 3     (NID 0x16 )
+  0x01671C11,
+  0x01671D64,
+  0x01671E01,
+  0x01671F01,
+
+  //Pin Complex 4     (NID 0x17 )
+  0x01771CF0,
+  0x01771D11,
+  0x01771E11,
+  0x01771F41,
+
+  //Pin Complex 5     (NID 0x18 )
+  0x01871C50,
+  0x01871D98,
+  0x01871EA1,
+  0x01871F02,
+
+  //Pin Complex 6     (NID 0x19 )
+  0x01971C12,
+  0x01971D14,
+  0x01971E01,
+  0x01971F01,
+
+  //Pin Complex 7     (NID 0x1A )
+  0x01A71C40,
+  0x01A71D34,
+  0x01A71E81,
+  0x01A71F01,
+
+  //Pin Complex 8     (NID 0x1B )
+  0x01B71C4F,
+  0x01B71D9C,
+  0x01B71EA1,
+  0x01B71F01,
+
+  //Pin Complex 9     (NID 0x1C )
+  0x01C71CF0,
+  0x01C71D11,
+  0x01C71E11,
+  0x01C71F41,
+
+  //Pin Complex 10    (NID 0x1D )
+  0x01D71CF0,
+  0x01D71D01,
+  0x01D71E83,
+  0x01D71F59,
+
+  //Pin Complex 11    (NID 0x1E )
+  0x01E71C30,
+  0x01E71D11,
+  0x01E71E45,
+  0x01E71F01,
+
+  //Pin Complex 12    (NID 0x1F )
+  0x01F71CF0,
+  0x01F71D11,
+  0x01F71E11,
+  0x01F71F41
+};
+
+
+// GUID Definition(s)
+
+// Protocol Definition(s)
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//---------------------------------------------------------------------------
+
+// All routines in this file will be added into CSP library.
+
+UINT32            CrbNbSaHdaVerbTableData[] = {
+  ///
+  /// Audio Verb Table - 0x80862807
+  ///
+  /// Pin Widget 5 - PORT B
+  ///
+  0x00571C10,
+  0x00571D00,
+  0x00571E56,
+  0x00571F58,
+  ///
+  /// Pin Widget 6 - PORT C
+  ///
+  0x00671C20,
+  0x00671D00,
+  0x00671E56,
+  0x00671F18,
+  ///
+  /// Pin Widget 7 - PORT D
+  ///
+  0x00771C30,
+  0x00771D00,
+  0x00771E56,
+  0x00771F18
+};
+
+NB_SA_HDA_VERB_TABLE CrbNbSaHdaVerbTable[] = {
+  { 
+      {
+      0x80862807, ///< Vendor ID/Device ID
+      0x0000,     ///< SubSystem ID
+      0xFF,       ///< Revision ID
+      0x02,       ///< Front panel support (1=yes, 2=no)
+      0x0003,     ///< Number of Rear Jacks
+      0x0000      ///< Number of Front Jacks
+      },
+    0             ///< Pointer to verb table data, need to be inited in the code.
+  }
+};
+//---------------------------------------------------------------------------
+
+//----------------------------------------------------------------------------
+// Procedure:   CrbSetupCallbacks
+//
+// Description: This function returns NB Chipset setup data from system SetupData
+//              variable 
+//
+// Input:       *Services    - Pointer to PeiServices or RuntimeServices
+//                             structure  
+//              *NbSetupData - Pointer to custom setup data to return
+//              *SetupData   - Pointer to system setup data.
+//              Pei          - Pei flag. If TRUE we are in PEI phase
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID CrbSetupCallbacks (
+    IN VOID              *Services,
+    IN OUT NB_SETUP_DATA *NbSetupData,
+    IN SETUP_DATA        *SetupData,
+    IN BOOLEAN           Pei )
+{
+    if (SetupData != NULL && !Pei) {
+        // Porting Start
+        NbSetupData->NbSaHdaVerbTable      = CrbNbSaHdaVerbTable;
+        NbSetupData->NbSaHdaVerbTable->VerbTableData = CrbNbSaHdaVerbTableData;
+        NbSetupData->NbSaHdaVerbTableNum   = sizeof (CrbNbSaHdaVerbTable) / sizeof (NB_SA_HDA_VERB_TABLE);
+        // Porting End
+    }
+}
+
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   IsRecoveryJumper
+//
+// Description: This function determines the system to boot in recovery mode
+//              if recovery jumper is in position.
+//
+// Input:       IN EFI_PEI_SERVICES             **PeiServices,
+//
+// Output:      TRUE - The system is booting in recovery mode
+//              FALSE - Normal Boot
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+BOOLEAN IsRecoveryJumper
+(
+  IN EFI_PEI_SERVICES **PeiServices
+)
+{
+  BOOLEAN           JumperFlag;
+  UINT32            GpioVal;
+
+  // Read the status of the GPIO22 recovery jumper from the GPIO registers
+  GpioVal = IoRead32 (GPIO_BASE_ADDRESS + GP_IOREG_GP_LVL);
+
+  JumperFlag = ((BOOLEAN) (!(GpioVal & BIT22)));
+
+  return JumperFlag;
+}
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBLib.h b/CRB/CRBLib.h
new file mode 100644
index 0000000..f3d3da6
--- /dev/null
+++ b/CRB/CRBLib.h
@@ -0,0 +1,79 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBLib.h 2     4/16/13 5:30a Thomaschen $
+//
+// $Revision: 2 $
+//
+// $Date: 4/16/13 5:30a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBLib.h $
+// 
+// 2     4/16/13 5:30a Thomaschen
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBLib.h
+//
+// Description: Custom Reference Board (or Demo Board) header file.
+//              Defines all the CRB specific equates and structures in
+//              this file. 
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+#ifndef __CRBLIB_H__
+#define __CRBLIB_H__
+
+//---------------------------------------------------------------------------
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+UINT32                          CrbHdaVerbTbl8[];
+UINT32                          CrbHdaVerbTbl9[];
+UINT32                          CrbHdaVerbTbl10[];
+
+BOOLEAN IsRecoveryJumper(
+  IN EFI_PEI_SERVICES **PeiServices
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBPei.DXS b/CRB/CRBPei.DXS
new file mode 100644
index 0000000..cf0ab1b
--- /dev/null
+++ b/CRB/CRBPei.DXS
@@ -0,0 +1,66 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBPei.DXS 2     4/16/13 5:32a Thomaschen $
+//
+// $Revision: 2 $
+//
+// $Date: 4/16/13 5:32a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBPei.DXS $
+// 
+// 2     4/16/13 5:32a Thomaschen
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBPEI.DXS
+//
+// Description: This file is the dependency file for the CRB PEIM.
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+#include <pei.h>
+#include "ppi\CpuIo.h"
+#include "ppi\PciCfg2.h"
+#include <Ppi\ReadOnlyVariable2.h>
+#include "ppi\CspLibPpi.h"
+
+DEPENDENCY_START
+   EFI_PEI_CPU_IO_PPI_INSTALLED_GUID AND
+   EFI_PEI_PCI_CFG2_PPI_GUID AND
+   EFI_PEI_READ_ONLY_VARIABLE2_PPI_GUID AND
+   AMI_PEI_PCI_TABLE_INIT_PPI_GUID
+DEPENDENCY_END
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBPei.c b/CRB/CRBPei.c
new file mode 100644
index 0000000..6483ad3
--- /dev/null
+++ b/CRB/CRBPei.c
@@ -0,0 +1,546 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBPei.c 12    4/16/13 5:25a Thomaschen $
+//
+// $Revision: 12 $
+//
+// $Date: 4/16/13 5:25a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBPei.c $
+// 
+// 12    4/16/13 5:25a Thomaschen
+// 
+// 11    9/28/12 10:27a Wesleychen
+//  - Remove "AMI_RAPID_START_WORKAROUND"
+//    CRB.SDL; CRB.PEI
+// 
+// 10    9/06/12 11:33a Wesleychen
+// Fixed system cannot wakeup via RTC if iFFS is enable.
+// (Token "AMI_RAPID_START_WORKAROUND")
+// 
+// 9     9/04/12 11:04p Wesleychen
+//  - Always enable 60h/64h decode.
+//  - Remove CRB GPIO settings.
+// 
+// 4     7/31/12 5:16a Wesleychen
+// Programming GPIOs by reference Intel BIOS v80 setting.
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBPEI.c
+//
+// Description: This file contains code for Chipset Reference Board
+//              Template initialization in the PEI stage
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+//---------------------------------------------------------------------------
+// Include(s)
+//---------------------------------------------------------------------------
+
+#include <Efi.h>
+#include <Pei.h>
+#include <Token.h>
+#include <AmiPeiLib.h>
+#include <Hob.h>
+#include <Setup.h>
+#include <AmiCspLib.h>
+#if defined(IntelPchInclude_SUPPORT) && IntelPchInclude_SUPPORT == 1
+#include <PchAccess.h>
+#endif
+#include <ppi\smbus.h>
+// Produced PPIs
+
+// Consumed PPIs
+#include <ppi\NBPPI.h>
+#include <ppi\SBPPI.h>
+// Intel Platform Policy Override Sample Code >>>
+//#####include <Ppi\PchPlatformPolicy\PchPlatformPolicy.h>
+//#####include <Ppi\SaPlatformPolicy\SaPlatformPolicy.h>
+// Intel Platform Policy Override Sample Code <<<
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+// Macro Definition(s)
+
+// Type Definition(s)
+
+typedef struct {
+    UINT64          BusDevFunReg;
+    UINT32          SubId;
+} PCI_SUBID_TABLE;
+
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+
+// GUID Definition(s)
+EFI_GUID gPeiSmBusPpiGuid             = EFI_PEI_SMBUS_PPI_GUID;
+// Intel Platform Policy Override Sample Code >>>
+//####EFI_GUID gOemPchPlatformPolicyOverridePpiGuid = AMI_PEI_SB_OEM_PLATFORM_POLICY_OVERRIDE_PPI_GUID;
+//####EFI_GUID gOemSalatformPolicyOverridePpiGuid = AMI_PEI_NB_OEM_PLATFORM_POLICY_OVERRIDE_PPI_GUID
+// Intel Platform Policy Override Sample Code <<<
+// PPI Definition(s)
+
+
+// Function Definition(s)
+EFI_STATUS InitCK505ClockGen(
+	IN EFI_PEI_SERVICES             **PeiServices,
+	IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+	IN VOID                         *NullPpi
+);
+
+// Intel Platform Policy Override Sample Code >>>
+//####EFI_STATUS OemPchPlatformPolicyOverride (
+//####  IN EFI_PEI_SERVICES             **PeiServices,
+//####  IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+//####  IN VOID                         *Ppi
+//####);
+
+//####EFI_STATUS OemSaPlatformPolicyOverride (
+//####  IN EFI_PEI_SERVICES             **PeiServices,
+//####  IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+//####  IN VOID                         *Ppi
+//####);
+// Intel Platform Policy Override Sample Code <<<
+
+// PPI that are installed
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = 
+{
+  {
+    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+    &gPeiSmBusPpiGuid,
+    InitCK505ClockGen
+  }
+};
+
+// Intel Platform Policy Override Sample Code >>>
+//####static EFI_PEI_NOTIFY_DESCRIPTOR  mOverrideNotifyList[] = {
+//####  {
+//####    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
+//####    &gOemSalatformPolicyOverridePpiGuid,
+//####    OemSaPlatformPolicyOverride
+
+//####    EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+//####    &gOemPchPlatformPolicyOverridePpiGuid,
+//####    OemPchPlatformPolicyOverride
+//####  }
+//####};
+// Intel Platform Policy Override Sample Code <<<
+
+// Function Prototype(s)
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+
+AMI_GPIO_INIT_TABLE_STRUCT Crb1GpioTable [] = {
+////  Intel CRB BIOS Setting  ////
+////  Just for reference only!!    ////
+/*
+    {0,  IS_GPIO + IS_GPI},
+    {1,  IS_GPIO + IS_GPI + GPI_INV},
+    {2,  IS_GPIO + IS_GPI + GPI_INV},
+    {3,  IS_NOT_GPIO},
+    {4,  IS_GPIO + IS_GPI},
+    {5,  IS_GPIO + IS_GPI},
+    {6,  IS_GPIO + IS_GPI},
+    {7,  IS_GPIO + IS_GPI + GPI_INV},
+
+    {8,  IS_GPIO + IS_GPI + GPI_INV},
+    {9,  IS_NOT_GPIO},
+    {10, IS_NOT_GPIO},
+    {11, IS_GPIO + IS_GPO + OUTPUT_LOW},
+    {12, IS_NOT_GPIO},
+    {13, IS_GPIO + IS_GPO + OUTPUT_LOW},
+    {14, IS_GPIO + IS_GPI + GPI_INV},
+    {15, IS_GPIO + IS_GPO + OUTPUT_LOW},
+
+    {16, IS_NOT_GPIO},
+    {17, IS_GPIO + IS_GPI + GPI_INV},
+    {18, IS_GPIO + IS_GPI},
+    {19, IS_GPIO + IS_GPI},
+    {20, IS_NOT_GPIO},
+    {21, IS_GPIO + IS_GPI},
+    {22, IS_GPIO + IS_GPI},
+    {23, IS_NOT_GPIO},
+
+    {24, IS_GPIO + IS_GPI},
+    {25, IS_GPIO + IS_GPI},
+    {26, IS_GPIO + IS_GPI},
+    {27, IS_GPIO + IS_GPI},
+    {28, IS_GPIO + IS_GPI},
+    {29, IS_NOT_GPIO},
+    {30, IS_NOT_GPIO},
+    {31, IS_GPIO + IS_GPI},
+
+    {32, IS_GPIO + IS_GPI},
+    {33, IS_GPIO + IS_GPI},
+    {34, IS_GPIO + IS_GPI},
+    {35, IS_GPIO + IS_GPI},
+    {36, IS_GPIO + IS_GPI},
+    {37, IS_GPIO + IS_GPI},
+    {38, IS_GPIO + IS_GPI},
+    {39, IS_GPIO + IS_GPI},
+
+    {40, IS_NOT_GPIO},
+    {41, IS_NOT_GPIO},
+    {42, IS_NOT_GPIO},
+    {43, IS_NOT_GPIO},
+    {44, IS_GPIO + IS_GPI},
+    {45, IS_GPIO + IS_GPO + OUTPUT_HIGH},
+    {46, IS_GPIO + IS_GPO + OUTPUT_HIGH},
+    {47, IS_GPIO + IS_GPO + OUTPUT_LOW},
+
+    {48, IS_GPIO + IS_GPI},
+    {49, IS_GPIO + IS_GPI},
+    {50, IS_GPIO + IS_GPI + OUTPUT_HIGH},
+    {51, IS_GPIO + IS_GPI},
+    {52, IS_GPIO + IS_GPI + OUTPUT_HIGH},
+    {53, IS_GPIO + IS_GPI},
+    {54, IS_GPIO + IS_GPI + OUTPUT_HIGH},
+    {55, IS_GPIO + IS_GPI},
+
+    {56, IS_NOT_GPIO},
+    {57, IS_GPIO + IS_GPI},
+    {58, IS_NOT_GPIO},
+    {59, IS_NOT_GPIO},
+    {60, IS_GPIO + IS_GPO + OUTPUT_HIGH},
+    {61, IS_NOT_GPIO},
+    {62, IS_NOT_GPIO},
+    {63, IS_NOT_GPIO},
+
+    {64, IS_NOT_GPIO},
+    {65, IS_NOT_GPIO},
+    {66, IS_NOT_GPIO},
+    {67, IS_NOT_GPIO},
+    {68, IS_GPIO + IS_GPI},
+    {69, IS_GPIO + IS_GPI},
+    {70, IS_GPIO + IS_GPI},
+    {71, IS_GPIO + IS_GPI},
+
+    {72, IS_GPIO + IS_GPO + OUTPUT_HIGH},
+    {73, IS_NOT_GPIO},
+    {74, IS_GPIO + IS_GPI},
+    {75, IS_NOT_GPIO},
+*/
+////  Intel CRB BIOS Setting  ////
+    {0xffff, 0xffff}, // End of the table.
+};
+AMI_GPIO_INIT_TABLE_STRUCT Crb2GpioTable [] = {
+//    {13, IS_GPIO + IS_GPI},
+    {0xffff, 0xffff}, // End of the table.
+};
+
+// GUID Definition(s)
+
+// PPI Definition(s)
+AMI_GPIO_INIT_PPI Crb1GpioInitPpi = { 
+    GPIO_BASE_ADDRESS,
+    Crb1GpioTable,
+    TRUE
+};
+
+AMI_GPIO_INIT_PPI Crb2GpioInitPpi = { 
+    GPIO_BASE_ADDRESS,
+    Crb2GpioTable,
+    TRUE
+};
+
+AMI_SB_PCI_SSID_TABLE_STRUCT Crb1SbSsidTable[] = { 
+    CRB1_SB_PCI_DEVICES_SSID_TABLE
+};
+
+AMI_NB_PCI_SSID_TABLE_STRUCT Crb1NbSsidTable[] = { 
+    CRB1_NB_PCI_DEVICES_SSID_TABLE
+};
+
+AMI_SB_PCI_SSID_TABLE_STRUCT Crb2SbSsidTable[] = { 
+    CRB2_SB_PCI_DEVICES_SSID_TABLE
+};
+
+AMI_NB_PCI_SSID_TABLE_STRUCT Crb2NbSsidTable[] = { 
+    CRB2_NB_PCI_DEVICES_SSID_TABLE
+};
+
+static AMI_PEI_SB_CUSTOM_PPI Crb1SbCustomPpi = {
+    &Crb1GpioInitPpi, 
+    Crb1SbSsidTable
+};
+
+static AMI_PEI_NB_CUSTOM_PPI Crb1NbCustomPpi = {
+    Crb1NbSsidTable
+};
+
+static AMI_PEI_SB_CUSTOM_PPI Crb2SbCustomPpi = {
+    &Crb2GpioInitPpi, 
+    Crb2SbSsidTable
+};
+
+static AMI_PEI_NB_CUSTOM_PPI Crb2NbCustomPpi = {
+    Crb2NbSsidTable
+};
+
+// PPI that are installed
+
+static EFI_PEI_PPI_DESCRIPTOR Crb1CustomPpi[] = {
+    { EFI_PEI_PPI_DESCRIPTOR_PPI , \
+      &gAmiPeiNBCustomPpiGuid, &Crb1NbCustomPpi },
+    { EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \
+      &gAmiPeiSBCustomPpiGuid, &Crb1SbCustomPpi },
+};
+
+static EFI_PEI_PPI_DESCRIPTOR Crb2CustomPpi[] = {
+    { EFI_PEI_PPI_DESCRIPTOR_PPI , \
+      &gAmiPeiNBCustomPpiGuid, &Crb2NbCustomPpi },
+    { EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \
+      &gAmiPeiSBCustomPpiGuid, &Crb2SbCustomPpi },
+};
+// PPI that are notified
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//---------------------------------------------------------------------------
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CRBPEI_Init
+//
+// Description: This function is the entry point for CRB PEIM.
+//              It initializes the chipset CRB in PEI phase.
+//
+// Input:       FfsHeader   - Pointer to the FFS file header.
+//              PeiServices - Pointer to the PEI services table.
+//
+// Output:      EFI_SUCCESS
+//
+// Notes:       This routine is called very early, prior to SBPEI and NBPEI.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS EFIAPI CRBPEI_Init (
+    IN EFI_FFS_FILE_HEADER      *FfsHeader,
+    IN EFI_PEI_SERVICES         **PeiServices )
+{
+    EFI_STATUS                  Status = EFI_SUCCESS;
+    EFI_PEI_PCI_CFG2_PPI        *PciCfg;
+    EFI_PEI_CPU_IO_PPI          *CpuIo;
+
+    // Get pointer to the PCI config PPI
+    PciCfg = (*PeiServices)->PciCfg;
+
+    // Get pointer to the CpuIo PPI
+    CpuIo = (*PeiServices)->CpuIo;
+
+    Status = SbLib_SetLpcDeviceDecoding(NULL,0x60, 0, dsPS2K);          // Decode SB Port 0x60,0x64
+
+    // Install custom PPI for customization
+    // Customers or OEM can define SSID and GPIO by different platform type
+#if CRB_CUSTOM_PPI_SUPPORT
+    // This is a sample for reference.
+    Status = (*PeiServices)->InstallPpi( PeiServices, Crb1CustomPpi );
+    ASSERT_PEI_ERROR( PeiServices, Status );
+//####  Status = (*PeiServices)->InstallPpi( PeiServices, Crb2CustomPpi );
+//####  ASSERT_PEI_ERROR( PeiServices, Status );
+#endif
+	// Set the CRB Notify PPI
+    if ( CLOCK_GENERATOR_ADDRESS != 0xFF)
+    {
+      Status = (*PeiServices)->NotifyPpi(PeiServices, mNotifyList);
+      ASSERT_PEI_ERROR (PeiServices, Status);
+    }
+
+// Intel Platform Policy Override Sample Code >>>
+//####    Status = (*PeiServices)->NotifyPpi(PeiServices, &mOverrideNotifyList[0]);
+//####    ASSERT_PEI_ERROR (PeiServices, Status);
+// Intel Platform Policy Override Sample Code <<<
+
+    return EFI_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InitCK505ClockGen
+//
+// Description: This function is to initialiae CK505 clock generator.
+//
+// Input:       IN EFI_PEI_SERVICES             **PeiServices,
+//              IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+//              IN VOID                         *NullPpi
+//
+// Output:      EFI_SUCCESS
+//
+// Notes:
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+EFI_STATUS InitCK505ClockGen
+(
+    IN EFI_PEI_SERVICES             **PeiServices,
+    IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+    IN VOID                         *NullPpi
+)
+{
+    EFI_STATUS        Status;
+    EFI_PEI_SMBUS_PPI    *SmBus;
+    EFI_SMBUS_DEVICE_ADDRESS    Address;
+    UINT8        CK505TBL[] =  CLOCK_GENERATOR_SETTINGS;
+    UINTN        Len = sizeof(CK505TBL);
+
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "Program CK505 start.\n"));
+
+    Address.SmbusDeviceAddress = CLOCK_GENERATOR_ADDRESS >> 1;
+
+    Status = (*PeiServices)->LocatePpi( PeiServices,
+			                &gPeiSmBusPpiGuid,
+			                0,
+			                NULL,
+			                &SmBus );
+    ASSERT_PEI_ERROR( PeiServices, Status);
+
+    SmBus->Execute( PeiServices,
+	            SmBus,
+ 	            Address,
+  	            0,
+   	            EfiSmbusWriteBlock,
+	            0,
+ 	            &Len,
+	            CK505TBL
+ 	           );
+
+    PEI_TRACE((TRACE_ALWAYS, PeiServices, "Program CK505 end.\n"));
+
+    return EFI_SUCCESS;
+}
+
+
+// Intel Platform Policy Override Sample Code >>>
+//####//<AMI_PHDR_START>
+//####//----------------------------------------------------------------------------
+//####//
+//####// Procedure:   OemPchPlatformPolicyOverride
+//####//
+//####// Description: This function is a sample code to guide user how to use
+//####//              AMI_PEI_SB_OEM_PLATFORM_POLICY_OVERRIDE_PPI_GUID to override
+//####//              Intel platform policy.
+//####//
+//####// Input:       IN EFI_PEI_SERVICES             **PeiServices,
+//####//              IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+//####//              IN VOID                         *NullPpi
+//####//
+//####// Output:      EFI_SUCCESS
+//####//
+//####// Notes:
+//####//----------------------------------------------------------------------------
+//####//<AMI_PHDR_END>
+//####EFI_STATUS OemPchPlatformPolicyOverride (
+//####  IN EFI_PEI_SERVICES             **PeiServices,
+//####  IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+//####  IN VOID                         *Ppi
+//####  )
+//####{
+//####  EFI_STATUS              Status;
+//####  PCH_PLATFORM_POLICY_PPI *PchPlatformPolicyPpi;
+//####  //
+//####  // Get platform policy settings through the PchPlatformPolicy PPI
+//####  //
+//####  Status = (**PeiServices).LocatePpi (
+//####                            PeiServices,
+//####                            &gOemPchPlatformPolicyOverridePpiGuid,
+//####                            0,
+//####                            NULL,
+//####                            &PchPlatformPolicyPpi );
+//####  ASSERT_PEI_ERROR (PeiServices, Status);
+
+//####  PchPlatformPolicyPpi->SataConfig->SataTraceConfig->PortLength[0] = 0x35;
+//####  PchPlatformPolicyPpi->SataConfig->SataTraceConfig->PortTopology[0] = 0;
+//####  PchPlatformPolicyPpi->SataConfig->SataTraceConfig->PortLength[1] = 0x20;
+//####  PchPlatformPolicyPpi->SataConfig->SataTraceConfig->PortTopology[1] = 1;
+//####
+//####  return Status;
+//####}
+
+//####//<AMI_PHDR_START>
+//####//----------------------------------------------------------------------------
+//####//
+//####// Procedure:   OemSaPlatformPolicyOverride
+//####//
+//####// Description: This function is a sample code to guide user how to use
+//####//              AMI_PEI_NB_OEM_PLATFORM_POLICY_OVERRIDE_PPI_GUID to override
+//####//              Intel platform policy.
+//####//
+//####// Input:       IN EFI_PEI_SERVICES             **PeiServices,
+//####//              IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+//####//              IN VOID                         *NullPpi
+//####//
+//####// Output:      EFI_SUCCESS
+//####//
+//####// Notes:
+//####//----------------------------------------------------------------------------
+//####//<AMI_PHDR_END>
+//####EFI_STATUS OemPchPlatformPolicyOverride (
+//####  IN EFI_PEI_SERVICES             **PeiServices,
+//####  IN EFI_PEI_NOTIFY_DESCRIPTOR    *NotifyDescriptor,
+//####  IN VOID                         *Ppi
+//####  )
+//####{
+//####  EFI_STATUS              Status;
+//####  PCH_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi;
+//####  //
+//####  // Get platform policy settings through the SaPlatformPolicyPpi
+//####  //
+//####  Status = (**PeiServices).LocatePpi (
+//####                            PeiServices,
+//####                            &gOemSalatformPolicyOverridePpiGuid,
+//####                            0,
+//####                            NULL,
+//####                            &SaPlatformPolicyPpi );
+//####  ASSERT_PEI_ERROR (PeiServices, Status);
+
+//####  SaPlatformPolicyPpi->PlatformData->FastBoot = 0;
+//####  SaPlatformPolicyPpi->MemConfig->RemapEnable = 0;
+//####
+//####  return Status;
+//####}
+// Intel Platform Policy Override Sample Code <<<
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBSec.ASM b/CRB/CRBSec.ASM
new file mode 100644
index 0000000..7cd1c79
--- /dev/null
+++ b/CRB/CRBSec.ASM
@@ -0,0 +1,103 @@
+        TITLE CRBSEC.ASM -- Chipset Reference Board SEC initialization
+;*************************************************************************
+;*************************************************************************
+;**                                                                     **
+;**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+;**                                                                     **
+;**                       All Rights Reserved.                          **
+;**                                                                     **
+;**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+;**                                                                     **
+;**                       Phone: (770)-246-8600                         **
+;**                                                                     **
+;*************************************************************************
+;*************************************************************************
+
+;*************************************************************************
+; $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBSec.ASM 1     2/12/12 10:38p Victortu $
+;
+; $Revision: 1 $
+;
+; $Date: 2/12/12 10:38p $
+;*************************************************************************
+; Revision History
+; ----------------
+; $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBSec.ASM $
+; 
+; 1     2/12/12 10:38p Victortu
+; Intel SharkBay CRB initially releases.
+; 
+;*************************************************************************
+;<AMI_FHDR_START>
+;
+; Name:         SRBSEC.ASM
+;
+; Description:  Program any workaround or initialization needed before
+;               enabling Cache as memory in the SEC stage for CRB.
+;
+;<AMI_FHDR_END>
+;*************************************************************************
+
+;---------------------------------------------------------------------------
+        INCLUDE token.equ
+;---------------------------------------------------------------------------
+
+.586P
+.XMM
+.MODEL SMALL
+
+; Externs
+EXTERN  SECCRB_EarlyInitEnd:NEAR32
+
+; Define the equates here
+
+;---------------------------------------------------------------------------
+;       STARTUP_SEG  S E G M E N T  STARTS
+;---------------------------------------------------------------------------
+STARTUP_SEG     SEGMENT     PARA PUBLIC 'CODE' USE32
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure:    SECCRB_EarlyInit
+;
+; Description:  This routine initializes CRB for PEI preparation
+;
+; Input:        ESP BIST Info
+;               EBP Reset ID (EDX at reset)
+;               Stack not available
+;
+; Output:       None
+;
+; Modified:     All, except EBP and ESP
+;
+; Notes:        NBSEC & SBSEC initialization is done at this point.
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+SECCRB_EarlyInit     PROC PUBLIC
+
+
+        jmp     SECCRB_EarlyInitEnd
+SECCRB_EarlyInit     ENDP
+
+;---------------------------------------------------------------------------
+;       STARTUP_SEG  S E G M E N T  ENDS
+;---------------------------------------------------------------------------
+STARTUP_SEG     ENDS
+END
+
+;*************************************************************************
+;*************************************************************************
+;**                                                                     **
+;**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+;**                                                                     **
+;**                       All Rights Reserved.                          **
+;**                                                                     **
+;**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+;**                                                                     **
+;**                       Phone: (770)-246-8600                         **
+;**                                                                     **
+;*************************************************************************
+;*************************************************************************
+
diff --git a/CRB/CRBSetup.c b/CRB/CRBSetup.c
new file mode 100644
index 0000000..8b54a3a
--- /dev/null
+++ b/CRB/CRBSetup.c
@@ -0,0 +1,114 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBSetup.c 1     2/12/12 10:38p Victortu $
+//
+// $Revision: 1 $
+//
+// $Date: 2/12/12 10:38p $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBSetup.c $
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBSetup.c
+//
+// Description: Chipset Reference Board Setup Routines
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+//---------------------------------------------------------------------------
+// Include(s)
+//---------------------------------------------------------------------------
+
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include <Setup.h>
+#include <SetupStrTokens.h>
+#include <Protocol\PciIo.h>
+#include <Protocol\DevicePath.h>
+#include <Protocol\PciRootBridgeIo.h>
+
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+// Macro Definition(s)
+
+// Type Definition(s)
+
+// Function Prototype(s)
+
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+
+// GUID Definition(s)
+
+// Protocol Definition(s)
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//---------------------------------------------------------------------------
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InitCRBStrings
+//
+// Description: Initializes Demo Board Setup String.
+//
+// Input:       HiiHandle - Handle to HII database
+//              Class     - Indicates the setup class
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID InitCRBStrings (
+    IN EFI_HII_HANDLE   HiiHandle,
+    IN UINT16           Class )
+{
+    EFI_STATUS          Status = EFI_SUCCESS;
+
+    if (Class == ADVANCED_FORM_SET_CLASS) {
+        
+    }
+}
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBSmi.DXS b/CRB/CRBSmi.DXS
new file mode 100644
index 0000000..ff918a5
--- /dev/null
+++ b/CRB/CRBSmi.DXS
@@ -0,0 +1,59 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBSmi.DXS 1     2/12/12 10:38p Victortu $
+//
+// $Revision: 1 $
+//
+// $Date: 2/12/12 10:38p $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBSmi.DXS $
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBSMI.DXS
+//
+// Description: This file is the dependency file for the CRB SMI driver.
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+#include <Protocol\BootScriptSave.h>
+#include <Protocol\SmmSwDispatch.h>
+
+DEPENDENCY_START
+    EFI_BOOT_SCRIPT_SAVE_GUID AND
+    EFI_SMM_SW_DISPATCH_PROTOCOL_GUID
+DEPENDENCY_END
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBSmi.c b/CRB/CRBSmi.c
new file mode 100644
index 0000000..208a0eb
--- /dev/null
+++ b/CRB/CRBSmi.c
@@ -0,0 +1,418 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBSmi.c 2     4/16/13 5:29a Thomaschen $
+//
+// $Revision: 2 $
+//
+// $Date: 4/16/13 5:29a $
+//*************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBSmi.c $
+// 
+// 2     4/16/13 5:29a Thomaschen
+// 
+// 1     2/12/12 10:38p Victortu
+// Intel SharkBay CRB initially releases.
+// 
+//*************************************************************************
+//<AMI_FHDR_START>
+//
+// Name:        CRBSMI.c
+//
+// Description: This file contains code for all CRB SMI events
+//
+//<AMI_FHDR_END>
+//*************************************************************************
+
+//---------------------------------------------------------------------------
+// Include(s)
+//---------------------------------------------------------------------------
+
+#include <Token.h>
+#include <AmiDxeLib.h>
+#include <AmiCspLib.h>
+
+// Produced Protocols
+
+// Consumed Protocols
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+#include <Protocol\S3SmmSaveState.h>
+#include <Protocol\SmmBase2.h>
+#include <Protocol\SmmSwDispatch2.h>
+#include <Protocol\SmmSxDispatch2.h>
+#else
+#include <Protocol\SmmBase.h>
+#include <Protocol\SmmSwDispatch.h>
+#include <Protocol\SmmSxDispatch.h>
+#endif
+
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+#define CRB_S3_SAVE_PROTOCOL         EFI_S3_SAVE_STATE_PROTOCOL
+#define CRB_SMM_SW_DISPATCH_PROTOCOL EFI_SMM_SW_DISPATCH2_PROTOCOL
+#define CRB_SMM_SW_DISPATCH_CONTEXT  EFI_SMM_SW_REGISTER_CONTEXT
+#define CRB_SMM_SX_DISPATCH_PROTOCOL EFI_SMM_SX_DISPATCH2_PROTOCOL
+#define CRB_SMM_SX_DISPATCH_CONTEXT  EFI_SMM_SX_REGISTER_CONTEXT
+#define SMM_CHILD_DISPATCH_SUCCESS   EFI_SUCCESS
+#else
+#define CRB_S3_SAVE_PROTOCOL         EFI_BOOT_SCRIPT_SAVE_PROTOCOL
+#define CRB_SMM_SW_DISPATCH_PROTOCOL EFI_SMM_SW_DISPATCH_PROTOCOL
+#define CRB_SMM_SW_DISPATCH_CONTEXT  EFI_SMM_SW_DISPATCH_CONTEXT
+#define CRB_SMM_SX_DISPATCH_PROTOCOL EFI_SMM_SX_DISPATCH_PROTOCOL
+#define CRB_SMM_SX_DISPATCH_CONTEXT  EFI_SMM_SX_DISPATCH_CONTEXT
+#define SMM_CHILD_DISPATCH_SUCCESS
+#endif
+
+// Macro Definition(s)
+
+// Type Definition(s)
+
+// Function Prototype(s)
+
+//---------------------------------------------------------------------------
+// Variable and External Declaration(s)
+//---------------------------------------------------------------------------
+// Variable Declaration(s)
+
+CRB_S3_SAVE_PROTOCOL *gBootScriptSave = NULL;
+
+// GUID Definition(s)
+
+// Protocol Definition(s)
+
+// External Declaration(s)
+
+// Function Definition(s)
+
+//---------------------------------------------------------------------------
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   GetCRBSmiContext
+//
+// Description: This is a template CRB SMI GetContext for Porting.
+//
+// Input:       None
+//
+// Output:      None
+//
+// Notes:       Here is the control flow of this function:
+//              1. Check if CRB Smi source.
+//              2. If yes, return TRUE.
+//              3. If not, return FALSE.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+BOOLEAN GetCRBSmiContext (VOID)
+{
+    // Porting if needed
+    return FALSE;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CRBSmiHandler
+//
+// Description: This is a template CRB SMI Handler for Porting.
+//
+// Input:       None
+//
+// Output:      None
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+VOID CRBSmiHandler (VOID)
+{
+    // Porting if needed
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CRBSwSmiHandler
+//
+// Description: This is a template CRB software SMI Handler for Porting.
+//
+// Input:       PI 0.91, 1.0
+//                  DispatchHandle   - SMI dispatcher handle
+//                  *DispatchContext - Pointer to the dispatch context
+//              PI 1.1, 1.2
+//                  DispatchHandle  - SMI dispatcher handle
+//                  *DispatchContext- Points to an optional S/W SMI context
+//                  CommBuffer      - Points to the optional communication
+//                                    buffer
+//                  CommBufferSize  - Points to the size of the optional
+//                                    communication buffer
+//
+// Output:      EFI_STATUS if the new SMM PI is applied.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+EFI_STATUS CRBSwSmiHandler (
+	IN EFI_HANDLE       DispatchHandle,
+	IN CONST VOID       *DispatchContext OPTIONAL,
+	IN OUT VOID         *CommBuffer OPTIONAL,
+	IN OUT UINTN        *CommBufferSize OPTIONAL )
+#else
+VOID CRBSwSmiHandler (
+    IN EFI_HANDLE                   DispatchHandle,
+    IN EFI_SMM_SW_DISPATCH_CONTEXT  *DispatchContext )
+#endif
+{
+    // Porting if needed
+    return SMM_CHILD_DISPATCH_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CRBSxSmiHandler
+//
+// Description: This is a template CRB Sx SMI Handler for Porting.
+//
+// Input:       PI 0.91, 1.0
+//                  DispatchHandle   - SMI dispatcher handle
+//                  *DispatchContext - Pointer to the dispatch context
+//              PI 1.1, 1.2
+//                  DispatchHandle  - SMI dispatcher handle
+//                  *DispatchContext- Points to an optional Sx SMI context
+//                  CommBuffer      - Points to the optional communication
+//                                    buffer
+//                  CommBufferSize  - Points to the size of the optional
+//                                    communication buffer
+//
+// Output:      EFI_STATUS if the new SMM PI is applied.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+EFI_STATUS CRBSxSmiHandler (
+	IN EFI_HANDLE       DispatchHandle,
+	IN CONST VOID       *DispatchContext OPTIONAL,
+	IN OUT VOID         *CommBuffer OPTIONAL,
+	IN OUT UINTN        *CommBufferSize OPTIONAL )
+#else
+VOID CRBSxSmiHandler (
+    IN EFI_HANDLE                   DispatchHandle,
+    IN EFI_SMM_SX_DISPATCH_CONTEXT  *DispatchContext )
+#endif
+{
+    // Porting if needed
+    return SMM_CHILD_DISPATCH_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   CRBChildDispatcher
+//
+// Description: This is an entry for CRB SMM Child Dispatcher Handler.
+//
+// Input:       PI 0.91, 1.0
+//                  SmmImageHandle       - SMI Image Hander
+//                  *CommunicationBuffer - Pointer to optional communication 
+//                                         buffer                            
+//                  *SourceSize          - Pointer to size of communication 
+//                                         buffer                           
+//              PI 1.1, 1.2
+//                  DispatchHandle  - SMI dispatcher handle
+//                  *DispatchContext- Pointer to the dispatched context
+//                  CommBuffer      - Pointer to a collection of data in
+//                                    memory that will be conveyed from a
+//                                    non-SMM environment into an SMM 
+//                                    environment 
+//                  CommBufferSize  - Pointer to the size of the CommBuffer
+//
+// Output:      EFI_STATUS
+//                  EFI_HANDLER_SUCCESS
+//
+// Referrals:   GetCRBSmiContext, CRBSmiHandler 
+//
+// Notes:       Here is the control flow of this function:
+//              1. Read SMI source status registers.
+//              2. If source, call handler.
+//              3. Repeat #2 for all sources registered.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS CRBChildDispatcher (
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+    IN EFI_HANDLE       DispatchHandle,
+	IN CONST VOID       *DispatchContext OPTIONAL,
+	IN OUT VOID         *CommBuffer OPTIONAL,
+	IN OUT UINTN        *CommBufferSize OPTIONAL )
+#else
+    IN EFI_HANDLE   SmmImageHandle,
+    IN OUT VOID     *CommunicationBuffer OPTIONAL,
+    IN OUT UINTN    *SourceSize OPTIONAL )
+#endif
+{
+    if (GetCRBSmiContext()) CRBSmiHandler();
+
+    return EFI_HANDLER_SUCCESS;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InSmmFunction
+//
+// Description: Installs CRB SMM Child Dispatcher Handler.
+//
+// Input:       ImageHandle - Image handle
+//              *SystemTable - Pointer to the system table
+//
+// Output:      EFI_STATUS
+//                  EFI_NOT_FOUND - The SMM Base protocol is not found.
+//                  EFI_SUCCESS   - Installs CRB SMM Child Dispatcher Handler
+//                                  successfully.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS InSmmFunction (
+    IN EFI_HANDLE           ImageHandle,
+    IN EFI_SYSTEM_TABLE     *SystemTable )
+{
+    EFI_STATUS                   Status;
+    CRB_SMM_SW_DISPATCH_PROTOCOL *pSwDispatch;
+    CRB_SMM_SX_DISPATCH_PROTOCOL *pSxDispatch;
+    CRB_SMM_SW_DISPATCH_CONTEXT  SwContext = {CRB_SWSMI};
+    CRB_SMM_SX_DISPATCH_CONTEXT  SxContext = {SxS3, SxEntry};
+    EFI_HANDLE                   Handle;
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+    EFI_HANDLE                   RootHandle;
+#else
+    EFI_SMM_BASE_PROTOCOL        *SmmBaseProtocol;
+#endif
+
+#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A)
+    Status = InitAmiSmmLib( ImageHandle, SystemTable );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status  = pSmst->SmmLocateProtocol( &gEfiSmmSwDispatch2ProtocolGuid, \
+                                        NULL, \
+                                        &pSwDispatch );
+    if (!EFI_ERROR(Status)) {
+        Status  = pSwDispatch->Register( pSwDispatch, \
+                                         CRBSwSmiHandler, \
+                                         &SwContext, \
+                                         &Handle );
+    }
+
+    Status  = pSmst->SmmLocateProtocol( &gEfiSmmSxDispatch2ProtocolGuid, \
+                                        NULL, \
+                                        &pSxDispatch );
+    if (!EFI_ERROR(Status)) {
+        Status  = pSxDispatch->Register( pSxDispatch, \
+                                         CRBSxSmiHandler, \
+                                         &SxContext, \
+                                         &Handle );
+    }
+
+    Status = pSmst->SmmLocateProtocol( &gEfiS3SmmSaveStateProtocolGuid, \
+                                       NULL, \
+                                       &gBootScriptSave );
+    ASSERT_EFI_ERROR(Status);
+
+    Status  = pSmst->SmiHandlerRegister( CRBChildDispatcher, \
+                                         NULL, \
+                                         &RootHandle );
+#else
+    Status = pBS->LocateProtocol( &gEfiSmmBaseProtocolGuid, \
+                                  NULL, \
+                                  &SmmBaseProtocol );
+    if (EFI_ERROR(Status)) return Status;
+
+    Status  = pBS->LocateProtocol( &gEfiSmmSwDispatchProtocolGuid, \
+                                   NULL, \
+                                   &pSwDispatch );
+    if (!EFI_ERROR(Status)) {
+        Status  = pSwDispatch->Register( pSwDispatch, \
+                                         CRBSwSmiHandler, \
+                                         &SwContext, \
+                                         &Handle );
+    }
+
+    Status = pBS->LocateProtocol( &gEfiSmmSxDispatchProtocolGuid, \
+                                  NULL, \
+                                  &pSxDispatch );
+    if (!EFI_ERROR(Status)) {
+        Status  = pSxDispatch->Register( pSxDispatch, \
+                                         CRBSxSmiHandler, \
+                                         &SxContext, \
+                                         &Handle );
+    }
+
+    Status = pBS->LocateProtocol( &gEfiBootScriptSaveGuid, \
+                                  NULL, \
+                                  &gBootScriptSave );
+    ASSERT_EFI_ERROR(Status);
+
+    //Register call backs
+    Status = SmmBaseProtocol->RegisterCallback( SmmBaseProtocol, \
+                                                ImageHandle, \
+                                                CRBChildDispatcher, \
+                                                FALSE, \
+                                                FALSE );
+#endif
+    return Status;
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+//
+// Procedure:   InitializeCRBSmm
+//
+// Description: Installs CRB SMM Child Dispatcher Handler.
+//
+// Input:       ImageHandle - Image handle
+//              *SystemTable - Pointer to the system table
+//
+// Output:      EFI_STATUS
+//                  EFI_NOT_FOUND - The SMM Base protocol is not found.
+//                  EFI_SUCCESS   - Installs CRB SMM Child Dispatcher Handler
+//                                  successfully.
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS InitializeCRBSmm (
+    IN EFI_HANDLE           ImageHandle,
+    IN EFI_SYSTEM_TABLE     *SystemTable )
+{
+    InitAmiLib(ImageHandle, SystemTable);
+    return InitSmmHandler(ImageHandle, SystemTable, InSmmFunction, NULL);
+}
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2013, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBTse.c b/CRB/CRBTse.c
new file mode 100644
index 0000000..db21975
--- /dev/null
+++ b/CRB/CRBTse.c
@@ -0,0 +1,209 @@
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2014, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
+//*************************************************************************
+// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CRBTse.c 1     3/17/14 2:36a Chaseliu $Revision:
+//
+// $Date: 3/17/14 2:36a $Log:
+// 
+//*************************************************************************
+#include "Efi.h"
+#include "token.h"
+#include <AmiLib.h>
+#include <AmiDxeLib.h>
+#include "Protocol\PciIo.h"
+#include "Protocol\DevicePath.h"
+#include "protocol\DriverBinding.h"
+#include "protocol\BlockIo.h"
+#include "Protocol\PDiskInfo.h"
+#include "Protocol\PIDEController.h"
+#include "Protocol\PIDEBus.h"
+#include "Protocol\PAhciBus.h"
+#include "Protocol\PIDEBus.h"
+#include <Setup.h>
+
+
+#define     SecurityEnabledMask         0x0002
+
+
+EFI_RUNTIME_SERVICES  *gRT;
+EFI_BOOT_SERVICES     *gBS;
+
+UINT8   Satamode=0;
+UINT8   GetVariableError=0;
+
+// Produced Protocols
+
+// Consumed Protocols
+
+//---------------------------------------------------------------------------
+// Constant, Macro and Type Definition(s)
+//---------------------------------------------------------------------------
+// Constant Definition(s)
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   GetSetupSataMode
+//
+// Description: Gets the sata mode before entering Setup and Store in Satamode.
+//              Global Variable.
+//
+// Input:       VOID
+//
+// Output:      VOID
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+GetSetupSataMode( )
+{
+
+    UINT32      SetupDataAttributes = 0;
+    UINTN       SetupDataSize = sizeof(SETUP_DATA);
+    SETUP_DATA  SetupData;
+    EFI_GUID    gSetupGuid = SETUP_GUID;
+    EFI_STATUS  Status;
+
+    Status = gRT->GetVariable(L"Setup", &gSetupGuid, &SetupDataAttributes,
+                                &SetupDataSize, &SetupData);
+
+    if(EFI_ERROR(Status)){
+        GetVariableError = 1;
+        return;
+    }
+    //
+    // Store the SataMode before going to setup.
+    //    
+    Satamode = SetupData.SataInterfaceMode;
+
+    return;
+
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   IssueColdReset
+//
+// Description: Issues cold reset.
+//
+// Input:       VOID
+//
+// Output:      VOID
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+IssueColdReset( )
+{
+    IoWrite8(0xcf9, 0xE);
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Procedure:   CheckForChangeinSataMode
+//
+// Description: Gets the sata mode when exiting and resetting from
+//              setup and checks whether sata mode is changed. If changed it
+//              issues cold reset. Satamode(Value got before entering setup) is 
+//              Stored in Satamode_Before_Setup.
+//
+// Input:       VOID
+//
+// Output:      VOID
+//
+//----------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+CheckForChangeinSataMode( )
+{
+
+    UINT32      SetupDataAttributes = 0;
+    UINTN       SetupDataSize = sizeof(SETUP_DATA);
+    EFI_GUID    gSetupGuid = SETUP_GUID;
+    UINTN       Count;
+    EFI_HANDLE  *HandleBuffer = NULL;
+    UINT16      SecurityStatus = 0;
+    EFI_STATUS  Status;
+    UINT8       i;
+    IDE_SECURITY_PROTOCOL *Security = NULL;
+    EFI_GUID    gIDESecurityProtocolGuid    = IDE_SECURITY_INTERFACE_GUID;
+    UINT8       Satamode_Before_Setup = Satamode;
+
+    
+    if(GetVariableError) {
+        return;
+    }
+
+    //
+    // Get the Setupdata.
+    //
+    GetSetupSataMode();
+    
+    //
+    // Check for change in the satamode selection in  setup.if yes, issue cold reset.
+    //
+    if( Satamode_Before_Setup != Satamode) {
+        //
+        // Check all HDD, if Password is installed in anyone of the HDD, issue cold reset.
+        //
+        Status = gBS->LocateHandleBuffer(ByProtocol,
+                                         &gIDESecurityProtocolGuid,
+                                         NULL,
+                                         &Count,
+                                         &HandleBuffer);
+
+        if(EFI_ERROR(Status)) {
+            return;
+        }
+
+        for(i = 0; i < Count; i++) {
+
+            Status = gBS->HandleProtocol(HandleBuffer[i], &gIDESecurityProtocolGuid, &Security);
+            if(EFI_ERROR(Status)) {
+                return;
+            }
+
+            //
+            // Get the security status of the device, to check whether password is installed.
+            //
+            Status = Security->ReturnSecurityStatus( Security, &SecurityStatus );
+            if(EFI_ERROR(Status)) {
+                return;
+            }
+
+            if( SecurityStatus & SecurityEnabledMask ) {
+                //
+                // Issue Cold Reset.
+                //
+                IssueColdReset();
+            }
+        }
+
+        gBS->FreePool(HandleBuffer);
+    }
+
+    return;
+}
+
+//*************************************************************************
+//*************************************************************************
+//**                                                                     **
+//**        (C)Copyright 1985-2014, American Megatrends, Inc.            **
+//**                                                                     **
+//**                       All Rights Reserved.                          **
+//**                                                                     **
+//**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+//**                                                                     **
+//**                       Phone: (770)-246-8600                         **
+//**                                                                     **
+//*************************************************************************
+//*************************************************************************
diff --git a/CRB/CRBoard.cif b/CRB/CRBoard.cif
new file mode 100644
index 0000000..91c41b8
--- /dev/null
+++ b/CRB/CRBoard.cif
@@ -0,0 +1,26 @@
+<component>
+	name = "Chipset Reference Board - Shark Bay"
+	category = eBoard
+	LocalRoot = "CRB\"
+	RefName = "CRB"
+    Rank = 59
+[files]
+"CSP.sdl"	
+"CRB.sdl"	
+"CRB.mak"	
+"CRB.sd"	
+"CRB.uni"	
+"CRBSec.ASM"	
+"CRBPei.c"	
+"CRBDxe.c"	
+"CRBSmi.c"	
+"CRBLib.h"	
+"CRBLib.c"	
+"CRBSetup.c"	
+"CRBAcpi.c"	
+"CRBTse.c"
+"CRBPei.DXS"	
+"CRBDxe.DXS"	
+"CRBSmi.DXS"	
+"VBT_5.0.1035_FC.BIN"	
+<endComponent>
diff --git a/CRB/CSP.sdl b/CRB/CSP.sdl
new file mode 100644
index 0000000..bfb10be
--- /dev/null
+++ b/CRB/CSP.sdl
@@ -0,0 +1,368 @@
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
+
+#*************************************************************************
+# $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CSP.sdl 5     4/24/13 2:49a Thomaschen $
+#
+# $Revision: 5 $
+#
+# $Date: 4/24/13 2:49a $
+#*************************************************************************
+# Revision History
+# ----------------
+# $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/CRB/CSP.sdl $
+# 
+# 5     4/24/13 2:49a Thomaschen
+# add token "USB_CONTROLLERS_WITH_RMH"
+# 
+# 4     12/13/12 4:02a Wesleychen
+# EIP#108566: Fixed ME will not work under debug mode.
+# 
+# 2     11/21/12 6:10a Wesleychen
+# Fix FV_BB size over 1MB cannot boot.
+# 
+# 1     2/12/12 10:38p Victortu
+# Intel SharkBay CRB initially releases.
+# 
+#*************************************************************************
+TOKEN
+	Name  = "USB_UHCI"
+	Value  = "0"
+	Help  = "Maximum number of UHCI controllers present in the system"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0-6"
+End
+
+TOKEN
+	Name  = "USB_EHCI"
+	Value  = "2"
+	Help  = "Maximum number of EHCI controllers present in the system"
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0-6"
+End
+
+TOKEN
+	Name  = "USB_XHCI"
+	Value  = "1"
+	Help  = "Maximum number of supported XHCI controllers"
+	TokenType = Integer
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "XHCI_EVENT_SERVICE_MODE"
+	Value  = "0"
+	Help  = "This token controlls xHCI event service mode.\0 - Use periodic timer SMI.\1 - Use xHCI hardware SMI.\2 - Both periodic timer SMI and se xHCI hardware SMI."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0..2"
+End
+
+TOKEN
+	Name  = "USB_XHCI_EXT_HW_SMI_PINS"
+	Value  = "255"
+	Help  = "List of xHCI GPI bit offset in the following format: GPI0, GPI1,...,GPIN.\Use 0xFF (255) to ignore the settings."
+	TokenType = Expression
+	TargetH = Yes
+	Range  = "0..31"
+	Token = "XHCI_EVENT_SERVICE_MODE" "!=" "0"
+End
+
+TOKEN
+	Name  = "EHCI_PCI_DEVICES"
+	Value  = "{0xD0, 0x20}, {0xE8, 0x20}"
+	Help  = "List of supported EHCI controllers in the following format: {dev1, 0}, {dev2, 0},...,{devN, 0}\dev represents the location of EHCI controller on PCI bus: dev = Bus << 8 + Dev << 3 + Func. Value followed by dev is the PCI device interface, for EHCI it must be 0x20.\Note: number of pairs {dev, 0} must not be less than a number of supported UHCI controllers specified in USB_UHCI token."
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "XHCI_PCI_DEVICES"
+	Value  = "{0xA0, 0x30}"
+	Help  = "List of supported onchip XHCI controllers in the following format: {dev1, 0}, {dev2, 0},...,{devN, 0}\dev represents the location of XHCI controller on PCI bus: dev = Bus << 8 + Dev << 3 + Func. Value followed by dev is the PCI device interface, for XHCI it must be 0x30.\Note: number of pairs {dev, 0} must not be less than a number of supported EHCI controllers specified in USB_XHCI token."
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "UHCI_PCI_DEVICES"
+	Value  = "{0xD0, 0}, {0xD1, 0}, {0xD2, 0}, {0xD3, 0}, {0xE8, 0}, {0xE9, 0}, {0xEA, 0}, {0xEB, 0}, {0xEC, 0}"
+	Help  = "List of supported UHCI controllers in the following format: {dev1, 0}, {dev2, 0},...,{devN, 0}\dev represents the location of UHCI controller on PCI bus: dev = Bus << 8 + Dev << 3 + Func. Value followed by dev is the PCI device interface, for UHCI it must be 0.\Note: number of pairs {dev, 0} must not be less than a number of supported UHCI controllers specified in USB_UHCI token."
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+        Name  = "USB_CONTROLLERS_WITH_RMH"
+        Value  = "{0x8086, 0x8C26}, {0x8086, 0x8C2D}" # for Intel Lynx Point
+        Help  = "List of USB controllers that have integrated USB 2.0 Rate Matching Hubs (RMH) in the following format: {vid1, did1}, {vid2, did2}"
+        TokenType = Expression
+        TargetH = Yes
+End
+
+TOKEN
+	Name  = "PEI_EHCI_PCI_BDFS"
+	Value  = "{0x1A0000, 0x1D0000}"
+	Help  = "List of supported EHCI controllers in the following format: {devfunc1, devfunc2,...,devfuncN}\devfunc represents the location of UHCI controller on PCI bus: dev = Bus << 24 + Dev << 16 + Func << 8. Value followed by dev is the PCI device interface, for UHCI it must be 0.\Note: number of entries {devfunc} must not be less than a number of supported EHCI controllers specified in PEI_NUM_EHCI token."
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PEI_UHCI_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable UHCI Controller support for USB recovery"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PEI_EHCI_SUPPORT"
+	Value  = "1"
+	Help  = "Main switch to enable EhciPei support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PEI_UHCI_PCI_DEVICES"
+	Value  = "{0x1A0000, 0x1A0100, 0x1A0200, 0x1D0000, 0x1D0100, 0x1D0200, 0x1D0300}"
+	Help  = "List of supported UHCI controllers in the following format: {devfunc1, devfunc2,...,devfuncN}\devfunc represents the location of UHCI controller on PCI bus: dev = Bus << 24 + Dev << 16 + Func << 8. Value followed by dev is the PCI device interface, for UHCI it must be 0.\Note: number of entries {devfunc} must not be less than a number of supported UHCI controllers specified in PEI_NUM_UHCI token."
+	TokenType = Expression
+	TargetH = Yes
+	Token = "PEI_UHCI_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "PEI_EHCI_PCI_BDFS"
+	Value  = "{0x1A0000, 0x1D0000}"
+	Help  = "List of supported EHCI controllers in the following format: {devfunc1, devfunc2,...,devfuncN}\devfunc represents the location of EHCI controller on PCI bus: dev = Bus << 24 + Dev << 16 + Func << 8. Value followed by dev is the PCI device interface, for EHCI it must be 0.\Note: number of entries {devfunc} must not be less than a number of supported EHCI controllers specified in PEI_NUM_EHCI token."
+	TokenType = Expression
+	TargetH = Yes
+	Token = "PEI_EHCI_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "PEI_EHCI_MEM_BASE_ADDRESSES"
+	Value  = "{$(EHCI_MMIO_BASE_ADDRESS1), $(EHCI_MMIO_BASE_ADDRESS2)}"
+	Help  = "List of supported EHCI controllers in the following format: {devfunc1, devfunc2,...,devfuncN}\devfunc represents the location of UHCI controller on PCI bus: dev = Bus << 24 + Dev << 16 + Func << 8. Value followed by dev is the PCI device interface, for UHCI it must be 0.\Note: number of entries {devfunc} must not be less than a number of supported EHCI controllers specified in USB_EHCI token."
+	TokenType = Expression
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SMM_CACHE_SUPPORT"
+	Value  = "1"
+	Help  = "Enable/disable SMM Cache Support"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "FWHFlash_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable FWH Flash support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "LPCFlash_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable LPC Flash support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "CMOS_USES_STANDARD_BATTERY_TEST"
+	Value  = "0"
+	Help  = "Specifies whether or not to use CMOS Manager's default battery test function.  If a platform provides a different battery test function this token should be disabled."
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "MAX_MANAGED_CMOS_ADDRESS"
+	Value  = "256"
+	Help  = "Last CMOS address + 1 use to specify the maximum address that is manages by CMOS Manager"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "SW_IRQ_GENERATION_REG"
+	Value  = "$(PM_BASE_ADDRESS)+0x70"
+	Help  = "Software IRQ generation regsiter from SB to generate the IRQ12 and IRQ1."
+	TokenType = Integer
+	TargetH = Yes
+	Token = "IRQ_EMUL_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "IODECODETYPE"
+	Value  = "0"
+	Help  = "Check project actually who does IODecode Implement by :\1 - decode by OEM porting with eLink function(default),\0 - decode by chipset porting in SBGeneric.c"
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "DUTY_OFFSET_VAL"
+	Value  = "0"
+	Help  = "The zero-based index of where the processor�s duty cycle setting is within the processor�s P_CNT register.\(for more information, ACPI SPEC)."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0-0xf0"
+End
+
+TOKEN
+	Name  = "DUTY_WIDTH_VAL"
+	Value  = "0"
+	Help  = "The bit width of the processor�s duty cycle setting value in the P_CNT register. Each processor�s duty cycle setting\allows the software to select a nominal processor frequency below its absolute frequency.\(for more information, ACPI SPEC)."
+	TokenType = Integer
+	TargetH = Yes
+	Range  = "0-0xff: depends on 'duty_offset'"
+End
+
+TOKEN
+	Name  = "RESET_RUNTIME_SERVICES_SUPPORT"
+	Value  = "0"
+	Help  = "If ON includes in project CORE implementation of reset \services (from TimeAndReset.c). \Set to OFF to use stand alone reset driver."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+	Token = "PchReset_SUPPORT" "=" "1"
+End
+
+TOKEN
+	Name  = "RTC_RUNTIME_SERVICES_SUPPORT"
+	Value  = "1"
+	Help  = "If ON includes in project CORE implementation of RTC \services (from TimeAndReset.c). \Set to OFF to use stand alone RTC driver."
+	TokenType = Boolean
+	TargetMAK = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CODE_CACHE_SIZE"
+	Value  = "0x100000"
+	Help  = "Code Cache Size in SEC phase\This size must a multiple of 4k and must be 2^n size. Caching the entire flash will cause cache line evictions."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "TOTAL_FV_BB_SIZE"
+	Value  = "$(FV_BB_BLOCKS)*$(FLASH_BLOCK_SIZE)"
+	Help  = "Total FV_BB size in byte."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "CODE_CACHE_PART2_SIZE"
+	Value  = "$(TOTAL_FV_BB_SIZE)-$(CODE_CACHE_SIZE)"
+	Help  = "Turn on CODE_CACHE_PART2 when FV_BB size > CODE_CACHE_SIZE.\Code Cache PART 2 Size ."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+	Token = "TOTAL_FV_BB_SIZE" ">" "0x100000"
+End
+
+TOKEN
+	Name  = "CODE_CACHE_PART2_BASE"
+	Value  = "0xffffffff-($(CODE_CACHE_SIZE)+$(CODE_CACHE_PART2_SIZE))+1"
+	Help  = "Turn on CODE_CACHE_PART2 when FV_BB size > CODE_CACHE_SIZE.\Code Cache PART 2 Base Address. 0 = No PART 2"
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+	Token = "TOTAL_FV_BB_SIZE" ">" "0x100000"
+End
+
+TOKEN
+	Name  = "NO_OF_PHYSICAL_MEMORY_ARRAY"
+	Value  = "$(MEMORY_ARRAY_NUM)"
+	Help  = "Specifies the Total number of Physical Arrays in the System."
+	TokenType = Integer
+	TargetEQU = Yes
+	TargetH = Yes
+	Range  = "1 - 5"
+End
+
+TOKEN
+	Name  = "ME_IGNITION_FW_MSG_SUPPORT"
+	Value  = "0"
+	Help  = "Enable this Token to Show Ignition FW status during POST"
+	TokenType = Boolean
+	TargetH = Yes
+End
+
+TOKEN
+	Name  = "PowerButton_SUPPORT"
+	Value  = "0"
+	Help  = "Main switch to enable PowerButton support in Project"
+	TokenType = Boolean
+	TargetEQU = Yes
+	TargetMAK = Yes
+End
+
+TOKEN
+	Name  = "LIBEXE"
+	Value  = "$(SILENT)LINK /LIB"
+	TokenType = Expression
+	TargetMAK = Yes
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\UsbBotPeim.ffs"
+	Parent  = "FV_BB"
+	Token = "UsbRecov_SUPPORT" "=" "1"
+	InvokeOrder = BeforeParent
+End
+
+ELINK
+	Name  = "$(BUILD_DIR)\Recovery.ffs"
+	Parent  = "FV_BB"
+	Token = "Recovery_SUPPORT" "=" "1"
+	InvokeOrder = BeforeParent
+End
+
+#*************************************************************************
+#*************************************************************************
+#**                                                                     **
+#**        (C)Copyright 1985-2011, American Megatrends, Inc.            **
+#**                                                                     **
+#**                       All Rights Reserved.                          **
+#**                                                                     **
+#**      5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093           **
+#**                                                                     **
+#**                       Phone: (770)-246-8600                         **
+#**                                                                     **
+#*************************************************************************
+#*************************************************************************
diff --git a/CRB/VBT_5.0.1035_FC.BIN b/CRB/VBT_5.0.1035_FC.BIN
new file mode 100644
index 0000000..a6bf335
--- /dev/null
+++ b/CRB/VBT_5.0.1035_FC.BIN
author	raywu <raywu0301@gmail.com>	2018-06-15 00:00:50 +0800
committer	raywu <raywu0301@gmail.com>	2018-06-15 00:00:50 +0800
commit	b7c51c9cf4864df6aabb99a1ae843becd577237c (patch)
tree	eebe9b0d0ca03062955223097e57da84dd618b9a /CRB
download	zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz