diff options
| author | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
|---|---|---|
| committer | raywu <raywu0301@gmail.com> | 2018-06-15 00:00:50 +0800 |
| commit | b7c51c9cf4864df6aabb99a1ae843becd577237c (patch) | |
| tree | eebe9b0d0ca03062955223097e57da84dd618b9a /Chipset/NB | |
| download | zprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz | |
Diffstat (limited to 'Chipset/NB')
58 files changed, 20469 insertions, 0 deletions
diff --git a/Chipset/NB/GOP/Haswell/IntelGopDriver.efi b/Chipset/NB/GOP/Haswell/IntelGopDriver.efi Binary files differnew file mode 100644 index 0000000..04f8cc0 --- /dev/null +++ b/Chipset/NB/GOP/Haswell/IntelGopDriver.efi diff --git a/Chipset/NB/GOP/Haswell/vbt.bin b/Chipset/NB/GOP/Haswell/vbt.bin Binary files differnew file mode 100644 index 0000000..0fca66b --- /dev/null +++ b/Chipset/NB/GOP/Haswell/vbt.bin diff --git a/Chipset/NB/GOP/IntelGopDriver.dxs b/Chipset/NB/GOP/IntelGopDriver.dxs new file mode 100644 index 0000000..40408e8 --- /dev/null +++ b/Chipset/NB/GOP/IntelGopDriver.dxs @@ -0,0 +1,61 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelGopDriver.dxs 2 1/27/15 11:17p Dennisliu $ +// +// $Revision: 2 $ +// +// $Date: 1/27/15 11:17p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelGopDriver.dxs $ +// +// 2 1/27/15 11:17p Dennisliu +// [TAG] EIP202457 +// [Category] Improvement +// [Description] Implement Loading Intel GOP driver Condition +// [Files] +// Chipset\NB\GOP\IntelGopDriver.dxs +// Chipset\NB\GOP\IntelSaGopDriver.mak +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelGopDriver.dxs +// +// Description: Dependency expression file for Intel GOP driver. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <Protocol\IntelSaGopDriver.h> + +DEPENDENCY_START + EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2015, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopDriver.cif b/Chipset/NB/GOP/IntelSaGopDriver.cif new file mode 100644 index 0000000..4b181d4 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopDriver.cif @@ -0,0 +1,17 @@ +<component> + name = "Intel SA GOP Driver" + category = ModulePart + LocalRoot = "Chipset\NB\GOP\" + RefName = "IntelSaGopDriver" +[files] +"IntelSaGopDriver.sdl" +"IntelSaGopDriver.mak" +"IntelSaGopPolicy.c" +"IntelSaGopDriver.dxs" +"IntelGopDriver.dxs" +"Haswell\IntelGopDriver.efi" +"Haswell\vbt.bin" +[parts] +"IntelSaGopSetup" +"IntelSaGopDriverProtocol" +<endComponent> diff --git a/Chipset/NB/GOP/IntelSaGopDriver.dxs b/Chipset/NB/GOP/IntelSaGopDriver.dxs new file mode 100644 index 0000000..9074cbc --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopDriver.dxs @@ -0,0 +1,61 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopDriver.dxs 1 3/08/12 10:54p Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 3/08/12 10:54p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopDriver.dxs $ +// +// 1 3/08/12 10:54p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopDriver.dxs +// +// Description: Dependency expression file for Platform GOP Policy driver. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <Protocol\CpuIo.h> +#include <PlatformInfo.h> + +DEPENDENCY_START + EFI_CPU_IO_PROTOCOL_GUID AND + EFI_PLATFORM_INFO_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopDriver.mak b/Chipset/NB/GOP/IntelSaGopDriver.mak new file mode 100644 index 0000000..0dfa205 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopDriver.mak @@ -0,0 +1,69 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +all : IntelSaGopDriver IgbGOPDriver + +IntelSaGopDriver : $(BUILD_DIR)\IntelSaGopDriver.mak IntelSaGopDriverBin + +IgbGOPDriver: $(BUILD_DIR)\BmpDummyName.ffs $(BUILD_DIR)\IntelGopDriver.ffs + + +$(BUILD_DIR)\IntelSaGopDriver.mak : $(IntelSaGopDriver_DIR)\$(@B).cif $(IntelSaGopDriver_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(IntelSaGopDriver_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +IntelSaGopDriver_INCLUDES=\ + $(PLATFORM_INFO_INCLUDES)\ + $(DxeKscLib_INCLUDES)\ + $(INTEL_MCH_INCLUDES)\ + +IntelSaGopDriverBin : $(AMIDXELIB) $(DxeKscLib_LIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\IntelSaGopDriver.mak all\ + GUID=5c266089-e103-4d43-9ab5-12d7095be2af\ + "MY_INCLUDES=$(IntelSaGopDriver_INCLUDES)"\ + ENTRY_POINT=IntelSaGopPolicyEntryPoint\ + DEPEX1=$(IntelSaGopDriver_DIR)\IntelSaGopDriver.dxs \ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER\ + COMPRESS=1 + +$(BUILD_DIR)\BmpDummyName.ffs : $(OEM_INTEL_GOP_VBT_BIN_FILE) + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=878AC2CC-5343-46F2-B563-51F89DAF56BA \ + TYPE=EFI_FV_FILETYPE_RAW \ + RAWFILE=$** FFSFILE=$@ COMPRESS=0 NAME=BmpDummyName + +$(BUILD_DIR)\IntelGopDriver.ffs : $(OEM_INTEL_GOP_EFI_DRIVER_FILE) + $(MAKE) /f Core\FFS.mak \ + BUILD_DIR=$(BUILD_DIR) \ + GUID=5BBA83E6-F027-4ca7-BFD0-16358CC9E123 \ + TYPE=EFI_FV_FILETYPE_DRIVER \ + DEPEX1=$(IntelSaGopDriver_DIR)\IntelGopDriver.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + PEFILE=$** FFSFILE=$@ COMPRESS=0 NAME=IntelGopDriver + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopDriver.sdl b/Chipset/NB/GOP/IntelSaGopDriver.sdl new file mode 100644 index 0000000..551c88a --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopDriver.sdl @@ -0,0 +1,59 @@ +TOKEN + Name = "IntelSaGopDriver_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable IntelSaGopDriver support in Project" +End + +PATH + Name = "IntelSaGopDriver_DIR" +End + +MODULE + Help = "Includes IntelSaGopDriver.mak to Project" + File = "IntelSaGopDriver.mak" +End + +TOKEN + Name = "====== Haswell ======" + TokenType = Expression +End + +TOKEN + Name = "OEM_INTEL_GOP_VBT_BIN_FILE" + Value = "$(IntelSaGopDriver_DIR)\Haswell\Vbt.bin" + TokenType = Expression + TargetMAK = Yes +End + +TOKEN + Name = "OEM_INTEL_GOP_EFI_DRIVER_FILE" + Value = "$(IntelSaGopDriver_DIR)\Haswell\IntelGopDriver.efi" + TokenType = Expression + TargetMAK = Yes +End + +ELINK + Name = "$(BUILD_DIR)\IntelSaGopDriver.ffs" + Parent = "FV_MAIN" + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(BUILD_DIR)\IntelGopDriver.ffs" + Parent = "FV_MAIN" + InvokeOrder = BeforeParent +End + +ELINK + Name = "$(BUILD_DIR)\BmpDummyName.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + + + diff --git a/Chipset/NB/GOP/IntelSaGopPolicy.c b/Chipset/NB/GOP/IntelSaGopPolicy.c new file mode 100644 index 0000000..ccc3b8d --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopPolicy.c @@ -0,0 +1,405 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopPolicy.c 5 5/13/14 10:42p Dennisliu $ +// +// $Revision: 5 $ +// +// $Date: 5/13/14 10:42p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopPolicy.c $ +// +// 5 5/13/14 10:42p Dennisliu +// [TAG] EIP167027 +// [Category] Improvement +// [Description] [SharkBay Aptio4]Variable's attribute needs to be +// reviewed by SA component driver +// [Files] NBDXEBoard.c; IntelSaGopSetup.c; IntelSaGopPolicy.c; +// NBDxe.c; NbPciCSP.c; PciHostBridge.c; +// +// 4 10/31/12 6:33a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] Add update GOP VBT address event. +// +// 3 8/14/12 5:42a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Implemented BIOS Integration Guide Rev 1.0 to Intel SA +// GOP driver. +// [Files] IntelSaGopDriver.cif, IntelSaGopDriver.mak, +// IntelSaGopDriver.sdl, +// IntelSaGopPolicy.c, IntelSaGopSetup.c, IntelSaGopSetup.h, +// IntelSaGopSetup.mak, IntelSaGopSetup.sd, IntelSaGopSetup.sdl, +// IntelSaGopSetup.uni, IntelSaGopSwitch.c, +// IntelSaGopDriver.h, +// NBPlatformData.h +// +// 2 7/27/12 7:42a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fix building error after update 4.6.5.4_Csm_OptOut_03. +// [Files] IntelSaGopPolicy.c +// +// 1 3/08/12 10:54p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopPolicy.c +// +// Description: This file initialises and Installs TerminalPlatformPolicy Protocol. +// +//<AMI_FHDR_END> +//********************************************************************** +#include <Token.h> +#include <AmiDxeLib.h> +#include <KscLib.h> +#include <Setup.h> +#include <AmiCspLib.h> +#include <Protocol\IntelSaGopDriver.h> +#include <Protocol\NBPlatformData.h> +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +#include <AmiLoadCsmPolicy.h> +#endif +#define _SA_COMMON_DEFINITIONS_H_ +#include <Protocol\SaPlatformPolicy\SaPlatformPolicy.h> + +EFI_GUID gPlatformGOPPolicyGuid = EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID; +EFI_GUID gDxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID; +EFI_GUID gSetupGuid = SETUP_GUID; +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +EFI_GUID gAmiOpromPolicyProtocolGuid = AMI_OPROM_POLICY_PROTOCOL_GUID; +EFI_GUID gAmiLoadCsmGuid = AMI_LOAD_CSM_GUID; +#endif + +PLATFORM_GOP_POLICY_PROTOCOL mPlatformGOPPolicy; +DXE_PLATFORM_SA_POLICY_PROTOCOL *gDxePlatformSaPolicy; +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) +AMI_OPROM_POLICY_PROTOCOL *gAmiOpRomPolicyProtocol = NULL; +VOID *gInterface = NULL; +#endif +// +// Function implementations +// + +EFI_STATUS +GetPlatformLidStatus ( + OUT LID_STATUS *CurrentLidStatus +) +{ +#if defined CRB_EC_SUPPORT && CRB_EC_SUPPORT == 1 + EFI_STATUS Status; + UINT8 PortDataOut; + Status = InitializeKscLib (); + + if (Status == EFI_SUCCESS) { + Status = SendKscCommand(KSC_C_READ_MEM); + if (Status == EFI_SUCCESS) { + Status = SendKscData(0x03); + if (Status == EFI_SUCCESS) { + Status = ReceiveKscData (&PortDataOut); + if (Status == EFI_SUCCESS) { + // + // Bit6 = Lid State (1 = Open, 0 = Closed) + // + if ((PortDataOut & BIT6) >> 6) + *CurrentLidStatus = LidOpen; + else + *CurrentLidStatus = LidClosed; + return EFI_SUCCESS; + } + } + } + } +#endif + + return EFI_UNSUPPORTED; +} + +EFI_STATUS +GetVbtData ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize +) +{ + EFI_STATUS Status; + UINTN FvProtocolCount; + EFI_HANDLE *FvHandles; +#if (PI_SPECIFICATION_VERSION < 0x00010000) + EFI_FIRMWARE_VOLUME_PROTOCOL *Fv; +#else + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; +#endif + UINTN Index; + UINT32 AuthenticationStatus; + EFI_FV_FILETYPE FileType; + EFI_FV_FILE_ATTRIBUTES FileAttributes; + + UINT8 *Buffer; + UINTN VbtBufferSize; + EFI_GUID BmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA }; + + Buffer = NULL; + FvHandles = NULL; + Status = pBS->LocateHandleBuffer ( + ByProtocol, + #if (PI_SPECIFICATION_VERSION < 0x00010000) + &gEfiFirmwareVolumeProtocolGuid, + #else + &gEfiFirmwareVolume2ProtocolGuid, + #endif + NULL, + &FvProtocolCount, + &FvHandles + ); + if (!EFI_ERROR (Status)) { + for (Index = 0; Index < FvProtocolCount; Index++) { + Status = pBS->HandleProtocol ( + FvHandles[Index], + #if (PI_SPECIFICATION_VERSION < 0x00010000) + &gEfiFirmwareVolumeProtocolGuid, + #else + &gEfiFirmwareVolume2ProtocolGuid, + #endif + (VOID **) &Fv + ); + + Status = Fv->ReadFile ( + Fv, + &BmpImageGuid, + &Buffer, + &VbtBufferSize, + &FileType, + &FileAttributes, + &AuthenticationStatus + ); + + if (!EFI_ERROR (Status)) { + *VbtAddress = (EFI_PHYSICAL_ADDRESS)Buffer; + *VbtSize = (UINT32)VbtBufferSize; + Status = EFI_SUCCESS; + break; + } + } + } else { + Status = EFI_NOT_FOUND; + } + + if (FvHandles != NULL) { + pBS->FreePool (FvHandles); + FvHandles = NULL; + } + + return Status; +} + +EFI_STATUS +GetPlatformDockStatus ( + OUT DOCK_STATUS CurrentDockStatus +) +{ + + return EFI_UNSUPPORTED; +} + +VOID IntelGopVbtUpdateNotify ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS VbtAddress; + UINT32 VbtSize; + + Status = pBS->LocateProtocol ( + &gDxePlatformSaPolicyGuid, + NULL, + (VOID **) &gDxePlatformSaPolicy + ); + if (!EFI_ERROR (Status)) { + + Status = GetVbtData(&VbtAddress, &VbtSize); + if (!EFI_ERROR (Status)) { + gDxePlatformSaPolicy->IgdConfig->VbtAddress = VbtAddress; + gDxePlatformSaPolicy->IgdConfig->Size = VbtSize; + } + } + // Kill event + pBS->CloseEvent(Event); + +} + +EFI_STATUS +EFIAPI +IntelSaGopPolicyEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + +Routine Description: + + Entry point for the Platform GOP Policy Driver. + +Arguments: + + ImageHandle Image handle of this driver. + SystemTable Global system service table. + +Returns: + + EFI_SUCCESS Initialization complete. + EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver. + +--*/ +{ + EFI_STATUS Status; + NB_PLATFORM_DATA NBPlatformData = {0}; + UINTN VariableSize; + SETUP_DATA *SetupData = NULL; + EFI_EVENT DxePlatformSaPolicyEvent; + VOID *DxePlatformSaPolicyReg; + UINT32 Attributes = 0; // [ EIP167027 ] + + + InitAmiLib (ImageHandle, SystemTable); + + // Read the NB Platform Data + VariableSize = sizeof (NB_PLATFORM_DATA); + //Status = pRS->GetVariable ( // [ EIP167027 ] + // L"NBPlatformData", + // &gSetupGuid, + // NULL, + // &VariableSize, + // &NBPlatformData + // ); + Status = pRS->GetVariable ( + L"NBPlatformData", + &gSetupGuid, + &Attributes, + &VariableSize, + &NBPlatformData + ); + if (EFI_ERROR(Status)) + Attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS; + + VariableSize = sizeof(SETUP_DATA); + Status = GetEfiVariable( + L"Setup", + &gSetupGuid, + NULL, + &VariableSize, + &SetupData + ); + +#if (defined(CSM_SUPPORT) && (CSM_SUPPORT != 0)) +#if defined(CsmOptOut_SUPPORT) && (CsmOptOut_SUPPORT == 1) + + Status = pBS->LocateProtocol( &gAmiLoadCsmGuid, \ + NULL, \ + &gInterface ); + if(!EFI_ERROR(Status)) + { + if ((SetupData->VideoOpRom == 0) || (SetupData->VideoOpRom == 2)) return EFI_UNSUPPORTED; + } + +#else + +#if defined(CORE_COMBINED_VERSION) && (CORE_COMBINED_VERSION <= 0x4028b) +{ + if ((SetupData->VideoOpRom) == 1) return EFI_UNSUPPORTED; +} +#else + return EFI_UNSUPPORTED; +#endif // CORE_COMBINED_VERSION +#endif // CsmOptOut_SUPPORT +#endif // CSM_SUPPORT + + pBS->SetMem (&mPlatformGOPPolicy, sizeof (PLATFORM_GOP_POLICY_PROTOCOL), 0); + + mPlatformGOPPolicy.Revision = PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02; + mPlatformGOPPolicy.GetPlatformLidStatus = GetPlatformLidStatus; + mPlatformGOPPolicy.GetVbtData = GetVbtData; + mPlatformGOPPolicy.GetPlatformDockStatus = GetPlatformDockStatus; + + // + // Install protocol to allow access to this Policy. + // + Status = pBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gPlatformGOPPolicyGuid, + &mPlatformGOPPolicy, + NULL + ); + + //NbSetupdata Pass to SaGlobalNvsArea. + Status = pBS->CreateEvent ( + EFI_EVENT_NOTIFY_SIGNAL, + TPL_CALLBACK, + IntelGopVbtUpdateNotify, + NULL, + &DxePlatformSaPolicyEvent + ); + + if (!EFI_ERROR (Status)) { + Status = pBS->RegisterProtocolNotify ( + &gDxePlatformSaPolicyGuid, + DxePlatformSaPolicyEvent, + &DxePlatformSaPolicyReg + ); + } + + + NBPlatformData.IGFXGopAvailable = 1; + + // Save SETUP variables. + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"NBPlatformData", + // &gSetupGuid, + // EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (NB_PLATFORM_DATA), + // &NBPlatformData + // ); + Status = pRS->SetVariable ( + L"NBPlatformData", + &gSetupGuid, + Attributes, + sizeof (NB_PLATFORM_DATA), + &NBPlatformData + ); + + ASSERT_EFI_ERROR (Status); + + return Status; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.c b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.c new file mode 100644 index 0000000..0253aeb --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.c @@ -0,0 +1,871 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.c 6 7/11/14 3:48a Dennisliu $ +// +// $Revision: 6 $ +// +// $Date: 7/11/14 3:48a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.c $ +// +// 6 7/11/14 3:48a Dennisliu +// [TAG] None +// [Category] Improvement +// [Description] Problem: #if directive for TSE_BUILD=0x1208 (EIP176870) +// [Files] +// Board\NB\NBSetup\NBSetup.c +// Chipset\NB\GOP\IntelSaGopSetup\IntelSaGopSetup.c +// +// 5 5/13/14 10:44p Dennisliu +// [TAG] EIP167027 +// [Category] Improvement +// [Description] [SharkBay Aptio4]Variable's attribute needs to be +// reviewed by SA component driver +// [Files] NBDXEBoard.c; IntelSaGopSetup.c; IntelSaGopPolicy.c; +// NBDxe.c; NbPciCSP.c; PciHostBridge.c; +// +// 4 4/23/13 8:02a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Support for BIST (Built-In Self Test) Protocol. +// [Files] IntelSaGopSetup.c; IntelSaGopSetup.h; +// IntelSaGopSetup.sd; +// IntelSaGopSetup.sd; IntelSaGopSetup.sdl; +// IntelSaGopSetup.uni; IntelSaGopDriver.h; +// +// 3 4/08/13 6:31a Ireneyang +// +// 2 8/14/12 5:47a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Implemented BIOS Integration Guide Rev 1.0 to Intel SA +// GOP driver. +// [Files] IntelSaGopDriver.cif, IntelSaGopDriver.mak, +// IntelSaGopDriver.sdl, IntelSaGopPolicy.c, +// IntelSaGopSetup.c, +// IntelSaGopSetup.h, IntelSaGopSetup.mak, +// IntelSaGopSetup.sd, +// IntelSaGopSetup.sdl, IntelSaGopSetup.uni, +// IntelSaGopSwitch.c, IntelSaGopDriver.h, NBPlatformData.h +// +// 1 3/08/12 10:55p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopSetup.c +// +// Description: GOP Setup Rountines +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- +#include <Token.h> +#include <Setup.h> +#include <SetupStrTokens.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\ComponentName2.h> +#include <Protocol\GraphicsOutput.h> +#include <Protocol\IntelSaGopDriver.h> +#include "IntelSaGopSetup.h" + +static EFI_GUID gEfiVariableGuid = EFI_GLOBAL_VARIABLE; +static EFI_GUID gSetupGuid = SETUP_GUID; +static EFI_GUID gGopDisplayBrightnessProtocolGuid = GOP_DISPLAY_BRIGHTNESS_PROTOCOL_GUID; +static EFI_GUID gGopDisplayBistProtocolGuid = GOP_DISPLAY_BIST_PROTOCOL_GUID; + +EFI_STATUS AmiGopDeviceCheck ( + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE DriverBindingHandle, + IN EFI_PCI_IO_PROTOCOL *PciIo +); + +EFI_STATUS GetIntelSaGopSetupDriverBindingHandle ( + IN EFI_HANDLE ControllerHandle, + OUT EFI_HANDLE *DriverBindingHandle +); + +EFI_STATUS GetChildDeviceHandlesControledByDriver ( + IN EFI_HANDLE DriverBindingHandle, + IN EFI_HANDLE ControllerHandle, + OUT UINTN *ChildControllerHandleCount, + OUT EFI_HANDLE **ChildControllerHandleBuffer +); + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Name: GetIntelSaGopSetupDriverBindingHandle +// +// Description: None. +// +// Input: None. +// +// Output: None. +// +// Notes: None. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GetIntelSaGopSetupDriverBindingHandle ( + IN EFI_HANDLE ControllerHandle, + OUT EFI_HANDLE *DriverBindingHandle ) +{ + EFI_STATUS Status; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + UINTN HandleIndex; + EFI_GUID **ProtocolGuidArray; + UINTN ArrayCount; + UINTN ProtocolIndex; + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo; + UINTN OpenInfoCount; + UINTN OpenInfoIndex; + UINTN Index; + + Status = pBS->LocateHandleBuffer( + AllHandles, + NULL, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR(Status)) return EFI_NOT_FOUND; + + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + ProtocolGuidArray = NULL; + Status = pBS->ProtocolsPerHandle( + HandleBuffer[HandleIndex], + &ProtocolGuidArray, + &ArrayCount); + if (EFI_ERROR(Status)) continue; + + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) { + Status = pBS->OpenProtocolInformation( + HandleBuffer[HandleIndex], + ProtocolGuidArray[ProtocolIndex], + &OpenInfo, + &OpenInfoCount); + if (EFI_ERROR(Status)) continue; + + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++) { + if (OpenInfo[OpenInfoIndex].ControllerHandle == ControllerHandle) { + if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_DRIVER) == EFI_OPEN_PROTOCOL_BY_DRIVER) { + for(Index = 0; Index < HandleCount; Index++) { + if(HandleBuffer[Index] == OpenInfo[OpenInfoIndex].AgentHandle) { + *DriverBindingHandle=HandleBuffer[Index]; + pBS->FreePool(OpenInfo); + pBS->FreePool(ProtocolGuidArray); + pBS->FreePool(HandleBuffer); + return EFI_SUCCESS; + } + } + } + } + } + if (OpenInfo != NULL) pBS->FreePool(OpenInfo); + } + if (ProtocolGuidArray != NULL) pBS->FreePool(ProtocolGuidArray); + } + if (HandleBuffer != NULL) pBS->FreePool(HandleBuffer); + return EFI_NOT_FOUND; +} + +// <AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Name: GetChildDeviceHandlesControledByDriver +// +// Description: +// Get all child device handles which are being opened by a specific driver. +// The rountine will allocate pool buffer for the found child device handles, +// and it is the caller's responsibility to safe free the buffer. +// +// Input: +// IN EFI_HANDLE DriverBindingHandle - the handle of a driver which +// contains the binding protocol +// IN EFI_HANDLE ControllerHandle - the device controller handle be opened +// by its child device +// OUT UINTN ChildControllerHandleCount - the number of available +// device handles returned in +// ControllerHandleBuffer +// OUT EFI_HANDLE ChildControllerHandleBuffer - a pointer to the buffer to +// return the array of child +// device handles +// +// Output: +// EFI_STATUS +// If returned status is not succeful or find no available device, +// the *ChildControllerHandleBuffer will be NULL +// +// Modified: +// +// Referrals: +// +// Notes: +// +//---------------------------------------------------------------------------- +// <AMI_PHDR_END> + +EFI_STATUS +GetChildDeviceHandlesControledByDriver ( + IN EFI_HANDLE DriverBindingHandle, + IN EFI_HANDLE ControllerHandle, + OUT UINTN *ChildControllerHandleCount, + OUT EFI_HANDLE **ChildControllerHandleBuffer ) +{ + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + BOOLEAN *HandleBufferMap; + EFI_STATUS Status; + UINTN HandleIndex; + UINTN AvailableIndex; + EFI_GUID **ProtocolGuidArray; + UINTN ArrayCount; + UINTN ProtocolIndex; + EFI_OPEN_PROTOCOL_INFORMATION_ENTRY *OpenInfo; + UINTN OpenInfoCount; + UINTN OpenInfoIndex; + + *ChildControllerHandleCount = 0; + *ChildControllerHandleBuffer = NULL; + HandleCount = 0; + HandleBuffer = NULL; + + if ((DriverBindingHandle == NULL) || (ControllerHandle == NULL)) { + Status = EFI_INVALID_PARAMETER; + goto Error; + } + + // + // Retrieve the list of all handles from the handle database + // + Status = pBS->LocateHandleBuffer ( + AllHandles, + NULL, + NULL, + &HandleCount, + &HandleBuffer); + if (EFI_ERROR(Status)) goto Error; + + // + // Create a map for HandleBuffer. If a handle in HandleBuffer is the wanted device handle, its map item is true. + // + HandleBufferMap = MallocZ (sizeof (BOOLEAN) * HandleCount); + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + HandleBufferMap[HandleIndex] = FALSE; + } + + // + // Retrieve the list of all the protocols on each handle + // + Status = pBS->ProtocolsPerHandle ( + ControllerHandle, + &ProtocolGuidArray, + &ArrayCount); + if (!EFI_ERROR (Status)) { + for (ProtocolIndex = 0; ProtocolIndex < ArrayCount; ProtocolIndex++) { + // + // Retrieve the list of agents that have opened each protocol + // + Status = pBS->OpenProtocolInformation ( + ControllerHandle, + ProtocolGuidArray[ProtocolIndex], + &OpenInfo, + &OpenInfoCount); + if (!EFI_ERROR (Status)) { + for (OpenInfoIndex = 0; OpenInfoIndex < OpenInfoCount; OpenInfoIndex++) { + if (OpenInfo[OpenInfoIndex].AgentHandle == DriverBindingHandle) { + if ((OpenInfo[OpenInfoIndex].Attributes & EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) == EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER) { + // + // OpenInfo[OpenInfoIndex].ControllerHandle is the wanted child device handle, find it in the handlebuffer + // A bus driver maybe open a Controller with BY_CHILD_CONTROLLER attribute for different protocol many times, + // + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + if (OpenInfo[OpenInfoIndex].ControllerHandle == HandleBuffer[HandleIndex]) { + HandleBufferMap[HandleIndex] = TRUE; + } + } + } + } + } + pBS->FreePool (OpenInfo); + } + } + pBS->FreePool (ProtocolGuidArray); + } + + // + // count how many device handles are found + // + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + if (HandleBufferMap[HandleIndex]) { + (*ChildControllerHandleCount)++; + } + } + + if (*ChildControllerHandleCount > 0) { + // + // Copy the found device handle to returned buffer + // + *ChildControllerHandleBuffer = MallocZ (sizeof (EFI_HANDLE) * (*ChildControllerHandleCount)); + for (HandleIndex = 0, AvailableIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + if (HandleBufferMap[HandleIndex]) { + (*ChildControllerHandleBuffer)[AvailableIndex] = HandleBuffer[HandleIndex]; + AvailableIndex++; + } + } + } + + if (HandleBuffer != NULL) pBS->FreePool (HandleBuffer); + return EFI_SUCCESS; + +Error: + if (HandleBuffer != NULL) pBS->FreePool (HandleBuffer); + return Status; +} + +//<AMI_PHDR_START> +//--------------------------------------------------------------------------- +// Name: IntelSaGopSetupInfo +// +// Description: This function will display Brightness Option in setup menu, +// if the system GOP supports it. +// +// Input: EFI_HII_HANDLE HiiHandle +// +// Output: VOID +//--------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +IntelSaGopSetupInfo( + EFI_HII_HANDLE HiiHandle, + UINT16 Class +) +{ + EFI_STATUS Status; + UINTN SetupSize; + NB_GOP_PLATFORM_DATA NBGopPlatformData = {0}; + + UINTN ControllerHandleIndex; + EFI_HANDLE ControllerHandle; + UINTN ControllerHandleCount = 0; + EFI_HANDLE *ControllerHandleBuffer = NULL; + + EFI_HANDLE DriverBindingHandle; + + EFI_PCI_IO_PROTOCOL *PciIo; + + UINTN ChildHandleCount = 0; + EFI_HANDLE *ChildHandleBuffer = NULL; + EFI_HANDLE ChildHandle; + UINTN ChildHandleIndex = 0; + UINT8 GopBistEnable; + UINT32 CurrentBrightness = 255; + GOP_DISPLAY_BRIGHTNESS_PROTOCOL *GopDisplayBrightnessProtocol = NULL; + GOP_DISPLAY_BIST_PROTOCOL *GopDisplayBistProtocol = NULL; + SETUP_DATA SetupData; + + SetupSize = sizeof (SETUP_DATA); + Status = pRS->GetVariable ( + L"Setup", + &gSetupGuid, + NULL, + &SetupSize, + &SetupData + ); + + GopBistEnable = (Status == EFI_SUCCESS) ? SetupData.EnableBIST : FALSE; + + // + // Get all drivers handles which has PCI IO Protocol + // + Status = pBS->LocateHandleBuffer( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &ControllerHandleCount, + &ControllerHandleBuffer); + if (EFI_ERROR(Status)) return; + + for (ControllerHandleIndex = 0; ControllerHandleIndex < ControllerHandleCount; ControllerHandleIndex++) { + + ControllerHandle = ControllerHandleBuffer[ControllerHandleIndex]; + Status = pBS->HandleProtocol (ControllerHandle, &gEfiPciIoProtocolGuid, &PciIo); + if (EFI_ERROR(Status)) continue; + + // + // Get Driver Binding Protocol for this VGA + // + Status = GetIntelSaGopSetupDriverBindingHandle (ControllerHandle, &DriverBindingHandle); + if (EFI_ERROR(Status)) continue; + + Status = AmiGopDeviceCheck (ControllerHandle, DriverBindingHandle, PciIo); + if (EFI_ERROR(Status)) continue; + + Status = GetChildDeviceHandlesControledByDriver (DriverBindingHandle, ControllerHandle, &ChildHandleCount, &ChildHandleBuffer); + + if (!EFI_ERROR(Status)) { + for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) { + ChildHandle = ChildHandleBuffer[ChildHandleIndex]; + + // + // Check if this device have Graphic Output Portocol. + // If it does, the system would support Brightness option in setup Menu. + // + Status = pBS->OpenProtocol ( + ChildHandle, + &gEfiGraphicsOutputProtocolGuid, + NULL, + NULL, + NULL, + EFI_OPEN_PROTOCOL_TEST_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + Status = pBS->OpenProtocol ( + ChildHandle, + &gGopDisplayBrightnessProtocolGuid, + (VOID**)&GopDisplayBrightnessProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if(GopDisplayBrightnessProtocol->Revision >= GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01) { + + NBGopPlatformData.BrightnessAvailable = 1; + Status = GopDisplayBrightnessProtocol->GetCurrentBrightnessLevel(GopDisplayBrightnessProtocol, &CurrentBrightness); + + if (EFI_ERROR(Status)) CurrentBrightness = 255; + }//if(GopDisplayBrightnessProtocol->Revision >= GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01) + } + + Status = pBS->OpenProtocol ( + ChildHandle, + &gGopDisplayBistProtocolGuid, + (VOID**)&GopDisplayBistProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) { + + NBGopPlatformData.GopBistAvailable = 1; + + if (GopBistEnable == 1) + Status = GopDisplayBistProtocol->EnableBist(GopDisplayBistProtocol); + else + Status = GopDisplayBistProtocol->DisableBist(GopDisplayBistProtocol); + }//if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) + } + + } + + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"NBGopPlatformData", + // &gSetupGuid, + // EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (NB_GOP_PLATFORM_DATA), + // &NBGopPlatformData + // ); + Status = pRS->SetVariable ( + L"NBGopPlatformData", + &gSetupGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS, + sizeof (NB_GOP_PLATFORM_DATA), + &NBGopPlatformData + ); + + }//for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) + }//if (!EFI_ERROR(Status)) + }//for (ControllerHandleIndex = 0; ControllerHandleIndex < ControllerHandleCount; ControllerHandleIndex++) + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Name: IntelGopSwitchFunction +// +// Description: For overriding ELink, AmiDefaultGopSwitchFunction. +// If it's Intel Device, the system should do this function, IntelGopSwitchFunction. +// +// Input: None. +// +// Output: None. +// +// Notes: None. +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +IntelGopSwitchFunction ( + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE DriverBindingHandle, + IN SETUP_DATA *SetupData, + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath ) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN ChildHandleCount = 0; + EFI_HANDLE *ChildHandleBuffer = NULL; + UINTN ChildHandleIndex = 0; + EFI_HANDLE OutPutDevHandle; + + EFI_DEVICE_PATH_PROTOCOL *GopDevicePath = NULL; + EFI_DEVICE_PATH_PROTOCOL *GopAcpiAdrDPNode = NULL; + ACPI_ADR_DEVICE_PATH *AcpiDPNode; + + UINTN SetupSize; + NB_GOP_PLATFORM_DATA NBGopPlatformData = {0}; + GOP_DISPLAY_BRIGHTNESS_PROTOCOL *GopDisplayBrightnessProtocol = NULL; + GOP_DISPLAY_BIST_PROTOCOL *GopDisplayBistProtocol = NULL; + UINT32 MaxBrightness = 255; + UINT32 CurrentBrightness = 255; + + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_DEV_INFO *Dev; + + Status = pBS->HandleProtocol (ControllerHandle, &gEfiPciIoProtocolGuid, &PciIo); + if (EFI_ERROR(Status)) return Status; + + Dev = (PCI_DEV_INFO*)PciIo; + + // + // If it's not Intel VGA, don't do this part. + // + if (Dev->DevVenId.VenId != 0x8086) { + return EFI_UNSUPPORTED; + } + + SetupSize = sizeof (NB_GOP_PLATFORM_DATA); + + AcpiDPNode = (ACPI_ADR_DEVICE_PATH*)GopAcpiAdrDPNode = DPGetLastNode(DevicePath); + Status = pBS->ConnectController( ControllerHandle, NULL, GopAcpiAdrDPNode, TRUE ); + +// Status = GetChildDeviceHandlesControledByDriver (DriverBindingHandle, ControllerHandle, &ChildHandleCount, &ChildHandleBuffer); + + if (!EFI_ERROR(Status)) { + // + // Find out Current Installed GOP Device + // +// for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) { +// if (SetupData->GopOutputSelect == ChildHandleIndex) { +// +// Status = pBS->OpenProtocol ( +// ChildHandleBuffer[ChildHandleIndex], +// &gEfiDevicePathProtocolGuid, +// (VOID**)&GopDevicePath, +// NULL, +// NULL, +// EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); +// if (EFI_ERROR(Status)) break; +// +// // +// // If Current installed GOP is Intels', conncect it. +// // +// if (!EFI_ERROR(Status)) { +// AcpiDPNode = (ACPI_ADR_DEVICE_PATH*)GopAcpiAdrDPNode = DPGetLastNode(GopDevicePath); +// Status = pBS->ConnectController( ControllerHandle, NULL, GopAcpiAdrDPNode, TRUE ); +// } +// +// // +// // Check if this device have Graphic Output Portocol. +// // If it does, the system would support Brightness option in setup Menu. +// // +// Status = pBS->OpenProtocol ( +// ChildHandleBuffer[ChildHandleIndex], +// &gEfiGraphicsOutputProtocolGuid, +// NULL, +// NULL, +// NULL, +// EFI_OPEN_PROTOCOL_TEST_PROTOCOL); + Status = pBS->LocateDevicePath(&gGopDisplayBrightnessProtocolGuid, &DevicePath, &OutPutDevHandle); + + if (!EFI_ERROR(Status)) { + + Status = pBS->OpenProtocol ( + OutPutDevHandle, + &gGopDisplayBrightnessProtocolGuid, + (VOID**)&GopDisplayBrightnessProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + if (!EFI_ERROR(Status)) { + if(GopDisplayBrightnessProtocol->Revision >= GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01) { + NBGopPlatformData.BrightnessAvailable = 1; + Status = GopDisplayBrightnessProtocol->GetMaxBrightnessLevel(GopDisplayBrightnessProtocol, &MaxBrightness); + if (!EFI_ERROR(Status)) { + if (SetupData->GopBrightness > MaxBrightness) { + SetupData->GopBrightness = MaxBrightness; +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + Status = HiiLibSetBrowserData (SetupSize, SetupData, &gSetupGuid, L"Setup"); +#endif + } + Status = GopDisplayBrightnessProtocol->GetCurrentBrightnessLevel(GopDisplayBrightnessProtocol, &CurrentBrightness); + if (!EFI_ERROR(Status)) { + if(CurrentBrightness != SetupData->GopBrightness) + Status = GopDisplayBrightnessProtocol->SetBrightnessLevel(GopDisplayBrightnessProtocol, SetupData->GopBrightness); + } + } + } // GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01 + } //OpenProtocol gGopDisplayBrightnessProtocol + + Status = pBS->OpenProtocol ( + OutPutDevHandle, + &gGopDisplayBistProtocolGuid, + (VOID**)&GopDisplayBistProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) { + + NBGopPlatformData.GopBistAvailable = 1; + + if (SetupData->EnableBIST == 1) + Status = GopDisplayBistProtocol->EnableBist(GopDisplayBistProtocol); + else + Status = GopDisplayBistProtocol->DisableBist(GopDisplayBistProtocol); + }//if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) + } //OpenProtocol gGopDisplayBistProtocolGuid + + } +// }// if (SetupData->GopOutputSelect == ChildHandleIndex) +// }// for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) + } + + Status = HiiLibSetBrowserData ( + sizeof (NB_GOP_PLATFORM_DATA), + &NBGopPlatformData, + &gSetupGuid, + L"NBGopPlatformData" + ); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------- +// Name: IntelGopMultifunctionCallback +// +// Description: If the device support Multifunction, it supports its key +// callbak funtion. +// +// Input: None. +// +// Output: None. +// +// Notes: None. +// +//---------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS IntelGopMultifunctionCallback ( + IN EFI_HII_HANDLE HiiHandle, + IN UINT16 Class, + IN UINT16 SubClass, + IN UINT16 Key ) +{ + + EFI_STATUS Status = EFI_SUCCESS; + SETUP_DATA *SetupData = NULL; + CALLBACK_PARAMETERS *CallbackParameters = NULL; + UINTN SetupSize; + EFI_STATUS NBGopPlatformDataStatus = EFI_UNSUPPORTED; + NB_GOP_PLATFORM_DATA NBGopPlatformData = {0}; + UINTN ControllerHandleIndex; + EFI_HANDLE ControllerHandle; + UINTN ControllerHandleCount = 0; + EFI_HANDLE *ControllerHandleBuffer = NULL; + + EFI_HANDLE DriverBindingHandle; + + EFI_PCI_IO_PROTOCOL *PciIo; + + UINTN ChildHandleCount = 0; + EFI_HANDLE *ChildHandleBuffer = NULL; + EFI_HANDLE ChildHandle; + UINTN ChildHandleIndex = 0; + + UINT32 CurrentBrightness = 255; + GOP_DISPLAY_BRIGHTNESS_PROTOCOL *GopDisplayBrightnessProtocol = NULL; + GOP_DISPLAY_BIST_PROTOCOL *GopDisplayBistProtocol = NULL; + + UINT32 MaxBrightness = 255; + + SetupSize = sizeof (SETUP_DATA); + + CallbackParameters = GetCallbackParameters(); + +#if ((TSE_BUILD >= 0x1224) && (EFI_SPECIFICATION_VERSION >= 0x2000A)) + if (CallbackParameters->Action != EFI_BROWSER_ACTION_CHANGED) return Status; +#elif ((TSE_BUILD > 0x1208) && (EFI_SPECIFICATION_VERSION >= 0x2000A)) + if (CallbackParameters->Action != EFI_BROWSER_ACTION_CHANGING) return Status; +#endif + + Status = pBS->AllocatePool (EfiBootServicesData, SetupSize, &SetupData); + if(EFI_ERROR(Status)) return Status; + +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + Status = HiiLibGetBrowserData (&SetupSize, SetupData, &gSetupGuid, L"Setup"); + if(EFI_ERROR(Status)) return Status; +#else + SetupData = (SETUP_DATA*)CallbackParameters->Data->NvRamMap; +#endif + +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + SetupSize = sizeof (NB_GOP_PLATFORM_DATA); + NBGopPlatformDataStatus = HiiLibGetBrowserData (&SetupSize, &NBGopPlatformData, &gSetupGuid, L"NBGopPlatformData"); +#endif + // + // Get all drivers handles which has PCI IO Protocol + // + Status = pBS->LocateHandleBuffer( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &ControllerHandleCount, + &ControllerHandleBuffer); + if (EFI_ERROR(Status)) return Status; + + for (ControllerHandleIndex = 0; ControllerHandleIndex < ControllerHandleCount; ControllerHandleIndex++) { + + ControllerHandle = ControllerHandleBuffer[ControllerHandleIndex]; + Status = pBS->HandleProtocol (ControllerHandle, &gEfiPciIoProtocolGuid, &PciIo); + if (EFI_ERROR(Status)) continue; + + Status = GetIntelSaGopSetupDriverBindingHandle (ControllerHandle, &DriverBindingHandle); + if (EFI_ERROR(Status)) continue; + + Status = AmiGopDeviceCheck (ControllerHandle, DriverBindingHandle, PciIo); + if (EFI_ERROR(Status)) continue; + + Status = GetChildDeviceHandlesControledByDriver (DriverBindingHandle, ControllerHandle, &ChildHandleCount, &ChildHandleBuffer); + + if (!EFI_ERROR(Status)) { + for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) { + ChildHandle = ChildHandleBuffer[ChildHandleIndex]; + + // + // Check if this device have Graphic Output Portocol. + // If it does, the system would support Brightness option in setup Menu. + // + Status = pBS->OpenProtocol ( + ChildHandle, + &gEfiGraphicsOutputProtocolGuid, + NULL, + NULL, + NULL, + EFI_OPEN_PROTOCOL_TEST_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if (Key == AGP_BRIGHTNESS_KEY) { + Status = pBS->OpenProtocol ( + ChildHandle, + &gGopDisplayBrightnessProtocolGuid, + (VOID**)&GopDisplayBrightnessProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + if (!EFI_ERROR(Status)) { + if(GopDisplayBrightnessProtocol->Revision >= GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01) { + NBGopPlatformData.BrightnessAvailable = 1; + Status = GopDisplayBrightnessProtocol->GetMaxBrightnessLevel(GopDisplayBrightnessProtocol, &MaxBrightness); + if (!EFI_ERROR(Status)) { + if (SetupData->GopBrightness > MaxBrightness) { + SetupData->GopBrightness = MaxBrightness; +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + SetupSize = sizeof (SETUP_DATA); + Status = HiiLibSetBrowserData (SetupSize, SetupData, &gSetupGuid, L"Setup"); +#endif + } + Status = GopDisplayBrightnessProtocol->GetCurrentBrightnessLevel(GopDisplayBrightnessProtocol, &CurrentBrightness); + if (!EFI_ERROR(Status)) { + if(CurrentBrightness != SetupData->GopBrightness) + Status = GopDisplayBrightnessProtocol->SetBrightnessLevel(GopDisplayBrightnessProtocol, SetupData->GopBrightness); + } + } + } // GOP_DISPLAY_BRIGHTNESS_PROTOCOL_REVISION_01 + } //OpenProtocol GopDisplayBrightnessProtocol + } // AGP_BRIGHTNESS_KEY + + if (Key == AGP_BIST_KEY) { + Status = pBS->OpenProtocol ( + ChildHandle, + &gGopDisplayBistProtocolGuid, + (VOID**)&GopDisplayBistProtocol, + NULL, + NULL, + EFI_OPEN_PROTOCOL_BY_HANDLE_PROTOCOL); + + if (!EFI_ERROR(Status)) { + + if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) { + + NBGopPlatformData.GopBistAvailable = 1; + + if (SetupData->EnableBIST == 1) + Status = GopDisplayBistProtocol->EnableBist(GopDisplayBistProtocol); + else + Status = GopDisplayBistProtocol->DisableBist(GopDisplayBistProtocol); + }//if(GopDisplayBistProtocol->Revision >= GOP_DISPLAY_BIST_PROTOCOL_REVISION_01) + } //OpenProtocol gGopDisplayBistProtocolGuid + } // AGP_BIST_KEY + }//OpenProtocol gEfiGraphicsOutputProtocolGuid + + }//for (ChildHandleIndex = 0; ChildHandleIndex < ChildHandleCount; ChildHandleIndex++) + }//if (!EFI_ERROR(Status)) + }//for (ControllerHandleIndex = 0; ControllerHandleIndex < ControllerHandleCount; ControllerHandleIndex++) + +#if defined(EFI_SPECIFICATION_VERSION) && EFI_SPECIFICATION_VERSION > 0x20000 + if(!EFI_ERROR(NBGopPlatformDataStatus)) { + HiiLibSetBrowserData ( + sizeof (NB_GOP_PLATFORM_DATA), + &NBGopPlatformData, + &gSetupGuid, + L"NBGopPlatformData" + ); + } +#endif + return Status; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.cif b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.cif new file mode 100644 index 0000000..429afd0 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.cif @@ -0,0 +1,13 @@ +<component> + name = "IntelSaGopSetup" + category = ModulePart + LocalRoot = "Chipset\NB\GOP\IntelSaGopSetup" + RefName = "IntelSaGopSetup" +[files] +"IntelSaGopSetup.sdl" +"IntelSaGopSetup.mak" +"IntelSaGopSetup.sd" +"IntelSaGopSetup.uni" +"IntelSaGopSetup.c" +"IntelSaGopSetup.h" +<endComponent> diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.h b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.h new file mode 100644 index 0000000..c46eef8 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.h @@ -0,0 +1,96 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.h 3 4/23/13 8:01a Ireneyang $ +// +// $Revision: 3 $ +// +// $Date: 4/23/13 8:01a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.h $ +// +// 3 4/23/13 8:01a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Support for BIST (Built-In Self Test) Protocol. +// [Files] IntelSaGopSetup.c; IntelSaGopSetup.h; +// IntelSaGopSetup.sd; +// IntelSaGopSetup.sd; IntelSaGopSetup.sdl; +// IntelSaGopSetup.uni; IntelSaGopDriver.h; +// +// 2 8/14/12 5:47a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Implemented BIOS Integration Guide Rev 1.0 to Intel SA +// GOP driver. +// [Files] IntelSaGopDriver.cif, IntelSaGopDriver.mak, +// IntelSaGopDriver.sdl, IntelSaGopPolicy.c, +// IntelSaGopSetup.c, +// IntelSaGopSetup.h, IntelSaGopSetup.mak, +// IntelSaGopSetup.sd, +// IntelSaGopSetup.sdl, IntelSaGopSetup.uni, +// IntelSaGopSwitch.c, IntelSaGopDriver.h, NBPlatformData.h +// +// 1 3/08/12 10:55p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopSetup.h +// +// Description: GOP Specific Setup Variables and Structures +// +//<AMI_FHDR_END> +//************************************************************************* +#ifndef _NB_GOP_PLATFORM_DATA_H_ +#define _NB_GOP_PLATFORM_DATA_H_ +#ifdef __cplusplus +extern "C" { +#endif + + #pragma pack(1) + + typedef struct _NB_GOP_PLATFORM_DATA + { + UINT8 BrightnessAvailable; + UINT8 GopBistAvailable; + }NB_GOP_PLATFORM_DATA; + + #pragma pack() + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.mak b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.mak new file mode 100644 index 0000000..49cf3fe --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.mak @@ -0,0 +1,49 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: IntelSaGopSetup.mak +# +# Description: This make file builds north bridge Setup +# components and link them to respective binary +# +#<AMI_FHDR_END> +#************************************************************************* +All : IntelSaGopSetup + +IntelSaGopSetup : $(BUILD_DIR)\IntelSaGopSetup.mak + +$(BUILD_DIR)\IntelSaGopSetup.mak : $(IntelSaGopSetup_DIR)\$(@B).cif $(IntelSaGopSetup_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(IntelSaGopSetup_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +SetupBin : $(BUILD_DIR)\IntelSaGopSetup.obj + +$(BUILD_DIR)\IntelSaGopSetup.obj : $(IntelSaGopSetup_DIR)\IntelSaGopSetup.c $(BUILD_DIR)\SetupStrTokens.h + $(CC) $(CFLAGS) /Fo$(BUILD_DIR)\ $(IntelSaGopSetup_DIR)\IntelSaGopSetup.c + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sd b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sd new file mode 100644 index 0000000..b62c2af --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sd @@ -0,0 +1,306 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.sd 7 8/06/14 10:28p Dennisliu $ +// +// $Revision: 7 $ +// +// $Date: 8/06/14 10:28p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/IntelGopDriver/IntelSaGopSetup/IntelSaGopSetup.sd $ +// +// 7 8/06/14 10:28p Dennisliu +// [TAG] EIP180652 +// [Category] Improvement +// [Description] IntelSaGopSetup needs updated to support latest +// AmiGopPolicy. +// [Files] Chipset\NB\GOP\IntelSaGopSetup\IntelSaGopSetup.sd +// +// 6 4/11/14 5:26a Dennisliu +// [TAG] None +// [Severity] Improvement +// [Description] Fixed coding error. +// [Files] IntelSaGopSetup.sd; +// +// 4 1/20/14 9:30p Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Fix showing messages, +// "invalid token near line xxx (text was '\')", +// when building code. +// [Files] IntelSaGopSetup.sd; +// +// 3 4/23/13 8:03a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Support for BIST (Built-In Self Test) Protocol. +// [Files] IntelSaGopSetup.c; IntelSaGopSetup.h; +// IntelSaGopSetup.sd; +// IntelSaGopSetup.sd; IntelSaGopSetup.sdl; +// IntelSaGopSetup.uni; IntelSaGopDriver.h; +// +// 2 8/14/12 5:47a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Implemented BIOS Integration Guide Rev 1.0 to Intel SA +// GOP driver. +// [Files] IntelSaGopDriver.cif, IntelSaGopDriver.mak, +// IntelSaGopDriver.sdl, IntelSaGopPolicy.c, +// IntelSaGopSetup.c, +// IntelSaGopSetup.h, IntelSaGopSetup.mak, +// IntelSaGopSetup.sd, +// IntelSaGopSetup.sdl, IntelSaGopSetup.uni, +// IntelSaGopSwitch.c, IntelSaGopDriver.h, NBPlatformData.h +// +// 1 3/08/12 10:55p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Create Haswell Intel SA GOP Driver module part. +// Notice : IntelGopDriver.efi and vbt.bin is dummy files. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: IntelSaGopSetup.sd +// +// Description: GOP setup form +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifdef SETUP_DATA_DEFINITION +//---------------------------------------------------------------------------- +// Put NVRAM data definitions here. +// For example: UINT8 Data1; +// These definitions will be converted by the build process +// to a definitions of SETUP_DATA fields. +//---------------------------------------------------------------------------- + UINT8 GopOutputSelect; + UINT32 GopBrightness; + UINT8 EnableBIST; +#endif //SETUP_DATA_DEFINITION + +#ifdef FORM_SET_TYPEDEF + #include "IntelSaGopSetup.h" + #include "Board\EM\AmiGopPolicy\AmiGopPolicy.h" +#endif + +//Select Top level menu itmem (forset) for you pages +#ifdef ADVANCED_FORM_SET + #ifndef SUPPRESS_GRAYOUT_ENDIF //old Core + #define SUPPRESS_GRAYOUT_ENDIF endif; + #endif + + #ifdef FORM_SET_VARSTORE + varstore AMI_GOP_POLICY_SETUP_DATA, + key = AUTO_ID(AMI_GOP_POLICY_SETUP_DATA_ID), + name = AmiGopPolicySetupData, + guid = AMI_GOP_POLICY_VARIABLE_GUID; + + varstore NB_GOP_PLATFORM_DATA, + key = AUTO_ID(NB_GOP_PLATFORM_DATA_ID), + name = NBGopPlatformData, + guid = SETUP_GUID; + #endif + +#ifdef FORM_SET_GOTO +// Define goto commands for the forms defined in this file +// goto ID_OF_MY_FORM, +// prompt = STRING_TOKEN(STR_FORM_TITLE), +// help = STRING_TOKEN(STR_FORM_HELP); + suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0; + goto AGP_FORM_ID, + prompt = STRING_TOKEN(STR_TITLE), + help = STRING_TOKEN(STR_TITLE_HELP); + endif; //suppressif GopDeviceCount < 1 +#endif //FORM_SET_GOTO + +#ifdef FORM_SET_FORM +// Define forms +// form formid = AUTO_ID(ID_OF_MY_FORM), +// title = STRING_TOKEN(STR_FORM_TITLE); +// endform; + form formid = AUTO_ID(AGP_FORM_ID), + title = STRING_TOKEN(STR_TITLE); + + //suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0; + SUBTITLE(STRING_TOKEN(STR_GOP_DEVICE_NAME_0)) + SUBTITLE(STRING_TOKEN(STR_GOP_DRIVER_NAME_0)) + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x1; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_0); + endoneof; + endif; //suppressif GopOutputCount != 1 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x2; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_1); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 2 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x3; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_2); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 3 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x4; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_3); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 4 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x5; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_4); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_4), value = 4, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 5 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x6; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_5); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_4), value = 4, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_5), value = 5, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 6 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x7; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_6); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_4), value = 4, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_5), value = 5, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_6), value = 6, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 7 + + suppressif NOT ideqval AMI_GOP_POLICY_SETUP_DATA.GopOutputCount == 0x8; + oneof varid = SETUP_DATA.GopOutputSelect, + prompt = STRING_TOKEN(STR_GOP_OUTPUT_SELECT), + help = STRING_TOKEN(STR_GOP_OUTPUT_HELP), + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_0), value = 0, flags = DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_KEY_7); + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_1), value = 1, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_2), value = 2, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_3), value = 3, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_4), value = 4, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_5), value = 5, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_6), value = 6, flags = 0; + option text = STRING_TOKEN(STR_GOP_OUTPUT_NAME_7), value = 7, flags = 0; + endoneof; + endif; //suppressif GopOutputCount != 8 + + + suppressif ideqval NB_GOP_PLATFORM_DATA.BrightnessAvailable == 0x00; + numeric varid = SETUP_DATA.GopBrightness, + prompt = STRING_TOKEN(STR_GOP_BRIGHTNESS), + help = STRING_TOKEN(STR_GOP_BRIGHTNESS_HELP), + flags = INTERACTIVE, key = AUTO_ID(AGP_BRIGHTNESS_KEY), + minimum = 0, + maximum = 0xffffffff, + step = 1, + default = 255, + option text = STRING_TOKEN (STR_GOP_BRIGHTNESS), value = 0, flags = MANUFACTURING | INTERACTIVE; + endnumeric; + endif; + + suppressif ideqval NB_GOP_PLATFORM_DATA.GopBistAvailable == 0x00; + oneof varid = SETUP_DATA.EnableBIST, + prompt = STRING_TOKEN(STR_GOP_BIST_ENABLE), + help = STRING_TOKEN(STR_GOP_BIST_ENABLE_HELP), + option text = STRING_TOKEN(STR_COMMON_DISABLED), value = 0, flags = RESET_REQUIRED | DEFAULT | MANUFACTURING | INTERACTIVE, key = AUTO_ID(AGP_BIST_KEY); + option text = STRING_TOKEN(STR_COMMON_ENABLED), value = 1, flags = RESET_REQUIRED; + endoneof; + endif; //suppressif GopBistAvailable == 0 + + //endif; //suppressif GopDeviceCount < 1 +/* + SEPARATOR + + suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x1; + SUBTITLE(STRING_TOKEN(STR_GOP_DEVICE_NAME_1)) + SUBTITLE(STRING_TOKEN(STR_GOP_DRIVER_NAME_1)) + endif; //suppressif GopDeviceCount < 2 + + SEPARATOR + + suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x1 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x2; + SUBTITLE(STRING_TOKEN(STR_GOP_DEVICE_NAME_2)) + SUBTITLE(STRING_TOKEN(STR_GOP_DRIVER_NAME_2)) + endif; //suppressif GopDeviceCount < 3 + + SEPARATOR + + suppressif ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x0 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x1 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x2 OR + ideqval AMI_GOP_POLICY_SETUP_DATA.GopDeviceCount == 0x3; + SUBTITLE(STRING_TOKEN(STR_GOP_DEVICE_NAME_3)) + SUBTITLE(STRING_TOKEN(STR_GOP_DRIVER_NAME_3)) + endif; //suppressif GopDeviceCount < 4 +*/ + endform; + +#endif //FORM_SET_FORM + +#endif //ADVANCED_FORM_SET + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sdl b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sdl new file mode 100644 index 0000000..ebfe462 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.sdl @@ -0,0 +1,72 @@ +TOKEN + Name = "IntelSaGopSetup_SUPPORT" + Value = "1" + Help = "Main switch to enable IntelSaGopSetup support in Project" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Master = Yes + Token = "AmiGopPolicy" "=" "1" +End + +PATH + Name = "IntelSaGopSetup_DIR" +End + +MODULE + Help = "Includes IntelSaGopSetup.mak to Project" + File = "IntelSaGopSetup.mak" +End + +ELINK + Name = "IntelSaGopSetupInfo," + Parent = "InitAmiGopPolicyStrings," + InvokeOrder = AfterParent +End + +ELINK + Name = "/I$(IntelSaGopSetup_DIR)" + Parent = "$(GLOBAL_DEFINES)" + InvokeOrder = AfterParent +End + +TOKEN + Name = "====== For Intel Brightness ======" + TokenType = Expression +End + +ELINK + Name = "$(IntelSaGopSetup_DIR)\IntelSaGopSetup.sd" + Parent = "$(AMIGOPPOLICY_DIR)\AmiGopPolicy.sd" + InvokeOrder = ReplaceParent + Token = "AmiGopPolicy" "=" "1" +End + +ELINK + Name = "$(IntelSaGopSetup_DIR)\IntelSaGopSetup.uni" + Parent = "$(AMIGOPPOLICY_DIR)\AmiGopPolicy.uni" + InvokeOrder = ReplaceParent + Token = "AmiGopPolicy" "=" "1" +End + +ELINK + Name = "IntelGopSwitchFunction," + Parent = "AmiDefaultGopSwitchFunction," + InvokeOrder = ReplaceParent + Token = "AmiGopPolicy" "=" "1" +End + +ELINK + Name = "ITEM_CALLBACK(ADVANCED_FORM_SET_CLASS,0,AGP_BRIGHTNESS_KEY,IntelGopMultifunctionCallback)," + Parent = "SetupItemCallbacks" + InvokeOrder = AfterParent + Token = "AmiGopPolicy" "=" "1" +End + + +ELINK + Name = "ITEM_CALLBACK(ADVANCED_FORM_SET_CLASS,0,AGP_BIST_KEY,IntelGopMultifunctionCallback)," + Parent = "SetupItemCallbacks" + InvokeOrder = AfterParent + Token = "AmiGopPolicy" "=" "1" +End diff --git a/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.uni b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.uni Binary files differnew file mode 100644 index 0000000..55eef78 --- /dev/null +++ b/Chipset/NB/GOP/IntelSaGopSetup/IntelSaGopSetup.uni diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.c b/Chipset/NB/LegacyRegion/LegacyRegion.c new file mode 100644 index 0000000..1dd32b6 --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.c @@ -0,0 +1,552 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2005, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.c 1 4/02/13 6:27a Ireneyang $ +// +// $Revision: 1 $ +// +// $Date: 4/02/13 6:27a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.c $ +// +// 1 4/02/13 6:27a Ireneyang +// Support CSM Label 80. +// +// 3 12/25/12 4:41a Abelwu +// Updated for supporting PI 1.x +// +// 2 12/25/12 3:57a Abelwu +// Update for supporting PI 1.x +// +// 1 12/25/12 3:03a Abelwu +// Move Legacy Region from CSM to NB eChipset +// +// 1 12/20/12 12:35p Olegi +// +// 18 6/16/11 6:30p Olegi +// Added variable that was accidently removed during previous check-in. +// +// 17 5/27/11 11:46a Olegi +// [TAG] EIP56524 +// [Category] New Feature +// [Description] Support for LEGACY_REGION2_PROTOCOL +// [Files] LegacyRegion.c, LegacyRegion2.h +// +// 16 10/14/09 11:21a Krishnakumarg +// CloseEvent funtion used instead of a static variable in callback +// routines - EIP 27065 +// +// 15 6/26/09 11:12a Olegi +// +// 14 6/26/09 10:00a Olegi +// gPciRootBridgeIo defined as "static". EIP#23538 +// +// 13 4/27/07 5:45p Olegi +// +// 12 4/27/07 5:42p Olegi +// +// 11 4/27/07 5:21p Olegi +// CSM.CHM preparations. +// +// 10 10/13/06 12:32a Felixp +// UEFI2.0 compliance: use CreateReadyToBootEvent instead of +// CreateEvent(READY_TO_BOOT) +// +// 9 4/24/06 12:47p Olegi +// +// 3 4/24/06 12:43p Olegi +// +// 2 4/18/06 12:11p Olegi +// +// 8 3/31/06 9:43a Olegi +// +// 7 3/31/06 9:06a Olegi +// +// 6 5/27/05 4:24p Markw +// Added Boot Script. +// +// 5 5/06/05 11:27a Yakovlevs +// +// 3 5/06/05 11:02a Yakovlevs +// +// 4 4/19/05 2:42p Sivagarn +// Included pointer to Boot & Runtime Services in PAM programming +// +// 3 4/04/05 4:21p Sivagarn +// Updated to latest template +// +// 2 2/22/05 10:00a Sivagarn +// - Updated to latest labeled CSM & Core +// +// 2 1/18/05 3:22p Felixp +// PrintDebugMessage renamed to Trace +// +// 1 10/26/04 9:48a Olegi +// +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: LegacyRegion.c +// +// Description: Legacy Region functions implementation +// +//<AMI_FHDR_END> +//********************************************************************** + +#include <efi.h> +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\LegacyRegion.h> +#include <Protocol\LegacyRegion2.h> +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\BootScriptSave.h> +#include <Protocol\cpu.h> + +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) +EFI_GUID gAmiS3SaveProtocolGuid = EFI_S3_SAVE_STATE_PROTOCOL_GUID; +#else +EFI_GUID gAmiS3SaveProtocolGuid = EFI_BOOT_SCRIPT_SAVE_GUID; +#endif + +EFI_GUID gCpu = EFI_CPU_ARCH_PROTOCOL_GUID; + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; + +EFI_EVENT gEvtBootScript; +EFI_CPU_ARCH_PROTOCOL Cpu; +EFI_CPU_ARCH_PROTOCOL *pCpu; + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: CallbackBootScript +// +// Description: Saves the PAM registers to Boot Script +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// Output: +// None +// +//<AMI_PHDR_END> +//********************************************************************** +VOID CallbackBootScript(IN EFI_EVENT Event, IN VOID *Context) +{ + EFI_STATUS Status; +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) + EFI_S3_SAVE_STATE_PROTOCOL *BootScriptSave; +#else + EFI_BOOT_SCRIPT_SAVE_PROTOCOL *BootScriptSave; +#endif + + Status = pBS->LocateProtocol( + &gAmiS3SaveProtocolGuid, + NULL, + &BootScriptSave + ); + if (EFI_ERROR(Status)) return; + + NBPAMWriteBootScript(BootScriptSave); + + // + //Kill the Event + // + pBS->CloseEvent(Event); + +} + + +#define LEGACY_REGION_LOCK 0 +#define LEGACY_REGION_BOOT_LOCK 1 +#define LEGACY_REGION_UNLOCK 2 +#define LEGACY_REGION_DECODE_ROM 3 + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ProgramPamRegisters +// +// Description: Program 0xc0000 - 0xfffff regions to Lock/Unlock. +// +// Input: UINT32 StartAddress +// UINT32 Length +// UINT8 Setting +// UINT32 *Granularity +// +// Output: Status of the operation +// +// Notes: Here is the control flow of this function: +// 1. Search the structure for the first entry matching +// the StartAddress. +// 2. If not found, return EFI_INVALID_PARAMETER. +// 3. Find the last entry in structure for the region to program, +// by adding the lengths of the entries. +// 4. If not found, return EFI_INVALID_PARAMETER. +// 5. Read/Write each register for the entry to set region. +// 6. Return the Granularity for the region. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ProgramPamRegisters( + UINT32 StartAddress, + UINT32 Length, + UINT8 Setting, + UINT32 *Granularity) +{ + EFI_STATUS Status; + UINT64 Attributes; + + Status = NBProgramPAMRegisters (pBS, pRS, StartAddress, Length, Setting, Granularity); + if (Status != EFI_SUCCESS) return Status; + + Status = CPUProgramPAMRegisters (pBS, pRS, StartAddress, Length, Setting, Granularity); + if (Status != EFI_SUCCESS) return Status; + +// Program the MTRRs + switch (Setting) { + + case LEGACY_REGION_LOCK: + Attributes = EFI_MEMORY_WP; + break; + + case LEGACY_REGION_BOOT_LOCK: + Attributes = EFI_MEMORY_WP; + break; + + case LEGACY_REGION_UNLOCK: + Attributes = EFI_MEMORY_WT; + break; + + default: + Attributes = EFI_MEMORY_UC; + + } + +// Status=DxeSvcTbl->SetMemorySpaceAttributes(StartAddress,Length,Attributes); + pCpu->SetMemoryAttributes(pCpu, StartAddress, Length, Attributes); + + return Status; +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: Decode +// +// Description: Program chipset to allow decoding of 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// IN BOOLEAN *On +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS Decode( + IN EFI_LEGACY_REGION_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + IN BOOLEAN *On +) +{ + UINT32 Granularity; + if (*On) { + return ProgramPamRegisters(Start, Length, LEGACY_REGION_UNLOCK, &Granularity); + } else { + return ProgramPamRegisters(Start, Length, LEGACY_REGION_DECODE_ROM, &Granularity); + } +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionDecode +// +// Description: Program chipset to allow decoding of 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity, +// IN BOOLEAN *On +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS LegacyRegionDecode( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity, + IN BOOLEAN *On +) +{ + if (*On) { + return ProgramPamRegisters(Start, Length, LEGACY_REGION_UNLOCK, Granularity); + } else { + return ProgramPamRegisters(Start, Length, LEGACY_REGION_DECODE_ROM, Granularity); + } +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: Lock +// +// Description: To disallow writes to memory 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS Lock( + IN EFI_LEGACY_REGION_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_LOCK, Granularity); +} + +EFI_STATUS LegacyRegionLock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_LOCK, Granularity); +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: BootLock +// +// Description: To permanently disallow writes to memory 0xc0000 - 0xffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS BootLock( + IN EFI_LEGACY_REGION_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + //Can't lock Region permanently. + return ProgramPamRegisters(Start, Length, LEGACY_REGION_BOOT_LOCK, Granularity); +} + +EFI_STATUS LegacyRegionBootLock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_BOOT_LOCK, Granularity); +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: Unlock +// +// Description: To allow read/write of memory 0xc0000-0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS Unlock( + IN EFI_LEGACY_REGION_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_UNLOCK, Granularity); +} + +EFI_STATUS LegacyRegionUnlock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return ProgramPamRegisters(Start, Length, LEGACY_REGION_UNLOCK, Granularity); +} + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: GetLegacyRegionInfo +// +// Description: +// This function is used to discover the granularity of the attributes +// for the memory in the legacy region. Each attribute may have a different +// granularity and the granularity may not be the same for all memory ranges +// in the legacy region. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This +// -- Indicates the EFI_LEGACY_REGION_PROTOCOL instance. +// +// Output: +// EFI_UNSUPPORTED - This function is not supported +// EFI_SUCCESS - The following information structure is returned: +// OUT UINT32 *DescriptorCount +// -- The number of region descriptor entries returned in the Descriptor +// buffer. See EFI_LEGACY_REGION_DESCRIPTOR definition for reference. +// OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor +// -- A pointer to a pointer used to return a buffer where the legacy +// region information is deposited. This buffer will contain a list +// of DescriptorCount number of region descriptors. This function will +// provide the memory for the buffer. +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS GetLegacyRegionInfo( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + OUT UINT32 *DescriptorCount, + OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor +) +{ + return EFI_UNSUPPORTED; // Note: to support this function there is a need + // to update NB template. +} + +EFI_LEGACY_REGION_PROTOCOL gLegacyRegionProtocol = +{ + Decode, Lock, BootLock, Unlock +}; + +EFI_LEGACY_REGION2_PROTOCOL gLegacyRegion2Protocol = +{ + LegacyRegionDecode, LegacyRegionLock, + LegacyRegionBootLock, LegacyRegionUnlock, + GetLegacyRegionInfo +}; + + +//********************************************************************** +//<AMI_PHDR_START> +// +// Procedure: InitializeLegacyRegion +// +// Description: Install the legacy region protocol. +// +// Input: +// IN EFI_HANDLE ImageHandle, +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: +// Status of the operation +// +// Notes: +// Here is the control flow of this function: +// 1. Get root bridge io protocol. +// 2. Install legacy region protocol. +// +//<AMI_PHDR_END> +//********************************************************************** +EFI_STATUS InitializeLegacyRegion( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + InitAmiLib(ImageHandle, SystemTable); + + pCpu = &Cpu; + Status = pBS->LocateProtocol(&gCpu, NULL, &pCpu); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return Status; + + Status = pBS->LocateProtocol( + &gEfiPciRootBridgeIoProtocolGuid, + NULL, + &gPciRootBridgeIo); + ASSERT_EFI_ERROR(Status); + + //Create event for boot script + Status = CreateReadyToBootEvent( + TPL_NOTIFY, + CallbackBootScript, + NULL, + &gEvtBootScript + ); + ASSERT_EFI_ERROR(Status); + + return pBS->InstallMultipleProtocolInterfaces( + &ImageHandle, + &gEfiLegacyRegionProtocolGuid, &gLegacyRegionProtocol, + &gEfiLegacyRegion2ProtocolGuid, &gLegacyRegion2Protocol, + NULL + ); +} + + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2005, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.cif b/Chipset/NB/LegacyRegion/LegacyRegion.cif new file mode 100644 index 0000000..e3c2d24 --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.cif @@ -0,0 +1,14 @@ +<component> + name = "LegacyRegion" + category = ModulePart + LocalRoot = "Chipset\NB\LegacyRegion\" + RefName = "NBLegacyRegion" +[files] +"LegacyRegion.sdl" +"LegacyRegion.mak" +"LegacyRegion.dxs" +"LegacyRegion.c" +[parts] +"LEGACY_REGION_PROTOCOLS" +"LEGACY_REGION_PROTOCOLS" +<endComponent> diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.dxs b/Chipset/NB/LegacyRegion/LegacyRegion.dxs new file mode 100644 index 0000000..b1670e2 --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.dxs @@ -0,0 +1,83 @@ +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2004, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** + +//********************************************************************** +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.dxs 1 4/02/13 6:27a Ireneyang $ +// +// $Revision: 1 $ +// +// $Date: 4/02/13 6:27a $ +//********************************************************************** +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.dxs $ +// +// 1 4/02/13 6:27a Ireneyang +// Support CSM Label 80. +// +// 2 12/26/12 6:01a Abelwu +// Support PI 1.x +// +// 1 12/25/12 3:03a Abelwu +// Move Legacy Region from CSM to NB eChipset +// +// 1 12/20/12 12:35p Olegi +// +// 4 4/27/07 5:21p Olegi +// CSM.CHM preparations. +// +// 3 5/01/06 2:22p Olegi +// +//********************************************************************** +//<AMI_FHDR_START> +// +// Name: LegacyRegion.dxs +// +// Description: Legacy Region dependency file +// +//<AMI_FHDR_END> +//********************************************************************** + +#include <Token.h> +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\Cpu.h> +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) +#include <Protocol\S3SaveState.h> +#else +#include <Protocol\BootScriptSave.h> +#endif + +DEPENDENCY_START + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID AND + EFI_CPU_ARCH_PROTOCOL_GUID AND +#if defined(PI_SPECIFICATION_VERSION)&&(PI_SPECIFICATION_VERSION>=0x0001000A) + EFI_S3_SAVE_STATE_PROTOCOL_GUID +#else + EFI_BOOT_SCRIPT_SAVE_GUID +#endif +DEPENDENCY_END + +//********************************************************************** +//********************************************************************** +//** ** +//** (C)Copyright 1985-2004, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 6145-F Northbelt Pkwy, Norcross, GA 30071 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//********************************************************************** +//********************************************************************** diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.mak b/Chipset/NB/LegacyRegion/LegacyRegion.mak new file mode 100644 index 0000000..7b47cfa --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.mak @@ -0,0 +1,96 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#********************************************************************** +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.mak 1 4/02/13 6:27a Ireneyang $ +# +# $Revision: 1 $ +# +# $Date: 4/02/13 6:27a $ +#********************************************************************** +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/LegacyRegion/LegacyRegion.mak $ +# +# 1 4/02/13 6:27a Ireneyang +# Support CSM Label 80. +# +# 2 12/26/12 6:05a Abelwu +# Move LegacyRegion from CSM to NB eChipset. +# +# 1 12/25/12 3:03a Abelwu +# Move Legacy Region from CSM to NB eChipset +# +# 1 12/20/12 12:35p Olegi +# +# 6 3/17/06 6:03p Felixp +# +# 5 12/02/05 11:44a Felixp +# +# 4 4/04/05 4:20p Sivagarn +# Included CSP Library in the build process +# +# 2 2/22/05 10:00a Sivagarn +# - Updated to latest labeled CSM & Core +# +# 3 1/18/05 3:22p Felixp +# PrintDebugMessage renamed to Trace +# +# 2 12/17/04 9:12a Olegi +# +# 1 10/26/04 9:48a Olegi +# +# 1 8/30/04 8:17p Markw +# +# 1 8/13/04 2:39p Markw +# +#********************************************************************** +#<AMI_FHDR_START> +# +# Name: LegacyRegion_mak +# +# Description: +# +#<AMI_FHDR_END> +#********************************************************************** +all : LegacyRegion + +LegacyRegion : $(BUILD_DIR)\NBLegacyRegion.mak LegacyRegionBin + +$(BUILD_DIR)\NBLegacyRegion.mak : $(LEGACY_REGION_DIR)\LegacyRegion.cif $(LEGACY_REGION_DIR)\LegacyRegion.mak $(BUILD_RULES) + $(CIF2MAK) $(LEGACY_REGION_DIR)\LegacyRegion.cif $(CIF2MAK_DEFAULTS) + +LegacyRegionBin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\NBLegacyRegion.mak all\ + GUID=59242DD8-E7CF-4979-B60E-A6067E2A185F \ + ENTRY_POINT=InitializeLegacyRegion \ + DEPEX1=$(LEGACY_REGION_DIR)\LegacyRegion.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER \ + COMPRESS=1\ + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2013, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/LegacyRegion/LegacyRegion.sdl b/Chipset/NB/LegacyRegion/LegacyRegion.sdl new file mode 100644 index 0000000..8966091 --- /dev/null +++ b/Chipset/NB/LegacyRegion/LegacyRegion.sdl @@ -0,0 +1,25 @@ +TOKEN + Name = "NB_LegacyRegion_SUPPORT" + Value = "0" + Help = "Main switch to enable North Bridge LegacyRegion support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +PATH + Name = "LEGACY_REGION_DIR" +End + +MODULE + Help = "Includes LegacyRegion.mak to Project" + File = "LegacyRegion.mak" +End + +ELINK + Name = "$(BUILD_DIR)\NBLegacyRegion.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + diff --git a/Chipset/NB/NB.ASL b/Chipset/NB/NB.ASL new file mode 100644 index 0000000..d9dfd61 --- /dev/null +++ b/Chipset/NB/NB.ASL @@ -0,0 +1,160 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB.ASL 6 5/06/13 7:12a Ireneyang $ +// +// $Revision: 6 $ +// +// $Date: 5/06/13 7:12a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB.ASL $ +// +// 6 5/06/13 7:12a Ireneyang +// [TAG] EIP105358 +// [Category] Improvement +// [Description] Save and restore the missed 81~86 reg lower nibbles for +// S3. +// [Files] NB.ASL; +// +// 5 10/14/12 11:39a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c +// +// 4 8/14/12 4:32a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.6.1. +// [Files] NB.sdl, NB.sd, NBCSP.CIF, NBDxe.c, NB.ASL, SaAudio.asl +// +// 3 7/03/12 6:39a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change the Save/Restore NB Registers position. +// [Files] NB.ASL, NBAcpi.c, NBDxe.c +// +// 2 6/14/12 4:39a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Support token to disable PEG 0 ~ 2. +// [Description] NB.sdl, NB.sd, NB.ASL, HOST_BUS.ASL +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NB.asl +// +// Description: The ASL file is for North Bridge specific function. +// +//<AMI_FHDR_END> +//************************************************************************* + +Scope(\_SB.PCI0) +{ + // Save/Restore NB Shadow Register(s) Buffer + Name (PA0H, 0) + Name (PA1H, 0) + Name (PA1L, 0) + Name (PA2H, 0) + Name (PA2L, 0) + Name (PA3H, 0) + Name (PA3L, 0) + Name (PA4H, 0) + Name (PA4L, 0) + Name (PA5H, 0) + Name (PA5L, 0) + Name (PA6H, 0) + Name (PA6L, 0) +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: NPTS +; Description: METHOD IS CALLED BY OS PRIOR TO ENTER ANY SLEEP STATE +; Input: Arg0 = Arg0 = Sleep state System about to enter +; Output: Nothing +; +;------------------------------------------------------------------------- +;<AMI_PHDR_END> +*/ + Method (NPTS, 1) { + Store(PM0H,PA0H) // 0x80 + Store(PM1H,PA1H) // 0x81 + Store(PM1L,PA1L) + Store(PM2H,PA2H) // 0x82 + Store(PM2L,PA2L) + Store(PM3H,PA3H) // 0x83 + Store(PM3L,PA3L) + Store(PM4H,PA4H) // 0x84 + Store(PM4L,PA4L) + Store(PM5H,PA5H) // 0x85 + Store(PM5L,PA5L) + Store(PM6H,PA6H) // 0x86 + Store(PM6L,PA6L) + } + +/* +;<AMI_PHDR_START> +;------------------------------------------------------------------------ +; +; Procedure: NWAK +; Description: METHOD CALLED ON WAKE UP FROM ANY SLEEP STATE +; Input: Arg0 = Sleep state System is resuming from +; Output: Nothing +; +;------------------------------------------------------------------------- +;<AMI_PHDR_END> +*/ + Method (NWAK, 1) { + Store(PA0H,PM0H) // 0x80 + Store(PA1H,PM1H) // 0x81 + Store(PA1L,PM1L) + Store(PA2H,PM2H) // 0x82 + Store(PA2L,PM2L) + Store(PA3H,PM3H) // 0x83 + Store(PA3L,PM3L) + Store(PA4H,PM4H) // 0x84 + Store(PA4L,PM4L) + Store(PA5H,PM5H) // 0x85 + Store(PA5L,PM5L) + Store(PA6H,PM6H) // 0x86 + Store(PA6L,PM6L) + } + + +}//Scope(\_SB.PCI0) + +//----------------------------------------------------------------------- +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + diff --git a/Chipset/NB/NB.cif b/Chipset/NB/NB.cif new file mode 100644 index 0000000..ab53dd2 --- /dev/null +++ b/Chipset/NB/NB.cif @@ -0,0 +1,13 @@ +<component> + name = "Intel System Agent" + category = eChipset + LocalRoot = "Chipset\NB\" + RefName = "Intel System Agent" +[files] +"ReleaseNotes.chm" +[parts] +"Intel SystemAgent NB Board" +"Intel SystemAgent NB Chipset" +"Intel SystemAgent NB Refcode" +"IntelSaGopDriver" +<endComponent> diff --git a/Chipset/NB/NBAcpi.c b/Chipset/NB/NBAcpi.c new file mode 100644 index 0000000..11024b4 --- /dev/null +++ b/Chipset/NB/NBAcpi.c @@ -0,0 +1,138 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBAcpi.c 2 7/03/12 6:39a Yurenlai $ +// +// $Revision: 2 $ +// +// $Date: 7/03/12 6:39a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBAcpi.c $ +// +// 2 7/03/12 6:39a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change the Save/Restore NB Registers position. +// [Files] NB.ASL, NBAcpi.c, NBDxe.c +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBACPI.c +// +// Description: This file contains 2 eLinks for all North Bridge ACPI +// Enabled/Disabled events. +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\SmmSwDispatch.h> + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbAcpiEnabled +// +// Description: This routine will be called when ACPI enabled. +// +// Input: DispatchHandle - Handle to the Dispatcher +// DispatchContext - SW SMM dispatcher context +// +// Output: None +// +// Notes: Porting if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbAcpiEnabled ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbAcpiDisabled +// +// Description: This routine will be called when ACPI disabled. +// +// Input: DispatchHandle - Handle to the Dispatcher +// DispatchContext - SW SMM dispatcher context +// +// Output: None +// +// Notes: Porting if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbAcpiDisabled ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +{ +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBCSP.CIF b/Chipset/NB/NBCSP.CIF new file mode 100644 index 0000000..2bc8825 --- /dev/null +++ b/Chipset/NB/NBCSP.CIF @@ -0,0 +1,22 @@ +<component> + name = "Intel SystemAgent NB Chipset" + category = ModulePart + LocalRoot = "Chipset\NB\" + RefName = "Intel SystemAgent NB Chipset" +[files] +"NBDxe.c" +"NBPEI.c" +"NBGeneric.c" +"NBCspLib.h" +"NbPciCSP.c" +"NBAcpi.c" +"NBSmm.c" +"hsw_VBios.dat" +"NB.ASL" +[parts] +"NBSMI" +"NB Protocols" +"NB PPI" +"SystemAgentWrap" +"NBLegacyRegion" +<endComponent> diff --git a/Chipset/NB/NBCspLib.h b/Chipset/NB/NBCspLib.h new file mode 100644 index 0000000..adac4ee --- /dev/null +++ b/Chipset/NB/NBCspLib.h @@ -0,0 +1,1278 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBCspLib.h 5 10/14/12 5:17a Jeffch $ +// +// $Revision: 5 $ +// +// $Date: 10/14/12 5:17a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBCspLib.h $ +// +// 5 10/14/12 5:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c; +// +// 4 10/14/12 12:20a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update by XTU4.0. +// [Files] NBPei.c, NBDxe.c, NBCspLib.h, NBGeneric.c +// +// 2 4/26/12 2:39a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Fixed PeiRamBootSupport = 1 warm boot system is hang. +// [Description] NBPEI.c, NBCspLib.h +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NbCspLib.h +// +// Description: This file contains North Bridge chipset porting functions +// and data structures definition for both PEI & DXE stage. +// +//<AMI_FHDR_END> +//************************************************************************* + +#ifndef __NBLIB_H__ +#define __NBLIB_H__ + +#include <Efi.h> +#include <Pei.h> +#include <Token.h> +#include <Protocol\PciHostBridgeResourceAllocation.h> +#include <Protocol\PciRootBridgeIo.h> +#include <PciHostBridge.h> +#include <AmiDxeLib.h> +#include <PciBus.h> + + +#if ACPI_SUPPORT + #if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x0001000A) + #include <Protocol\S3SaveState.h> + #else + #include <Protocol\BootScriptSave.h> + #endif +#endif + +#ifndef AMI_S3_SAVE_PROTOCOL + #if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x0001000A) + #define AMI_S3_SAVE_PROTOCOL EFI_S3_SAVE_STATE_PROTOCOL + #define AMI_S3_SAVE_PROTOCOL_GUID &gEfiS3SaveStateProtocolGuid + #else + #define AMI_S3_SAVE_PROTOCOL EFI_BOOT_SCRIPT_SAVE_PROTOCOL + #define AMI_S3_SAVE_PROTOCOL_GUID &gEfiBootScriptSaveGuid + #endif +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#if CSM_SUPPORT +#define LEGACY_REGION_LOCK 0 +#define LEGACY_REGION_BOOT_LOCK 1 +#define LEGACY_REGION_UNLOCK 2 +#define LEGACY_REGION_DECODE_ROM 3 +#endif + +typedef struct { + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 Reg; + EFI_BOOT_SCRIPT_WIDTH Width; + UINT32 Mask; +} BOOT_SCRIPT_NB_PCI_REG_SAVE; + +typedef struct { + UINT8 Register; + UINT8 Mask; + UINT32 StartAddress; + UINT32 Length; +} NB_PAM_STRUCT; + +UINT8 +NbFrequencyToRatio ( + UINT32 Frequency, + UINT8 RefClk, + UINT32 RefBClk +); + +UINT32 +NbRatioToFrequency ( + UINT8 Ratio, + UINT8 RefClk, + UINT32 RefBClk +); + +EFI_STATUS NBProgramPAMRegisters ( + EFI_BOOT_SERVICES *pBS, + EFI_RUNTIME_SERVICES *pRS, + UINT32 StartAddress, + UINT32 Length, + UINT8 Setting, + UINT32 *Granularity +); + +EFI_STATUS NBPeiProgramPAMRegisters ( + EFI_PEI_SERVICES **PeiServices, + UINT32 StartAddress, + UINT32 Length, + UINT8 Setting, + UINT32 *Granularity OPTIONAL +); + +VOID NBRetrainLinkPciDevice ( + IN UINT8 PciBus, + IN UINT8 PciDev, + IN UINT8 PciFun, + IN UINT8 CapPtr +); + +EFI_STATUS NBProtectedPciDevice ( + IN PCI_DEV_INFO *PciDevice +); + +EFI_STATUS NBProgramPciDevice ( + IN PCI_DEV_INFO *PciDevice +); + +EFI_STATUS NBUpdatePciDeviceAttributes ( + IN PCI_DEV_INFO *PciDevice, + IN OUT UINT64 *Attributes, + IN UINT64 Capabilities, + IN BOOLEAN Set +); + +EFI_STATUS NBPAMWriteBootScript( + IN AMI_S3_SAVE_PROTOCOL *BootScriptSave +); + +VOID NbRuntimeShadowRamWrite( + IN BOOLEAN Enable +); + +BOOLEAN +CheckPeiFvCopyToRam ( + IN EFI_PEI_SERVICES **PeiServices +); + +#if (CORE_COMBINED_VERSION >= 0x4027C) // 4.6.3.6 +#if AMI_ROOT_BRIDGE_SUPPORT == 1 +UINTN HbCspMapRootBrgToHost( + IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr, + IN UINT64 *AllocationAttr, + IN UINT64 *RbSuportedAttr +); + +EFI_STATUS HbCspAllocateResources( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex +); +#endif +#else +UINTN HbCspMapRootBrgToHost( + IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr +); +#endif + +UINT32 NBGetTsegBase ( VOID ); + +VOID NBEnableEmrr( + IN UINT32 IedStart, + IN UINT32 IedSize +); + +UINT32 NbFindCapPtr( + IN UINT64 PciAddress, + IN UINT8 CapId +); + + +VOID +WritePci8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 WriteValue8 +); + +VOID +WritePci16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 WriteValue16 +); + +VOID +WritePci32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 WriteValue32 +); + +VOID +RwPci8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID +RwPci16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID +RwPci32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +VOID +WriteMem8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT8 Value +); + +VOID +WriteMem16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT16 Value +); + +VOID +WriteMem32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT32 Value +); + +VOID +RwMem8S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID +RwMem16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID +RwMem32S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +UINT8 +ReadPci8( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg +); + +UINT16 +ReadPci16( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg +); + +UINT32 +ReadPci32( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg +); + +VOID +WritePci8( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 Value8 +); + +VOID +WritePci16( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 Value16 +); + +VOID +WritePci32( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 Value32 +); + +VOID +RwPci8( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID +RwPci16( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID +RwPci32( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +VOID +WriteMem8 ( + IN UINT64 Address, + IN UINT8 Value8 +); + +VOID +WriteMem16 ( + IN UINT64 Address, + IN UINT16 Value16 +); + +VOID +WriteMem32 ( + IN UINT64 Address, + IN UINT32 Value32 +); + +VOID +RwMem8( + IN UINT64 Address, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 +); + +VOID +RwMem16( + IN UINT64 Address, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 +); + +VOID +RwMem32( + IN UINT64 Address, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 +); + +//---------------------------------------------------------------------------- +// Standard PCI Macros, No Porting Required. +//---------------------------------------------------------------------------- + +#define READ_PCI8(Bx, Dx, Fx, Rx) ReadPci8(Bx, Dx, Fx, Rx) +#define READ_PCI16(Bx, Dx, Fx, Rx) ReadPci16(Bx, Dx, Fx, Rx) +#define READ_PCI32(Bx, Dx, Fx, Rx) ReadPci32(Bx, Dx, Fx, Rx) +#define WRITE_PCI8(Bx, Dx, Fx, Rx, bVal) WritePci8(Bx, Dx, Fx, Rx, bVal) +#define WRITE_PCI16(Bx, Dx, Fx, Rx, wVal) WritePci16(Bx, Dx, Fx, Rx, wVal) +#define WRITE_PCI32(Bx, Dx, Fx, Rx, dVal) WritePci32(Bx, Dx, Fx, Rx, dVal) +#define RW_PCI8(Bx, Dx, Fx, Rx, Set, Rst) \ + WritePci8(Bx, Dx, Fx, Rx, ReadPci8(Bx, Dx, Fx, Rx) & ~(Rst) | (Set)) +#define RW_PCI16(Bx, Dx, Fx, Rx, Set, Rst) \ + WritePci16(Bx, Dx, Fx, Rx, ReadPci16(Bx, Dx, Fx, Rx) & ~(Rst)|(Set)) +#define RW_PCI32(Bx, Dx, Fx, Rx, Set, Rst) \ + WritePci32(Bx, Dx, Fx, Rx, ReadPci32(Bx, Dx, Fx, Rx) & ~(Rst)|(Set)) +#define SET_PCI8(Bx, Dx, Fx, Rx, bSet) \ + WritePci8(Bx, Dx, Fx, Rx, ReadPci8(Bx, Dx, Fx, Rx) | (bSet)) +#define SET_PCI16(Bx, Dx, Fx, Rx, wSet) \ + WritePci16(Bx, Dx, Fx, Rx, ReadPci16(Bx, Dx, Fx, Rx) | (wSet)) +#define SET_PCI32(Bx, Dx, Fx, Rx, dSet) \ + WritePci32(Bx, Dx, Fx, Rx, ReadPci32(Bx, Dx, Fx, Rx) | (dSet)) +#define RESET_PCI8(Bx, Dx, Fx, Rx, bReset) \ + WritePci8(Bx, Dx, Fx, Rx, ReadPci8(Bx, Dx, Fx, Rx) & ~(bReset)) +#define RESET_PCI16(Bx, Dx, Fx, Rx, wRst) \ + WritePci16(Bx, Dx, Fx, Rx, ReadPci16(Bx, Dx, Fx, Rx) & ~(wRst)) +#define RESET_PCI32(Bx, Dx, Fx, Rx, dRst) \ + WritePci32(Bx, Dx, Fx, Rx, ReadPci32(Bx, Dx, Fx, Rx) & ~(dRst)) + +#define WRITE_PCI8_S3(mBtScSv, Bx, Dx, Fx, Rx, bValue) \ + WritePci8S3(mBtScSv, Bx, Dx, Fx, Rx, bValue) +#define SET_PCI8_S3(mBtScSv, Bx, Dx, Fx, Rx, bSet) \ + RwPci8S3(mBtScSv, Bx, Dx, Fx, Rx, bSet, 0) +#define RESET_PCI8_S3(mBtScSv, Bx, Dx, Fx, Rx, bReset) \ + RwPci8S3(mBtScSv, Bx, Dx, Fx, Rx, 0, bReset) +#define RW_PCI8_S3(mBtScSv, Bx, Dx, Fx, Rx, bSet, bRst) \ + RwPci8S3(mBtScSv, Bx, Dx, Fx, Rx, bSet, bRst) +#define WRITE_PCI16_S3(mBtScSv, Bx, Dx, Fx, Rx, wValue) \ + WritePci16S3(mBtScSv, Bx, Dx, Fx, Rx, wValue) +#define SET_PCI16_S3(mBtScSv, Bx, Dx, Fx, Rx, wSet) \ + RwPci16S3(mBtScSv, Bx, Dx, Fx, Rx, wSet, 0) +#define RESET_PCI16_S3(mBtScSv, Bx, Dx, Fx, Rx, wReset) \ + RwPci16S3(mBtScSv, Bx, Dx, Fx, Rx, 0, wReset) +#define RW_PCI16_S3(mBtScSv, Bx, Dx, Fx, Rx, wSet, wRst) \ + RwPci16S3(mBtScSv, Bx, Dx, Fx, Rx, wSet, wRst) +#define WRITE_PCI32_S3(mBtScSv, Bx, Dx, Fx, Rx, dValue) \ + WritePci32S3(mBtScSv, Bx, Dx, Fx, Rx, dValue) +#define SET_PCI32_S3(mBtScSv, Bx, Dx, Fx, Rx, dSet) \ + RwPci32S3(mBtScSv, Bx, Dx, Fx, Rx, dSet, 0) +#define RESET_PCI32_S3(mBtScSv, Bx, Dx, Fx, Rx, dReset) \ + RwPci32S3(mBtScSv, Bx, Dx, Fx, Rx, 0, dReset) +#define RW_PCI32_S3(mBtScSv, Bx, Dx, Fx, Rx, dSet, dRst) \ + RwPci32S3(mBtScSv, Bx, Dx, Fx, Rx, dSet, dRst) + +//---------------------------------------------------------------------------- +// Standard Memory Macros, No Porting Required. +//---------------------------------------------------------------------------- + +#define READ_MEM8(Addr64) MMIO_READ8(Addr64) +#define MEM_READ8(Addr64) MMIO_READ8(Addr64) +#define READ_MMIO8(Addr64) MMIO_READ8(Addr64) +#define WRITE_MEM8(Addr64, bValue) WriteMem8(Addr64, bValue) +#define MEM_WRITE8(Addr64, bValue) WriteMem8(Addr64, bValue) +#define WRITE_MMIO8(Addr64, bValue) WriteMem8(Addr64, bValue) +#define SET_MEM8(Addr64, bSet) RwMem8(Addr64, bSet, 0) +#define MEM_SET8(Addr64, bSet) RwMem8(Addr64, bSet, 0) +#define SET_MMIO8(Addr64, bSet) RwMem8(Addr64, bSet, 0) +#define MMIO_SET8(Addr64, bSet) RwMem8(Addr64, bSet, 0) +#define RESET_MEM8(Addr64, bReset) RwMem8(Addr64, 0, bReset) +#define MEM_RESET8(Addr64, bReset) RwMem8(Addr64, 0, bReset) +#define RESET_MMIO8(Addr64, bReset) RwMem8(Addr64, 0, bReset) +#define MMIO_RESET8(Addr64, bReset) RwMem8(Addr64, 0, bReset) +#define RW_MEM8(Addr64, bSet, bReset) RwMem8(Addr64, bSet, bReset) +#define MEM_RW8(Addr64, bSet, bReset) RwMem8(Addr64, bSet, bReset) +#define RW_MMIO8(Addr64, bSet, bReset) RwMem8(Addr64, bSet, bReset) +#define MMIO_RW8(Addr64, bSet, bReset) RwMem8(Addr64, bSet, bReset) + +#define READ_MEM16(Addr64) MMIO_READ16(Addr64) +#define MEM_READ16(Addr64) MMIO_READ16(Addr64) +#define READ_MMIO16(Addr64) MMIO_READ16(Addr64) +#define WRITE_MEM16(Addr64, wValue) WriteMem16(Addr64, wValue) +#define MEM_WRITE16(Addr64, wValue) WriteMem16(Addr64, wValue) +#define WRITE_MMIO16(Addr64, wValue) WriteMem16(Addr64, wValue) +#define SET_MEM16(Addr64, wSet) RwMem16(Addr64, wSet, 0) +#define MEM_SET16(Addr64, wSet) RwMem16(Addr64, wSet, 0) +#define SET_MMIO16(Addr64, wSet) RwMem16(Addr64, wSet, 0) +#define MMIO_SET16(Addr64, wSet) RwMem16(Addr64, wSet, 0) +#define RESET_MEM16(Addr64, wReset) RwMem16(Addr64, 0, wReset) +#define MEM_RESET16(Addr64, wReset) RwMem16(Addr64, 0, wReset) +#define RESET_MMIO16(Addr64, wReset) RwMem16(Addr64, 0, wReset) +#define MMIO_RESET16(Addr64, wReset) RwMem16(Addr64, 0, wReset) +#define RW_MEM16(Addr64, wSet, wReset) RwMem16(Addr64, wSet, wReset) +#define MEM_RW16(Addr64, wSet, wReset) RwMem16(Addr64, wSet, wReset) +#define RW_MMIO16(Addr64, wSet, wReset) RwMem16(Addr64, wSet, wReset) +#define MMIO_RW16(Addr64, wSet, wReset) RwMem16(Addr64, wSet, wReset) + +#define READ_MEM32(Addr64) MMIO_READ32(Addr64) +#define MEM_READ32(Addr64) MMIO_READ32(Addr64) +#define READ_MMIO32(Addr64) MMIO_READ32(Addr64) +#define WRITE_MEM32(Addr64, dValue) WriteMem32(Addr64, dValue) +#define MEM_WRITE32(Addr64, dValue) WriteMem32(Addr64, dValue) +#define WRITE_MMIO32(Addr64, dValue) WriteMem32(Addr64, dValue) +#define SET_MEM32(Addr64, dSet) RwMem32(Addr64, dSet, 0) +#define MEM_SET32(Addr64, dSet) RwMem32(Addr64, dSet, 0) +#define SET_MMIO32(Addr64, dSet) RwMem32(Addr64, dSet, 0) +#define MMIO_SET32(Addr64, dSet) RwMem32(Addr64, dSet, 0) +#define RESET_MEM32(Addr64, dReset) RwMem32(Addr64, 0, dReset) +#define MEM_RESET32(Addr64, dReset) RwMem32(Addr64, 0, dReset) +#define RESET_MMIO32(Addr64, dReset) RwMem32(Addr64, 0, dReset) +#define MMIO_RESET32(Addr64, dReset) RwMem32(Addr64, 0, dReset) +#define RW_MEM32(Addr64, dSet, dReset) RwMem32(Addr64, dSet, dReset) +#define MEM_RW32(Addr64, dSet, dReset) RwMem32(Addr64, dSet, dReset) +#define RW_MMIO32(Addr64, dSet, dReset) RwMem32(Addr64, dSet, dReset) +#define MMIO_RW32(Addr64, dSet, dReset) RwMem32(Addr64, dSet, dReset) + +//---------------------------------------------------------------------------- + +#define WRITE_MEM8_S3(mBtScSv, Addr64, bValue) \ + WriteMem8S3(mBtScSv, Addr64, bValue) +#define MEM_WRITE8_S3(mBtScSv, Addr64, bValue) \ + WriteMem8S3(mBtScSv, Addr64, bValue) +#define WRITE_MMIO8_S3(mBtScSv, Addr64, bValue) \ + WriteMem8S3(mBtScSv, Addr64, bValue) +#define MMIO_WRITE8_S3(mBtScSv, Addr64, bValue) \ + WriteMem8S3(mBtScSv, Addr64, bValue) +#define SET_MEM8_S3(mBtScSv, Addr64, bSet) \ + RwMem8S3(mBtScSv, Addr64, bSet, 0) +#define MEM_SET8_S3(mBtScSv, Addr64, bSet) \ + RwMem8S3(mBtScSv, Addr64, bSet, 0) +#define SET_MMIO8_S3(mBtScSv, Addr64, bSet) \ + RwMem8S3(mBtScSv, Addr64, bSet, 0) +#define MMIO_SET8_S3(mBtScSv, Addr64, bSet) \ + RwMem8S3(mBtScSv, Addr64, bSet, 0) +#define RESET_MEM8_S3(mBtScSv, Addr64, bReset) \ + RwMem8S3(mBtScSv, Addr64, 0, bReset) +#define MEM_RESET8_S3(mBtScSv, Addr64, bReset) \ + RwMem8S3(mBtScSv, Addr64, 0, bReset) +#define RESET_MMIO8_S3(mBtScSv, Addr64, bReset) \ + RwMem8S3(mBtScSv, Addr64, 0, bReset) +#define MMIO_RESET8_S3(mBtScSv, Addr64, bReset) \ + RwMem8S3(mBtScSv, Addr64, 0, bReset) +#define RW_MEM8_S3(mBtScSv, Addr64, bSet, bReset) \ + RwMem8S3(mBtScSv, Addr64, bSet, bReset) +#define MEM_RW8_S3(mBtScSv, Addr64, bSet, bReset) \ + RwMem8S3(mBtScSv, Addr64, bSet, bReset) +#define RW_MMIO8_S3(mBtScSv, Addr64, bSet, bReset) \ + RwMem8S3(mBtScSv, Addr64, bSet, bReset) +#define MMIO_RW8_S3(mBtScSv, Addr64, bSet, bReset) \ + RwMem8S3(mBtScSv, Addr64, bSet, bReset) +#define WRITE_MEM16_S3(mBtScSv, Addr64, wValue) \ + WriteMem16S3(mBtScSv, Addr64, wValue) +#define MEM_WRITE16_S3(mBtScSv, Addr64, wValue) \ + WriteMem16S3(mBtScSv, Addr64, wValue) +#define WRITE_MMIO16_S3(mBtScSv, Addr64, wValue) \ + WriteMem16S3(mBtScSv, Addr64, wValue) +#define MMIO_WRITE16_S3(mBtScSv, Addr64, wValue) \ + WriteMem16S3(mBtScSv, Addr64, wValue) +#define SET_MEM16_S3(mBtScSv, Addr64, wSet) \ + RwMem16S3(mBtScSv, Addr64, wSet, 0) +#define MEM_SET16_S3(mBtScSv, Addr64, wSet) \ + RwMem16S3(mBtScSv, Addr64, wSet, 0) +#define SET_MMIO16_S3(mBtScSv, Addr64, wSet) \ + RwMem16S3(mBtScSv, Addr64, wSet, 0) +#define MMIO_SET16_S3(mBtScSv, Addr64, wSet) \ + RwMem16S3(mBtScSv, Addr64, wSet, 0) +#define RESET_MEM16_S3(mBtScSv, Addr64, wReset) \ + RwMem16S3(mBtScSv, Addr64, 0, wReset) +#define MEM_RESET16_S3(mBtScSv, Addr64, wReset) \ + RwMem16S3(mBtScSv, Addr64, 0, wReset) +#define RESET_MMIO16_S3(mBtScSv, Addr64, wReset) \ + RwMem16S3(mBtScSv, Addr64, 0, wReset) +#define MMIO_RESET16_S3(mBtScSv, Addr64, wReset) \ + RwMem16S3(mBtScSv, Addr64, 0, wReset) +#define RW_MEM16_S3(mBtScSv, Addr64, wSet, wReset) \ + RwMem16S3(mBtScSv, Addr64, wSet, wReset) +#define MEM_RW16_S3(mBtScSv, Addr64, wSet, wReset) \ + RwMem16S3(mBtScSv, Addr64, wSet, wReset) +#define RW_MMIO16_S3(mBtScSv, Addr64, wSet, wReset) \ + RwMem16S3(mBtScSv, Addr64, wSet, wReset) +#define MMIO_RW16_S3(mBtScSv, Addr64, wSet, wReset) \ + RwMem16S3(mBtScSv, Addr64, wSet, wReset) +#define WRITE_MEM32_S3(mBtScSv, Addr64, dValue) \ + WriteMem32S3(mBtScSv, Addr64, dValue) +#define MEM_WRITE32_S3(mBtScSv, Addr64, dValue) \ + WriteMem32S3(mBtScSv, Addr64, dValue) +#define WRITE_MMIO32_S3(mBtScSv, Addr64, dValue) \ + WriteMem32S3(mBtScSv, Addr64, dValue) +#define MMIO_WRITE32_S3(mBtScSv, Addr64, dValue) \ + WriteMem32S3(mBtScSv, Addr64, dValue) +#define SET_MEM32_S3(mBtScSv, Addr64, dSet) \ + RwMem32S3(mBtScSv, Addr64, dSet, 0) +#define MEM_SET32_S3(mBtScSv, Addr64, dSet) \ + RwMem32S3(mBtScSv, Addr64, dSet, 0) +#define SET_MMIO32_S3(mBtScSv, Addr64, dSet) \ + RwMem32S3(mBtScSv, Addr64, dSet, 0) +#define MMIO_SET32_S3(mBtScSv, Addr64, dSet) \ + RwMem32S3(mBtScSv, Addr64, dSet, 0) +#define RESET_MEM32_S3(mBtScSv, Addr64, dReset) \ + RwMem32S3(mBtScSv, Addr64, 0, dReset) +#define MEM_RESET32_S3(mBtScSv, Addr64, dReset) \ + RwMem32S3(mBtScSv, Addr64, 0, dReset) +#define RESET_MMIO32_S3(mBtScSv, Addr64, dReset) \ + RwMem32S3(mBtScSv, Addr64, 0, dReset) +#define MMIO_RESET32_S3(mBtScSv, Addr64, dReset) \ + RwMem32S3(mBtScSv, Addr64, 0, dReset) +#define RW_MEM32_S3(mBtScSv, Addr64, dSet, dReset) \ + RwMem32S3(mBtScSv, Addr64, dSet, dReset) +#define MEM_RW32_S3(mBtScSv, Addr64, dSet, dReset) \ + RwMem32S3(mBtScSv, Addr64, dSet, dReset) +#define RW_MMIO32_S3(mBtScSv, Addr64, dSet, dReset) \ + RwMem32S3(mBtScSv, Addr64, dSet, dReset) +#define MMIO_RW32_S3(mBtScSv, Addr64, dSet, dReset) \ + RwMem32S3(mBtScSv, Addr64, dSet, dReset) + +//---------------------------------------------------------------------------- +// Chipset PCI Macros, Porting Required. +//---------------------------------------------------------------------------- + +#define READ_PCI8_NB(Rx) READ_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx) +#define WRITE_PCI8_NB(Rx, Val) WRITE_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI8_NB(Rx, Set) SET_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI8_NB(Rx, Rst) RESET_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx, Rst) +#define RW_PCI8_NB(Rx, St, Rt) RW_PCI8(NB_BUS, NB_DEV, NB_FUN, Rx, St, Rt) +#define READ_PCI16_NB(Rx) READ_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx) +#define WRITE_PCI16_NB(Rx, Val) WRITE_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI16_NB(Rx, Set) SET_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI16_NB(Rx, Rst) RESET_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx, Rst) +#define RW_PCI16_NB(Rx, St, Rt) RW_PCI16(NB_BUS, NB_DEV, NB_FUN, Rx, St, Rt) +#define READ_PCI32_NB(Rx) READ_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx) +#define WRITE_PCI32_NB(Rx, Val) WRITE_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI32_NB(Rx, Set) SET_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI32_NB(Rx, Rst) RESET_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx, Rst) +#define RW_PCI32_NB(Rx, St, Rt) RW_PCI32(NB_BUS, NB_DEV, NB_FUN, Rx, St, Rt) + +//---------------------------------------------------------------------------- + +#define READ_PCI8_PCIEBRN(Rx) \ + READ_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx) +#define WRITE_PCI8_PCIEBRN(Rx, Val) \ + WRITE_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Val) +#define SET_PCI8_PCIEBRN(Rx, Set) \ + SET_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI8_PCIEBRN(Rx, Rst) \ + RESET_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rst) +#define RW_PCI8_PCIEBRN(Rx, St, Rt) \ + RW_PCI8(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St, Rt) +#define READ_PCI16_PCIEBRN(Rx) \ + READ_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx) +#define WRITE_PCI16_PCIEBRN(Rx, Vx) \ + WRITE_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Vx) +#define SET_PCI16_PCIEBRN(Rx, Set) \ + SET_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI16_PCIEBRN(Rx, Rt) \ + RESET_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rt) +#define RW_PCI16_PCIEBRN(Rx, St, Rt) \ + RW_PCI16(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St,Rt) +#define READ_PCI32_PCIEBRN(Rx) \ + READ_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx) +#define WRITE_PCI32_PCIEBRN(Rx, Vx) \ + WRITE_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Vx) +#define SET_PCI32_PCIEBRN(Rx, Set) \ + SET_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI32_PCIEBRN(Rx, Rt) \ + RESET_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rt) +#define RW_PCI32_PCIEBRN(Rx, St, Rt) \ + RW_PCI32(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St,Rt) + +//---------------------------------------------------------------------------- + +#define READ_PCI8_IGD(Rx) READ_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx) +#define WRITE_PCI8_IGD(Rx, Val) WRITE_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Val) +#define SET_PCI8_IGD(Rx, Set) SET_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI8_IGD(Rx, Rst) RESET_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Rst) +#define RW_PCI8_IGD(Rx, St, Rt) RW_PCI8(IGD_BUS, IGD_DEV, IGD_FUN, Rx, St, Rt) +#define READ_PCI16_IGD(Rx) READ_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx) +#define WRITE_PCI16_IGD(Rx, Vx) WRITE_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Vx) +#define SET_PCI16_IGD(Rx, Set) SET_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI16_IGD(Rx, Rt) RESET_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Rt) +#define RW_PCI16_IGD(Rx, St,Rt) RW_PCI16(IGD_BUS, IGD_DEV, IGD_FUN, Rx, St,Rt) +#define READ_PCI32_IGD(Rx) READ_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx) +#define WRITE_PCI32_IGD(Rx, Vx) WRITE_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Vx) +#define SET_PCI32_IGD(Rx, Set) SET_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI32_IGD(Rx, Rt) RESET_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx, Rt) +#define RW_PCI32_IGD(Rx, St,Rt) RW_PCI32(IGD_BUS, IGD_DEV, IGD_FUN, Rx, St,Rt) + +//---------------------------------------------------------------------------- + +#define WRITE_PCI8_NB_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI8_NB_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI8_NB_S3(mBoot, Rx, Reset) \ + RESET_PCI8_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Reset) +#define RW_PCI8_NB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set, Rst) +#define WRITE_PCI16_NB_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI16_NB_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI16_NB_S3(mBoot, Rx, Reset) \ + RESET_PCI16_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Reset) +#define RW_PCI16_NB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set, Rst) +#define WRITE_PCI32_NB_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Val) +#define SET_PCI32_NB_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set) +#define RESET_PCI32_NB_S3(mBoot, Rx, Reset) \ + RESET_PCI32_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Reset) +#define RW_PCI32_NB_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, NB_BUS, NB_DEV, NB_FUN, Rx, Set, Rst) + +//---------------------------------------------------------------------------- + +#define WRITE_PCI8_PCIEBRN_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Val) +#define SET_PCI8_PCIEBRN_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI8_PCIEBRN_S3(mBoot, Rx, Rst) \ + RESET_PCI8_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rst) +#define RW_PCI8_PCIEBRN_S3(mBoot, Rx, St, Rt) \ + RW_PCI8_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St, Rt) +#define WRITE_PCI16_PCIEBRN_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Val) +#define SET_PCI16_PCIEBRN_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI16_PCIEBRN_S3(mBoot, Rx, Rst) \ + RESET_PCI16_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rst) +#define RW_PCI16_PCIEBRN_S3(mBoot, Rx, St, Rt) \ + RW_PCI16_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St, Rt) +#define WRITE_PCI32_PCIEBRN_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Val) +#define SET_PCI32_PCIEBRN_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Set) +#define RESET_PCI32_PCIEBRN_S3(mBoot, Rx, Reset) \ + RESET_PCI32_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, Rst) +#define RW_PCI32_PCIEBRN_S3(mBoot, Rx, St, Rt) \ + RW_PCI32_S3(mBoot, PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, Rx, St, Rt) + +//---------------------------------------------------------------------------- + +#define WRITE_PCI8_IGD_S3(mBoot, Rx, Val) \ + WRITE_PCI8_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Val) +#define SET_PCI8_IGD_S3(mBoot, Rx, Set) \ + SET_PCI8_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI8_IGD_S3(mBoot, Rx, Reset) \ + RESET_PCI8_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Reset) +#define RW_PCI8_IGD_S3(mBoot, Rx, Set, Rst) \ + RW_PCI8_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set, Rst) +#define WRITE_PCI16_IGD_S3(mBoot, Rx, Val) \ + WRITE_PCI16_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Val) +#define SET_PCI16_IGD_S3(mBoot, Rx, Set) \ + SET_PCI16_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI16_IGD_S3(mBoot, Rx, Reset) \ + RESET_PCI16_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Reset) +#define RW_PCI16_IGD_S3(mBoot, Rx, Set, Rst) \ + RW_PCI16_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set, Rst) +#define WRITE_PCI32_IGD_S3(mBoot, Rx, Val) \ + WRITE_PCI32_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Val) +#define SET_PCI32_IGD_S3(mBoot, Rx, Set) \ + SET_PCI32_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set) +#define RESET_PCI32_IGD_S3(mBoot, Rx, Reset) \ + RESET_PCI32_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Reset) +#define RW_PCI32_IGD_S3(mBoot, Rx, Set, Rst) \ + RW_PCI32_S3(mBoot, IGD_BUS, IGD_DEV, IGD_FUN, Rx, Set, Rst) + +//---------------------------------------------------------------------------- +// Chipset MMIO Macros, Porting Required. +//---------------------------------------------------------------------------- + +#define READ_MEM8_EP(wReg) READ_MEM8(NB_EP_BASE_ADDRESS | wReg) +#define READ_MMIO8_EP(wReg) READ_MEM8(NB_EP_BASE_ADDRESS | wReg) +#define WRITE_MEM8_EP(wReg, bVal) WRITE_MEM8(NB_EP_BASE_ADDRESS | wReg,bVal) +#define WRITE_MMIO8_EP(wReg, bVal) WRITE_MEM8(NB_EP_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_EP(wReg, Set) RW_MEM8(NB_EP_BASE_ADDRESS | wReg, Set, 0) +#define SET_MMIO8_EP(wReg, Set) RW_MEM8(NB_EP_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_EP(wReg, Rst) RW_MEM8(NB_EP_BASE_ADDRESS | wReg, 0, Rst) +#define RESET_MMIO8_EP(wReg, Rst) RW_MEM8(NB_EP_BASE_ADDRESS | wReg, 0, Rst) +#define RW_MEM8_EP(wReg, Set, Rst) RW_MEM8(NB_EP_BASE_ADDRESS|wReg, Set, Rst) +#define RW_MMIO8_EP(wReg, Set, Rst) RW_MEM8(NB_EP_BASE_ADDRESS|wReg, Set, Rst) +#define READ_MEM16_EP(wReg) READ_MEM16(NB_EP_BASE_ADDRESS | wReg) +#define READ_MMIO16_EP(wReg) READ_MEM16(NB_EP_BASE_ADDRESS | wReg) +#define WRITE_MEM16_EP(wReg, wVal) WRITE_MEM16(NB_EP_BASE_ADDRESS|wReg, wVal) +#define WRITE_MMIO16_EP(wReg, wVal) WRITE_MEM16(NB_EP_BASE_ADDRESS|wReg, wVal) +#define SET_MEM16_EP(wReg, Set) RW_MEM16(NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO16_EP(wReg, Set) RW_MEM16(NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM16_EP(wReg, Rst) RW_MEM16(NB_EP_BASE_ADDRESS | wReg, 0,Rst) +#define RESET_MMIO16_EP(wReg, Rst) RW_MEM16(NB_EP_BASE_ADDRESS | wReg, 0,Rst) +#define RW_MEM16_EP(wReg, Set, Rst) RW_MEM16(NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO16_EP(wReg, Set,Rst) RW_MEM16(NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define READ_MEM32_EP(wReg) READ_MEM32(NB_EP_BASE_ADDRESS | wReg) +#define READ_MMIO32_EP(wReg) READ_MEM32(NB_EP_BASE_ADDRESS | wReg) +#define WRITE_MEM32_EP(wReg, dVal) WRITE_MEM32(NB_EP_BASE_ADDRESS|wReg, dVal) +#define WRITE_MMIO32_EP(wReg, dVal) WRITE_MEM32(NB_EP_BASE_ADDRESS|wReg, dVal) +#define SET_MEM32_EP(wReg, Set) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_EP(wReg, Set) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_EP(wReg, Rst) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_EP(wReg, Rst) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_EP(wReg, Set, Rst) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO32_EP(wReg, Set,Rst) RW_MEM32(NB_EP_BASE_ADDRESS|wReg, Set,Rst) + +//---------------------------------------------------------------------------- + +#define READ_MEM8_MCH(wReg) READ_MEM8(NB_MCH_BASE_ADDRESS | wReg) +#define READ_MMIO8_MCH(wReg) READ_MEM8(NB_MCH_BASE_ADDRESS | wReg) +#define WRITE_MEM8_MCH(wReg, bVal) WRITE_MEM8(NB_MCH_BASE_ADDRESS| wReg,bVal) +#define WRITE_MMIO8_MCH(wReg, bVal) WRITE_MEM8(NB_MCH_BASE_ADDRESS| wReg,bVal) +#define SET_MEM8_MCH(wReg, Set) RW_MEM8(NB_MCH_BASE_ADDRESS | wReg, Set,0) +#define SET_MMIO8_MCH(wReg, Set) RW_MEM8(NB_MCH_BASE_ADDRESS | wReg, Set,0) +#define RESET_MEM8_MCH(wReg, Rst) RW_MEM8(NB_MCH_BASE_ADDRESS | wReg,0, Rst) +#define RESET_MMIO8_MCH(wReg, Rst) RW_MEM8(NB_MCH_BASE_ADDRESS | wReg,0, Rst) +#define RW_MEM8_MCH(wReg, Set, Rst) RW_MEM8(NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO8_MCH(wReg, Set,Rst) RW_MEM8(NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define READ_MEM16_MCH(wReg) READ_MEM16(NB_MCH_BASE_ADDRESS | wReg) +#define READ_MMIO16_MCH(wReg) READ_MEM16(NB_MCH_BASE_ADDRESS | wReg) +#define WRITE_MEM16_MCH(wReg, wVal) WRITE_MEM16(NB_MCH_BASE_ADDRESS|wReg,wVal) +#define WRITE_MMIO16_MCH(wReg,wVal) WRITE_MEM16(NB_MCH_BASE_ADDRESS|wReg,wVal) +#define SET_MEM16_MCH(wReg, Set) RW_MEM16(NB_MCH_BASE_ADDRESS|wReg,Set, 0) +#define SET_MMIO16_MCH(wReg, Set) RW_MEM16(NB_MCH_BASE_ADDRESS|wReg,Set, 0) +#define RESET_MEM16_MCH(wReg, Rst) RW_MEM16(NB_MCH_BASE_ADDRESS | wReg,0,Rst) +#define RESET_MMIO16_MCH(wReg, Rst) RW_MEM16(NB_MCH_BASE_ADDRESS | wReg,0,Rst) +#define RW_MEM16_MCH(wReg, Set,Rst) RW_MEM16(NB_MCH_BASE_ADDRESS|wReg,Set,Rst) +#define RW_MMIO16_MCH(wReg,Set,Rst) RW_MEM16(NB_MCH_BASE_ADDRESS|wReg,Set,Rst) +#define READ_MEM32_MCH(wReg) READ_MEM32(NB_MCH_BASE_ADDRESS | wReg) +#define READ_MMIO32_MCH(wReg) READ_MEM32(NB_MCH_BASE_ADDRESS | wReg) +#define WRITE_MEM32_MCH(wReg, dVal) WRITE_MEM32(NB_MCH_BASE_ADDRESS|wReg,dVal) +#define WRITE_MMIO32_MCH(wReg,dVal) WRITE_MEM32(NB_MCH_BASE_ADDRESS|wReg,dVal) +#define SET_MEM32_MCH(wReg, Set) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_MCH(wReg, Set) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_MCH(wReg, Rst) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_MCH(wReg, Rst) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_MCH(wReg, Set,Rst) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg,Set,Rst) +#define RW_MMIO32_MCH(wReg,Set,Rst) RW_MEM32(NB_MCH_BASE_ADDRESS|wReg,Set,Rst) + +//---------------------------------------------------------------------------- + +#define READ_MEM8_DMI(wReg) READ_MEM8(NB_DMI_BASE_ADDRESS | wReg) +#define READ_MMIO8_DMI(wReg) READ_MEM8(NB_DMI_BASE_ADDRESS | wReg) +#define WRITE_MEM8_DMI(wReg, bVal) WRITE_MEM8(NB_DMI_BASE_ADDRESS| wReg,bVal) +#define WRITE_MMIO8_DMI(wReg, bVal) WRITE_MEM8(NB_DMI_BASE_ADDRESS| wReg,bVal) +#define SET_MEM8_DMI(wReg, Set) RW_MEM8(NB_DMI_BASE_ADDRESS | wReg, Set,0) +#define SET_MMIO8_DMI(wReg, Set) RW_MEM8(NB_DMI_BASE_ADDRESS | wReg, Set,0) +#define RESET_MEM8_DMI(wReg, Rst) RW_MEM8(NB_DMI_BASE_ADDRESS | wReg,0, Rst) +#define RESET_MMIO8_DMI(wReg, Rst) RW_MEM8(NB_DMI_BASE_ADDRESS | wReg,0, Rst) +#define RW_MEM8_DMI(wReg, Set, Rst) RW_MEM8(NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO8_DMI(wReg, Set,Rst) RW_MEM8(NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define READ_MEM16_DMI(wReg) READ_MEM16(NB_DMI_BASE_ADDRESS | wReg) +#define READ_MMIO16_DMI(wReg) READ_MEM16(NB_DMI_BASE_ADDRESS | wReg) +#define WRITE_MEM16_DMI(wReg, wVal) WRITE_MEM16(NB_DMI_BASE_ADDRESS|wReg,wVal) +#define WRITE_MMIO16_DMI(wReg,wVal) WRITE_MEM16(NB_DMI_BASE_ADDRESS|wReg,wVal) +#define SET_MEM16_DMI(wReg, Set) RW_MEM16(NB_DMI_BASE_ADDRESS|wReg,Set, 0) +#define SET_MMIO16_DMI(wReg, Set) RW_MEM16(NB_DMI_BASE_ADDRESS|wReg,Set, 0) +#define RESET_MEM16_DMI(wReg, Rst) RW_MEM16(NB_DMI_BASE_ADDRESS | wReg,0,Rst) +#define RESET_MMIO16_DMI(wReg, Rst) RW_MEM16(NB_DMI_BASE_ADDRESS | wReg,0,Rst) +#define RW_MEM16_DMI(wReg, Set,Rst) RW_MEM16(NB_DMI_BASE_ADDRESS|wReg,Set,Rst) +#define RW_MMIO16_DMI(wReg,Set,Rst) RW_MEM16(NB_DMI_BASE_ADDRESS|wReg,Set,Rst) +#define READ_MEM32_DMI(wReg) READ_MEM32(NB_DMI_BASE_ADDRESS | wReg) +#define READ_MMIO32_DMI(wReg) READ_MEM32(NB_DMI_BASE_ADDRESS | wReg) +#define WRITE_MEM32_DMI(wReg, dVal) WRITE_MEM32(NB_DMI_BASE_ADDRESS|wReg,dVal) +#define WRITE_MMIO32_DMI(wReg,dVal) WRITE_MEM32(NB_DMI_BASE_ADDRESS|wReg,dVal) +#define SET_MEM32_DMI(wReg, Set) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_DMI(wReg, Set) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_DMI(wReg, Rst) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_DMI(wReg,Rst) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_DMI(wReg, Set,Rst) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg,Set,Rst) +#define RW_MMIO32_DMI(wReg,Set,Rst) RW_MEM32(NB_DMI_BASE_ADDRESS|wReg,Set,Rst) + +//---------------------------------------------------------------------------- + +#define WRITE_MEM8_EP_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg,bVal) +#define WRITE_MMIO8_EP_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_EP_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, Set, 0) +#define SET_MMIO8_EP_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_EP_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, 0, Rst) +#define RESET_MMIO8_EP_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, 0, Rst) +#define RW_MEM8_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, Rst) +#define RW_MMIO8_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, Rst) +#define WRITE_MEM16_EP_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, wVal) +#define WRITE_MMIO16_EP_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, wVal) +#define SET_MEM16_EP_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO16_EP_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM16_EP_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, 0,Rst) +#define RESET_MMIO16_EP_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS | wReg, 0,Rst) +#define RW_MEM16_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO16_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define WRITE_MEM32_EP_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, dVal) +#define WRITE_MMIO32_EP_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, dVal) +#define SET_MEM32_EP_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_EP_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_EP_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_EP_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO32_EP_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_EP_BASE_ADDRESS|wReg, Set,Rst) + +//---------------------------------------------------------------------------- + +#define WRITE_MEM8_MCH_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg,bVal) +#define WRITE_MMIO8_MCH_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_MCH_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, Set, 0) +#define SET_MMIO8_MCH_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, 0, Rst) +#define RESET_MMIO8_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, 0, Rst) +#define RW_MEM8_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, Rst) +#define RW_MMIO8_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, Rst) +#define WRITE_MEM16_MCH_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, wVal) +#define WRITE_MMIO16_MCH_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, wVal) +#define SET_MEM16_MCH_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO16_MCH_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM16_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, 0,Rst) +#define RESET_MMIO16_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS | wReg, 0,Rst) +#define RW_MEM16_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO16_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define WRITE_MEM32_MCH_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, dVal) +#define WRITE_MMIO32_MCH_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, dVal) +#define SET_MEM32_MCH_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_MCH_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_MCH_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO32_MCH_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_MCH_BASE_ADDRESS|wReg, Set,Rst) + +//---------------------------------------------------------------------------- + +#define WRITE_MEM8_DMI_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg,bVal) +#define WRITE_MMIO8_DMI_S3(mBoot, wReg, bVal) \ + WRITE_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg,bVal) +#define SET_MEM8_DMI_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, Set, 0) +#define SET_MMIO8_DMI_S3(mBoot, wReg, Set) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, Set, 0) +#define RESET_MEM8_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, 0, Rst) +#define RESET_MMIO8_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, 0, Rst) +#define RW_MEM8_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, Rst) +#define RW_MMIO8_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM8_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, Rst) +#define WRITE_MEM16_DMI_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, wVal) +#define WRITE_MMIO16_DMI_S3(mBoot, wReg, wVal) \ + WRITE_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, wVal) +#define SET_MEM16_DMI_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO16_DMI_S3(mBoot, wReg, Set) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM16_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, 0,Rst) +#define RESET_MMIO16_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS | wReg, 0,Rst) +#define RW_MEM16_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO16_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM16_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define WRITE_MEM32_DMI_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, dVal) +#define WRITE_MMIO32_DMI_S3(mBoot, wReg, dVal) \ + WRITE_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, dVal) +#define SET_MEM32_DMI_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define SET_MMIO32_DMI_S3(mBoot, wReg, Set) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set, 0) +#define RESET_MEM32_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, 0, Rst) +#define RESET_MMIO32_DMI_S3(mBoot, wReg, Rst) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, 0, Rst) +#define RW_MEM32_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set,Rst) +#define RW_MMIO32_DMI_S3(mBoot, wReg, Set, Rst) \ + RW_MEM32_S3(mBoot, NB_DMI_BASE_ADDRESS|wReg, Set,Rst) + +//---------------------------------------------------------------------------- +// Chipset I/O Macros, Porting Required if needed. +//---------------------------------------------------------------------------- + +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- +//---------------------------------------------------------------------------- + +//To Exclude AMI Native Root Bridge Driver HOOKS from CSP LIB +#if AMI_ROOT_BRIDGE_SUPPORT == 1 + +//---------------------------------------------------------------------------- +//Function Prototypes for PciRootBridgeIo +//---------------------------------------------------------------------------- + +extern DXE_SERVICES *gDxeSvcTbl; + +EFI_STATUS HbResAllocNotifyPhase ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase +); + +EFI_STATUS HbResAllocGetNextRootBridge ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHandle +); + +EFI_STATUS HbResAllocGetAllocAttributes ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes +); + +EFI_STATUS HbResAllocStartBusEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration +); + +EFI_STATUS HbResAllocSetBusNumbers ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration +); + +EFI_STATUS HbResAllocSubmitResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration +); + +EFI_STATUS HbResAllocGetProposedResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration +); + +EFI_STATUS HbResAllocPreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_CONFIGURATION_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase +); + +EFI_STATUS HbNotifyCspBeforeEnumeration ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspBeginBusAllocation ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspEndBusAllocation ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspBeginResourceAllocation ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspAllocateResources ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspSetResources ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbNotifyCspEndResourceAllocation ( + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + UINTN RbCount +); + +EFI_STATUS HbCspStartBusEnumeration ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgIndex +); + +EFI_STATUS HbCspSetBusNnumbers ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgIndex +); + +EFI_STATUS HbCspSubmitResources ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgIndex +); + +EFI_STATUS HbCspAdjustMemoryMmioOverlap ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgIndex +); + +EFI_STATUS HbCspBasicChipsetInit ( + PCI_HOST_BRG_DATA *HostBrg0 +); + +UINTN HbCspGetPciSegment ( + UINTN HostBridgeNumber, + UINTN RootBridgeNumber +); + +EFI_STATUS HbCspPreprocessController ( + PCI_HOST_BRG_DATA *HostBrgData, + PCI_ROOT_BRG_DATA *RootBrgData, + UINTN RootBrgNumber, + EFI_PCI_CONFIGURATION_ADDRESS PciAddress, + EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase +); + +EFI_STATUS RbCspIoPciMap ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN EFI_PHYSICAL_ADDRESS HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping +); + +EFI_STATUS RbCspIoPciUnmap ( + IN PCI_ROOT_BRG_DATA *RbData, + IN PCI_ROOT_BRIDGE_MAPPING *Mapping +); + +EFI_STATUS RbCspIoPciAttributes( + IN PCI_ROOT_BRG_DATA *RbData, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase OPTIONAL, + IN OUT UINT64 *ResourceLength OPTIONAL +); + +EFI_STATUS RootBridgeIoPciRW ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer, + IN BOOLEAN Write +); + +EFI_STATUS RbCspIoPciUnmap ( + IN PCI_ROOT_BRG_DATA *RbData, + OUT PCI_ROOT_BRIDGE_MAPPING *Mapping +); + +EFI_STATUS RbCspIoPciMap ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN EFI_PHYSICAL_ADDRESS HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping +); + +//-------------------------------------- +//#if AMI_ROOT_BRIDGE_SUPPORT == 1 +#endif + +#ifdef __cplusplus +} +#endif +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBDxe.c b/Chipset/NB/NBDxe.c new file mode 100644 index 0000000..15dbbd0 --- /dev/null +++ b/Chipset/NB/NBDxe.c @@ -0,0 +1,4650 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBDxe.c 50 12/02/14 3:20a Dennisliu $ +// +// $Revision: 50 $ +// +// $Date: 12/02/14 3:20a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBDxe.c $ +// +// 50 12/02/14 3:20a Dennisliu +// [TAG] EIP194524 +// [Category] Spec Update +// [Description] Shark Bay SA Reference Code Production Version 1.9.0 +// +// 49 5/28/14 3:03a Dennisliu +// [TAG] EIP161790 +// [Category] Improvement +// [Description] DRAM Init BIT should be set after saving MRC S3 data to +// NVRAM in DXE Phase as Intel suggested. +// [Files] NBPei.c; NBDxe.c; +// +// 48 5/13/14 10:40p Dennisliu +// [TAG] EIP167027 +// [Category] Improvement +// [Description] [SharkBay Aptio4]Variable's attribute needs to be +// reviewed by SA component driver +// [Files] NBDXEBoard.c; IntelSaGopSetup.c; IntelSaGopPolicy.c; +// NBDxe.c; NbPciCSP.c; PciHostBridge.c; +// +// 47 7/16/13 6:57a Jeffch +// [TAG] None +// [Severity] Improvement +// [Description] Remove same offset acpi device. +// [Files] NBDXE.c; +// +// 46 7/09/13 4:23a Ireneyang +// [TAG] EIP128014 +// [Category] BrugFix +// [Symptom] When populating PC3L DIMM x2 or upper DIMM slot only, +// DMI type17 has wrong values. +// [RootCause] When using Dimm with SPD funciton, there's no need to +// use when using memorydown way to get spd data. +// [Solution] Only when using memorydown Dimm needs to get SPD data. +// [Files] NBDxe.c; +// +// 45 5/24/13 6:21a Jeffch +// [TAG] None +// [Severity] BugFix +// [Description] Fix smbios type 17 data is incorrect for memory down +// system . +// [Files] NBDxe.c; +// +// 44 4/01/13 11:47p Ireneyang +// # [TAG] None +// [Severity] Improvement +// [Description] Reduce boot time through PEG. +// [Files] NB.mak; NBDxe.c; NBPEI.c; NBPPI.h; Sa.asl; +// PcieComplex.c; GraphicsInit.c; PciExpressInit.c; +// +// 43 3/15/13 1:56a Ireneyang +// [TAG] EIP118133 +// [Severity] BugFix +// [Description] Fix and restructure PlatformConfig setting of SA policy. +// [Files] NBDxe.c; GetSetupData.c; NbSetupData.h; +// +// 42 3/12/13 2:30a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Remove related SaSsdt acpi data to DSDT +// [Files] SaInit.c; INTELGFX.ASL; Sa.asl; SaSsdt.asl; +// SaSsdtTables.sdl; NBDxe.c; NB.mak; +// +// 41 3/07/13 2:20a Ireneyang +// [TAG] None +// [Severity] Bug Fix +// [Description] Intel Display Device disappear after S3 resume. +// [Files] NBDXE.c; +// +// 39 2/09/13 10:23a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 1.1.0 +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; +// +// 38 1/28/13 5:53a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 1.0. +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; +// NB.sd; NB.uni; NBDxeBoard.c +// +// 37 1/11/13 1:49a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Fixed Peg error log init bug. +// [Files] NBDXE.c; +// +// 36 1/10/13 6:00a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Fixed not program HDA codec for SaHDAVerbtable link bug. +// [Files] NBDXE.c; GetSetupData.c; NbSetupData.h +// +// 35 1/03/13 7:30a Jeffch +// [TAG] None +// [Severity] Improvement +// [Description] added SaHDAVerbtable link to OEM. +// [Files] NBDxe.c; NbSetupData.h; GetSetupData.c; +// +// 34 12/24/12 3:16a Jeffch +// [TAG] None +// [Category] Bug Fix +// [Description] fixed XTU not have create XMP GACI table. +// [Files] NBDxe.c; +// +// 33 12/24/12 3:06a Jeffch +// [TAG] None +// [Category] Bug Fix +// [Description] fixed XTU build fail issue. +// [Files] NBDxe.c; +// +// 32 12/24/12 2:55a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] added ULT SKU auto disable PEG. +// [Files] NBPei.c; NBDxe.c; NbPlatform.h; NB.sd; +// [TAG] None +// [Category] Bug Fix +// [Description] Remove tRPab and fixed XTU build fail issue. +// [Files] NBPei.c; NBDxe.c; NB.sd; +// +// 31 12/22/12 2:28a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Fxied anyway show Memory Timing default value. +// [Files] NBPei.c; +// +// 30 12/19/12 7:15a Jeffch +// [TAG] VddVoltage +// [Severity] Bug Fix +// [Description] Fixed show error Memory Voltage value. +// [Files] NBDxe.c; +// +// 29 12/18/12 5:14a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 0.81. +// [Files] NBDxe.c; NBPei.c +// +// 28 12/14/12 5:29a Jeffch +// // [TAG] None +// // [Severity] Important +// // [Description] Show memory voltage. +// // [Files] NB.sd; NB.uni; NBDxe.c. +// +// 27 12/03/12 5:57a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] optimize DetectNonComplaint function. +// [Description] NBPEI.c, NBPPI.h, NBDxe.c +// +// 2 11/29/12 3:41a Jeffch +// +// 26 11/29/12 2:32a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] added bootime check IGFX Available. +// [Files] NBDxe.c; NbPlatform.h; NB.sd; +// +// 23 11/20/12 2:57a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update SA RC 0.80. +// [Files] NBDxe.c; NBPei.c +// +// 22 11/14/12 5:38a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update XTU4.x function +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; NB.sd; +// NB.uni +// +// 21 11/07/12 6:22a Jeffch +// [TAG] EIP106013 +// [Severity] Important +// [Description] Sound and image abnormal with HDMI. +// [Files] NBDxe.c; +// +// 20 10/30/12 7:02a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update SA RC 0.72. +// [Files] NBDxe.c; NBPei.c +// +// 19 10/16/12 9:39a Jeffch +// [TAG] None +// [Severity] Important +// [Description] SA RC 0.71 for support ULT. +// [Files] NBDxe.c; +// +// 18 10/14/12 5:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c +// +// 17 10/14/12 12:22a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update by XTU4.0. +// [Files] NBPei.c, NBDxe.c, NBCspLib.h, NBGeneric.c +// [TAG] None +// [Severity] Important +// [Description] Follow Update by Mahobay. +// [Files] NBPei.c, NBDxe.c; +// +// 16 9/28/12 4:12a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] BDAT function support. +// [Files] NB.sd, NBDxe.c, NBPEI.c, SystemAgent.sdl, +// BdatAccessHandler.sdl +// +// 15 9/12/12 6:17a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Restore Performance Tuning the skip part +// [Files] NBDxe.c +// +// 14 8/31/12 2:32a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Update Board ID for Haswell platform. +// [Files] NBDxe.c +// +// 13 8/24/12 8:13a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Corrected GTT reference define. +// [Files] NBDxe.c, NBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Remove useless iME_SUPPORT. +// [Files] NBDxe.c +// +// 12 8/14/12 4:32a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.6.1. +// [Files] NB.sdl, NB.sd, NBCSP.CIF, NBDxe.c, NB.ASL, SaAudio.asl +// +// 11 7/27/12 8:38a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] IGfx Fource Disable Support. +// [Files] GetSetupData.c, NB.sdl, NB.sd, NB.uni, NbSetupData.h, +// NBDxe.c, NBPEI.c +// +// [TAG] None +// [Category] Improvement +// [Description] Adjusted NB policy debault. +// [Files] NB.sd, NBDxe.c +// +// [TAG] None +// [Category] Improvement +// [Description] Change to before Dxe SaInit to set maximum payload. +// [Files] NBDxe.c +// +// 10 7/03/12 6:44a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.6.0. +// [Files] NBPEI.DXS, NB.sd, NBDxe.c, NBPEI.c +// +// 9 7/03/12 6:39a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change the Save/Restore NB Registers position. +// [Files] NB.ASL, NBAcpi.c, NBDxe.c +// +// 8 6/14/12 4:56a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Set Max Payload Size for EDS. +// [Description] NBDxe.c +// +// 7 6/14/12 4:55a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fix some devices work abnormal in the PEG slot. +// [Description] NBDxe.c +// +// 6 4/26/12 2:52a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Adjust Intel System Agent module the Setup item and +// Policy. +// [Description] GetSetupData.c, NB.sdl, NB.sd, NB.uni, NBDxe.c, +// NBPEI.c, +// NBSetup.c, NBSetupReset.c, NbSetupData.h +// +// 5 4/05/12 5:45a Yurenlai +// [TAG] None +// [Category] New Feature +// [Severity] Normal +// [Description] Enabled GDXC feature. +// [Files] NBDxe.c, NBPEI.c +// +// 3 4/05/12 5:12a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Correct the Memory Info. +// [Files] NBDxe.c +// +// 2 4/05/12 2:34a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.5.5 . +// [Files] NBDxe.c, NBPEI.c, NBSMI.C, NBGeneric.cm NB.sd, NBSetup.c, +// GetSetupData.c, NbSetupData.h +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBDXE.C +// +// Description: This file contains code for North Bridge initialization +// in the DXE stage +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <Token.h> +#include <DXE.h> +#include <AmiDxeLib.h> +#include <AmiHobs.h> +#include <Setup.h> +#include <AmiCspLib.h> +#include <PciBus.h> +//#include "NbS3Save.h" +#include <Acpi20.h> +#include <AMIVfr.h> +#include <ppi\NBPPI.h> +// Consumed Protocols +#include <Protocol\PciRootBridgeIo.h> +#include <Protocol\NBPlatformData.h> + +#if ACPI_SUPPORT + #if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x00010014) + #include <Protocol\AcpiSystemDescriptionTable.h> + #else + #include <Protocol\AcpiSupport.h> + #endif +#endif + +#define _SA_COMMON_DEFINITIONS_H_ +#include <Protocol\SaPlatformPolicy\SaPlatformPolicy.h> +#include <Protocol\AmiUsbController.h> +#include <SaDataHob\SaDataHob.h> +#include <Hob.h> +#include "MemInfoHob.h" +#include <Protocol\MemInfo\MemInfo.h> + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +#include <PerfTune.h> +#include <Protocol\PerfTuneProtocol.h> +#endif +#endif + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 +#include <Protocol\Wdt\Wdt.h> +#endif + +#include <Protocol\PchS3Support\PchS3Support.h> + +#if NB_ERROR_LOG_SUPPORT +#include <Protocol\GenericElog.h> +#endif + +#include <Protocol\ConsoleControl.h> +#include <Protocol\SmBus.h> +#include <AmiLoadCsmPolicy.h> + +#include <SaGlobalNvsArea\SaGlobalNvsArea.h> +#include <Protocol\GlobalNvsArea\GlobalNvsArea.h> + +#ifndef EFI_SIGNATURE_16 +#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8)) +#endif + +#ifndef EFI_SIGNATURE_32 +#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16)) +#endif + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +#ifndef SMM_SUPPORT + #define SMM_SUPPORT 0 +#endif + +#define NB_TEMP_PCI_BUS 0x10 + +// Macro Definition(s) + +// Type Definition(s) +typedef struct { + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + VOID *Process; +} DEVICES_AFTER_PCIIO; + + +#define RC_EFI_ACPI_VARIABLE_GUID \ + { \ + 0xc020489e, 0x6db2, 0x4ef2, 0x9a, 0xa5, 0xca, 0x6, 0xfc, 0x11, 0xd3, 0x6a \ + } + +#define EFI_PCI_ENUMERATION_COMPLETE_GUID \ + { \ + 0x30cfe3e7, 0x3de1, 0x4586, { 0xbe, 0x20, 0xde, 0xab, 0xa1, 0xb3, 0xb7, 0x93 } \ + } + +typedef struct { + /// + /// Acpi Related variables + /// + EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase; + UINT32 AcpiReservedMemorySize; + EFI_PHYSICAL_ADDRESS S3ReservedLowMemoryBase; + EFI_PHYSICAL_ADDRESS AcpiBootScriptTable; + EFI_PHYSICAL_ADDRESS RuntimeScriptTableBase; + EFI_PHYSICAL_ADDRESS AcpiFacsTable; + UINT64 SystemMemoryLength; + ACPI_CPU_DATA AcpiCpuData; + /// + /// VGA OPROM to support Video Re-POST for Linux S3 + /// + EFI_PHYSICAL_ADDRESS VideoOpromAddress; + UINT32 VideoOpromSize; + + /// + /// S3 Debug extension + /// + EFI_PHYSICAL_ADDRESS S3DebugBufferAddress; + EFI_PHYSICAL_ADDRESS S3ResumeNvsEntryPoint; +} RC_ACPI_VARIABLE_SET; + + +// Function Prototype(s) + +EFI_STATUS NBDXE_BoardInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable, + IN NB_SETUP_DATA *SetupData +); + +VOID NbInitAfterDeviceInstall ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID InitNbRegsBeforeBoot ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID InitRcAcpiVariableSet( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS InstallNbMemoryInfo ( + IN EFI_SYSTEM_TABLE *SystemTable +); + +VOID CreateNbAcpiComponent ( VOID ); + +EFI_STATUS NbSmmInit ( + IN EFI_EVENT Event, + IN VOID *Context); + +#ifdef CSM_OPRROM_POLICY_GUID +VOID NbCheckOprom ( + IN EFI_EVENT Event, + IN VOID *Context +); +#endif + +VOID NbSetupNvramUpdatedCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID NbPciEnumerationCompleteProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +VOID NbExitPmAuthProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS InstallDxePlatformSaPolicy (VOID); + +EFI_STATUS +RmrrUpdateCallback ( + IN EFI_EVENT Event, + IN VOID *Context +); + +EFI_STATUS NBDXE_ShadowRam ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +); + +// (P20121012A) >> Update XTU 4.0 +EFI_STATUS NbReportXmpInfo( + IN EFI_EVENT Event, + IN VOID *Context +); + +typedef struct { + UINT32 tCK; + MrcFrequency DDRFreq; + UINT8 RefClkFlag; // 0 = invalid freq. 1 = valid only at 133 RefClk, 2 = valid only at 100 RefClk, 3 = valid at both. +} NbTRangeTable; + +typedef struct { + MrcFrequency DDRFreq; + MrcTiming TimingData; +} NbXmpProfileData; + +typedef struct { + NbXmpProfileData XmpProfileTiming[2]; +} XmpDimmData; + +//NbXmpProfileData XmpProfileTiming[2] = {0}; +//XmpDimmData XmpDimm[4] = {0}; +//XmpDimmData XmpChannel[2] = {0}; + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +VOID NbXTUSetGACITable( + IN EFI_EVENT Event, + IN VOID *Context +); + +DDDT_PRESENT_FLAG_HOB *gDddtPresentFlagHob = NULL; +#endif +#endif +// (P20121012A) << Update XTU 4.0 +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo = NULL; +AMI_S3_SAVE_PROTOCOL *gBootScript = NULL; +EFI_EVENT gEvent; +EFI_EVENT gEvtBootScript; +VOID *gNBInitNotifyReg = NULL; +VOID *gUpdateCsmProtocolNotifyReg = NULL; +NB_SETUP_DATA *gNbSetupData = NULL; +VOID *gCsmOpromReg = NULL; +VOID *gNbSetupNvramUpdatedReg = NULL; +VOID *gPciEnumerationCompleteProtocolReg = NULL; +VOID *gNbExitPmAuthProtocolReg = NULL; +VOID *gInterface = NULL; +MEM_INFO_PROTOCOL gMemInfoHobProtocol; +NB_PLATFORM_DATA NBPlatformData = {0}; +UINT32 gBClkFrequency = 0; +BOOLEAN gHideIGFXdevice; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +PERF_TUNE_ASL_PROTOCOL *gPerfTuneAslProtocol = NULL; +#endif +#endif +MrcProfile MemoryProfile = 0; +MrcTiming *NBMrcTimingData; + + +// GUID Definition(s) + +EFI_GUID gEfiPciRootBridgeIoProtocolGuid = \ + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_GUID; +EFI_GUID gEfiPciIoProtocolGuid = EFI_PCI_IO_PROTOCOL_GUID; +EFI_GUID gSetupNvramUpdatedGuid = AMITSE_NVRAM_UPDATE_GUID; +EFI_GUID gHobListGuid = HOB_LIST_GUID; +//EFI_GUID gMrcS3ResumeDataHobGuid = AMI_MRC_S3_RESUME_DATA_HOB_GUID; +EFI_GUID gDxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID; +EFI_GUID gMemInfoProtocolGuid = MEM_INFO_PROTOCOL_GUID; +EFI_GUID gMemRestoreDataGuid = EFI_MEMORY_RESTORE_DATA_GUID; +EFI_GUID gAmiNbPegGen3PresetSearchGuid = AMI_NB_PEG_GEN3_PRESET_SEARCH_GUID; +EFI_GUID gMrcInfoHobGuid = AMI_MRC_INFO_HOB_GUID; +EFI_GUID gSetupGuid = SETUP_GUID; +EFI_GUID gAmiLoadCsmGuid = AMI_LOAD_CSM_GUID; +EFI_GUID gConOutStartedCheckGuid = CONSOLE_OUT_DEVICES_STARTED_PROTOCOL_GUID; +EFI_GUID gExitPmAuthProtocolGuid = EXIT_PM_AUTH_PROTOCOL_GUID; +EFI_GUID gEfiSmbusProtocolGuid = EFI_SMBUS_HC_PROTOCOL_GUID; +EFI_GUID gAmiNbPegInfoGuid = AMI_NB_PEG_INFO_GUID; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +EFI_GUID gPerfTuneAslProtocolGuid = PERF_TUNE_ASL_PROTOCOL_GUID; +EFI_GUID gAmiPerfTuneDataHobGuid = AMI_PERF_TUNE_DATA_HOB_GUID; +EFI_GUID gAmiInternalFactoryTdcTdpHobGuid = AMI_INTERNAL_FACTORY_TDC_TDP_HOB_GUID; +#endif +#endif + +#ifdef CSM_OPRROM_POLICY_GUID +EFI_GUID gCsmOpromPolicyGuid = CSM_OPRROM_POLICY_GUID; +#endif + +#if NB_ERROR_LOG_SUPPORT +EFI_GUID gElogProtocolGuid = EFI_SM_ELOG_PROTOCOL_GUID; +#endif + +extern EFI_GUID gSaDataHobGuid; +extern EFI_GUID gEfiSmmAccessProtocolGuid; + +#if (CORE_VERSION >= 4600) +//---------------------------------------------------------------------------- +//THIS TABLE MUST BE FILLED WITH RESOURCE REGIONS DECODED BY THE NB FOR ITSELF +//!!! NOTE :Use Attributes field == -1 to mark an IO Space Resource. +// you must provide valid attributes for Memory Mapped IO regions. +//---------------------------------------------------------------------------- + +CSP_RES_ITEM gNbCspResTable[] = { +//---------------------------------------------------------------------------- +// UINT64 ResBase UINTN ResLength GCD_MEMORY_TYPE ResType UINT64 Attributes +//---------------------------------------------------------------------------- +//Add PCI Express region +{ PCIEX_BASE_ADDRESS, PCIEX_LENGTH,EfiGcdMemoryTypeMemoryMappedIo , \ + (EFI_MEMORY_UC|EFI_MEMORY_RUNTIME)}, +//Local APICs dedicated Space +{ LOCAL_APIC_BASE , 0x00001000 ,EfiGcdMemoryTypeMemoryMappedIo , \ + (EFI_MEMORY_UC|EFI_MEMORY_RUNTIME)}, +//Egress Port Base Address Region +{ NB_EP_BASE_ADDRESS, 4*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//MCH Memory Mapped Base Address Region +{ NB_MCH_BASE_ADDRESS, 16*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//Root Complex Base Address Region +{ NB_DMI_BASE_ADDRESS, 4*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//Edram Base Address Region +{ NB_DERAM_BASE_ADDRESS, 16*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//GDXC Base Address Region +{ NB_GDXC_BASE_ADDRESS, 4*1024 ,EfiGcdMemoryTypeMemoryMappedIo , \ + EFI_MEMORY_UC}, +//Here Goes Reserved IO Space +//IO Used for PCI Config access +{ NB_PCICFG_SPACE_INDEX_REG , 8 ,EfiGcdIoTypeIo , -1 }, + +}; + +UINTN gNbCspResCount = sizeof(gNbCspResTable) / sizeof(CSP_RES_ITEM); + +#endif + + +DEVICES_AFTER_PCIIO gDevicesTable[] = { + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, NULL }, + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, NULL }, + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, NULL }, + { 0xFF, 0xFF, 0xFF, NULL } +}; + +UINTN gEventCount = sizeof(gDevicesTable) / sizeof(DEVICES_AFTER_PCIIO); + +PCIE_ASPM_DEV_INFO mPcieAspmDevsOverride[] = { + /// + /// Tekoa w/o iAMT + /// + {0x8086, 0x108b, 0xff, 2, 2}, + /// + /// Tekoa A2 + /// + {0x8086, 0x108c, 0x00, 0, 0}, + /// + /// Tekoa others + /// + {0x8086, 0x108c, 0xff, 2, 2}, + /// + /// Vidalia + /// + {0x8086, 0x109a, 0xff, 2, 2}, + /// + /// 3945ABG + /// + {0x8086, 0x4222, 0xff, 2, 3}, + /// + /// 3945ABG + /// + {0x8086, 0x4227, 0xff, 2, 3}, + /// + /// 3945ABG + /// + {0x8086, 0x4228, 0xff, 2, 3}, + /// + /// End of table + /// + {SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0} +}; + +PCIE_LTR_DEV_INFO mPcieLtrDevsOverride[] = { + /// + /// Place holder for PCIe devices with correct LTR requirements + /// + /// + /// End of table + /// + {SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0} +}; +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//---------------------------------------------------------------------------- + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBDXE_Init +// +// Description: This function is the entry point for this DXE. This function +// initializes the chipset NB before PCI Bus enumeration. +// +// Input: ImageHandle - Image handle +// SystemTable - Pointer to the system table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBDXE_Init ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status = EFI_SUCCESS; + CPUINFO_HOB *CpuInfoHob = NULL; + EFI_GUID AmiCpuinfoHobGuid = AMI_CPUINFO_HOB_GUID; + UINT8 i = 0; + UINTN VariableSize; + EFI_EVENT Event; + VOID *HobData; + VOID *VariableData; + UINTN S3DataOffset; + UINT16 McDeviceId; + UINT16 LpcDeviceId; + VOID *Protocol = NULL; + VOID *NotifyReg = NULL; + UINT32 Attributes = 0; // [ EIP167027 ] + + + InitAmiLib(ImageHandle, SystemTable); + + PROGRESS_CODE (DXE_NB_INIT); + + Status = pBS->LocateProtocol( &gEfiPciRootBridgeIoProtocolGuid, \ + NULL, \ + &gPciRootBridgeIo ); + ASSERT_EFI_ERROR(Status); + + Status = pBS->LocateProtocol( AMI_S3_SAVE_PROTOCOL_GUID, \ + NULL, \ + &gBootScript ); + ASSERT_EFI_ERROR(Status); + + VariableData = NULL; + S3DataOffset = 0; + + HobData = (EFI_HOB_GENERIC_HEADER *) GetEfiConfigurationTable (pST, &gHobListGuid); + if (!HobData)ASSERT_EFI_ERROR (EFI_NOT_FOUND); + + Status = FindNextHobByGuid (&gSaDataHobGuid, &HobData); + if (Status == EFI_SUCCESS) { + + // Use the hob to save PegGen3PresetSearch Configuration Data + S3DataOffset = (UINTN) &(((SA_DATA_HOB *) 0)->PegData); + + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"PegGen3PresetSearchData", + // &gAmiNbPegGen3PresetSearchGuid, + // (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS), + // sizeof(SA_PEG_DATA), + // (UINT8 *) HobData + S3DataOffset + // ); + Status = pRS->SetVariable ( + L"PegGen3PresetSearchData", + &gAmiNbPegGen3PresetSearchGuid, + (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS), + sizeof(SA_PEG_DATA), + (UINT8 *) HobData + S3DataOffset + ); + ASSERT_EFI_ERROR(Status); + + } + + HobData = (EFI_HOB_GENERIC_HEADER *) GetEfiConfigurationTable (pST, &gHobListGuid); + if (!HobData)ASSERT_EFI_ERROR (EFI_NOT_FOUND); + + Status = FindNextHobByGuid (&gMemRestoreDataGuid, &HobData); + if (Status == EFI_SUCCESS) { + + // Use the hob to save Memory Configuration Data + S3DataOffset = (UINTN) &(((HOB_SAVE_MEMORY_DATA *) 0)->MrcData.SysSave); + + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"MrcS3Resume", + // &gMemRestoreDataGuid, + // (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS), + // sizeof(SysSave), + // (UINT8 *) HobData + S3DataOffset + // ); + Status = pRS->SetVariable ( + L"MrcS3Resume", + &gMemRestoreDataGuid, + (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS), + sizeof(SysSave), + (UINT8 *) HobData + S3DataOffset + ); + ASSERT_EFI_ERROR(Status); + + } + + // Set DRAM Initialization Bit. // [ EIP161790 ] + if ((READ_PCI8_SB(SB_REG_GEN_PMCON_2) & BIT07) == 0) + { + SET_PCI8_SB(SB_REG_GEN_PMCON_2, BIT07); // 0xA2 + } + + // Read the NB Setup Data + VariableSize = sizeof (NB_SETUP_DATA); + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &gNbSetupData ); + ASSERT_EFI_ERROR(Status); + + GetNbSetupData( pRS, gNbSetupData, FALSE ); + + // Read the NB Platform Data + VariableSize = sizeof (NB_PLATFORM_DATA); + //Status = pRS->GetVariable ( // [ EIP167027 ] + // L"NBPlatformData", + // &gSetupGuid, + // NULL, + // &VariableSize, + // &NBPlatformData + // ); + Status = pRS->GetVariable ( + L"NBPlatformData", + &gSetupGuid, + &Attributes, + &VariableSize, + &NBPlatformData + ); + if (EFI_ERROR(Status)) + Attributes = EFI_VARIABLE_BOOTSERVICE_ACCESS; + + // Check CPU is Support IGFX. + NBPlatformData.IGFXCapability = (READ_PCI32_NB (R_SA_MC_CAPID0_A_OFFSET) & BIT11) ? FALSE : TRUE; + + NBPlatformData.PegAvailable = (GetPchSeries() == PchLp) ? FALSE : TRUE; + // Check IGFX is Available. + NBPlatformData.IGFXAvailable = (READ_PCI32_IGD (R_SA_IGD_VID) != 0xFFFFFFFF) ? TRUE : FALSE; + +#if defined NB_IGFX_FORCE_DISABLE_SUPPORT && NB_IGFX_FORCE_DISABLE_SUPPORT == 1 + if(gNbSetupData->IGfxForceDisable == 1) + NBPlatformData.IGFXAvailable = 0; +#endif // NB_IGFX_FORCE_DISABLE_SUPPORT + + // Read MC device ID + McDeviceId = READ_PCI16_NB(R_SA_MC_DEVICE_ID); + + // Read PCH device ID + LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + + NBPlatformData.PresentCPU = 2; + + // Mobile - 0; Desktop - 2; UpServer - 3; FlavorWorkStation - 4; + if(IS_SA_DEVICE_ID_MOBILE(McDeviceId)) { + NBPlatformData.UserBoard = FlavorMobile; + } else if(IS_SA_DEVICE_ID_DESKTOP (McDeviceId) | IS_SA_DEVICE_ID_SERVER(McDeviceId)) { + if(IS_PCH_LPT_LPC_DEVICE_ID_WS (LpcDeviceId)) { + NBPlatformData.UserBoard = FlavorWorkStation; + } else if(IS_PCH_LPT_LPC_DEVICE_ID_SERVER (LpcDeviceId)) { + NBPlatformData.UserBoard = FlavorUpServer; + } else { + NBPlatformData.UserBoard = FlavorDesktop; + } + } else { + NBPlatformData.UserBoard = FlavorDesktop; + } + + Status = NBDXE_BoardInit(ImageHandle, SystemTable, gNbSetupData); + + // + // Detect if CSM is exist. If it's not, the shawdow ram can be set. + // + Status = pBS->LocateProtocol( &gAmiLoadCsmGuid, \ + NULL, \ + &gInterface ); + if(EFI_ERROR(Status)) + { + Status = NBDXE_ShadowRam(ImageHandle, SystemTable); + } + +#if PciHostBridge_SUPPORT + CreateNbAcpiComponent(); +#endif + + Status = RegisterProtocolCallback( &gEfiPciIoProtocolGuid, \ + NbInitAfterDeviceInstall, \ + NULL, &gEvent, &gNBInitNotifyReg ); + ASSERT_EFI_ERROR(Status); + + Status = RegisterProtocolCallback( &gConOutStartedCheckGuid, + NbPciEnumerationCompleteProtocolCallback, + NULL, &gEvent, &gPciEnumerationCompleteProtocolReg ); + ASSERT_EFI_ERROR(Status); + + Status = RegisterProtocolCallback( &gExitPmAuthProtocolGuid, \ + NbExitPmAuthProtocolCallback, \ + NULL, \ + &Event, \ + &gNbExitPmAuthProtocolReg ); + ASSERT_EFI_ERROR(Status); + + Status = CreateReadyToBootEvent( TPL_NOTIFY, InitNbRegsBeforeBoot, \ + NULL, &gEvent ); + ASSERT_EFI_ERROR(Status); + + Status = CreateReadyToBootEvent( + (TPL_CALLBACK - 1), + InitRcAcpiVariableSet, + NULL, + &Event); + ASSERT_EFI_ERROR(Status); + + Status = InstallDxePlatformSaPolicy (); + ASSERT_EFI_ERROR(Status); + + Status = InstallNbMemoryInfo ( SystemTable ); + ASSERT_EFI_ERROR(Status); + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + if(!EFI_ERROR(Status)) + { + EFI_EVENT Event; + VOID *Reg; + + Status = pBS->LocateProtocol (&gPerfTuneAslProtocolGuid, NULL, &gPerfTuneAslProtocol); + if(Status == EFI_SUCCESS) + { + NbXTUSetGACITable(NULL,NULL); + }else{ + //Create event for Notify XTU setting + Status = RegisterProtocolCallback( + &gPerfTuneAslProtocolGuid, + NbXTUSetGACITable, + NULL, &Event, &Reg); + ASSERT_EFI_ERROR(Status); + } + } +#endif +#endif + +#ifdef CSM_OPRROM_POLICY_GUID + Status = RegisterProtocolCallback( &gCsmOpromPolicyGuid, \ + NbCheckOprom, \ + NULL, \ + &Event, \ + &gCsmOpromReg ); + + ASSERT_EFI_ERROR(Status); +#endif + + Status = RegisterProtocolCallback( &gSetupNvramUpdatedGuid, + NbSetupNvramUpdatedCallback, + NULL, + &Event, + &gNbSetupNvramUpdatedReg ); + +#if (CORE_VERSION >= 4600) + Status = LibAllocCspResource( gNbCspResTable, \ + gNbCspResCount, \ + ImageHandle, \ + SystemTable ); +#endif + +#if SMM_SUPPORT + Status = pBS->LocateProtocol(&gEfiSmmAccessProtocolGuid, NULL, &Protocol); + if (EFI_ERROR(Status)) + { + Status = RegisterProtocolCallback( + &gEfiSmmAccessProtocolGuid, + NbSmmInit, + NULL, + &Event, + &NotifyReg); + ASSERT_EFI_ERROR(Status); + } + else + { + Status = NbSmmInit(NULL, NULL); + ASSERT_EFI_ERROR(Status); + } +#endif + +#ifndef OVERRIDE_FOR_SET_MAX_PAYLOAD + { + UINTN PegAddress; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + UINTN i; + + for ( i = 0; gDevicesTable[i].Bus != 0xff; i++) + { + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + + if (READ_PCI32 (PegBus, PegDev, PegFun, PCI_VID) == 0xFFFFFFFF) continue; + + // Haswell EDS 2.19.35 + // Default indicates 256B max supported payload for + // Transaction Layer Packets (TLP) for x16 PEG only. + // x8 and x4 PEG are limited to 128B support. + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, 0); + if (((READ_MMIO16 (PegAddress + R_SA_PEG_LSTS_OFFSET) & 0x01F0) >> 4) != 0x10) + RESET_MMIO8 (PegAddress + R_SA_PEG_DCAP_OFFSET, BIT0 + BIT1 + BIT2); + } + } +#endif // OVERRIDE_FOR_SET_MAX_PAYLOAD + + // Save SETUP variables. + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"NBPlatformData", + // &gSetupGuid, + // EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (NB_PLATFORM_DATA), + // &NBPlatformData + // ); + Status = pRS->SetVariable ( + L"NBPlatformData", + &gSetupGuid, + Attributes, + sizeof (NB_PLATFORM_DATA), + &NBPlatformData + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitNbRegsBeforeBoot +// +// Description: This function can initialize any NB registers before DXE +// stage exiting. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID InitNbRegsBeforeBoot ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ +//#if defined Remove_SaSsdt_Data_To_Dsdt && Remove_SaSsdt_Data_To_Dsdt + UINT32 Index; + EFI_ACPI_SUPPORT_PROTOCOL *As; + FACP_20 *Table = NULL; + EFI_ACPI_TABLE_VERSION Version; + UINTN Handle; + ACPI_HDR *DsdtPtr = NULL; + EFI_STATUS Status; + ASL_OBJ_INFO ObjInfo; + UINT16 ASLDeviceOP; + UINT8 ASLDeviceOPLength; + UINT8 *ptr; + UINT8 i; + UINT8 j; +#if defined Remove_SaSsdt_Data_To_Dsdt && Remove_SaSsdt_Data_To_Dsdt + UINT8 *GlobalSaptr, *SAptr; + SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL *SaGlobalNvsArea, *GlobalSaNvsArea; + EFI_GUID gSaGlobalNvsAreaProtocolGuid = SYSTEM_AGENT_GLOBAL_NVS_AREA_PROTOCOL_GUID; + EFI_GUID gEfiGlobalSaNvsAreaProtocolGuid = EFI_GLOBAL_SANVS_AREA_PROTOCOL_GUID; +#endif + UINT8 *ptr1; + UINT16 PXSXASLDeviceOP; + UINT8 PXSXASLDeviceOPLength; + UINT8 HPMEASLMethodOPLength; + UINT16 HPMEASLMethodOPLength16; + UINT16 ASLDeviceOPLength16; + UINT32 *Signature; + +#if NB_ERROR_LOG_SUPPORT == 1 +#if NB_ECC_ERROR_LOG_SUPPORT == 1 + + if(gNbSetupData->EccSupport) { + + if (((READ_MEM32_MCH(0x5004) & (BIT24 | BIT25)) != 0) || + ((READ_MEM32_MCH(0x5008) & (BIT24 | BIT25)) != 0)) + { + RW_MEM32_MCH(0x40B8, 0, (BIT14 | BIT16 | BIT17)); + RW_MEM32_MCH(0x44B8, 0, (BIT14 | BIT16 | BIT17)); + + // Disable Error and SCI Commands + RW_PCI16_NB(0xCA, 0, (BIT00 | BIT01)); + RW_PCI16_NB(0xCE, 0, (BIT00 | BIT01)); + + // Enable SMI Command + //SET_PCI8_NB(0xC8, BIT00); + RW_PCI16_NB(0xCC, (BIT00 | BIT01), 0); + } + + } + +#endif +#endif + +#if defined Remove_SaSsdt_Data_To_Dsdt && Remove_SaSsdt_Data_To_Dsdt + /// + /// Locate the SA SSDT NVS Protocol. + /// + Status = pBS->LocateProtocol ( + &gSaGlobalNvsAreaProtocolGuid, + NULL, + &SaGlobalNvsArea + ); + ASSERT_EFI_ERROR (Status); + + // + // Locate the SA Global NVS Protocol. + // + Status = pBS->LocateProtocol ( + &gEfiGlobalSaNvsAreaProtocolGuid, + NULL, + &GlobalSaNvsArea + ); + ASSERT_EFI_ERROR (Status); + + // Update SA SSDT GNVS data to Global DSDT SA GNVS + SAptr = (UINT8*)(SaGlobalNvsArea->Area); + GlobalSaptr = (UINT8*)(GlobalSaNvsArea->Area); + TRACE((TRACE_ALWAYS, "Global SA GNVS PTR=0x%08X, SA SSDT GNVS PTR=0x%08X\n", GlobalSaptr, SAptr)); + + for (Index = 0; Index < sizeof (SYSTEM_AGENT_GLOBAL_NVS_AREA); Index++) { + *(UINT8*)(GlobalSaptr + Index) = (UINT8)*(UINT8*)(SAptr + Index); + } + +#endif + + // It must be only one instance of such protocol + Status = pBS->LocateProtocol(&gEfiAcpiSupportGuid, NULL, &As); + if(EFI_ERROR(Status)) { + TRACE((-1, "ACPI Support Protocol is not ready for NB components\n")); + return; + } + TRACE((-1,"NB Locate Protocol(ACPISupport)- %r Success\n", Status)); + + // Find DSDT ACPI Table + for (Index = 0; Index < ACPI_RSDT_TABLE_NUM; Index++) { + Status = As->GetAcpiTable(As, Index, &Table, &Version, &Handle); + if (EFI_ERROR(Status)) break;//no more tables left + if ((Table->Header.Signature == FACP_SIG) && (DsdtPtr == NULL)) { + DsdtPtr = (ACPI_HDR*)Table->DSDT; + + TRACE((-1, "NBDxe: Found DSDT Table at 0x%08X\n", DsdtPtr)); + + + break; + } + } + + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), DsdtPtr->Length - sizeof(ACPI_HDR) - 1, + "P0P2", otDevice, &ObjInfo ); + + if (!EFI_ERROR(Status)) + { + ptr = (UINT8*)(ObjInfo.DataStart) - 7; + (UINT16)ASLDeviceOP = *(UINT32*)(ptr); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 2); + + TRACE((TRACE_ALWAYS, "SA POP2 Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr, (UINT16)ASLDeviceOP, (UINT8)ASLDeviceOPLength)); + if (ASLDeviceOP == 0x825B) // Is DeviceOP ? + { + for ( i = 0; i < ASLDeviceOPLength + 2; i++) { + *(UINT8*)(ptr + i) = 0; + } + } + } + + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), DsdtPtr->Length - sizeof(ACPI_HDR) - 1, + "P0PA", otDevice, &ObjInfo ); + + if (!EFI_ERROR(Status)) + { + ptr = (UINT8*)(ObjInfo.DataStart) - 7; + (UINT16)ASLDeviceOP = *(UINT32*)(ptr); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 2); + + TRACE((TRACE_ALWAYS, "SA POPA Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr, (UINT16)ASLDeviceOP, (UINT8)ASLDeviceOPLength)); + if (ASLDeviceOP == 0x825B) // Is ASL DeviceOP ? + { + for ( i = 0; i < ASLDeviceOPLength + 2; i++) { + *(UINT8*)(ptr + i) = 0; + } + } + } + + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), DsdtPtr->Length - sizeof(ACPI_HDR) - 1, + "P0PB", otDevice, &ObjInfo ); + + if (!EFI_ERROR(Status)) + { + ptr = (UINT8*)(ObjInfo.DataStart) - 7; + (UINT16)ASLDeviceOP = *(UINT32*)(ptr); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 2); + + TRACE((TRACE_ALWAYS, "SA POPB Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr, (UINT16)ASLDeviceOP, (UINT8)ASLDeviceOPLength)); + if (ASLDeviceOP == 0x825B) // Is ASL DeviceOP ? + { + for ( i = 0; i < ASLDeviceOPLength + 2; i++) { + *(UINT8*)(ptr + i) = 0; + } + } + } + + if (GetPchSeries() == PchLp) { + if(gNbSetupData->PrimaryDisplay == 4) { + + Status = GetAslObj( (UINT8*)(DsdtPtr + 1), DsdtPtr->Length - sizeof(ACPI_HDR) - 1, + "RP05", otDevice, &ObjInfo ); + if (!EFI_ERROR(Status)) + { + ptr = (UINT8*)(ObjInfo.DataStart) - 8; + (UINT16)ASLDeviceOP = *(UINT32*)(ptr); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 2); + ASLDeviceOPLength16 = (ASLDeviceOPLength & 0x0F); + (UINT8)ASLDeviceOPLength = *(UINT32*)(ptr + 3); + ASLDeviceOPLength16 = (ASLDeviceOPLength << 4) | ASLDeviceOPLength16; + + TRACE((TRACE_ALWAYS, "RP05 Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr, (UINT16)ASLDeviceOP, (UINT16)ASLDeviceOPLength16)); + if (ASLDeviceOP == 0x825B) // Is ASL DeviceOP ? + { + Status = GetAslObj( (UINT8*)(ptr + 1), ASLDeviceOPLength16 - sizeof(ACPI_HDR) - 1, + "_STA", otMethod, &ObjInfo ); + if (!EFI_ERROR(Status)) + { + ptr1 = (UINT8*)(ObjInfo.DataStart) - 5; + TRACE((TRACE_ALWAYS, "_STA Method PTR=0x%08X\n", ptr1)); + *(UINT8*)ptr1 = 'X'; + } + + //remove device PXSX + Status = GetAslObj( (UINT8*)(ptr + 1), ASLDeviceOPLength16 - sizeof(ACPI_HDR) - 1, + "PXSX", otDevice, &ObjInfo ); + if (!EFI_ERROR(Status)) + { + + ptr1 = (UINT8*)(ObjInfo.DataStart) - 7; + (UINT16)PXSXASLDeviceOP = *(UINT32*)(ptr1); + (UINT8)PXSXASLDeviceOPLength = *(UINT32*)(ptr1 + 2); + TRACE((TRACE_ALWAYS, "PXSX Device PTR=0x%08X, ASLDeviceOP=0x%X, ASLDeviceOPLength=0x%X\n", ptr1, (UINT16)PXSXASLDeviceOP, (UINT8)PXSXASLDeviceOPLength)); + + if (PXSXASLDeviceOP == 0x825B) // Is ASL DeviceOP ? + { + for ( i = 0; i < PXSXASLDeviceOPLength + 2; i++) { + *(UINT8*)(ptr1 + i) = 0; + } + } + } + + Status = GetAslObj( (UINT8*)(ptr + 1), ASLDeviceOPLength16 - sizeof(ACPI_HDR) - 1, + "HPME", otMethod, &ObjInfo ); + if (!EFI_ERROR(Status)) + { + ptr1 = (UINT8*)(ObjInfo.DataStart) - 8; + (UINT8)HPMEASLMethodOPLength = *(UINT32*)(ptr1 + 1); + HPMEASLMethodOPLength16 = (HPMEASLMethodOPLength & 0x0F); + (UINT8)HPMEASLMethodOPLength = *(UINT32*)(ptr1 + 2); + HPMEASLMethodOPLength16 = (HPMEASLMethodOPLength << 4) | HPMEASLMethodOPLength16; + TRACE((TRACE_ALWAYS, "HPME Method PTR=0x%08X,HPMEASLMethodOPLength16=0x%X\n", ptr1,(UINT16)HPMEASLMethodOPLength16)); + + for ( i = 0; i < HPMEASLMethodOPLength16 ; i++) { + Signature = (UINT32 *) (ptr1 + i); + //TRACE((TRACE_ALWAYS, "PXSX Notify PTR%d = 0x%08X\n", i,Signature)); + if(*Signature == EFI_SIGNATURE_32 ('P', 'X', 'S', 'X')){ + TRACE((TRACE_ALWAYS, "PXSX Notify PTR = 0x%08X\n", Signature)); + for ( j = 0; j < 7 ; j++) { + *(UINT8*)(ptr1 + i + j -1) = 0; + } + } + } + } + + + } + } + }// if(gNbSetupData->PrimaryDisplay == 4) { + }//if (GetPchSeries() == PchLp) + + //Kill the Event + pBS->CloseEvent(Event); + +} + +VOID InitRcAcpiVariableSet( + IN EFI_EVENT Event, + IN VOID *Context) +{ + EFI_STATUS Status; + EFI_GUID mEfiAcpiVariableGuid = EFI_ACPI_VARIABLE_GUID; + EFI_GUID mRcEfiAcpiVariableGuid = RC_EFI_ACPI_VARIABLE_GUID; + ACPI_VARIABLE_SET *pAcpiVariableSet = NULL; + RC_ACPI_VARIABLE_SET *pRcAcpiVariableSet = NULL; + UINTN VariableSize = sizeof(UINT32); + UINT32 Attributes; + + //Status = pRS->GetVariable ( // [ EIP167027 ] + // L"AcpiGlobalVariable", + // &mEfiAcpiVariableGuid, + // NULL, + // &VariableSize, + // &pAcpiVariableSet + // ); + Status = pRS->GetVariable ( + L"AcpiGlobalVariable", + &mEfiAcpiVariableGuid, + &Attributes, + &VariableSize, + &pAcpiVariableSet + ); + if (EFI_ERROR(Status)) + { + return; + } + + Status = pBS->AllocatePool( + EfiACPIMemoryNVS, + sizeof(RC_ACPI_VARIABLE_SET), + &pRcAcpiVariableSet + ); + ASSERT_EFI_ERROR(Status); + + pBS->SetMem(pRcAcpiVariableSet, sizeof(RC_ACPI_VARIABLE_SET), 0); + + pRcAcpiVariableSet->AcpiReservedMemoryBase = pAcpiVariableSet->AcpiReservedMemoryBase; + pRcAcpiVariableSet->AcpiReservedMemorySize = pAcpiVariableSet->AcpiReservedMemorySize; + pRcAcpiVariableSet->S3ReservedLowMemoryBase = pAcpiVariableSet->S3ReservedLowMemoryBase; + pRcAcpiVariableSet->AcpiBootScriptTable = pAcpiVariableSet->AcpiBootScriptTable; + pRcAcpiVariableSet->RuntimeScriptTableBase = pAcpiVariableSet->RuntimeScriptTableBase; + pRcAcpiVariableSet->AcpiFacsTable = pAcpiVariableSet->AcpiFacsTable[0]; + pRcAcpiVariableSet->SystemMemoryLength = pAcpiVariableSet->SystemMemoryLength; + pRcAcpiVariableSet->AcpiCpuData = pAcpiVariableSet->AcpiCpuData; + + //Status = pRS->SetVariable( // [ EIP167027 ] + // L"AcpiGlobalVariable", + // &mRcEfiAcpiVariableGuid, + // EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof(UINT64), + // &pRcAcpiVariableSet + // ); + Status = pRS->SetVariable( + L"AcpiGlobalVariable", + &mRcEfiAcpiVariableGuid, + Attributes, + sizeof(UINT64), + &pRcAcpiVariableSet + ); + ASSERT_EFI_ERROR(Status); + + //Kill the Event + Status = pBS->CloseEvent(Event); + ASSERT_EFI_ERROR(Status); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetExtCapStrucAddr +// +// Description: This routine is called to get the 16-bit offset of a +// structure which can be located using the PCI Extended +// Capabilities Pointer mechanism. +// +// Input: Bus - The PCI bus number of the PCI device. +// Dev - The PCI device number of the PCI device. +// Fun - The PCI function number of the PCI device. +// FindCapNo - The Extended Capability ID to be found. +// CapPtr16 - The offset address of desired structure +// +// Output: EFI_STATUS +// EFI_NOT_FOUND - The desired structure is not found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetExtCapStrucAddr ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 FindCapNo, + OUT UINT16 *CapPtr16 ) +{ + UINT32 Buffer32; + + *CapPtr16 = 0x100; + + Buffer32 = READ_PCI32(Bus, Dev, Fun, *CapPtr16); + while (Buffer32 != 0xffffffff) { + if ((UINT16)Buffer32 == FindCapNo) return EFI_SUCCESS; + *CapPtr16 = (UINT16)((Buffer32 >> 20) & 0xfffc); + if (*CapPtr16 == 0) break; + Buffer32 = READ_PCI32(Bus, Dev, Fun, *CapPtr16); + } + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetLegCapStrucAddr +// +// Description: This routine is called to get the 16-bit offset of a +// structure which can be located using the PCI Legacy +// Capabilities Pointer mechanism. +// +// Input: Bus - The PCI bus number of the PCI device. +// Dev - The PCI device number of the PCI device. +// Fun - The PCI function number of the PCI device. +// FindCapNo - The Legacy Capability ID to be found. +// CapPtr16 - The offset address of desired structure +// +// Output: EFI_STATUS +// EFI_NOT_FOUND - The desired structure is not found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS GetLegCapStrucAddr ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT8 FindCapNo, + OUT UINT16 *CapPtr16 ) +{ + UINT8 Buffer8; + + if (READ_PCI32(Bus, Dev, Fun, PCI_VID) != 0xffffffff) { + if (READ_PCI16(Bus, Dev, Fun, 6) & 0x10) { + *CapPtr16 = ((READ_PCI8(Bus, Dev, Fun, 14) & 0x7f) == 2) ? \ + 0x14:0x34; + *CapPtr16 = (UINT16)READ_PCI8(Bus, Dev, Fun, *CapPtr16); + if (*CapPtr16 == 0) return EFI_NOT_FOUND; + Buffer8 = READ_PCI8(Bus, Dev, Fun, *CapPtr16); + while (Buffer8 != 0) { + if (Buffer8 == FindCapNo) return EFI_SUCCESS; + Buffer8 = (UINT8)(*CapPtr16) + 1; + *CapPtr16 = (UINT16)(READ_PCI8(Bus, Dev, Fun, Buffer8)); + if (*CapPtr16 == 0) break; + Buffer8 = READ_PCI8(Bus, Dev, Fun, *CapPtr16); + } + } + } + return EFI_NOT_FOUND; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: FindPciGraphicAdapter +// +// Description: This routine tries to find any PCI graphic adapter on the +// PCI bus. +// +// Input: None +// +// Output: EFI_STATUS +// EFI_NOT_FOUND - No PCI Graphic Adapter to be found. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS FindPciGraphicAdapter (VOID) +{ + UINT8 StartBus; + UINT8 EndBus; + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 EndFun; + UINT8 Buffer8; + UINT32 Vid32; + + StartBus = READ_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, PCIBR_REG_SBUSN); + EndBus = READ_PCI8(PCIBR_BUS, PCIBR_DEV, PCIBR_FUN, PCIBR_REG_SUBUSN); + + for (Bus = StartBus; Bus <= EndBus; Bus++) { + for (Dev = 0; Dev <= PCI_MAX_DEVICE; Dev++) { + Vid32 = READ_PCI32(Bus, Dev, 0, PCI_VID); + if (Vid32 != 0xffffffff) { + Buffer8 = READ_PCI8(Bus, Dev, 0, PCI_HDR); + EndFun = (Buffer8 & 0x80) ? 8 : 1; + for (Fun = 0; Fun < EndFun; Fun++) { + Vid32 = READ_PCI32(Bus, Dev, Fun, PCI_VID); + if (Vid32 != 0xffffffff) { + Buffer8=READ_PCI8(Bus, Dev, Fun, PCI_BCC); + if (Buffer8 == 3) return EFI_SUCCESS; + } + } + } + } + } + + return EFI_NOT_FOUND; +} +#if NB_PCIE_ERROR_LOG_SUPPORT + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbEnablePciDevErr +// +// Description: Enable the error register of PCI-Express Device. +// +// Input: IN UINT64 Address - PCIE devices Address +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NbEnablePciDevErr( + IN UINT64 Address +) +{ + UINT32 DevBaseAddr = (UINT32)Address; + UINT8 CapPtr; + + // Clear Error Status + WRITE_MEM8_S3(gBootScript, DevBaseAddr + 0x07, 0xff);//(BIT0 | BIT1 | BIT2 | BIT3)); + + CapPtr = NbFindCapPtr(DevBaseAddr, 0x10); + if(CapPtr != 0) + { + // Clear Device Error Status + SET_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x0A, (BIT0 | BIT1 | BIT2)); + // Enable the error bits of Device Control + SET_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x08, (BIT0 | BIT1 | BIT2)); + } + + // Root? +// if ((READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0xF0) == 0x40) + // if device is bridge + if (READ_MEM16(DevBaseAddr + 0x0A) == 0x0604) + { + WRITE_MEM8_S3(gBootScript, DevBaseAddr + 0x1F, 0xff);//(BIT0 | BIT1 | BIT2 | BIT3)); + if(CapPtr != 0) + SET_MEM8_S3(gBootScript, DevBaseAddr + CapPtr + 0x1C, (BIT0 | BIT1 | BIT2)); + } + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbPciExpressDeviceInitialize +// +// Description: Init NB Pcie devices error register +// +// Input: IN UINT64 Address - PCIE devices Address +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NbPciExpressDeviceInitialize( + IN UINT64 Address +) +{ + UINT8 Dev; + UINT8 Func; + UINT8 CurrentBus; + UINT16 Buffer16; + UINT64 DevAddress; + UINT8 PciFun = (Address >> 12) & 0x07; + UINT8 CapPtr; + UINT8 Buffer8; + + CapPtr = NbFindCapPtr(Address, 0x10); + Buffer8 = READ_MEM8(Address + CapPtr + 0x08); + Buffer8 &= 0xF0; + Buffer8 |= (BIT03 | BIT02 | BIT01 | BIT00); + + WRITE_MEM8_S3( gBootScript, \ + Address + CapPtr + 0x08, \ + Buffer8 ); + + CurrentBus = READ_MEM8((UINT32)Address + PCIBR_REG_SBUSN); + + for (Dev = 0; Dev < 32; Dev++) + { + for (Func = 0; Func < 8; Func++) + { + DevAddress = (UINT64)NB_PCIE_CFG_ADDRESS(CurrentBus, Dev, Func, 0); + + if (READ_MEM16(DevAddress) == 0xFFFF) + continue; + + NbEnablePciDevErr(DevAddress); + + Buffer16 = READ_MEM16((UINT32)NB_PCIE_CFG_ADDRESS(CurrentBus, Dev, 0, 0) + PCI_SCC); + if (Buffer16 == 0x0604) + { + DevAddress = (UINT64)NB_PCIE_CFG_ADDRESS(CurrentBus, Dev, 0, 0); + NbPciExpressDeviceInitialize(DevAddress); + } + } + } +} +#endif +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbInitAfterDeviceInstall +// +// Description: This callback function is called when a PCI I/O Protocol is +// installed. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbInitAfterDeviceInstall ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN BufferSize = 20 * sizeof(EFI_HANDLE); + UINTN PciSeg; + UINTN PciBus; + UINTN PciDev; + UINTN PciFun; + UINT8 PciSeg8; + UINT8 PciBus8; + UINT8 PciDev8; + UINT8 PciFun8; + static UINT8 BrBus = 0; + UINT16 CapPtr16 = 0; + PCI_DEV_INFO *PciDevInfo = NULL; + + Status = pBS->LocateHandle( ByRegisterNotify, NULL, gNBInitNotifyReg, \ + &BufferSize, &Handle ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + // Locate PciIo protocol installed on Handle + + Status = pBS->HandleProtocol( Handle, &gEfiPciIoProtocolGuid, &PciIo ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + // Get PCI Device Bus/Device/Function Numbers + Status = PciIo->GetLocation(PciIo, &PciSeg, &PciBus, &PciDev, &PciFun); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + PciSeg8 = (UINT8)PciSeg; + PciBus8 = (UINT8)PciBus; + PciDev8 = (UINT8)PciDev; + PciFun8 = (UINT8)PciFun; + + if (NB_PCI_CFG_ADDRESS(PciBus, PciDev, PciFun, 0) == NB_PCIEBRN_BUS_DEV_FUN) + { + + } + + if (NB_PCI_CFG_ADDRESS(PciBus, PciDev, PciFun, 0) == NB_IGD_BUS_DEV_FUN) { + + } + + if ((BrBus != 0) && (PciBus == BrBus)) { + + } + + if (((UINT8)PciBus == PCIEBRN_BUS) && \ + ((UINT8)PciDev == PCIEBRN_DEV) && \ + (((UINT8)PciFun >= PCIEBRN_FUN) || ((UINT8)PciFun <= PCIEBRN_FUN2))) { + + } + + pBS->CloseEvent(Event); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RegisterDisplayDIMMPopulationErrMsg +// +// Description: Notification function on SimpleIn protocol Installation +// +// Input: SystemTable - Pointer to the System Table +// +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +EFIAPI +RegisterDisplayDIMMPopulationErrMsg ( + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallNbMemoryInfo +// +// Description: This function collects all memory information and creates a +// structure use for other DXE drivers. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InstallNbMemoryInfo ( + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle=NULL; + EFI_GUID MemInfoHobGuid = EFI_MEMORY_RESTORE_DATA_GUID; + HOB_SAVE_MEMORY_DATA *MemInfoHob; + UINT8 node; + UINT8 Ch; + UINT8 Dimm; + UINT8 Slot0; + UINT8 Slot1; + UINT8 Slot2; + UINT8 Slot3; + VOID *FirstHob; + BOOLEAN MemoryTimingValuesInitialized; + + // + // Get the HOB list and install MemInfo protocol + // + FirstHob = GetEfiConfigurationTable(SystemTable,&gHobListGuid); + if (!FirstHob)return EFI_INVALID_PARAMETER; + + MemInfoHob = (HOB_SAVE_MEMORY_DATA *) FirstHob; + + while (!EFI_ERROR (Status = FindNextHobByType (EFI_HOB_TYPE_GUID_EXTENSION, &MemInfoHob))) { + if (guidcmp (&MemInfoHob->EfiHobGuidType.Name, &MemInfoHobGuid) == 0) { + break; + } + } + + MemoryTimingValuesInitialized = FALSE; + + if (Status == EFI_SUCCESS) { + gMemInfoHobProtocol.MemInfoData.memSize = (UINT16)MemInfoHob->MrcData.SysOut.Outputs.MemoryMapData.TotalPhysicalMemorySize; + gMemInfoHobProtocol.MemInfoData.ddrFreq = (UINT16)MemInfoHob->MrcData.SysOut.Outputs.Frequency; + gMemInfoHobProtocol.MemInfoData.VddVoltage[0] = (UINT16)MemInfoHob->MrcData.SysOut.Outputs.VddVoltage[0]; + + gMemInfoHobProtocol.MemInfoData.EccSupport = MemInfoHob->MrcData.SysOut.Outputs.EccSupport; + gMemInfoHobProtocol.MemInfoData.RefClk = MemInfoHob->MrcData.SysOut.Outputs.RefClk; + gMemInfoHobProtocol.MemInfoData.Ratio = MemInfoHob->MrcData.SysOut.Outputs.Ratio; + NBPlatformData.DDR3Type = MemInfoHob->MrcData.SysOut.Outputs.DdrType; + gBClkFrequency = MemInfoHob->MrcData.SysIn.Inputs.BClkFrequency; + MemoryProfile = gMemInfoHobProtocol.MemInfoData.Profile = MemInfoHob->MrcData.SysIn.Inputs.MemoryProfile; + + // + // Getting the tRAS + // See MRC_TimingConfiguration.c for tRAS algorithm + // + for (node = 0; node < NODE_NUM; node++) { + for (Ch = 0; Ch < CH_NUM; Ch++) { + for (Dimm = 0; Dimm < DIMM_NUM; Dimm++) { + gMemInfoHobProtocol.MemInfoData.dimmSize[(node << 2) + (Ch << 1) + Dimm] = (UINT16) MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Dimm[Dimm].DimmCapacity; + TRACE ( + (TRACE_ALWAYS, + "Node %d Ch %d Dimm %d Size: %d\n", + node, + Ch, + Dimm, + gMemInfoHobProtocol.MemInfoData.dimmSize[(node << 2) + (Ch << 1) + Dimm]) + ); + gMemInfoHobProtocol.MemInfoData.DimmExist[(node << 2) + (Ch << 1) + Dimm] = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Dimm[Dimm].Status == DIMM_PRESENT) ? TRUE : FALSE; + gMemInfoHobProtocol.MemInfoData.RankInDimm[(node << 2) + (Ch << 1) + Dimm] = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Dimm[Dimm].RankInDIMM; + gMemInfoHobProtocol.MemInfoData.DimmsSpdData[(node << 2) + (Ch << 1) + Dimm] = NULL; + + // + // Updating tCL, tRCD and tRP to MemInfoHobProtocol from MemInfoHob + // + if (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Dimm[Dimm].Status == DIMM_PRESENT) { + gMemInfoHobProtocol.MemInfoData.Timing[0].tCL = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tCL; + gMemInfoHobProtocol.MemInfoData.Timing[0].tCWL = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tCWL; + gMemInfoHobProtocol.MemInfoData.Timing[0].tFAW = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tFAW; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRAS = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRAS; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRC = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRC; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRCD = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRCD; + gMemInfoHobProtocol.MemInfoData.Timing[0].tREFI = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tREFI; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRFC = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRFC; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRP = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRP; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRRD = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRRD; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRTP = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRTP; + gMemInfoHobProtocol.MemInfoData.Timing[0].tWR = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tWR; + gMemInfoHobProtocol.MemInfoData.Timing[0].tWTR = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tWTR; + gMemInfoHobProtocol.MemInfoData.Timing[0].tRPab = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing[MemoryProfile].tRPab; + + NBMrcTimingData = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing; + + NBPlatformData.XmpProfile1 = (NBMrcTimingData[2].tCK != 0) ? TRUE : FALSE; + NBPlatformData.XmpProfile2 = (NBMrcTimingData[3].tCK != 0) ? TRUE : FALSE; + + // + // mrc input spd send to smbios memory spd data. + // + if(gNbSetupData->IsRunMemoryDown) + gMemInfoHobProtocol.MemInfoData.DimmsSpdData[(node << 2) + (Ch << 1) + Dimm] = (UINT8*)&MemInfoHob->MrcData.SysIn.Inputs.Controller[0].Channel[Ch].Dimm[Dimm].Spd; + +// gMemInfoHobProtocol.MemInfoData.NMode = MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[Ch].Timing.NMode; + // + // Since we have only one setup varaiable to keep track of each memory timing, We inititialize the Memory Info HOB with the first occurence of data + // + MemoryTimingValuesInitialized = TRUE; + } + } + } + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 +#if defined APAC_NB_SETUP_SUPPORT || defined NB_SETUP_SUPPORT +#if APAC_NB_SETUP_SUPPORT == 1 || NB_SETUP_SUPPORT == 1 +{ + SETUP_DATA *SetupData = NULL; + EFI_GUID SetupGuid = SETUP_GUID; + UINTN VarSize = 0; + WDT_PROTOCOL *WdtProtocol = NULL; + EFI_GUID WdtProtocolGuid = WDT_PROTOCOL_GUID; + UINT32 Attributes; // [ EIP167027 ] + + + if (MemoryTimingValuesInitialized) { + //Status = GetEfiVariable(L"Setup", &SetupGuid, NULL, &VarSize, &SetupData); // [ EIP167027 ] + Status = GetEfiVariable(L"Setup", &SetupGuid, &Attributes, &VarSize, &SetupData); + if (!EFI_ERROR(Status)) { + // + + Status = pBS->LocateProtocol(&WdtProtocolGuid, NULL, &WdtProtocol); + if (!EFI_ERROR(Status)) { + if (WdtProtocol->CheckStatus() == V_PCH_OC_WDT_CTL_STATUS_FAILURE) + SetupData->SpdProfileSelected = 0; // Auto + } + + SetupData->tCL = NBMrcTimingData[MemoryProfile].tCL; + SetupData->tCWL = NBMrcTimingData[MemoryProfile].tCWL; + SetupData->tFAW = NBMrcTimingData[MemoryProfile].tFAW; + SetupData->tRAS = NBMrcTimingData[MemoryProfile].tRAS; + SetupData->tRC = NBMrcTimingData[MemoryProfile].tRC; + SetupData->tRCD = NBMrcTimingData[MemoryProfile].tRCD; + SetupData->tREFI = NBMrcTimingData[MemoryProfile].tREFI; + SetupData->tRFC = NBMrcTimingData[MemoryProfile].tRFC; + SetupData->tRP = NBMrcTimingData[MemoryProfile].tRP; + SetupData->tRRD = NBMrcTimingData[MemoryProfile].tRRD; + SetupData->tRTP = NBMrcTimingData[MemoryProfile].tRTP; + SetupData->tWR = NBMrcTimingData[MemoryProfile].tWR; + SetupData->tWTR = NBMrcTimingData[MemoryProfile].tWTR; + SetupData->tRPab = NBMrcTimingData[MemoryProfile].tRPab; + + SetupData->OcDdrFreqLimit = gMemInfoHobProtocol.MemInfoData.ddrFreq; + + //Status = pRS->SetVariable ( // [ EIP167027 ] + // L"Setup", + // &SetupGuid, + // EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof(SETUP_DATA), + // SetupData); + Status = pRS->SetVariable ( + L"Setup", + &SetupGuid, + Attributes, + sizeof(SETUP_DATA), + SetupData); + ASSERT_EFI_ERROR (Status); + } + } +} +#endif +#endif +#endif + + // Mobile - 0; Desktop - 2; UpServer - 3; FlavorWorkStation - 4; + if (NBPlatformData.UserBoard != FlavorMobile) { + + Slot0 = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[0].Dimm[0].Status == DIMM_PRESENT) ? TRUE : FALSE; + Slot1 = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[0].Dimm[1].Status == DIMM_PRESENT) ? TRUE : FALSE; + Slot2 = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[1].Dimm[0].Status == DIMM_PRESENT) ? TRUE : FALSE; + Slot3 = (MemInfoHob->MrcData.SysOut.Outputs.Controller[0].Channel[1].Dimm[1].Status == DIMM_PRESENT) ? TRUE : FALSE; + + // + // Channel 0 Channel 1 + // Slot0 Slot1 Slot0 Slot1 - Population AIO board + // 0 0 0 0 - Invalid - Invalid + // 0 0 0 1 - Valid - Invalid + // 0 0 1 0 - Invalid - Valid + // 0 0 1 1 - Valid - Valid + // 0 1 0 0 - Valid - Invalid + // 0 1 0 1 - Valid - Invalid + // 0 1 1 0 - Invalid - Invalid + // 0 1 1 1 - Valid - Invalid + // 1 0 0 0 - Invalid - Valid + // 1 0 0 1 - Invalid - Invalid + // 1 0 1 0 - Invalid - Valid + // 1 0 1 1 - Invalid - Valid + // 1 1 0 0 - Valid - Valid + // 1 1 0 1 - Valid - Invalid + // 1 1 1 0 - Invalid - Valid + // 1 1 1 1 - Valid - Valid + // + if ((Slot0 && (Slot1 == 0)) || (Slot2 && (Slot3 == 0))) { + RegisterDisplayDIMMPopulationErrMsg (SystemTable); + } + } + + Status = pBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gMemInfoProtocolGuid, + &gMemInfoHobProtocol, + NULL + ); + } + + return EFI_SUCCESS; +} + +#ifdef CSM_OPRROM_POLICY_GUID +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbCheckOprom +// +// Description: This callback function is called before/after processing all +// PCI optonal ROM. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbCheckOprom ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + UINTN BufferSize = sizeof(EFI_HANDLE); + EFI_HANDLE Handle; + CSM_PLATFORM_POLICY_DATA *Data; + UINTN Seg; + UINTN Bus; + UINTN Dev; + UINTN Fun; + + Status = pBS->LocateHandle( ByRegisterNotify, \ + NULL, \ + gCsmOpromReg, \ + &BufferSize, \ + &Handle ); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) return; + + // Locate CSM Platform Policy data + Status = pBS->HandleProtocol( Handle, &gCsmOpromPolicyGuid, &Data ); + + if ( EFI_ERROR(Status) ) return; + if (Data == NULL) return; + if (Data->ExecuteThisRom == FALSE) return; + if(Data->PciIo == NULL) return; + + Status = Data->PciIo->GetLocation( Data->PciIo, &Seg, &Bus, &Dev, &Fun ); + + // Close the event if needed. + // pBS->CloseEvent(Event); +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbSetupNvramUpdatedCallback +// +// Description: This callback function is called after Setup NVRAM variable +// being updated. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbSetupNvramUpdatedCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status; + NB_SETUP_DATA *NBSetupData = NULL; + UINTN VariableSize = sizeof(NB_SETUP_DATA); + + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &NBSetupData ); + ASSERT_EFI_ERROR(Status); + + GetNbSetupData( pRS, NBSetupData, FALSE ); + + // Free memory used for setup data + pBS->FreePool( NBSetupData ); + + pBS->CloseEvent(Event); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbPciEnumerationCompleteProtocolCallback +// +// Description: Install gEfiPciEnumerationCompleteProtocolGuid Protocol. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbPciEnumerationCompleteProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context) +{ + EFI_STATUS Status; + EFI_GUID gEfiPciEnumerationCompleteProtocolGuid = EFI_PCI_ENUMERATION_COMPLETE_GUID; + EFI_HANDLE Handle = NULL; + + Status = pBS->InstallProtocolInterface ( + &Handle, + &gEfiPciEnumerationCompleteProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL); + ASSERT_EFI_ERROR(Status); + + pBS->CloseEvent(Event); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbExitPmAuthProtocolCallback +// +// Description: This callback function is called after ExitPmAuthProtocol +// being installed. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbExitPmAuthProtocolCallback ( + IN EFI_EVENT Event, + IN VOID *Context) +{ + EFI_STATUS Status; + VOID *ProtocolPointer; + UINTN PegAddress; + UINT32 Data32And; + UINT32 Data32Or; + UINT32 Data32; + UINT16 Data16; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + UINTN i; +#if NB_PCIE_ERROR_LOG_SUPPORT + UINT8 CapPtr = 0; + EFI_SM_ELOG_PROTOCOL *GenericElogProtocol = NULL; +#endif + // + // Check whether this is real ExitPmAuth notification, or just a SignalEvent + // + Status = pBS->LocateProtocol (&gExitPmAuthProtocolGuid, NULL, &ProtocolPointer); + if (EFI_ERROR (Status)) return; + + + for ( i = 0; gDevicesTable[i].Bus != 0xff; i++) + { + + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + + Data32 = READ_PCI32 (PegBus, PegDev, PegFun, PCI_VID); + + if (Data32 == 0xFFFFFFFF) continue; + + // + // 6.3.7 Virtual Channel Configuration of PCI Express Port + // Set the VC0RCTL register D1:F0 Offset 114h [7:1] = 7Fh + // + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, 0); + Data32And = 0xFFFFFF00 + BIT0; + Data32Or = BIT1 + BIT2 + BIT3 + BIT4 + BIT5 +BIT6 + BIT7; + RW_MEM32_S3(gBootScript, (PegAddress + R_SA_PEG_VC0RCTL0_OFFSET), Data32Or, ~Data32And); + + // + // Store the Root port Bus assignemnt for S3 resume path + // + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, PCI_PBUS); + Data32 = READ_MEM32 (PegAddress); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint32, \ + PegAddress, \ + 1, \ + &Data32 ); + + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, PCI_BAR3); + Data16 = READ_MEM16 (PegAddress); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + gBootScript, \ + EfiBootScriptWidthUint16, \ + PegAddress, \ + 1, \ + &Data16 ); + +#if NB_PCIE_ERROR_LOG_SUPPORT + Status = pBS->LocateProtocol( &gElogProtocolGuid, + NULL, + &GenericElogProtocol ); + if (!EFI_ERROR (Status)) { + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, 0); + // if enable PCI SERR and PERR + if((READ_MEM16(PegAddress + PCI_CMD) & (BIT6 | BIT8)) == (BIT6 | BIT8)) + { + NbPciExpressDeviceInitialize(PegAddress); + + // Clear Error status + WRITE_MEM8_S3(gBootScript, PegAddress + 0x07, 0xff); + WRITE_MEM8_S3(gBootScript, PegAddress + 0x1F, 0xff); + + CapPtr = NbFindCapPtr(PegAddress, 0x10); + + if (CapPtr != 0) + { + // Clear Device Error status + SET_MEM8_S3(gBootScript, PegAddress + CapPtr + 0x0A, (BIT0 | BIT1 | BIT2)); + // Enable the error bits of Device Control + SET_MEM8_S3(gBootScript, PegAddress + CapPtr + 0x08, (BIT0 | BIT1 | BIT2)); + // Enable the error bits of Root Control + SET_MEM8_S3(gBootScript, PegAddress + CapPtr + 0x1C, (BIT2)); + } + } + } +#endif + + } + + pBS->CloseEvent(Event); + +} + +//---------------------------------------------------------------------------- +#if (ACPI_SUPPORT) + +UINT8 ACPI_OEM_ID[6] = CONVERT_TO_STRING(T_ACPI_OEM_ID); +UINT8 ACPI_OEM_TBL_ID[8] = CONVERT_TO_STRING(T_ACPI_OEM_TBL_ID); + +UINTN mMcfgTblHandle=0; +EFI_EVENT mAcpiEvent; +VOID *mAcpiReg; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CreateNbAcpiCallback +// +// Description: This function will create all ACPI components for NB when +// ACPI support protocol is available. +// +// Input: Event - Event of callback +// Context - Context of callback. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CreateNbAcpiCallback ( + IN EFI_EVENT Event, + IN VOID *Context ) +{ + EFI_STATUS Status = EFI_SUCCESS; + MCFG_20 *mcfg; + EFI_ACPI_TABLE_PROTOCOL *At; + UINT8 i; + UINTN TableKey; + + // It must be only one instance of such protocol + Status = pBS->LocateProtocol( &gEfiAcpiTableProtocolGuid, NULL, &At ); + TRACE((-1,"PciHostCSHooks: LocateProtocol(ACPITableProtocol) = %r\n", Status)); + if(EFI_ERROR(Status)) return; + +//-------------------------------- + //it must be only one instance of such protocol + mcfg=MallocZ(sizeof(MCFG_20)); + ASSERT(mcfg); + if(!mcfg) return; + + //Fill Table header; + mcfg->Header.Signature=MCFG_SIG; + mcfg->Header.Length=sizeof(MCFG_20); + mcfg->Header.Revision=1; + mcfg->Header.Checksum=0; + for (i=0;i<6;i++) { + mcfg->Header.OemId[i]=ACPI_OEM_ID[i]; + } + + for (i=0;i<8;i++) { + mcfg->Header.OemTblId[i]=ACPI_OEM_TBL_ID[i]; + } + mcfg->Header.OemRev=ACPI_OEM_REV; + mcfg->Header.CreatorId=0x5446534d; // "MSFT" 4D 53 46 54 + mcfg->Header.CreatorRev=0x97; + + //fill MCFG Fields + mcfg->BaseAddr=PCIEX_BASE_ADDRESS; // Base address of 256MB extended config space + mcfg->PciSeg=0; // Segment # of PCI Bus + mcfg->StartBus=0; // Start bus number of PCI segment + mcfg->EndBus=(UINT8)((PCIEX_LENGTH >> 20) - 1);// End bus number of PCI segment + + // Add table + Status = At->InstallAcpiTable( At, mcfg, sizeof(MCFG_20), &TableKey ); + TRACE((-1,"PciHostCSHooks: ACPITable->InstallAcpiTable(MCFG)=%r\n",Status)); + ASSERT_EFI_ERROR(Status); + + //free memory used for table image + pBS->FreePool(mcfg); + + //Kill the Event + pBS->CloseEvent(Event); + +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: CreateNbAcpiComponent +// +// Description: This function creates all ACPI components supported by NB. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID CreateNbAcpiComponent (VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + +#if (ACPI_SUPPORT) + Status = RegisterProtocolCallback( &gEfiAcpiTableProtocolGuid, \ + CreateNbAcpiCallback, \ + NULL, \ + &mAcpiEvent, \ + &mAcpiReg ); + // If System Description Table Protocol has been installed we can use + // it rigth on the way + pBS->SignalEvent( mAcpiEvent ); +#endif + +} + +// Protocols that are installed +DXE_PLATFORM_SA_POLICY_PROTOCOL mDxePlatformSaPolicy = { 0 }; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallDxePlatformSaPolicy +// +// Description: This Function installs the SNB SA POLICY PROTOCOL +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS InstallDxePlatformSaPolicy (VOID) +{ + VOID *Registration; + EFI_EVENT Event; + EFI_STATUS Status; + EFI_STATUS FindNbPegHobStatus = EFI_NOT_FOUND; + EFI_HANDLE Handle; + VOID *HobData; + SB_SETUP_DATA *SBSetupData = NULL; + UINTN VariableSize = sizeof(SB_SETUP_DATA); + UINT8 Index; + UINT16 McDeviceId; + UINT32 RegEax, RegEbx, RegEcx, RegEdx, CpuSteppingId, CpuFamilyId; + + Status = pBS->AllocatePool( EfiBootServicesData, \ + VariableSize, \ + &SBSetupData ); + ASSERT_EFI_ERROR(Status); + + // Read the Setup Data + GetSbSetupData( pRS, SBSetupData, FALSE ); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_VTD_CONFIGURATION), + &(mDxePlatformSaPolicy.Vtd) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_MEMORY_CONFIGURATION), + &(mDxePlatformSaPolicy.MemoryConfig) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + (sizeof (UINT8) * DIMM_SLOT_NUM), + (VOID **) &mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool (EfiBootServicesData, + sizeof (SA_PCIE_CONFIGURATION), + &(mDxePlatformSaPolicy.PcieConfig) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool (EfiBootServicesData, + sizeof (SA_IGD_CONFIGURATION), + &(mDxePlatformSaPolicy.IgdConfig) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool (EfiBootServicesData, + sizeof (SA_MISC_CONFIGURATION), + &(mDxePlatformSaPolicy.MiscConfig) + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_DEFAULT_SVID_SID), + (VOID **) &mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid + ); + ASSERT_EFI_ERROR (Status); + + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_HDA_VERB_TABLE), + (VOID **) &mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTable + ); + ASSERT_EFI_ERROR (Status); +#if ( defined(SwitchableGraphics_SUPPORT) && (SwitchableGraphics_SUPPORT == 1) ) + Status = pBS->AllocatePool ( + EfiBootServicesData, + sizeof (SA_DEFAULT_SVID_SID), + (VOID **) &mDxePlatformSaPolicy.VbiosConfig + ); + ASSERT_EFI_ERROR (Status); +#endif + + // RMRR Base and Limit Address for USB + Status = pBS->AllocatePool ( + EfiBootServicesData, + (sizeof (EFI_PHYSICAL_ADDRESS) * 2), + (VOID **) &mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress + ); + ASSERT_EFI_ERROR (Status); + + // Read MC device ID + McDeviceId = READ_PCI16_NB(R_SA_MC_DEVICE_ID); + + CPULib_CpuID(1, &RegEax, &RegEbx, &RegEcx, &RegEdx); + + CpuSteppingId = RegEax & 0x0000000F; + CpuFamilyId = RegEax & 0x0FFF0FF0; + + NBPlatformData.VTdAvailable = (READ_PCI32_NB(0xe4) & BIT23) ? 0 : 1; + + + mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[0] = DIMM1_SMBUS_ADDRESS; + mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[1] = DIMM2_SMBUS_ADDRESS; + mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[2] = DIMM3_SMBUS_ADDRESS; + mDxePlatformSaPolicy.MemoryConfig->SpdAddressTable[3] = DIMM4_SMBUS_ADDRESS; + + mDxePlatformSaPolicy.MemoryConfig->ChannelASlotMap = 0x03; + mDxePlatformSaPolicy.MemoryConfig->ChannelBSlotMap = 0x03; + +#if A1_MEMORY_SOCKETS == 2 + mDxePlatformSaPolicy.MemoryConfig->ChannelASlotMap = 0x01; + mDxePlatformSaPolicy.MemoryConfig->ChannelBSlotMap = 0x01; +#endif + +#if A1_MEMORY_SOCKETS == 6 + mDxePlatformSaPolicy.MemoryConfig->ChannelASlotMap = 0x07; + mDxePlatformSaPolicy.MemoryConfig->ChannelBSlotMap = 0x07; +#endif + + + mDxePlatformSaPolicy.Vtd->BaseAddress[0] = NB_VTD_BASE_ADDRESS; + mDxePlatformSaPolicy.Vtd->BaseAddress[1] = NB_VTD_BASE_ADDRESS + 0x1000; + + // System Agent Configuration Misc + + mDxePlatformSaPolicy.MiscConfig->ChapDeviceEnable = gNbSetupData->SaDevice7;; + mDxePlatformSaPolicy.MiscConfig->Device4Enable = (gNbSetupData->SaDevice4); + mDxePlatformSaPolicy.MiscConfig->CridEnable = gNbSetupData->EnableNbCrid; + mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid->SubSystemVendorId = gNbSetupData->NBDxeSubSystemVendorId; + mDxePlatformSaPolicy.MiscConfig->DefaultSvidSid->SubSystemId = gNbSetupData->NBDxeSubSystemId; + + mDxePlatformSaPolicy.MiscConfig->AudioEnable = gNbSetupData->SaAudioEnable; + mDxePlatformSaPolicy.MiscConfig->FviReport = 1; // Default Enable FVI SMBIOS Report + mDxePlatformSaPolicy.MiscConfig->FviSmbiosType = 0xDD; // Default SMBIOS Type 221 + + // Port B +// gNbSaHdaVerbTableData[4] &= 0xFFFFFF00; +// if (gNbSetupData->SaHdmiCodecPortB == 0) +// gNbSaHdaVerbTableData[4] |= 0x58; +// else +// gNbSaHdaVerbTableData[4] |= 0x18; + + // Port C +// gNbSaHdaVerbTableData[8] &= 0xFFFFFF00; +// if (gNbSetupData->SaHdmiCodecPortC == 0) +// gNbSaHdaVerbTableData[8] |= 0x58; +// else +// gNbSaHdaVerbTableData[8] |= 0x18; + + // Port D +// gNbSaHdaVerbTableData[12] &= 0xFFFFFF00; +// if (gNbSetupData->SaHdmiCodecPortD == 0) +// gNbSaHdaVerbTableData[12] |= 0x58; +// else +// gNbSaHdaVerbTableData[12] |= 0x18; + +// if ((CpuFamilyId == 0x000306C0) && (CpuSteppingId < 2)) { // B0 + + if (gNbSetupData->NbSaHdaVerbTable != NULL) { + mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTableNum = gNbSetupData->NbSaHdaVerbTableNum; + (pBS->CopyMem) (&mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTable[0], &gNbSetupData->NbSaHdaVerbTable[0], sizeof (SA_HDA_VERB_TABLE_HEADER)); + mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTable[0].VerbTableData = gNbSetupData->NbSaHdaVerbTable[0].VerbTableData; + } + +// } else { +// mDxePlatformSaPolicy.MiscConfig->SaHdaVerbTable[0].VerbTableData = &(gNbSaHdaVerbTableData[1]); +// } + + // + // BIOS must update USB RMRR base address + // + mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress[0] = 0x3E2E0000; + mDxePlatformSaPolicy.Vtd->RmrrUsbBaseAddress[1] = 0x3E2FFFFF; + + // Protocol revision number + mDxePlatformSaPolicy.Revision = DXE_SA_PLATFORM_POLICY_PROTOCOL_REVISION_8; + + // Init DxePlaformSaPolicy if Setup Variable is exist + mDxePlatformSaPolicy.Vtd->VtdEnable = gNbSetupData->EnableVtd; + + // PCIE related Setup data + mDxePlatformSaPolicy.PcieConfig->DmiAspm = gNbSetupData->NBDmiAspm; + mDxePlatformSaPolicy.PcieConfig->DmiExtSync = gNbSetupData->NBDmiExtSync; + mDxePlatformSaPolicy.PcieConfig->DmiDeEmphasis = gNbSetupData->DmiDeEmphasis; + mDxePlatformSaPolicy.PcieConfig->DmiIot = gNbSetupData->DmiIot; + mDxePlatformSaPolicy.PcieConfig->C7Allowed = gNbSetupData->C7Allowed; + for (Index = 0; Index < SA_PEG_MAX_FUN; Index++) { + mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrEnable = gNbSetupData->LtrEnable[Index]; + mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrMaxSnoopLatency = gNbSetupData->LtrMaxSnoopLatency[Index];//V_SA_LTR_MAX_SNOOP_LATENCY_VALUE; + mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].LtrMaxNoSnoopLatency = gNbSetupData->LtrMaxNoSnoopLatency[Index];//V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE; + mDxePlatformSaPolicy.PcieConfig->PegPwrOpt[Index].ObffEnable = gNbSetupData->ObffEnable[Index]; + } + + + + if (gNbSetupData->DetectNonComplaint == 1) { + HobData = (EFI_HOB_GENERIC_HEADER *) GetEfiConfigurationTable (pST, &gHobListGuid); + if (HobData) { + FindNbPegHobStatus = FindNextHobByGuid (&gAmiNbPegInfoGuid, &HobData); + } + } + + for (Index = 0; Index < 3; Index++) { + mDxePlatformSaPolicy.PcieConfig->PegAspm[Index] = gNbSetupData->PegAspm[Index]; + mDxePlatformSaPolicy.PcieConfig->PegAspmL0s[Index] = gNbSetupData->PegAspmL0s[Index]; + if (EFI_ERROR (FindNbPegHobStatus)) { + mDxePlatformSaPolicy.PcieConfig->PegDeEmphasis[Index] = gNbSetupData->PegDeEmphasis[Index]; + } else { + mDxePlatformSaPolicy.PcieConfig->PegDeEmphasis[Index] = ((NB_PEG_INFO_HOB *)HobData)->PegDeOverride[Index]; + } + } + + mDxePlatformSaPolicy.PcieConfig->PcieAspmDevsOverride = mPcieAspmDevsOverride; + mDxePlatformSaPolicy.PcieConfig->PcieLtrDevsOverride = mPcieLtrDevsOverride; + + // IGD related Setup data + mDxePlatformSaPolicy.IgdConfig->RenderStandby = gNbSetupData->RenderStandby; + + mDxePlatformSaPolicy.IgdConfig->DeepRenderStandby = gNbSetupData->DeepRenderStandby; + + if (GetPchSeries() == PchLp) { + mDxePlatformSaPolicy.IgdConfig->CdClk = 1; + } else { + mDxePlatformSaPolicy.IgdConfig->CdClk = 2; // (EIP106013) + } + + + mDxePlatformSaPolicy.IgdConfig->PlatformConfig = gNbSetupData->AcpiLowPowerS0Idle; + + +#ifdef BDAT_SUPPORT + mDxePlatformSaPolicy.MemoryConfig->RmtBdatEnable = gNbSetupData->BdatAcpiTableSupport; +#endif + +#if ( defined(SwitchableGraphics_SUPPORT) && (SwitchableGraphics_SUPPORT == 1) ) + /// + /// Initialize the Switchable Graphics DXE Policies + /// + + /// + /// 1 = Load secondary display device VBIOS + /// 0 = Do not load + /// + mDxePlatformSaPolicy.VbiosConfig->LoadVbios = 0; // Shark Bay SA Reference Code Production Version 1.9.0 [ EIP194524 ] + /// + /// 1 = Execute the secondary display device VBIOS (only if LoadVbios == 1) + /// 0 = Do no execute + /// + mDxePlatformSaPolicy.VbiosConfig->ExecuteVbios = 0; + /// + /// 1 = secondary display device VBIOS Source is PCI Card + /// 0 = secondary display device VBIOS Source is FW Volume + /// + mDxePlatformSaPolicy.VbiosConfig->VbiosSource = 1; +#endif + + Handle = NULL; + // Install protocol to to allow access to this Policy. + Status = pBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gDxePlatformSaPolicyGuid, + &mDxePlatformSaPolicy, + NULL + ); + ASSERT_EFI_ERROR (Status); + + + // Register Callback function for updating USB Rmrr address + Status = pBS->CreateEvent ( + EFI_EVENT_NOTIFY_SIGNAL, + TPL_CALLBACK, + RmrrUpdateCallback, + NULL, + &Event + ); + + if (!EFI_ERROR (Status)) { + Status = pBS->RegisterProtocolNotify ( + &gEfiUsbProtocolGuid, + Event, + &Registration + ); + } + + // Free memory used for setup data + pBS->FreePool( SBSetupData ); + + return Status; + +} + +//<AMI_PHDR_START> +//------------------------------------------------------------------------------------------------- +// +// Procedure: RmrrUpdateCallback +// +// Description: This Function is update IGD & USB Rmrr BaseAddress +// +// Input: Event A pointer to the Event that triggered the callback. +// Context A pointer to private data registered with the callback function. +// +// Output: None +//-------------------------------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +RmrrUpdateCallback ( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status; + EFI_USB_PROTOCOL *UsbProtocol; + DXE_PLATFORM_SA_POLICY_PROTOCOL *DxePlatformSaPolicy; + UINT16 IgdMode; + UINT16 GttMode; + UINT32 IgdMemSize; + UINT32 GttMemSize; + EFI_PHYSICAL_ADDRESS RmrrIGDBaseAddress; + EFI_PHYSICAL_ADDRESS RmrrIGDSize; + DXE_SERVICES *DxeSvcTbl = NULL; + EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdMemorySpaceDescriptor; + UINT64 Attributes; + + pBS->CloseEvent(Event); + // + // Update USB Reserved Memory Base Address and Limit Address for VT-d. + // + Status = pBS->LocateProtocol (&gDxePlatformSaPolicyGuid, NULL, &DxePlatformSaPolicy); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = pBS->LocateProtocol (&gEfiUsbProtocolGuid, NULL, &UsbProtocol); + if (!EFI_ERROR (Status)) + { + + Status = UsbProtocol->UsbGetRuntimeRegion ( + &DxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[0], + &DxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[1] + ); + + TRACE ((TRACE_ALWAYS, "RmrrUsbBaseAddress = 0x%X\n", DxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[0])); + TRACE ((TRACE_ALWAYS, "RmrrUsbLimitAddress = 0x%X\n", DxePlatformSaPolicy->Vtd->RmrrUsbBaseAddress[1])); + } + + if (READ_PCI32_IGD (R_SA_IGD_VID) == 0xFFFFFFFF) return Status; + + Status = LibGetDxeSvcTbl(&DxeSvcTbl); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) return Status; + + // + // Calculate IGD memsize + // + IgdMode = (READ_PCI16_NB (R_SA_GGC) & B_SA_GGC_GMS_MASK) >> 3; + if (IgdMode <= V_SA_GGC_GMS_512MB) + { + IgdMemSize = IgdMode * 32 * (1024) * (1024); + } else if (IgdMode >= 0x11) // V_SA_GGC_GMS_1024MB + { + IgdMemSize = 0x20 * 32 * (1024) * (1024); + } else { + IgdMemSize = 0; + } + + // + // Calculate GTT mem size + // + GttMode = (READ_PCI16_NB (R_SA_GGC) & B_SA_GGC_GGMS_MASK) >> N_SA_GGC_GGMS_OFFSET; + if (GttMode <= V_SA_GGC_GGMS_2MB) + { + GttMemSize = GttMode * (1024) * (1024); + } else { + GttMemSize = 0; + } + + if ((IgdMemSize + GttMemSize) == 0) return Status; + + RmrrIGDBaseAddress = (EFI_PHYSICAL_ADDRESS)((READ_PCI32_NB (R_SA_TOLUD) & ~(0x01)) - IgdMemSize - GttMemSize); + RmrrIGDSize = (EFI_PHYSICAL_ADDRESS)(IgdMemSize + GttMemSize); + + Status = DxeSvcTbl->GetMemorySpaceDescriptor (RmrrIGDBaseAddress, &GcdMemorySpaceDescriptor); + ASSERT_EFI_ERROR (Status); + + Attributes = GcdMemorySpaceDescriptor.Attributes | EFI_MEMORY_RUNTIME; + + Status=DxeSvcTbl->SetMemorySpaceAttributes(RmrrIGDBaseAddress,RmrrIGDSize,Attributes); + ASSERT_EFI_ERROR(Status); + + TRACE ((TRACE_ALWAYS, "RmrrIGDBaseAddress = 0x%X\n", RmrrIGDBaseAddress)); + TRACE ((TRACE_ALWAYS, "RmrrIGDSize = 0x%X\n", RmrrIGDSize)); + + return Status; +} + +//<AMI_PHDR_START> +//------------------------------------------------------------------------------------------------- +// +// Procedure: NBDXE_ShadowRam +// +// Description: For setting PAM0\PAM5\PAM6 to "Disable", "Read Only", "Write Only", or "R/W Enable" +// under not using legacy. +// +// Input: EFI_HANDLE +// EFI_SYSTEM_TABL +// +// Output: None +//-------------------------------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBDXE_ShadowRam ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINT8 Default_PAM0 = (UINT8)(NB_F0000_PAM0 << 4); + UINT8 Default_PAM5 = (UINT8)((NB_E0000_PAM5 << 4) | NB_E0000_PAM5); + UINT8 Default_PAM6 = (UINT8)((NB_E8000_PAM6 << 4) | NB_E8000_PAM6); + + // + // Set "Disable", "Read Only", "Write Only", or "R/W Enable" as Token value into PAM0\PAM5\PAM6. + // + WRITE_PCI8_NB (0x80, Default_PAM0); + WRITE_PCI8_NB (0x85, Default_PAM5); + WRITE_PCI8_NB (0x86, Default_PAM6); + + return Status; +} + + +#if defined (PERF_TUNE_SUPPORT) && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +#define OC_MAILBOX_MSR 0x00000150 +#define MAILBOX_WAIT_TIMEOUT 1000 ///< 1 millisecond +#define OC_LIB_CMD_GET_OC_CAPABILITIES 0x01 +#define OC_LIB_CMD_GET_VOLTAGE_FREQUENCY 0x10 +#define OC_LIB_COMPLETION_CODE_SUCCESS 0x00 +#define BIT0_MASK 0x1 +#define MAX_RATIO_MASK 0x000000FF +#define VOLTAGE_TARGET_MASK 0x000FFF00 +#define VOLTAGE_TARGET_OFFSET 8 +#define VOLTAGE_MODE_MASK 0x00100000 +#define VOLTAGE_MODE_OFFSET 20 +#define VOLTAGE_OFFSET_MASK 0xFFE00000 +#define VOLTAGE_OFFSET_OFFSET 21 + +#define MILLIVOLTS_PER_VOLT 1000 +#define MAX_TARGET_MV 4095 +#define MAX_OFFSET_MV 500 + +#define CONVERT_TO_FIXED_POINT_VOLTS 0 +#define CONVERT_TO_BINARY_MILLIVOLT 1 + +#define OC_CAPS_MAX_RATIO_MASK 0x000000FF +#define OC_CAPS_RATIO_SUPPORT_MASK 0x00000100 +#define OC_CAPS_RATIO_SUPPORT_OFFSET 8 +#define OC_CAPS_OVERRIDE_SUPPORT_MASK 0x00000200 +#define OC_CAPS_OVERRIDE_SUPPORT_OFFSET 9 +#define OC_CAPS_OFFSET_SUPPORT_MASK 0x00000400 +#define OC_CAPS_OFFSET_SUPPORT_OFFSET 10 +// +// Bit 10 is the S11.0.10V sign bit +// +#define FIXED_POINT_SIGN_BIT_MASK 0x0400 +#define INT16_SIGN_BIT_MASK 0x8000 + +// +// tCL Macro definitions +// +#ifndef tCL_MINIMUM +#define tCL_MINIMUM 4 +#endif +#ifndef tCL_MAXIMUM +#define tCL_MAXIMUM 18 +#endif +#define tCL_NumOfValues tCL_MAXIMUM - tCL_MINIMUM + 1 +// +// tRP Macro definitions +// +#ifndef tRP_MINIMUM +#define tRP_MINIMUM 4 +#endif +#ifndef tRP_MAXIMUM +#define tRP_MAXIMUM 15 +#endif +#define tRP_NumOfValues tRP_MAXIMUM - tRP_MINIMUM + 1 +// +// tRCD Macro definitions +// +#ifndef tRCD_MINIMUM +#define tRCD_MINIMUM 4 +#endif +#ifndef tRCD_MAXIMUM +#define tRCD_MAXIMUM 20 +#endif +#define tRCD_NumOfValues tRCD_MAXIMUM - tRCD_MINIMUM + 1 +// +// tRAS Macro definitions +// +#ifndef tRAS_MINIMUM +#define tRAS_MINIMUM 10 +#endif +#ifndef tRAS_MAXIMUM +#define tRAS_MAXIMUM 40 +#endif +#define tRAS_NumOfValues tRAS_MAXIMUM - tRAS_MINIMUM + 1 +// +// tWR Macro definitions +// +#ifndef tWR_MINIMUM +#define tWR_MINIMUM 5 +#endif +#ifndef tWR_MAXIMUM +#define tWR_MAXIMUM 30 +#endif +#define tWR_NumOfValues tWR_MAXIMUM - tWR_MINIMUM + 1 +// +// tRFC Macro definitions +// +#ifndef tRFC_MINIMUM +#define tRFC_MINIMUM 1 +#endif +#ifndef tRFC_MAXIMUM +#define tRFC_MAXIMUM 511 +#endif +#define tRFC_NumOfValues tRFC_MAXIMUM - tRFC_MINIMUM + 1 +// +// tRRD Macro definitions +// +#ifndef tRRD_MINIMUM +#define tRRD_MINIMUM 4 +#endif +#ifndef tRRD_MAXIMUM +#define tRRD_MAXIMUM 7 +#endif +#define tRRD_NumOfValues tRRD_MAXIMUM - tRRD_MINIMUM + 1 +// +// tWTR Macro definitions +// +#ifndef tWTR_MINIMUM +#define tWTR_MINIMUM 4 +#endif +#ifndef tWTR_MAXIMUM +#define tWTR_MAXIMUM 10 +#endif +#define tWTR_NumOfValues tWTR_MAXIMUM - tWTR_MINIMUM + 1 +// +// tRTP Macro definitions +// +#ifndef tRTP_MINIMUM +#define tRTP_MINIMUM 4 +#endif +#ifndef tRTP_MAXIMUM +#define tRTP_MAXIMUM 15 +#endif + +#define tRTP_NumOfValues tRTP_MAXIMUM - tRTP_MINIMUM + 1 +// +// tFAW Macro definitions +// +#ifndef tFAW_MINIMUM +#define tFAW_MINIMUM 10 +#endif +#ifndef tFAW_MAXIMUM +#define tFAW_MAXIMUM 54 +#endif +#define tFAW_NumOfValues tFAW_MAXIMUM - tFAW_MINIMUM + 1 +// +// tRC Macro definitions +// +#ifndef tRC_MINIMUM +#define tRC_MINIMUM 1 +#endif +#ifndef tRC_MAXIMUM +#define tRC_MAXIMUM 4095 +#endif +#define tRC_NumOfValues tRC_MAXIMUM - tRC_MINIMUM + 1 +// +// +// tCWL Macro definitions +// +#ifndef tCWL_MINIMUM +#define tCWL_MINIMUM 5 +#endif +#ifndef tCWL_MAXIMUM +#define tCWL_MAXIMUM 12 +#endif +#define tCWL_NumOfValues tCWL_MAXIMUM - tCWL_MINIMUM + 1 +// +// tREFI Macro definitions +// +#ifndef tREFI_MINIMUM +#define tREFI_MINIMUM 1 +#endif +#ifndef tREFI_MAXIMUM +#define tREFI_MAXIMUM 10000 +#endif +#define tREFI_NumOfValues tREFI_MAXIMUM - tREFI_MINIMUM + 1 +// +// tRPab Macro definitions +// +#ifndef tRPab_MINIMUM +#define tRPab_MINIMUM 4 +#endif +#ifndef tRPab_MAXIMUM +#define tRPab_MAXIMUM 18 +#endif +#define tRPab_NumOfValues tRPab_MAXIMUM - tRPab_MINIMUM + 1 +// +// +// iGfxRatio Macro definitions +// +#ifndef iGfxRatio_MINIMUM +#define iGfxRatio_MINIMUM 17 +#endif +#ifndef iGfxRatio_MAXIMUM +#define iGfxRatio_MAXIMUM 60 +#endif +#define iGfxRatio_NumOfValues iGfxRatio_MAXIMUM - iGfxRatio_MINIMUM + 1 + +// +// iGfxVolt Macro definitions +// +#ifndef iGfxVoltOverride_MINIMUM +#define iGfxVoltOverride_MINIMUM 0 +#endif +#ifndef iGfxVoltOverride_MAXIMUM +#define iGfxVoltOverride_MAXIMUM 2000 +#endif +#define iGfxVoltOverride_NumOfValues iGfxVoltOverride_MAXIMUM - iGfxVoltOverride_MINIMUM + 1 + +#ifndef iGfxVoltOffset_MINIMUM +#define iGfxVoltOffset_MINIMUM 0 +#endif +#ifndef iGfxVoltOffset_MAXIMUM +#define iGfxVoltOffset_MAXIMUM 1000 +#endif +#define iGfxVoltOffset_NumOfValues iGfxVoltOffset_MAXIMUM - iGfxVoltOffset_MINIMUM + 1 + +#ifndef SaVoltOffset_MINIMUM +#define SaVoltOffset_MINIMUM 0 +#endif +#ifndef SaVoltOffset_MAXIMUM +#define SaVoltOffset_MAXIMUM 1000 +#endif +#define SaVoltOffset_NumOfValues SaVoltOffset_MAXIMUM - SaVoltOffset_MINIMUM + 1 + +#ifndef IoaVoltOffset_MINIMUM +#define IoaVoltOffset_MINIMUM 0 +#endif +#ifndef IoaVoltOffset_MAXIMUM +#define IoaVoltOffset_MAXIMUM 1000 +#endif +#define IoaVoltOffset_NumOfValues IoaVoltOffset_MAXIMUM - IoaVoltOffset_MINIMUM + 1 + +#ifndef IodVoltOffset_MINIMUM +#define IodVoltOffset_MINIMUM 0 +#endif +#ifndef IodVoltOffset_MAXIMUM +#define IodVoltOffset_MAXIMUM 1000 +#endif +#define IodVoltOffset_NumOfValues IodVoltOffset_MAXIMUM - IodVoltOffset_MINIMUM + 1 + +//========================================== GACI TABLE ====================================================== + +// GACI_DATA DevNameGaciData {ControlID,NumberOfValues,\ +// Precision,Flags,DefaultDataValue,MinDataValue,MaxDataValue,MinDisplayValue,MaxDisplayValue} +static GACI_DATA tCLGaciData = {BIOS_TCL_IMPLEMENTATION,\ + tCL_NumOfValues, 0, 0, 0, tCL_MINIMUM, tCL_MAXIMUM, tCL_MINIMUM, tCL_MAXIMUM}; + +static GACI_DATA tCWLGaciData = {BIOS_TCWL_IMPLEMENTATION,\ + tCWL_NumOfValues, 0, 0, 0, tCWL_MINIMUM, tCWL_MAXIMUM, tCWL_MINIMUM, tCWL_MAXIMUM}; + +static GACI_DATA tREFIGaciData = {BIOS_TREFI_IMPLEMENTATION,\ + tREFI_NumOfValues, 0, 0, 0, tREFI_MINIMUM, tREFI_MAXIMUM, tREFI_MINIMUM, tREFI_MAXIMUM}; + +static GACI_DATA tRASGaciData = {BIOS_TRAS_IMPLEMENTATION,\ + tRAS_NumOfValues, 0, 0, 0, tRAS_MINIMUM, tRAS_MAXIMUM, tRAS_MINIMUM, tRAS_MAXIMUM}; + +static GACI_DATA tRPGaciData = {BIOS_TRP_IMPLEMENTATION,\ + tRP_NumOfValues, 0, 0, 0, tRP_MINIMUM, tRP_MAXIMUM, tRP_MINIMUM, tRP_MAXIMUM}; + +static GACI_DATA tRCDGaciData = {BIOS_TRCD_IMPLEMENTATION,\ + tRCD_NumOfValues, 0, 0, 0, tRCD_MINIMUM, tRCD_MAXIMUM, tRCD_MINIMUM, tRCD_MAXIMUM}; + +static GACI_DATA tWRGaciData = {BIOS_TWR_IMPLEMENTATION,\ + tWR_NumOfValues, 0, 0, 0, tWR_MINIMUM, tWR_MAXIMUM, tWR_MINIMUM, tWR_MAXIMUM}; + +static GACI_DATA tRFCGaciData = {BIOS_TRFC_IMPLEMENTATION,\ + tRFC_NumOfValues, 0, 0, 0, tRFC_MINIMUM, tRFC_MAXIMUM, tRFC_MINIMUM, tRFC_MAXIMUM}; + +static GACI_DATA tRRDGaciData = {BIOS_TRRD_IMPLEMENTATION,\ + tRRD_NumOfValues, 0, 0, 0, tRRD_MINIMUM, tRRD_MAXIMUM, tRRD_MINIMUM, tRRD_MAXIMUM}; + +static GACI_DATA tWTRGaciData = {BIOS_TWTR_IMPLEMENTATION,\ + tWTR_NumOfValues, 0, 0, 0, tWTR_MINIMUM, tWTR_MAXIMUM, tWTR_MINIMUM, tWTR_MAXIMUM}; + +static GACI_DATA tRTPGaciData = {BIOS_TRTP_IMPLEMENTATION,\ + tRTP_NumOfValues, 0, 0, 0, tRTP_MINIMUM, tRTP_MAXIMUM, tRTP_MINIMUM, tRTP_MAXIMUM}; + +static GACI_DATA tFAWGaciData = {BIOS_TFAW_IMPLEMENTATION,\ + tFAW_NumOfValues, 0, 0, 0, tFAW_MINIMUM, tFAW_MAXIMUM, tFAW_MINIMUM, tFAW_MAXIMUM}; + +static GACI_DATA tRCGaciData = {BIOS_TRC_IMPLEMENTATION,\ + tRC_NumOfValues, 0, 0, 0, tRC_MINIMUM, tRC_MAXIMUM, tRC_MINIMUM, tRC_MAXIMUM}; + +//static GACI_DATA tRPabGaciData = {BIOS_TRPAB_IMPLEMENTATION,\ +// tRPab_NumOfValues, 0, 0, 0, tRPab_MINIMUM, tRPab_MAXIMUM, tRPab_MINIMUM, tRPab_MAXIMUM}; + +static GACI_DATA DramMultiGaciData = {BIOS_DDR_MULT_IMPLEMENTATION,\ + 0xFFFF, 2, 0, 0, 0, 0, 0, 0}; + +static GACI_DATA XmpProfSelData = {BIOS_XMP_PROFILE_SELECTION_IMPLEMENTATION,\ + 3, 0, 0, 0, 0, 3, 0, 3}; + +static GACI_DATA CpuRuntimeTurbo = {BIOS_RUNTIME_TURBO_OVERRIDE_IMPLEMENTATION,\ + 0, 0, 0, 0, 0, 0, 0, 0}; + +static GACI_DATA iGfxTurboRatioData = {BIOS_GRAPHICS_TURBO_RATIO_LIMIT_IMPLEMENTATION,\ + iGfxRatio_NumOfValues, 1, 0, 0, 0, iGfxRatio_MAXIMUM, 0, iGfxRatio_MAXIMUM}; + +//static GACI_DATA iGfxVoltageData = {BIOS_GRAPHICS_CORE_VOLTAGE_IMPLEMENTATION,\ +// iGfxVolt_NumOfValues, 0, 0, 0, iGfxVolt_MINIMUM, iGfxVolt_MAXIMUM, iGfxVolt_MINIMUM, iGfxVolt_MAXIMUM}; + +static GACI_DATA iGfxVoltageOverride = {BIOS_GRAPHICS_CORE_VOLTAGE_OVERRIDE_IMPLEMENTATION,\ + iGfxVoltOverride_NumOfValues, 3, 0, 0, iGfxVoltOverride_MINIMUM, iGfxVoltOverride_MAXIMUM, iGfxVoltOverride_MINIMUM, iGfxVoltOverride_MAXIMUM}; + +static GACI_DATA iGfxVoltageMode = {BIOS_GRAPHICS_CORE_VOLTAGE_MODE_IMPLEMENTATION,\ + 1, 0, 0, 0, 0, 1, 0, 1}; + +static GACI_DATA iGfxVoltageOffset = {BIOS_GRAPHICS_CORE_VOLTAGE_OFFSET_IMPLEMENTATION,\ + 2001, 0, 0, 1000, 0, 2000, 0xFFFFFc18, 1000}; + +static GACI_DATA SaVoltageOffset = {BIOS_SYSTEM_AGENT_VOLTAGE_OFFSET_IMPLEMENTATION,\ + 2001, 0, 0, 1000, 0, 2000, 0xFFFFFc18, 1000}; + +static GACI_DATA IoaVoltageOffset = {BIOS_IO_ANALOG_VOLTAGE_OFFSET_IMPLEMENTATION,\ + 2001, 0, 0, 1000, 0, 2000, 0xFFFFFc18, 1000}; + +static GACI_DATA IodVoltageOffset = {BIOS_IO_DIGITAL_VOLTAGE_OFFSET_IMPLEMENTATION,\ + 2001, 0, 0, 1000, 0, 2000, 0xFFFFFc18, 1000}; + +static GACI_DATA MemClockMultiplier = {BIOS_MEM_CLOCK_MULTIPLIER_IMPLEMENTATION,\ + 0xFFFF, 2, 0, 0, 0, 0, 0, 0}; + +//========================================== XMP Profile TABLE ====================================================== +//Profile 1 data +// GXDV DevNameGxdvData = {ControlID, Reserved, Precision, DisplayValue}; +static GXDV_DATA Pro1tCLGxdvData = {BIOS_TCL_IMPLEMENTATION, 0, 0, 8}; +static GXDV_DATA Pro1tRASGxdvData = {BIOS_TRAS_IMPLEMENTATION, 0, 0, 23}; +static GXDV_DATA Pro1tRPGxdvData = {BIOS_TRP_IMPLEMENTATION, 0, 0, 8}; +static GXDV_DATA Pro1tRCDGxdvData = {BIOS_TRCD_IMPLEMENTATION, 0, 0, 8}; +static GXDV_DATA Pro1tWRGxdvData = {BIOS_TWR_IMPLEMENTATION, 0, 0, 9}; +static GXDV_DATA Pro1tRFCGxdvData = {BIOS_TRFC_IMPLEMENTATION, 0, 0, 73}; +static GXDV_DATA Pro1tRRDGxdvData = {BIOS_TRRD_IMPLEMENTATION, 0, 0, 4}; +static GXDV_DATA Pro1tWTRGxdvData = {BIOS_TWTR_IMPLEMENTATION, 0, 0, 5}; +static GXDV_DATA Pro1tRTPGxdvData = {BIOS_TRTP_IMPLEMENTATION, 0, 0, 5}; +static GXDV_DATA Pro1tFAWGxdvData = {BIOS_TFAW_IMPLEMENTATION, 0, 0, 20}; +static GXDV_DATA Pro1tRCGxdvData = {BIOS_TRC_IMPLEMENTATION, 0, 0, 20}; +static GXDV_DATA Pro1tREFIGxdvData = {BIOS_TREFI_IMPLEMENTATION, 0, 0, 1000}; +static GXDV_DATA Pro1tCWLGxdvData = {BIOS_TCWL_IMPLEMENTATION, 0, 0, 8}; +//static GXDV_DATA Pro1tRPabGxdvData = {BIOS_TRPAB_IMPLEMENTATION, 0, 0, 4}; +static GXDV_DATA Pro1DdrMulGxdvData = {BIOS_DDR_MULT_IMPLEMENTATION, 0, 0, 16}; +static GXDV_DATA Pro1DdrClkMulGxdvData = {BIOS_MEM_CLOCK_MULTIPLIER_IMPLEMENTATION, 0,2, 133}; + +//profile 2 data +// GXDV DevNameGxdvData = {ControlID, Reserved, Precision, DisplayValue}; +static GXDV_DATA Pro2tCLGxdvData = {BIOS_TCL_IMPLEMENTATION, 0, 0, 7}; +static GXDV_DATA Pro2tRASGxdvData = {BIOS_TRAS_IMPLEMENTATION, 0, 0, 22}; +static GXDV_DATA Pro2tRPGxdvData = {BIOS_TRP_IMPLEMENTATION, 0, 0, 7}; +static GXDV_DATA Pro2tRCDGxdvData = {BIOS_TRCD_IMPLEMENTATION, 0, 0, 7}; +static GXDV_DATA Pro2tWRGxdvData = {BIOS_TWR_IMPLEMENTATION, 0, 0, 8}; +static GXDV_DATA Pro2tRFCGxdvData = {BIOS_TRFC_IMPLEMENTATION, 0, 0, 72}; +static GXDV_DATA Pro2tRRDGxdvData = {BIOS_TRRD_IMPLEMENTATION, 0, 0, 4}; +static GXDV_DATA Pro2tWTRGxdvData = {BIOS_TWTR_IMPLEMENTATION, 0, 0, 5}; +static GXDV_DATA Pro2tRTPGxdvData = {BIOS_TRTP_IMPLEMENTATION, 0, 0, 5}; +static GXDV_DATA Pro2tFAWGxdvData = {BIOS_TFAW_IMPLEMENTATION, 0, 0, 20}; +static GXDV_DATA Pro2tRCGxdvData = {BIOS_TRC_IMPLEMENTATION, 0, 0, 20}; +static GXDV_DATA Pro2tREFIGxdvData = {BIOS_TREFI_IMPLEMENTATION, 0, 0, 1000}; +static GXDV_DATA Pro2tCWLGxdvData = {BIOS_TCWL_IMPLEMENTATION, 0, 0, 8}; +//static GXDV_DATA Pro2tRPabGxdvData = {BIOS_TRPAB_IMPLEMENTATION, 0, 0, 4}; +static GXDV_DATA Pro2DdrMulGxdvData = {BIOS_DDR_MULT_IMPLEMENTATION, 0, 0, 18}; +static GXDV_DATA Pro2DdrClkMulGxdvData = {BIOS_MEM_CLOCK_MULTIPLIER_IMPLEMENTATION, 0,2, 133}; +//=================================================================================================================== + + +static +MrcFrequency +NbGetDimmFrequency ( + IN UINT32 tCK + ); + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetIGDSettings +// +// Description: Update XTU GACI Table function . +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 GetIGDSettings(void) +{ + UINT32 GTTMMADR;// = 0xF7800000; + UINT32 Data32; + + // + // Program GT PM Settings if GTTMMADR allocation is Successful + // + GTTMMADR = (UINT32)NB_TEMP_MMIO_BASE; + WRITE_PCI32_IGD (R_SA_IGD_GTTMMADR, (GTTMMADR | BIT02)); // 0x10 + + // + // Enable Bus Master, I/O and Memory access on 0:2:0 + // + SET_PCI8_IGD (R_SA_IGD_CMD , (BIT02 | BIT01)); // 0x04 + + TRACE((-1,"GT Overclocking Support is enabled in BIOS Setup\n")); + + // + // Wait for Mailbox ready + // + while (READ_MEM32 ((UINTN)(GTTMMADR + 0x138124)) & BIT31) { + Data32 = READ_MEM32 ((UINTN)(GTTMMADR + 0x138124)); + }; + + // + // Mailbox Command - MAILBOX_GTDRIVER_CMD_READ_OVERCLOCK_PARAMS to READ OC SUPPORT + // + Data32 = 0x8000000C; + WRITE_MEM32 ((UINTN)(GTTMMADR + 0x138124), Data32); + + // + // Wait for Mailbox ready + // + while (READ_MEM32 ((UINTN)(GTTMMADR + 0x138124)) & BIT31) { + Data32 = READ_MEM32 ((UINTN)(GTTMMADR + 0x138124)); + }; + + + if (READ_MEM32 ((UINTN)(GTTMMADR + 0x138128)) & BIT31) + { + Data32 = READ_MEM32 ((UINTN)(GTTMMADR + 0x138128)); + return Data32; + } + return Data32; +} + +EFI_STATUS GetDddtPresentFlagHob() +{ + EFI_STATUS Status; + EFI_GUID gDddtPreFlagHobGuid = AMI_DDDT_PRESENT_FLAG_HOB_GUID; + VOID *gDddtPreFlagHobList = NULL; + UINTN FlagCount = (sizeof(BIOS_SETTING_DATA) - sizeof(BIOS_SETTING_HDR))/sizeof(UINT16); + +// Get Hob List + gDddtPreFlagHobList = GetEfiConfigurationTable(pST, &gHobListGuid); + if (!gDddtPreFlagHobList) return EFI_NOT_FOUND; + +// Find CPUID Checksum Data Hob. + gDddtPresentFlagHob = (DDDT_PRESENT_FLAG_HOB*)gDddtPreFlagHobList; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &gDddtPresentFlagHob))) + { + if (guidcmp(&gDddtPresentFlagHob->EfiHobGuidType.Name, &gDddtPreFlagHobGuid) == 0) + break; + } + + if (EFI_ERROR(Status)) return EFI_NOT_FOUND; + return Status; +} + +typedef union _OC_MAILBOX_INTERFACE { + UINT32 InterfaceData; + struct { + UINT8 CommandCompletion:8; + UINT8 Param1:8; + UINT8 Param2:8; + UINT8 Reserved:7; + UINT8 RunBusy:1; + } Fields; +} OC_MAILBOX_INTERFACE; + +typedef struct _OC_MAILBOX_FULL { + UINT32 Data; + OC_MAILBOX_INTERFACE Interface; +} OC_MAILBOX_FULL; + +typedef struct { + UINT8 MaxOcRatio; + UINT8 VoltageTargetMode; + UINT16 VoltageTarget; + INT16 VoltageOffset; +} VOLTAGE_FREQUENCY_SETTINGS; + +typedef struct { + VOLTAGE_FREQUENCY_SETTINGS VfSettings; + UINT8 DomainId; +} VOLTAGE_FREQUENCY_ITEM; + +typedef struct { + UINT8 MaxOcRatioLimit; + BOOLEAN RatioOcSupported; + BOOLEAN VoltageOverridesSupported; + BOOLEAN VoltageOffsetSupported; + UINT8 DomainId; +} OC_CAPABILITIES_ITEM; + +typedef union _OC_MAILBOX_COMMAND { + UINT32 InterfaceData; + struct { + UINT8 CommandCompletion:8; + UINT8 Param1:8; + UINT8 Param2:8; + UINT8 Reserved:7; + UINT8 RunBusy:1; + } Fields; +} OC_MAILBOX_COMMAND; + +typedef struct _OC_MAILBOX_ITEM { + UINT32 Data; + OC_MAILBOX_COMMAND Interface; +} OC_MAILBOX_ITEM; + + +EFI_STATUS +EFIAPI PollOcMailboxReady ( + ) +/** + + Poll the run/busy bit of the mailbox until available or timeout expires. + + @param[IN] MailboxType, + + @retval EFI_STATUS + +**/ +{ + EFI_STATUS Status; + UINT16 StallCount; + UINT8 RunBusyBit; + UINT64 MsrData; + OC_MAILBOX_FULL OcMailboxFull; + + Status = EFI_SUCCESS; + StallCount = 0; + RunBusyBit = 1; + + do { +// case MAILBOX_TYPE_OC: + /// + /// Read the OC mailbox run/busy state + /// + MsrData = ReadMsr(OC_MAILBOX_MSR); + pBS->CopyMem (&OcMailboxFull.Data, &MsrData, sizeof(OcMailboxFull)); + RunBusyBit = OcMailboxFull.Interface.Fields.RunBusy; +// break; + // + // Wait for 1us + // + CountTime(4, PM_BASE_ADDRESS); + StallCount++; + } + while ((RunBusyBit == 1) && (StallCount < MAILBOX_WAIT_TIMEOUT)); + + if ((RunBusyBit == 0) && (StallCount == MAILBOX_WAIT_TIMEOUT)) { + TRACE ((TRACE_ALWAYS, "(MAILBOX) Mailbox interface timed out.\n")); + Status = EFI_TIMEOUT; + } + return Status; +} + + +EFI_STATUS +EFIAPI OcMailboxRead ( + IN UINT32 MailboxCommand, + OUT UINT32 *MailboxDataPtr, + OUT UINT32 *MailboxStatus + + ) +/** + + Generic Mailbox function for mailbox read commands. This function will write + the read request, and populate the read results in the output data. + + @param[IN] MailboxType, + @param[IN] MailboxCommand, + @param[OUT] *MailboxDataPtr, + @param[OUT] *MailboxStatus + + @retval EFI_STATUS + +**/ +{ + EFI_STATUS Status; + UINT64 MsrData; + OC_MAILBOX_FULL OcMailboxFull; + OC_MAILBOX_FULL OcMailboxFullVerify; + + /// + /// Poll the run/busy to ensure the interface is available + /// + Status = PollOcMailboxReady(); + if (EFI_ERROR(Status)) { + return Status; + } + + TRACE ((TRACE_ALWAYS, "(MAILBOX) Mailbox Read Command = %2X\n", (UINT8)MailboxCommand)); + + // MAILBOX_TYPE_OC: + /// + /// Set the Run/Busy bit to signal mailbox data is ready to process + /// + OcMailboxFull.Interface.InterfaceData = MailboxCommand; + OcMailboxFull.Data = *MailboxDataPtr; + OcMailboxFull.Interface.Fields.RunBusy = 1; + pBS->CopyMem (&MsrData, &OcMailboxFull, sizeof(MsrData)); + + /// + /// Write mailbox command to OC mailbox + /// + WriteMsr (OC_MAILBOX_MSR, MsrData); + + /// + /// Poll run/busy to indicate the completion of write request + /// + PollOcMailboxReady(); + + /// + /// Read the OC mailbox to verify read completion success. + /// Mailbox protocol requires software to read back the interface twice + /// to ensure the read results are consistent. + /// + MsrData = ReadMsr (OC_MAILBOX_MSR); + pBS->CopyMem (&OcMailboxFull, &MsrData, sizeof(OcMailboxFull)); + + CountTime(40000, PM_BASE_ADDRESS); // 10ms + + MsrData = ReadMsr (OC_MAILBOX_MSR); + pBS->CopyMem (&OcMailboxFullVerify, &MsrData, sizeof(OcMailboxFullVerify)); + + /// + /// If the data is inconsistent, we cannot trust the results + /// + if (OcMailboxFull.Interface.InterfaceData != OcMailboxFullVerify.Interface.InterfaceData ){ + if (OcMailboxFull.Data != OcMailboxFullVerify.Data) { + TRACE ((TRACE_ALWAYS, "(MAILBOX) Mailbox read data is corrupted.\n")); + return EFI_INVALID_PARAMETER; + } + } + + /// + /// Copy Overclocking mailbox completion code and read results + /// + *MailboxStatus = OcMailboxFull.Interface.Fields.CommandCompletion; + pBS->CopyMem(MailboxDataPtr, &OcMailboxFull.Data, sizeof(UINT32)); + + + TRACE ((TRACE_ALWAYS, "(MAILBOX) Mailbox Status = %2X\n", *MailboxStatus)); + + return Status; +} + +VOID +ConvertVoltageTarget ( + IN UINT16 InputVoltageTarget, + OUT UINT16* OutputVoltageTarget, + IN UINT8 ConversionType + ) +/** + + Converts the input voltage target to the fixed point U12.2.10 Volt format or + the Binary millivolts representation based on the ConversionType + +@param[IN] InputVoltageTarget +@param[OUT] *OutputVoltageTarget +@param[IN] ConversionType - 0:fixed point, 1:Binary millivolts + +**/ +{ + /// Fixed point representation: + /// + /// U12.2.10V format + /// | | | | + /// | | | v + /// | | v Exponent + /// | v Significand Size + /// v Size + /// Signed/Unsigned + /// + /// Float Value = Significand x (Base ^ Exponent) + /// (Base ^ Exponent) = 2 ^ 10 = 1024 + /// + + if (InputVoltageTarget == 0){ + *OutputVoltageTarget = 0; + return; + } + + if(ConversionType == CONVERT_TO_FIXED_POINT_VOLTS){ + /// + /// Input Voltage is in number of millivolts. Clip the input Voltage + /// to the max allowed by the fixed point format + /// + if (InputVoltageTarget > MAX_TARGET_MV) + InputVoltageTarget = MAX_TARGET_MV; + + /// + /// InputTargetVoltage is the significand in mV. Need to convert to Volts + /// + *OutputVoltageTarget = (InputVoltageTarget * 1024)/ MILLIVOLTS_PER_VOLT; + + } + else if (ConversionType == CONVERT_TO_BINARY_MILLIVOLT){ + /// + /// InputVoltage is specified in fixed point representation, need to + /// convert to millivolts + /// + *OutputVoltageTarget = (InputVoltageTarget * MILLIVOLTS_PER_VOLT)/1024; + } + + return; +} + +VOID +ConvertVoltageOffset ( + IN INT16 InputVoltageOffset, + OUT INT16* OutputVoltageOffset, + IN UINT8 ConversionType + ) +/** + + Converts the input votlage Offset to the fixed point S11.0.10 Volt format or + to Binary illivolts representation based on the ConversionType. + +@param[IN] InputVoltageTarget +@param[OUT] *OutputVoltageTarget +@param[IN] ConversionType - 0:fixed point, 1:Signed Binary millivolts + + +**/ +{ + BOOLEAN NumIsNegative; + /// Fixed point representation: + /// + /// S11.0.10V format + /// | | | | + /// | | | v + /// | | v Exponent + /// | v Significand Size + /// v Size + /// Signed/Unsigned + /// + /// Float Value = Significand x (Base ^ Exponent) + /// (Base ^ Exponent) = 2 ^ 10 = 1024 + /// + *OutputVoltageOffset = 0; + NumIsNegative = FALSE; + + if (InputVoltageOffset == 0){ + *OutputVoltageOffset = 0; + return; + } + + if (ConversionType == CONVERT_TO_FIXED_POINT_VOLTS){ + /// + /// Input Voltage is in INT16 representation. Check if numenr is negative + /// + if ( (InputVoltageOffset & INT16_SIGN_BIT_MASK) != 0){ + NumIsNegative = TRUE; + /// + /// Need to 2's complement adjust to make this number positive for + /// voltage calculation + /// + InputVoltageOffset = (~InputVoltageOffset+1) & (INT16_SIGN_BIT_MASK -1); + } + + /// + /// Clip the input Voltage Offset to 500mv + /// + if (InputVoltageOffset > MAX_OFFSET_MV) { + InputVoltageOffset = MAX_OFFSET_MV; + } + + /// + /// Convert to fixed point representation + /// + *OutputVoltageOffset = (InputVoltageOffset * 1024)/ MILLIVOLTS_PER_VOLT; + if (NumIsNegative){ + /// 2's complement back to a negative number + *OutputVoltageOffset = ~(*OutputVoltageOffset) + 1; + } + } + else if (ConversionType == CONVERT_TO_BINARY_MILLIVOLT){ + /// + /// Input Voltage is in fixed point representation. Check if number negative + /// + if( (InputVoltageOffset & FIXED_POINT_SIGN_BIT_MASK)!= 0){ + NumIsNegative = TRUE; + /// + /// Need to 2's complement adjust to make this number positive for + /// voltage calculation + /// + InputVoltageOffset = (~InputVoltageOffset+1) & (FIXED_POINT_SIGN_BIT_MASK -1); + } + + /// + /// Convert to INT16 representation in millivolts + /// + *OutputVoltageOffset = (InputVoltageOffset * MILLIVOLTS_PER_VOLT)/1024; + if (NumIsNegative){ + /// 2's complement back to a negative number + *OutputVoltageOffset = ~(*OutputVoltageOffset) + 1; + } + } + + return; +} + +EFI_STATUS +EFIAPI GetOcCapabilities ( + OUT OC_CAPABILITIES_ITEM *OcCapabilities, + OUT UINT32 *LibStatus + ) +/** + Get the overclocking capabilities for a given CPU Domain + + @param[OUT] *OcCapabilities + @param[OUT] *LibStatus + + @retval EFI_STATUS +**/ +{ + EFI_STATUS Status; + UINT32 CommandId; + OC_MAILBOX_ITEM OcCapsMsg; + + Status = EFI_SUCCESS; + +// ZeroMem(&OcCapsMsg,sizeof(OC_MAILBOX_ITEM)); + + /// + /// Convert OC capabilties message to Mailbox command format + /// + CommandId = OC_LIB_CMD_GET_OC_CAPABILITIES; + //ConvertToMailboxFormat((VOID *)OcCapabilities, &OcCapsMsg, CommandId); + OcCapsMsg.Data = 0; + OcCapsMsg.Interface.Fields.CommandCompletion = CommandId; + OcCapsMsg.Interface.Fields.Param1 = 1; + /// + /// Read From the OC Library + /// + Status = OcMailboxRead(OcCapsMsg.Interface.InterfaceData, &OcCapsMsg.Data, LibStatus); + + /// + /// Copy mailbox data to OC Capabilities structure + /// + if ( (Status == EFI_SUCCESS) && (*LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS)) { + OcCapabilities->MaxOcRatioLimit = + (UINT8) OcCapsMsg.Data & OC_CAPS_MAX_RATIO_MASK; + + OcCapabilities->RatioOcSupported = + (UINT8) ((OcCapsMsg.Data & OC_CAPS_RATIO_SUPPORT_MASK) >> OC_CAPS_RATIO_SUPPORT_OFFSET); + + OcCapabilities->VoltageOverridesSupported = + (UINT8) ((OcCapsMsg.Data & OC_CAPS_OVERRIDE_SUPPORT_MASK) >> OC_CAPS_OVERRIDE_SUPPORT_OFFSET); + + OcCapabilities->VoltageOffsetSupported = + (UINT8) ((OcCapsMsg.Data & OC_CAPS_OFFSET_SUPPORT_MASK) >> OC_CAPS_OFFSET_SUPPORT_OFFSET); + } + + return Status; +} + +EFI_STATUS +EFIAPI GetVoltageFrequencyItem ( + OUT VOLTAGE_FREQUENCY_ITEM * VfSettings, + OUT UINT32 *LibStatus + ) +/** + + Gets the Voltage and Frequency information for a given CPU domain + + @param[OUT] *VfSettings + @param[OUT] *LibStatus + + @retval EFI_STATUS + +**/ +{ + EFI_STATUS Status; + UINT32 CommandId; + UINT16 TempVoltageTarget; + INT16 TempVoltageOffset; + OC_MAILBOX_ITEM VfMsg; + + Status = EFI_SUCCESS; + + /// + /// Convert v/f command to Mailbox command format + /// + CommandId = OC_LIB_CMD_GET_VOLTAGE_FREQUENCY; + +// ConvertToMailboxFormat((VOID*)VfSettings, &VfMsg, CommandId); + + /// + /// Voltage Frequency Settings are on a per domain basis + /// + VfMsg.Data = 0; + VfMsg.Interface.Fields.CommandCompletion = CommandId; + VfMsg.Interface.Fields.Param1 = 1; + + /// + /// Read From the OC Library + /// + Status = OcMailboxRead(VfMsg.Interface.InterfaceData, &VfMsg.Data, LibStatus); + + /// + /// Copy mailbox data to VfSettings + /// + if ( (Status == EFI_SUCCESS) && (*LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS)){ + VfSettings->VfSettings.MaxOcRatio = (UINT8) (VfMsg.Data & MAX_RATIO_MASK); + VfSettings->VfSettings.VoltageTargetMode = (UINT8) ( (VfMsg.Data & VOLTAGE_MODE_MASK) >> VOLTAGE_MODE_OFFSET); + + TempVoltageTarget = (UINT16) (VfMsg.Data & VOLTAGE_TARGET_MASK) >> VOLTAGE_TARGET_OFFSET; + ConvertVoltageTarget(TempVoltageTarget, &VfSettings->VfSettings.VoltageTarget, CONVERT_TO_BINARY_MILLIVOLT); + + TempVoltageOffset = (INT16)((VfMsg.Data & VOLTAGE_OFFSET_MASK) >> VOLTAGE_OFFSET_OFFSET); + ConvertVoltageOffset(TempVoltageOffset, &VfSettings->VfSettings.VoltageOffset, CONVERT_TO_BINARY_MILLIVOLT); + } + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbXTUSetGACITable +// +// Description: Update XTU GACI Table function . +// +// Input: +// IN EFI_EVENT Event +// IN VOID *Context +// +// Output: +// VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbXTUSetGACITable( + IN EFI_EVENT Event, + IN VOID *Context +) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + UINT8 *Buffer = NULL; + UINTN Len = 0; + UINT8 channel = 0; + EFI_GUID gXtuDataHobGuid = AMI_PERF_TUNE_DATA_HOB_GUID; + UINT8 NumOcBins = (UINT8)(ReadMsr(0x194) >> 17) & 0x7; + VOID *FirstHob; + AMI_INTERNAL_FACTORY_TDC_TDP_HOB *TdcTdpHob = NULL; + BOOLEAN TdcTdpHobFound = FALSE, OcDataHobFound = FALSE; + UINT16 OneCoreRatioLimit; + UINT16 MaxNonTurboRatio; + UINT8 MemRatio, RefClkRatio; + UINT32 CurrentRatio; + OC_CAPABILITIES_ITEM OcCaps; + UINT32 LibStatus; + PERF_TUNE_DATA_HOB *PerfTuneDataHob = NULL; + UINT32 MemFreq; + MrcFrequency DDRFrequency[2] = {fNoInit}; + + if (gPerfTuneAslProtocol == NULL) + { + Status = pBS->LocateProtocol(&gPerfTuneAslProtocolGuid, NULL, &gPerfTuneAslProtocol); + if(EFI_ERROR(Status))goto Done; + } + + FirstHob = GetEfiConfigurationTable(pST, &gHobListGuid); + + TdcTdpHob = (AMI_INTERNAL_FACTORY_TDC_TDP_HOB*)FirstHob; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &TdcTdpHob))) { + if (guidcmp(&TdcTdpHob->EfiHobGuidType.Name, &gAmiInternalFactoryTdcTdpHobGuid) == 0) { + TdcTdpHobFound = TRUE; + break; + } + } + + FirstHob = GetEfiConfigurationTable(pST, &gHobListGuid); + + PerfTuneDataHob = (PERF_TUNE_DATA_HOB*)FirstHob; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &PerfTuneDataHob))) { + if (guidcmp(&PerfTuneDataHob->EfiHobGuidType.Name, &gXtuDataHobGuid) == 0) { + OcDataHobFound = TRUE; + break; + } + } + +//========================== GACI TABLE ============================================= +//------------------------- tCL Setting ---------------------------------------- + Len = sizeof(tCLGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tCLGaciData.DefaultDataValue = NBMrcTimingData[0].tCL;//DefaultData.tCL; + + MemCpy(Buffer, &tCLGaciData, sizeof(tCLGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tCL); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tCWL Setting --------------------------------------- + Len = sizeof(tCWLGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tCWLGaciData.DefaultDataValue = NBMrcTimingData[0].tCWL;//DefaultData.tCWL; + + MemCpy(Buffer, &tCWLGaciData, sizeof(tCWLGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tCWL); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tREFI Setting --------------------------------------- + Len = sizeof(tREFIGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tREFIGaciData.DefaultDataValue = NBMrcTimingData[0].tREFI;//DefaultData.tREFI; + + MemCpy(Buffer, &tREFIGaciData, sizeof(tREFIGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tREFI); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRCD Setting --------------------------------------- + Len = sizeof(tRCDGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRCDGaciData.DefaultDataValue = NBMrcTimingData[0].tRCD;//DefaultData.tRCD; + + MemCpy(Buffer, &tRCDGaciData, sizeof(tRCDGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRCD); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRP Setting ---------------------------------------- + Len = sizeof(tRPGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRPGaciData.DefaultDataValue = NBMrcTimingData[0].tRP;//DefaultData.tRP; + + MemCpy(Buffer, &tRPGaciData, sizeof(tRPGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRP); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRAS Setting --------------------------------------- + Len = sizeof(tRASGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRASGaciData.DefaultDataValue = NBMrcTimingData[0].tRAS;//DefaultData.tRAS; + + MemCpy(Buffer, &tRASGaciData, sizeof(tRASGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRAS); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tWR Setting --------------------------------------- + Len = sizeof(tWRGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tWRGaciData.DefaultDataValue = NBMrcTimingData[0].tWR;//DefaultData.tWR; + + MemCpy(Buffer, &tWRGaciData, sizeof(tWRGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tWR); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRFC Setting --------------------------------------- + Len = sizeof(tRFCGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRFCGaciData.DefaultDataValue = NBMrcTimingData[0].tRFC;//DefaultData.tRFC; + + MemCpy(Buffer, &tRFCGaciData, sizeof(tRFCGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRFC); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRRD Setting --------------------------------------- + Len = sizeof(tRRDGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + tRRDGaciData.DefaultDataValue = NBMrcTimingData[0].tRRD;//DefaultData.tRRD; + + MemCpy(Buffer, &tRRDGaciData, sizeof(tRRDGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRRD); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tWTR Setting --------------------------------------- + Len = sizeof(tWTRGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tWTRGaciData.DefaultDataValue = NBMrcTimingData[0].tWTR;//DefaultData.tWTR; + + MemCpy(Buffer, &tWTRGaciData, sizeof(tWTRGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tWTR); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRTP Setting --------------------------------------- + Len = sizeof(tRTPGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRTPGaciData.DefaultDataValue = NBMrcTimingData[0].tRTP;//DefaultData.tRTP; + + MemCpy(Buffer, &tRTPGaciData, sizeof(tRTPGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRTP); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tFAW Setting --------------------------------------- + Len = sizeof(tFAWGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tFAWGaciData.DefaultDataValue = NBMrcTimingData[0].tFAW;//DefaultData.tFAW; + + MemCpy(Buffer, &tFAWGaciData, sizeof(tFAWGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tFAW); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRC Setting --------------------------------------- + Len = sizeof(tRCGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + tRCGaciData.DefaultDataValue = NBMrcTimingData[0].tRC;//DefaultData.tRC; + + MemCpy(Buffer, &tRCGaciData, sizeof(tRCGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRC); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------- tRPab Setting --------------------------------------- +// Len = sizeof(tRPabGaciData); +// Buffer = MallocZ(Len); +// if(!Buffer) goto Done; + +// tRPabGaciData.DefaultDataValue = NBMrcTimingData[0].tRPab;//DefaultData.tRPab; + +// MemCpy(Buffer, &tRPabGaciData, sizeof(tRPabGaciData)); +// Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)NBMrcTimingData[MemoryProfile].tRPab); +// Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); +// pBS->FreePool(Buffer); +//----------------------------- iGfX Core Ratio Limit --------------------------- + if (READ_PCI32_IGD (R_SA_IGD_VID) != 0xFFFFFFFF) { + + Status = GetOcCapabilities(&OcCaps,&LibStatus); + if ( (Status == EFI_SUCCESS) && (LibStatus == OC_LIB_COMPLETION_CODE_SUCCESS)) { + + Len = sizeof(iGfxTurboRatioData); + Buffer = MallocZ(Len); + + + CurrentRatio = OcCaps.MaxOcRatioLimit; + + iGfxTurboRatioData.MinDataValue = READ_MEM8_MCH(0x5998); // Rpm + iGfxTurboRatioData.MaxDataValue = CurrentRatio; + iGfxTurboRatioData.DefaultDataValue = READ_MEM8_MCH(0x5998); // Rpm + + + iGfxTurboRatioData.MinDisplayValue = iGfxTurboRatioData.MinDataValue * 5; + iGfxTurboRatioData.MaxDisplayValue = iGfxTurboRatioData.MaxDataValue * 5; + iGfxTurboRatioData.NumberOfValues = iGfxTurboRatioData.MaxDataValue - iGfxTurboRatioData.MinDataValue + 1; + + + MemCpy(Buffer, &iGfxTurboRatioData, sizeof(iGfxTurboRatioData)); + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------------- iGfX Voltage mode ------------------------------- + Len = sizeof(iGfxVoltageMode); + Buffer = MallocZ(Len); + + iGfxVoltageMode.MaxDataValue = 1; + iGfxVoltageMode.MaxDisplayValue = 1; + iGfxVoltageMode.NumberOfValues = 2; + + MemCpy(Buffer, &iGfxVoltageMode, sizeof(iGfxVoltageMode)); + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------------- iGfX Voltage ------------------------------- +// Len = sizeof(iGfxVoltageData); +// Buffer = MallocZ(Len); + + //GtOcVolt = CurrentVfItem.VfSettings.VoltageTarget; + +// MemCpy(Buffer, &iGfxVoltageData, sizeof(iGfxVoltageData)); + + //Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, (UINT16)GtOcVolt); + +// Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); +// pBS->FreePool(Buffer); +//------------------------------- iGfX Voltage Override------------------------------- + Len = sizeof(iGfxVoltageOverride); + Buffer = MallocZ(Len); + + + MemCpy(Buffer, &iGfxVoltageOverride, sizeof(iGfxVoltageOverride)); + + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + +//------------------------------- iGfX Voltage Offset------------------------------- + Len = sizeof(iGfxVoltageOffset); + Buffer = MallocZ(Len); + + + MemCpy(Buffer, &iGfxVoltageOffset, sizeof(iGfxVoltageOffset)); + + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + } // GetVoltageFrequencyItem + } // if have IGFX ? +//------------------------------- Sa Voltage Offset ------------------------------- + Len = sizeof(SaVoltageOffset); + Buffer = MallocZ(Len); + + MemCpy(Buffer, &SaVoltageOffset, sizeof(SaVoltageOffset)); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + +//------------------------------- IOA Voltage Offset ------------------------------- + Len = sizeof(IoaVoltageOffset); + Buffer = MallocZ(Len); + + MemCpy(Buffer, &IoaVoltageOffset, sizeof(IoaVoltageOffset)); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + +//------------------------------- IOD Voltage Offset ------------------------------- + Len = sizeof(IodVoltageOffset); + Buffer = MallocZ(Len); + + MemCpy(Buffer, &IodVoltageOffset, sizeof(IodVoltageOffset)); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//------------------------------- Runtime Turbo ------------------------------- + if (TdcTdpHobFound) { + + Len = sizeof(CpuRuntimeTurbo); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + OneCoreRatioLimit = (UINT16)(TdcTdpHob->OneCoreRatioLimit); + MaxNonTurboRatio = ((UINT16)ReadMsr(0xCE) >> 8) & 0xFF; + + if(OcDataHobFound) { + if(PerfTuneDataHob->PerfTuneDataHob.RuntimeTurboEanble == 0x1) { + if(PerfTuneDataHob->PerfTuneDataHob.RuntimeTurbo == 0xFFFF) + WRITE_MEM8_MCH(0x5990, (UINT8)OneCoreRatioLimit); + else + WRITE_MEM8_MCH(0x5990, (UINT8)PerfTuneDataHob->PerfTuneDataHob.RuntimeTurbo); + } else { + WRITE_MEM8_MCH(0x5990, 0xFF); + } + } + + CpuRuntimeTurbo.DefaultDataValue = OneCoreRatioLimit; + + if (NumOcBins == 7) { + CpuRuntimeTurbo.MaxDataValue = 0x3b; //max ratio is 59. + CpuRuntimeTurbo.MaxDisplayValue = 0x3b; + } else if((NumOcBins > 0) && (NumOcBins < 7)) { + CpuRuntimeTurbo.MaxDataValue = OneCoreRatioLimit + NumOcBins; + CpuRuntimeTurbo.MaxDisplayValue = OneCoreRatioLimit + NumOcBins; + } + + CpuRuntimeTurbo.MinDataValue = MaxNonTurboRatio; + CpuRuntimeTurbo.MinDisplayValue = MaxNonTurboRatio; + CpuRuntimeTurbo.NumberOfValues = CpuRuntimeTurbo.MaxDataValue - CpuRuntimeTurbo.MinDataValue + 1; + + MemCpy(Buffer, &CpuRuntimeTurbo, sizeof(CpuRuntimeTurbo)); + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); + } +//-------------------------- Mem Freq Setting ---------------------------------------- + Len = sizeof(DramMultiGaciData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + MemFreq = gMemInfoHobProtocol.MemInfoData.ddrFreq; + MemRatio = (NbFrequencyToRatio(MemFreq, gMemInfoHobProtocol.MemInfoData.RefClk, gBClkFrequency)*2); + DramMultiGaciData.DefaultDataValue = (UINT32)MemRatio; + + MemCpy(Buffer, &DramMultiGaciData, sizeof(DramMultiGaciData)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, MemRatio); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//----------------------------Memory Clock Multiplier----------------------- + Len = sizeof(MemClockMultiplier); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + if(gMemInfoHobProtocol.MemInfoData.RefClk == MRC_REF_CLOCK_100){ + RefClkRatio = 100; + }else{ + RefClkRatio = 133; + } + + MemClockMultiplier.DefaultDataValue = (UINT32)RefClkRatio; + MemCpy(Buffer, &MemClockMultiplier, sizeof(MemClockMultiplier)); + Status = gPerfTuneAslProtocol->SyncHwValue(Buffer, RefClkRatio); + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//-------------------------- XMP Profile Selection ------------------------- + + Len = sizeof(XmpProfSelData); + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + //Add core to Update the Minimum and Maximum. + //According to XMP profile count. + + // Default + XmpProfSelData.MaxDataValue = 1; + XmpProfSelData.MaxDisplayValue = 1; + XmpProfSelData.NumberOfValues = 2; + + DDRFrequency[0] = NbGetDimmFrequency(NBMrcTimingData[2].tCK); + DDRFrequency[1] = NbGetDimmFrequency(NBMrcTimingData[3].tCK); + + if (DDRFrequency[0] != fNoInit && DDRFrequency[1] == fNoInit) { // Porfile 1 + XmpProfSelData.MaxDataValue = 2; + XmpProfSelData.MaxDisplayValue = 2; + XmpProfSelData.NumberOfValues = 3; + } else if (DDRFrequency[0] != fNoInit && DDRFrequency[1] != fNoInit) { // Both Profile + XmpProfSelData.MaxDataValue = 3; + XmpProfSelData.MaxDisplayValue = 3; + XmpProfSelData.NumberOfValues = 4; + } + + MemCpy(Buffer, &XmpProfSelData, Len); + + Status = gPerfTuneAslProtocol->SetGaciData(Buffer, Len); + pBS->FreePool(Buffer); +//---------------------------- GXDV START ----------------------------------- + + Len = sizeof(GXDV_DATA); + Len = (UINTN)Mul64(Len, 30); // 32 mean, define GXDV count. + Buffer = MallocZ(Len); + if(!Buffer) goto Done; + + //Add code to change profile 1 display value + if (DDRFrequency[0] != fNoInit) { + MemRatio = NbFrequencyToRatio(DDRFrequency[0], gMemInfoHobProtocol.MemInfoData.RefClk, gBClkFrequency); + + Pro1tCLGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tCL; + Pro1tRASGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRAS; + Pro1tRPGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRP; + Pro1tRCDGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRCD; + Pro1tWRGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tWR; + Pro1tRFCGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRFC; + Pro1tRRDGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRRD; + Pro1tWTRGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tWTR; + Pro1tRTPGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRTP; + Pro1tFAWGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tFAW; + Pro1tRCGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRC; + Pro1tREFIGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tREFI; + Pro1tCWLGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tCWL; +// Pro1tRPabGxdvData.DisplayValue = (UINT32)NBMrcTimingData[2].tRPab; + Pro1DdrMulGxdvData.DisplayValue = (UINT32)DDRFrequency[0]; + Pro1DdrMulGxdvData.DisplayValue = (UINT32)MemRatio * 2; + Pro1DdrClkMulGxdvData.DisplayValue = (UINT32)RefClkRatio; + + } + + //Add code to change Profile 2 display value + if (DDRFrequency[1] != fNoInit) { + MemRatio = NbFrequencyToRatio(DDRFrequency[1], gMemInfoHobProtocol.MemInfoData.RefClk, gBClkFrequency); + + Pro2tCLGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tCL; + Pro2tRASGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRAS; + Pro2tRPGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRP; + Pro2tRCDGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRCD; + Pro2tWRGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tWR; + Pro2tRFCGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRFC; + Pro2tRRDGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRRD; + Pro2tWTRGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tWTR; + Pro2tRTPGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRTP; + Pro2tFAWGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tFAW; + Pro2tRCGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRC; + Pro2tREFIGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tREFI; + Pro2tCWLGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tCWL; +// Pro1tRPabGxdvData.DisplayValue = (UINT32)NBMrcTimingData[3].tRPab; + Pro2DdrMulGxdvData.DisplayValue = (UINT32)DDRFrequency[1]; + Pro2DdrMulGxdvData.DisplayValue = (UINT32)MemRatio * 2; + Pro2DdrClkMulGxdvData.DisplayValue = (UINT32)RefClkRatio; + } + + MemCpy(Buffer, &Pro1tCLGxdvData, Len); + + if (DDRFrequency[0] == fNoInit && DDRFrequency[1] == fNoInit) // Default + Status = gPerfTuneAslProtocol->SetGxdvData(XmpNotSupport,Buffer, Len); + else if (DDRFrequency[0] != fNoInit && DDRFrequency[1] == fNoInit) // Profile 1 + Status = gPerfTuneAslProtocol->SetGxdvData(Profiles1,Buffer, Len); + else if (DDRFrequency[0] != fNoInit && DDRFrequency[1] != fNoInit) // Both Profile + Status = gPerfTuneAslProtocol->SetGxdvData(Both,Buffer, Len); + + pBS->FreePool(Buffer); + +//---------------------------- GXDV END ----------------------------------- + +Done: + // Kill event + pBS->CloseEvent(Event); +} +#endif +#endif + + +EFI_STATUS ReadSpdData ( + IN EFI_SMBUS_HC_PROTOCOL *Smbus, + IN UINT8 SpdSalveAddr, + IN UINT8 Offset, + IN UINTN Count, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN Length; + EFI_SMBUS_OPERATION Operation; + EFI_SMBUS_DEVICE_COMMAND Command; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + + SlaveAddress.SmbusDeviceAddress = SpdSalveAddr >> 1; + + + for (Index = 0; Index < Count; Index++) + { + Command = Offset + Index; + + Length = 1; + Operation = EfiSmbusReadByte; + Status = Smbus->Execute (Smbus, + SlaveAddress, + Command, + Operation, + FALSE, + &Length, + &Buffer[Index] ); + if (EFI_ERROR(Status)) return Status; + } + + return EFI_SUCCESS; +} + +#define MRC_FREQUENCY_MTB_OFFSET 1000000 +#define MRC_FREQUENCY_FTB_OFFSET 1000 +#define MRC_DDR3_800_TCK_MIN 2500000 /// 1/(800/2) femtoseconds +#define MRC_DDR3_1000_TCK_MIN 2000000 /// 1/(1000/2) femtoseconds +#define MRC_DDR3_1067_TCK_MIN 1875000 /// 1/(1067/2) femtoseconds +#define MRC_DDR3_1200_TCK_MIN 1666666 /// 1/(1200/2) femtoseconds +#define MRC_DDR3_1333_TCK_MIN 1500000 /// 1/(1333/2) femtoseconds +#define MRC_DDR3_1400_TCK_MIN 1428571 /// 1/(1400/2) femtoseconds +#define MRC_DDR3_1600_TCK_MIN 1250000 /// 1/(1600/2) femtoseconds +#define MRC_DDR3_1800_TCK_MIN 1111111 /// 1/(1800/2) femtoseconds +#define MRC_DDR3_1867_TCK_MIN 1071428 /// 1/(1867/2) femtoseconds +#define MRC_DDR3_2000_TCK_MIN 1000000 /// 1/(2000/2) femtoseconds +#define MRC_DDR3_2133_TCK_MIN 937500 /// 1/(2133/2) femtoseconds +#define MRC_DDR3_2200_TCK_MIN 909090 /// 1/(2200/2) femtoseconds +#define MRC_DDR3_2400_TCK_MIN 833333 /// 1/(2400/2) femtoseconds +#define MRC_DDR3_2600_TCK_MIN 769230 /// 1/(2600/2) femtoseconds +#define MRC_DDR3_2667_TCK_MIN 750000 /// 1/(2667/2) femtoseconds +#define MRC_DDR3_2800_TCK_MIN 714285 /// 1/(2800/2) femtoseconds +#define TREFIMULTIPLIER 1000 /// tREFI value defined in XMP 1.3 spec is actually in thousands of MTB units. +#define MAX(a,b) (((a) > (b)) ? (a) : (b)) +#define MIN(a,b) (((a) < (b)) ? (a) : (b)) + +const NbTRangeTable NbRange[] = { + { 0xFFFFFFFF, fUnSupport, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_800_TCK_MIN, f800, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1000_TCK_MIN, f1000, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1067_TCK_MIN, f1067, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1200_TCK_MIN, f1200, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1333_TCK_MIN, f1333, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1400_TCK_MIN, f1400, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1600_TCK_MIN, f1600, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1800_TCK_MIN, f1800, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1867_TCK_MIN, f1867, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2000_TCK_MIN, f2000, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2133_TCK_MIN, f2133, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2200_TCK_MIN, f2200, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2400_TCK_MIN, f2400, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2600_TCK_MIN, f2600, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2667_TCK_MIN, f2667, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { 0, fNoInit, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) } +}; + +static BOOLEAN +NbGetDimmTimeBase ( + IN SPD_EXTREME_MEMORY_PROFILE *const XmpSpd, + IN UINT8 MemoryProfile, + OUT INT32 *const Mtb, + OUT INT32 *const Ftb + ) +{ + UINT8 SpdMtbDividend; + UINT8 SpdMtbDivisor; + UINT8 SpdFtbDividend; + UINT8 SpdFtbDivisor; + + + SpdFtbDividend = XmpSpd->Header.FineTimeBase.Bits.Dividend; + SpdFtbDivisor = XmpSpd->Header.FineTimeBase.Bits.Divisor; + SpdMtbDividend = XmpSpd->Header.MediumTimeBase[MemoryProfile].Dividend.Bits.Dividend; + SpdMtbDivisor = XmpSpd->Header.MediumTimeBase[MemoryProfile].Divisor.Bits.Divisor; + + *Ftb = (SpdFtbDivisor == 0) ? 0 : (SpdFtbDividend * MRC_FREQUENCY_FTB_OFFSET) / SpdFtbDivisor; + *Mtb = (SpdMtbDivisor == 0) ? 0 : (SpdMtbDividend * MRC_FREQUENCY_MTB_OFFSET) / SpdMtbDivisor; + + return (*Mtb == 0) ? FALSE : TRUE; +} + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + +static +MrcFrequency +NbGetDimmFrequency ( + IN UINT32 tCK + ) +{ + UINT32 Index; + MrcFrequency XmpFrequency = fNoInit; + UINT32 NbRangeSize = (sizeof (NbRange) / sizeof (NbTRangeTable)) - 1; + + if(tCK == 0 || tCK == 0xffffffff) return fNoInit; + + for (Index = 0; Index < NbRangeSize; Index++) { + if ((tCK <= NbRange[Index].tCK) && (tCK > NbRange[Index + 1].tCK)) { + XmpFrequency = NbRange[Index].DDRFreq; + break; + } + } + + while (Index) { + if ((NbRange[Index].RefClkFlag & (1 << gMemInfoHobProtocol.MemInfoData.RefClk)) == MRC_REF_CLOCK_133) { + XmpFrequency = NbRange[--Index].DDRFreq; + } else break; + } + + return XmpFrequency; +} +/* +static +BOOLEAN +NbGetDimmFrequency ( + IN SPD_EXTREME_MEMORY_PROFILE *const XmpSpd, + IN UINT8 MemoryProfile, + IN UINT8 DimmCount + ) +{ + INT32 MediumTimebase; + INT32 FineTimebase; + INT32 tCKminMtb; + INT32 tCKminFine; + INT32 tCKmin; + UINT32 NbRangeSize = (sizeof (NbRange) / sizeof (NbTRangeTable)) - 1; + UINT32 Index; + UINT32 TimingMTB; + INT32 TimingFTB; + SPD_EXTREME_MEMORY_PROFILE_DATA *ExtremeData; + NbXmpProfileData *ProfileTimingData; + MrcFrequency XmpFrequency; + UINT32 Calculated; + UINT32 tAAmin; + UINT32 tAAminFine; + + XmpFrequency = fNoInit; + tCKmin = 0; + tCKminMtb = 0; + tCKminFine = 0; + TimingMTB = 0; + TimingFTB = 0; + Calculated = 0; + tAAmin = 0; + tAAminFine = 0; + + ProfileTimingData = &XmpDimm[DimmCount].XmpProfileTiming[MemoryProfile]; + + if(NbGetDimmTimeBase (XmpSpd, MemoryProfile, &MediumTimebase, &FineTimebase)) { + ExtremeData = &XmpSpd->Data[MemoryProfile]; + tCKminMtb = ExtremeData->tCKmin.Bits.tCKmin; + tCKminFine = ExtremeData->tCKminFine.Bits.tCKminFine; + tCKmin = (MediumTimebase * tCKminMtb) + (FineTimebase * tCKminFine); + + for (Index = 0; Index < NbRangeSize; Index++) { + if ((tCKmin <= NbRange[Index].tCK) && (tCKmin > NbRange[Index + 1].tCK)) { + XmpFrequency = NbRange[Index].DDRFreq; + ProfileTimingData->TimingData.tCK = NbRange[Index].tCK; + break; + } + } + + while (Index) { + if ((NbRange[Index].RefClkFlag & (1 << gMemInfoHobProtocol.MemInfoData.RefClk)) == MRC_REF_CLOCK_133) { + XmpFrequency = NbRange[--Index].DDRFreq; + } else break; + } +// *tCKminIndex = Index; + + // tCL + tAAmin = ExtremeData->tAAmin.Bits.tAAmin; + tAAminFine = ExtremeData->tAAminFine.Bits.tAAminFine; + tAAmin = (MediumTimebase * tAAmin) + (FineTimebase * tAAminFine); + ProfileTimingData->TimingData.tCL = (UINT16) ((tAAmin + (ProfileTimingData->TimingData.tCK - 1)) / ProfileTimingData->TimingData.tCK); + ProfileTimingData->TimingData.tCL = MIN (ProfileTimingData->TimingData.tCL, tCL_MAXIMUM); + // tCWL + TimingMTB = ExtremeData->tCWLmin.Bits.tCWLmin; + ProfileTimingData->TimingData.tCWL = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tCWL = MIN (ProfileTimingData->TimingData.tCWL, tCWL_MAXIMUM); + // tWR + TimingMTB = ExtremeData->tWRmin.Bits.tWRmin; + Calculated = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + // + // Special case, tWRmin values of 9, 11, 13, and 15 are not supported by DDR3 Mode Register 0 (MR0). + // If we see one of these values, then add one clock to it in order to make it valid. + // + if ((9 == Calculated) || (11 == Calculated) || (13 == Calculated) || (15 == Calculated)) { + Calculated++; + } + ProfileTimingData->TimingData.tWR = Calculated; + ProfileTimingData->TimingData.tWR = MIN (ProfileTimingData->TimingData.tWR, tWR_MAXIMUM); + // tRRD + TimingMTB = ExtremeData->tRRDmin.Bits.tRRDmin; + ProfileTimingData->TimingData.tRRD = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRRD = MIN (ProfileTimingData->TimingData.tRRD, tRRD_MAXIMUM); + // tRCD + TimingMTB = ExtremeData->tRCDmin.Bits.tRCDmin; + TimingFTB = ExtremeData->tRCDminFine.Bits.tRCDminFine; + ProfileTimingData->TimingData.tRCD = ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRCD = MIN (ProfileTimingData->TimingData.tRCD, tRCD_MAXIMUM); + // tRP + TimingMTB = ExtremeData->tRPmin.Bits.tRPmin; + TimingFTB = ExtremeData->tRPminFine.Bits.tRPminFine; + ProfileTimingData->TimingData.tRP = ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRP = MIN (ProfileTimingData->TimingData.tRP, tRP_MAXIMUM); + // tRAS + TimingMTB = ((UINT32) (ExtremeData->tRASMintRCMinUpper.Bits.tRASminUpper) << 8) | (UINT32) (ExtremeData->tRASmin.Bits.tRASmin); + ProfileTimingData->TimingData.tRAS = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRAS = MIN (ProfileTimingData->TimingData.tRAS, tRAS_MAXIMUM); + // tRFC + TimingMTB = ExtremeData->tRFCmin.Bits.tRFCmin; + ProfileTimingData->TimingData.tRFC = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRFC = MIN (ProfileTimingData->TimingData.tRFC, tRFC_MAXIMUM); + + // tWTR + TimingMTB = ExtremeData->tWTRmin.Bits.tWTRmin; + ProfileTimingData->TimingData.tWTR = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tWTR = MIN (ProfileTimingData->TimingData.tWTR, tWTR_MAXIMUM); + + // tRTP + TimingMTB = ExtremeData->tRTPmin.Bits.tRTPmin; + ProfileTimingData->TimingData.tRTP = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRTP = MIN (ProfileTimingData->TimingData.tRTP, tRTP_MAXIMUM); + + // tFAW + TimingMTB = ((UINT32) (ExtremeData->tFAWMinUpper.Bits.tFAWminUpper) << 8) | (UINT32) (ExtremeData->tFAWmin.Bits.tFAWmin); + ProfileTimingData->TimingData.tFAW = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tFAW = MIN (ProfileTimingData->TimingData.tFAW, tFAW_MAXIMUM); + + // tRC + TimingMTB = ((UINT32) (ExtremeData->tRASMintRCMinUpper.Bits.tRCminUpper) << 8) | (UINT32) (ExtremeData->tRCmin.Bits.tRCmin); + TimingFTB = ExtremeData->tRCminFine.Bits.tRCminFine; + ProfileTimingData->TimingData.tRC = ((MediumTimebase * TimingMTB) + (FineTimebase * TimingFTB) + (tCKmin - 1)) / tCKmin; + ProfileTimingData->TimingData.tRC = MIN (ProfileTimingData->TimingData.tRC, tRC_MAXIMUM); + + // tREFI + TimingMTB = ExtremeData->tREFImin.Bits.tREFImin; + ProfileTimingData->TimingData.tREFI = (UINT32)Div64 (((Mul64 (MediumTimebase, TimingMTB * TREFIMULTIPLIER) + (tCKmin - 1))), tCKmin, NULL); + ProfileTimingData->TimingData.tREFI = MIN (ProfileTimingData->TimingData.tREFI, tREFI_MAXIMUM); + //NMode + TimingMTB = ExtremeData->SystemCmdRate.Bits.NMode; + if (TimingMTB > 0) { + ProfileTimingData->TimingData.NMode = ((MediumTimebase * TimingMTB) + (tCKmin - 1)) / tCKmin; + } + } + + ProfileTimingData->DDRFreq = XmpFrequency; + + if (XmpFrequency != fNoInit) return TRUE; + + return FALSE; +} +*/ +#endif +#endif + +EFI_STATUS NbReportXmpInfo( + IN EFI_EVENT Event, + IN VOID *Context +) +{ +/* + EFI_STATUS Status; + EFI_SMBUS_HC_PROTOCOL *Smbus; + SPD_EXTREME_MEMORY_PROFILE XmpSpd; + VOID *SpdData = &XmpSpd; + UINT8 i, DimmCount; + + Status = pBS->LocateProtocol( &gEfiSmbusProtocolGuid, \ + NULL, \ + &Smbus ); + if (EFI_ERROR(Status))return Status; + + + for (i = DIMM1_SMBUS_ADDRESS, DimmCount = 0; DimmCount < 4; i += 2, DimmCount++) { + Status = ReadSpdData(Smbus, i, 176, 2, (UINT8*)SpdData); + if (EFI_ERROR(Status) || (XmpSpd.Header.XmpId != 0x4A0C)) continue; + Status = ReadSpdData(Smbus, i, 176, 79, (UINT8*)SpdData); + if (EFI_ERROR(Status)) continue; + + if(XmpSpd.Header.XmpOrgConf.Bits.ProfileEnable1) { + NBPlatformData.XmpProfile1 = 1; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + NbGetDimmFrequency (SpdData, 0, DimmCount); +#endif +#endif + } else continue; + + if(XmpSpd.Header.XmpOrgConf.Bits.ProfileEnable2) { + NBPlatformData.XmpProfile2 = 1; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + NbGetDimmFrequency (SpdData, 1, DimmCount); +#endif +#endif + } + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + // Channel 0 XmpProfile 1~2 + XmpChannel[0].XmpProfileTiming[0].DDRFreq = MAX(XmpDimm[0].XmpProfileTiming[0].DDRFreq, XmpDimm[1].XmpProfileTiming[0].DDRFreq); + XmpChannel[0].XmpProfileTiming[1].DDRFreq = MAX(XmpDimm[0].XmpProfileTiming[1].DDRFreq, XmpDimm[1].XmpProfileTiming[1].DDRFreq); + XmpChannel[0].XmpProfileTiming[0].TimingData.tCL = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tCL, XmpDimm[1].XmpProfileTiming[0].TimingData.tCL); + XmpChannel[0].XmpProfileTiming[1].TimingData.tCL = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tCL, XmpDimm[1].XmpProfileTiming[1].TimingData.tCL); + XmpChannel[0].XmpProfileTiming[0].TimingData.tCWL = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tCWL, XmpDimm[1].XmpProfileTiming[0].TimingData.tCWL); + XmpChannel[0].XmpProfileTiming[1].TimingData.tCWL = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tCWL, XmpDimm[1].XmpProfileTiming[1].TimingData.tCWL); + XmpChannel[0].XmpProfileTiming[0].TimingData.tWR = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tWR, XmpDimm[1].XmpProfileTiming[0].TimingData.tWR); + XmpChannel[0].XmpProfileTiming[1].TimingData.tWR = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tWR, XmpDimm[1].XmpProfileTiming[1].TimingData.tWR); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRRD = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRRD, XmpDimm[1].XmpProfileTiming[0].TimingData.tRRD); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRRD = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRRD, XmpDimm[1].XmpProfileTiming[1].TimingData.tRRD); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRCD = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRCD, XmpDimm[1].XmpProfileTiming[0].TimingData.tRCD); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRCD = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRCD, XmpDimm[1].XmpProfileTiming[1].TimingData.tRCD); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRP = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRP, XmpDimm[1].XmpProfileTiming[0].TimingData.tRP); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRP = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRP, XmpDimm[1].XmpProfileTiming[1].TimingData.tRP); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRAS = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRAS, XmpDimm[1].XmpProfileTiming[0].TimingData.tRAS); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRAS = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRAS, XmpDimm[1].XmpProfileTiming[1].TimingData.tRAS); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRFC = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRFC, XmpDimm[1].XmpProfileTiming[0].TimingData.tRFC); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRFC = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRFC, XmpDimm[1].XmpProfileTiming[1].TimingData.tRFC); + XmpChannel[0].XmpProfileTiming[0].TimingData.tWTR = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tWTR, XmpDimm[1].XmpProfileTiming[0].TimingData.tWTR); + XmpChannel[0].XmpProfileTiming[1].TimingData.tWTR = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tWTR, XmpDimm[1].XmpProfileTiming[1].TimingData.tWTR); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRTP = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRTP, XmpDimm[1].XmpProfileTiming[0].TimingData.tRTP); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRTP = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRTP, XmpDimm[1].XmpProfileTiming[1].TimingData.tRTP); + XmpChannel[0].XmpProfileTiming[0].TimingData.tFAW = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRC, XmpDimm[1].XmpProfileTiming[0].TimingData.tFAW); + XmpChannel[0].XmpProfileTiming[1].TimingData.tFAW = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRC, XmpDimm[1].XmpProfileTiming[1].TimingData.tFAW); + XmpChannel[0].XmpProfileTiming[0].TimingData.tREFI = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tREFI, XmpDimm[1].XmpProfileTiming[0].TimingData.tREFI); + XmpChannel[0].XmpProfileTiming[1].TimingData.tREFI = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tREFI, XmpDimm[1].XmpProfileTiming[1].TimingData.tREFI); + XmpChannel[0].XmpProfileTiming[0].TimingData.tRC = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.tRC, XmpDimm[1].XmpProfileTiming[0].TimingData.tRC); + XmpChannel[0].XmpProfileTiming[1].TimingData.tRC = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.tRC, XmpDimm[1].XmpProfileTiming[1].TimingData.tRC); + XmpChannel[0].XmpProfileTiming[0].TimingData.NMode = MAX(XmpDimm[0].XmpProfileTiming[0].TimingData.NMode, XmpDimm[1].XmpProfileTiming[0].TimingData.NMode); + XmpChannel[0].XmpProfileTiming[1].TimingData.NMode = MAX(XmpDimm[0].XmpProfileTiming[1].TimingData.NMode, XmpDimm[1].XmpProfileTiming[1].TimingData.NMode); + + // Channel 1 XmpProfile 1~2 + XmpChannel[1].XmpProfileTiming[0].DDRFreq = MAX(XmpDimm[2].XmpProfileTiming[0].DDRFreq, XmpDimm[3].XmpProfileTiming[0].DDRFreq); + XmpChannel[1].XmpProfileTiming[1].DDRFreq = MAX(XmpDimm[2].XmpProfileTiming[1].DDRFreq, XmpDimm[3].XmpProfileTiming[1].DDRFreq); + XmpChannel[1].XmpProfileTiming[0].TimingData.tCL = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tCL, XmpDimm[3].XmpProfileTiming[0].TimingData.tCL); + XmpChannel[1].XmpProfileTiming[1].TimingData.tCL = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tCL, XmpDimm[3].XmpProfileTiming[1].TimingData.tCL); + XmpChannel[1].XmpProfileTiming[0].TimingData.tCWL = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tCWL, XmpDimm[3].XmpProfileTiming[0].TimingData.tCWL); + XmpChannel[1].XmpProfileTiming[1].TimingData.tCWL = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tCWL, XmpDimm[3].XmpProfileTiming[1].TimingData.tCWL); + XmpChannel[1].XmpProfileTiming[0].TimingData.tWR = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tWR, XmpDimm[3].XmpProfileTiming[0].TimingData.tWR); + XmpChannel[1].XmpProfileTiming[1].TimingData.tWR = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tWR, XmpDimm[3].XmpProfileTiming[1].TimingData.tWR); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRRD = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRRD, XmpDimm[3].XmpProfileTiming[0].TimingData.tRRD); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRRD = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRRD, XmpDimm[3].XmpProfileTiming[1].TimingData.tRRD); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRCD = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRCD, XmpDimm[3].XmpProfileTiming[0].TimingData.tRCD); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRCD = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRCD, XmpDimm[3].XmpProfileTiming[1].TimingData.tRCD); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRP = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRP, XmpDimm[3].XmpProfileTiming[0].TimingData.tRP); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRP = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRP, XmpDimm[3].XmpProfileTiming[1].TimingData.tRP); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRAS = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRAS, XmpDimm[3].XmpProfileTiming[0].TimingData.tRAS); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRAS = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRAS, XmpDimm[3].XmpProfileTiming[1].TimingData.tRAS); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRFC = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRFC, XmpDimm[3].XmpProfileTiming[0].TimingData.tRFC); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRFC = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRFC, XmpDimm[3].XmpProfileTiming[1].TimingData.tRFC); + XmpChannel[1].XmpProfileTiming[0].TimingData.tWTR = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tWTR, XmpDimm[3].XmpProfileTiming[0].TimingData.tWTR); + XmpChannel[1].XmpProfileTiming[1].TimingData.tWTR = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tWTR, XmpDimm[3].XmpProfileTiming[1].TimingData.tWTR); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRTP = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRTP, XmpDimm[3].XmpProfileTiming[0].TimingData.tRTP); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRTP = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRTP, XmpDimm[3].XmpProfileTiming[1].TimingData.tRTP); + XmpChannel[1].XmpProfileTiming[0].TimingData.tFAW = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRC, XmpDimm[3].XmpProfileTiming[0].TimingData.tFAW); + XmpChannel[1].XmpProfileTiming[1].TimingData.tFAW = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRC, XmpDimm[3].XmpProfileTiming[1].TimingData.tFAW); + XmpChannel[1].XmpProfileTiming[0].TimingData.tREFI = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tREFI, XmpDimm[3].XmpProfileTiming[0].TimingData.tREFI); + XmpChannel[1].XmpProfileTiming[1].TimingData.tREFI = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tREFI, XmpDimm[3].XmpProfileTiming[1].TimingData.tREFI); + XmpChannel[1].XmpProfileTiming[0].TimingData.tRC = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.tRC, XmpDimm[3].XmpProfileTiming[0].TimingData.tRC); + XmpChannel[1].XmpProfileTiming[1].TimingData.tRC = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.tRC, XmpDimm[3].XmpProfileTiming[1].TimingData.tRC); + XmpChannel[1].XmpProfileTiming[0].TimingData.NMode = MAX(XmpDimm[2].XmpProfileTiming[0].TimingData.NMode, XmpDimm[3].XmpProfileTiming[0].TimingData.NMode); + XmpChannel[1].XmpProfileTiming[1].TimingData.NMode = MAX(XmpDimm[2].XmpProfileTiming[1].TimingData.NMode, XmpDimm[3].XmpProfileTiming[1].TimingData.NMode); + + // Output XmpProfile 1~2 + XmpProfileTiming[0].DDRFreq = MAX(XmpChannel[0].XmpProfileTiming[0].DDRFreq, XmpChannel[1].XmpProfileTiming[0].DDRFreq); + XmpProfileTiming[1].DDRFreq = MAX(XmpChannel[0].XmpProfileTiming[1].DDRFreq, XmpChannel[1].XmpProfileTiming[1].DDRFreq); + XmpProfileTiming[0].TimingData.tCL = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tCL, XmpChannel[1].XmpProfileTiming[0].TimingData.tCL); + XmpProfileTiming[1].TimingData.tCL = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tCL, XmpChannel[1].XmpProfileTiming[1].TimingData.tCL); + XmpProfileTiming[0].TimingData.tCWL = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tCWL, XmpChannel[1].XmpProfileTiming[0].TimingData.tCWL); + XmpProfileTiming[1].TimingData.tCWL = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tCWL, XmpChannel[1].XmpProfileTiming[1].TimingData.tCWL); + XmpProfileTiming[0].TimingData.tWR = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tWR, XmpChannel[1].XmpProfileTiming[0].TimingData.tWR); + XmpProfileTiming[1].TimingData.tWR = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tWR, XmpChannel[1].XmpProfileTiming[1].TimingData.tWR); + XmpProfileTiming[0].TimingData.tRRD = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRRD, XmpChannel[1].XmpProfileTiming[0].TimingData.tRRD); + XmpProfileTiming[1].TimingData.tRRD = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRRD, XmpChannel[1].XmpProfileTiming[1].TimingData.tRRD); + XmpProfileTiming[0].TimingData.tRCD = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRCD, XmpChannel[1].XmpProfileTiming[0].TimingData.tRCD); + XmpProfileTiming[1].TimingData.tRCD = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRCD, XmpChannel[1].XmpProfileTiming[1].TimingData.tRCD); + XmpProfileTiming[0].TimingData.tRP = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRP, XmpChannel[1].XmpProfileTiming[0].TimingData.tRP); + XmpProfileTiming[1].TimingData.tRP = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRP, XmpChannel[1].XmpProfileTiming[1].TimingData.tRP); + XmpProfileTiming[0].TimingData.tRAS = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRAS, XmpChannel[1].XmpProfileTiming[0].TimingData.tRAS); + XmpProfileTiming[1].TimingData.tRAS = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRAS, XmpChannel[1].XmpProfileTiming[1].TimingData.tRAS); + XmpProfileTiming[0].TimingData.tRFC = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRFC, XmpChannel[1].XmpProfileTiming[0].TimingData.tRFC); + XmpProfileTiming[1].TimingData.tRFC = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRFC, XmpChannel[1].XmpProfileTiming[1].TimingData.tRFC); + XmpProfileTiming[0].TimingData.tWTR = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tWTR, XmpChannel[1].XmpProfileTiming[0].TimingData.tWTR); + XmpProfileTiming[1].TimingData.tWTR = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tWTR, XmpChannel[1].XmpProfileTiming[1].TimingData.tWTR); + XmpProfileTiming[0].TimingData.tRTP = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRTP, XmpChannel[1].XmpProfileTiming[0].TimingData.tRTP); + XmpProfileTiming[1].TimingData.tRTP = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRTP, XmpChannel[1].XmpProfileTiming[1].TimingData.tRTP); + XmpProfileTiming[0].TimingData.tFAW = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tFAW, XmpChannel[1].XmpProfileTiming[0].TimingData.tFAW); + XmpProfileTiming[1].TimingData.tFAW = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tFAW, XmpChannel[1].XmpProfileTiming[1].TimingData.tFAW); + XmpProfileTiming[0].TimingData.tREFI = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tREFI, XmpChannel[1].XmpProfileTiming[0].TimingData.tREFI); + XmpProfileTiming[1].TimingData.tREFI = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tREFI, XmpChannel[1].XmpProfileTiming[1].TimingData.tREFI); + XmpProfileTiming[0].TimingData.tRC = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.tRC, XmpChannel[1].XmpProfileTiming[0].TimingData.tRC); + XmpProfileTiming[1].TimingData.tRC = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.tRC, XmpChannel[1].XmpProfileTiming[1].TimingData.tRC); + XmpProfileTiming[0].TimingData.NMode = MAX(XmpChannel[0].XmpProfileTiming[0].TimingData.NMode, XmpChannel[1].XmpProfileTiming[0].TimingData.NMode); + XmpProfileTiming[1].TimingData.NMode = MAX(XmpChannel[0].XmpProfileTiming[1].TimingData.NMode, XmpChannel[1].XmpProfileTiming[1].TimingData.NMode); +#endif +#endif + + Status = pRS->SetVariable ( + L"NBPlatformData", + &gSetupGuid, + EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS, + sizeof (NB_PLATFORM_DATA), + &NBPlatformData + ); + ASSERT_EFI_ERROR (Status); + + // Kill event + pBS->CloseEvent(Event); +*/ + return EFI_SUCCESS; +} +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBGeneric.c b/Chipset/NB/NBGeneric.c new file mode 100644 index 0000000..6f9a95f --- /dev/null +++ b/Chipset/NB/NBGeneric.c @@ -0,0 +1,1782 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBGeneric.c 6 10/14/12 5:17a Jeffch $ +// +// $Revision: 6 $ +// +// $Date: 10/14/12 5:17a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBGeneric.c $ +// +// 6 10/14/12 5:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c +// +// 5 10/14/12 12:20a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update by XTU4.0. +// [Files] NBPei.c, NBDxe.c, NBCspLib.h, NBGeneric.c +// +// 4 9/12/12 6:20a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Fixed some pcie card compatibility issue. <from Jeffch> +// [Files] NBGeneric.c +// +// 3 8/24/12 8:09a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Remove useless SB_SHADOW_CONTROL. +// [Files] NBGeneric.c +// +// 2 4/05/12 2:45a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.5.5 . +// [Files] NBDxe.c, NBPEI.c, NBSMI.C, NBGeneric.cm NB.sd, NBSetup.c, +// GetSetupData.c, NbSetupData. +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBGeneric.C +// +// Description: This file contains generic NB code that is common between +// various components such as NB PEI, DXE etc +// +// Notes: MAKE SURE NO PEI OR DXE SPECIFIC CODE IS NEEDED +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <token.h> +#include <AmiLib.h> +#include <AmiCspLib.h> +#include <AmiDxeLib.h> +#include <Protocol\PciRootBridgeIo.h> + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) +//--------------------EMRR Support-------------------------------------------- +#define MAX_NR_BUS ((PCIEX_LENGTH/0x100000)-1) +#define UNCORE_CR_MCSEG_BASE0 (volatile UINT64*)NB_PCIE_CFG_ADDRESS(MAX_NR_BUS, 0, 1, 0x60) +#define UNCORE_CR_MCSEG_MASK0_LOW (volatile UINT32*)NB_PCIE_CFG_ADDRESS(MAX_NR_BUS, 0, 1, 0x68) +#define UNCORE_CR_MCSEG_MASK0_HIGH (volatile UINT32*)NB_PCIE_CFG_ADDRESS(MAX_NR_BUS, 0, 1, 0x6C) +#define UNCORE_CR_MCSEG_BASE1 (volatile UINT64*)NB_PCIE_CFG_ADDRESS((MAX_NR_BUS - 1), 0, 1, 0x60) +#define UNCORE_CR_MCSEG_MASK1_LOW (volatile UINT32*)NB_PCIE_CFG_ADDRESS((MAX_NR_BUS - 1), 0, 1, 0x68) +#define UNCORE_CR_MCSEG_MASK1_HIGH (volatile UINT32*)NB_PCIE_CFG_ADDRESS((MAX_NR_BUS - 1), 0, 1, 0x6C) +//---------------------------------------------------------------------------- + +#if CSM_SUPPORT +#define ATTR_DISABLED 0 // Shadow RAM Disabled +#define ATTR_READ 1 // Shadow RAM Read Enabled +#define ATTR_WRITE 2 // Shadow RAM Write Enabled +#define ATTR_READ_WRITE 3 // Shadow RAM Read/Write Enabled +#endif + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; + +EFI_RUNTIME_SERVICES *pRS; + +//---------------------------------------------------------------------------- +// The following table contains the information regarding the shadow RAM +// registers and other North Bridge registers that need to be restored +// during the S3 wakeup. +// Mention all register address (bus, device, function , register), specify +// the size of the register ans the mask also. +//---------------------------------------------------------------------------- +BOOT_SCRIPT_NB_PCI_REG_SAVE gNbRegsSaveTbl[] = { + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM0, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM1, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM2, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM3, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM4, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM5, EfiBootScriptWidthUint8, 0x33}, + {SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PAM6, EfiBootScriptWidthUint8, 0x33}, + // {SAD_BUS, SAD_DEV, SAD_FUN, SAD_REG_SMRAM, EfiBootScriptWidthUint8, 0xff}, +}; + +#define NUM_NB_PCI_REG_SAVE \ + sizeof(gNbRegsSaveTbl)/sizeof(BOOT_SCRIPT_NB_PCI_REG_SAVE) + +#if CSM_SUPPORT + +/** Porting required for the following structure **/ +NB_PAM_STRUCT gPamStruct[] = +{ + {R_SA_PAM1, 0xfc, 0xc0000, 0x4000}, + {R_SA_PAM1, 0xcf, 0xc4000, 0x4000}, + {R_SA_PAM2, 0xfc, 0xc8000, 0x4000}, + {R_SA_PAM2, 0xcf, 0xcc000, 0x4000}, + {R_SA_PAM3, 0xfc, 0xd0000, 0x4000}, + {R_SA_PAM3, 0xcf, 0xd4000, 0x4000}, + {R_SA_PAM4, 0xfc, 0xd8000, 0x4000}, + {R_SA_PAM4, 0xcf, 0xdc000, 0x4000}, + {R_SA_PAM5, 0xfc, 0xe0000, 0x4000}, + {R_SA_PAM5, 0xcf, 0xe4000, 0x4000}, + {R_SA_PAM6, 0xfc, 0xe8000, 0x4000}, + {R_SA_PAM6, 0xcf, 0xec000, 0x4000}, + {R_SA_PAM0, 0xcf, 0xf0000,0x10000} +}; + +#define NUM_PAM_ENTRIES (sizeof(gPamStruct) / sizeof(NB_PAM_STRUCT)) + +//---------------------------------------------------------------------------- +// Start OF CSM Related Porting Hooks +//---------------------------------------------------------------------------- + +// The following data structure specifies the PCI device/function number of +// the root bridge(s). Number of entries in this table defined by +// ROOT_BRIDGE_COUNT. +// This table is a missing link between RootBridgeIo and PciIo, which allows +// to update BusNumXlat table with actual bus numbers. +// Each entry in the table is a pair of RootBridge UID (UINT32), provided in +// RootBridge device path, and PCI Dev/Func number (UINT8) that can be used +// to access Root Bridge on +// PCI bus. + +// PORTING PORTING - Include device function number of RB + +ROOT_BRIDGE_MAPPING_ENTRY RbMap[ROOT_BRIDGE_COUNT] = { +// RB ID Device function number + {0x00, (UINT8)((NB_DEV << 3) + NB_FUN)} +}; +UINTN RbCount = ROOT_BRIDGE_COUNT; + +#endif +/* +typedef enum { + fNoInit = 0, + f800 = 800, + f1000 = 1000, + f1067 = 1067, + f1200 = 1200, + f1333 = 1333, + f1400 = 1400, + f1600 = 1600, + f1800 = 1800, + f1867 = 1867, + f2000 = 2000, + f2133 = 2133, + f2200 = 2200, + f2400 = 2400, + f2600 = 2600, + f2667 = 2667, + fUnSupport= 0x7FFFFFFF +} NbFrequency; +*/ +#define BCLK_DEFAULT (100 * 1000 * 1000) +#define fNoInit (0) +#define f800 (800) +#define f1000 (1000) +#define f1067 (1067) +#define f1200 (1200) +#define f1333 (1333) +#define f1400 (1400) +#define f1600 (1600) +#define f1800 (1800) +#define f1867 (1867) +#define f2000 (2000) +#define f2133 (2133) +#define f2200 (2200) +#define f2400 (2400) +#define f2600 (2600) +#define f2667 (2667) +#define fUnSupport (0x7FFFFFFF) +typedef UINT32 NbFrequency; +typedef UINT8 NbClockRatio; + +// GUID Definition(s) + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbFrequencyToRatio +// +// Description: Convert the given frequency and reference clock to a clock ratio. +// +// Input: +// IN Frequency - The memory frequency. +// IN The memory reference clock. +// IN RefBClk - The base system reference clock. +// +// Output: +// Returns the memory clock ratio. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +NbFrequencyToRatio ( + UINT32 Frequency, + UINT8 RefClk, + UINT32 RefBClk +) +{ + UINT64 Value; + UINT64 FreqValue; + UINT32 RefClkValue; + UINT32 BClkValue; + + BClkValue = (RefBClk == 0) ? (BCLK_DEFAULT / 100000) : (RefBClk / 100000); + RefClkValue = (RefClk == 1) ? 200000 : 266667; + FreqValue = Mul64 (Frequency, 1000000000ULL); + Value = Div64 (FreqValue, (RefClkValue * BClkValue), NULL); + Value = ((UINT32) Value + 500) / 1000; + + return ((NbClockRatio) Value); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbRatioToFrequency +// +// Description: Convert the given ratio and reference clock to a memory frequency. +// +// Input: +// IN Ratio - The memory ratio. +// IN RefClk - The memory reference clock. +// IN RefBClk - The base system reference clock. +// +// Output: +// Returns the memory frequency. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 +NbRatioToFrequency ( + UINT8 Ratio, + UINT8 RefClk, + UINT32 RefBClk +) +{ + + UINT64 Value; + UINT32 BClkValue; + UINT32 RefClkValue; + + BClkValue = (RefBClk == 0) ? BCLK_DEFAULT : RefBClk; + RefClkValue = (RefClk == 1) ? 200000000 : 266666667; + Value = Mul64 (RefClkValue, Ratio * BClkValue); + Value += 50000000000000ULL; + Value = Div64 (Value, (UINTN)100000000000000ULL, NULL); + return ((NbFrequency) Value); +} +//---------------------------------------------------------------------------- +#if CSM_SUPPORT + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NBGetPamStartEndIndex +// +// Description: Helper function to get the Start and End Index for +// PAM register table. +// +// Input: StartAddress - Shadow RAM start address to be programed +// Length - Shadow RAM length to be programed +// *StartIndex - Pointer a variable for the Start index +// *EndIndex - Pointer a variable for the End index +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Input Parameter is invalid. +// EFI_SUCCESS - Get indexs from PAM register +// table successfully. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBGetPamStartEndIndex ( + IN UINT32 StartAddress, + IN UINT32 Length, + OUT UINT32 *StartIndex, + OUT UINT32 *EndIndex ) +{ + UINT32 StartIdx; + UINT32 EndIdx; + UINT32 TotalLength = 0; + + if (StartAddress < gPamStruct[0].StartAddress) + return EFI_INVALID_PARAMETER; + + for(StartIdx = 0; StartIdx < NUM_PAM_ENTRIES; ++StartIdx) { + if (StartAddress <= gPamStruct[StartIdx].StartAddress) break; + } + if (StartAddress < gPamStruct[StartIdx].StartAddress) StartIdx--; + + if (StartIdx == NUM_PAM_ENTRIES) return EFI_INVALID_PARAMETER; + + // Adjust the length of the requested region if starting address is + // out of bounds. + Length += (StartAddress - gPamStruct[StartIdx].StartAddress); + + for(EndIdx = StartIdx; EndIdx < NUM_PAM_ENTRIES; ++EndIdx) { + TotalLength += gPamStruct[EndIdx].Length; + if (TotalLength >= Length) break; + } + if (EndIdx == NUM_PAM_ENTRIES) return EFI_INVALID_PARAMETER; + + *StartIndex = StartIdx; + *EndIndex = EndIdx; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBProgramPAMRegisters +// +// Description: Program 0xc0000 - 0xfffff regions to Lock/Unlock. +// +// Input: pBS - Pointer to Boot Service Table +// pRS - Pointer to Runtime Service Table +// StartAddress - Shadow RAM start address to be programed +// Length - Shadow RAM length to be programed +// Setting - Shadow RAM Lock/Unlock status to program +// *Granularity - The granularity for this region +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Input Parameter is invalid. +// EFI_SUCCESS - Program successfully. +// +// Notes: Here is the control flow of this function: +// 1. Search the structure for the first entry matching +// the StartAddress. +// 2. If not found, return EFI_INVALID_PARAMETER. +// 3. Find the last entry in structure for the region to program, +// by adding the lengths of the entries. +// 4. If not found, return EFI_INVALID_PARAMETER. +// 5. Read/Write each register for the entry to set region. +// 6. Return the Granularity for the region. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBProgramPAMRegisters ( + IN EFI_BOOT_SERVICES *pBS, + IN EFI_RUNTIME_SERVICES *pRS, + IN UINT32 StartAddress, + IN UINT32 Length, + IN UINT8 Setting, + IN OUT UINT32 *Granularity ) +{ + // NB shadow programming. + // Note: For this routine to work, the gPamStruct regions must + // be continuous. + + EFI_STATUS Status = EFI_SUCCESS; + UINT32 StartIndex; + UINT32 EndIndex; + UINTN i; + UINT8 Data; + UINT8 Shift; + + Status = NBGetPamStartEndIndex( StartAddress, \ + Length, \ + &StartIndex, \ + &EndIndex ); + if (EFI_ERROR(Status)) return Status; + + + for (i = StartIndex; i <= EndIndex; ++i) { + //Bus 0, Device 0, Function 0 + Data = READ_PCI8_NB(gPamStruct[i].Register); + Data &= gPamStruct[i].Mask; + Shift = (gPamStruct[i].Mask == 0xfc) ? 0 : 4; + switch (Setting) { + case 0 : // Read Only + case 1 : // Read Only (Permanently) + Data |= (ATTR_READ << Shift); + break; + case 2 : // Read/Write + Data |= (ATTR_READ_WRITE << Shift); + break; + case 3 : // Disabled + default: + break; + } + WRITE_PCI8_NB(gPamStruct[i].Register, Data); + } + + if (Granularity) + *Granularity = ( (StartAddress+Length) < 0xf0000 ) ? 0x4000 : 0x10000; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPeiProgramPAMRegisters +// +// Description: Program 0xc0000 - 0xfffff regions to Lock/Unlock. +// +// Input: PeiServices - The PEI core services table. +// StartAddress - Shadow RAM start address to be programed +// Length - Shadow RAM length to be programed +// Setting - Shadow RAM Lock/Unlock status to program +// *Granularity - The granularity for this region +// +// Output: EFI_STATUS +// EFI_INVALID_PARAMETER - Input Parameter is invalid. +// EFI_SUCCESS - Program successfully. +// +// Notes: Here is the control flow of this function: +// 1. Search the structure for the first entry matching +// the StartAddress. +// 2. If not found, return EFI_INVALID_PARAMETER. +// 3. Find the last entry in structure for the region to program, +// by adding the lengths of the entries. +// 4. If not found, return EFI_INVALID_PARAMETER. +// 5. Read/Write each register for the entry to set region. +// 6. Return the Granularity for the region. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBPeiProgramPAMRegisters ( + IN EFI_PEI_SERVICES **PeiServices, + IN UINT32 StartAddress, + IN UINT32 Length, + IN UINT8 Setting, + IN OUT UINT32 *Granularity OPTIONAL ) +{ + // NB shadow programming. + // Note: For this routine to work, the gPamStruct regions must + // be continuous. + + EFI_STATUS Status = EFI_SUCCESS; + UINT32 StartIndex; + UINT32 EndIndex; + UINTN i; + UINT8 Data; + UINT8 Shift; + + Status = NBGetPamStartEndIndex( StartAddress, \ + Length, \ + &StartIndex, \ + &EndIndex ); + if (EFI_ERROR(Status)) return Status; + + + for (i = StartIndex; i <= EndIndex; ++i) { + //Bus 0, Device 0, Function 0 + Data = READ_PCI8_NB(gPamStruct[i].Register); + Data &= gPamStruct[i].Mask; + Shift = (gPamStruct[i].Mask == 0xfc) ? 0 : 4; + switch (Setting) { + case 0 : // Read Only + case 1 : // Read Only (Permanently) + Data |= (ATTR_READ << Shift); + break; + case 2 : // Read/Write + Data |= (ATTR_READ_WRITE << Shift); + break; + case 3 : // Disabled + default: + break; + } + WRITE_PCI8_NB(gPamStruct[i].Register, Data); + } + + if (Granularity) + *Granularity = ( (StartAddress+Length) < 0xf0000 ) ? 0x4000 : 0x10000; + + return EFI_SUCCESS; +} + +//---------------------------------------------------------------------------- +#endif // END OF CSM Related Porting Hooks +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPAMWriteBootScript +// +// Description: Writes the final settings of NB registers to the BOOT Script +// +// Input: *BootScriptSave - Pointer to Boot Script Save Protocal +// +// Output: EFI_STATUS +// EFI_SUCCESS +// +// Notes: Here is the control flow of this function: +// 1. From the Pci register save table, read the pci register +// to save. +// 2. Write to the boot script the value. +// 3. Repeat 1 & 2 for all table entries. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBPAMWriteBootScript ( + IN AMI_S3_SAVE_PROTOCOL *BootScriptSave ) +{ + UINT8 PciBus8; + UINT8 PciSubBus8; + UINTN i; + UINT32 Value32; + UINT64 Address64; + + //Porting required: Write Boot Script + + for (i = 0; i < NUM_NB_PCI_REG_SAVE; ++i) { + Address64 = NB_PCI_CFG_ADDRESS( gNbRegsSaveTbl[i].Bus, \ + gNbRegsSaveTbl[i].Dev, \ + gNbRegsSaveTbl[i].Fun, \ + gNbRegsSaveTbl[i].Reg ); + gPciRootBridgeIo->Pci.Read( gPciRootBridgeIo, \ + gNbRegsSaveTbl[i].Width, \ + Address64, \ + 1, \ + &Value32 ); + Value32 &= gNbRegsSaveTbl[i].Mask; + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( BootScriptSave, \ + gNbRegsSaveTbl[i].Width, \ + Address64, \ + 1, \ + &Value32 ); + } + + PciBus8 = READ_PCI8_PCIEBRN(PCIEBRN_REG_SBUSN); // 0x19 + // Check nVIDIA PCIe VGA card + if (READ_PCI16(PciBus8, 0, 0, PCI_VID) == 0x10de) { + Value32 = READ_PCI32(PciBus8, 0, 0, PCI_SVID); // 0x2c + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + BootScriptSave, \ + EfiBootScriptWidthUint8, \ + PCIEBRN_REG(PCIEBRN_REG_SBUSN), \ + 1, \ + &PciBus8 ); + PciSubBus8 = READ_PCI8_PCIEBRN(PCIEBRN_REG_SUBUSN); // 0x1a + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + BootScriptSave, \ + EfiBootScriptWidthUint8, \ + PCIEBRN_REG(PCIEBRN_REG_SUBUSN), \ + 1, \ + &PciSubBus8 ); + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + BootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCI_CFG_ADDRESS(PciBus8, 0 ,0, 0x40),\ + 1, \ + &Value32 ); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbFindCapPtr +// +// Description: This function searches the PCI address space for the PCI +// device specified for a particular capability ID and returns +// the offset in the PCI address space if one found +// +// Input: UINT64 PciAddress, +// UINT8 CapId +// +// Output: Capability ID Address if one found +// Otherwise returns 0 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT32 NbFindCapPtr( + IN UINT64 PciAddress, + IN UINT8 CapId +) +{ + UINT8 Value; + UINT32 Address = (UINT32)PciAddress; + + Address = (Address & 0xffffff00) | 6; //PCI Status Register. + Value = READ_MEM8(Address + 0); + + if (Value == 0xff) return 0; // No device. + if (!(Value & (1 << 4))) return 0; // Check if capabilities list. + + *(UINT8*)&Address = 0x34; // Register to First capabilities pointer + // if 0, then capabilities + for(;;) + { + Value = READ_MEM8(Address + 0); + if (Value == 0) return 0; + + *(UINT8*)&Address = Value; // PciAddress = ptr to CapID + Value = READ_MEM8(Address + 0); // New cap ptr. + + //If capablity ID, return register that points to it. + if (Value == CapId) return Address; + + ++Address; // Equals to next capability pointer. + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBRetrainLinkPciDevice +// +// Description: This function is Retrain Link NB Pci Device. +// +// Input: PciBus - PCI Bus Number. +// PciDev - PCI Device Number. +// PciFun - PCI Function Number. +// PciCapPtr - PCI CapPtr Number. +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NBRetrainLinkPciDevice ( + IN UINT8 PciBus, + IN UINT8 PciDev, + IN UINT8 PciFun, + IN UINT8 CapPtr ) +{ + // Disable Link + SET_PCI8(PciBus, PciDev, PciFun, CapPtr + 0x10, BIT04); + + // Retrain Link + RW_PCI8(PciBus, PciDev, PciFun, CapPtr + 0x10 , BIT05, BIT04); + + // Wait Link States + while (READ_PCI16(PciBus, PciDev, PciFun, CapPtr + 0x12) & BIT11); + + // if Retrain Link Anyway 1, Clear Retrain Link + if (READ_PCI8(PciBus, PciDev, PciFun, CapPtr + 0x10) & BIT05) { + RESET_PCI8(PciBus, PciDev, PciFun, CapPtr + 0x10 , BIT05); + } + + // Wait Link States + while (READ_PCI16(PciBus, PciDev, PciFun, CapPtr + 0x12) & BIT11); +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBProtectedPciDevice +// +// Description: This function is called by PCI Bus Driver before configuring +// or disabling any PCI device. This function should examine the +// Vendor/Device ID or PCI Bus, Device and Function numbers to +// make sure it is not a north bridge device or any other device +// which should no be configured by PCI Bus Driver. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// +// Output: EFI_STATUS +// EFI_SUCCESS - SKIP this device, do not touch +// PCI Command register. +// EFI_UNSUPPORTED - DON'T SKIP this device do complete +// enumeration as usual. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBProtectedPciDevice ( + IN PCI_DEV_INFO *PciDevice ) +{ + +//####if ((PciDevice->Address.Addr.Bus == NB_BUS) && \ +//#### (PciDevice->Address.Addr.Device == NB_DEV) && \ +//#### (PciDevice->Address.Addr.Function == NB_FUN)) { +//#### +//#### return EFI_SUCCESS; +//####} + + return EFI_UNSUPPORTED; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBProgramPciDevice +// +// Description: This function is called by PCI Bus Driver before installing +// Protocol Interface for the input device. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// +// Output: EFI_SUCCESS +// +// Notes: All resource in the device had been assigned, but the command +// register is disabled. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBProgramPciDevice ( + IN PCI_DEV_INFO *PciDevice ) +{ + +//####if ((PciDevice->Address.Addr.Bus == NB_BUS) && \ +//#### (PciDevice->Address.Addr.Device == NB_DEV) && \ +//#### (PciDevice->Address.Addr.Function == NB_FUN)) { +//#### // Do any porting if needed. +//####} + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBUpdatePciDeviceAttributes +// +// Description: This function is called by PCI Bus Driver, can be used to +// the attributes of the PCI device. +// +// Input: *PciDevice - Pointer to PCI Device Info structure. +// *Attributes - Attributes bitmask which caller whants to +// change. +// Capabilities - The PCI device supports Capabilityes +// Set - Specifies weathere to set or reset given +// "Attributes". +// +// Output: EFI_SUCCESS +// +// Notes: This routine may be invoked twice depend on the device type, +// the first time is at BDS phase, the second is before +// legacy boot. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBUpdatePciDeviceAttributes ( + IN PCI_DEV_INFO *PciDevice, + IN OUT UINT64 *Attributes, + IN UINT64 Capabilities, + IN BOOLEAN Set ) +{ + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBGetTsegBase +// +// Description: Returns the base address of TSEG. +// +// Input: None +// +// Output: UINT32 - The Base Address of TSEG. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 NBGetTsegBase (VOID) +{ + return (READ_PCI32_NB(0xB8) & 0xFFF00000); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBEnableEmrr +// +// Description: Enable and lock CPU EMRR. +// +// Input: UINT32 IedStart - Intel Enhanced Debug start. +// UINT32 IedSize - Intel Enhanced Debug size. +// +// Output: VOID +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NBEnableEmrr( + IN UINT32 IedStart, + IN UINT32 IedSize +) +{ + if ((*UNCORE_CR_MCSEG_MASK0_LOW & (1 << 11)) == 0 ) { + *UNCORE_CR_MCSEG_BASE0 = (UINT32)IedStart + 0x200000; + *UNCORE_CR_MCSEG_MASK0_LOW = 0xffe00000; + *UNCORE_CR_MCSEG_MASK0_HIGH = 0xff; + *UNCORE_CR_MCSEG_MASK0_LOW |= (1 << 11); //Enable bit. + *UNCORE_CR_MCSEG_MASK0_LOW |= (1 << 10); //Lock bit. + } + + if ((*UNCORE_CR_MCSEG_MASK1_LOW & (1 << 11)) == 0 ) { + *UNCORE_CR_MCSEG_BASE1 = (UINT32)IedStart + 0x300000; + *UNCORE_CR_MCSEG_MASK1_LOW = 0xffe00000; + *UNCORE_CR_MCSEG_MASK1_HIGH = 0xff; + *UNCORE_CR_MCSEG_MASK1_LOW |= (1 << 11); //Enable bit. + *UNCORE_CR_MCSEG_MASK1_LOW |= (1 << 10); //Lock bit. + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbRuntimeShadowRamWrite +// +// Description: This function provides runtime interface to enable/disable +// writing in E000-F000 segment +// +// Input: IN BOOLEAN Enable - if TRUE - enable writing, if FALSE - disable +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbRuntimeShadowRamWrite( + IN BOOLEAN Enable +) +{ + // Porting Required. + static UINT8 F000Reg = 0xff; // 0x80 + static UINT8 E000Reg = 0xff; // 0x85 + static UINT8 E800Reg = 0xff; // 0x86 + + if (Enable) { + F000Reg = READ_PCI8_NB(R_SA_PAM0); // 0x80 + SET_PCI8_NB(R_SA_PAM0, 0x30); + + E000Reg = READ_PCI8_NB(R_SA_PAM5); // 0x85 + E800Reg = READ_PCI8_NB(R_SA_PAM6); // 0x86 + SET_PCI8_NB(R_SA_PAM5, 0x33); + SET_PCI8_NB(R_SA_PAM6, 0x33); + } else { + if (F000Reg != 0xff) { + WRITE_PCI8_NB(R_SA_PAM0, F000Reg); // 0x80 + WRITE_PCI8_NB(R_SA_PAM5, E000Reg); // 0x85 + WRITE_PCI8_NB(R_SA_PAM6, E800Reg); // 0x86 + } + } + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: CheckPeiFvCopyToRam +// +// Description: Check system is cold or warm boot +// +// Input: PeiServices - The PEI core services table. +// +// Output: PeiFvCopyToRam - TRUE for cold boot. +// - FALSE for warm boot. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN +CheckPeiFvCopyToRam ( + IN EFI_PEI_SERVICES **PeiServices +) +{ + + UINT16 Buff16; + BOOLEAN PeiFvCopyToRam; + + + Buff16 = READ_PCI16_SB(0xA2); + + if (((Buff16 & BIT5) != 0) && ((Buff16 & BIT7) != 0)) + { + PeiFvCopyToRam = FALSE; + + } else { + + PeiFvCopyToRam = TRUE; + } + + if (READ_MEM32_MCH(0x5D10) == 0)PeiFvCopyToRam = TRUE; + + return PeiFvCopyToRam; + +} + +//---------------------------------------------------------------------------- +// Standard PCI Access Routines, No Porting Required. +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadPci8 +// +// Description: This function reads an 8bits data from the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// +// Output: UINT8 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT8 ReadPci8 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg ) +{ + if (Reg >= 0x100) { + return MMIO_READ8(NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg)); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + return IoRead8(NB_PCICFG_SPACE_DATA_REG | (UINT8)(Reg & 3)); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadPci16 +// +// Description: This function reads a 16bits data from the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// +// Output: UINT16 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT16 ReadPci16 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg ) +{ + if (Reg >= 0x100) { + return MMIO_READ16(NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg)); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + return IoRead16(NB_PCICFG_SPACE_DATA_REG | (UINT8)(Reg & 2)); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ReadPci32 +// +// Description: This function reads a 32bits data from the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// +// Output: UINT32 +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINT32 ReadPci32 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg ) +{ + if (Reg >= 0x100) { + return MMIO_READ32(NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg)); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + return IoRead32(NB_PCICFG_SPACE_DATA_REG); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci8 +// +// Description: This function writes an 8bits data to the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value8 - An 8 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci8 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 Value8 ) +{ + if (Reg >= 0x100) { + WriteMem8((UINT64)NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), Value8); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + IoWrite8(NB_PCICFG_SPACE_DATA_REG | (UINT8)(Reg & 3), Value8); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci16 +// +// Description: This function writes a 16bits data to the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value16 - A 16 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci16 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 Value16 ) +{ + if (Reg >= 0x100) { + WriteMem16((UINT64)NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), Value16); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + IoWrite16(NB_PCICFG_SPACE_DATA_REG | (UINT8)(Reg & 2), Value16); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci32 +// +// Description: This function writes a 32bits data to the specific PCI +// register. +// +// Input: Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value32 - A 32 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci32 ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 Value32 ) +{ + if (Reg >= 0x100) { + WriteMem32((UINT64)NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), Value32); + } else { + IoWrite32(NB_PCICFG_SPACE_INDEX_REG, \ + BIT31 | (Bus << 16) | (Dev << 11) | (Fun << 8) | (Reg & 0xfc)); + IoWrite32(NB_PCICFG_SPACE_DATA_REG, Value32); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci8S3 +// +// Description: This function writes an 8bits data to the specific PCI +// register and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value8 - An 8 Bits data will be written to the +// specific PCI register and Boot Script. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 Value8 ) +{ + WritePci8(Bus, Dev, Fun, Reg, Value8); + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value8 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci16S3 +// +// Description: This function writes a 16bits data to the specific PCI +// register and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value16 - A 16 Bits data will be written to the +// specific PCI register and Boot Script. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 Value16 ) +{ + + WritePci16(Bus, Dev, Fun, Reg, Value16); + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value16 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WritePci32S3 +// +// Description: This function writes a 32bits data to the specific PCI +// register and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// Value32 - A 32 Bits data will be written to the +// specific PCI register and Boot Script. +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WritePci32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 Value32 ) +{ + + WritePci32(Bus, Dev, Fun, Reg, Value32); + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value32 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + 1, \ + &Value32 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwPci8S3 +// +// Description: This function reads an 8bits data from the specific PCI +// register, applies masks, and writes it back, also writes it +// to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// SetBit8 - Mask of bits to set (1 = Set) +// ResetBit8 - Mask of bits to clear (1 = clear) +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwPci8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + RW_PCI8(Bus, Dev, Fun, Reg, SetBit8, ResetBit8); + + ResetBit8 = ~ResetBit8; + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit8, \ + &ResetBit8 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit8, \ + &ResetBit8 ); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwPci16S3 +// +// Description: This function reads a 16bits data from the specific PCI +// register, applies masks, and writes it back, also writes it +// to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// SetBit16 - Mask of bits to set (1 = Set) +// ResetBit16 - Mask of bits to clear (1 = clear) +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwPci16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 ) +{ + RW_PCI16(Bus, Dev, Fun, Reg, SetBit16, ResetBit16); + + ResetBit16 = ~ResetBit16; + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit16, \ + &ResetBit16 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit16, \ + &ResetBit16 ); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwPci32S3 +// +// Description: This function reads a 32bits data from the specific PCI +// register, applies masks, and writes it back, also writes it +// to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Bus - PCI Bus number. +// Dev - PCI Device number. +// Fun - PCI Function number. +// Reg - PCI Register number. +// SetBit32 - Mask of bits to set (1 = Set) +// ResetBit32 - Mask of bits to clear (1 = clear) +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwPci32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 Reg, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 ) +{ + RW_PCI32(Bus, Dev, Fun, Reg, SetBit32, ResetBit32); + + ResetBit32 = ~ResetBit32; + + if (Reg >= 0x100) + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCIE_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit32, \ + &ResetBit32 ); + else + BOOT_SCRIPT_S3_PCI_CONFIG_READ_WRITE_MACRO( \ + mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + NB_PCI_CFG_ADDRESS(Bus, Dev, Fun, Reg), \ + &SetBit32, \ + &ResetBit32 ); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem8 +// +// Description: This function writes an 8bits data to the specific memory +// (or MMIO) register. +// +// Input: Address - An 64Bits Memory (or MMIO) address +// Value8 - An 8 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem8 ( + IN UINT64 Address, + IN UINT8 Value8 ) +{ + MMIO_WRITE8(Address, Value8); + Value8 = MMIO_READ8(Address); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem16 +// +// Description: This function writes a 16bits data to the specific memory +// (or MMIO) register. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// Value16 - A 16 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem16 ( + IN UINT64 Address, + IN UINT16 Value16 ) +{ + MMIO_WRITE16(Address, Value16); + Value16 = MMIO_READ16(Address); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem32 +// +// Description: This function writes a 32bits data to the specific memory +// (or MMIO) register. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// Value32 - A 32 Bits data will be written to the specific +// PCI register. +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem32 ( + IN UINT64 Address, + IN UINT32 Value32 ) +{ + MMIO_WRITE32(Address, Value32); + Value32 = MMIO_READ32(Address); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem8 +// +// Description: This function reads an 8bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// SetBit8 - Mask of bits to set (1 = Set) +// ResetBit8 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem8 ( + IN UINT64 Address, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + UINT8 Buffer8 = MMIO_READ8(Address) & ~ResetBit8 | SetBit8; + + WriteMem8(Address, Buffer8); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem16 +// +// Description: This function reads a 16bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// SetBit16 - Mask of bits to set (1 = Set) +// ResetBit16 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem16 ( + IN UINT64 Address, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 ) +{ + UINT16 Buffer16 = MMIO_READ16(Address) & ~ResetBit16 | SetBit16; + + WriteMem16(Address, Buffer16); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem32 +// +// Description: This function reads a 32bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back. +// +// Input: Address - A 64Bits Memory (or MMIO) address +// SetBit32 - Mask of bits to set (1 = Set) +// ResetBit32 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem32 ( + IN UINT64 Address, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 ) +{ + UINT32 Buffer32 = MMIO_READ32(Address) & ~ResetBit32 | SetBit32; + + WriteMem32(Address, Buffer32); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem8S3 +// +// Description: This function writes an 8bits data to a specific memory +// (or MMIO) address and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// Value8 - An 8Bits data writes to the address. +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT8 Value8 ) +{ + + WriteMem8(Address, Value8); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + Address, \ + 1, \ + &Value8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem16S3 +// +// Description: This function writes a 16bits data to a specific memory +// (or MMIO) address and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// Value16 - A 16Bits data writes to the address. +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem16S3( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT16 Value16 ) +{ + WriteMem16(Address, Value16); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + Address, \ + 1, \ + &Value16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: WriteMem32S3 +// +// Description: This function writes a 32bits data to a specific memory +// (or MMIO) address and Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// Value32 - A 32Bits data writes to the address. +// +// Output: None. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID WriteMem32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT32 Value32 ) +{ + + WriteMem32(Address, Value32); + + BOOT_SCRIPT_S3_MEM_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + Address, \ + 1, \ + &Value32 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem8S3 +// +// Description: This function reads an 8bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back, also +// writes it to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// SetBit8 - Mask of bits to set (1 = Set) +// ResetBit8 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem8S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT8 SetBit8, + IN UINT8 ResetBit8 ) +{ + RwMem8(Address, SetBit8, ResetBit8); + + ResetBit8 = ~ResetBit8; + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint8, \ + Address, \ + &SetBit8, \ + &ResetBit8 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem16S3 +// +// Description: This function reads a 16bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back, also +// writes it to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// SetBit16 - Mask of bits to set (1 = Set) +// ResetBit16 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem16S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT16 SetBit16, + IN UINT16 ResetBit16 ) +{ + RwMem16(Address, SetBit16, ResetBit16); + + ResetBit16 = ~ResetBit16; + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint16, \ + Address, \ + &SetBit16, \ + &ResetBit16 ); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RwMem32S3 +// +// Description: This function reads a 32bits data from a specific memory +// (or MMIO) address, applies masks, and writes it back, also +// writes it to Boot Script. +// +// Input: *mBootScriptSave - Pointer to Boot Script Save Protocal +// Address - A 64Bits Memory (or MMIO) address +// SetBit32 - Mask of bits to set (1 = Set) +// ResetBit32 - Mask of bits to clear (1 = clear) +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID RwMem32S3 ( + IN AMI_S3_SAVE_PROTOCOL *mBootScriptSave, + IN UINT64 Address, + IN UINT32 SetBit32, + IN UINT32 ResetBit32 ) +{ + RwMem32(Address, SetBit32, ResetBit32); + + ResetBit32 = ~ResetBit32; + BOOT_SCRIPT_S3_MEM_READ_WRITE_MACRO( mBootScriptSave, \ + EfiBootScriptWidthUint32, \ + Address, \ + &SetBit32, \ + &ResetBit32 ); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBPEI.c b/Chipset/NB/NBPEI.c new file mode 100644 index 0000000..52f61f4 --- /dev/null +++ b/Chipset/NB/NBPEI.c @@ -0,0 +1,3039 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBPEI.c 57 5/28/14 3:03a Dennisliu $ +// +// $Revision: 57 $ +// +// $Date: 5/28/14 3:03a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBPEI.c $ +// +// 57 5/28/14 3:03a Dennisliu +// [TAG] EIP161790 +// [Category] Improvement +// [Description] DRAM Init BIT should be set after saving MRC S3 data to +// NVRAM in DXE Phase as Intel suggested. +// [Files] NBPei.c; NBDxe.c; +// +// 56 8/14/13 6:44a Ireneyang +// [TAG] EIP129631 +// [Category] BrugFix +// [Symptom] RBU function is not working +// [Description] 1. The current make file doesn¡¦t build *.hdr file, +// we can use that file to verify RBU function under DOS. +// 2. We could build *.hdr file manually, and also verified +// the RBU function under DOS. But the RBU function is +// not working. +// [Files] MemoryInit.sdl; MemoryInit.c; NBPEI.c; +// +// 55 6/26/13 4:35a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Add new related items into structure. +// [Files] NBPEI.c; +// +// 53 6/03/13 2:04a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Fix some PEG cards can't be detected. +// [Files] NBPEI.c; +// +// 52 5/22/13 6:41a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Add Token SG_GPIO_SUPPORT for GpioSupport. +// [Files] NB.sdl; NBPEI.c; +// +// 51 5/13/13 6:26a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Add PanelPowerEnable for enabling/disabling VDD force +// bit. +// (Required only for early enabling of eDP panel) +// [Files] NBSetup.c; GetSetupData.c; NbSetupData.h; NBPEI.c; +// +// 50 5/09/13 7:20a Ireneyang +// [TAG] EIP119332 +// [Category] BrugFix +// [Symptom] Some PEG Lan Cards on NorthBridge would cause hanging +// issue when waking through them. +// [RootCause] These Lan cards on NorthBridge do not clear PME for Nb's +// slots. Therefore, this causes hanging issue. +// [Solution] Checking if this PEG card is Lan card. If it's, then +// clear PME status. +// [Files] NBPEI.c; +// +// 48 5/09/13 7:08a Ireneyang +// [TAG] EIP118377 +// [Category] BugFix +// [Symptom] System became resuming from S5 when system is resuming +// from S4. +// [Description] Reproducing steps (UEFI OS) +// 1. Boot into USB key, run afudos.exe +// 2. Remove USB key. +// 3. Warm reset and don't press any key. +// 4. Screen will show "Reboot and select proper Boot +// device... +// No boot option" +// 5. Warm reset and press DEL to enter BIOS setup. +// 6. Change "Launch Video OpROM policy" to "UEFI only". +// 7. Save and reset. +// 8. Press DEL key to enter BIOS setup. +// 9. Change "Launch CSM" to "Disable" +// 10. Save and reset,enter OS(UEFI WIN8) +// 11. Open any file and do "Hibernate" to enter inot S4. +// 12. Power on, resuming back from S4 to desktop, the file +// would be disappeared. It looks like it doesn't resume +// back from S4 but S5. +// [RootCause] It's out of variable type for S4 resume. +// [Solution] The variable type should be +// "PreviousMemoryTypeInformation" +// but MemoryTypeInformation. +// [Files] NBPEI.c +// +// 47 4/01/13 11:48p Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Reduce boot time through PEG. +// [Files] NB.mak; NBDxe.c; NBPEI.c; NBPPI.h; Sa.asl; +// PcieComplex.c; GraphicsInit.c; PciExpressInit.c; +// +// 46 3/14/13 1:37a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Fix some PEG card with no VGA can't work normally under +// SG mode. +// [Files] NBPEI.c; +// +// 45 3/07/13 6:14a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Make some default SaPlatformPolicy items flexible. +// Define some SaPlatformPolicy items into NB_SETUP_DATA +// structure. +// [Files] NbSetupData.h; GetSetupData.c; NBPEI.c; +// +// 44 3/07/13 3:53a Ireneyang +// [TAG] None +// [Severity] Improvement +// [Description] Add "Hot only" option for Memory Refresh 2x support to +// meet Intel Spec. +// [Files] NBPEI.c; NB.uni; NB.sd; NbSetupData.h; GetSetupData.c; +// +// 43 3/04/13 3:16a Ireneyang +// [TAG] EIP115090 +// [Category] Improvement +// [Description] Memory data hasn't been cleared after running MRC base +// memory test. +// [Files] NB.sdl; NBPEI.c; +// +// 41 2/09/13 10:23a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 1.1.0 +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; +// +// 40 1/28/13 5:54a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 1.0. +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; +// NB.sd; NB.uni; NBDxeBoard.c +// +// 39 1/21/13 3:55a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Fixed RMT memory type error issue for ULT. +// [Files] NBPei.c; +// +// 38 1/15/13 4:07a Jeffch +// [TAG] None +// [Severity] Bug Fix +// [Description] Changed MRC error report status for SA RC 0.90. +// [Files] NBPei.c; MemoryInit.c; +// +// 37 1/14/13 6:06a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Create setup item for SA RC 0.90. +// [Files] NBPei.c; GetNbSetupData.c NB.sd; NB.uni; +// +// 36 1/10/13 5:57a Jeffch +// +// [TAG] None +// [Severity] Important +// [Description] Create DDR PowerDown and idle counter for setup item. +// [Files] NBPei.c; NB.sd; NB.uni; GetSetupData.c; NbSetupData.h +// +// 35 1/03/13 7:27a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Follow MRC error report status. +// [Files] NBPei.c +// [TAG] None +// [Severity] Improvement +// [Description] Use SG GPIO ULT by token. +// [Files] NBPei.c +// +// 34 12/24/12 2:55a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] added ULT SKU auto disable PEG. +// [Files] NBPei.c; NBDxe.c; NbPlatform.h; NB.sd; +// [TAG] None +// [Category] Bug Fix +// [Description] Remove tRPab and fixed XTU build fail issue. +// [Files] NBPei.c; NBDxe.c; NB.sd; +// +// 33 12/22/12 2:26a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Create setup item for SA RC 0.81. +// [Files] NBPei.c; GetNbSetupData.c NB.sd; NB.uni; +// [TAG] None +// [Severity] Bug Fix +// [Description] Fxied XTU MRC Timing bug. +// [Files] NBPei.c; +// +// 32 12/18/12 5:14a Jeffch +// [TAG] None +// [Severity] Spec update +// [Description] Update SA RC 0.81. +// [Files] NBDxe.c; NBPei.c +// +// 31 12/03/12 5:56a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] optimize DetectNonComplaint function. +// [Description] NBPEI.c, NBPPI.h, NBDxe.c +// [TAG] None +// [Category] Improvement +// [Description] Change for mxm SgDgpuPwrEnable->Active = +// ACTIVE_dGPU_PWR_EN. +// [Description] NBPEI.c, NBPPI.h, NBDxe.c +// +// 30 11/28/12 9:52p Jeffch +// [TAG] DetectNonComplaint +// [Category] Improvement +// [Description] added peg DetectNonComplaint function. +// +// 29 11/20/12 2:41a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update SA RC 0.80. +// [Files] NBDxe.c; NBPei.c +// +// 28 11/14/12 5:37a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update XTU4.x function +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h; NBDXE.c; NB.sd; +// NB.uni +// +// 27 11/12/12 12:11a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Change name SMRAMC to R_SA_SMRAMC for build error. +// [Files] NBPei.c; +// +// 26 11/07/12 6:19a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Support ULT one BIOS +// [Files] NBPei.c; GetSetupData.c; NbSetupData.h +// +// 25 10/30/12 7:05a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update SA RC 0.72. +// [Files] NBDxe.c; NBPei.c +// +// 2 10/22/12 6:38a Jeffch +// +// 24 10/18/12 11:04p Jeffch +// [TAG] None +// [Severity] Important +// [Description] Support Disable AB SEG. +// [Files] NBPei.c; +// +// 23 10/16/12 9:38a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Remove invalid code. +// [Files] NBPei.c; +// +// 22 10/14/12 5:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow SA RC 0.71. +// [Files] NBPei.c, NBDxe.c; NBGeneric.c; NBCspLib.h; NBSetup.c; +// Nb.sd; GetSetupData.c +// +// 21 10/14/12 12:21a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Update by XTU4.0. +// [Files] NBPei.c, NBDxe.c, NBCspLib.h, NBGeneric.c +// [TAG] None +// [Severity] Important +// [Description] Follow Update by Mahobay. +// [Files] NBPei.c, NBDxe.c; +// +// 20 9/28/12 4:12a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] BDAT function support. +// [Files] NB.sd, NBDxe.c, NBPEI.c, SystemAgent.sdl, +// BdatAccessHandler.sdl +// +// 19 9/26/12 9:20a Yurenlai +// [TAG] None +// [Category] Update +// [Severity] Important +// [Description] Changed for Shark Bay SA Framework Reference Code Beta +// Version 0.7.0. +// [Files] NBPEI.c +// +// [TAG] EIP101495 +// [Category] Improvement +// [Severity] Important +// [Description] Initialize SSID of B0:D3:F0 and B0:D2:F0/F1. +// [Files] NB.h, NB.sdl, NBPEI.c +// +// 18 9/12/12 6:15a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Add RxCEM Loop back setup item. +// [Files] GetSetupData.c, NB.sd, NB.uni, NBPEI.c, NbSetupData.h, +// NBPEI.c, +// +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Modified for Switchable Graphics support. +// [Files] NBPEI.c, SwitchableGraphicsInit.c, SystemAgent.sdl +// +// 17 8/24/12 8:15a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Corrected GTT reference define. +// [Files] NBDxe.c, NBPEI.c +// +// 16 7/27/12 8:34a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] IGfx Fource Disable Support. +// [Files] GetSetupData.c, NB.sdl, NB.sd, NB.uni, NbSetupData.h, +// NBDxe.c, NBPEI.c +// +// 15 7/03/12 11:25p Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Fix building error. +// [Files] NBPEI.c +// +// 14 7/03/12 6:44a Yurenlai +// [TAG] None +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.6.0. +// [Files] NBPEI.DXS, NB.sd, NBDxe.c, NBPEI.c +// +// 13 6/14/12 4:49a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Add Notify BeforeMrc and AfterMrc. +// [Description] NBPEI.c, NBPPI.h, MemoryInit. +// +// 12 6/14/12 4:47a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fixed S4 resume fail. +// [Description] NBPEI.c +// +// 11 4/26/12 2:52a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Adjust Intel System Agent module the Setup item and +// Policy. +// [Description] GetSetupData.c, NB.sdl, NB.sd, NB.uni, NBDxe.c, +// NBPEI.c, +// NBSetup.c, NBSetupReset.c, NbSetupData.h +// +// 10 4/26/12 2:39a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Fixed PeiRamBootSupport = 1 warm boot system is hang. +// [Description] NBPEI.c, NBCspLib.h +// +// 9 4/26/12 2:35a Yurenlai +// [TAG] None +// [Category] Improvement +// [Severity] Important +// [Description] Support Locate MRC error Report. +// [Description] NBPEI.c, MemoryInit.c +// +// 8 4/05/12 4:46a Yurenlai +// +// [TAG] None +// [Category] New Feature +// [Severity] Normal +// [Description] Enabled GDXC feature. +// [Files] NBPEI.c +// +// 7 4/05/12 2:43a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Add routine RetrieveGdxcMemorySize to support GDXC +// feature and SA RC rev. 0.5.5. +// [Files] NBPEI.c +// +// 6 4/05/12 2:39a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.5.5 . +// [Files] NBDxe.c, NBPEI.c, NBSMI.C, NBGeneric.c, NB.sd, NBSetup.c, +// GetSetupData.c, NbSetupData.h +// +// 5 3/23/12 3:32a Yurenlai +// Fixed the build error of Help Builder. +// +// 4 3/22/12 11:08p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fixed MRC_DEBUG_PRINT = 0 for not send MRC debug message. +// [Files] NBPEI.c, MemoryInit.sdl, MrcOemDebugPrint.h +// +// 3 3/08/12 10:30p Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Support MRC debug message print information and RMT +// message. +// [Files] NBPEI.c +// +// 2 2/23/12 6:45a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Adjusted North Bridge the policy configuration. +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBPEI.C +// +// Description: This file contains code for North Bridge initialization +// in the PEI stage +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <Pei.h> +#include <token.h> +#include <HOB.h> +#include <StatusCodes.h> +#include <AmiLib.h> +#include <AmiPeiLib.h> +#include <AmiCspLib.h> + +#include <ppi\PciCfg2.h> +#include <ppi\CpuIo.h> +#include <ppi\NBPPI.h> +#include <ppi\CspLibPpi.h> +#include <ppi\smbus.h> +#include <ppi\ReadOnlyVariable2.h> +#include <Setup.h> +#include <CpuHobs.h> + +#include <Core\EM\ACPI\AcpiS3.h> + +#include <Protocol\NBMemInfo.h> + +#include <Core\GUID\MemoryTypeInformation.h> + +// Produced PPIs +#include <ppi\BaseMemorytest.h> + +#if SystemAgent_SUPPORT +#include <PchAccess.h> +#include <MemInfoHob.h> +#include <SaDataHob\SaDataHob.h> +#define _SA_COMMON_DEFINITIONS_H_ +#include <Ppi\SaPlatformPolicy\SaPlatformPolicy.h> +#include <SampleCode\Ppi\PlatformMemorySize\PlatformMemorySize.h> +#include <SampleCode\Ppi\PlatformMemoryRange\PlatformMemoryRange.h> +#endif + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +#include <PPI\PerfTunePpi.h> +#endif +#endif + +#if SB_STALL_PPI_SUPPORT +#include <Ppi\Stall.h> +#endif + +#include <Ppi\Wdt\Wdt.h> + +#ifdef SSA_FLAG +#define __EDKII_GLUE_PEIM_H__ +#include "SsaCallbackPeim.h" +#include "MrcOem.h" +#endif // SSA_FLAG + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +VOID NBResetCpuOnly ( // Do CPU Only Reset + IN EFI_PEI_SERVICES **PeiServices +); + +VOID ProgramNBSubId ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg +); + +EFI_STATUS BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN struct _PEI_BASE_MEMORY_TEST_PPI *This, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress +); + +EFI_STATUS +EFIAPI +ChooseRanges ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_RANGE_PPI *This, + IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask, + IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask, + IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY *GraphicsMemoryMask, + IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask +); + +EFI_STATUS +EFIAPI +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN struct _PEI_PLATFORM_MEMORY_SIZE_PPI *This, + IN OUT UINT64 *MemorySize +); + +EFI_STATUS NBPeiBeforeMrcPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS NBPeiEndOfMrcPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS ProgramNBRegBeforeEndofPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi +); + +EFI_STATUS CreateCPUHob( + IN EFI_PEI_SERVICES **PeiServices +); + +VOID +GtOcInit ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +); + +EFI_STATUS +InstallSaPlatformPolicyPpi ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +); + +#ifdef SSA_FLAG +MrcStatus +AmiSsaCallbackPpi ( + EFI_PEI_SERVICES **PeiServices, + struct _SSA_BIOS_CALLBACKS_PPI *SsaBiosCallBacksPpi, + MRC_OEM_STATUS_COMMAND StatusCommand, + VOID *CheckpointData +); +#endif // SSA_FLAG + +EFI_STATUS +MemoryErrorRead ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_MEMORY_ERROR_REPORT_PPI *This, + IN OUT UINT32 MemErrData +); + + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +// GUID Definition(s) +EFI_GUID gAmiNbPegInfoGuid = AMI_NB_PEG_INFO_GUID; +EFI_GUID gAmiPEINbInitPolicyGuid = AMI_PEI_NBINIT_POLICY_PPI_GUID; +EFI_GUID gBaseMemoryTestGuid = PEI_BASE_MEMORY_TEST_GUID; +EFI_GUID gEfiPeiEndOfPeiPhasePpiGuid = EFI_PEI_END_OF_PEI_PHASE_PPI_GUID; +EFI_GUID gAmiNbInfoHobGuid = AMI_NB_INFO_HOB_GUID; +EFI_GUID gMrcInfoHobGuid = AMI_MRC_INFO_HOB_GUID; +//EFI_GUID gEfiNBMemoryInfoGuid = EFI_NB_MEMORY_INFO_GUID; +EFI_GUID gEfiNbMrcS3DataGuid = EFI_NB_MRC_S3_DATA_GUID; +EFI_GUID gSetupGuid = SETUP_GUID; +EFI_GUID gAmiMemoryErrorReportPpiGuid = AMI_MEMORY_ERROR_REPORT_PPI_GUID; +EFI_GUID gWdtPpiGuid = WDT_PPI_GUID; +#if SB_STALL_PPI_SUPPORT +EFI_GUID gStallPpiGuid = EFI_PEI_STALL_PPI_GUID; +#endif +#if SystemAgent_SUPPORT +EFI_GUID gSaPlatformPolicyPpiGuid = SA_PLATFORM_POLICY_PPI_GUID; +EFI_GUID gMemRestoreDataGuid = EFI_MEMORY_RESTORE_DATA_GUID; +EFI_GUID gAmiNbPegGen3PresetSearchGuid = AMI_NB_PEG_GEN3_PRESET_SEARCH_GUID; +EFI_GUID gPlatformMemorySizeGuid = PEI_PLATFORM_MEMORY_SIZE_PPI_GUID; +EFI_GUID gPlatformMemoryRangeGuid = PEI_PLATFORM_MEMORY_RANGE_PPI_GUID; +EFI_GUID gEfiMemoryTypeInformationGuid = EFI_MEMORY_TYPE_INFORMATION_GUID; +#endif +EFI_GUID gEfiGlobalVariableGuid = EFI_GLOBAL_VARIABLE; + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +static EFI_GUID gPerfTunePpiGuid = PERF_TUNE_PPI_GUID; +EFI_GUID gAmiDddtPreFlagHobGuid = AMI_DDDT_PRESENT_FLAG_HOB_GUID; +#endif +#endif + +// PPI Definition(s) + +// PPI that are installed +static AMI_PEI_NBINIT_POLICY_PPI gAMIPEINBInitPolicyPpi = { + TRUE +}; + +static PEI_PLATFORM_MEMORY_SIZE_PPI mMemorySize = { + GetPlatformMemorySize +}; + +static PEI_PLATFORM_MEMORY_RANGE_PPI mPlatformMemoryRange = { + ChooseRanges +}; + + +static PEI_BASE_MEMORY_TEST_PPI gBaseMemoryTest = { + BaseMemoryTest +}; + +static EFI_PEI_NB_CPU_ONLY_RESET_PPI gNBCpuOnlyResetPpi = { + NBResetCpuOnly +}; + + +#ifdef SSA_FLAG +static SSA_BIOS_CALLBACKS_PPI gAmiSsaCallbackPpi = { + 0, + AmiSsaCallbackPpi, + NULL +}; +#endif // SSA_FLAG +static PEI_MEMORY_ERROR_REPORT_PPI gPeiMemoryErrorReportPpi = { + MemoryErrorRead +}; + + +// Include any additional PPI needed for memory detection in this +// list and define the functions in this file + +static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = { +#ifdef SSA_FLAG + { EFI_PEI_PPI_DESCRIPTOR_PPI, + &gSsaBiosCallBacksPpiGuid, + &gAmiSsaCallbackPpi}, +#endif // SSA_FLAG + { EFI_PEI_PPI_DESCRIPTOR_PPI, + &gAmiMemoryErrorReportPpiGuid, + &gPeiMemoryErrorReportPpi }, + + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gPlatformMemorySizeGuid, \ + &mMemorySize }, + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gPlatformMemoryRangeGuid, \ + &mPlatformMemoryRange }, + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gBaseMemoryTestGuid, \ + &gBaseMemoryTest }, + { EFI_PEI_PPI_DESCRIPTOR_PPI, \ + &gAmiPeiNBCpuOnlyResetPpiGuid, \ + &gNBCpuOnlyResetPpi }, + { (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), \ + &gAmiPEINbInitPolicyGuid, \ + &gAMIPEINBInitPolicyPpi } +}; + +// PPI that are notified + +static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = { + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK, \ + &gAmiPeiBeforeMrcGuid, NBPeiBeforeMrcPei }, + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK, \ + &gAmiPeiEndOfMemDetectGuid, NBPeiEndOfMrcPei }, + { EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | \ + EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, \ + &gEfiPeiEndOfPeiPhasePpiGuid, ProgramNBRegBeforeEndofPei }, +}; + +// External Declaration(s) + +// Function Definition(s) + +UINT32 NBPcieBridge[] = +{ + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, PCI_VID)}, + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, PCI_VID)}, + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, PCI_VID)}, + {0xFFFFFFFF} +}; +// << (EIP69780) + +//(EIP96114) +// Type Definition(s) +typedef struct { + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT16 PegBitOffset; +} DEVICES_AFTER_PCIIO; + +DEVICES_AFTER_PCIIO gDevicesTable[] = { + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, B_SA_DEVEN_D1F2EN_MASK }, + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, B_SA_DEVEN_D1F1EN_MASK }, + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, B_SA_DEVEN_D1F0EN_MASK }, + { 0xFF, 0xFF, 0xFF, 0, }, +}; + +UINTN gDevicesTableCount = sizeof(gDevicesTable) / sizeof(DEVICES_AFTER_PCIIO); +//(EIP96114) + +#ifdef RC_PEG_0 +DEVICES_AFTER_PCIIO gDisablePegDevicesTable[] = { +#if RC_PEG_0 == 0 + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, NULL }, +#endif +#if !(defined RC_PEG_1) || RC_PEG_1 == 0 + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, NULL }, +#endif +#if !(defined RC_PEG_2) || RC_PEG_2 == 0 + { PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, NULL }, +#endif + { 0xFF, 0xFF, 0xFF, NULL } +}; + +UINTN gDisablePegCount = sizeof(gDisablePegDevicesTable) / sizeof(DEVICES_AFTER_PCIIO); +#endif + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPEI_Init +// +// Description: This function is the entry point for this PEI. +// it must be ported to do NB specific programming needed +// at power-on, both in wakeup path as well as power-on path. +// +// Input: FfsHeader Pointer to the FFS file header +// PeiServices Pointer to the PEI services table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +// +// Notes: This function should initialize North Bridge before memory +// detection. +// Install AMI_PEI_NBINIT_POLICY_PPI to indicate that NB Init +// PEIM is installed +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS EFIAPI NBPEI_Init ( + IN EFI_FFS_FILE_HEADER *FfsHeader, + IN EFI_PEI_SERVICES **PeiServices ) +{ + + EFI_STATUS Status; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + EFI_PEI_CPU_IO_PPI *CpuIo; + NB_SETUP_DATA *NbSetupData = NULL; +#if defined SIO_SUPPORT && SIO_SUPPORT == 1// For SIO off. Without this compiler fails +#if defined SIO_Smsc1007 && SIO_Smsc1007 == 1 + UINT8 GpioDataReg3; +#endif +#endif + + // Get pointer to the PCI config PPI + PciCfg = (*PeiServices)->PciCfg; + CpuIo = (*PeiServices)->CpuIo; + + PEI_PROGRESS_CODE (PeiServices, PEI_CAR_NB_INIT); + + //Create CPU HOB + CreateCPUHob(PeiServices); + + // + // Allocate buffer for setup data variable. + // + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (NB_SETUP_DATA), &NbSetupData); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) NbSetupData, sizeof (NB_SETUP_DATA), 0); + + GetNbSetupData( PeiServices, NbSetupData, TRUE ); + + // Disable IGFX for UpSever +#if defined NB_IGFX_FORCE_DISABLE_SUPPORT && NB_IGFX_FORCE_DISABLE_SUPPORT == 1 + if(NbSetupData->IGfxForceDisable == 1) + { + NbSetupData->InternalGraphics = 0; // disable IGFX + NbSetupData->PrimaryDisplay = 1; // PEG Only + } +#endif // NB_IGFX_FORCE_DISABLE_SUPPORT + +#if defined SMM_THUNK_IN_CSM && SMM_THUNK_IN_CSM == 0 + // Enable Global SMRAM + SET_PCI8_NB(R_SA_SMRAMC, 8); // 0x88 +#else +#if defined SMM_THUNK_NO_AB_SEG && SMM_THUNK_NO_AB_SEG == 1 + // Enable Global SMRAM + SET_PCI8_NB(R_SA_SMRAMC, 8); // 0x88 +#endif +#endif + + // Install the NB Init Policy PPI + Status = (*PeiServices)->InstallPpi(PeiServices, &mPpiList[0]); + ASSERT_PEI_ERROR (PeiServices, Status); + + // Set up necessary PPI notifications + Status = (*PeiServices)->NotifyPpi( PeiServices, &mNotifyList[0] ); + ASSERT_PEI_ERROR ( PeiServices, Status ); + + // Program SSID + ProgramNBSubId( PeiServices, PciCfg ); + + // Install SaPlatformPolicyPpi + InstallSaPlatformPolicyPpi (PeiServices, NbSetupData); + +#if defined SIO_SUPPORT && SIO_SUPPORT == 1// For SIO off. Without this compiler fails +#if defined SIO_Smsc1007 && SIO_Smsc1007 == 1 + // Set up PWM or GMBus(I2C) panel backlight inverter. + // General Purpose I/O Data Register 3, this is not a config reg, so no need to enter config mode. + // From CRB schematic BIOS Note: Disable both BKLTSEL lines before enabling one. + GpioDataReg3 = READ_IO8(Smsc1007_PME_BASE_ADDRESS + 0x0E); + GpioDataReg3 |= (BIT07 | BIT01); + WRITE_IO8(Smsc1007_PME_BASE_ADDRESS + 0x0E, GpioDataReg3); + + // Program SIO to switch inverter + if ((NbSetupData->IgdLcdBlc == 0) || (NbSetupData->IgdLcdBlc == 2)) { + + // PWM backlight control + // Choose L_BKLTSEL0# via GPIO37 to enable PWM backlight control + GpioDataReg3 &= ~BIT07; // L_BKLTSEL0# + } else { + + // GMBus backlight control(also known as I2C) + // Choose L_BKLTSEL1# via GPIO31 to enable GMBus to support backlight control + GpioDataReg3 &= ~BIT01; // L_BKLTSEL1# + } + + WRITE_IO8(Smsc1007_PME_BASE_ADDRESS + 0x0E, GpioDataReg3); +#endif +#endif + + return EFI_SUCCESS; +} + + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBResetCpuOnly +// +// Description: This function issues a CPU only reset. +// +// Input: PeiServices - Pointer to the PEI services table +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NBResetCpuOnly ( // Do CPU Only Reset + IN EFI_PEI_SERVICES **PeiServices ) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramNBSubId +// +// Description: This function programs NB PCI devices sub-vendor ID and +// sub-system ID. +// +// Input: PeiServices - Pointer to the PEI services table +// PciCfg - Pointer to the PCI Configuration PPI +// +// Output: VOID +// +// Notes: 1. This routine only programs the PCI device in NB, hence, we +// have to check the bus/device/function numbers whether they +// are a NB PCI device or not. +// 2. This routine is invoked by PEI phase.(After PEI permantent +// memory be installed) +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID ProgramNBSubId ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_PCI_CFG2_PPI *PciCfg ) +{ + EFI_STATUS Status = EFI_SUCCESS; + AMI_PEI_NB_CUSTOM_PPI *NBPeiOemPpi; + UINTN i = 0; + UINT8 SsidReg = 0; + UINT32 PciSid = 0xffffffff; + AMI_NB_PCI_SSID_TABLE_STRUCT DefaultSIdTbl[] = {NB_PCI_DEVICES_SSID_TABLE}; + AMI_NB_PCI_SSID_TABLE_STRUCT *SsidTblPtr = DefaultSIdTbl; + + Status = (*PeiServices)->LocatePpi( PeiServices, \ + &gAmiPeiNBCustomPpiGuid, \ + 0, \ + NULL, \ + &NBPeiOemPpi ); + + if (Status == EFI_SUCCESS) { + if (NBPeiOemPpi->SsidTable != NULL) + SsidTblPtr = NBPeiOemPpi->SsidTable; + } + + while (SsidTblPtr[i].PciAddr != 0xffffffffffffffff) { + if ((SsidTblPtr[i].PciAddr == NB_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_IGD_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_IGD_BUS_DEV_FUN1) || \ + (SsidTblPtr[i].PciAddr == NB_HDA_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx16_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx8_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx4_BUS_DEV_FUN)) \ + { + if (SsidTblPtr[i].Sid == 0xffffffff) { + Status = PciCfg->Read( PeiServices, + PciCfg, + EfiPeiPciCfgWidthUint32, + SsidTblPtr[i].PciAddr, + &PciSid); + } else { + PciSid = SsidTblPtr[i].Sid; + } + + SsidReg = PCI_SVID; + + if((SsidTblPtr[i].PciAddr == NB_PCIEBRNx16_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx8_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRNx4_BUS_DEV_FUN) || \ + (SsidTblPtr[i].PciAddr == NB_PCIEBRN_BUS_DEV6_FUN)) + { + SsidReg = R_SA_PEG_SS_OFFSET; + } + + Status = PciCfg->Write( PeiServices, + PciCfg, + EfiPeiPciCfgWidthUint32, + SsidTblPtr[i].PciAddr | SsidReg, + &PciSid); + + } + + i++; + } + + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPeiBeforeMrcPei +// +// Description: This function can be Call NB PEI before Mrc. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBPeiBeforeMrcPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + + CpuIo = (*PeiServices)->CpuIo; + PciCfg = (*PeiServices)->PciCfg; + + PEI_TRACE((TRACE_ALWAYS, PeiServices, "NBPeiBeforeMrc Start.\n")); + + PEI_TRACE((TRACE_ALWAYS, PeiServices, "NBPeiBeforeMrc end.\n")); + + return Status; +} + +//(EIP96114) +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbPegDetectNonComplaint +// +// Description: This function is Detect peg NonComplaint devices. +// +// Input: PeiServices - Pointer to the PEI services table +// NB_SETUP_DATA - NbSetupData - NB Setup data stored in NVRAM +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NbPegDetectNonComplaint ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +) +{ +// UINT16 DetectCount; +// UINT16 Count; + UINT16 i; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + UINT16 PegBitMap = 0; + EFI_STATUS Status = EFI_SUCCESS; + NB_PEG_INFO_HOB *NbPegInfoHob; + BOOLEAN CardDetect[sizeof(gDevicesTable) / sizeof(DEVICES_AFTER_PCIIO)] = {FALSE}; + + Status = (*PeiServices)->CreateHob (PeiServices, EFI_HOB_TYPE_GUID_EXTENSION, sizeof (NB_PEG_INFO_HOB), (VOID **) &NbPegInfoHob); + if (EFI_ERROR (Status)) return ; + + NbPegInfoHob->Header.Name = gAmiNbPegInfoGuid; + + for ( i = 0; i < gDevicesTableCount; i++) + { + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + NbPegInfoHob->PegDeOverride[PegFun] = NbSetupData->PegDeEmphasis[PegFun]; + + if (READ_PCI32(PegBus, PegDev, PegFun, 0) == 0xffffffff) continue; + + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00010100); + WRITE_PCI16 (1, 0, 0, PCI_VID, 0); + CountTime(4000, PM_BASE_ADDRESS); // 1ms + if(READ_PCI8 (PegBus, PegDev, PegFun, R_SA_PEG_SLOTSTS_OFFSET) & BIT06) { + if(READ_PCI16 (1, 0, 0, PCI_VID) != 0xffff) { + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00000000); + CardDetect[i] = TRUE; + continue; + } + } + + RW_PCI8(PegBus, PegDev, PegFun, 0xD0, 0x01, 0xff); // Gen 1 + CountTime(4000, PM_BASE_ADDRESS); // 1ms + if(READ_PCI8 (PegBus, PegDev, PegFun, R_SA_PEG_SLOTSTS_OFFSET) & BIT06) { + if(READ_PCI16 (1, 0, 0, PCI_VID) != 0xffff) { + NbPegInfoHob->PegDeOverride[PegFun] = 0; // Set 6DB. + CardDetect[i] = TRUE; + } + } + + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00000000); + } + if (NbSetupData->AlwaysEnablePeg != 1) { + + for ( i = 0; i < gDevicesTableCount; i++) { + + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + + if (READ_PCI32(PegBus, PegDev, PegFun, 0) == 0xffffffff) continue; + + if (CardDetect[i]) { + continue; + } else { + + // if devices insert D1 F1 or F2, do not disable F0. + if(PegFun == 0 && (CardDetect[0] || CardDetect[1])) break; + PegBitMap |= gDevicesTable[i].PegBitOffset; + SET_MEM8 (NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, R_SA_PEG_LCTL_OFFSET), BIT4); + SET_MEM8 (NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, R_SA_PEG_DEBUP2_OFFSET), BIT0); + } + } + + // Disable Peg + RESET_PCI16_NB(R_SA_DEVEN, PegBitMap); // 0x54 + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbClearPegCtrlRegVgaEnable +// +// Description: This function is Clear PEG 0x3E bit3 for 3D card. +// +// Input: PeiServices - Pointer to the PEI services table +// NB_SETUP_DATA - NbSetupData - NB Setup data stored in NVRAM +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NbClearPegCtrlRegVgaEnable ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +) +{ + UINT16 i; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + + for ( i = 0; i < gDevicesTableCount; i++) + { + PegBus = gDevicesTable[i].Bus; + PegDev = gDevicesTable[i].Dev; + PegFun = gDevicesTable[i].Fun; + if (READ_PCI32(PegBus, PegDev, PegFun, 0) == 0xffffffff) continue; + if ((READ_PCI8 (PegBus, PegDev, PegFun, R_SA_PEG_SLOTSTS_OFFSET) & BIT06) == 0) continue; // 0xBA + + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00010100); + WRITE_PCI16 (1, 0, 0, PCI_VID, 0); + + // Clear Peg VgaEnable + RESET_PCI8(PegBus, PegDev, PegFun, PCI_BRIDGE_CNTL, BIT03); + WRITE_PCI32 (PegBus, PegDev, PegFun, PCI_PBUS, 0x00000000); + } +} +//(EIP73801) +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPeiEndOfMrcPei +// +// Description: This function can be Call NB PEI after Mrc. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBPeiEndOfMrcPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + NB_SETUP_DATA *NbSetupData = NULL; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 + WDT_PPI *WdtPpi = NULL; +#endif + EFI_BOOT_MODE BootMode; // [ EIP161790 ] + + + CpuIo = (*PeiServices)->CpuIo; + PciCfg = (*PeiServices)->PciCfg; + + PEI_TRACE((TRACE_ALWAYS, PeiServices, "NBPeiAfterMrc Start.\n")); + + // + // Allocate buffer for setup data variable. + // + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (NB_SETUP_DATA), &NbSetupData); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) NbSetupData, sizeof (NB_SETUP_DATA), 0); + + GetNbSetupData( PeiServices, NbSetupData, TRUE ); + + + // Set DRAM Initialization Bit. + //if ((READ_PCI8_SB(SB_REG_GEN_PMCON_2) & BIT07) == 0) // [ EIP161790 ] + //{ + // SET_PCI8_SB(SB_REG_GEN_PMCON_2, BIT07); // 0xA2 + //} + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if ((!EFI_ERROR (Status)) && (BootMode == BOOT_ON_S3_RESUME)) + { + if ((READ_PCI8_SB(SB_REG_GEN_PMCON_2) & BIT07) == 0) + { + SET_PCI8_SB(SB_REG_GEN_PMCON_2, BIT07); // 0xA2 + } + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 + // + // Locate WDT PPI for access to Wdt->Disable() + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gWdtPpiGuid, + 0, + NULL, + &WdtPpi + ); + if (!EFI_ERROR (Status)) { + WdtPpi->Disable(); + } +#endif + +//(EIP96114) + +#if (defined RC_PEG_0) && RC_PEG_0 == 1 + if (NbSetupData->DetectNonComplaint && NbSetupData->AlwaysEnablePeg != 2) + { + // Peg Detect NonComplaint devices. + NbPegDetectNonComplaint(PeiServices, NbSetupData); + } +#endif + + // if SG and have pGPU + if (READ_PCI32(0, 2, 0, 0) != 0xffffffff && NbSetupData->PrimaryDisplay == 4) { + // Clear PEG 0x3E bit3 for SG mode. + NbClearPegCtrlRegVgaEnable(PeiServices, NbSetupData); + } + + PEI_TRACE((TRACE_ALWAYS, PeiServices, "NBPeiAfterMrc end.\n")); + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ProgramNBRegBeforeEndofPei +// +// Description: This function can be used to program any NB regisater before +// end of PEI phase. +// +// Input: PeiServices - Pointer to the PEI services table +// NotifyDescriptor - Pointer to the descriptor for the +// notification event. +// InvokePpi - Pointer to the PPI that was installed +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS ProgramNBRegBeforeEndofPei ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *InvokePpi ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PCI_CFG2_PPI *PciCfg; + EFI_BOOT_MODE BootMode; + UINTN PegAddress; + UINT8 CapPtr = 0; + UINT8 i = 0; + UINT8 PrimaryBus, SecondaryBus; + CpuIo = (*PeiServices)->CpuIo; + PciCfg = (*PeiServices)->PciCfg; + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + + if (BootMode == BOOT_ON_S3_RESUME) { + // Porting if needed. + + for (i = 0; NBPcieBridge[i] != 0xFFFFFFFF; i++) + { + if (READ_MEM32(NBPcieBridge[i]) == 0xFFFFFFFF) continue; + if (!(READ_MEM8(NBPcieBridge[i] + R_SA_PEG_SLOTSTS_OFFSET) & BIT06)) continue; + + PrimaryBus = READ_MEM8 (NBPcieBridge[i] + PCI_PBUS + 1); + SecondaryBus = READ_MEM8 (NBPcieBridge[i] + PCI_PBUS + 2); + + for (; PrimaryBus <= SecondaryBus; PrimaryBus++) { + PegAddress = NB_PCIE_CFG_ADDRESS(PrimaryBus, 0, 0, 0); + + // Network Card. + if (READ_MEM8(PegAddress + 0x0B) == 0x02) { + // Find Cap ID 0x01 + CapPtr = NbFindCapPtr(PegAddress, 0x01); + if(CapPtr != 0) { + // Clear PME status + SET_MEM16((PegAddress + CapPtr + 0x04), BIT15); + } + } + } + + // Clear root port PME status + SET_MEM8((NBPcieBridge[i] + 0xC2), BIT01); + } + + } + + return EFI_SUCCESS; +} + +//---------------------------------------------------------------------------- +// BaseMemoryTest +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: BaseMemoryTest +// +// Description: This function performs the base memory test. +// +// Input: PeiServices - Pointer to the PEI services table +// This - Pointer to the Base Memory Test PPI +// BeginAddress - The begin address for test. +// MemoryLength - The length in byte for test. +// Operation - The memort test operated policy. +// ErrorAddress - The error address when test is failed. +// +// Output: EFI_STATUS +// EFI_DEVICE_ERROR - Tge base memory test is failure. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BASE_MEMORY_TEST_PPI *This, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress ) +{ + +#if defined PEI_MRC_BASE_MEMORY_TEST_ENABLE && PEI_MRC_BASE_MEMORY_TEST_ENABLE == 1 + UINT32 TestPattern; + UINT32 TestMask; + UINT32 SpanSize; + EFI_PHYSICAL_ADDRESS TempAddress; + +#if defined PeiRamBootSupport && PeiRamBootSupport == 1 + if(!CheckPeiFvCopyToRam(PeiServices)) return EFI_SUCCESS; +#endif + + (*PeiServices)->ReportStatusCode ( + PeiServices, + EFI_PROGRESS_CODE, + EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_PC_TEST, + 0, + NULL, + NULL + ); + + TestPattern = 0x5A5A5A5A; + TestMask = 0; + SpanSize = 0; + + // + // Make sure we don't try and test anything above the max physical address range + // + ASSERT_PEI_ERROR (PeiServices, BeginAddress + MemoryLength < 0xFFFFFFFFFFFFFFFF); + + switch (Operation) { + case Extensive: + SpanSize = 0x4; + break; + case Sparse: + case Quick: + SpanSize = 0x40000; + break; + case Ignore: + return EFI_SUCCESS; + } + + // + // Write the test pattern into memory range + // + TempAddress = BeginAddress; + while (TempAddress < BeginAddress + MemoryLength) { + (*(UINT32*)(UINTN)TempAddress) = TestPattern; + TempAddress += SpanSize; + } + + // + // Read pattern from memory and compare it + // + TempAddress = BeginAddress; + while (TempAddress < BeginAddress + MemoryLength) { + if ((*(UINT32*)(UINTN)TempAddress) != TestPattern) { + *ErrorAddress = TempAddress; + (*PeiServices)->ReportStatusCode ( + PeiServices, + EFI_ERROR_CODE + EFI_ERROR_UNRECOVERED, + EFI_COMPUTING_UNIT_MEMORY + EFI_CU_MEMORY_EC_UNCORRECTABLE, + 0, + NULL, + NULL + ); + return EFI_DEVICE_ERROR; + } else { + (*(UINT32*)(UINTN)TempAddress) = 0; + } + TempAddress += SpanSize; + } +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: ChooseRanges +// +// Description: Find out which memory ranges to reserve on this platform +// +// Input: PeiServices - Pointer to the PEI services table. +// This - Pointer to the Pei platform memory range ppi. +// OptionRomMask - The reserve for option ROM usage. +// SmramMask - The reserve for smram usage. +// GraphicsMemoryMask - The reserve for graphics memory usage. +// PciMemoryMask - The reserve for Pei Memory usage. +// +// Output: +// EFI_STATUS - EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +ChooseRanges ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_RANGE_PPI *This, + IN OUT PEI_MEMORY_RANGE_OPTION_ROM *OptionRomMask, + IN OUT PEI_MEMORY_RANGE_SMRAM *SmramMask, + IN OUT PEI_MEMORY_RANGE_GRAPHICS_MEMORY *GraphicsMemoryMask, + IN OUT PEI_MEMORY_RANGE_PCI_MEMORY *PciMemoryMask + ) +{ + UINT16 GraphicsControlRegister; + UINT32 IgdSize; + UINT32 GttSize; + EFI_STATUS Status; + SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi; +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + VOID *FirstHob; + DDDT_PRESENT_FLAG_HOB *DddtPreFlagHob; + UINT8 NumOcBins = (UINT8)(ReadMsr(0x194) >> 17) & 0x7; + Status = (*PeiServices)->GetHobList(PeiServices, &FirstHob); + ASSERT_PEI_ERROR(PeiServices, Status); + + // Get XTU devices Present HOB + DddtPreFlagHob = (DDDT_PRESENT_FLAG_HOB*) FirstHob; + while (!EFI_ERROR(Status = FindNextHobByType(EFI_HOB_TYPE_GUID_EXTENSION, &DddtPreFlagHob))) { + if (guidcmp(&((EFI_HOB_GUID_TYPE*)DddtPreFlagHob)->Name, &gAmiDddtPreFlagHobGuid) == 0) { + break; + } + } + + // default XTU graphics Present is disable + DddtPreFlagHob->PresentFlag[BIOS_GRAPHICS_TURBO_RATIO_LIMIT_IMPLEMENTATION] = 0; + DddtPreFlagHob->PresentFlag[BIOS_GRAPHICS_CORE_VOLTAGE_IMPLEMENTATION] = 0; + + //If cpu is lock version then clear runtime turbo DDD table flag. + if(NumOcBins == 0) + DddtPreFlagHob->PresentFlag[BIOS_RUNTIME_TURBO_OVERRIDE_IMPLEMENTATION] = 0; +#endif +#endif + + // + // Get platform policy settings through the SaPlatformPolicy PPI + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gSaPlatformPolicyPpiGuid, + 0, + NULL, + &SaPlatformPolicyPpi + ); + if (EFI_ERROR (Status))SaPlatformPolicyPpi->GtConfig->InternalGraphics = 2; + // + // Choose regions to reserve for Option ROM usage. + // + *OptionRomMask = PEI_MR_OPTION_ROM_NONE; + + // + // Choose regions to reserve for SMM usage. + // Each block is 128KB which is defined in PlatformRange PPI. + // Needs to convert the value of TSEG_SIZE from bytes to blocks. + // + *SmramMask = (TSEG_SIZE >> 17) | PEI_MR_SMRAM_CACHEABLE_MASK | +#if defined SMM_THUNK_IN_CSM && SMM_THUNK_IN_CSM == 0 + PEI_MR_SMRAM_ABSEG_MASK | +#else +#if defined SMM_THUNK_NO_AB_SEG && SMM_THUNK_NO_AB_SEG == 1 + PEI_MR_SMRAM_ABSEG_MASK | +#endif +#endif + PEI_MR_SMRAM_TSEG_MASK; + + // + // Choose regions to reserve for Graphics Memory usage. + // + *GraphicsMemoryMask = PEI_MR_GRAPHICS_MEMORY_NONE; + + GraphicsControlRegister = READ_PCI16_NB (R_SA_GGC); + if (((GraphicsControlRegister & B_SA_GGC_IVD_MASK) == 0) || (SaPlatformPolicyPpi->GtConfig->InternalGraphics == 1)) { + // + // IGD is enabled, fill the IGD and GTT stolen memory sizes. + // + IgdSize = (GraphicsControlRegister & B_SA_GGC_GMS_MASK) >> N_SA_GGC_GMS_OFFSET; + + // + // Add a w/a to handle 1G Stolen Memory - As per SNB ConfigDB definition, + // Max No of bits to support this encoding is '5' 0/0/0/GGC[7:3] which can + // hold a value of '1Fh'. + // For 1G, suggested encoding is '11h'. Set the GraphicsMemoryMask as '2048' + // to reserve 1G stolen memory. + // + // *GraphicsMemoryMask = IgdSize * PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE; + // *GraphicsMemoryMask = 32 * 64 + // *GraphicsMemoryMask = 2048 + + if (IgdSize == 0x11) { + IgdSize = 0x20; + } + + *GraphicsMemoryMask = IgdSize * PEI_MR_GRAPHICS_MEMORY_32M_NOCACHE; + + // + // Add GTT memory to reserved graphics memory + // + GttSize = (GraphicsControlRegister & B_SA_GGC_GGMS_MASK) >> N_SA_GGC_GGMS_OFFSET; + + switch (GttSize) { + case 1: + *GraphicsMemoryMask += PEI_MR_GRAPHICS_MEMORY_1M_NOCACHE; + break; + + case 2: + *GraphicsMemoryMask += PEI_MR_GRAPHICS_MEMORY_2M_NOCACHE; + break; + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C + // if IGD is enabled ,XTU graphics Present is enable + DddtPreFlagHob->PresentFlag[BIOS_GRAPHICS_TURBO_RATIO_LIMIT_IMPLEMENTATION] = 1; + DddtPreFlagHob->PresentFlag[BIOS_GRAPHICS_CORE_VOLTAGE_IMPLEMENTATION] = 1; +#endif +#endif + } + + *PciMemoryMask = 0; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RetrieveGdxcMemorySize +// +// Description: Determine the memory size desired by GDXC +// +// Input: PeiServices - Pointer to the PEI services table. +// MotSize - Gdxc Mot memory size to return. +// GdxcSize - Gdxc Required memory size to return. +// +// Output: +// VOID +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +RetrieveGdxcMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *MotSize, + IN OUT UINT64 *GdxcSize) +{ + UINT32 MchBar; + UINT32 GdxcBar; + UINT32 TempMotSize; + UINT32 TempOclaSize; + + // + // Get MchBAR + // + MchBar = MmPci32(0, 0, 0, R_SA_MCHBAR) & B_SA_MCHBAR_MCHBAR_MASK; + // + // Get GdxcBar + // + GdxcBar = MmioRead32(MchBar+NCDECS_CR_GDXCBAR_NCU_REG); + GdxcBar &= NCDECS_CR_GDXCBAR_NCU_MAX; + // + // Determine Gdxc size: Includes MOT\PSMI\IOT (OCLA) + // + TempMotSize = MmioRead32(GdxcBar+0x18); + *GdxcSize = (((TempMotSize & 0xFFFF0000) >> 16) - (TempMotSize & 0x0000FFFF) + 1) << 23; + *MotSize = *GdxcSize; + + TempOclaSize = MmioRead32(GdxcBar+0x28); + *GdxcSize += (((TempOclaSize & 0xFFFF0000) >> 16) - (TempOclaSize & 0x0000FFFF)) << 23; + + // Add 16MB if some allocated to MOT and/or IOT + if (*GdxcSize != 0) + *GdxcSize += (16 << 20); +} + +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = { + { EfiACPIReclaimMemory, 0x5 }, + { EfiACPIMemoryNVS, 0x280 }, + { EfiReservedMemoryType, 0x500}, + { EfiRuntimeServicesData, 0x2A}, +#ifdef EFI_DEBUG + { EfiRuntimeServicesCode, 0x80 }, + { EfiBootServicesCode, 0x1000}, +#else + { EfiRuntimeServicesCode, 0x3A}, + { EfiBootServicesCode, 0x1000}, +#endif + { EfiMaxMemoryType, 0 } +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetPlatformMemorySize +// +// Description: Get the platform for the minimum memory size +// +// Input: PeiServices - Pointer to the PEI services table. +// This - Pointer to the Pei platform memory range ppi. +// MemorySize - Platform for the minimum memory size. +// +// Output: +// EFI_STATUS - Status +// EFI_ERROR - Create hob fail +// EFI_SUCCESS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, + IN OUT UINT64 *MemorySize + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData [EfiMaxMemoryType + 1]; + UINTN Index; + EFI_BOOT_MODE BootMode; + EFI_HOB_GUID_TYPE *Hob; +// UINT64 GdxcRequiredMemSize; +// UINT64 GdxcMotMemSize; + + // RetrieveGdxcMemorySize(PeiServices, &GdxcMotMemSize, &GdxcRequiredMemSize); + + // Accumulate maximum amount of memory needed + // *MemorySize = (READ_PCI32_NB (R_SA_TSEGMB) & B_SA_TSEGMB_TSEGMB_MASK) - 0x1000000; + // *MemorySize -= GdxcRequiredMemSize; + + *MemorySize = PEI_MIN_MEMORY_SIZE; + + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + &Variable + ); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->GetBootMode (PeiServices, &BootMode); + ASSERT_PEI_ERROR (PeiServices, Status); + + DataSize = sizeof (MemoryData); + + Status = Variable->GetVariable ( + Variable, + (BootMode == BOOT_ON_S4_RESUME) + ? L"PreviousMemoryTypeInformation" + : EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + + if (EFI_ERROR (Status) || ( BootMode == BOOT_ON_FLASH_UPDATE )) { + if ( BootMode == BOOT_IN_RECOVERY_MODE ) { + return EFI_SUCCESS; + } + + // Use default value to avoid memory fragment. OS boot/installation fails + // if there is not enough continuous memory available + DataSize = sizeof (mDefaultMemoryTypeInformation); + (*PeiServices)->CopyMem (MemoryData, mDefaultMemoryTypeInformation, DataSize); + } + + for (Index = 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATION); Index++) { + *MemorySize += MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE; + } + + // Build the GUID'd HOB for DXE + Status = (*PeiServices)->CreateHob ( + PeiServices, + EFI_HOB_TYPE_GUID_EXTENSION, + (UINT16) (sizeof (EFI_HOB_GUID_TYPE) + DataSize), + &Hob + ); + if (EFI_ERROR (Status))return Status; + + ((EFI_HOB_GUID_TYPE *)(Hob))->Name = gEfiMemoryTypeInformationGuid; + + Hob++; + + // Copy memory data to Hob + (*PeiServices)->CopyMem (Hob, MemoryData, DataSize); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: CreateCPUHob +// +// Description: Create Cpu Hob and initialize it. +// +// Input: +// IN EFI_PEI_SERVICES **PeiServices +// +// Output: +// EFI_STATUS - EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS CreateCPUHob( + IN EFI_PEI_SERVICES **PeiServices +) +{ + EFI_HOB_CPU *pCpu = NULL; + EFI_STATUS Status; + + Status = (*PeiServices)->CreateHob( PeiServices, \ + EFI_HOB_TYPE_CPU, \ + sizeof(EFI_HOB_CPU), \ + &pCpu ); + if (Status == EFI_SUCCESS) { + pCpu->SizeOfMemorySpace = 36; + pCpu->SizeOfIoSpace = 16; + MemSet(pCpu->Reserved, 6, 0); + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DisablePegDevices +// +// Description: Check Disable Peg Devices. +// +// Input: +// +// Output: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID DisablePegDevices() +{ + UINT16 PegDisFun; + UINT16 i; +#ifdef RC_PEG_0 + for ( i = 0; gDisablePegDevicesTable[i].Bus != 0xff; i++) + { + UINTN PegAddress; + UINT8 PegBus; + UINT8 PegDev; + UINT8 PegFun; + + PegBus = gDisablePegDevicesTable[i].Bus; + PegDev = gDisablePegDevicesTable[i].Dev; + PegFun = gDisablePegDevicesTable[i].Fun; + + PegAddress = NB_PCIE_CFG_ADDRESS(PegBus, PegDev, PegFun, 0); + + if (READ_MEM32(PegAddress) == 0xFFFFFFFF) continue; + + // Disable Link +// CapPtr = NbFindCapPtr(PegAddress, 0x10); +// SET_MEM8((PegAddress + CapPtr + 0x10), BIT04); + SET_MEM8 ((PegAddress + R_SA_PEG_LCTL_OFFSET), BIT4); + SET_MEM8 ((PegAddress + R_SA_PEG_DEBUP2_OFFSET), BIT0); + SET_MEM32 ((PegAddress + R_SA_PEG_PEGCOMLCGCTRL_OFFSET), BIT30); + } + + PegDisFun = 0 +#if RC_PEG_0 == 0 + | B_SA_DEVEN_D1F0EN_MASK +#endif +#if !(defined RC_PEG_1) || RC_PEG_1 == 0 + | B_SA_DEVEN_D1F1EN_MASK +#endif +#if !(defined RC_PEG_2) || RC_PEG_2 == 0 + | B_SA_DEVEN_D1F2EN_MASK +#endif + ; + + // Disable PEG + if(PegDisFun != 0) + RESET_PCI16_NB(R_SA_DEVEN, PegDisFun); // 0x54 + +#endif //#ifdef RC_PEG_0 +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InstallSaPlatformPolicyPpi +// +// Description: InstallSaPlatformPolicyPpi: This Function installs the SNB SA POLICY PPI +// +// Parameters: +// PeiServices - General purpose services available to every PEIM +// NbSetupData - NB Setup data stored in NVRAM +// +// Returns: +// Status: Return Status +// Notes: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS +InstallSaPlatformPolicyPpi ( + IN EFI_PEI_SERVICES **PeiServices, + IN NB_SETUP_DATA *NbSetupData +) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices = NULL; + UINTN VariableSize; + VOID *MrcS3ResumeData; + VOID *PegGen3Data; + EFI_PEI_CPU_IO_PPI *CpuIo; + EFI_PEI_PPI_DESCRIPTOR *SaPlatformPolicyPpiDesc; + SA_PLATFORM_POLICY_PPI *SaPlatformPolicyPpi; + SA_PLATFORM_DATA *PlatformData; + GT_CONFIGURATION *GtConfig; + MEMORY_CONFIGURATION *MemConfig; + PCIE_CONFIGURATION *PcieConfig; + OVERCLOCKING_CONFIGURATION *OcConfig; + PEG_GPIO_DATA *PegGpioData; + SA_GPIO_INFO *SaPegReset; +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + SG_GPIO_DATA *SgGpioData; + SA_GPIO_INFO *SgDgpuPwrOK; + SA_GPIO_INFO *SgDgpuHoldRst; + SA_GPIO_INFO *SgDgpuPwrEnable; + SA_GPIO_INFO *SgDgpuPrsnt; +#endif + UINTN MemoryCeiling = 0; + UINT16 LpcDeviceId; + UINT16 McDeviceId; + UINTN i = 0; + UINT16 CapPtr = 0; + + CpuIo = (*PeiServices)->CpuIo; + + // Locate Variable Ppi + Status = (*PeiServices)->LocatePpi (PeiServices, &gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, &VariableServices); + ASSERT_PEI_ERROR (PeiServices, Status); + + // Allocate descriptor and PPI structures + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_PLATFORM_POLICY_PPI), &SaPlatformPolicyPpi); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (EFI_PEI_PPI_DESCRIPTOR), &SaPlatformPolicyPpiDesc); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_PLATFORM_DATA), &PlatformData); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (GT_CONFIGURATION), &GtConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (MEMORY_CONFIGURATION), &MemConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PCIE_CONFIGURATION), &PcieConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (PEG_GPIO_DATA), &PegGpioData); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (OVERCLOCKING_CONFIGURATION), &OcConfig); + ASSERT_PEI_ERROR (PeiServices, Status); + +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SG_GPIO_DATA), &SgGpioData); + ASSERT_PEI_ERROR (PeiServices, Status); +#endif + + // Set Default to Variable not found + (*PeiServices)->SetMem ((VOID*) PlatformData, sizeof (SA_PLATFORM_DATA), 0); + (*PeiServices)->SetMem ((VOID*) SaPlatformPolicyPpiDesc, sizeof (EFI_PEI_PPI_DESCRIPTOR), 0); + (*PeiServices)->SetMem ((VOID*) GtConfig, sizeof (GT_CONFIGURATION), 0); + (*PeiServices)->SetMem ((VOID*) MemConfig, sizeof (MEMORY_CONFIGURATION), 0); + (*PeiServices)->SetMem ((VOID*) PcieConfig, sizeof (PCIE_CONFIGURATION), 0); + (*PeiServices)->SetMem ((VOID*) SaPlatformPolicyPpi, sizeof (SA_PLATFORM_POLICY_PPI), 0); + (*PeiServices)->SetMem ((VOID*) PegGpioData, sizeof (PEG_GPIO_DATA), 0); + (*PeiServices)->SetMem ((VOID*) OcConfig, sizeof (OVERCLOCKING_CONFIGURATION), 0); +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + (*PeiServices)->SetMem ((VOID*) SgGpioData, sizeof (SG_GPIO_DATA), 0); +#endif + + SaPlatformPolicyPpi->PlatformData = PlatformData; + SaPlatformPolicyPpi->GtConfig = GtConfig; + SaPlatformPolicyPpi->MemConfig = MemConfig; + SaPlatformPolicyPpi->PcieConfig = PcieConfig; + SaPlatformPolicyPpi->PcieConfig->PegGpioData = PegGpioData; + SaPlatformPolicyPpi->OcConfig = OcConfig; +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + SaPlatformPolicyPpi->SgGpioData = SgGpioData; +#endif + SaPlatformPolicyPpi->S3DataPtr = NULL; + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SaPegReset); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SaPegReset, sizeof (SA_GPIO_INFO), 0); + SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset = SaPegReset; + +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SgDgpuPwrOK); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SgDgpuPwrOK, sizeof (SA_GPIO_INFO), 0); + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK = SgDgpuPwrOK; + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SgDgpuPwrEnable); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SgDgpuPwrEnable, sizeof (SA_GPIO_INFO), 0); + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable = SgDgpuPwrEnable; + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SgDgpuHoldRst); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SgDgpuHoldRst, sizeof (SA_GPIO_INFO), 0);; + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst = SgDgpuHoldRst; + + Status = (*PeiServices)->AllocatePool (PeiServices, sizeof (SA_GPIO_INFO), &SgDgpuPrsnt); + ASSERT_PEI_ERROR (PeiServices, Status); + (*PeiServices)->SetMem ((VOID*) SgDgpuPrsnt, sizeof (SA_GPIO_INFO), 0); + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt = SgDgpuPrsnt; +#endif + + // + // Initialize the PPI + // + SaPlatformPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + SaPlatformPolicyPpiDesc->Guid = &gSaPlatformPolicyPpiGuid; + SaPlatformPolicyPpiDesc->Ppi = SaPlatformPolicyPpi; + + // Read MC device ID + McDeviceId = READ_PCI16_NB(R_SA_MC_DEVICE_ID); + + // Read PCH device ID + LpcDeviceId = READ_PCI16_SB(R_PCH_LPC_DEVICE_ID); + + // Update the REVISION number + SaPlatformPolicyPpi->Revision = SA_PLATFORM_POLICY_PPI_REVISION_15; + + // Get the Platform Configuration from NbSetupData + SaPlatformPolicyPpi->PlatformData->SpdAddressTable[0] = DIMM1_SMBUS_ADDRESS; + SaPlatformPolicyPpi->PlatformData->SpdAddressTable[1] = DIMM2_SMBUS_ADDRESS; + SaPlatformPolicyPpi->PlatformData->SpdAddressTable[2] = DIMM3_SMBUS_ADDRESS; + SaPlatformPolicyPpi->PlatformData->SpdAddressTable[3] = DIMM4_SMBUS_ADDRESS; + SaPlatformPolicyPpi->PlatformData->MchBar = (UINT32)NB_MCH_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->DmiBar = (UINT32)NB_DMI_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->EpBar = (UINT32)NB_EP_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->PciExpressBar = (UINT32)PCIEX_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->SmbusBar = (UINT32)SMBUS_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->EdramBar = (UINT32)NB_DERAM_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->GdxcBar = (UINT32)NB_GDXC_BASE_ADDRESS; + SaPlatformPolicyPpi->PlatformData->TsegSize = (UINT32)TSEG_SIZE; + SaPlatformPolicyPpi->PlatformData->IedSize = (UINT32)IED_SIZE; + SaPlatformPolicyPpi->PlatformData->FastBoot = NbSetupData->MrcFastBoot; + + if(NbSetupData->IsRunMemoryDown) { + SaPlatformPolicyPpi->PlatformData->BoardId = 0; + } else { + SaPlatformPolicyPpi->PlatformData->BoardId = 0xff; + } + + SaPlatformPolicyPpi->MemConfig->MrcFastBoot = NbSetupData->MrcFastBoot; + + SaPlatformPolicyPpi->MemConfig->BClkFrequency = 100 * 1000 * 1000; + SaPlatformPolicyPpi->MemConfig->MaxRttWr = NbSetupData->MaxRttWr; + SaPlatformPolicyPpi->MemConfig->PowerDownMode = NbSetupData->PowerDownMode0; + SaPlatformPolicyPpi->MemConfig->PwdwnIdleCounter = NbSetupData->PwdwnIdleCounter; + SaPlatformPolicyPpi->MemConfig->RankInterleave = NbSetupData->RankInterleave; + SaPlatformPolicyPpi->MemConfig->EnhancedInterleave = NbSetupData->EnhancedInterleave; + SaPlatformPolicyPpi->MemConfig->WeaklockEn = NbSetupData->WeaklockEn; + SaPlatformPolicyPpi->MemConfig->EnCmdRate = 7; + SaPlatformPolicyPpi->MemConfig->CmdTriStateDis = FALSE; + SaPlatformPolicyPpi->MemConfig->RefreshRate2x = NbSetupData->Refresh2X; + + SaPlatformPolicyPpi->MemConfig->McLock = NbSetupData->McLock; + + SaPlatformPolicyPpi->MemConfig->GdxcEnable = NbSetupData->GdxcEnable; + SaPlatformPolicyPpi->MemConfig->GdxcIotSize = NbSetupData->GdxcIotSize; + SaPlatformPolicyPpi->MemConfig->GdxcMotSize = NbSetupData->GdxcMotSize; + SaPlatformPolicyPpi->MemConfig->MemoryTrace = NbSetupData->MemoryTrace; + + SaPlatformPolicyPpi->MemConfig->ECT = NbSetupData->ECT; + SaPlatformPolicyPpi->MemConfig->SOT = NbSetupData->SOT; + SaPlatformPolicyPpi->MemConfig->RDMPRT = NbSetupData->RDMPRT; + SaPlatformPolicyPpi->MemConfig->RCVET = NbSetupData->RCVET; + SaPlatformPolicyPpi->MemConfig->JWRL = NbSetupData->JWRL; + SaPlatformPolicyPpi->MemConfig->FWRL = NbSetupData->FWRL; + SaPlatformPolicyPpi->MemConfig->WRTC1D = NbSetupData->WRTC1D; + SaPlatformPolicyPpi->MemConfig->RDTC1D = NbSetupData->RDTC1D; + SaPlatformPolicyPpi->MemConfig->DIMMODTT = NbSetupData->DIMMODTT; + SaPlatformPolicyPpi->MemConfig->WRDST = NbSetupData->WRDST; + SaPlatformPolicyPpi->MemConfig->WREQT = NbSetupData->WREQT; + + SaPlatformPolicyPpi->MemConfig->RDODTT = NbSetupData->RDODTT; + SaPlatformPolicyPpi->MemConfig->RDEQT = NbSetupData->RDEQT; + SaPlatformPolicyPpi->MemConfig->RDAPT = NbSetupData->RDAPT; + SaPlatformPolicyPpi->MemConfig->WRTC2D = NbSetupData->WRTC2D; + SaPlatformPolicyPpi->MemConfig->RDTC2D = NbSetupData->RDTC2D; + SaPlatformPolicyPpi->MemConfig->CMDVC = NbSetupData->CMDVC; + SaPlatformPolicyPpi->MemConfig->WRVC2D = NbSetupData->WRVC2D; + SaPlatformPolicyPpi->MemConfig->RDVC2D = NbSetupData->RDVC2D; + SaPlatformPolicyPpi->MemConfig->LCT = NbSetupData->LCT; + SaPlatformPolicyPpi->MemConfig->RTL = NbSetupData->RTL; + SaPlatformPolicyPpi->MemConfig->TAT = NbSetupData->TAT; + SaPlatformPolicyPpi->MemConfig->MEMTST = NbSetupData->MEMTST; + SaPlatformPolicyPpi->MemConfig->DIMMODTT1D = NbSetupData->DIMMODTT1D; + SaPlatformPolicyPpi->MemConfig->WRSRT = NbSetupData->WRSRT; + SaPlatformPolicyPpi->MemConfig->DIMMRONT = NbSetupData->DIMMRONT; + SaPlatformPolicyPpi->MemConfig->ALIASCHK = NbSetupData->ALIASCHK; + SaPlatformPolicyPpi->MemConfig->RCVENC1D = NbSetupData->RCVENC1D; + SaPlatformPolicyPpi->MemConfig->RMC = NbSetupData->RMC; + + /// + /// Channel Hash Configuration + /// + SaPlatformPolicyPpi->MemConfig->ChHashEnable = NbSetupData->ChHashEnable; + SaPlatformPolicyPpi->MemConfig->ChHashMask = NbSetupData->ChHashMask; + SaPlatformPolicyPpi->MemConfig->ChHashInterleaveBit = NbSetupData->ChHashInterleaveBit; + + /// + /// MrcUltPoSafeConfig + /// 1 to enable, 0 to disable + /// +// SaPlatformPolicyPpi->MemConfig->MrcUltPoSafeConfig = 0; + + if (GetPchSeries() == PchLp) { + /// + /// Interleaving mode of DQ/DQS pins - depends on board routing + /// + SaPlatformPolicyPpi->MemConfig->DqPinsInterleaved = NbSetupData->DqPinsInterleaved; + } + + // Get the Graphics configuration from the NbSetupData + SaPlatformPolicyPpi->GtConfig->IgdDvmt50PreAlloc = NbSetupData->IgdDvmt50PreAlloc; + + if (GetPchSeries() == PchLp) { + NbSetupData->AlwaysEnablePeg = 2; + } + + if (NbSetupData->AlwaysEnablePeg != 0) DisablePegDevices(); + + //if AlwaysEnablePeg Auto and Enable send to Policy , disable device + switch (NbSetupData->AlwaysEnablePeg) { + case 0: + case 1: + SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg = NbSetupData->AlwaysEnablePeg; + break; + case 2: + // Disable Link + for (i = 0; NBPcieBridge[i] != 0xFFFFFFFF; i++) + { + if (READ_MEM32(NBPcieBridge[i]) == 0xFFFFFFFF) continue; + SET_MEM8((NBPcieBridge[i] + R_SA_PEG_LCTL_OFFSET), BIT04); + SET_MEM8 ((NBPcieBridge[i] + R_SA_PEG_DEBUP2_OFFSET), BIT0); + SET_MEM32 ((NBPcieBridge[i] + R_SA_PEG_PEGCOMLCGCTRL_OFFSET), BIT30); + + } + // Disable PEG + RESET_PCI16_NB(R_SA_DEVEN, (B_SA_DEVEN_D1F0EN_MASK | B_SA_DEVEN_D1F1EN_MASK | B_SA_DEVEN_D1F2EN_MASK)); // 0x54 + break; + } + + SaPlatformPolicyPpi->GtConfig->InternalGraphics = NbSetupData->InternalGraphics; + SaPlatformPolicyPpi->GtConfig->PrimaryDisplay = NbSetupData->PrimaryDisplay; + SaPlatformPolicyPpi->GtConfig->ApertureSize = NbSetupData->ApertureSize; + + // Control for enabling/disabling VDD force bit (Required only for early enabling of eDP panel) + SaPlatformPolicyPpi->GtConfig->PanelPowerEnable = NbSetupData->PanelPowerEnable; + + SaPlatformPolicyPpi->GtConfig->GttSize = NbSetupData->GTTSize; + SaPlatformPolicyPpi->GtConfig->GttMmAdr = NB_TEMP_MMIO_BASE; + + // Get the PciExpress Configuration from the NbSetupData + SaPlatformPolicyPpi->PcieConfig->DmiVc1 = NbSetupData->DmiVc1; + SaPlatformPolicyPpi->PcieConfig->DmiVcp = NbSetupData->DmiVcp; + SaPlatformPolicyPpi->PcieConfig->DmiVcm = NbSetupData->DmiVcm; + SaPlatformPolicyPpi->PcieConfig->DmiGen2 = NbSetupData->DmiGen2; + + SaPlatformPolicyPpi->PcieConfig->PegGenx[0] = NbSetupData->PegGenx0; + SaPlatformPolicyPpi->PcieConfig->PegGenx[1] = NbSetupData->PegGenx1; + SaPlatformPolicyPpi->PcieConfig->PegGenx[2] = NbSetupData->PegGenx2; + + for (i = 0; i < SA_PEG_MAX_FUN; i++) { + SaPlatformPolicyPpi->PcieConfig->PowerDownUnusedBundles[i] = NbSetupData->PowerDownUnusedBundles[i]; + } + + + // UserBd = Mobile - 0; Desktop/UpServer - 1; ULT - 5; + if(IS_SA_DEVICE_ID_MOBILE (McDeviceId)) { + SaPlatformPolicyPpi->PlatformData->UserBd = btCRBMB; + } else { + if (GetPchSeries() == PchLp) { + SaPlatformPolicyPpi->PlatformData->UserBd = btUser4; + } else { + SaPlatformPolicyPpi->PlatformData->UserBd = btCRBDT; + } + } + + SaPlatformPolicyPpi->MemConfig->SpdProfileSelected = NbSetupData->SpdProfileSelected; + SaPlatformPolicyPpi->MemConfig->NModeSupport = NbSetupData->NModeSupport; + SaPlatformPolicyPpi->MemConfig->RMT = NbSetupData->RmtCrosserEnable; + +#ifdef EFI_DEBUG +#if MRC_DEBUG_PRINT_SUPPORT + SaPlatformPolicyPpi->MemConfig->MrcTimeMeasure = FALSE; + SaPlatformPolicyPpi->MemConfig->SerialDebug = MSG_LEVEL_NOTE; +#else // #if MRC_DEBUG_PRINT_SUPPORT + SaPlatformPolicyPpi->MemConfig->MrcTimeMeasure = FALSE; + SaPlatformPolicyPpi->MemConfig->SerialDebug = MSG_LEVEL_WARNING; +#endif // #if MRC_DEBUG_PRINT_SUPPORT +#else // EFI_DEBUG + SaPlatformPolicyPpi->MemConfig->MrcTimeMeasure = FALSE; + SaPlatformPolicyPpi->MemConfig->SerialDebug = MSG_LEVEL_NEVER; +#endif // EFI_DEBUG + + SaPlatformPolicyPpi->MemConfig->DDR3Voltage = 0; + SaPlatformPolicyPpi->MemConfig->DDR3VoltageWaitTime = NbSetupData->DDRVoltageWaitTime; + SaPlatformPolicyPpi->MemConfig->RefClk = 0; + SaPlatformPolicyPpi->MemConfig->Ratio = 0; + + // + // Thermal Management Configuration + // + SaPlatformPolicyPpi->MemConfig->ThermalManagement = NbSetupData->MemoryThermalManagement; + SaPlatformPolicyPpi->MemConfig->PeciInjectedTemp = NbSetupData->PeciInjectedTemp; + SaPlatformPolicyPpi->MemConfig->ExttsViaTsOnBoard = NbSetupData->ExttsViaTsOnBoard; + SaPlatformPolicyPpi->MemConfig->ExttsViaTsOnDimm = NbSetupData->ExttsViaTsOnBoard; + SaPlatformPolicyPpi->MemConfig->VirtualTempSensor = NbSetupData->VirtualTempSensor; + /// + /// Options for Thermal settings + /// + SaPlatformPolicyPpi->MemConfig->EnableExtts = NbSetupData->EnableExtts; + SaPlatformPolicyPpi->MemConfig->EnableCltm = NbSetupData->EnableCltm; + SaPlatformPolicyPpi->MemConfig->EnableOltm = NbSetupData->EnableOltm; + SaPlatformPolicyPpi->MemConfig->EnablePwrDn = NbSetupData->EnablePwrDn; + SaPlatformPolicyPpi->MemConfig->Refresh2X = NbSetupData->Refresh2XMode; + SaPlatformPolicyPpi->MemConfig->LpddrThermalSensor = NbSetupData->LpddrThermalSensor; + SaPlatformPolicyPpi->MemConfig->LockPTMregs = NbSetupData->LockPTMregs; + SaPlatformPolicyPpi->MemConfig->UserPowerWeightsEn = NbSetupData->UserPowerWeightsEn; + + SaPlatformPolicyPpi->MemConfig->EnergyScaleFact = NbSetupData->EnergyScaleFact; + SaPlatformPolicyPpi->MemConfig->RaplPwrFlCh1 = NbSetupData->RaplPwrFlCh1; + SaPlatformPolicyPpi->MemConfig->RaplPwrFlCh0 = NbSetupData->RaplPwrFlCh0; + + SaPlatformPolicyPpi->MemConfig->RaplLim2Lock = NbSetupData->RaplLim2Lock; + SaPlatformPolicyPpi->MemConfig->RaplLim2WindX = NbSetupData->RaplLim2WindX; + SaPlatformPolicyPpi->MemConfig->RaplLim2WindY = NbSetupData->RaplLim2WindY; + SaPlatformPolicyPpi->MemConfig->RaplLim2Ena = NbSetupData->RaplLim2Ena; + SaPlatformPolicyPpi->MemConfig->RaplLim2Pwr = NbSetupData->RaplLim2Pwr; + SaPlatformPolicyPpi->MemConfig->RaplLim1WindX = NbSetupData->RaplLim1WindX; + SaPlatformPolicyPpi->MemConfig->RaplLim1WindY = NbSetupData->RaplLim1WindY; + SaPlatformPolicyPpi->MemConfig->RaplLim1Ena = NbSetupData->RaplLim1Ena; + SaPlatformPolicyPpi->MemConfig->RaplLim1Pwr = NbSetupData->RaplLim1Pwr; + + SaPlatformPolicyPpi->MemConfig->WarmThresholdCh0Dimm0 = NbSetupData->WarmThresholdCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->WarmThresholdCh0Dimm1 = NbSetupData->WarmThresholdCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->WarmThresholdCh1Dimm0 = NbSetupData->WarmThresholdCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->WarmThresholdCh1Dimm1 = NbSetupData->WarmThresholdCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->HotThresholdCh0Dimm0 = NbSetupData->HotThresholdCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->HotThresholdCh0Dimm1 = NbSetupData->HotThresholdCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->HotThresholdCh1Dimm0 = NbSetupData->HotThresholdCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->HotThresholdCh1Dimm1 = NbSetupData->HotThresholdCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->WarmBudgetCh0Dimm0 = NbSetupData->WarmBudgetCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->WarmBudgetCh0Dimm1 = NbSetupData->WarmBudgetCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->WarmBudgetCh1Dimm0 = NbSetupData->WarmBudgetCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->WarmBudgetCh1Dimm1 = NbSetupData->WarmBudgetCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->HotBudgetCh0Dimm0 = NbSetupData->HotBudgetCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->HotBudgetCh0Dimm1 = NbSetupData->HotBudgetCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->HotBudgetCh1Dimm0 = NbSetupData->HotBudgetCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->HotBudgetCh1Dimm1 = NbSetupData->HotBudgetCh1Dimm1; + + SaPlatformPolicyPpi->MemConfig->IdleEnergyCh0Dimm1 = NbSetupData->IdleEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->IdleEnergyCh0Dimm0 = NbSetupData->IdleEnergyCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->PdEnergyCh0Dimm1 = NbSetupData->PdEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->PdEnergyCh0Dimm0 = NbSetupData->PdEnergyCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->ActEnergyCh0Dimm1 = NbSetupData->ActEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->ActEnergyCh0Dimm0 = NbSetupData->ActEnergyCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->RdEnergyCh0Dimm1 = NbSetupData->RdEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->RdEnergyCh0Dimm0 = NbSetupData->RdEnergyCh0Dimm0; + SaPlatformPolicyPpi->MemConfig->WrEnergyCh0Dimm1 = NbSetupData->WrEnergyCh0Dimm1; + SaPlatformPolicyPpi->MemConfig->WrEnergyCh0Dimm0 = NbSetupData->WrEnergyCh0Dimm0; + + SaPlatformPolicyPpi->MemConfig->IdleEnergyCh1Dimm1 = NbSetupData->IdleEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->IdleEnergyCh1Dimm0 = NbSetupData->IdleEnergyCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->PdEnergyCh1Dimm1 = NbSetupData->PdEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->PdEnergyCh1Dimm0 = NbSetupData->PdEnergyCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->ActEnergyCh1Dimm1 = NbSetupData->ActEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->ActEnergyCh1Dimm0 = NbSetupData->ActEnergyCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->RdEnergyCh1Dimm1 = NbSetupData->RdEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->RdEnergyCh1Dimm0 = NbSetupData->RdEnergyCh1Dimm0; + SaPlatformPolicyPpi->MemConfig->WrEnergyCh1Dimm1 = NbSetupData->WrEnergyCh1Dimm1; + SaPlatformPolicyPpi->MemConfig->WrEnergyCh1Dimm0 = NbSetupData->WrEnergyCh1Dimm0; + + SaPlatformPolicyPpi->MemConfig->SrefCfgEna = NbSetupData->SrefCfgEna; + SaPlatformPolicyPpi->MemConfig->SrefCfgIdleTmr = NbSetupData->SrefCfgIdleTmr; + SaPlatformPolicyPpi->MemConfig->ThrtCkeMinDefeat = NbSetupData->ThrtCkeMinDefeat; + SaPlatformPolicyPpi->MemConfig->ThrtCkeMinTmr = NbSetupData->ThrtCkeMinTmr; + + if (GetPchSeries() == PchLp) { + SaPlatformPolicyPpi->MemConfig->ThrtCkeMinDefeatLpddr = NbSetupData->ThrtCkeMinDefeatLpddr; + SaPlatformPolicyPpi->MemConfig->ThrtCkeMinTmrLpddr = NbSetupData->ThrtCkeMinTmrLpddr; + SaPlatformPolicyPpi->MemConfig->EnablePwrDnLpddr = NbSetupData->EnablePwrDnLpddr; + } + + + // + // Scrambler + // + SaPlatformPolicyPpi->MemConfig->ScramblerSupport = NbSetupData->ScramblerSupport; + + // + // Power Mode Setting + // + SaPlatformPolicyPpi->MemConfig->ForceColdReset = NbSetupData->ForceColdReset; + // + // Channel DIMM Disable + // + SaPlatformPolicyPpi->MemConfig->DisableDimmChannel[0] = NbSetupData->DisableDimmChannel0; + SaPlatformPolicyPpi->MemConfig->DisableDimmChannel[1] = NbSetupData->DisableDimmChannel1; + + SaPlatformPolicyPpi->MemConfig->AutoSelfRefreshSupport = NbSetupData->AutoSelfRefreshSupport; + SaPlatformPolicyPpi->MemConfig->ExtTemperatureSupport = NbSetupData->ExtTemperatureSupport; + + /// + /// Options for MC Register Offsets + /// + SaPlatformPolicyPpi->MemConfig->CAVrefCtlOffset = NbSetupData->CAVrefCtlOffset; + SaPlatformPolicyPpi->MemConfig->Ch0VrefCtlOffset = NbSetupData->Ch0VrefCtlOffset; + SaPlatformPolicyPpi->MemConfig->Ch1VrefCtlOffset = NbSetupData->Ch1VrefCtlOffset; + SaPlatformPolicyPpi->MemConfig->Ch0ClkPiCodeOffset = NbSetupData->Ch0ClkPiCodeOffset; + SaPlatformPolicyPpi->MemConfig->Ch1ClkPiCodeOffset = NbSetupData->Ch1ClkPiCodeOffset; + SaPlatformPolicyPpi->MemConfig->Ch0RcvEnOffset = NbSetupData->Ch0RcvEnOffset; + SaPlatformPolicyPpi->MemConfig->Ch0RxDqsOffset = NbSetupData->Ch0RxDqsOffset; + SaPlatformPolicyPpi->MemConfig->Ch0TxDqOffset = NbSetupData->Ch0TxDqOffset; + SaPlatformPolicyPpi->MemConfig->Ch0TxDqsOffset = NbSetupData->Ch0TxDqsOffset; + SaPlatformPolicyPpi->MemConfig->Ch0VrefOffset = NbSetupData->Ch0VrefOffset; + SaPlatformPolicyPpi->MemConfig->Ch1RcvEnOffset = NbSetupData->Ch1RcvEnOffset; + SaPlatformPolicyPpi->MemConfig->Ch1RxDqsOffset = NbSetupData->Ch1RxDqsOffset; + SaPlatformPolicyPpi->MemConfig->Ch1TxDqOffset = NbSetupData->Ch1TxDqOffset; + SaPlatformPolicyPpi->MemConfig->Ch1TxDqsOffset = NbSetupData->Ch1TxDqsOffset; + SaPlatformPolicyPpi->MemConfig->Ch1VrefOffset = NbSetupData->Ch1VrefOffset; + + // + // Initialize the 16bit CMOS location for scrambling seed storage when iFFS is enabled + // + SaPlatformPolicyPpi->ScramblerSeedCmosLocation = NB_CMOS_IFFS_SCRAMBLER_SEED; + + SaPlatformPolicyPpi->MemConfig->RemapEnable = NbSetupData->RemapEnable; + +#ifdef BDAT_SUPPORT + SaPlatformPolicyPpi->MemConfig->RmtBdatEnable = NbSetupData->BdatAcpiTableSupport; +#endif + + SaPlatformPolicyPpi->PcieConfig->PegGen3Equalization = NbSetupData->PegGen3Equalization; + + // + // PEG Sampler Calibration: 0 = Disabled, 1 = Enabled, 2 = Auto (default) + // + SaPlatformPolicyPpi->PcieConfig->PegSamplerCalibrate = NbSetupData->PegSamplerCalibrate;; + + // + // PEG Gen3 Equalization Phase 2: 0 = Disabled (default), 1 = Enabled + // + SaPlatformPolicyPpi->PcieConfig->PegGen3EqualizationPhase2 = NbSetupData->PegGen3EqualizationPhase2; + + // + // PEG Gen3 Preset Search: 0 = Disabled (default), 1 = Enabled + // PEG Gen3 Preset Search dwell time: 400 ms + // PEG Gen3 Preset Search Margin Steps: 2 + // PEG Gen3 Preset Search Start Margin: 15 + // PEG Gen3 Preset Search Error Target: 4 + // + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearch = NbSetupData->PegGen3PresetSearch; + SaPlatformPolicyPpi->PcieConfig->PegGen3ForcePresetSearch = NbSetupData->PegGen3ForcePresetSearch; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchDwellTime = NbSetupData->PegGen3PresetSearchDwellTime; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchMarginSteps = NbSetupData->PegGen3PresetSearchMarginSteps; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchStartMargin = NbSetupData->PegGen3PresetSearchStartMargin; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchVoltageMarginSteps = NbSetupData->PegGen3PresetSearchVoltageMarginSteps; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchVoltageStartMargin = NbSetupData->PegGen3PresetSearchVoltageStartMargin; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchFavorTiming = NbSetupData->PegGen3PresetSearchFavorTiming; + SaPlatformPolicyPpi->PcieConfig->PegGen3PresetSearchErrorTarget = NbSetupData->PegGen3PresetSearchErrorTarget; + + for (i = 0; i < 16; i++) { + // RP preset goes to bits [3:0] and [19:16] + // EP preset goes to bits [11:8] and [27:24] + // EP hint goes to bits [14:12] and [30:28] + SaPlatformPolicyPpi->PcieConfig->Gen3RootPortPreset[i] = NbSetupData->Gen3RootPortPreset[i]; + SaPlatformPolicyPpi->PcieConfig->Gen3EndPointPreset[i] = NbSetupData->Gen3EndPointPreset[i]; + SaPlatformPolicyPpi->PcieConfig->Gen3EndPointHint[i] = NbSetupData->Gen3EndPointHint[i]; + } + + /// + /// Parameters for PCIe ASPM flow control + /// InitPcieAspmAfterOprom: + /// 0 (default) - PCIe ASPM will be initialized Before Oprom + /// 1 - PCIe ASPM will be initialized After Oprom (required IOTRAP SMI handler) + /// Note: This setting should match supported mode! + /// + /// SaIotrapSmiAddress: + /// IOTRAP SMI address for SA SMI callback handler. This should be given if platform supports InitPcieAspmAfterOprom = 1 scenario (SaLateInitSmm driver was compiled) + /// + SaPlatformPolicyPpi->PcieConfig->InitPcieAspmAfterOprom = NbSetupData->InitPcieAspmAfterOprom; + SaPlatformPolicyPpi->PcieConfig->SaIotrapSmiAddress = NB_IOTRAP_SMI_ADDRESSE; + + /// + /// Parameters for PCIe Gen3 device reset + /// + SaPlatformPolicyPpi->PcieConfig->PegGpioData->GpioSupport = NbSetupData->AllowPerstGpioUsage; + if (SaPlatformPolicyPpi->PcieConfig->PegGpioData->GpioSupport) { + /// + /// PEG Reset: GPIO 50, Active Low (Mobile PDG) + /// + SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Value = NbSetupData->AllowPerstGpio; + SaPlatformPolicyPpi->PcieConfig->PegGpioData->SaPegReset->Active = NbSetupData->AllowPerstGpioActive; + } + + /// + /// Enable/Disable RxCEM Loop back + /// 1=Enable, 0=Disable (default) + /// When enabled, Lane for loop back should be selected (0 ~ 15 and default is Lane 0) + /// + SaPlatformPolicyPpi->PcieConfig->RxCEMLoopback = NbSetupData->RxCEMLoopback; + SaPlatformPolicyPpi->PcieConfig->RxCEMLoopbackLane = NbSetupData->RxCEMLoopbackLane; + + /// + /// Gen3 RxCTLE peaking default is 8 + /// + for (i = 0; i < SA_PEG_MAX_BUNDLE; i++) { + SaPlatformPolicyPpi->PcieConfig->Gen3RxCtleP[i] = NbSetupData->Gen3RxCtleP[i]; + } + + /// + /// Initialize the SA PEG Data pointer for saved preset search results + /// + SaPlatformPolicyPpi->PcieConfig->PegDataPtr = NULL; + + SaPlatformPolicyPpi->PcieConfig->PegSwingControl = NbSetupData->SwingControl; + + SaPlatformPolicyPpi->PcieConfig->PegComplianceTestingMode = NbSetupData->PegComplianceTestingMode; + + + // + // Read DDR Frequecy setting selected in Bios setup + // + switch (NbSetupData->DdrFreqLimit) { + case DDR3_FREQ_1067: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 1067; + break; + + case DDR3_FREQ_1333: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 1333; + break; + + case DDR3_FREQ_1600: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 1600; + break; + + case DDR3_FREQ_1867: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 1867; + break; + + case DDR3_FREQ_2133: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 2133; + break; + + case DDR3_FREQ_2400: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 2400; + break; + + case DDR3_FREQ_2667: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 2667; + break; + + case DDR3_FREQ_AUTO: + default: + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 0; + break; + + } + +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 0 +{ + WDT_PPI *WdtPpi = NULL; + UINT8 WdtFlag = V_PCH_OC_WDT_CTL_STATUS_FAILURE; + + // + // Locate WDT PPI for access to Wdt->CheckStatus() + // + Status = (*PeiServices)->LocatePpi ( + PeiServices, + &gWdtPpiGuid, + 0, + NULL, + &WdtPpi + ); + if (!EFI_ERROR (Status)) { + WdtFlag = WdtPpi->CheckStatus(); + } + + if (WdtFlag == V_PCH_OC_WDT_CTL_STATUS_OK) { + if(NbSetupData->SpdProfileSelected == 1) { // UserDefault + if(NbSetupData->OcDdrFreqLimit != 0) + + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = NbSetupData->OcDdrFreqLimit; + // if (SettingData.MemoryClockMultiplier == 100) + // SaPlatformPolicyPpi->MemConfig->RefClk = MRC_REF_CLOCK_100; + + SaPlatformPolicyPpi->MemConfig->Ratio = \ + NbFrequencyToRatio(SaPlatformPolicyPpi->MemConfig->DdrFreqLimit, MRC_REF_CLOCK_133, SaPlatformPolicyPpi->MemConfig->BClkFrequency);//SaPlatformPolicyPpi->MemConfig->RefClk); + + SaPlatformPolicyPpi->MemConfig->tCL = NbSetupData->tCL; + SaPlatformPolicyPpi->MemConfig->tCWL = NbSetupData->tCWL; + SaPlatformPolicyPpi->MemConfig->tFAW = NbSetupData->tFAW; + SaPlatformPolicyPpi->MemConfig->tRAS = NbSetupData->tRAS; + SaPlatformPolicyPpi->MemConfig->tRC = NbSetupData->tRC; + SaPlatformPolicyPpi->MemConfig->tRCD = NbSetupData->tRCD; + SaPlatformPolicyPpi->MemConfig->tREFI = NbSetupData->tREFI; + SaPlatformPolicyPpi->MemConfig->tRFC = NbSetupData->tRFC; + SaPlatformPolicyPpi->MemConfig->tRP = NbSetupData->tRP; + SaPlatformPolicyPpi->MemConfig->tRRD = NbSetupData->tRRD; + SaPlatformPolicyPpi->MemConfig->tRTP = NbSetupData->tRTP; + SaPlatformPolicyPpi->MemConfig->tWR = NbSetupData->tWR; + SaPlatformPolicyPpi->MemConfig->tWTR = NbSetupData->tWTR; +// SaPlatformPolicyPpi->MemConfig->tWTR = NbSetupData->tRPab; + + } else if (SaPlatformPolicyPpi->MemConfig->SpdProfileSelected >= 2) { // XMP + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 0; + } + +#ifndef EFI_DEBUG + if (WdtPpi != NULL && SaPlatformPolicyPpi->MemConfig->SpdProfileSelected != 0) { + WdtPpi->ReloadAndStart (10); // 10 Sec + } +#endif + + } else if (WdtFlag == V_PCH_OC_WDT_CTL_STATUS_FAILURE) { + SaPlatformPolicyPpi->MemConfig->SpdProfileSelected = 0; // Auto + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = 0; + } +} +#endif +// (P20121012A) >> Update XTU 4.0 +#if defined PERF_TUNE_SUPPORT && PERF_TUNE_SUPPORT == 1 +#if defined IXTU_LABLE_VERSION && IXTU_LABLE_VERSION >= 0x00C +{ + PERF_TUNE_PPI *PerfTunePpi; + BIOS_SETTING_DATA SettingData; + + Status = (*PeiServices)->LocatePpi( + PeiServices, + &gPerfTunePpiGuid, + 0, + NULL, + &PerfTunePpi); + if (EFI_ERROR(Status)) + { + ASSERT_PEI_ERROR(PeiServices, Status); + }else{ + + Status = PerfTunePpi->GetSettingData(PeiServices, &SettingData); + if((!EFI_ERROR (Status)) && (!PerfTunePpi->IsRunDefault(PeiServices))) + { + + SaPlatformPolicyPpi->MemConfig->SpdProfileSelected = (UINT8)SettingData.XmpProfilesSelect; + if (SettingData.XmpProfilesSelect == 1) { // UserDefault + + + if (SettingData.MemoryClockMultiplier == 100) + SaPlatformPolicyPpi->MemConfig->RefClk = MRC_REF_CLOCK_100; + + SaPlatformPolicyPpi->MemConfig->Ratio = (UINT8)SettingData.DDRMul / 2; + + SaPlatformPolicyPpi->MemConfig->DdrFreqLimit = \ + NbRatioToFrequency(SaPlatformPolicyPpi->MemConfig->Ratio, SaPlatformPolicyPpi->MemConfig->RefClk, SaPlatformPolicyPpi->MemConfig->BClkFrequency); + + SaPlatformPolicyPpi->MemConfig->tCL = SettingData.tCL; + SaPlatformPolicyPpi->MemConfig->tCWL = SettingData.tCWL; + SaPlatformPolicyPpi->MemConfig->tFAW = SettingData.tFAW; + SaPlatformPolicyPpi->MemConfig->tRAS = SettingData.tRAS; + SaPlatformPolicyPpi->MemConfig->tRC = SettingData.tRC; + SaPlatformPolicyPpi->MemConfig->tRCD = SettingData.tRCD; + SaPlatformPolicyPpi->MemConfig->tREFI = SettingData.tREFI; + SaPlatformPolicyPpi->MemConfig->tRFC = SettingData.tRFC; + SaPlatformPolicyPpi->MemConfig->tRP = SettingData.tRP; + SaPlatformPolicyPpi->MemConfig->tRRD = SettingData.tRRD; + SaPlatformPolicyPpi->MemConfig->tRTP = SettingData.tRTP; + SaPlatformPolicyPpi->MemConfig->tWR = SettingData.tWR; + SaPlatformPolicyPpi->MemConfig->tWTR = SettingData.tWTR; + //SaPlatformPolicyPpi->MemConfig->tRPab = SettingData.tRPab; + } // SettingData.XmpProfilesSelect == 1 + + WRITE_MEM8_MCH(0x5990, (UINT8)SettingData.RuntimeTurbo); + + NbSetupData->GtOcSupport = 0; // if XTU is Enable, Default = disable. + if((SettingData.GraphicTurboRatioLimit!=0xFFFF)){ + NbSetupData->GtMaxOcTurboRatio = SettingData.GraphicTurboRatioLimit; + NbSetupData->GtExtraTurboVoltage = SettingData.GraphicsCoreVoltageOverride; + + NbSetupData->GtVoltageOverride = SettingData.GraphicsCoreVoltageOverride; + NbSetupData->GtVoltageMode = (UINT8)SettingData.GraphicsCoreVoltageMode; + // GT offset + if (SettingData.GraphicsCoreVoltageOffset >=0 && \ + SettingData.GraphicsCoreVoltageOffset <= 999){ + NbSetupData->GtVoltageOffset = ~(1000 - SettingData.GraphicsCoreVoltageOffset) + 1; + }else if (SettingData.GraphicsCoreVoltageOffset >=1000 && \ + SettingData.GraphicsCoreVoltageOffset <= 1998){ + NbSetupData->GtVoltageOffset = SettingData.GraphicsCoreVoltageOffset - 1000; + } + // SA offset + if (SettingData.SystemAgentVoltageOffset >=0 && \ + SettingData.SystemAgentVoltageOffset <= 999){ + NbSetupData->SaVoltageOffset = ~(1000 - SettingData.SystemAgentVoltageOffset) + 1; + }else if (SettingData.SystemAgentVoltageOffset >=1000 && \ + SettingData.SystemAgentVoltageOffset <= 1998){ + NbSetupData->SaVoltageOffset = SettingData.SystemAgentVoltageOffset - 1000; + } + // IOA offset + if (SettingData.IOAnalogVoltageOffset >=0 && \ + SettingData.IOAnalogVoltageOffset <= 999){ + NbSetupData->IoaVoltageOffset = ~(1000 - SettingData.IOAnalogVoltageOffset) + 1; + }else if (SettingData.IOAnalogVoltageOffset >=1000 && \ + SettingData.IOAnalogVoltageOffset <= 1998){ + NbSetupData->IoaVoltageOffset = SettingData.IOAnalogVoltageOffset - 1000; + } + + // IOD offset + if (SettingData.IODigitalVoltageOffset >=0 && \ + SettingData.IODigitalVoltageOffset <= 999){ + NbSetupData->IodVoltageOffset = ~(1000 - SettingData.IODigitalVoltageOffset) + 1; + }else if (SettingData.IODigitalVoltageOffset >=1000 && \ + SettingData.IODigitalVoltageOffset <= 1998){ + NbSetupData->IodVoltageOffset = SettingData.IODigitalVoltageOffset - 1000; + } + NbSetupData->GtOcSupport = 1; + } + }else{ + NbSetupData->GtVoltageOffset = 0; + NbSetupData->GtVoltageOverride = 0; + NbSetupData->GtExtraTurboVoltage = 0; + NbSetupData->GtMaxOcTurboRatio = READ_MEM8_MCH(0x5998); + NbSetupData->SaVoltageOffset = 0; + NbSetupData->GtVoltageMode = 0; + NbSetupData->GtOcSupport = 1; + NbSetupData->IoaVoltageOffset = 0; + NbSetupData->IodVoltageOffset = 0; + } + } +} +#endif +#endif + + /// + /// Initialize the Overclocking Configuration + /// + if (NbSetupData->GtOcSupport == 0) + { + SaPlatformPolicyPpi->OcConfig->GtVoltageOffset = 0; + SaPlatformPolicyPpi->OcConfig->GtVoltageOverride = 0; + SaPlatformPolicyPpi->OcConfig->GtExtraTurboVoltage = 0; + SaPlatformPolicyPpi->OcConfig->GtMaxOcTurboRatio = 0; + SaPlatformPolicyPpi->OcConfig->SaVoltageOffset = 0; + SaPlatformPolicyPpi->OcConfig->GtVoltageMode = 0; + SaPlatformPolicyPpi->OcConfig->OcSupport = 0; + SaPlatformPolicyPpi->OcConfig->IoaVoltageOffset = 0; + SaPlatformPolicyPpi->OcConfig->IodVoltageOffset = 0; + } else { + SaPlatformPolicyPpi->OcConfig->GtVoltageOffset = NbSetupData->GtVoltageOffset; + SaPlatformPolicyPpi->OcConfig->GtVoltageOverride = NbSetupData->GtVoltageOverride; + SaPlatformPolicyPpi->OcConfig->GtExtraTurboVoltage = NbSetupData->GtExtraTurboVoltage; + SaPlatformPolicyPpi->OcConfig->GtMaxOcTurboRatio = NbSetupData->GtMaxOcTurboRatio; + SaPlatformPolicyPpi->OcConfig->SaVoltageOffset = NbSetupData->SaVoltageOffset; + SaPlatformPolicyPpi->OcConfig->GtVoltageMode = NbSetupData->GtVoltageMode; + SaPlatformPolicyPpi->OcConfig->OcSupport = 1; + SaPlatformPolicyPpi->OcConfig->IoaVoltageOffset = NbSetupData->IoaVoltageOffset; + SaPlatformPolicyPpi->OcConfig->IodVoltageOffset = NbSetupData->IodVoltageOffset; + } +// (P20121012A) << Update XTU 4.0 + // Make sure we have a PPI. + if (VariableServices != NULL) { + + // If Maximum TOLUD set to Dynamic assignment in BIOS setup, then set TOLUD/TOLM based on largest MMIO length of graphic controllers + if (NbSetupData->MaxTolud == NB_MAX_TOLUD_DYNAMIC) { + VariableSize = sizeof(UINT32); + Status = VariableServices->GetVariable( + VariableServices, + L"MemCeil.", + &gEfiNbMrcS3DataGuid, + NULL, + &VariableSize, + &MemoryCeiling); + + if(Status == EFI_NOT_FOUND) { + Status = VariableServices->GetVariable( + VariableServices, + L"MemCeil.", + &gEfiGlobalVariableGuid, + NULL, + &VariableSize, + &MemoryCeiling); + } + if(!EFI_ERROR(Status)) { + if(MemoryCeiling >= 0xE0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_3_5G; + } else if(MemoryCeiling >= 0xD0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_3_25G; + } else if(MemoryCeiling >= 0xC0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_3G; + } else if(MemoryCeiling >= 0xB0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_2_75G; + } else if(MemoryCeiling >= 0xA0000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_2_5G; + } else if(MemoryCeiling >= 0x90000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_2_25G; + } else if(MemoryCeiling >= 0x80000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_2G; + } else if(MemoryCeiling >= 0x70000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_1_75G; + } else if(MemoryCeiling >= 0x60000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_1_5G; + } else if(MemoryCeiling >= 0x50000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_1_25G; + } else if(MemoryCeiling >= 0x40000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_1G; + } else if(MemoryCeiling >= 0x30000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_0_75G; + } else if(MemoryCeiling <= 0x20000000) { + NbSetupData->MaxTolud = NB_MAX_TOLUD_0_5G; + } + } else { + NbSetupData->MaxTolud = NB_MAX_TOLUD_DYNAMIC; // default value + } + } + } + + // + // Based on BIOS setup to determine maximum top of memory size below 4G, and reserved for MMIO + // + switch (NbSetupData->MaxTolud) { + case NB_MAX_TOLUD_0_5G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xE00; + break; + + case NB_MAX_TOLUD_0_75G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xD00; + break; + + case NB_MAX_TOLUD_1G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xC00; + break; + + case NB_MAX_TOLUD_1_25G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xB00; + break; + + case NB_MAX_TOLUD_1_5G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0xA00; + break; + + case NB_MAX_TOLUD_1_75G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x900; + break; + + case NB_MAX_TOLUD_2G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x800; + break; + + case NB_MAX_TOLUD_2_25G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x700; + break; + + case NB_MAX_TOLUD_2_5G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x600; + break; + + case NB_MAX_TOLUD_2_75G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x500; + break; + + default: + + case NB_MAX_TOLUD_3G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x400; + break; + + case NB_MAX_TOLUD_3_25G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x300; + break; + + case NB_MAX_TOLUD_3_5G: + SaPlatformPolicyPpi->GtConfig->MmioSize = 0x200; + break; + } + + // EccSupport = 1 for UpSever and WS + if (!(IS_SA_DEVICE_ID_SERVER (McDeviceId) || IS_PCH_LPT_LPC_DEVICE_ID_SERVER(LpcDeviceId)) && + (IS_PCH_LPT_LPC_DEVICE_ID_MOBILE(LpcDeviceId) || IS_PCH_LPT_LPC_DEVICE_ID_DESKTOP(LpcDeviceId))) { + SaPlatformPolicyPpi->MemConfig->EccSupport = NbSetupData->EccSupport; + } else { + SaPlatformPolicyPpi->MemConfig->EccSupport = 1; + } + + // Get the Memory Configuration from NbSetupData + SaPlatformPolicyPpi->MemConfig->MaxTolud = NbSetupData->MaxTolud; + +#if defined SwitchableGraphics_SUPPORT && SwitchableGraphics_SUPPORT == 1 + if (NbSetupData->PrimaryDisplay == 4) // SG + { + SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg = 1; // Enable + SaPlatformPolicyPpi->GtConfig->PrimaryDisplay = 0; // IGFX + + /// + /// Initialize the Switchable Graphics Configuration + /// + /// + /// Switchable Graphics mode set as MUXLESS (By default) + /// + SaPlatformPolicyPpi->PlatformData->SgMode = SgModeMuxless; + SaPlatformPolicyPpi->PlatformData->SgSubSystemId = 0x2112; + + /// + /// Configure below based on the OEM platfrom design + /// Switchable Graphics GPIO support - 1=Supported 0=Not Supported + /// + SaPlatformPolicyPpi->SgGpioData->GpioSupport = SG_GPIO_SUPPORT; + + if (SaPlatformPolicyPpi->SgGpioData->GpioSupport) { + /// + /// Initialzie the GPIO Configuration + /// + if (GetPchSeries() == PchLp) { + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Value = GPIO_dGPU_PWROK_ULT; // dGPU PWROK GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Active = ACTIVE_dGPU_PWROK_ULT; // dGPU PWROK Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Value = GPIO_dGPU_HOLD_RST_ULT; // dGPU HLD RST GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Active = ACTIVE_dGPU_HOLD_RST_ULT; // dGPU HLD RST Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Value = GPIO_dGPU_PWR_EN_ULT; // dGPU PWR Enable GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Active = ACTIVE_dGPU_PWR_EN_ULT; // dGPU PWR Enable Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Value = GPIO_dGPU_PRSNT_ULT; // dGPU_PRSNT# GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Active = ACTIVE_dGPU_PRSNT_ULT; // dGPU_PRSNT# Active Low + + } else{ + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Value = GPIO_dGPU_PWROK; // dGPU PWROK GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrOK->Active = ACTIVE_dGPU_PWROK; // dGPU PWROK Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Value = GPIO_dGPU_HOLD_RST; // dGPU HLD RST GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuHoldRst->Active = ACTIVE_dGPU_HOLD_RST; // dGPU HLD RST Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Value = GPIO_dGPU_PWR_EN; // dGPU PWR Enable GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPwrEnable->Active = ACTIVE_dGPU_PWR_EN; // dGPU PWR Enable Active + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Value = GPIO_dGPU_PRSNT; // dGPU_PRSNT# GPIO assigned + SaPlatformPolicyPpi->SgGpioData->SgDgpuPrsnt->Active = ACTIVE_dGPU_PRSNT; // dGPU_PRSNT# Active Low + } + } + } +#endif + +#if (defined RC_PEG_0) && RC_PEG_0 == 1 + if (NbSetupData->DetectNonComplaint && NbSetupData->AlwaysEnablePeg != 2) + { + SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg = 1; // Enable + } +#endif + + if (GetPchSeries() == PchLp) { + SaPlatformPolicyPpi->PcieConfig->AlwaysEnablePeg = 2; + } + + // Make sure we have a PPI. + if (VariableServices != NULL) { + + // Get variable size first. + // Set VariableSize = 0 in order to get the required size. + VariableSize = 0; + MrcS3ResumeData = NULL; + + Status = VariableServices->GetVariable ( + VariableServices, + L"MrcS3Resume", + &gMemRestoreDataGuid, + NULL, + &VariableSize, + MrcS3ResumeData + ); + + // Should fail with EFI_BUFFER_TOO_SMALL + if (Status == EFI_BUFFER_TOO_SMALL) { + + // Allocate buffer for S3 data variable. + Status = (*PeiServices)->AllocatePool (PeiServices, VariableSize, &MrcS3ResumeData); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = VariableServices->GetVariable ( + VariableServices, + L"MrcS3Resume", + &gMemRestoreDataGuid, + NULL, + &VariableSize, + MrcS3ResumeData + ); + } + + if (Status == EFI_SUCCESS) { + // MemoryConfig variable memory layout: MRC_OutputParames, MRC_S3Params + // Increment the pointer, MrcS3ResumeData, to point to MRC_S3Params + SaPlatformPolicyPpi->S3DataPtr = MrcS3ResumeData; + } + + PegGen3Data = NULL; + VariableSize = sizeof(SA_PEG_DATA); + + // Allocate buffer for PegGen3PresetSearch data variable. + Status = (*PeiServices)->AllocatePool (PeiServices, VariableSize, &PegGen3Data); + ASSERT_PEI_ERROR (PeiServices, Status); + + Status = VariableServices->GetVariable ( + VariableServices, + L"PegGen3PresetSearchData", + &gAmiNbPegGen3PresetSearchGuid, + NULL, + &VariableSize, + PegGen3Data + ); + + if (Status == EFI_SUCCESS) { + // Increment the pointer, PegGen3PresetSearch Data, to point to PegDataPtr + SaPlatformPolicyPpi->PcieConfig->PegDataPtr = PegGen3Data; + } + + } + + // Install SA Platform Policy PPI + Status = (**PeiServices).InstallPpi (PeiServices, SaPlatformPolicyPpiDesc); + ASSERT_PEI_ERROR (PeiServices, Status); + + return Status; +} + +#ifdef SSA_FLAG + +MrcStatus +AmiSsaCallbackPpi ( + EFI_PEI_SERVICES **PeiServices, + struct _SSA_BIOS_CALLBACKS_PPI *SsaBiosCallBacksPpi, + MRC_OEM_STATUS_COMMAND StatusCommand, + VOID *CheckpointData) +{ + EFI_STATUS Status; + PEI_MEMORY_ERROR_REPORT_PPI *MemoryErrorPpi; + + // if oem have reinstall gAmiMemoryErrorReportPpi, it can Locate AmiMemoryError for oem. + Status = (*PeiServices)->LocatePpi( + PeiServices, &gAmiMemoryErrorReportPpiGuid, 0, NULL, + &MemoryErrorPpi ); + + ASSERT_PEI_ERROR(PeiServices, Status); + + if (Status == EFI_SUCCESS) + MemoryErrorPpi->AmiMemoryErrorRead(PeiServices, MemoryErrorPpi, (UINT32)StatusCommand); + + return StatusCommand; +} +#endif // #ifndef SSA_FLAG +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: MemoryErrorRead +// +// Description: +// This function reports the error status after memory training. +// +// Parameters: +// IN EFI_PEI_SERVICES PeiServices - PEI Services table pointer +// IN PEI_MEMORY_ERROR_REPORT_PPI *This - Pointer to the PPI structure +// IN OUT UINT32 MemErrData - Pointer to error data buffer +// +// Returns: +// EFI_STATUS +// EFI_SUCCESS The function completed successfully. +// Notes: +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS +MemoryErrorRead ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_MEMORY_ERROR_REPORT_PPI *This, + IN OUT UINT32 MemErrData + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + switch (MemErrData) { + case MRC_MC_CONFIG_ERROR : + case MRC_MC_MEMORY_MAP_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_CONFIGURING, EFI_ERROR_MAJOR); + break; + case MRC_DIMM_RON_ERROR : + case MRC_DIMM_ODT_ERROR : + case MRC_WRITE_DS_ERROR : + case MRC_WRITE_SR_ERROR : + case MRC_WRITE_EQ_ERROR : + case MRC_READ_ODT_ERROR : + case MRC_READ_EQ_ERROR : + case MRC_READ_AMP_POWER_ERROR : + case MRC_CMP_OPT_ERROR : + case MRC_PWR_MTR_ERROR : + case MRC_SPD_PROCESSING_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_SPD_FAIL, EFI_ERROR_MAJOR); + break; + case MRC_RESET_ERROR : ///< before jedec reset + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_INVALID_TYPE, EFI_ERROR_MAJOR); + break; + case MRC_PRE_TRAINING_ERROR : + case MRC_EARLY_COMMAND_ERROR : + case MRC_JEDEC_INIT_LPDDR3_ERROR : + case MRC_SENSE_AMP_OFFSET_ERROR : + case MRC_RECEIVE_ENABLE_ERROR : + case MRC_JEDEC_WRITE_LEVELING_ERROR : + case MRC_WRITE_TIMING_1D_ERROR : + case MRC_WRITE_TIMING_2D_ERROR : + case MRC_READ_TIMING_1D_ERROR : + case MRC_READ_TIMING_2D_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_INVALID_SPEED, EFI_ERROR_MAJOR); + break; + case MRC_ECC_CLEAN_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_ERROR, EFI_ERROR_MAJOR); + break; + case MRC_NO_MEMORY_DETECTED : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_NOT_DETECTED, EFI_ERROR_MAJOR); + break; + case MRC_MEM_INIT_DONE_WITH_ERRORS : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_TEST, EFI_ERROR_MAJOR); + break; + case MRC_WRITE_VREF_2D_ERROR : + case MRC_READ_VREF_2D_ERROR : + case MRC_LATE_COMMAND_ERROR : + case MRC_ROUND_TRIP_LAT_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_NONE_USEFUL, EFI_ERROR_MAJOR); + break; + case MRC_TURN_AROUND_ERROR : + case MRC_SAVE_MC_VALUES_ERROR : + case MRC_RMT_TOOL_ERROR : + case MRC_CPGC_MEMORY_TEST_ERROR : + case MRC_RESTORE_TRAINING_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_MISMATCH, EFI_ERROR_MAJOR); + break; + case MRC_SELF_REFRESH_EXIT_ERROR : + case MRC_MRC_NORMAL_MODE_ERROR : + case MRC_ALIAS_CHECK_ERROR : + case MRC_POST_TRAINING_ERROR : + case MRC_MC_ACTIVATE_ERROR : + case MRC_DONE_WITH_ERROR : + case MRC_FILL_RMT_STRUCTURE_ERROR : + PEI_ERROR_CODE(PeiServices, PEI_MEMORY_NOT_INSTALLED, EFI_ERROR_MAJOR); + break; + default : //Default to " N/A " + break; + } + + return Status; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBSMI.C b/Chipset/NB/NBSMI.C new file mode 100644 index 0000000..478ec8b --- /dev/null +++ b/Chipset/NB/NBSMI.C @@ -0,0 +1,996 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.C 5 10/14/12 12:17a Jeffch $ +// +// $Revision: 5 $ +// +// $Date: 10/14/12 12:17a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.C $ +// +// 5 10/14/12 12:17a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow MahoBay Update. +// [Files] NBSMI.c, NBSMI.Dxe +// +// 3 6/14/12 4:36a Yurenlai +// [TAG] None +// [Category] Improvement +// [Description] Fixed PEG PERR log lost issue. +// [Description] NBSMI.C +// +// 2 4/05/12 3:18a Yurenlai +// [TAG] EIP87103 +// [Category] Spec Update +// [Severity] Important +// [Description] Change for SystemAgent RefCode Revision: 0.5.5 . +// [Files] NBDxe.c, NBPEI.c, NBSMI.C, NBGeneric.cm NB.sd, NBSetup.c, +// GetSetupData.c, NbSetupData.h +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBSMI.c +// +// Description: This file contains code for all North Bridge SMI events +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Token.h> +#include <AmiDxeLib.h> +#include <Protocol\SmmBase.h> +#include <Protocol\SmmSwDispatch.h> +#include <Protocol\SmmSxDispatch.h> +#include <Protocol\NBPlatformData.h> +#include <AmiCspLib.h> +#include <Setup.h> +#if NB_ERROR_LOG_SUPPORT +#include <Edk\Foundation\Framework\Protocol\SmmIchnDispatch\SmmIchnDispatch.h> +#include <Protocol\SmbiosElogSupport.h> +#include <NBSMI.h> +#endif +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) +static BOOLEAN gEccErrHandleEnable = FALSE; +static BOOLEAN gPegErrHandleEnable = FALSE; +NB_ASL_BUFFER *gNbAslBufPtr = NULL; +NB_SETUP_DATA *gNbSetupData = NULL; +// GUID Definition(s) +#if NB_ERROR_LOG_SUPPORT +EFI_GUID gNbErrorLogDispatchProtocolGuid = EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL_GUID; +EFI_GUID gIchnDispatchProtocolGuid = EFI_SMM_ICHN_DISPATCH_PROTOCOL_GUID; +#endif +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) +#if NB_ERROR_LOG_SUPPORT +NB_ERROR_LOG_DISPATCH_LINK *gNbErrorLogDispatchHead = 0, *gNbErrorLogDispatchTail = 0; + +UINT32 NBPcieBridge[] = +{ + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN, PCI_VID)}, + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN1, PCI_VID)}, + {(UINT32)NB_PCIE_CFG_ADDRESS(PCIEBRN_BUS, PCIEBRN_DEV, PCIEBRN_FUN2, PCI_VID)}, + {0xFFFFFFFF} +}; + +EFI_STATUS NbErrorLogRegister ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_NB_ERROR_LOG_DISPATCH Function, + OUT EFI_HANDLE *Handle +); + +EFI_STATUS NbErrorLogUnregister ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle +); + +EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL gEfiNbErrorLogDispatchProtocol = \ + {NbErrorLogRegister, NbErrorLogUnregister}; + +NB_ERROR_INFO NbErrorInfo; +UINT32 DevBaseAddr = 0; + +#if NB_ECC_ERROR_LOG_SUPPORT +EFI_STATUS NBEccErrLogHandle(VOID); +#endif + +#endif + +#if NB_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: AddLink +// +// Description: Create and add link to specified list. +// +// Parameters: Size - +// Head - +// Tail - +// +// Returns: VOID Pointer +// +// Modified: +// +// Referrals: SmmAllocatePool +// +// Notes: Here is the control flow of this function: +// 1. Allocate Link in Smm Pool. +// 2. Add Link to end. +// 3. Return Link address. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID * AddLink ( + IN UINT32 Size, + IN VOID **Head, + IN VOID **Tail ) +{ + VOID *Link; + + if (pSmst->SmmAllocatePool(0, Size, &Link) != EFI_SUCCESS) return 0; + + ((GENERIC_LINK*)Link)->Link = 0; + if (!*Head) { + *Head = *Tail = Link; + } else { + ((GENERIC_LINK*)*Tail)->Link = Link; + *Tail = Link; + } + + return Link; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RemoveLink +// +// Description: Remove link from specified list. +// +// Parameters: Handle - EFI Handle +// Head - +// Tail - +// +// Returns: BOOLEAN +// TRUE if link was removed. FALSE if link not in the list. +// +// Modified: +// +// Referrals: SmmFreePool +// +// Notes: Here is the control flow of this function: +// 1. Search link list for Link. +// 2. Remove link from list. +// 3. Free link. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN RemoveLink ( + IN EFI_HANDLE Handle, + IN VOID **Head, + IN VOID **Tail ) +{ + GENERIC_LINK *PrevLink,*Link; + + PrevLink = *Head; + + // Is link first. Link address is the same as the Handle. + if (((GENERIC_LINK*)*Head) == Handle) { + if (PrevLink == *Tail) *Tail = 0; // If Tail = Head, then 0. + *Head = PrevLink->Link; + pSmst->SmmFreePool(PrevLink); + return TRUE; + } + + // Find Link. + for (Link=PrevLink->Link; Link; PrevLink=Link, Link=Link->Link) { + if (Link == Handle) { // Link address is the same as the Handle. + if (Link == *Tail) *Tail = PrevLink; + PrevLink->Link = Link->Link; + pSmst->SmmFreePool(Link); + return TRUE; + } + } + + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EfiNbErrorLogEnRegister +// +// Description: Register a Link on NbErrorLog enable SMI. +// +// Parameters: This - +// Function - +// Context - +// +// +// Returns: Handle - +// EFI_STATUS +// +// Modified: gNbErrorLogDispatchHead, gNbErrorLogDispatchTail +// +// Referrals: AddLink +// +// Notes: Here is the control flow of this function: +// 1. Verify if Context if valid. If invalid, +// return EFI_INVALID_PARAMETER. +// 2. Allocate structure and add to link list. +// 3. Fill link. +// 4. Enable Smi Source. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NbErrorLogRegister ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_NB_ERROR_LOG_DISPATCH Function, + OUT EFI_HANDLE *Handle ) +{ + NB_ERROR_LOG_DISPATCH_LINK *NewLink; + + NewLink = AddLink( sizeof(NB_ERROR_LOG_DISPATCH_LINK), \ + &gNbErrorLogDispatchHead, \ + &gNbErrorLogDispatchTail ); + if (!NewLink) return EFI_OUT_OF_RESOURCES; + + NewLink->Function = Function; + *Handle = NewLink; + +#if NB_ECC_ERROR_LOG_SUPPORT + if(((READ_PCI16_NB(0xC8) & (BIT00 | BIT01)) != 0) && gEccErrHandleEnable) + { + NBEccErrLogHandle(); + } +#endif + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbErrorLogUnregister +// +// Description: Unregister a Link on NbErrorLog enable SMI. +// +// Parameters: This - +// Handle - +// +// Returns: EFI_STATUS +// +// Modified: gNbErrorLogDispatchHead, gNbErrorLogDispatchTail +// +// Referrals: RemoveLink +// +// Notes: Here is the control flow of this function: +// 1. Remove link. If no link, return EFI_INVALID_PARAMETER. +// 2. Disable SMI Source if no other handlers using source. +// 3. Return EFI_SUCCESS. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NbErrorLogUnregister ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE Handle ) +{ + if (!RemoveLink(Handle, &gNbErrorLogDispatchHead, &gNbErrorLogDispatchTail)) + return EFI_INVALID_PARAMETER; + return EFI_SUCCESS; +} +#endif +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetNbSmiContext +// +// Description: This is a template NB SMI GetContext for Porting. +// +// Input: None +// +// Output: BOOLEAN +// +// Notes: Here is the control flow of this function: +// 1. Check if NB Smi source. +// 2. If yes, return TRUE. +// 3. If not, return FALSE. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetNbSmiContext (VOID) +{ + return FALSE; +} + +#if NB_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBPcieErrLogHandle +// +// Description: Init NB PCIE Error devices log. +// +// Input: VOID +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NBPcieErrLogHandle (VOID) +{ + EFI_STATUS Status = EFI_SUCCESS; + NB_ERROR_LOG_DISPATCH_LINK *Link; + UINT8 CapPtr; + UINT16 PciStatus; + UINT16 PcieStatus; + UINT16 DeviceStatus; + +// if (READ_IO8(NMI_SC_PORT) & BIT7) // SERR#_NMI_STS? +// { + + MemSet((VOID*)&NbErrorInfo, sizeof(NB_ERROR_INFO), 0); + + PciStatus = READ_MEM16(DevBaseAddr + 0x06); + PcieStatus = READ_MEM16(DevBaseAddr + 0x1E); + + CapPtr = NbFindCapPtr(DevBaseAddr, 0x10); + if (CapPtr != 0) + DeviceStatus = READ_MEM16(DevBaseAddr + CapPtr + 0x0A); + + if ((PciStatus & (BIT8 | BIT15)) || (PcieStatus & (BIT8 | BIT15))) + NbErrorInfo.PcieErrorInfo.ParityError = TRUE; + else + NbErrorInfo.PcieErrorInfo.ParityError = FALSE; + + if (READ_IO8(NMI_SC_PORT) & BIT7) // SERR#_NMI_STS? + { + if ((PciStatus & BIT14) || (PcieStatus & BIT14) || ((CapPtr != 0) && (DeviceStatus & 0x7))) + NbErrorInfo.PcieErrorInfo.SystemError = TRUE; + else + NbErrorInfo.PcieErrorInfo.SystemError = FALSE; + } + + if ((NbErrorInfo.PcieErrorInfo.ParityError) || (NbErrorInfo.PcieErrorInfo.SystemError)) + { + NbErrorInfo.PcieErrorInfo.Bus = (DevBaseAddr >> 20) & ((UINT8)((PCIEX_LENGTH >> 20) - 1)); + NbErrorInfo.PcieErrorInfo.Dev = (DevBaseAddr >> 15) & 0x1F; + NbErrorInfo.PcieErrorInfo.Fun = (DevBaseAddr >> 12) & 0x07; + NbErrorInfo.PcieErrorInfo.VendorId = READ_MEM16(DevBaseAddr + 0x00); + NbErrorInfo.PcieErrorInfo.DeviceId = READ_MEM16(DevBaseAddr + 0x02); + NbErrorInfo.PcieErrorInfo.PciCommand = READ_MEM16(DevBaseAddr + 0x04); + NbErrorInfo.PcieErrorInfo.PciCCode = READ_MEM16(DevBaseAddr + 0x0A); + NbErrorInfo.PcieErrorInfo.BridgeControl = READ_MEM16(DevBaseAddr + 0x3E); + NbErrorInfo.PcieErrorInfo.Version = READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0x0F; + NbErrorInfo.PcieErrorInfo.PortType = (UINT32)((READ_MEM8(DevBaseAddr + CapPtr + 0x02) & 0xF0) >> 4); + + if (CapPtr != 0) { + NbErrorInfo.PcieErrorInfo.Correctable = (DeviceStatus & BIT0)? TRUE : FALSE; + NbErrorInfo.PcieErrorInfo.NonFatal = (DeviceStatus & BIT1)? TRUE : FALSE; + NbErrorInfo.PcieErrorInfo.Fatal = (DeviceStatus & BIT2)? TRUE : FALSE; + } + + NbErrorInfo.ErrorType = NbPcieError; // PCIE Error + + // Clear Error status + WRITE_MEM16(DevBaseAddr + 0x06, PciStatus); + WRITE_MEM16(DevBaseAddr + 0x1E, PcieStatus); + + if (CapPtr != 0) + // Clear Error Status + WRITE_MEM16(DevBaseAddr + CapPtr + 0x0A, DeviceStatus); + + // Clear DMISERR + SET_IO16((TCO_BASE_ADDRESS + 0x04), BIT12); + + // Clear SERR#_NMI_STS & NMI2SMI_STS by set Port 61h[2] = 1 then set it to 0. + if(NbErrorInfo.PcieErrorInfo.SystemError) + { + SET_IO8(NMI_SC_PORT, BIT02); + RESET_IO8(NMI_SC_PORT, BIT02); + } + + for(Link = gNbErrorLogDispatchHead; Link; Link = Link->Link) { + Link->Function(Link, NbErrorInfo); + } + } +// }// SERR#_NMI_STS? +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetNbPcieContext +// +// Description: The function will check PCIE error event. +// +// Input: N/A +// +// Output: EFI_SUCCESS - ECC error event generated. +// Other - No ECC error event +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetNbPcieContext( +) +{ + UINT8 i; + + if(!gPegErrHandleEnable) return FALSE; + + for (i = 0; NBPcieBridge[i] != 0xFFFFFFFF; i++) + { + DevBaseAddr = NBPcieBridge[i]; + if (READ_MEM32(DevBaseAddr) == 0xFFFFFFFF) + continue; + + if(((READ_MEM16(DevBaseAddr + PCI_CMD) & (BIT6 | BIT8)) == (BIT6 | BIT8)) && + (((READ_MEM16(DevBaseAddr + 0x06) & (BIT08 | BIT14 | BIT15)) != 0) || + ((READ_MEM16(DevBaseAddr + 0x1E) & (BIT08 | BIT14 | BIT15)) != 0))) + { + return TRUE; + } + } + return FALSE; +} +#endif + +#if NB_ECC_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: EccEnableFunction +// +// Description: The function will check what ECC feature is enable or disable. +// +// Input: N/A +// +// Output: EFI_SUCCESS - ECC feature is support. +// EFI_UNSUPPORTED - ECC feature is not support +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS EccEnableFunction(VOID) +{ + if (((READ_MEM32_MCH(0x5004) & (BIT24 | BIT25)) != 0) || \ + ((READ_MEM32_MCH(0x5008) & (BIT24 | BIT25)) != 0)) + { + RW_MEM32_MCH(0x40B8, 0, (BIT14 | BIT16 | BIT17)); + RW_MEM32_MCH(0x44B8, 0, (BIT14 | BIT16 | BIT17)); + + // Disable Error and SCI Commands + RW_PCI16_NB(0xCA, 0, (BIT00 | BIT01)); + RW_PCI16_NB(0xCE, 0, (BIT00 | BIT01)); + + // Enable SMI Command +// RW_PCI16_NB(0xC8, (BIT00 | BIT01), 0); + RW_PCI16_NB(0xCC, (BIT00 | BIT01), 0); + + return EFI_SUCCESS; + } + + return EFI_UNSUPPORTED; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: GetNbEccContext +// +// Description: The function will check ECC error event. +// +// Input: N/A +// +// Output: EFI_SUCCESS - ECC error event generated. +// Other - No ECC error event +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +BOOLEAN GetNbEccContext(VOID) +{ + if (gEccErrHandleEnable) + { + if (((READ_PCI16_NB(0xCC) & (BIT00 | BIT01)) != 0) && + ((READ_PCI16_NB(0xC8) & (BIT00 | BIT01)) != 0)) + { + return TRUE; + } + } + + return FALSE; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBEccErrLogHandle +// +// Description: This function handles ECC error. +// +// Input: *This - NB SMI Context pointer +// +// Output: EFI_SUCCESS - ECC error is handled. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS NBEccErrLogHandle(VOID) +{ + + NB_ERROR_INFO NbErrorInfo; + NB_ERROR_LOG_DISPATCH_LINK *Link; + + MemSet((VOID*)&NbErrorInfo, sizeof(NB_ERROR_INFO), 0); + + if ((READ_MEM32_MCH(0x4CC8) & (BIT00 | BIT01)) != 0) + { + NbErrorInfo.EccErrorInfo.EccErrLog0 = READ_MEM32_MCH(0x4CC8); + NbErrorInfo.EccErrorInfo.EccErrLog1 = READ_MEM32_MCH(0x4CCC); + } + + // Channel 0 + if ((READ_MEM32_MCH(0x40C8) & (BIT00 | BIT01)) != 0) + { + NbErrorInfo.EccErrorInfo.Ch0_EccErrLog0 = READ_MEM32_MCH(0x40C8); + NbErrorInfo.EccErrorInfo.Ch0_EccErrLog1 = READ_MEM32_MCH(0x40CC); + // [28:27] 00 or 01 = DimmNum 0, 10 or 11 = DimmNum 1 + NbErrorInfo.EccErrorInfo.EccErrDimmNum = (READ_MEM32_MCH(0x40C8) & BIT28) ? 1 : 0; + } + + // Channel 1 + if ((READ_MEM32_MCH(0x44C8) & (BIT00 | BIT01)) != 0) + { + NbErrorInfo.EccErrorInfo.Ch1_EccErrLog0 = READ_MEM32_MCH(0x44C8); + NbErrorInfo.EccErrorInfo.Ch1_EccErrLog1 = READ_MEM32_MCH(0x44CC); + // [28:27] 00 or 01 = DimmNum 0, 10 or 11 = DimmNum 1 + NbErrorInfo.EccErrorInfo.EccErrDimmNum = (READ_MEM32_MCH(0x44C8) & BIT28) ? 3 : 2; + } + + if ((READ_PCI16_NB(0xC8) & BIT00) != 0) + NbErrorInfo.EccErrorInfo.Correctable = 1; + + if ((READ_PCI16_NB(0xC8) & BIT01) != 0) + NbErrorInfo.EccErrorInfo.UnCorrectable = 1; + + NbErrorInfo.ErrorType = NbEccError; // Ecc Error + + for(Link = gNbErrorLogDispatchHead; Link; Link = Link->Link) { + Link->Function(Link, NbErrorInfo); + } + + RW_PCI16_NB(0xC8, (BIT00 | BIT01), 0); + +#if ECC_MULTI_BIT_TYPE_HANG == 1 + if (NbErrorInfo.EccErrorInfo.UnCorrectable == 1){ + EFI_DEADLOOP() + } +#endif + + return EFI_SUCCESS; +} +#endif + +#if NB_ERROR_LOG_SUPPORT +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBErrLogHandler +// +// Description: North Bridge error logging handler. +// +// Input: DispatchHandle - Handle of dispatch function, for when interfacing +// with the parent SMM driver, will be the address of linked +// list link in the call back record. +// DispatchContext - Pointer to the dispatch function's context. +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID NBErrLogHandler ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_ICHN_DISPATCH_CONTEXT *DispatchContext +) +{ +//#if NB_PCIE_ERROR_LOG_SUPPORT +// if (GetNbPcieContext()) NBPcieErrLogHandle(); +//#endif +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbSmiHandler +// +// Description: This is a template NB SMI Handler for Porting. +// +// Input: None +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbSmiHandler (VOID) +{ + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbSwSmiIgfxGetSetupHandler +// +// Description: This is a NB software SMI Handler for IGFX int15 get setup data. +// +// Input: DispatchHandle - EFI Handle +// DispatchContext - Pointer to the EFI_SMM_SW_DISPATCH_CONTEXT +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbSwSmiIgfxGetSetupHandler ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SW_DISPATCH_CONTEXT *DispatchContext ) +{ + EFI_SMM_CPU_SAVE_STATE *pCpuSaveState = pSmst->CpuSaveState; + UINTN Cpu = pSmst->CurrentlyExecutingCpu - 1; + UINT8 RegBL; + + // Nb int 15 go to here + RegBL = (UINT8)pCpuSaveState[Cpu].Ia32SaveState.EBX; + + switch (RegBL) { + case IGFX_LCD_PANEL_TYPE: // 0x80 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->LcdPanelType; + break; + case IGFX_LCD_PANEL_SCALING: // 0x81 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->LcdPanelScaling; + break; + case IGFX_BOOT_TYPE: // 0x82 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->IgdBootType; + break; + case IGFX_BACKLIGHT_TYPE: // 0x83 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->IgdLcdBlc; + break; + case IGFX_LFP_PANEL_COLOR_DEPTH_TYPE: // 0x84 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->LfpColorDepth; + break; + case IGFX_EDP_ACTIVE_LFP_CONFIG_TYPE: // 0x85 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->ActiveLFP; + break; + case IGFX_PRIMARY_DISPLAY_TYPE: // 0x86 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->PrimaryDisplay; + break; + case IGFX_DISPLAY_PIPE_B_TYPE: // 0x87 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->DisplayPipeB; + break; + case IGFX_SDVO_PANEL_TYPE: // 0x88 + pCpuSaveState[Cpu].Ia32SaveState.EBX = (UINT8)gNbSetupData->SdvoPanelType; + break; + default: + break; + } // switch + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbSxSmiHandler +// +// Description: This is a template NB Sx SMI Handler for Porting. +// +// Input: DispatchHandle - EFI Handle +// DispatchContext - Pointer to the EFI_SMM_SX_DISPATCH_CONTEXT +// +// Output: None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +VOID NbSxSmiHandler ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_SX_DISPATCH_CONTEXT *DispatchContext ) +{ +/* + // SMBAVUMA Workaround + WRITE_IO8(0x3c4, 0x01); + SET_IO8(0x3c5, 0x20); +*/ +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NbChildDispatcher +// +// Description: North Bridge SMM Child Dispatcher Handler. +// +// Input: SmmImageHandle - +// *CommunicationBuffer - OPTIONAL +// *SourceSize - OPTIONAL +// +// Output: EFI_STATUS +// +// Modified: +// +// Referrals: EfiSmmSwDispatch EfiSmmSxDispatch +// +// Notes: Here is the control flow of this function: +// 1. Read SMI source status registers. +// 2. If source, call handler. +// 3. Repeat #2 for all sources registered. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NbChildDispatcher ( + IN EFI_HANDLE SmmImageHandle, + IN OUT VOID *CommunicationBuffer OPTIONAL, + IN OUT UINTN *SourceSize OPTIONAL ) +{ + if (GetNbSmiContext()) NbSmiHandler(); +#if NB_ECC_ERROR_LOG_SUPPORT + if (GetNbEccContext()) NBEccErrLogHandle(); +#endif +#if NB_PCIE_ERROR_LOG_SUPPORT + if (GetNbPcieContext()) NBPcieErrLogHandle(); +#endif + return EFI_HANDLER_SUCCESS; +} + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InSmmFunction +// +// Description: Installs North Bridge SMM Child Dispatcher Handler. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InSmmFunction ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status; + EFI_STATUS IchnDispatchStatus = EFI_SUCCESS; + EFI_SMM_SW_DISPATCH_PROTOCOL *pSwDispatch; + EFI_SMM_SX_DISPATCH_PROTOCOL *pSxDispatch; + EFI_SMM_SW_DISPATCH_CONTEXT SwContext = {NB_SWSMI_IGFX_GET_SETUP}; + EFI_SMM_SX_DISPATCH_CONTEXT SxContext = {SxS3, SxEntry}; + EFI_HANDLE DummyHandle = NULL; + EFI_HANDLE Handle; + EFI_SMM_BASE_PROTOCOL *SmmBaseProtocol; + EFI_GUID NbAslBufPtrGuid = NB_ASL_BUFFER_PTR_GUID; + CHAR16 NbAslBufPtrVar[] = \ + NB_ASL_BUFFER_PTR_VARIABLE; + UINTN VarSize = sizeof(UINT32); + UINT32 NbAslBufPtr; + UINTN VariableSize = sizeof(NB_SETUP_DATA); +#if NB_ERROR_LOG_SUPPORT + EFI_SMM_ICHN_DISPATCH_PROTOCOL *IchnDispatch; + EFI_SMM_ICHN_DISPATCH_CONTEXT IchnContext; +#endif + + // + // Get SETUP variables and change defaults for some boards. + // + + Status = pRS->GetVariable( NbAslBufPtrVar, \ + &NbAslBufPtrGuid, \ + NULL, \ + &VarSize, \ + &NbAslBufPtr ); + if (!EFI_ERROR(Status)) gNbAslBufPtr = (NB_ASL_BUFFER *)NbAslBufPtr; + + Status = pBS->LocateProtocol( &gEfiSmmBaseProtocolGuid, \ + NULL, \ + &SmmBaseProtocol ); + if (EFI_ERROR(Status)) return Status; + + Status = SmmBaseProtocol->SmmAllocatePool( \ + SmmBaseProtocol, \ + EfiRuntimeServicesData, \ + VariableSize, \ + &gNbSetupData ); + if (!EFI_ERROR (Status)){ + GetNbSetupData( pRS, gNbSetupData, FALSE ); + } else { + gNbSetupData->EccSupport = 0; + gNbSetupData->LcdPanelType = 0; + gNbSetupData->SdvoPanelType = 0; + gNbSetupData->LcdPanelScaling = 0; + gNbSetupData->IgdBootType = 0; + gNbSetupData->DisplayPipeB = 0; + gNbSetupData->IgdLcdBlc = 0; + gNbSetupData->ActiveLFP = 1; + gNbSetupData->LfpColorDepth = 0; + gNbSetupData->PrimaryDisplay = 3; + } + + Status = pBS->LocateProtocol( &gEfiSmmSwDispatchProtocolGuid, \ + NULL, \ + &pSwDispatch ); + if (!EFI_ERROR(Status)) { + + if (READ_PCI32_IGD (R_SA_IGD_VID) != 0xFFFFFFFF) { + + Status = pSwDispatch->Register( pSwDispatch, \ + NbSwSmiIgfxGetSetupHandler, \ + &SwContext, \ + &Handle ); + + } + } + + Status = pBS->LocateProtocol( &gEfiSmmSxDispatchProtocolGuid, \ + NULL, \ + &pSxDispatch ); + if (!EFI_ERROR(Status)) { + Status = pSxDispatch->Register( pSxDispatch, \ + NbSxSmiHandler, \ + &SxContext, \ + &Handle ); + } + +#if NB_ERROR_LOG_SUPPORT + + if (gNbSetupData->SmbiosLogging == 1) + { + + Status = pBS->LocateProtocol ( &gIchnDispatchProtocolGuid, \ + NULL, \ + &IchnDispatch ); + +#if NB_ECC_ERROR_LOG_SUPPORT + + if(gNbSetupData->EccSupport) + { + if (!EFI_ERROR(Status)) + { + IchnContext.Type = IchnMch; //TCO DMI SMI + IchnDispatchStatus = IchnDispatch->Register( IchnDispatch, \ + NBErrLogHandler, \ + &IchnContext, \ + &Handle ); + ASSERT_EFI_ERROR (IchnDispatchStatus); + + if (!EFI_ERROR(IchnDispatchStatus)) gEccErrHandleEnable = TRUE; + // Enable ECC error log function + //EccEnableFunction(); + } + } + +#endif + +#if NB_PCIE_ERROR_LOG_SUPPORT + + if (!EFI_ERROR(Status)) + { + IchnContext.Type = IchnNmi; //TCO NMI2 SMI + IchnDispatchStatus = IchnDispatch->Register( IchnDispatch, \ + NBErrLogHandler, \ + &IchnContext, \ + &Handle ); + ASSERT_EFI_ERROR (IchnDispatchStatus); + + if (!EFI_ERROR(IchnDispatchStatus)) gPegErrHandleEnable = TRUE; + + } + +#endif + + + +// pBS->FreePool( NBSetupData ); + + Status = pBS->InstallProtocolInterface( &DummyHandle, \ + &gNbErrorLogDispatchProtocolGuid, \ + EFI_NATIVE_INTERFACE, \ + &gEfiNbErrorLogDispatchProtocol ); + } +#endif + + // Register Callbacks + SmmBaseProtocol->RegisterCallback( SmmBaseProtocol, \ + ImageHandle, \ + NbChildDispatcher, \ + FALSE, \ + FALSE ); + + return EFI_SUCCESS; + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitializeNBSmm +// +// Description: Installs North Bridge SMM Child Dispatcher Handler. +// +// Input: ImageHandle - Image handle +// *SystemTable - Pointer to the system table +// +// Output: EFI_STATUS +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS InitializeNBSmm ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + InitAmiLib(ImageHandle, SystemTable); + return InitSmmHandler(ImageHandle, SystemTable, InSmmFunction, NULL); +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBSMI.CIF b/Chipset/NB/NBSMI.CIF new file mode 100644 index 0000000..099a66e --- /dev/null +++ b/Chipset/NB/NBSMI.CIF @@ -0,0 +1,12 @@ +<component> + name = "NB SMI" + category = ModulePart + LocalRoot = "Chipset\NB" + RefName = "NBSMI" +[files] +"\NBSMI.C" +"\NBSMI.H" +"\NBSMI.MAK" +"\NBSMI.DXS" +"\NBSMI.SDL" +<endComponent> diff --git a/Chipset/NB/NBSMI.DXS b/Chipset/NB/NBSMI.DXS new file mode 100644 index 0000000..7f41c0a --- /dev/null +++ b/Chipset/NB/NBSMI.DXS @@ -0,0 +1,76 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.DXS 2 10/14/12 12:16a Jeffch $ +// +// $Revision: 2 $ +// +// $Date: 10/14/12 12:16a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.DXS $ +// +// 2 10/14/12 12:16a Jeffch +// [TAG] None +// [Severity] Important +// [Description] Follow MahoBay Update. +// [Files] NBSMI.c, NBSMI.Dxe +// +// 1 2/08/12 4:35a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NbSmi.dxs +// +// Description: This file is the dependency file for the North Bridge SMI +// handler. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <token.h> +#if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x0001000A) +#include <Protocol\SmmSwDispatch2.h> +#include <Protocol\SmmSxDispatch2.h> +#else +#include <Protocol\SmmSwDispatch.h> +#include <Protocol\SmmSxDispatch.h> +#endif + +DEPENDENCY_START +#if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x0001000A) + EFI_SMM_SW_DISPATCH2_PROTOCOL_GUID AND + EFI_SMM_SX_DISPATCH2_PROTOCOL_GUID +#else + EFI_SMM_SW_DISPATCH_PROTOCOL_GUID AND + EFI_SMM_SX_DISPATCH_PROTOCOL_GUID +#endif +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBSMI.H b/Chipset/NB/NBSMI.H new file mode 100644 index 0000000..4bdc232 --- /dev/null +++ b/Chipset/NB/NBSMI.H @@ -0,0 +1,153 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.H 1 2/08/12 4:34a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:34a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.H $ +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +//************************************************************************* +// +// Name: NBSMI.h +// +// Description: This file contains all definitions for South Bridge SMI +// driver +// +//************************************************************************* +//<AMI_FHDR_END> + +#ifndef _NBSMI_H__ +#define _NBSMI_H__ + +// {FF2D54D4-5C55-4c06-8549-C3627CB8B995} +#define EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL_GUID \ + {0xff2d54d4, 0x5c55, 0x4c06, 0x85, 0x49, 0xc3, 0x62, 0x7c, 0xb8, 0xb9, 0x95} + +typedef enum { + NbErrorNone, + NbEccError, + NbPcieError, + NbErrorMax, +} AMI_NB_ERROR_LOG_TYPE; + +// Prototypes +typedef struct _NB_ECC_INFO +{ + UINT32 Correctable:1; + UINT32 UnCorrectable:1; + UINT32 EccErrDimmNum:2; // DIMM 0/1/2/3 + UINT32 Reserved:28; + UINT32 EccErrLog0; + UINT32 EccErrLog1; + UINT32 Ch0_EccErrLog0; + UINT32 Ch0_EccErrLog1; + UINT32 Ch1_EccErrLog0; + UINT32 Ch1_EccErrLog1; +} NB_ECC_INFO; + +typedef struct _NB_PCIE_INFO +{ + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT16 VendorId; + UINT16 DeviceId; + UINT16 PciCommand; + UINT16 PciStatus; + UINT16 PciCCode; + UINT16 PcieStatus; + UINT32 PortType; + UINT8 Version; + UINT16 SecondaryStatus; + UINT16 BridgeControl; + BOOLEAN Correctable; + BOOLEAN NonFatal; + BOOLEAN Fatal; + BOOLEAN ParityError; + BOOLEAN SystemError; +} NB_PCIE_INFO; + +typedef struct _NB_ERROR_INFO +{ + UINT8 ErrorType; + NB_ECC_INFO EccErrorInfo; + NB_PCIE_INFO PcieErrorInfo; +} NB_ERROR_INFO; + +typedef struct _EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL; + +#ifndef __SMM_CHILD_DISPATCH__H__ +#ifndef _SB_SMI_PROTOCOL_H +typedef struct _GENERIC_LINK GENERIC_LINK; +typedef struct _GENERIC_LINK { + void *Link; +}; +#endif +#endif + +typedef VOID (EFIAPI *EFI_NB_ERROR_LOG_DISPATCH) ( + IN EFI_HANDLE DispatchHandle, + IN NB_ERROR_INFO NbErrorInfo +); + +typedef struct _NB_ERROR_LOG_DISPATCH_LINK NB_ERROR_LOG_DISPATCH_LINK; +struct _NB_ERROR_LOG_DISPATCH_LINK { + IN NB_ERROR_LOG_DISPATCH_LINK *Link; + IN EFI_NB_ERROR_LOG_DISPATCH Function; +}; + +typedef EFI_STATUS (EFIAPI *EFI_NB_ERROR_LOG_REGISTER) ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_NB_ERROR_LOG_DISPATCH DispatchFunction, + OUT EFI_HANDLE *DispatchHandle +); + +typedef EFI_STATUS (EFIAPI *EFI_NB_ERROR_LOG_UNREGISTER) ( + IN EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle +); + +struct _EFI_NB_ERROR_LOG_DISPATCH_PROTOCOL { + EFI_NB_ERROR_LOG_REGISTER Register; + EFI_NB_ERROR_LOG_UNREGISTER UnRegister; +}; + +#define NMI_SC_PORT 0x61 + +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NBSMI.MAK b/Chipset/NB/NBSMI.MAK new file mode 100644 index 0000000..2553524 --- /dev/null +++ b/Chipset/NB/NBSMI.MAK @@ -0,0 +1,72 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.MAK 1 2/08/12 4:35a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:35a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.MAK $ +# +# 1 2/08/12 4:35a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +#<AMI_FHDR_START> +# +# Name: NBSMI.MAK +# +# Description: Make file for the NB SMI handler code +# +#<AMI_FHDR_END> +#************************************************************************* + +all : NBSMI + +NBSMI: $(BUILD_DIR)\NBSMI.mak NBSMIBin + +$(BUILD_DIR)\NBSMI.mak : $(NB_SMI_PATH)\NBSMI.cif $(NB_SMI_PATH)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(NB_SMI_PATH)\NBSMI.cif $(CIF2MAK_DEFAULTS) + +NB_SMI_OBJECTS = $(BUILD_NB_CHIPSET_DIR)\NBSMI.obj \ +$(BUILD_NB_BOARD_DIR)\GetSetupData.obj + +NBSMIBin : $(AMIDXELIB) $(AMICSPLib) + @set INCLUDE=%%INCLUDE%% + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\NBSMI.mak all\ + "CFLAGS=$(CFLAGS) /I$(NB_BOARD_DIR) /I$(SB_BOARD_DIR) /I$(SB_CHIPSET_DIR)"\ + OBJECTS="$(NB_SMI_OBJECTS)" \ + GUID=D933DEDE-0260-4e76-A7D9-2F9F2440E5A5\ + ENTRY_POINT=InitializeNBSmm\ + TYPE=BS_DRIVER \ + COMPRESS=1 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/NBSMI.SDL b/Chipset/NB/NBSMI.SDL new file mode 100644 index 0000000..81e5e69 --- /dev/null +++ b/Chipset/NB/NBSMI.SDL @@ -0,0 +1,114 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.SDL 1 2/08/12 4:35a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:35a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NB SMI/NBSMI.SDL $ +# +# 1 2/08/12 4:35a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "NBSMI_SUPPORT" + Value = "1" + Help = "Main switch to enable NB SMI support in Project" + TokenType = Boolean + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "NB_ERROR_LOG_SUPPORT" + Value = "1" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "ErrorLogging_SUPPORT" "=" "1" + Token = "IpmiLib_SUPPORT" "=" "1" + Token = "SmmRuntime_SUPPORT" "=" "1" +End + +TOKEN + Name = "NB_PCIE_ERROR_LOG_SUPPORT" + Value = "1" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "NB_ERROR_LOG_SUPPORT" "=" "1" +End + +TOKEN + Name = "NB_ECC_ERROR_LOG_SUPPORT" + Value = "1" + TokenType = Boolean + TargetMAK = Yes + TargetH = Yes + Token = "NB_ERROR_LOG_SUPPORT" "=" "1" +End + +TOKEN + Name = "ECC_MULTI_BIT_TYPE_HANG" + Value = "0" + TokenType = Boolean + TargetH = Yes + Token = "NB_ECC_ERROR_LOG_SUPPORT" "=" "1" +End + +TOKEN + Name = "NB_SWSMI_IGFX_GET_SETUP" + Value = "0xb0" + Help = "Value to write into SMI command register to generate software SMI for NB" + TokenType = Integer + TargetEQU = Yes + TargetH = Yes + Range = "0xB0 - 0xB6" +End + +PATH + Name = "NB_SMI_PATH" + Path = "Chipset\NB" +End + +MODULE + Help = "Includes NBSMI.mak to Project" + File = "NBSMI.mak" +End + +ELINK + Name = "$(BUILD_DIR)\NBSMI.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/NBSmm.c b/Chipset/NB/NBSmm.c new file mode 100644 index 0000000..64499c9 --- /dev/null +++ b/Chipset/NB/NBSmm.c @@ -0,0 +1,625 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBSmm.c 1 2/08/12 4:34a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:34a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NBSmm.c $ +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NBSMM.C +// +// Description: This file contains code for SMM access and control (both the +// protocol defined by Framework +// +//<AMI_FHDR_END> +//************************************************************************* + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include <Efi.h> +#include <token.h> +#include <HOB.h> +#include <DXE.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> + +// Used Protocols +#include <Protocol\PciRootBridgeIo.h> +// Produced Protocols +#include <Protocol\SmmAccess.h> +#if PI_SPECIFICATION_VERSION >= 0x0001000A +#include <Protocol\SmmAccess2.h> +#endif + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// Variable Declaration(s) + +EFI_HOB_HANDOFF_INFO_TABLE *pHIT; + +static EFI_SMRAM_DESCRIPTOR gSmramMap[] = { + { + 0xA0000, // PhysicalStart + 0xA0000, // CpuStart + 128*1024, // PhysicalSize + EFI_ALLOCATED | EFI_SMRAM_CLOSED // RegionState + }, + { + 0, // PhysicalStart + 0, // CputStart + TSEG_SIZE, // PhysicalSize + EFI_ALLOCATED | EFI_SMRAM_CLOSED // RegionState + } +}; + +#define SMRAM_MAP_NUM_DESCRIPTORS (sizeof(gSmramMap)/sizeof(EFI_SMRAM_DESCRIPTOR)) +static UINTN SmramMapNumDescriptors = SMRAM_MAP_NUM_DESCRIPTORS; + +// GUID Definition(s) + +EFI_GUID gGuidHobList = HOB_LIST_GUID; +EFI_GUID gEfiSmmAccessProtocolGuid = EFI_SMM_ACCESS_PROTOCOL_GUID; + +// Protocol Definition(s) + +// External Declaration(s) + +//#### extern EFI_GUID gEfiBootScriptSaveGuid; +//#### extern EFI_GUID gEfiPciRootBridgeIoProtocolGuid; +//#### extern EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *gPciRootBridgeIo; +//#### extern EFI_BOOT_SCRIPT_SAVE_PROTOCOL *gBootScriptSave; + +// Function Definition(s) + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_EnableSMMAddress +// +// Description: This function programs the NB chipset registers to enable +// appropriate SMRAM area. +// +// Input: None +// +// Output: EFI_SUCCESS Always +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_EnableSMMAddress (VOID) +{ + UINT64 qTsegAddress; + + // Currently TSEG address is assumed to be TOM - TSEG_SIZE + // THIS CODE SHOULD BE CHANGED TO GET THE TSEG LOCATION FROM CPU INFO HOB + qTsegAddress = pHIT->EfiMemoryTop; +#if NB_DEBUG_MESSAGE + TRACE((TRACE_ALWAYS, "TSEG Address %x.\n", qTsegAddress)); +#endif + gSmramMap[1].PhysicalStart = gSmramMap[1].CpuStart = qTsegAddress; + gSmramMap[1].PhysicalSize = TSEG_SIZE; + +// Porting Required - Enable SMM area in Chipset (both TSEG & 0xA0000) +// TSEG & 0xA0000 had been enabled at PEI phase. +// Porting ENDS + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_OpenSmram +// +// Description: This function programs the NB chipset registers to open +// the SMRAM area. +// +// Input: *This - Pointer to the SMM access protocol +// DescriptorIndex - Index of SMM Descriptor +// +// Output: EFI_STATUS +// EFI_SUCCESS Opened the SMM area. +// EFI_INVALID_PARAMETER Descriptor doesn't exist. +// EFI_ACCESS_DENIED SMM area locked +// +// Modified: gSmramMap[DescriptorIndex].RegionState to EFI_SMRAM_OPEN. +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1. If invalid Descriptor return EFI_INVALID_PARAMETER. +// 2. Read NB SMM register. +// 3. If locked, return EFI_ACCESS_DENIED +// 4. Set Value for register to Open SMM area (0a0000-bffff) +// 5. Write Register. +// 6. Set OpenState to TRUE. +// 7. Set the RegionState to EFI_SMRAM_OPEN. +// 8. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_OpenSmram ( + IN EFI_SMM_ACCESS_PROTOCOL *This, + IN UINTN DescriptorIndex ) +{ + //-UINT8 SmramControl; + + if (DescriptorIndex >= SmramMapNumDescriptors) + return EFI_INVALID_PARAMETER; + +// Porting Required - Open SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_LOCKED ) + /* Write code to check SMM lock */ + return EFI_ACCESS_DENIED; //If device is locked, return error. + +/* + SmramControl = MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC); + + if ((SmramControl & SMRAMC_D_LCK_MASK) != 0) + { + gSmramMap[0].RegionState = EFI_SMRAM_LOCKED; + gSmramMap[1].RegionState = EFI_SMRAM_LOCKED; + return EFI_DEVICE_ERROR; + } + + SmramControl |= SMRAMC_D_OPEN_MASK; + SmramControl &= ~(SMRAMC_D_CLS_MASK); + + MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC) = SmramControl; +*/ +// Porting ENDS + + // Update appropriate flags + This->OpenState = TRUE; + gSmramMap[0].RegionState = EFI_SMRAM_OPEN; + gSmramMap[1].RegionState = EFI_SMRAM_OPEN; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_CloseSmram +// +// Description: This function programs the NB chipset registers to close +// the SMRAM area. +// +// Input: *This Pointer to the SMM access protocol +// DescriptorIndex Index of SMM Descriptor +// +// Output: EFI_STATUS +// EFI_SUCCESS Closed the SMM area. +// EFI_INVALID_PARAMETER Descriptor doesn't exist. +// EFI_ACCESS_DENIED SMM area locked +// +// Modified: gSmramMap[DescriptorIndex].RegionState to EFI_SMRAM_CLOSED & +// EFI_ALLOCATED +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1. If invalid Descriptor return EFI_INVALID_PARAMETER. +// 2. Read NB SMM register. +// 3. If locked, return EFI_ACCESS_DENIED +// 4. Set Value for register to close SMM area (0a0000-bffff) +// 5. Write Register. +// 6. Set OpenState to FALSE. +// 7. Set the RegionState to EFI_SMRAM_CLOSED & EFI_ALLOCATED +// 8. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_CloseSmram ( + IN EFI_SMM_ACCESS_PROTOCOL *This, + IN UINTN DescriptorIndex ) +{ + //-UINT8 SmramControl; + + if (DescriptorIndex >= SmramMapNumDescriptors) + return EFI_INVALID_PARAMETER; + +// Porting Required - Close SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_LOCKED ) + /* Write code to check SMM lock */ + return EFI_ACCESS_DENIED; //If device is locked, return error. + +/* + SmramControl = MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC); + + if ((SmramControl & SMRAMC_D_LCK_MASK) != 0) + { + gSmramMap[0].RegionState = EFI_SMRAM_LOCKED; + gSmramMap[1].RegionState = EFI_SMRAM_LOCKED; + return EFI_DEVICE_ERROR; + } + + SmramControl &= ~(SMRAMC_D_OPEN_MASK); + + MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC) = SmramControl; +*/ +// Porting ENDS + + // Update appropriate flags + This->OpenState = FALSE; + gSmramMap[0].RegionState = EFI_SMRAM_CLOSED | EFI_ALLOCATED; + gSmramMap[1].RegionState = EFI_SMRAM_CLOSED | EFI_ALLOCATED; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_LockSmram +// +// Description: This function programs the NB chipset registers to lock +// the SMRAM area from opening/closing. Only system level reset +// can unlock the SMRAM lock. +// +// Input: *This Pointer to the SMM access protocol +// DescriptorIndex Index of SMM Descriptor +// +// Output: EFI_STATUS +// EFI_SUCCESS Locked the SMM area. +// EFI_INVALID_PARAMETER Descriptor doesn't exist. +// EFI_DEVICE_ERROR SMM area is opened, need to be +// closed first before locking +// +// Modified: gSmramMap[DescriptorIndex].RegionState to EFI_SMRAM_LOCKED. +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1. If invalid Descriptor return EFI_INVALID_PARAMETER. +// 2. Read NB SMM register. +// 3. If opened, return EFI_ACCESS_DENIED +// 4. Set Value for register to lock SMM area (0a0000-bffff) +// 5. Write Register. +// 6. Set the RegionState to EFI_SMRAM_CLOSED & EFI_ALLOCATED +// 7. Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_LockSmram ( + IN EFI_SMM_ACCESS_PROTOCOL *This, + IN UINTN DescriptorIndex ) +{ + //-UINT8 SmramControl; + + //Both regions must open and close at the same time. + if (DescriptorIndex >= SmramMapNumDescriptors) + return EFI_INVALID_PARAMETER; + +// Porting Required - Lock SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_OPEN) + { + /* Write code to check SMM lock */ + return EFI_ACCESS_DENIED; //If SMM is opened, return error. + } + +/* + SmramControl = MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC); + + SmramControl &= ~(SMRAMC_D_OPEN_MASK); + SmramControl |= (SMRAMC_D_LCK_MASK); + + MmPci8(MC_BUS, MC_DEV, MC_FUN, SMRAMC) = SmramControl; +*/ +// Porting ENDS + + // Update appropriate flags + This->LockState = TRUE; + gSmramMap[0].RegionState = EFI_SMRAM_LOCKED; + gSmramMap[1].RegionState = EFI_SMRAM_LOCKED; + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_GetCapabilities +// +// Description: This function returns the current SMRAM area map information +// such as number of regions and its start address and size +// +// Input: *This Pointer to the SMM access protocol +// *SmramMapSize Size of the SMRAM map buffer provided +// *SmramMap Buffer to copy the SMRAM map information +// +// Output: EFI_STATUS +// EFI_SUCCESS Smram Map copied into buffer +// EFI_BUFFER_TOO_SMALL Indicates that provided buffer is +// not enough +// *SmramMapSize Filled with required/updated size +// +// Notes: CHIPSET AND/OR BOARD PORTING NEEDED +// Here is the control flow of this function: +// 1.If Smram Map Size less than the actual map size, set +// the map size and return EFI_BUFFER_TOO_SMALL. +// 2.Copy the Smram Map descriptors into the supplied buffer. +// 3.Set the map size in *SmramMapSize, just in case is +// larger than the actual buffer. +// 4.Return EFI_SUCCESS. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NBSMM_GetCapabilities ( + IN EFI_SMM_ACCESS_PROTOCOL *This, + IN OUT UINTN *SmramMapSize, + OUT EFI_SMRAM_DESCRIPTOR *SmramMap ) +{ + UINTN i; + + if (*SmramMapSize < sizeof(gSmramMap)) + { + // If input map size to small, + // report the correct map size and return error. + *SmramMapSize = sizeof(gSmramMap); + return EFI_BUFFER_TOO_SMALL; + } + + for(i=0; i < SmramMapNumDescriptors; ++i) + SmramMap[i] = gSmramMap[i]; + + *SmramMapSize = sizeof(gSmramMap); // Set the correct map size + + return EFI_SUCCESS; +} + +EFI_SMM_ACCESS_PROTOCOL mSmmAccess = { + NBSMM_OpenSmram, + NBSMM_CloseSmram, + NBSMM_LockSmram, + NBSMM_GetCapabilities, + FALSE, + FALSE +}; + +EFI_SMM_ACCESS_PROTOCOL *gSmmAccess = NULL; + +#if PI_SPECIFICATION_VERSION >= 0x0001000A +EFI_STATUS OpenSmram2(IN EFI_SMM_ACCESS2_PROTOCOL *This) +{ + EFI_STATUS Status; + UINTN i; + + if ((This->LockState != gSmmAccess->LockState) || + (This->OpenState != gSmmAccess->OpenState)) + { + This->LockState = gSmmAccess->LockState; + This->OpenState = gSmmAccess->OpenState; + } + +// Porting Required - Open SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_LOCKED) + { + /* Write code to check SMM lock */ + + //If device is locked, return error. + return EFI_ACCESS_DENIED; + } + + for(i=0; i < SmramMapNumDescriptors; ++i) + { + Status = gSmmAccess->Open(gSmmAccess, i); + if (Status != EFI_SUCCESS) + return Status; + } +// Porting ENDS + + // Update appropriate flags + This->OpenState = TRUE; + + return EFI_SUCCESS; +} + +EFI_STATUS CloseSmram2(IN EFI_SMM_ACCESS2_PROTOCOL *This) +{ + EFI_STATUS Status; + UINTN i; + + if ((This->LockState != gSmmAccess->LockState) || + (This->OpenState != gSmmAccess->OpenState)) + { + This->LockState = gSmmAccess->LockState; + This->OpenState = gSmmAccess->OpenState; + } + +// Porting Required - Close SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_LOCKED) + { + /* Write code to check SMM lock */ + + //If device is locked, return error. + return EFI_ACCESS_DENIED; + } + + for(i=0; i < SmramMapNumDescriptors; ++i) + { + Status = gSmmAccess->Close(gSmmAccess, i); + if (Status != EFI_SUCCESS) + return Status; + } +// Porting ENDS + + // Update appropriate flags + This->OpenState = FALSE; + + return EFI_SUCCESS; +} + +EFI_STATUS LockSmram2(IN EFI_SMM_ACCESS2_PROTOCOL *This) +{ + EFI_STATUS Status; + UINTN i; + + if ((This->LockState != gSmmAccess->LockState) || + (This->OpenState != gSmmAccess->OpenState)) + { + This->LockState = gSmmAccess->LockState; + This->OpenState = gSmmAccess->OpenState; + } + +// Porting Required - Lock SMM area in Chipset (both TSEG & 0xA0000) + if (gSmramMap[0].RegionState == EFI_SMRAM_OPEN) + { + /* Write code to check SMM lock */ + return EFI_ACCESS_DENIED; //If SMM is opened, return error. + } + + for(i=0; i < SmramMapNumDescriptors; ++i) + { + Status = gSmmAccess->Lock(gSmmAccess, i); + if (Status != EFI_SUCCESS) + return Status; + } +// Porting ENDS + + // Update appropriate flags + This->LockState = TRUE; + + return EFI_SUCCESS; +} + +EFI_STATUS GetCapabilities2( + IN CONST EFI_SMM_ACCESS2_PROTOCOL *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap +) +{ + EFI_STATUS Status; + + Status = gSmmAccess->GetCapabilities(gSmmAccess, SmramMapSize, SmramMap); + + return Status; +} + +EFI_SMM_ACCESS2_PROTOCOL gSmmAccess2 = { + OpenSmram2, + CloseSmram2, + LockSmram2, + GetCapabilities2, + FALSE, + FALSE +}; +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: NBSMM_Init +// +// Description: This function is invoked from NB DXE to initialize SMM +// related stuff in NorthBridge and install appropriate +// SMM protocols such as SMM Access & SMM Control +// +// Input: ImageHandle Image handle +// SystemTable Pointer to the system table +// +// Output: Return Status based on errors that occurred while waiting for +// time to expire. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS NbSmmInit ( + IN EFI_EVENT Event, + IN VOID *Context) +{ + EFI_STATUS Status = EFI_SUCCESS; + UINTN SmramMapSize = sizeof(gSmramMap); + + PROGRESS_CODE (DXE_NB_SMM_INIT); + + Status = pBS->LocateProtocol(&gEfiSmmAccessProtocolGuid, NULL, &gSmmAccess); + if (EFI_ERROR(Status)) + { + pHIT = GetEfiConfigurationTable(pST, &gGuidHobList); + + // Enable SMM address range by programming appropriate chipset registers + NBSMM_EnableSMMAddress (); + + Status = pBS->InstallMultipleProtocolInterfaces(&TheImageHandle, + &gEfiSmmAccessProtocolGuid, + &mSmmAccess, +#if PI_SPECIFICATION_VERSION >= 0x0001000A + &gEfiSmmAccess2ProtocolGuid, + &gSmmAccess2, +#endif + NULL, + NULL ); + ASSERT_EFI_ERROR(Status); + } + else + { + Status = gSmmAccess->GetCapabilities(gSmmAccess, &SmramMapSize, gSmramMap); + ASSERT_EFI_ERROR(Status); + + SmramMapNumDescriptors = SmramMapSize / sizeof(EFI_SMRAM_DESCRIPTOR); + +#if PI_SPECIFICATION_VERSION >= 0x0001000A + Status = pBS->InstallMultipleProtocolInterfaces(&TheImageHandle, + &gEfiSmmAccess2ProtocolGuid, + &gSmmAccess2, + NULL, + NULL ); + ASSERT_EFI_ERROR(Status); +#endif + } + + return Status; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/NbPciCSP.c b/Chipset/NB/NbPciCSP.c new file mode 100644 index 0000000..396e0df --- /dev/null +++ b/Chipset/NB/NbPciCSP.c @@ -0,0 +1,1165 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NbPciCSP.c 2 5/13/14 10:41p Dennisliu $ +// +// $Revision: 2 $ +// +// $Date: 5/13/14 10:41p $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/NbPciCSP.c $ +// +// 2 5/13/14 10:41p Dennisliu +// [TAG] EIP167027 +// [Category] Improvement +// [Description] [SharkBay Aptio4]Variable's attribute needs to be +// reviewed by SA component driver +// [Files] NBDXEBoard.c; IntelSaGopSetup.c; IntelSaGopPolicy.c; +// NBDxe.c; NbPciCSP.c; PciHostBridge.c; +// +// 1 2/08/12 4:34a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: NbPciCSP.c +// +// Description: Chipset Porting Hooks for PCI Host Bridge Driver. +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <Token.h> +#if AMI_ROOT_BRIDGE_SUPPORT == 1 +/****** DO NOT WRITE ABOVE THIS LINE *******/ + +//---------------------------------------------------------------------------- +// Include(s) +//---------------------------------------------------------------------------- + +#include "PciHostBridge.h" +#include <Acpi11.h> +#include <Acpi20.h> +#include <Protocol\AcpiTable.h> +#include <AmiCspLib.h> + +//---------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//---------------------------------------------------------------------------- +// Constant Definition(s) + +#if ACPI_SUPPORT + #if defined(PI_SPECIFICATION_VERSION) && (PI_SPECIFICATION_VERSION >= 0x00010014) + #include <Protocol\AcpiSystemDescriptionTable.h> + #else + #include <Protocol\AcpiSupport.h> + #endif +#endif + +// Macro Definition(s) + +// Type Definition(s) + +// Function Prototype(s) + +//---------------------------------------------------------------------------- +// Variable and External Declaration(s) +//---------------------------------------------------------------------------- +// GUID Definition(s) + +EFI_GUID gEfiGlobalVariableGuid = EFI_GLOBAL_VARIABLE; + +// Variable Declaration(s) + +EFI_EVENT mAcpiEvent; +VOID *mAcpiReg; +UINTN mMcfgTblHandle = 0; +CHAR16 gMemoryCeilingVariable[] = L"MemCeil."; + +#if (CORE_VERSION <= 4635) +//---------------------------------------------------------------------------- +// For HOST AND ROOT BRIDGE Architectural information +// see chapter 12.1.1 PCI Root Bridge I/O Overview of EFI 1.1 spec +//---------------------------------------------------------------------------- +//This table will provide information on how many Root Bridges +//particular Host Bridge will produce. +//The table has NB_NUMBER_OF_HOST_BRG entries. +//(Token NB_NUMBER_OF_HOST_BRG is defined in NB.sdl) +// +//For desktop chipset it will be ONE ROOT UNDER ONE HOST. +// +//If system has more than ONE Host Add more Lines +//----------------------------------------------------------------------------------------------- + +UINTN gRbCountTbl[NB_NUMBER_OF_HOST_BRG]={ + 1, //Number of root bridges produced by Host #0 + //Number of root bridges produced by Host #1 + //Number of root bridges produced by Host #2 + //Number of root bridges produced by Host #3 +}; + +//----------------------------------------------------------------------------------------------- +// This is the table to provide each host allocation attributes +// The table has NB_NUMBER_OF_HOST_BRG entries. +// (Token NB_NUMBER_OF_HOST_BRG is defined in NB.sdl) +// Accepted values are: +// EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM +// EFI_PCI_HOST_BRIDGE_MEM64_DECODE +// These values can be ORed. +// The values are defined and explained in +// PCI Host Bridge Resource Allocation Protocol Specification V 0.9 +//----------------------------------------------------------------------------------------------- + +UINT64 gHbAllocAttribTbl[NB_NUMBER_OF_HOST_BRG]={ + 0, //Allocation Attributes of Host #0 + //Allocation Attributes of Host #1 + //Allocation Attributes of Host #2 + //Allocation Attributes of Host #3 + // And so on +}; + +//----------------------------------------------------------------------------------------------- +// This table will provide PCI Buses Decoding Information +// in form of ACPI QWORD resource descriptor. +// The only valid fields are: +// ResourceType, _MIN, _LEN. +// Maximum Bus may be calculated as: _MAX=_MIN+_LEN -1 +// +// If system has more then one root bridge, add more lines +// +// Desktop chipset is simple chipset with only one root bridge +// which decodes all bus ranges from 0 to 0xFF +// +// See definition of QWORD ACPI Resource Descriptor in ACPI 2.0 Spec +// and "Address Space Resource Descriptor Internal definitions" in AcpiRes.h +// Number of table entries depends on values ported in gRbCountTbl +//----------------------------------------------------------------------------------------------- + +// Name, Len, Resource Type, Flags ,_GRA, _MIN, _MAX, _TRA, _LEN +ASLR_QWORD_ASD gRbBusesTbl[] = { +// for Root 0 at Host 0 + {0x8a, 0x2b,ASLRV_SPC_TYPE_BUS, 0, 0, 0x1, 0x00, 0xff, 0, 0x100} +// for Root 1 at Host 0 if any + +// for Root 0 at Host 1 if any +}; + +//----------------------------------------------------------------------------------------------- +// This is the table for the Capabilities Supported by ROOT BRIDGE +// See EFI 1.1 spec for meaning of the Capabilities bits +// +// if system has more than one root bridge add more lines +// Number of table entries depends on values ported in gRbCountTbl +//----------------------------------------------------------------------------------------------- + +UINT64 gRbSupportsTbl[] = { +//for Root 0 at Host 0 + (EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO| \ + EFI_PCI_ATTRIBUTE_ISA_IO | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | \ + EFI_PCI_ATTRIBUTE_VGA_MEMORY | EFI_PCI_ATTRIBUTE_VGA_IO | \ + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO), +//for Root 1 at Host 0 if any + +//for Root 0 at Host 1 if any + +// and so on... +}; +#endif + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) + +//---------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspGetPciSegment +// +// Description: This procedure returns PCI segment number for chipsets which +// capable of decoding multiple PCI segments. +// +// Input: HostBridgeNumber - Host Bridge Number (0 Based) +// RootBridgeNumber - Root Bridge Number (0 Based) +// +// Output: UINTN - PCI Segment Number (0 Based) +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINTN HbCspGetPciSegment ( + IN UINTN HostBridgeNumber, + IN UINTN RootBridgeNumber ) +{ + + // Usually even server chipsets decodes only one PCI segment + // but if chipsets has more than one SEGMENT we have to specify + // which HOST/ROOT(s) pare will have SEG=0; SEG=1 and so on... + + return 0; // this is for Single Host chipset + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspBeforeEnumeration +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeBeginEnumeration. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspBeforeEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspBeginBusAllocation +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeBeginBusAllocation. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspBeginBusAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspEndBusAllocation +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeEndBusAllocation +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspEndBusAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspBeginResourceAllocation +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeBeginResourceAllocation. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspBeginResourceAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspAllocateResources +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeAllocateResources. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspAllocateResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspSetResources +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeSetResources. +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspSetResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbNotifyCspEndResourceAllocation +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// when NotifyPhase function is called with phase +// EfiPciHostBridgeEndResourceAllocation +// +// Input: ResAllocProtocol - Pointer to Host Bridge Resource +// Allocation Protocol. +// RbIoProtocolBuffer - Pointer to Root Bridge I/O Protocol. +// RbCount - Root Bridge counter. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbNotifyCspEndResourceAllocation ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAllocProtocol, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL **RbIoProtocolBuffer, + IN UINTN RbCount ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspStartBusEnumeration +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// StartBusEnumeration function, it must prepare initial Bus +// ACPI Resource +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspStartBusEnumeration ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status = EFI_SUCCESS; +#if (CORE_COMBINED_VERSION <= 0x4027B) // 4.6.3.5 + + ASLR_QWORD_ASD *br; // Bus Resource Descriptor + + br = Malloc(sizeof(ASLR_QWORD_ASD)); + ASSERT(br); + if(!br) return EFI_OUT_OF_RESOURCES; + + // Fill out Bus Resource Requirements + MemCpy(br, &gRbBusesTbl[RootBrgIndex], sizeof(ASLR_QWORD_ASD)); + Status = AppendItemLst((T_ITEM_LIST*)&RootBrgData->ResInitCnt, br); + ASSERT_EFI_ERROR(Status); +#endif + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspSetBusNnumbers +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// SubmitBusNumbers function. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspSetBusNnumbers ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspSubmitResources +// +// Description: This procedure will be invoked in PCI Host Bridge Protocol +// SubmitResources function. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspSubmitResources ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspAdjustMemoryMmioOverlap +// +// Description: This procedure will be invoked during PCI bus enumeration, +// it determines the PCI memory base address below 4GB whether +// it is overlapping the main memory, if it is overlapped, then +// updates MemoryCeiling variable and reboot. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspAdjustMemoryMmioOverlap ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status; + + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap; + UINTN NumberOfDescriptors; + ASLR_QWORD_ASD *Res; + UINTN i; + EFI_PHYSICAL_ADDRESS Highest4GMem = 0; + EFI_PHYSICAL_ADDRESS LowestMMIO = 0xffffffff; + EFI_PHYSICAL_ADDRESS LowestAllocMMIO = 0xffffffff; + UINTN MemoryCeiling = 0; // Init to 0 + UINTN NewMemoryCeiling = 0xffffffff; + UINTN DataSize = sizeof(UINT32); + UINT32 Attributes; // [ EIP167027 ] +#if (CORE_VERSION >= 4600) + DXE_SERVICES *DxeSvc; + +//------------------------------------ + Status = LibGetDxeSvcTbl( &DxeSvc ); + ASSERT_EFI_ERROR(Status) + if(EFI_ERROR(Status)) return Status; +#else + ASSERT(gDxeSvcTbl); +#endif + return EFI_SUCCESS; + //pRS->GetVariable ( gMemoryCeilingVariable, \ // [ EIP167027 ] + // &gEfiGlobalVariableGuid, \ + // NULL, \ + // &DataSize, \ + // &MemoryCeiling ); + pRS->GetVariable ( gMemoryCeilingVariable, \ + &gEfiGlobalVariableGuid, \ + &Attributes, \ + &DataSize, \ + &MemoryCeiling ); + if (EFI_ERROR(Status)) + Attributes = EFI_VARIABLE_NON_VOLATILE + EFI_VARIABLE_BOOTSERVICE_ACCESS; + + // Memory sizing uses memory ceiling to set top of memory. + + +#if (CORE_VERSION >= 4600) + Status = DxeSvc->GetMemorySpaceMap( &NumberOfDescriptors, \ + &MemorySpaceMap ); +#else + Status = gDxeSvcTbl->GetMemorySpaceMap( &NumberOfDescriptors, \ + &MemorySpaceMap ); +#endif + ASSERT_EFI_ERROR(Status) + + // Find the lowest MMIO and lowest allocated MMIO in GCD. + for (i = 0; i < NumberOfDescriptors; ++i) { + EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descr = &MemorySpaceMap[i]; + EFI_PHYSICAL_ADDRESS Base = Descr->BaseAddress; + + // Find highest system below 4GB memory. + // Treat any non MMIO as system memory. Not all system memory is + // reported as system memory, such as SMM. + + if (Descr->GcdMemoryType != EfiGcdMemoryTypeMemoryMappedIo && \ + Base < LowestMMIO) { + EFI_PHYSICAL_ADDRESS EndMem = Base + Descr->Length - 1; + if (EndMem > Highest4GMem && EndMem <= 0xffffffff) + Highest4GMem = EndMem; + + // Find Lowest mmio above system memory. + } else if (Descr->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) { + if (Base >= 0x100000) { + if (Base < LowestMMIO) LowestMMIO = Base; + + // If ImageHandle, then MMIO is allocated. + if ((Base < LowestAllocMMIO) && Descr->ImageHandle) + LowestAllocMMIO = Base; + } + } + } + + pBS->FreePool(MemorySpaceMap); + + if (Highest4GMem + 1 != LowestMMIO) { + TRACE( (-1, "PciHostCSHooks: ") ); + TRACE( (-1, "System Memory and MMIO are not consequitive.\n") ); + TRACE( (-1, "Top of Below 4G Memory: %lX", Highest4GMem) ); + TRACE( (-1, "Bottom of MMIO: %X\n", LowestMMIO) ); + } + + + // Find any MMIO that could not be allocated due to small of MMIO region. + for (i = 0; i < RootBrgData->ResCount; ++i) { + EFI_PHYSICAL_ADDRESS NeededBottomMmio; + + Res = RootBrgData->RbRes[i]; + + // Any unallocated MMIO will have Res->_MIN set to zero for the MMIO + // type. + if (Res->Type != ASLRV_SPC_TYPE_MEM || Res->_GRA != 32 || Res->_MIN) + continue; + + // Determine new memory ceiling variable needed to allocate this + // memory. + NeededBottomMmio = LowestAllocMMIO - Res->_LEN; + + // Round down. If resource is not allocated, _MAX contains + // granularity. + NeededBottomMmio &= ~Res->_MAX; + if (NeededBottomMmio < NewMemoryCeiling) + NewMemoryCeiling = (UINTN) NeededBottomMmio; + } + + // Check if a NewMemory Ceiling is needed. + if (NewMemoryCeiling < 0xffffffff) { + if (!MemoryCeiling || MemoryCeiling != NewMemoryCeiling ) { + + // Set memory ceiling variable. + //pRS->SetVariable( gMemoryCeilingVariable, \ // [ EIP167027 ] + // &gEfiGlobalVariableGuid, \ + // EFI_VARIABLE_NON_VOLATILE + \ + // EFI_VARIABLE_BOOTSERVICE_ACCESS + \ + // EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (UINT32), \ + // &NewMemoryCeiling ); + pRS->SetVariable( gMemoryCeilingVariable, \ + &gEfiGlobalVariableGuid, \ + Attributes, + sizeof (UINT32), \ + &NewMemoryCeiling ); + + TRACE((-1, "Adjusting maximum top of RAM.\n Resetting System.\n")); + + // Reset only needed of type of physical memory overlaps with MMIO. + +#if (NV_SIMULATION != 1) + // Don't reset system in case of NVRAM simulation + pRS->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL); +#endif + // Control should not come here if NV_SIMULATION = 0. + } + return EFI_SUCCESS; + } + + // Check to see if Ceiling needs to be increased. If too low, + // then part of the memory be not be usuable. + if (MemoryCeiling != LowestAllocMMIO) { + + // Set memory ceiling variable. + //pRS->SetVariable( gMemoryCeilingVariable, \ // [ EIP167027 ] + // &gEfiGlobalVariableGuid, \ + // EFI_VARIABLE_NON_VOLATILE + \ + // EFI_VARIABLE_BOOTSERVICE_ACCESS + \ + // EFI_VARIABLE_RUNTIME_ACCESS, + // sizeof (UINT32), \ + // &LowestAllocMMIO ); + pRS->SetVariable( gMemoryCeilingVariable, \ + &gEfiGlobalVariableGuid, \ + Attributes, + sizeof (UINT32), \ + &LowestAllocMMIO ); + + TRACE((-1, "Adjusting maximum top of RAM.\n Resetting System.\n")); + +#if (NV_SIMULATION != 1) + // Don't reset system in case of NVRAM simulation + pRS->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL); +#endif + // Control should not come here if NV_SIMULATION = 0. + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspPreprocessController +// +// Description: This function is called for all the PCI controllers that +// the PCI bus driver finds. +// It can be used to Preprogram the controller. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgNumber - Root Bridge number (0 Based). +// PciAddress - Address of the controller on the PCI bus. +// Phase - The phase during enumeration +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspPreprocessController ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgNumber, + IN EFI_PCI_CONFIGURATION_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspMapRootBrgToHost +// +// Description: Chipset specific function that returns Host Bridge Number for +// the corresponded Root Bridge. +// +// Input: RootBrgXlatHdr - Pointer to Root Bridge XLAT table entry. +// AllocationAttr - Pointer to allocation attribute. +// RbSuportedAttr - Pointer to Root Bridge supported attribute. +// +// Output: UINTN - Number of the Host Bridge that root bridge +// identified by RootBrgXlatHdr belongs to. +// +// Note: THIS FUNCTION MUST BE PORTED FOR MULTI-HOST SYSTEMS +// HOST bridge handle supports: +// - ResourceAllocation Protocol (REQUIRED); +// - RootHotplugControllerInitialization +// Protocol (OPTIONAL); +// - PciPlatform Protocol (OPTIONAL). +// ROOT bridge handle supports: +// - PciRootBridgeIo Protocol (REQUIRED). +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +UINTN HbCspMapRootBrgToHost ( +#if (PCIBUS_VERSION > 020102) + IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr, + IN UINT64 *AllocationAttr, + IN UINT64 *RbSuportedAttr ) +#else + IN PCI_BUS_XLAT_HDR *RootBrgXlatHdr ) +#endif +{ + // Usually even server chipsets use only one PCI HOST abstraction + // but if chipset has more than one HOST we have to specify + // which ROOT from PciBusXlat table belongs to which HOST. + + // Check if we need to update/change Allocation Attributes Passed to + // this function. + // Here we have ability to override Automaticaly generated Attributes + // based on SDL tokens COMBINE_MEM_PMEM and ABOVE_4G_PCI_DECODE + // bits currently defined for Allocation Attributes is: + // EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM + // EFI_PCI_HOST_BRIDGE_MEM64_DECODE + // Usually nothing needs to be done sor SINGLE HOST-SINGLE-ROOT systems + // NOTE: this function could be called more than one time for each HOST + // if you updating AllocationAttr only last data will be valid. + // PCI HostBridge Driver sets DEFAULT allocation attributes. + // Add code only if you need to overwrite it. + + // if i.e. second root does not support PF_MMIO + // if(RootBrgXlatHdr->BusBuild == 0x80 ) \ + // *AllocationAttr &= ~(EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM); + // else *RbSuportedAttr = ....; + + // Check that in VeB PCI Wizard this Root creates bus 0 + // This is usualy a compatibility bus + // Set the Compatibility bus Attributes it must decode Legacy resources + + // PCI HostBridge Driver sets DEFAULT Supported ROOT BRIDGE Attributes. + // Add code only if you need to overwrite it. + + // if (RootBrgXlatHdr->BusBuild == 0) *RbSuportedAttr= \ + // (EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | \ + // EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \ + // EFI_PCI_ATTRIBUTE_ISA_IO | \ + // EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO | \ + // EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ + // EFI_PCI_ATTRIBUTE_VGA_IO | \ + // EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO); + // else *RbSuportedAttr = 0; + + // Returning Host Number for Root Bridge corresponded to the Root + // ported as RootBrgXlatHdr->BusBuild from BusXLat Table + // for single SINGLEHOST-SINGLE-ROOT system this value always 0 + + // If your system MULTY-HOST/MULTY-ROOTs system + // you need to add code here to correctly map each ROOT referenced in + // VeB wizard to it's corresponded host + + return 0; +} + +#if (PCIBUS_VERSION > 020102) + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspAllocateResources +// +// Description: This function is invoked in PCI Host Bridge Driver when time +// to ask GCD for resources. You can overwrite a default +// algorithm used to allocate resources for the Root Bridge. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// RootBrgData - Pointer to Root Bridge private structure data. +// RootBrgIndex - Root Bridge index (0 Based). +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspAllocateResources ( + IN PCI_HOST_BRG_DATA *HostBrgData, + IN PCI_ROOT_BRG_DATA *RootBrgData, + IN UINTN RootBrgIndex ) +{ + EFI_STATUS Status = EFI_UNSUPPORTED; + + return Status; +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: HbCspBasicChipsetInit +// +// Description: This function will be invoked after Initialization of generic +// part of the Host and Root Bridges. +// All Handles for PCIHostBrg and PciRootBrg has been created +// and Protocol Intergaces installed. +// +// Input: HostBrgData - Pointer to Host Bridge private structure data. +// +// Output: EFI_STATUS +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS HbCspBasicChipsetInit ( + IN PCI_HOST_BRG_DATA *HostBrg0 ) +{ + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RbCspIoPciMap +// +// Description: Chipset Specific function to Map Internal Device address +// residing ABOVE 4G to the BELOW 4G address space for DMA. +// MUST BE IMPLEMENTED if CHIPSET supports address space +// decoding ABOVE 4G. +// +// Input: *RbData - Root Bridge private structure data +// Operation - Operation to provide Mapping for +// HostAddress - HostAddress of the Device +// *NumberOfBytes - Number of Byte in Mapped Buffer. +// *DeviceAddress - Mapped Device Address. +// **Mapping - Mapping Info Structure this function must +// allocate and fill. +// +// Output: EFI_STATUS +// EFI_SUCCESS - Successful. +// EFI_UNSUPPORTED - The Map function is not supported. +// EFI_INVALID_PARAMETER - One of the parameters has an +// invalid value. +// +// Notes: Porting is required for chipsets that supports Decoding +// of the PCI Address Space ABOVE 4G. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RbCspIoPciMap ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN EFI_PHYSICAL_ADDRESS HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping ) +{ + + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + *Mapping = NULL; + Status = EFI_UNSUPPORTED; + + // For Chipsets which DOES support decoding of the PCI resources ABOVE 4G. + // here must be something like that. + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RbCspIoPciUnmap +// +// Description: Chipset Specific function to Unmap previousely Mapped +// buffer for DMA. +// MUST BE IMPLEMENTED if CHIPSET supports address space +// decoding ABOVE 4G. +// +// Input: *RbData - Root Bridge private structure data +// *Mapping - Mapping Info Structure this function must free. +// +// Output: EFI_STATUS +// EFI_SUCCESS - Successful. +// EFI_UNSUPPORTED - The Unmap function is not supported. +// EFI_INVALID_PARAMETER - One of the parameters has an +// invalid value. +// +// Notes: Porting required if needed. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RbCspIoPciUnmap ( + IN PCI_ROOT_BRG_DATA *RbData, + OUT PCI_ROOT_BRIDGE_MAPPING *Mapping ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + + if (Mapping != NULL) return EFI_INVALID_PARAMETER; + // for all other conditions we would return EFI_UNSUPPORTED. + Status = EFI_UNSUPPORTED; + + // for Chipsets which DOES support decoding of the PCI resources ABOVE 4G. + // And provides corresponded mapping for the host address + // here must be something like that. + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RbCspIoPciAttributes +// +// Description: Chipset Specific function to do PCI RB Attributes releated +// programming. +// +// Input: RbData - Pointer to Root Bridge private structure. +// Attributes - The Root Bridge attributes to be programming. +// ResourceBase - Pointer to the resource base. (OPTIONAL) +// ResourceLength - Pointer to the resource Length. (OPTIONAL) +// +// Output: EFI_STATUS +// EFI_SUCCESS - Successful. +// EFI_INVALID_PARAMETER - One of the parameters has an +// invalid value. +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS RbCspIoPciAttributes ( + IN PCI_ROOT_BRG_DATA *RbData, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase OPTIONAL, + IN OUT UINT64 *ResourceLength OPTIONAL ) +{ + + + EFI_STATUS Status = EFI_SUCCESS; + + // Any Additional Variables goes here + + return Status; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: RootBridgeIoPciRW +// +// Description: Read Pci Registers into buffer. +// Csp Function which actualy access PCI Config Space. +// Chipsets that capable of having PCI EXPRESS Ext Cfg Space +// transactions. +// Must Implement this access routine here. +// +// Input: *RbData - Root Bridge private structure. +// Width - PCI Width. +// Address - PCI Address. +// Count - Number of width reads/writes. +// *Buffer - Buffer where read/written. +// Write - Set if write. +// +// Output: EFI_STATUS +// EFI_SUCCESS - Successful read. +// EFI_INVALID_PARAMETER - One of the parameters has an +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS RootBridgeIoPciRW ( + IN PCI_ROOT_BRG_DATA *RbData, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer, + IN BOOLEAN Write ) +{ + BOOLEAN ValidCfg = TRUE; + UINT8 IncrementValue = 1 << (Width & 3); // 1st 2 bits currently define + // width. + // Other bits define type. + + UINTN PciAddress = PCIEX_BASE_ADDRESS + \ + (((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->Bus << 20 ) + \ + (((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->Device << 15 ) + \ + (((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->Function << 12 ); + + PciAddress += \ + ((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->ExtendedRegister ? \ + ((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->ExtendedRegister : \ + ((EFI_PCI_CONFIGURATION_ADDRESS*) &Address)->Register; + + // To read 64bit values, reduce Increment Value (by half) and + // double the count value (by twice) + if (IncrementValue > 4) { + IncrementValue >>= 1; + Count <<= 1; + } + + if (Width >= EfiPciWidthMaximum || IncrementValue > 4) + return EFI_INVALID_PARAMETER; + + while (Count--) { + if (PciAddress >= (PCIEX_BASE_ADDRESS + PCIEX_LENGTH)) \ + ValidCfg = FALSE; + if (Write) { + switch(IncrementValue) { + case 1: + if (ValidCfg) *(UINT8*)PciAddress = *(UINT8*)Buffer; + break; + case 2: + if (ValidCfg) *(UINT16*)PciAddress = *(UINT16*)Buffer; + break; + default: + if (ValidCfg) *(UINT32*)PciAddress = *(UINT32*)Buffer; + break; + } + } else { + switch(IncrementValue) { + case 1: + *(UINT8*)Buffer = (ValidCfg) ? *(UINT8*)PciAddress : -1; + break; + case 2: + *(UINT16*)Buffer = (ValidCfg) ? *(UINT16*)PciAddress : -1; + break; + default: + *(UINT32*)Buffer = (ValidCfg) ? *(UINT32*)PciAddress : -1; + break; + } + } + + if (Width <= EfiPciWidthFifoUint64) { + Buffer = ((UINT8 *)Buffer + IncrementValue); + // Buffer is increased for only EfiPciWidthUintxx and + // EfiPciWidthFifoUintxx + } + + // Only increment the PCI address if Width is not a FIFO. + if ((Width & 4) == 0) { + PciAddress += IncrementValue; + } + } + + return EFI_SUCCESS; +} + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#endif //#if AMI_ROOT_BRIDGE_SUPPORT == 1 + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/ReleaseNotes.chm b/Chipset/NB/ReleaseNotes.chm Binary files differnew file mode 100644 index 0000000..b652c4c --- /dev/null +++ b/Chipset/NB/ReleaseNotes.chm diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.c b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.c new file mode 100644 index 0000000..3a5a8b4 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.c @@ -0,0 +1,263 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/LegacyRegion2/LegacyRegion2.c 1 4/05/12 3:08a Yurenlai $ +// +// $Date: 4/05/12 3:08a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: LegacyRegion2.c +// +// Description: Legacy Region 2 functions implementation +// +//<AMI_FHDR_END> +//************************************************************************* + +#include <efi.h> +#include <AmiDxeLib.h> +#include <AmiCspLib.h> +#include <Protocol\LegacyRegion.h> +#include <Protocol\LegacyRegion2.h> + +EFI_LEGACY_REGION_PROTOCOL *gLegacyRegionProtocol = NULL; + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionDecode +// +// Description: Program chipset to allow decoding of 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity, +// IN BOOLEAN *On +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS LegacyRegionDecode( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity, + IN BOOLEAN *On +) +{ + return gLegacyRegionProtocol->Decode( gLegacyRegionProtocol, Start, Length, On); +} + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionLock +// +// Description: To disallow writes to memory 0xc0000 - 0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS LegacyRegionLock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return gLegacyRegionProtocol->Lock( gLegacyRegionProtocol, Start, Length, Granularity); +} + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionBootLock +// +// Description: To permanently disallow writes to memory 0xc0000 - 0xffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS LegacyRegionBootLock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return gLegacyRegionProtocol->BootLock( gLegacyRegionProtocol, Start, Length, Granularity); +} + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: LegacyRegionUnlock +// +// Description: To allow read/write of memory 0xc0000-0xfffff. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This, +// IN UINT32 Start, +// IN UINT32 Length, +// OUT UINT32 *Granularity OPTIONAL +// +// Output: +// Status of the operation +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS LegacyRegionUnlock( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + IN UINT32 Start, + IN UINT32 Length, + OUT UINT32 *Granularity OPTIONAL +) +{ + return gLegacyRegionProtocol->UnLock(gLegacyRegionProtocol, Start, Length, Granularity); +} + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: GetLegacyRegionInfo +// +// Description: +// This function is used to discover the granularity of the attributes +// for the memory in the legacy region. Each attribute may have a different +// granularity and the granularity may not be the same for all memory ranges +// in the legacy region. +// +// Input: +// IN EFI_LEGACY_REGION_PROTOCOL *This +// -- Indicates the EFI_LEGACY_REGION_PROTOCOL instance. +// +// Output: +// EFI_UNSUPPORTED - This function is not supported +// EFI_SUCCESS - The following information structure is returned: +// OUT UINT32 *DescriptorCount +// -- The number of region descriptor entries returned in the Descriptor +// buffer. See EFI_LEGACY_REGION_DESCRIPTOR definition for reference. +// OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor +// -- A pointer to a pointer used to return a buffer where the legacy +// region information is deposited. This buffer will contain a list +// of DescriptorCount number of region descriptors. This function will +// provide the memory for the buffer. +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS GetLegacyRegionInfo( + IN EFI_LEGACY_REGION2_PROTOCOL *This, + OUT UINT32 *DescriptorCount, + OUT EFI_LEGACY_REGION_DESCRIPTOR **Descriptor +) +{ + return EFI_UNSUPPORTED; // Note: to support this function there is a need + // to update NB template. +} + +EFI_LEGACY_REGION2_PROTOCOL gLegacyRegion2Protocol = +{ + LegacyRegionDecode, LegacyRegionLock, + LegacyRegionBootLock, LegacyRegionUnlock, + GetLegacyRegionInfo +}; + +//************************************************************************* +//<AMI_PHDR_START> +// +// Procedure: InitializeLegacyRegion2 +// +// Description: Install the legacy region 2 protocol. +// +// Input: +// IN EFI_HANDLE ImageHandle, +// IN EFI_SYSTEM_TABLE *SystemTable +// +// Output: +// Status of the operation +// +// Notes: +// Here is the control flow of this function: +// 1. Get root bridge io protocol. +// 2. Install legacy region protocol. +// +//<AMI_PHDR_END> +//************************************************************************* +EFI_STATUS InitializeLegacyRegion2( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + InitAmiLib(ImageHandle, SystemTable); + + Status = pBS->LocateProtocol( + &gEfiLegacyRegionProtocolGuid, + NULL, + &gLegacyRegionProtocol); + + if(!EFI_ERROR(Status)) { + + Status = pBS->InstallProtocolInterface ( + &ImageHandle, + &gEfiLegacyRegion2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &gLegacyRegion2Protocol + ); + } + + return Status; + +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.cif b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.cif new file mode 100644 index 0000000..429cfe6 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.cif @@ -0,0 +1,11 @@ +<component> + name = "LegacyRegion2" + category = ModulePart + LocalRoot = "Chipset\NB\SystemAgentWrap\LegacyRegion2\" + RefName = "LegacyRegion2" +[files] +"LegacyRegion2.sdl" +"LegacyRegion2.mak" +"LegacyRegion2.dxs" +"LegacyRegion2.c" +<endComponent> diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.dxs b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.dxs new file mode 100644 index 0000000..1e5b3e0 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.dxs @@ -0,0 +1,51 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/LegacyRegion2/LegacyRegion2.dxs 1 4/05/12 3:08a Yurenlai $ +// +// $Date: 4/05/12 3:08a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: LegacyRegion2.dxs +// +// Description: Legacy Region 2 dependency file +// +//<AMI_FHDR_END> +//************************************************************************* +#include <protocol\LegacyRegion.h> + +DEPENDENCY_START + EFI_LEGACY_REGION_PROTOCOL_GUID +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2012, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.mak b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.mak new file mode 100644 index 0000000..da09a37 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.mak @@ -0,0 +1,44 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +all : LegacyRegion2 + +LegacyRegion2 : $(BUILD_DIR)\LegacyRegion2.mak LegacyRegion2Bin + +$(BUILD_DIR)\LegacyRegion2.mak : $(LEGACY_REGION2_DIR)\$(@B).cif $(LEGACY_REGION2_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(LEGACY_REGION2_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +LegacyRegion2Bin : $(AMIDXELIB) $(AMICSPLib) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\LegacyRegion2.mak all\ + GUID=FE6F8ACD-55A6-4c6b-B448-64E659DE94B3 \ + ENTRY_POINT=InitializeLegacyRegion2 \ + DEPEX1=$(LEGACY_REGION2_DIR)\LegacyRegion2.dxs\ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER \ + COMPRESS=1\ + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2012, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.sdl b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.sdl new file mode 100644 index 0000000..2f6de11 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/LegacyRegion2/LegacyRegion2.sdl @@ -0,0 +1,26 @@ +TOKEN + Name = "LegacyRegion2_SUPPORT" + Value = "1" + Help = "Main switch to enable LegacyRegion2 support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "CSM_SUPPORT" "=" "1" +End + +PATH + Name = "LEGACY_REGION2_DIR" +End + +MODULE + Help = "Includes LegacyRegion.mak to Project" + File = "LegacyRegion2.mak" +End + +ELINK + Name = "$(BUILD_DIR)\LegacyRegion2.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.c b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.c new file mode 100644 index 0000000..275b297 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.c @@ -0,0 +1,80 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.c 1 2/08/12 4:36a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:36a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.c $ +// +// 1 2/08/12 4:36a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: MiscSubclass.c +// +// Description: This file for BIOS id Build in to Hii data base. +// +//<AMI_FHDR_END> +//********************************************************************** + +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <Setup.h> +#include <SetupStrTokens.h> + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InitiMiscStrings +// +// Description: Create BIOS id string. +// +// Input: HiiHandle - Handle to HII database +// Class - Indicates the setup class +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +InitiMiscStrings ( + IN EFI_HII_HANDLE HiiHandle, + IN UINT16 Class +) +{ + STRING_REF Dummy [] = { STRING_TOKEN (STR_BIOS_ID)} + return; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.cif b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.cif new file mode 100644 index 0000000..e105399 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.cif @@ -0,0 +1,13 @@ +<component> + name = "MiscSubclass" + category = ModulePart + LocalRoot = "Chipset\NB\SystemAgentWrap\MiscSubclass" + RefName = "MiscSubclass" +[files] +"MiscSubclass.sdl" +"MiscSubclass.mak" +"MiscSubclassStrings.uni" +"MiscSubclass.c" +"MiscSubclassDxe.c" +"MiscSubclassDxe.dxs" +<endComponent> diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.mak b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.mak new file mode 100644 index 0000000..66c165d --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.mak @@ -0,0 +1,106 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.mak 1 2/08/12 4:36a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:36a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.mak $ +# +# 1 2/08/12 4:36a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* + +#--------------------------------------------------------------------------- +# Create SmBiosMemory DXE driver +#--------------------------------------------------------------------------- +all: MiscSubclass MiscSubclassSDB MiscSubclassDxe + +#MiscSubclass: $(BUILD_DIR)\MiscSubclass.mak MiscSubclassBin +MiscSubclass: $(BUILD_DIR)\MiscSubclass.mak + +$(BUILD_DIR)\MiscSubclass.mak : $(MiscSubclass_DIR)\$(@B).cif $(MiscSubclass_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(MiscSubclass_DIR)\$(@B).cif $(CIF2MAK_DEFAULTS) + +MiscSubclass_OBJECTS = \ +$(BUILD_DIR)\$(MiscSubclass_DIR)\MiscSubclass.obj \ +$(BUILD_DIR)\MiscSubclassStrings.obj \ + +#MiscSubclassBin : $(PRINTLIB) $(EFIDRIVERLIB) $(EDKGUIDLIB) $(EFIPROTOCOLLIB) $(EFIIFRSUPPORTLIB) +# $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ +# /f $(BUILD_DIR)\MiscSubclass.mak all\ +# GUID=EDA39402-F375-4496-92D3-83B43CB8A76A\ +# "MY_INCLUDES=$(SmBiosMemory_INCLUDES)" \ +# ENTRY_POINT=MiscSubclass\ +# TYPE=BS_DRIVER\ +# "OBJECTS=$(MiscSubclass_OBJECTS)"\ +# DEPEX1=$(SmBiosMemory_DIR)\SmBiosMemory.dxs\ +# DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX\ +# COMPRESS=1 + +#--------------------------------------------------------------------------- +# Create MiscSubclass Setup Screens +#--------------------------------------------------------------------------- +MiscSubclassSDB : $(BUILD_DIR)\MiscSubclass.mak + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MiscSubclass.mak all\ + TYPE=SDB NAME=MiscSubclass + $(STRGATHER) -dump -lang $(SUPPORTED_LANGUAGES: = -lang )\ + -db $(BUILD_DIR)\MiscSubclass.sdb\ + -bn MiscSubclass\ + -oh $(BUILD_DIR)\MiscSubclassStrings.h\ + -oc $(BUILD_DIR)\MiscSubclassStrings.c + $(CC) $(CFLAGS) /Fo$(BUILD_DIR)\ $(BUILD_DIR)\MiscSubclassStrings.c + +#---------------------------------------------------------------------------- +# Create MiscSubclass DXE Component +#---------------------------------------------------------------------------- +MiscSubclassDxe : $(BUILD_DIR)\MiscSubclass.mak MiscSubclassDxeBin + +MiscSubclass_DXE_OBJECTS = $(BUILD_DIR)\$(MiscSubclass_DIR)\MiscSubclassDxe.obj \ +$(BUILD_DIR)\MiscSubclassStrings.obj \ + +MiscSubclassDxeBin : $(AMICSPLib) $(AMIDXELIB) + $(MAKE) /$(MAKEFLAGS) $(BUILD_DEFAULTS)\ + /f $(BUILD_DIR)\MiscSubclass.mak all\ + NAME=MiscSubclassDxe\ + MAKEFILE=$(BUILD_DIR)\MiscSubclass.mak \ + OBJECTS="$(MiscSubclass_DXE_OBJECTS)" \ + GUID=16271FCA-55D9-4a33-93FC-5A3EB128DE21 \ + ENTRY_POINT=MiscSubclassDxe_Init \ + "CFLAGS=$(CFLAGS) /I$(NB_CHIPSET_DIR) /I$(NB_BOARD_DIR) /I$(SB_CHIPSET_DIR) /I$(SB_BOARD_DIR)"\ + "EXT_HEADERS=$(BUILD_DIR)\token.h"\ + TYPE=BS_DRIVER \ + DEPEX1=$(MiscSubclass_DIR)\MiscSubclassDxe.dxs DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + COMPRESS=1 + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl new file mode 100644 index 0000000..df10827 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl @@ -0,0 +1,69 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl 1 2/08/12 4:36a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:36a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclass.sdl $ +# +# 1 2/08/12 4:36a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "MISC_SUBCLASS_SUPPORT" + Value = "1" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + TargetH = Yes + Master = Yes + Help = "Main switch to enable MiscSubclass support in Project" +End + +MODULE + Help = "Includes MiscSubclass.mak to Project" + File = "MiscSubclass.mak" +End + +PATH + Name = "MiscSubclass_DIR" +End + +ELINK + Name = "$(BUILD_DIR)\MiscSubclassDxe.ffs" + Parent = "FV_MAIN" + Help = "Add Intel MiscSubclass Dxe driver" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c new file mode 100644 index 0000000..8f87be9 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c @@ -0,0 +1,483 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c 1 2/08/12 4:36a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:36a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.c $ +// +// 1 2/08/12 4:36a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: MiscSubclassDxe.c +// +// Description: This file for init Hii data base in BIOS id. +// +//<AMI_FHDR_END> +//************************************************************************* + +//--------------------------------------------------------------------------- +// Include(s) +//--------------------------------------------------------------------------- + +#include <Efi.h> +#include <token.h> +#include <AmiLib.h> +#include <AmiDxeLib.h> +#include <Setup.h> +#include <Dxe.h> +#include <PCI.h> +#include <AmiHobs.h> +#include <AmiCspLib.h> + +// Produced Protocols + +// Consumed Protocols + +#include <Protocol\DataHub.h> +#include <Include\DataHubSubClass.h> + +#if EFI_SPECIFICATION_VERSION >= 0x2000A +#include "Include\UefiHii.h" +#include "Protocol\HiiDatabase.h" +#include "Protocol\HiiString.h" +#else +#include <Protocol/Hii.h> +#endif + +//--------------------------------------------------------------------------- +// Constant, Macro and Type Definition(s) +//--------------------------------------------------------------------------- +// Constant Definition(s) + +// Macro Definition(s) +#define EFI_MISC_SUBCLASS_GUID \ +{ 0x772484B2, 0x7482, 0x4b91, 0x9F, 0x9A, 0xAD, 0x43, 0xF8, 0x1C, 0x58, 0x81 } + +#define EFI_MISC_SUBCLASS_DRIVER_GUID \ + { 0xF50E702C, 0x8653, 0x4CDE, 0xBB, 0xCE, 0x43, 0xB4, 0xD5, 0x5B, 0x34, 0xB8 } + +// Type Definition(s) + +#define EFI_MISC_SUBCLASS_VERSION 0x0100 +#define EFI_DATA_RECORD_CLASS_DATA 0x0000000000000004 +#define EFI_MISC_BIOS_VENDOR_RECORD_NUMBER 0x00000002 + +#define EFI_SUBCLASS_INSTANCE_NON_APPLICABLE 0xFFFF //16 bit +// Function Prototype(s) + +//--------------------------------------------------------------------------- +// Variable and External Declaration(s) +//--------------------------------------------------------------------------- +// Variable Declaration(s) + +// GUID Definition(s) +EFI_GUID gEfiMiscSubClassGuid = EFI_MISC_SUBCLASS_GUID; +EFI_GUID gEfiMiscSubClassDriverGuid = EFI_MISC_SUBCLASS_DRIVER_GUID; +EFI_GUID gEfiDataHubProtocolGuid = EFI_DATA_HUB_PROTOCOL_GUID; + +// Protocol Definition(s) + +// External Declaration(s) + +// Function Definition(s) +EFI_STATUS InstallMiscSubClassData ( + IN EFI_HANDLE ImageHandle +); + + +typedef struct { + UINT8 LastPciBus; +} EFI_MISC_LAST_PCI_BUS; + +typedef struct { + UINT32 Reserved1 :2; + UINT32 Unknown :1; + UINT32 BiosCharacteristicsNotSupported :1; + UINT32 IsaIsSupported :1; + UINT32 McaIsSupported :1; + UINT32 EisaIsSupported :1; + UINT32 PciIsSupported :1; + UINT32 PcmciaIsSupported :1; + UINT32 PlugAndPlayIsSupported :1; + UINT32 ApmIsSupported :1; + UINT32 BiosIsUpgradable :1; + UINT32 BiosShadowingAllowed :1; + UINT32 VlVesaIsSupported :1; + UINT32 EscdSupportIsAvailable :1; + UINT32 BootFromCdIsSupported :1; + UINT32 SelectableBootIsSupported :1; + UINT32 RomBiosIsSocketed :1; + UINT32 BootFromPcmciaIsSupported :1; + UINT32 EDDSpecificationIsSupported :1; + UINT32 JapaneseNecFloppyIsSupported :1; + UINT32 JapaneseToshibaFloppyIsSupported :1; + UINT32 Floppy525_360IsSupported :1; + UINT32 Floppy525_12IsSupported :1; + UINT32 Floppy35_720IsSupported :1; + UINT32 Floppy35_288IsSupported :1; + UINT32 PrintScreenIsSupported :1; + UINT32 Keyboard8042IsSupported :1; + UINT32 SerialIsSupported :1; + UINT32 PrinterIsSupported :1; + UINT32 CgaMonoIsSupported :1; + UINT32 NecPc98 :1; + UINT32 AcpiIsSupported :1; + UINT32 UsbLegacyIsSupported :1; + UINT32 AgpIsSupported :1; + UINT32 I20BootIsSupported :1; + UINT32 Ls120BootIsSupported :1; + UINT32 AtapiZipDriveBootIsSupported :1; + UINT32 Boot1394IsSupported :1; + UINT32 SmartBatteryIsSupported :1; + UINT32 BiosBootSpecIsSupported :1; + UINT32 FunctionKeyNetworkBootIsSupported :1; + UINT32 TargetContentDistributionEnabled :1; + UINT32 Reserved :21; +} EFI_MISC_BIOS_CHARACTERISTICS; + +typedef struct { + UINT32 BiosReserved :16; + UINT32 SystemReserved :16; + UINT32 Reserved :32; +} EFI_MISC_BIOS_CHARACTERISTICS_EXTENSION; + +typedef struct { + STRING_REF BiosVendor; + STRING_REF BiosVersion; + STRING_REF BiosReleaseDate; + EFI_PHYSICAL_ADDRESS BiosStartingAddress; + EFI_EXP_BASE2_DATA BiosPhysicalDeviceSize; + EFI_MISC_BIOS_CHARACTERISTICS BiosCharacteristics1; + EFI_MISC_BIOS_CHARACTERISTICS_EXTENSION BiosCharacteristics2; + UINT8 BiosMajorRelease; + UINT8 BiosMinorRelease; + UINT8 BiosEmbeddedFirmwareMajorRelease; + UINT8 BiosEmbeddedFirmwareMinorRelease; +} EFI_MISC_BIOS_VENDOR; + +typedef union { + EFI_MISC_LAST_PCI_BUS LastPciBus; + EFI_MISC_BIOS_VENDOR MiscBiosVendor; +} EFI_MISC_SUBCLASS_RECORDS; + +typedef struct { + EFI_SUBCLASS_TYPE1_HEADER Header; + EFI_MISC_SUBCLASS_RECORDS Record; +} EFI_MISC_SUBCLASS_DRIVER_DATA; + +extern UINT8 MiscSubclass[]; + +//--------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: MiscSubclassDxe_Init +// +// Description: This function is the entry point for MiscSubclass DXE driver. +// This function initializes the MiscSubclass in DXE phase. +// +// Input: ImageHandle - Image handle +// SystemTable - Pointer to the system table +// +// Output: EFI_SUCCESS +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +EFI_STATUS MiscSubclassDxe_Init ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + InitAmiLib(ImageHandle, SystemTable); + + Status = InstallMiscSubClassData (ImageHandle); + ASSERT_EFI_ERROR(Status); + + return EFI_SUCCESS; +} + + +#if EFI_SPECIFICATION_VERSION >= 0x2000A +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PreparePackageList +// +// Description: +// Assemble EFI_HII_PACKAGE_LIST according to the passed in packages. +// +// Input: NumberOfPackages - Number of packages. +// GuidId - Package GUID. +// +// +// Output: Pointer of EFI_HII_PACKAGE_LIST_HEADER. +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_HII_PACKAGE_LIST_HEADER * +PreparePackageList ( + IN UINTN NumberOfPackages, + IN EFI_GUID *GuidId, + IN ... +) +{ + va_list Marker; + EFI_HII_PACKAGE_LIST_HEADER *PackageListHeader = NULL; + UINT8 *PackageListData; + UINT32 PackageListLength; + UINT32 PackageLength; + EFI_HII_PACKAGE_HEADER PackageHeader; + UINT8 *PackageArray; + UINTN Index; + + PackageListLength = sizeof (EFI_HII_PACKAGE_LIST_HEADER); + + va_start (Marker, GuidId); + for (Index = 0; Index < NumberOfPackages; Index++) { + pBS->CopyMem (&PackageLength, va_arg (Marker, VOID *), sizeof (UINT32)); + PackageListLength += (PackageLength - sizeof (UINT32)); + } + va_end (Marker); + + // + // Include the lenght of EFI_HII_PACKAGE_END + // + PackageListLength += sizeof (EFI_HII_PACKAGE_HEADER); + //PackageListHeader = EfiLibAllocateZeroPool (PackageListLength); + + // PackageListHeader = EfiLibAllocatePool (PackageListLength); + pBS->AllocatePool (EfiBootServicesData, PackageListLength, &PackageListHeader); + + if (PackageListHeader != NULL) { + pBS->SetMem (PackageListHeader, PackageListLength, 0); + } + + ASSERT (PackageListHeader != NULL); + pBS->CopyMem (&PackageListHeader->PackageListGuid, GuidId, sizeof (EFI_GUID)); + PackageListHeader->PackageLength = PackageListLength; + + PackageListData = ((UINT8 *) PackageListHeader) + sizeof (EFI_HII_PACKAGE_LIST_HEADER); + + va_start (Marker, GuidId); + for (Index = 0; Index < NumberOfPackages; Index++) { + PackageArray = (UINT8 *) va_arg (Marker, VOID *); + pBS->CopyMem (&PackageLength, PackageArray, sizeof (UINT32)); + PackageLength -= sizeof (UINT32); + PackageArray += sizeof (UINT32); + pBS->CopyMem (PackageListData, PackageArray, PackageLength); + PackageListData += PackageLength; + } + va_end (Marker); + + // + // Append EFI_HII_PACKAGE_END + // + PackageHeader.Type = EFI_HII_PACKAGE_END; + PackageHeader.Length = sizeof (EFI_HII_PACKAGE_HEADER); + pBS->CopyMem (PackageListData, &PackageHeader, PackageHeader.Length); + + return PackageListHeader; +} + +#else +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: PreparePackages +// +// Description: +// Assemble EFI_HII_PACKAGE_LIST according to the passed in packages. +// +// Input: NumberOfPackages - Number of packages. +// GuidId - Package GUID. +// +// +// Output: Pointer of EFI_HII_PACKAGE_LIST_HEADER. +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_HII_PACKAGES * +PreparePackages ( + IN UINTN NumberOfPackages, + IN EFI_GUID *GuidId, + IN ... +) +{ + va_list args; + EFI_HII_PACKAGES *HiiPackages; + VOID **Package; + UINTN Index; + EFI_STATUS Status; + ASSERT (NumberOfPackages > 0); + + Status = pBS->AllocatePool(EfiBootServicesData, (sizeof (EFI_HII_PACKAGES)) + NumberOfPackages * sizeof (VOID *), &HiiPackages); + HiiPackages->GuidId = GuidId; + HiiPackages->NumberOfPackages = NumberOfPackages; + Package = (VOID **) (((UINT8 *) HiiPackages) + sizeof (EFI_HII_PACKAGES)); + + va_start (args, GuidId); + + for (Index = 0; Index < NumberOfPackages; Index++) { + *Package = va_arg (args, VOID *); + Package++; + } + + va_end (args); + + return HiiPackages; +} + +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// +// Procedure: InstallMiscSubClassData +// +// Description: +// Install MiscSubClassData for IgdOpRegion. +// +// Input: ImageHandle +// +// +// Output: Status. +// +// Notes: +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS InstallMiscSubClassData ( + IN EFI_HANDLE ImageHandle +) +{ + EFI_STATUS Status; + EFI_DATA_HUB_PROTOCOL *DataHub; + EFI_MISC_SUBCLASS_DRIVER_DATA MiscSubClassData; + EFI_STRING StringBuffer; + EFI_HII_HANDLE HiiHandle; +#if EFI_SPECIFICATION_VERSION >= 0x2000A + CHAR8 Language[]="en-US"; + EFI_HII_DATABASE_PROTOCOL *HiiDatabase; + EFI_HII_STRING_PROTOCOL *HiiString; + EFI_HII_PACKAGE_LIST_HEADER *PackageList; +#else + EFI_HII_PROTOCOL *Hii; + EFI_HII_PACKAGES *PackageList; +#endif + + Status = pBS->LocateProtocol (&gEfiDataHubProtocolGuid, NULL, &DataHub); + ASSERT_EFI_ERROR (Status); + +#if EFI_SPECIFICATION_VERSION >= 0x2000A + // There should only be one HII Database protocol + Status = pBS->LocateProtocol (&gEfiHiiDatabaseProtocolGuid, NULL, &HiiDatabase); + ASSERT_EFI_ERROR (Status); + + Status = pBS->LocateProtocol (&gEfiHiiStringProtocolGuid, NULL, &HiiString); + ASSERT_EFI_ERROR (Status); + +#else + // There should only be one HII protocol + Status = pBS->LocateProtocol (&gEfiHiiProtocolGuid, NULL, &Hii); + ASSERT_EFI_ERROR (Status); +#endif + + MiscSubClassData.Header.Version = EFI_MISC_SUBCLASS_VERSION; + MiscSubClassData.Header.HeaderSize = sizeof (EFI_SUBCLASS_TYPE1_HEADER); + MiscSubClassData.Header.Instance = 1; + MiscSubClassData.Header.SubInstance = EFI_SUBCLASS_INSTANCE_NON_APPLICABLE; + MiscSubClassData.Header.RecordType = EFI_MISC_BIOS_VENDOR_RECORD_NUMBER; + + Status = pBS->AllocatePool(EfiBootServicesData, (sizeof (CHAR16)) * 100, &StringBuffer); + pBS->SetMem(StringBuffer, (sizeof(CHAR16)) * 100, 0); + + Strcpy ((char*)StringBuffer, CONVERT_TO_STRING(BIOSID)); + +#if EFI_SPECIFICATION_VERSION >= 0x2000A + + PackageList = PreparePackageList (1, &gEfiMiscSubClassDriverGuid, MiscSubclass); + + Status = HiiDatabase->NewPackageList ( + HiiDatabase, + PackageList, + ImageHandle, + &HiiHandle + ); + +#else + PackageList = PreparePackages (1, &gEfiMiscSubClassDriverGuid, MiscSubclass); + Status = Hii->NewPack (Hii, PackageList, &HiiHandle); +#endif + ASSERT_EFI_ERROR (Status); + pBS->FreePool (PackageList); + + MiscSubClassData.Record.MiscBiosVendor.BiosVersion = (STRING_REF)0; +#if EFI_SPECIFICATION_VERSION >= 0x2000A + Status = HiiString->NewString (HiiString, HiiHandle, &MiscSubClassData.Record.MiscBiosVendor.BiosVersion, Language, NULL, StringBuffer, NULL); + +// Status = HiiLibSetString(HiiHandle, MiscSubClassData.Record.MiscBiosVendor.BiosVersion, StringBuffer); + if (EFI_ERROR(Status)) return Status; +#else + Hii->NewString ( + Hii, + NULL, + HiiHandle, + &MiscSubClassData.Record.MiscBiosVendor.BiosVersion, + StringBuffer + ); +#endif + + + Status = DataHub->LogData ( + DataHub, + &gEfiMiscSubClassGuid, + &gEfiMiscSubClassDriverGuid, + EFI_DATA_RECORD_CLASS_DATA, + &MiscSubClassData, + sizeof (EFI_SUBCLASS_TYPE1_HEADER) + sizeof (EFI_MISC_BIOS_VENDOR) + ); + + pBS->FreePool(StringBuffer); + + return Status; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs new file mode 100644 index 0000000..aa12ec3 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs @@ -0,0 +1,70 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs 1 2/08/12 4:37a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:37a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/MiscSubclass/MiscSubclassDxe.dxs $ +// +// 1 2/08/12 4:37a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: MiscSubclassDxe.DXS +// +// Description: This file is the dependency file for the MiscSubclass DXE driver. +// +//<AMI_FHDR_END> +//************************************************************************* +#include <Protocol\DataHub.h> + +#if EFI_SPECIFICATION_VERSION >= 0x2000A +#include "Include\UefiHii.h" +#include "Protocol\HiiDatabase.h" +#include "Protocol\HiiString.h" +#else +#include <Protocol/Hii.h> +#endif + +DEPENDENCY_START + EFI_DATA_HUB_PROTOCOL_GUID AND +#if EFI_SPECIFICATION_VERSION >= 0x2000A + EFI_HII_DATABASE_PROTOCOL_GUID AND + EFI_HII_STRING_PROTOCOL_GUID +#else + EFI_HII_PROTOCOL_GUID +#endif +DEPENDENCY_END + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassStrings.uni b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassStrings.uni Binary files differnew file mode 100644 index 0000000..508d5e6 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/MiscSubclass/MiscSubclassStrings.uni diff --git a/Chipset/NB/SystemAgentWrap/SystemAgentWrap.cif b/Chipset/NB/SystemAgentWrap/SystemAgentWrap.cif new file mode 100644 index 0000000..bd07ece --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/SystemAgentWrap.cif @@ -0,0 +1,12 @@ +<component> + name = "SystemAgentWrap" + category = ModulePart + LocalRoot = "Chipset\NB\SystemAgentWrap\" + RefName = "SystemAgentWrap" +[files] +"SystemAgentWrap.sdl" +[parts] +"MiscSubclass" +"UpdateMemoryRecord" +"LegacyRegion2" +<endComponent> diff --git a/Chipset/NB/SystemAgentWrap/SystemAgentWrap.sdl b/Chipset/NB/SystemAgentWrap/SystemAgentWrap.sdl new file mode 100644 index 0000000..badcac8 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/SystemAgentWrap.sdl @@ -0,0 +1,77 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/SystemAgentWrap.sdl 3 7/31/13 3:28a Ireneyang $ +# +# $Revision: 3 $ +# +# $Date: 7/31/13 3:28a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/SystemAgentWrap.sdl $ +# +# 3 7/31/13 3:28a Ireneyang +# [TAG] None +# [Category] Improvement +# [Description] Change token name REFERENCE_DDR_IO_BUS to DCLK_FREQUENCY. +# When it's 0, it would show DDR Frequency in SMBIOS +# (DCLK Frequency). +# When it's 1, it would show DDR IO Bus Clock in SMBIOS +# (QCLK Frequency). +# [Files] SystemAgentWrap.sdl; +# +# 2 6/26/13 5:29a Ireneyang +# [TAG] None +# [Category] Improvement +# [Description] According to SMBIOS spec, Set REFERENCE_DDR_IO_BUS token +# for choosing how to show DDR speed. +# [Files] SystemAgentWrap.sdl; UpdateMemoryRecord.c; +# +# 1 2/08/12 4:36a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "SystemAgentWrap_SUPPORT" + Value = "1" + Help = "Main switch to enable SystemAgentWrap support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes +End + +TOKEN + Name = "DCLK_FREQUENCY" + Value = "0" + Help = "Default: 0, 0 : DDR Frequency (DCLK Frequency) 1: DDR IO Bus Clock (QCLK Frequency)" + TokenType = Integer + TargetH = Yes +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c new file mode 100644 index 0000000..cd4a8f6 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c @@ -0,0 +1,1701 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c 1 4/19/16 7:41a Chienhsieh $ +// +// $Revision: 1 $ +// +// $Date: 4/19/16 7:41a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/Projects/Intel/Haswell/LynxPoint_SharkBay-DT_Crb_1AQQW/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.c $ +// +// 1 4/19/16 7:41a Chienhsieh +// Update rev10. +// +// 10 12/21/15 5:58a Chienhsieh +// [TAG] EIP249553 +// [Category] Improvement +// [Description] SMBIOS Type17 memory speed report issue with Hawell +// (Sharkbay) platform +// [Files] UpdateMemoryRecord.c +// +// 9 8/23/13 2:59a Ireneyang +// [TAG] EIP126356 +// [Category] Improvement +// [Description] Change calucating method for Dimm Frequency. +// [Files] UpdateMemoryRecord.c; +// +// 8 7/31/13 3:38a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Change token name REFERENCE_DDR_IO_BUS to DCLK_FREQUENCY. +// When it's 0, it would show DDR Frequency in SMBIOS +// (DCLK Frequency). +// When it's 1, it would show DDR IO Bus Clock in SMBIOS +// (QCLK Frequency). +// [Files] SystemAgentWrap.sdl; UpdateMemoryRecord.c; +// +// 7 6/26/13 10:00a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] According to SMBIOS spec, Set REFERENCE_DDR_IO_BUS token +// for choosing how to show DDR speed. +// [Files] SystemAgentWrap.sdl; UpdateMemoryRecord.c; +// +// 5 6/26/13 4:27a Ireneyang +// [TAG] None +// [Category] Improvement +// [Description] Rename NbSmbiosType17Voltage() to +// NbSmbiosType17VoltageAndSpeed(). +// [Files] UpdateMemoryRecord.c; +// +// 4 6/13/13 7:14a Ireneyang +// [TAG] EIP125449 +// [Category] Improvement +// [Description] Update XmpId for SMBIOS Spec 2.8.0. +// +// 3 6/07/13 8:13a Ireneyang +// [TAG] EIP125449 +// [Category] Improvement +// [Description] Update SMBIOS Spec 2.8.0. +// +// 2 1/28/13 2:58a Jeffch +// [TAG] None +// [Category] Improvement +// [Description] Update SMBIOS Spec 2.7.1. +// +// +// 1 2/08/12 4:37a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: UpdateMemoryRecord.c +// +// Description: This file for update SMBIOS Type 16 ~19. +// +//<AMI_FHDR_END> +//********************************************************************** + +#include "UpdateMemoryRecord.h" + +#include <MemInfo\MemInfo.h> +#define __EFI__H__ +#ifndef GUID_VARIABLE_DEFINITION +#define GUID_VARIABLE_DECLARATION(Variable, Guid) extern EFI_GUID Variable +#else +#define GUID_VARIABLE_DECLARATION(Variable, Guid) GLOBAL_REMOVE_IF_UNREFERENCED EFI_GUID Variable=Guid +#endif +#include <Protocol\SmBus.h> + +#include <Protocol\SaPlatformPolicy\SaPlatformPolicy.h> + + +#define EFI_SMBIOS_BOARD_PROTOCOL_GUID \ + {0x903dd14, 0x2ca0, 0x458a, 0xb5, 0xeb, 0xc, 0xc, 0xa3, 0xd, 0x78, 0x5c} + +#define EFI_MEMORY_SUBCLASS_DRIVER_GUID \ + { 0x1767CEED, 0xDB82, 0x47cd, 0xBF, 0x2B, 0x68, 0x45, 0x8A, 0x8C, 0xCF, 0xFF } + + +EFI_GUID gEfiMemorySubClassDriverGuid = EFI_MEMORY_SUBCLASS_DRIVER_GUID; +EFI_GUID gEfiSmbiosBoardProtocolGuid = EFI_SMBIOS_BOARD_PROTOCOL_GUID; +EFI_GUID gEfiSmbiosUpdateDataProtocolGuid = EFI_SMBIOS_UPDATE_DATA_PROTOCOL_GUID; +EFI_GUID gDxePlatformSaPolicyGuid = DXE_PLATFORM_SA_POLICY_GUID; +EFI_GUID gMemInfoHobProtocolGuid = MEM_INFO_PROTOCOL_GUID; +EFI_GUID gEfiSmbusProtocolGuid = EFI_SMBUS_HC_PROTOCOL_GUID; + + +EFI_SMBIOS_UPDATE_DATA_PROTOCOL *gSBUpdate; +EFI_SMBIOS_PROTOCOL *gSmbiosProtocol; +MEM_INFO_PROTOCOL *gMemInfoHobProtocol = NULL; +EFI_SMBUS_HC_PROTOCOL *gSmbusProtocol = NULL; +DXE_PLATFORM_SA_POLICY_PROTOCOL *gDxePlatformSaPolicy = NULL; +static UINT8 DimmNumber = 0; +static UINT8 DimmSlot[4] = { DIMM1_SMBUS_ADDRESS, + DIMM2_SMBUS_ADDRESS, + DIMM3_SMBUS_ADDRESS, + DIMM4_SMBUS_ADDRESS + }; + +#define MRC_REF_CLOCK_133 (0) +#define MRC_REF_CLOCK_100 (1) +#define fNoInit (0) +#define f800 (800) +#define f1000 (1000) +#define f1067 (1067) +#define f1200 (1200) +#define f1333 (1333) +#define f1400 (1400) +#define f1600 (1600) +#define f1800 (1800) +#define f1867 (1867) +#define f2000 (2000) +#define f2133 (2133) +#define f2200 (2200) +#define f2400 (2400) +#define f2600 (2600) +#define f2667 (2667) +#define fUnSupport (0x7FFFFFFF) + +#define MRC_FREQUENCY_MTB_OFFSET 1000000 +#define MRC_FREQUENCY_FTB_OFFSET 1000 +#define MRC_DDR3_800_TCK_MIN 2500000 /// 1/(800/2) femtoseconds +#define MRC_DDR3_1000_TCK_MIN 2000000 /// 1/(1000/2) femtoseconds +#define MRC_DDR3_1067_TCK_MIN 1875000 /// 1/(1067/2) femtoseconds +#define MRC_DDR3_1200_TCK_MIN 1666666 /// 1/(1200/2) femtoseconds +#define MRC_DDR3_1333_TCK_MIN 1500000 /// 1/(1333/2) femtoseconds +#define MRC_DDR3_1400_TCK_MIN 1428571 /// 1/(1400/2) femtoseconds +#define MRC_DDR3_1600_TCK_MIN 1250000 /// 1/(1600/2) femtoseconds +#define MRC_DDR3_1800_TCK_MIN 1111111 /// 1/(1800/2) femtoseconds +#define MRC_DDR3_1867_TCK_MIN 1071428 /// 1/(1867/2) femtoseconds +#define MRC_DDR3_2000_TCK_MIN 1000000 /// 1/(2000/2) femtoseconds +#define MRC_DDR3_2133_TCK_MIN 937500 /// 1/(2133/2) femtoseconds +#define MRC_DDR3_2200_TCK_MIN 909090 /// 1/(2200/2) femtoseconds +#define MRC_DDR3_2400_TCK_MIN 833333 /// 1/(2400/2) femtoseconds +#define MRC_DDR3_2600_TCK_MIN 769230 /// 1/(2600/2) femtoseconds +#define MRC_DDR3_2667_TCK_MIN 750000 /// 1/(2667/2) femtoseconds +#define MRC_DDR3_2800_TCK_MIN 714285 /// 1/(2800/2) femtoseconds +#define TREFIMULTIPLIER 1000 /// tREFI value defined in XMP 1.3 spec is actually in thousands of MTB units. +#define MAX(a,b) (((a) > (b)) ? (a) : (b)) +#define MIN(a,b) (((a) < (b)) ? (a) : (b)) + +typedef struct { + UINT32 tCK; + UINT32 DDRFreq; + UINT8 RefClkFlag; // 0 = invalid freq. 1 = valid only at 133 RefClk, 2 = valid only at 100 RefClk, 3 = valid at both. +} NbTRangeTable; + +// Timing Range table +const NbTRangeTable NbRange[] = { + { 0xFFFFFFFF, fUnSupport, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_800_TCK_MIN, f800, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1000_TCK_MIN, f1000, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1067_TCK_MIN, f1067, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1200_TCK_MIN, f1200, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1333_TCK_MIN, f1333, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1400_TCK_MIN, f1400, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1600_TCK_MIN, f1600, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1800_TCK_MIN, f1800, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_1867_TCK_MIN, f1867, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2000_TCK_MIN, f2000, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2133_TCK_MIN, f2133, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2200_TCK_MIN, f2200, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2400_TCK_MIN, f2400, (1 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2600_TCK_MIN, f2600, (0 << MRC_REF_CLOCK_133) | (1 << MRC_REF_CLOCK_100) }, + { MRC_DDR3_2667_TCK_MIN, f2667, (1 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) }, + { 0, fNoInit, (0 << MRC_REF_CLOCK_133) | (0 << MRC_REF_CLOCK_100) } +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ReadSpdData +// +// Description: Returns the length of the Dimm Spd +// +// Input: UINT8 SpdSalveAddr, +// UINT8 Offset, +// UINTN Count, +// Output: UINT8 *Buffer +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS ReadSpdData ( + IN UINT8 SpdSalveAddr, + IN UINT8 Offset, + IN UINTN Count, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN Length; + EFI_SMBUS_OPERATION Operation; + EFI_SMBUS_DEVICE_COMMAND Command; + EFI_SMBUS_DEVICE_ADDRESS SlaveAddress; + + if(gSmbusProtocol == NULL) return EFI_UNSUPPORTED; + + SlaveAddress.SmbusDeviceAddress = SpdSalveAddr >> 1; + + for (Index = 0; Index < Count; Index++) + { + Command = Offset + Index; + + Length = 1; + Operation = EfiSmbusReadByte; + Status = gSmbusProtocol->Execute (gSmbusProtocol, + SlaveAddress, + Command, + Operation, + FALSE, + &Length, + &Buffer[Index] ); + if (EFI_ERROR(Status)) return Status; + } + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbGetDimmTCK +// +// Description: Returns the Dimm tCK Timing +// +// +// Input: UINT32 tCK +// +// Output: TRUE - Have tCK Timing +// FALSE - Not have tCK Timing +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +static BOOLEAN +NbGetDimmTCK ( + UINT8 SpdFtbDividend, + UINT8 SpdFtbDivisor, + UINT8 SpdMtbDividend, + UINT8 SpdMtbDivisor, + UINT8 tCKminMtb, +// UINT8 tCKminFine, // EIP249553 + INT8 tCKminFine, + OUT UINT32 *tCK + ) +{ + INT32 MediumTimebase = 0; + INT32 FineTimebase = 0; + + FineTimebase = (SpdFtbDivisor == 0) ? 0 : (SpdFtbDividend * MRC_FREQUENCY_FTB_OFFSET) / SpdFtbDivisor; + MediumTimebase = (SpdMtbDivisor == 0) ? 0 : (SpdMtbDividend * MRC_FREQUENCY_MTB_OFFSET) / SpdMtbDivisor; + *tCK = (MediumTimebase * tCKminMtb) + (FineTimebase * tCKminFine); + + return (MediumTimebase == 0) ? FALSE : TRUE; +} +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbGetDimmFrequency +// +// Description: Returns Dimm Frequency +// +// +// Input: UINT32 tCK +// +// Output: UINT32 XmpFrequency +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> + +static +UINT32 +NbGetDimmFrequency ( + IN UINT32 tCK + ) +{ + UINT32 Index; + UINT32 XmpFrequency = fNoInit; + UINT32 NbRangeSize = (sizeof (NbRange) / sizeof (NbTRangeTable)) - 1; + + if(tCK == 0 || tCK == 0xffffffff) return fNoInit; + + for (Index = 0; Index < NbRangeSize; Index++) { + if ((tCK <= NbRange[Index].tCK) && (tCK > NbRange[Index + 1].tCK)) { + XmpFrequency = NbRange[Index].DDRFreq; + break; + } + } + + while (Index) { + if ((NbRange[Index].RefClkFlag & (1 << gMemInfoHobProtocol->MemInfoData.RefClk)) == MRC_REF_CLOCK_133) { + XmpFrequency = NbRange[--Index].DDRFreq; + } else break; + } + + return XmpFrequency; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: NbSmbiosType17Voltage +// +// Description: To update MinimumVoltage, MaximumVoltage, ConfiguredVoltage +// and Dimm Frequency +// +// +// Input: SMBIOS_MEMORY_DEVICE_INFO *TypeBuffer +// +// Output: SMBIOS_MEMORY_DEVICE_INFO *TypeBuffer +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS NbSmbiosType17VoltageAndSpeed ( + IN OUT SMBIOS_MEMORY_DEVICE_INFO *TypeBuffer + ) +{ + UINT8 VoltageCap = 0; + UINT16 XmpId = 0; + UINT8 XmpProfileCap = 0; + UINT8 SpdFtbDividend = 0; + UINT8 SpdFtbDivisor = 0; + UINT8 SpdMtbDividend = 0; + UINT8 SpdMtbDivisor = 0; + UINT8 tCKminMtb = 0; +// UINT8 tCKminFine = 0; // EIP249553 + INT8 tCKminFine; + UINT32 tCK = 0; + UINT32 XmpProfile1Speed = 0; + UINT32 XmpProfile2Speed = 0; + UINT8 SpdData[18] = {6, 9, 10, 11, 12, 34, 176, 177, 178, 180, 181, 182, 183, 184, 186, 211, 221, 246}; + EFI_STATUS Status; + UINT8 i; + + // find DimmNumber + for ( ; DimmNumber < 4; DimmNumber++) { + if (DimmSlot[DimmNumber] != 0) break; + } + + if(gMemInfoHobProtocol != NULL) { + if (gMemInfoHobProtocol->MemInfoData.DimmExist[DimmNumber]) { // DIMM_PRESENT + for (i = 0; i < sizeof(SpdData) ; i++) { + // Get Spd data + Status = ReadSpdData(DimmSlot[DimmNumber], SpdData[i], 1, &SpdData[i]); + if (EFI_ERROR (Status)) { + // if memory down mode, use MemInfoHob + SpdData[i] = *(UINT8 *)(gMemInfoHobProtocol->MemInfoData.DimmsSpdData[DimmNumber] + SpdData[i]); + } + } + + XmpId = *(UINT16 *)&SpdData[6]; + + VoltageCap = SpdData[0]; + XmpProfileCap = SpdData[8]; + +#if defined AMI_SMBIOS_MODULE_VERSION && AMI_SMBIOS_MODULE_VERSION >= 105 + if (VoltageCap & 0x04) { // 1.25 v + TypeBuffer->MinimumVoltage = 1250; + } else if (VoltageCap & 0x02) { // 1.35 v + TypeBuffer->MinimumVoltage = 1350; + } else if (!(VoltageCap & 0x01)) { // 1.5 v bit0 = 0 + TypeBuffer->MinimumVoltage = 1500; + } + + if (!(VoltageCap & 0x01)) { // 1.5 v bit0 = 0 + TypeBuffer->MaximumVoltage = 1500; + } else if (VoltageCap & 0x02) { // 1.35 v + TypeBuffer->MaximumVoltage = 1350; + } else if (VoltageCap & 0x04) { // 1.25 v + TypeBuffer->MaximumVoltage = 1250; + } + + TypeBuffer->ConfiguredVoltage = gMemInfoHobProtocol->MemInfoData.VddVoltage[0]; +#endif + // Calculate Dimm STD Profile + SpdFtbDivisor = SpdData[1]; + SpdFtbDividend = (UINT8)(SpdFtbDivisor >> 4); + SpdFtbDivisor &= 0x0f; + SpdMtbDividend = SpdData[2]; + SpdMtbDivisor = SpdData[3]; + tCKminMtb = SpdData[4]; + tCKminFine = SpdData[5]; + // Get tCK Timing + if(NbGetDimmTCK(SpdFtbDividend, SpdFtbDivisor, SpdMtbDividend, SpdMtbDivisor, tCKminMtb, tCKminFine, &tCK)){ + // Get Dimm Frequency + TypeBuffer->Speed = NbGetDimmFrequency(tCK); + +#if defined DCLK_FREQUENCY && DCLK_FREQUENCY == 1 + // Get Dimm Frequency + if((NbGetDimmFrequency(tCK)%5) == 3) { + TypeBuffer->Speed = (NbGetDimmFrequency(tCK)/2)+1; + } else { + TypeBuffer->Speed = (NbGetDimmFrequency(tCK)/2); + } +#endif + } + + if(XmpId == 0x4A0C) { // is XMP + + // Calculate Dimm XMP Profile 1 + if (XmpProfileCap & 0x01) { + SpdFtbDivisor = SpdData[13]; + SpdFtbDividend = (UINT8)(SpdFtbDivisor >> 4); + SpdFtbDivisor &= 0x0f; + SpdMtbDividend = SpdData[9]; + SpdMtbDivisor = SpdData[10]; + tCKminMtb = SpdData[14]; + tCKminFine = SpdData[15]; + // Get tCK Timing + if(NbGetDimmTCK(SpdFtbDividend, SpdFtbDivisor, SpdMtbDividend, SpdMtbDivisor, tCKminMtb, tCKminFine, &tCK)){ + // Get Dimm Frequency + XmpProfile1Speed = NbGetDimmFrequency(tCK); + // Speed must MAX Speed. + TypeBuffer->Speed = MAX(TypeBuffer->Speed, XmpProfile1Speed); + +#if defined DCLK_FREQUENCY && DCLK_FREQUENCY == 1 + // Speed must MAX Speed. + TypeBuffer->Speed = MAX(TypeBuffer->Speed, ((XmpProfile1Speed/2)+1)); +#endif + } + } + + // Calculate Dimm XMP Profile 2 + if (XmpProfileCap & 0x02) { + SpdFtbDivisor = SpdData[13]; + SpdFtbDividend = (UINT8)(SpdFtbDivisor >> 4); + SpdFtbDivisor &= 0x0f; + SpdMtbDividend = SpdData[11]; + SpdMtbDivisor = SpdData[12]; + tCKminMtb = SpdData[16]; + tCKminFine = SpdData[17]; + // Get tCK Timing + if(NbGetDimmTCK(SpdFtbDividend, SpdFtbDivisor, SpdMtbDividend, SpdMtbDivisor, tCKminMtb, tCKminFine, &tCK)){ + // Get Dimm Frequency + XmpProfile2Speed = NbGetDimmFrequency(tCK); + // Speed must MAX Speed. + TypeBuffer->Speed = MAX(TypeBuffer->Speed, XmpProfile2Speed); + +#if defined DCLK_FREQUENCY && DCLK_FREQUENCY == 1 + // Speed must MAX Speed. + TypeBuffer->Speed = MAX(TypeBuffer->Speed, ((XmpProfile2Speed/2)+1)); +#endif + } + } + + } // if(XmpId == 0x4A0C) + } // if (gMemInfoHobProtocol.MemInfoData.DimmExist != DIMM_PRESENT) + } // if(gMemInfoHobProtocol != NULL) + + return EFI_SUCCESS; +}; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: GetStructureLength +// +// Description: Returns the length of the structure pointed by BufferStart +// in bytes +// +// Input: UINT8 *BufferStart +// +// Output: Structure Size +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT16 +GetStructureLength( + IN UINT8 *BufferStart +) +{ + UINT8 *BufferEnd = BufferStart; + + BufferEnd += ((SMBIOS_STRUCTURE_HEADER*)BufferStart)->Length; + while (*(UINT16*)BufferEnd != 0) + { + BufferEnd++; + } + + return (UINT16)(BufferEnd + 2 - BufferStart); // +2 for double zero terminator +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: FindStructureType +// +// Description: Find structure type starting from memory location pointed by +// Buffer +// +// Input: UINT8 **Buffer +// UINT8 **StructureFoundPtr +// UINT8 SearchType +// UINT8 Instance +// +// Output: If SearchType is found: +// UINT8 **Buffer - Points to the next structure +// UINT8 **StructureFoundPtr - Points to the structure +// that was found +// If SearchType is not found: +// UINT8 **Buffer - No change +// UINT8 **StructureFoundPtr = NULL +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +BOOLEAN +FindStructureType( + IN OUT UINT8 **Buffer, + IN OUT UINT8 **StructureFoundPtr, + IN UINT8 SearchType, + IN UINT8 Instance // 1-based +) +{ + UINT8 *BufferPtr = *Buffer; + BOOLEAN FindStatus = FALSE; + + *StructureFoundPtr = NULL; + while (((SMBIOS_STRUCTURE_HEADER*)BufferPtr)->Type != 127) + { + if (((SMBIOS_STRUCTURE_HEADER*)BufferPtr)->Type == SearchType) + { + // If this instance, set the find status flag and update the Buffer pointer + if (--Instance == 0) + { + FindStatus = TRUE; + *StructureFoundPtr = BufferPtr; + *Buffer = BufferPtr + GetStructureLength(BufferPtr); + break; + } + } + BufferPtr += GetStructureLength(BufferPtr); + } + + if ((FindStatus == FALSE) & (SearchType == 127)) + { + FindStatus = TRUE; + *StructureFoundPtr = BufferPtr; + *Buffer = BufferPtr + GetStructureLength(BufferPtr); + } + + return FindStatus; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType16 +// +// Description: Build SMBIOS Type 16 +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: +// None +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType16( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_PHYSICAL_MEM_ARRAY_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_PHYSICAL_MEM_ARRAY_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 16; // Type 16 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_PHYSICAL_MEM_ARRAY_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + // Build Content of structure + TypeBuffer->Location = MemorySubClassData->ArrayLocationData.MemoryArrayLocation; + TypeBuffer->Use = MemorySubClassData->ArrayLocationData.MemoryArrayUse; + TypeBuffer->MemErrorCorrection = MemorySubClassData->ArrayLocationData.MemoryErrorCorrection; + TypeBuffer->MaxCapacity = MemorySubClassData->ArrayLocationData.MaximumMemoryCapacity; + if (TypeBuffer->MaxCapacity >= 0x80000000) + { + TypeBuffer->ExtMaxCapacity = TypeBuffer->MaxCapacity; + TypeBuffer->MaxCapacity = 0x80000000; + } + else + { + TypeBuffer->ExtMaxCapacity = 0; + } + + // + // Maximum memory supported by the memory controller + // 2 GB in terms of KB + // +#if MEMORY_ERROR_INFO + TypeBuffer->MemErrInfoHandle = SMBIOS_UNKNOW; +#else + TypeBuffer->MemErrInfoHandle = SMBIOS_NOT_PROVIDE; +#endif + TypeBuffer->NumberOfMemDev = MemorySubClassData->ArrayLocationData.NumberMemoryDevices; + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType17 +// +// Description: Build SMBIOS Type 17 +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType17( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_MEMORY_DEVICE_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_MEMORY_DEVICE_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 17; // Type 17 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_MEMORY_DEVICE_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + // Build Content of structure + TypeBuffer->PhysicalMemArrayHandle = (UINT16)gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 16, 1); +#if MEMORY_ERROR_INFO + TypeBuffer->MemErrorInfoHandle = SMBIOS_UNKNOW; +#else + TypeBuffer->MemErrorInfoHandle = SMBIOS_NOT_PROVIDE; +#endif + TypeBuffer->TotalWidth = MemorySubClassData->ArrayLink.MemoryTotalWidth; + TypeBuffer->DataWidth = MemorySubClassData->ArrayLink.MemoryDataWidth; + TypeBuffer->Size = (UINT16) (RShiftU64 (MemorySubClassData->ArrayLink.MemoryDeviceSize, 20)); + TypeBuffer->FormFactor = MemorySubClassData->ArrayLink.MemoryFormFactor; + TypeBuffer->DeviceSet = MemorySubClassData->ArrayLink.MemoryDeviceSet; + TypeBuffer->DeviceLocator = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryDeviceLocator); + TypeBuffer->BankLocator = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryBankLocator); + TypeBuffer->MemoryType = MemorySubClassData->ArrayLink.MemoryType; + TypeBuffer->TypeDetail = *((UINT16*)(&(MemorySubClassData->ArrayLink.MemoryTypeDetail))); + TypeBuffer->Speed = 0; + TypeBuffer->Manufacturer = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryManufacturer); + TypeBuffer->SerialNumber = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemorySerialNumber); + TypeBuffer->AssetTag = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryAssetTag); + TypeBuffer->PartNumber = TransferHiiStringToSmbios((UINT8 *)TypeBuffer, MemorySubClassData->ArrayLink.MemoryPartNumber); + TypeBuffer->Attributes = MemorySubClassData->ArrayLink.MemoryAttributes; + TypeBuffer->ConfMemClkSpeed = MemorySubClassData->ArrayLink.MemorySpeed; +#if defined DCLK_FREQUENCY && DCLK_FREQUENCY == 1 + TypeBuffer->ConfMemClkSpeed = ((MemorySubClassData->ArrayLink.MemorySpeed)/2)+1; +#endif + TypeBuffer->ExtendedSize = 0; +#if defined AMI_SMBIOS_MODULE_VERSION && AMI_SMBIOS_MODULE_VERSION >= 105 + TypeBuffer->MinimumVoltage = 0; // unknown SmBios 2.8.0+ + TypeBuffer->MaximumVoltage = 0; // unknown SmBios 2.8.0+ + TypeBuffer->ConfiguredVoltage = 0; // unknown SmBios 2.8.0+ +#endif + + if (TypeBuffer->Size >= 0x8000 ) // 32G + { + TypeBuffer->ExtendedSize = TypeBuffer->Size; + + // ExtendedSize Bit 31 is reserved for future use and must be set to 0. + if (TypeBuffer->ExtendedSize >= BIT31) { + TypeBuffer->ExtendedSize = BIT31 - 1; + } + TypeBuffer->Size = 0x7FFF; + } + + // SmBios 2.8.0+ + // To update MinimumVoltage, MaximumVoltage, ConfiguredVoltage and Dimm Frequency + NbSmbiosType17VoltageAndSpeed (TypeBuffer); + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); +} + +#if MEMORY_ERROR_INFO +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType18 +// +// Description: Build SMBIOS Type 18 +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType18( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_MEMORY_ERROR_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_MEMORY_ERROR_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 18; // Type 18 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_MEMORY_ERROR_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.ErrorType = 3; + TypeBuffer->ErrorType = 3; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.ErrorGranularity = 2; + TypeBuffer->ErrorGranularity = 2; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.ErrorOperation = 2; + TypeBuffer->ErrorOperation = 2; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.MemArrayErrorAddress = 0x80000000; + TypeBuffer->MemArrayErrorAddress = 0x80000000; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.DeviceErrorAddress = 0x80000000; + TypeBuffer->DeviceErrorAddress = 0x80000000; + //Memory.PhysicalMemArray[PMAIdx].ArrayMemoryError.ErrorResolution = 0x80000000; + TypeBuffer->ErrorResolution = 0x80000000; + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); + +} +#endif + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType19 +// +// Description: Build SMBIOS Type 19 +// +// +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType19( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_MEM_ARRAY_MAP_ADDR_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_MEM_ARRAY_MAP_ADDR_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 19; // Type 19 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_MEM_ARRAY_MAP_ADDR_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + // Build Content of structure + TypeBuffer->StartingAddress = (UINT32)(MemorySubClassData->ArrayStartAddress.MemoryArrayStartAddress / 1024); + TypeBuffer->EndingAddress = (UINT32)(MemorySubClassData->ArrayStartAddress.MemoryArrayEndAddress / 1024); + TypeBuffer->MemoryArrayHandle = (UINT16)gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 16, 0); + TypeBuffer->PartitionWidth = (UINT8) MemorySubClassData->ArrayStartAddress.MemoryArrayPartitionWidth; + TypeBuffer->ExtendedStartAddr = (MemorySubClassData->ArrayStartAddress.MemoryArrayStartAddress / 1024); + if ((MemorySubClassData->ArrayStartAddress.MemoryArrayEndAddress / 1024) >= 0xFFFFFFFF) + { + TypeBuffer->ExtendedEndAddr = (MemorySubClassData->ArrayStartAddress.MemoryArrayEndAddress / 1024); + TypeBuffer->EndingAddress = 0xFFFFFFFF; + } + else + { + TypeBuffer->ExtendedEndAddr = 0; + } + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: BuildType20 +// +// Description: Build SMBIOS Type 20 +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +BuildType20( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData +) +{ + SMBIOS_MEM_DEV_MAP_ADDR_INFO *TypeBuffer; + UINT16 bsize; + + // Allocate temporary buffer + TypeBuffer = EfiLibAllocateZeroPool(sizeof(SMBIOS_MEM_DEV_MAP_ADDR_INFO)+0x100); + + // Build header of structure + TypeBuffer->StructureType.Type = 20; // Type 20 + TypeBuffer->StructureType.Length = sizeof(SMBIOS_MEM_DEV_MAP_ADDR_INFO); + TypeBuffer->StructureType.Handle = gSBUpdate->SMBIOS_GetFreeHandle(SmbiosBuffer); + + // Build Content of structure + TypeBuffer->StartingAddress = (UINT32)(MemorySubClassData->DeviceStartAddress.MemoryDeviceStartAddress / 1024); + TypeBuffer->EndingAddress = (UINT32)(MemorySubClassData->DeviceStartAddress.MemoryDeviceEndAddress / 1024); + + TypeBuffer->MemoryDeviceHandle = SMBIOS_UNKNOW; + TypeBuffer->MemoryArrayMapAddrHandle = (UINT16)gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 19, 1); + + TypeBuffer->PartitionRowPosition = 0xFF;// unknow type. + //MemorySubClassData->DeviceStartAddress.MemoryDevicePartitionRowPosition; + TypeBuffer->InterleavePosition = 0xFF;// unknow type. + //MemorySubClassData->DeviceStartAddress.MemoryDeviceInterleavePosition; + TypeBuffer->InterleaveDataDepth = 0xFF;// unknow type. + //MemorySubClassData->DeviceStartAddress.MemoryDeviceInterleaveDataDepth; + if ((MemorySubClassData->DeviceStartAddress.MemoryDeviceEndAddress / 1024) >= 0xFFFFFFFF) + { + TypeBuffer->ExtendedEndAddr = (MemorySubClassData->DeviceStartAddress.MemoryDeviceEndAddress / 1024); + TypeBuffer->EndingAddress = 0xFFFFFFFF; + } + else + { + TypeBuffer->ExtendedEndAddr = 0; + } + + // Write structure To SMBIOS Buffer + bsize = SMBIOS_GetStructureTotalSize((UINT8 *)TypeBuffer); + gSBUpdate->SMBIOS_InsertStructure(SmbiosBuffer, (UINT8 *)TypeBuffer, bsize); + + // Fix handle link + SMBIOS_FixHandleLink(SmbiosBuffer); + + // Free temporary buffer + gBS->FreePool(TypeBuffer); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SmbiosProcessMemoryDataRecord +// +// Description: +// This function parses the data record and stores it into the Smbios format +// +// Input: EFI_DATA_RECORD_HEADER *Record, +// SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +// +// Output: None +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +SmbiosProcessMemoryDataRecord( + IN EFI_DATA_RECORD_HEADER *Record, + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +) +{ + UINT8 *SrcData; + EFI_SUBCLASS_TYPE1_HEADER *DataHeader; + EFI_MEMORY_SUBCLASS_RECORDS *MemorySubClassData; + + if (EfiCompareGuid (&Record->DataRecordGuid, &gEfiMemorySubClassGuid)) + { + DEBUG((EFI_D_ERROR, "SMBIOS Memory Record Address:0x%X\n", Record)); + + DataHeader = (EFI_SUBCLASS_TYPE1_HEADER *) (Record + 1); + SrcData = (UINT8 *) (DataHeader + 1); + MemorySubClassData = (EFI_MEMORY_SUBCLASS_RECORDS *) SrcData; + + switch (DataHeader->RecordType) + { + case EFI_MEMORY_ARRAY_LOCATION_RECORD_NUMBER: // 16 + BuildType16(SmbiosBuffer, MemorySubClassData); + break; + case EFI_MEMORY_ARRAY_LINK_RECORD_NUMBER: // 17 + BuildType17(SmbiosBuffer, MemorySubClassData); +#if MEMORY_ERROR_INFO + BuildType18(SmbiosBuffer, MemorySubClassData); // 18 +#endif + // next dimm + DimmNumber ++; + break; + case EFI_MEMORY_ARRAY_START_ADDRESS_RECORD_NUMBER: // 19 + BuildType19(SmbiosBuffer, MemorySubClassData); + break; + case EFI_MEMORY_DEVICE_START_ADDRESS_RECORD_NUMBER: // 20 + BuildType20(SmbiosBuffer, MemorySubClassData); + break; + } + } + + return; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: DynamicUpdateMemoryRecord +// +// Description: Updates Memory related structures (Type 16-20) in +// input Buffer with dynamically detected Record for Intel Tiano +// SmBiosMemory Driver. +// +// Input: UINT8 *Buffer +// +// Output: EFI_STATUS - EFI_SUCCESS +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS DynamicUpdateMemoryRecord( + IN SMBIOS_TABLE_ENTRY_POINT *Buffer +) +{ + EFI_STATUS Status; + EFI_HANDLE DataHubHandle; + UINTN HandleSize; + UINT64 MonotonicCount; + EFI_DATA_HUB_PROTOCOL *DataHub; + EFI_DATA_RECORD_HEADER *Record; + EFI_GUID gEfiDataHubProtocolGuid = EFI_DATA_HUB_PROTOCOL_GUID; + UINT8 BitIndex; + + Status = EFI_SUCCESS; + DataHub = NULL; + + // + // Get the SmbusProtocol. + // + Status = gBS->LocateProtocol( &gEfiSmbusProtocolGuid, \ + NULL, \ + &gSmbusProtocol ); + // + // Get the MemInfoHobProtocol. + // + Status = gBS->LocateProtocol (&gMemInfoHobProtocolGuid, \ + NULL, \ + &gMemInfoHobProtocol); + + // + // Get the DxePlatformSaPolicyProtocol. + // + Status = gBS->LocateProtocol (&gDxePlatformSaPolicyGuid, \ + NULL, \ + &gDxePlatformSaPolicy); + if (EFI_ERROR (Status)) return Status; + + // Check User Dimm Map + for (BitIndex = 0; BitIndex < 2; BitIndex++) { + if (!((gDxePlatformSaPolicy->MemoryConfig->ChannelASlotMap >> BitIndex) & BIT0)) { + DimmSlot[BitIndex] = 0; //if not, Clear Spd sddress; + } + if (!((gDxePlatformSaPolicy->MemoryConfig->ChannelBSlotMap >> BitIndex) & BIT0)) { + DimmSlot[BitIndex + 2] = 0; //if not, Clear Spd sddress; + } + } + + // + // Get the Data Hub Protocol. Assume only one instance + // of Data Hub Protocol is availabe in the system. + // + HandleSize = sizeof (EFI_HANDLE); + + Status = gBS->LocateHandle ( + ByProtocol, + &gEfiDataHubProtocolGuid, + NULL, + &HandleSize, + &DataHubHandle + ); + + if (EFI_ERROR (Status)) + { + return EFI_SUCCESS; + } + Status = gBS->HandleProtocol ( + DataHubHandle, + &gEfiDataHubProtocolGuid, + &DataHub + ); + + if (EFI_ERROR (Status)) + { + return EFI_SUCCESS; + } +#if defined (MEMORY_DEVICE_INFO) && MEMORY_DEVICE_INFO == 1 + // Clean strcutures which need rebuild + SMBIOS_DeleteStructureByType(Buffer, 16, SMBIOS_FOR_ALL); + SMBIOS_DeleteStructureByType(Buffer, 17, SMBIOS_FOR_ALL); +#if defined (MEMORY_ERROR_INFO) && MEMORY_ERROR_INFO == 1 + SMBIOS_DeleteStructureByType(Buffer, 18, SMBIOS_FOR_ALL); +#endif + SMBIOS_DeleteStructureByType(Buffer, 19, SMBIOS_FOR_ALL); + SMBIOS_DeleteStructureByType(Buffer, 20, SMBIOS_FOR_ALL); +#endif + // + // Get all available data records from data hub + // + MonotonicCount = 0; + Record = NULL; + + do { + Status = DataHub->GetNextRecord ( + DataHub, + &MonotonicCount, + NULL, + &Record + ); + + if (!EFI_ERROR (Status)) + { + if (Record->DataRecordClass == EFI_DATA_RECORD_CLASS_DATA) + { + SmbiosProcessMemoryDataRecord (Record, Buffer); + } + } + } while (!EFI_ERROR (Status) && (MonotonicCount != 0)); + + return EFI_SUCCESS; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMIBiosUpdateMemoryRecordDriverEntryPoint +// +// Description: Update memory record DXE driver for Intel Tiano SmBiosMemory Driver. +// +// Input: ImageHandle - Image handle. +// SystemTable - Pointer to the system table. +// +// Output: EFI_STATUS - EFI_SUCCESS. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +EFI_STATUS SMIBiosUpdateMemoryRecordDriverEntryPoint( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + EFI_GUID gEfiSmbiosProtocolGuid = EFI_SMBIOS_PROTOCOL_GUID; + SMBIOS_TABLE_ENTRY_POINT *SmbiosTableEntryPoint; + + DxeInitializeDriverLib (ImageHandle, SystemTable); + Status = gBS->LocateProtocol(&gEfiSmbiosUpdateDataProtocolGuid, NULL, &gSBUpdate); + ASSERT_EFI_ERROR(Status); + + Status = gBS->LocateProtocol(&gEfiSmbiosProtocolGuid, NULL, &gSmbiosProtocol); + ASSERT_EFI_ERROR(Status); + SmbiosTableEntryPoint = gSmbiosProtocol->SmbiosGetTableEntryPoint(); + + Status = DynamicUpdateMemoryRecord(SmbiosTableEntryPoint); + ASSERT_EFI_ERROR(Status); + + return EFI_SUCCESS; +} + +//----------------------------------------------------------------------------- +// SMBIOS Dynamic Maintain Functions +//----------------------------------------------------------------------------- + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_DeleteStructureByType +// +// Description: SMBIOS Delete Structure Type +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, +// UINT8 Type, +// UINT8 Index +// +// Output: UINTN count +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINTN +SMBIOS_DeleteStructureByType( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + IN UINT8 Type, + IN UINT8 Index +) +{ + UINT8 i; + UINT16 handle; + UINTN count; + + count = 0; + if (Index != SMBIOS_FOR_ALL) + { // for Single + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, Type, Index); + if (handle != SMBIOS_NOT_FOUND) + { + gSBUpdate->SMBIOS_DeleteStructure(SmbiosBuffer, handle); + } + } else { // -1 for ALL + for(i = 0; i < MAX_HANDLES; i++) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, Type, 1); + if (handle != SMBIOS_NOT_FOUND) + { + gSBUpdate->SMBIOS_DeleteStructure(SmbiosBuffer, handle); + count++; + } + } + } + + return count; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_GetStructureTotalSize +// +// Description: SMBIOS get structure total size +// +// Input: UINT8 *BufferStart +// +// Output: UINT16 Total Size. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT16 +SMBIOS_GetStructureTotalSize( + IN UINT8 *BufferStart +) +{ + UINT8 *BufferEnd; + + BufferEnd = BufferStart; + BufferEnd += ((SMBIOS_STRUCTURE_HEADER*)BufferStart)->Length; + while (*(UINT16*)BufferEnd != 0) + { + BufferEnd++; + } + + return (UINT16)(BufferEnd + 2 - BufferStart); // +2 for double zero terminator +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_GetStringBase +// +// Description: SMBIOS get String Base +// +// Input: UINT8 *Buffer +// +// Output: UINT8 Buffer +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8* SMBIOS_GetStringBase( + IN UINT8 *Buffer +) +{ + SMBIOS_STRUCTURE_HEADER *p; + + p = (SMBIOS_STRUCTURE_HEADER *)Buffer; + Buffer += p->Length; + + return Buffer; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_NextString +// +// Description: SMBIOS next String +// +// Input: UINT8 *String +// +// Output: String point. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8* SMBIOS_NextString( + IN UINT8 *String +) +{ + return String+(EfiAsciiStrLen(String)+1); +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_FindString +// +// Description: SMBIOS find String +// +// Input: CHAR8 *Buffer +// CHAR8 *String +// +// Output: String point. +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +SMBIOS_FindString( + IN CHAR8 *Buffer, + IN CHAR8 *String +) +{ + CHAR8 *sp; + UINT8 i; + UINTN quit; + UINTN l; + + quit = 0; + i = 1; + sp = SMBIOS_GetStringBase(Buffer); + while (quit == 0) + { + l = EfiAsciiStrLen(sp); + if (l == 0) + { + i = 0xFF; + quit = 1; + } else if (EfiAsciiStrCmp(String, sp) == 0) + { + quit = 1; + } else { + sp = SMBIOS_NextString(sp); + i++; + } + } + + return i; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_AddString +// +// Description: SMBIOS add String +// +// Input: CHAR8 *Buffer +// CHAR8 *String +// +// Output: UINT8 +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +SMBIOS_AddString( + IN CHAR8 *Buffer, + IN CHAR8 *String +) +{ + CHAR8 *sp; + UINT8 i; + UINTN l; + + if (EfiAsciiStrLen(String) == 0) + { + EfiAsciiStrCpy(String, "[Empty]"); + } + + i = 1; + sp = SMBIOS_GetStringBase(Buffer); + while ((l = EfiAsciiStrLen(sp)) != 0) + { + sp = sp + (l+1); + i++; + } + + EfiAsciiStrCpy(sp, String); + sp = SMBIOS_NextString(sp); + *sp = 0; + + return i; + +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: SMBIOS_FixHandleLink +// +// Description: SMBIOS fix handle link +// +// Input: SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +// +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +SMBIOS_FixHandleLink( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +) +{ + UINT16 handle; + SMBIOS_PHYSICAL_MEM_ARRAY_INFO *T16_p; + SMBIOS_MEMORY_DEVICE_INFO *T17_p; + SMBIOS_MEM_ARRAY_MAP_ADDR_INFO *T19_p; + SMBIOS_MEM_DEV_MAP_ADDR_INFO *T20_p; + UINT16 T19_Handle; + UINT16 T17_Size_KB; + UINT16 T20_Size_KB; + UINTN Q_flag; + UINT8 i, j; +#if MEMORY_ERROR_INFO + SMBIOS_MEMORY_ERROR_INFO *T18_p = NULL; +#endif + + T16_p = NULL; + T17_p = NULL; + T19_p = NULL; + T20_p = NULL; + T19_Handle = SMBIOS_UNKNOW; + Q_flag = 0; + T17_Size_KB = 0; + + // Looking for Type 19 to set MemoryArrayHandle + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 19, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T19_p = (SMBIOS_MEM_ARRAY_MAP_ADDR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T19_Handle = T19_p->StructureType.Handle; + if (T19_p->MemoryArrayHandle == SMBIOS_UNKNOW) + { + // Looking for Type 16 + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 16, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T16_p = (SMBIOS_PHYSICAL_MEM_ARRAY_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T19_p->MemoryArrayHandle = T16_p->StructureType.Handle; + } + } + } + +#if MEMORY_ERROR_INFO + // Looking for Type 16 + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 16, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T16_p = (SMBIOS_PHYSICAL_MEM_ARRAY_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + if (T16_p->MemErrInfoHandle == SMBIOS_UNKNOW) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 18, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T18_p = (SMBIOS_MEMORY_ERROR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T16_p->MemErrInfoHandle = T18_p->StructureType.Handle; + } + } + } + + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 17, 1); + if (handle != SMBIOS_NOT_FOUND) + { + T17_p = (SMBIOS_MEMORY_DEVICE_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + if (T17_p->MemErrorInfoHandle == SMBIOS_UNKNOW) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 18, 2); + if (handle != SMBIOS_NOT_FOUND) + { + T18_p = (SMBIOS_MEMORY_ERROR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T17_p->MemErrorInfoHandle = T18_p->StructureType.Handle; + } + } + } + + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 17, 3); + if (handle != SMBIOS_NOT_FOUND) + { + T17_p = (SMBIOS_MEMORY_DEVICE_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + if (T17_p->MemErrorInfoHandle == SMBIOS_UNKNOW) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 18, 3); + if (handle != SMBIOS_NOT_FOUND) + { + T18_p = (SMBIOS_MEMORY_ERROR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T17_p->MemErrorInfoHandle = T18_p->StructureType.Handle; + } + } + } +#endif + + Q_flag = 0; + // Looking for Type 20 to set MemoryArrayMapAddrHandle and MemoryDeviceHandle + for(i = 1; i < MAX_HANDLES; i++) + { + T20_Size_KB = 0; + + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 20, i); + if (handle != SMBIOS_NOT_FOUND) + { + T20_p = (SMBIOS_MEM_DEV_MAP_ADDR_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + T20_p->MemoryArrayMapAddrHandle = T19_Handle; + if (T20_p->MemoryDeviceHandle == SMBIOS_UNKNOW) + { + T20_Size_KB =(UINT16) T20_p->EndingAddress + 1; + + // Looking for Type 17 + for(j = i; j < MAX_HANDLES; j++) + { + handle = gSBUpdate->SMBIOS_FindStructure(SmbiosBuffer, 17, j); + if (handle != SMBIOS_NOT_FOUND) + { + T17_p = (SMBIOS_MEMORY_DEVICE_INFO *)gSBUpdate->SMBIOS_GetStructureBase(SmbiosBuffer, handle); + + T17_Size_KB = (T17_p->Size & 0x7FFF) * ((T17_p->Size & 0x8000) ? 1 : 1024); + if (T17_Size_KB == T20_Size_KB) + { + T20_p->MemoryDeviceHandle = T17_p->StructureType.Handle; + } + } + } + } + Q_flag++; + } + + if (Q_flag == 0) + break; + } +} + +#if (EFI_SPECIFICATION_VERSION < 0x0002000A) +//----------------------------------------------------------------------------- +// HII Functions +//----------------------------------------------------------------------------- +EFI_HII_HANDLE HiiHandle; +EFI_HII_PROTOCOL *Hii = NULL; + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: InitHiiString +// +// Description: Init Hii string +// +// Input: VOID +// +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +InitHiiString(VOID) +{ + EFI_STATUS Status; + UINT16 HandleBufferLength; + EFI_HII_HANDLE *HiiHandleBuffer; + UINTN NumberOfHiiHandles; + UINTN Index; + UINT16 Length; + EFI_GUID HiiGuid; + + if (Hii == NULL) + { + HandleBufferLength = 0x1000; + HiiHandleBuffer = NULL; + HiiHandle = 0; + + // + // Locate HII protocol + // + Status = gBS->LocateProtocol (&gEfiHiiProtocolGuid, NULL, &Hii); + ASSERT_EFI_ERROR (Status); + + HiiHandleBuffer = EfiLibAllocateZeroPool (HandleBufferLength); + + Status = Hii->FindHandles (Hii, &HandleBufferLength, HiiHandleBuffer); + ASSERT_EFI_ERROR (Status); + + // + // Get the Hii Handle that matches the StructureNode->ProducerName + // + NumberOfHiiHandles = HandleBufferLength / sizeof (EFI_HII_HANDLE); + for (Index = 0; Index < NumberOfHiiHandles; Index++) + { + Length = 0; + Status = ExtractDataFromHiiHandle ( + HiiHandleBuffer[Index], + &Length, + NULL, + &HiiGuid + ); + if (EfiCompareGuid (&gEfiMemorySubClassDriverGuid, &HiiGuid)) + { + HiiHandle = HiiHandleBuffer[Index]; + break; + } + } + gBS->FreePool (HiiHandleBuffer); + } +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: HiiGetString +// +// Description: Init get string +// +// Input: STRING_REF Token +// +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +CHAR16 * +HiiGetString( + IN STRING_REF Token +) +{ + UINTN StringBufferLength; + CHAR16 *StringBuffer; + EFI_STATUS Status; + + InitHiiString(); + + Status = EFI_SUCCESS; + StringBufferLength = 0x100; + StringBuffer = EfiLibAllocateZeroPool(StringBufferLength); + ASSERT(StringBuffer); + + // + // Find the string based on the current language + // + Status = Hii->GetString ( + Hii, + HiiHandle, + Token, + FALSE, + NULL, + &StringBufferLength, + StringBuffer + ); + + if (EFI_ERROR (Status)) + { + gBS->FreePool(StringBuffer); + StringBuffer = NULL; + } + + return StringBuffer; +} +#endif //EFI_SPECIFICATION_VERSION < 0x0002000A + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: ConvertChar16ToChar8 +// +// Description: Convert char 16 to char 8 +// +// Input: CHAR8 *Dest +// CHAR16 *Src +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +VOID +ConvertChar16ToChar8 ( + IN CHAR8 *Dest, + IN CHAR16 *Src +) +{ + while (*Src) + { + *Dest++ = (UINT8) (*Src++); + } + + *Dest = 0; +} + +//<AMI_PHDR_START> +//---------------------------------------------------------------------------- +// Procedure: TransferHiiStringToSmbios +// +// Description: Transfer Hii string to Smbios +// +// Input: CHAR8 *Structure +// STRING_REF Token +// +// Output: VOID +// +//---------------------------------------------------------------------------- +//<AMI_PHDR_END> +UINT8 +TransferHiiStringToSmbios ( + IN UINT8 *Structure, + IN STRING_REF Token +) +{ + CHAR8 *Buffer; + UINTN BufferSize; + UINT8 i; + CHAR16 *String; + +#if (EFI_SPECIFICATION_VERSION >= 0x0002000A) + EFI_STATUS Status; +#endif + + BufferSize = 0x100; + Buffer = EfiLibAllocateZeroPool(BufferSize); + ASSERT(Buffer); + i = (UINT8) -1; + +#if (EFI_SPECIFICATION_VERSION < 0x0002000A) + String = HiiGetString(Token); +#else + + Status = GetStringFromToken (&gEfiMemorySubClassDriverGuid, Token, (EFI_STRING *)&String); + ASSERT_EFI_ERROR(Status); + +#endif + + ConvertChar16ToChar8(Buffer, String); + + i = SMBIOS_AddString(Structure, Buffer); + gBS->FreePool(String); + gBS->FreePool(Buffer); + return i; +} + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.cif b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.cif new file mode 100644 index 0000000..e0e556e --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.cif @@ -0,0 +1,12 @@ +<component> + name = "UpdateMemoryRecord" + category = ModulePart + LocalRoot = "Chipset\NB\SystemAgentWrap\UpdateMemoryRecord" + RefName = "UpdateMemoryRecord" +[files] +"UpdateMemoryRecord.sdl" +"UpdateMemoryRecord.mak" +"UpdateMemoryRecord.dxs" +"UpdateMemoryRecord.c" +"UpdateMemoryRecord.h" +<endComponent> diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs new file mode 100644 index 0000000..fe4a9cb --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs @@ -0,0 +1,86 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs 2 8/31/12 2:38a Yurenlai $ +// +// $Revision: 2 $ +// +// $Date: 8/31/12 2:38a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.dxs $ +// +// 2 8/31/12 2:38a Yurenlai +// [TAG] EIP99526 +// [Category] Improvement +// [Severity] Important +// [Description] Fixed system hang at CKP 0x6A if +// PI_SPECIFICATION_VERSION = 0x10000. +// [Files] UpdateMemoryRecord.dxs +// +// 1 2/08/12 4:37a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* + +#if (PI_SPECIFICATION_VERSION < 0x10014) +#include <Token.h> +#include <protocol\SmbiosGetFlashDataProtocol.h> +#define __AMIHOBS_H__ +#include <protocol\SmbiosDynamicData.h> +#include <Protocol\Datahub.h> +#if (EFI_SPECIFICATION_VERSION >= 0x0002000A) +#include <Protocol/HiiDatabase.h> +#else +#include <Protocol/HII.h> +#endif +#define __EFI__H__ +#include <Protocol\Smbus.h> +#include <SmbiosUpdateDataProtocol.h> +#include <SaInfo\SaInfo.h> + +DEPENDENCY_START + EFI_SMBIOS_BOARD_PROTOCOL_GUID AND + EFI_DATA_HUB_PROTOCOL_GUID AND +#if (EFI_SPECIFICATION_VERSION >= 0x0002000A) + EFI_HII_DATABASE_PROTOCOL_GUID AND +#else + EFI_HII_PROTOCOL_GUID AND +#endif + EFI_SA_INFO_PROTOCOL_GUID AND + EFI_SMBUS_HC_PROTOCOL_GUID AND + EFI_SMBIOS_PROTOCOL_GUID AND + EFI_SMBIOS_UPDATE_DATA_PROTOCOL_GUID +DEPENDENCY_END +#else +DEPENDENCY_START + AFTER {0xEDA39402, 0xF375, 0x4496, 0x92, 0xD3, 0x83, 0xB4, 0x3C, 0xB8, 0xA7, 0x6A} +DEPENDENCY_END +#endif + +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h new file mode 100644 index 0000000..254f132 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h @@ -0,0 +1,108 @@ +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//************************************************************************* + +//************************************************************************* +// $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h 1 2/08/12 4:37a Yurenlai $ +// +// $Revision: 1 $ +// +// $Date: 2/08/12 4:37a $ +//************************************************************************* +// Revision History +// ---------------- +// $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.h $ +// +// 1 2/08/12 4:37a Yurenlai +// Intel Haswell/NB eChipset initially releases. +// +//************************************************************************* +//<AMI_FHDR_START> +// +// Name: UpdateMemoryRecord.h +// +// Description: +// +//<AMI_FHDR_END> +//********************************************************************** +#ifndef __UPDATE_MEMORY_RECORD_H__ +#define __UPDATE_MEMORY_RECORD_H__ + +#include <Tiano.h> +#include <Protocol\SMBios.h> +#include <Protocol\SmbiosGetFlashDataProtocol.h> +#include "EfiDriverLib.h" +#include "Guid\DataHubRecords\DataHubSubClassMemory.h" +#include "SmbiosUpdateDataProtocol.h" + +#if (EFI_SPECIFICATION_VERSION >= 0x0002000A) +#include "UefiIfrLibrary.h" +#include EFI_PROTOCOL_DEPENDENCY (HiiDatabase) +#include EFI_PROTOCOL_DEPENDENCY (HiiString) +#else +#include "Library\Dxe\EfiIfrSupportLib\IfrLibrary.h" +#include EFI_PROTOCOL_DEPENDENCY (Hii) +#endif + +#define SMBIOS_NOT_FOUND 0xFFFF +#define SMBIOS_UNKNOW 0xFFFF +#define SMBIOS_NOT_PROVIDE 0xFFFE +#define MAX_HANDLES 0x10 +#define SMBIOS_FOR_ALL 0xFF + +VOID +SMBIOS_FixHandleLink( + IN SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer +); + +EFI_STATUS +ExtractDataFromHiiHandle ( + IN EFI_HII_HANDLE HiiHandle, + IN OUT UINT16 *ImageLength, + OUT UINT8 *DefaultImage, + OUT EFI_GUID *Guid +); + + +UINT8 +TransferHiiStringToSmbios ( + IN UINT8 *Structure, + IN STRING_REF Token +); + +UINT16 +SMBIOS_GetStructureTotalSize( + IN UINT8 *BufferStart +); + +UINTN +SMBIOS_DeleteStructureByType ( + SMBIOS_TABLE_ENTRY_POINT *SmbiosBuffer, + UINT8 Type, + UINT8 Index +); + +#endif +//************************************************************************* +//************************************************************************* +//** ** +//** (C)Copyright 1985-2011, American Megatrends, Inc. ** +//** ** +//** All Rights Reserved. ** +//** ** +//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +//** ** +//** Phone: (770)-246-8600 ** +//** ** +//************************************************************************* +//*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.mak b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.mak new file mode 100644 index 0000000..df6ad4a --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.mak @@ -0,0 +1,44 @@ +# /*++ +# Copyright (c) 2011 Intel Corporation. All rights reserved. +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# --*/ +all : UpdateMemoryRecord + +UpdateMemoryRecord : $(BUILD_DIR)\UpdateMemoryRecord.mak UpdateMemoryRecordBin + +$(BUILD_DIR)\UpdateMemoryRecord.mak : $(UpdateMemroyRecord_DIR)\UpdateMemoryRecord.CIF $(UpdateMemroyRecord_DIR)\$(@B).mak $(BUILD_RULES) + $(CIF2MAK) $(UpdateMemroyRecord_DIR)\UpdateMemoryRecord.CIF $(CIF2MAK_DEFAULTS) + +MemoryRecord_INCLUDES = \ + $(EDK_INCLUDES)\ + $(INTEL_MCH_INCLUDES) \ + /I$(SMBIOSUpdateData_DIR)\ + /I$(UefiEfiIfrSupportLib_DIR)\ + /I$(PROJECT_DIR)\ + /IInclude\ + +MemoryRecord_LIB_LINKS =\ + $(EFIDRIVERLIB)\ +!IF $(EFI_SPECIFICATION_VERSION) >= 0x2000A + $(UEFIEFIIFRSUPPORTLIB) +!ELSE + $(EFIIFRSUPPORTLIB)\ +!ENDIF + +UpdateMemoryRecordBin : $(MemoryRecord_LIB_LINKS) + $(MAKE) /$(MAKEFLAGS) $(EDK_DEFAULTS)\ + /f $(BUILD_DIR)\UpdateMemoryRecord.mak all\ + NAME=UpdateMemoryRecord\ + "MY_INCLUDES=$(MemoryRecord_INCLUDES)"\ + GUID=24CCD374-3DF6-4181-86F6-E3C66920A145\ + ENTRY_POINT=SMIBiosUpdateMemoryRecordDriverEntryPoint\ + DEPEX1=$(UpdateMemroyRecord_DIR)\UpdateMemoryRecord.dxs \ + DEPEX1_TYPE=EFI_SECTION_DXE_DEPEX \ + TYPE=BS_DRIVER\ + COMPRESS=1\ diff --git a/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl new file mode 100644 index 0000000..8accc20 --- /dev/null +++ b/Chipset/NB/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl @@ -0,0 +1,69 @@ +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#************************************************************************* + +#************************************************************************* +# $Header: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl 1 2/08/12 4:37a Yurenlai $ +# +# $Revision: 1 $ +# +# $Date: 2/08/12 4:37a $ +#************************************************************************* +# Revision History +# ---------------- +# $Log: /Alaska/BIN/Chipset/Intel/NorthBridge/Haswell/Intel SystemAgent NB Chipset/SystemAgentWrap/UpdateMemoryRecord/UpdateMemoryRecord.sdl $ +# +# 1 2/08/12 4:37a Yurenlai +# Intel Haswell/NB eChipset initially releases. +# +#************************************************************************* +TOKEN + Name = "UpdateMemoryRecord_SUPPORT" + Value = "1" + Help = "Main switch to enable UpdateMemoryRecord support in Project" + TokenType = Boolean + TargetEQU = Yes + TargetMAK = Yes + Master = Yes + Token = "SMBIOS_MEMORY_SUPPORT" "=" "1" + Token = "SMBIOS_SUPPORT" "=" "1" +End + +PATH + Name = "UpdateMemroyRecord_DIR" +End + +MODULE + Help = "Includes UpdateMemoryRecord.mak to Project" + File = "UpdateMemoryRecord.mak" +End + +ELINK + Name = "$(BUILD_DIR)\UpdateMemoryRecord.ffs" + Parent = "FV_MAIN" + InvokeOrder = AfterParent +End + +#************************************************************************* +#************************************************************************* +#** ** +#** (C)Copyright 1985-2011, American Megatrends, Inc. ** +#** ** +#** All Rights Reserved. ** +#** ** +#** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 ** +#** ** +#** Phone: (770)-246-8600 ** +#** ** +#************************************************************************* +#*************************************************************************
\ No newline at end of file diff --git a/Chipset/NB/hsw_VBios.dat b/Chipset/NB/hsw_VBios.dat Binary files differnew file mode 100644 index 0000000..1e23bf1 --- /dev/null +++ b/Chipset/NB/hsw_VBios.dat |