diff options
| author | raywu <raywu@aaeon.com.tw> | 2018-09-14 08:31:46 +0800 |
|---|---|---|
| committer | raywu <raywu@aaeon.com.tw> | 2018-09-14 08:31:46 +0800 |
| commit | 86318e713d1a2ec5a8165a8964d570e4c5a90dd8 (patch) | |
| tree | c507aaba039b70236b53bd8bbff8c5709a7697ae /Chipset/SB/SBGeneric.c | |
| parent | 31bb486c913795c8b67d1c4dbaae2bdec4943fc9 (diff) | |
| download | zprj-86318e713d1a2ec5a8165a8964d570e4c5a90dd8.tar.xz | |
BIOS Custom Done
Diffstat (limited to 'Chipset/SB/SBGeneric.c')
| -rw-r--r-- | Chipset/SB/SBGeneric.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/Chipset/SB/SBGeneric.c b/Chipset/SB/SBGeneric.c index 097ce6f..7edb117 100644 --- a/Chipset/SB/SBGeneric.c +++ b/Chipset/SB/SBGeneric.c @@ -1561,9 +1561,18 @@ BOOLEAN SBIsDefaultConfigMode ( IN EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadVariablePpi ) { UINT8 Buffer8; + UINT8 CmosDiagnosticSts = FALSE; Buffer8 = READ_PCI8_SB(SB_REG_GEN_PMCON_3); // 0xA4 - return (Buffer8 & 4) ? TRUE : FALSE; +// return (Buffer8 & 4) ? TRUE : FALSE; + + IoWrite8(0x70, 0x0E); + CmosDiagnosticSts = IoRead8(0x71) & (BIT6 + BIT7); + + if( Buffer8 & 4 || CmosDiagnosticSts ) { + return TRUE; + } + return FALSE; } #if SB_STALL_PPI_SUPPORT |