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authorraywu <raywu0301@gmail.com>2018-06-15 00:00:50 +0800
committerraywu <raywu0301@gmail.com>2018-06-15 00:00:50 +0800
commitb7c51c9cf4864df6aabb99a1ae843becd577237c (patch)
treeeebe9b0d0ca03062955223097e57da84dd618b9a /Chipset/eM/Ahci
downloadzprj-b7c51c9cf4864df6aabb99a1ae843becd577237c.tar.xz
init. 1AQQW051HEADmaster
Diffstat (limited to 'Chipset/eM/Ahci')
-rw-r--r--Chipset/eM/Ahci/AHCI.EQU583
-rw-r--r--Chipset/eM/Ahci/AHCIACC.ASM1181
-rw-r--r--Chipset/eM/Ahci/AINT13.EQU748
-rw-r--r--Chipset/eM/Ahci/AInt13Csp.c111
-rw-r--r--Chipset/eM/Ahci/AhciAccess.c252
-rw-r--r--Chipset/eM/Ahci/AhciAccess.cif8
-rw-r--r--Chipset/eM/Ahci/AhciCsp.cif12
-rw-r--r--Chipset/eM/Ahci/HACCESS.EQU108
8 files changed, 3003 insertions, 0 deletions
diff --git a/Chipset/eM/Ahci/AHCI.EQU b/Chipset/eM/Ahci/AHCI.EQU
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+++ b/Chipset/eM/Ahci/AHCI.EQU
@@ -0,0 +1,583 @@
+; TITLE AHCI.EQU - Equates and structures
+;****************************************************************************
+;****************************************************************************
+;** **
+;** (C)Copyright 1985-2011, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone (770)-246-8600 **
+;** **
+;****************************************************************************
+;****************************************************************************
+
+;****************************************************************************
+; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCI.EQU 3 2/10/11 10:52a Rameshr $
+;
+; $Revision: 3 $
+;
+; $Date: 2/10/11 10:52a $
+;
+;****************************************************************************
+; Revision History
+; ----------------
+; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCI.EQU $
+;
+; 3 2/10/11 10:52a Rameshr
+; [TAG] EIP53704
+; [Category] Improvement
+; [Description] AMI headers update for Alaska Ahci Driver
+; [Files] AHCIACC.ASM
+; HACCESS.EQU
+; AHCI.EQU
+; AINT13.EQU
+; AInt13Csp.c
+;
+; 2 5/28/08 9:44a Rameshraju
+; Updated the AMI Address.
+;
+; 1 12/07/07 11:17a Olegi
+;
+; 6 1/29/07 1:25a Iminglin
+;
+; 5 11/09/06 3:55a Iminglin
+; Make code generic.
+;
+; 4 10/24/06 11:25p Iminglin
+; Stylization.
+;
+; 3 9/13/06 1:58a Iminglin
+; Issue Freeze Lock Command.
+;
+; 2 9/28/05 5:40a Iminglin
+; Update for CDROM.
+;
+; 1 6/09/05 11:29p Iminglin
+; Initialized version
+;
+; 1 5/20/05 2:37a Iminglin
+; Intel AHCI source
+;
+;****************************************************************************
+;
+;************************************************************************;
+;* *;
+;* Intel(r) Restricted Secret *;
+;* *;
+;* Support for and Booting from SATA devices in AHCI mode *;
+;* *;
+;* Enterprise Software Technology *;
+;* *;
+;* Copyright (c) 2003-2005 Intel Corporation *;
+;* *;
+;* Version iSrc03x *;
+;* *;
+;* This information is provided in connection with Intel products. *;
+;* No license, express or implied, by estoppel or otherwise, to *;
+;* any intellectual property rights is granted by this information *;
+;* or by the sale of Intel products. Except as provided in Intel's *;
+;* Terms and Conditions of Sale for such products, Intel assumes *;
+;* no liability whatsoever, and Intel disclaims any express or *;
+;* implied warranty, relating to sale and/or use of Intel products *;
+;* including liability or warranties relating to fitness for a *;
+;* particular purpose, merchantability, or infringement of any *;
+;* patent, copyright or other intellectual property right. Intel *;
+;* products are not intended for use in medical, life saving, or *;
+;* life sustaining applications. *;
+;* Intel retains the right to make changes to specifications and *;
+;* product descriptions at any time, without notice and may choose *;
+;* to develop product based on these designs. *;
+;* *;
+;* *Third-party brands and names are the property of their *;
+;* respective owners. *;
+;* *;
+;************************************************************************;
+;* *;
+;* REFERENCES *;
+;* *;
+;* Revision Title *;
+;* ==================================================================== *;
+;* 1.0 Serial ATA Advanced Host Controller Interface (AHCI) *;
+;* *;
+;************************************************************************;
+;
+;;;;;;;;;;;; Specification related equates and structures ;;;;;;;;;;;;;;;;
+;-------------------------------------------------------------------------
+; Maximum #of ports supported by each SATA controller
+;
+MAX_PORT_NUM equ 20h ; Max #of SATA Ports per SATA Controller
+;
+;-------------------------------------------------------------------------
+; SATA Controller Information Table
+; 1. Contains the AHCI related data for the device
+; 2. Built during POST
+; 3. Each device has its own table
+;
+INFO_CONTROLLER_STRUC struc
+ wBusDevFunc dw ? ; Bus#, Dev#, Func#
+ dHbaBaseAddr dd ? ; HBA Base Address
+ bIrq db ? ; IRQ used
+ dHbaCap dd ? ; HBA Capabilities (dCAP field)
+ dBitPortImp dd ? ; Bit-mapped info of port implemented (dPI field)
+INFO_CONTROLLER_STRUC ends
+;
+;-------------------------------------------------------------------------
+; Generic Host Control registers
+;
+GENERAL_HOST_OFFSET equ 0000h ; Offset of start of Generic Host Control Registers from AHCI Base
+;
+GENERAL_HOST_STRUC struc
+ dCAP dd ? ; HBA Capabilities (see below for details)
+ dGHC dd ? ; Global HBA Control (see below for details)
+ dIS dd ? ; Interrupt Status Register (see below for details)
+ dPI dd ? ; Ports Implemented (see below for details)
+ dVS dd ? ; AHCI Version (see below for details)
+GENERAL_HOST_STRUC ends
+;
+; Details of dCAP field
+;
+dCAP_NP_MASK equ 1Fh shl 0 ; Bit4-0 = max #of ports (0-based) supported
+dCAP_NCS_MASK equ 1Fh shl 8 ; Bit12-8 = #of command slots (0-based) supported
+dCAP_PSC equ 1 shl 13 ; Bit-13 = Partial State Capable
+dCAP_SSC equ 1 shl 14 ; Bit-14 = Slumber State Capable
+dCAP_PMD equ 1 shl 15 ; Bit-15 = PIO Multiple DRQ Block
+dCAP_SPM equ 1 shl 17 ; Bit-17 = Supports Port Multiplier
+dCAP_SAM equ 1 shl 18 ; Bit-18 = Supports AHCI Mode only
+dCAP_SNZO equ 1 shl 19 ; Bit-19 = Supports Non-Zero DMA offsets
+dCAP_ISS_MASK equ 0Fh shl 20; Bit23-20 = Interface Speed Support
+ ISS_1P5_GBPS equ 0001b ; 1.5 Gbps
+ ISS_1P5_3_GBPS equ 0010b ; 1.5 Gbps and 3 Gbps
+dCAP_SCLO equ 1 shl 24 ; Bit-24 = Supports Command List Override
+dCAP_SAL equ 1 shl 25 ; Bit-25 = Supports Activity LED
+dCAP_SALP equ 1 shl 26 ; Bit-26 = Supports Aggresive Link Power Management
+dCAP_SSS equ 1 shl 27 ; Bit-27 = Supports Staggered Spin-Up
+dCAP_SIS equ 1 shl 28 ; Bit-28 = Supports Interlock Switch
+dCAP_SNCQ equ 1 shl 30 ; Bit-30 = Supports Native Command Queuing
+dCAP_S64A equ 1 shl 31 ; Bit-31 = Supports 64-bit Addressing
+;
+; Details of dGHC field
+;
+dGHC_HR equ 1 shl 0 ; Bit-0 = HBA Reset
+dGHC_IE equ 1 shl 1 ; Bit-1 = Interrupt Enable
+dGHC_AE equ 1 shl 31 ; Bit-31 = AHCI Enable
+;
+; Details of dIS field
+; A particular bit, if set to 1, indicates that the corresponding port has an
+; interrupt pending. Only ports, that are implemented, have a corresponding
+; valid bit; all other bits are reserved.
+;
+; Details of dPI field
+; A particular bit, if set to 1, indicates that the corresponding port is
+; available for use. If set to 0, the corresponding port is not available.
+; The maximum number of bits that are set to 1, shall not exceed the value
+; of (dCap_NP_MASK + 1). At least one bit must be set to 1.
+;
+; Details of dVS field
+;
+dVS_MINOR equ 0FFFFh shl 0 ; Bit15-0 = Minor Version
+dVS_MAJOR equ 0FFFFh shl 16 ; Bit31-16 = Major Version
+;
+;-------------------------------------------------------------------------
+; Port registers
+;
+PORT_REGISTER_START equ 100h ; Port registers start at offset 100h from AHCI base
+PORT_REGISTER_SET_SIZE equ 80h ; Each port registers set is 128bytes
+PORT_REGISTER_SET_SIZE_N equ 07h ; #of bits to be shifted left
+;
+; Thus Port-N registers set starts at following offset from AHCI base
+; PORT_REGISTER_START + (N * 80h)
+; i.e. PORT_REGISTER_START + (N << 07h)
+;
+PORT_REG_STRUC struc
+ dPCLB dd ? ; Port Command List Base Address (lower 32bit)
+ dPCLBU dd ? ; Port Command List Base Address (upper 32bit)
+ dPFB dd ? ; Port FIS Base Address (lower 32bit)
+ dPFBU dd ? ; Port FIS Base Address (upper 32bit)
+ dPIS dd ? ; Port Interrupt Status (see below for details)
+ dPIE dd ? ; Port Interrupt Enable (see below for details)
+ dPCMD dd ? ; Port Command (see below for details)
+ dReserved dd ? ; Reserved
+ dPTFD dd ? ; Port Task File Data (see below for details)
+ dPSIG dd ? ; Port Signature (see below for details)
+ dPSSTS dd ? ; Port Serial ATA Status (see below for details)
+ dPSCTL dd ? ; Port Serial ATA Control (see below for details)
+ dPSERR dd ? ; Port Serial ATA Error (see below for details)
+ dPSACT dd ? ; Port Serial ATA Active
+ dPCI dd ? ; Port Command Issue
+PORT_REG_STRUC ends
+;
+; Details of dPIS field
+;
+dPIS_DHRS equ 1 shl 0 ; Bit-0 = Device to Host Register FIS Interrupt
+dPIS_PSS equ 1 shl 1 ; Bit-1 = PIO Setup FIS Interrupt
+dPIS_DSS equ 1 shl 2 ; Bit-2 = DMA Setup FIS Interrupt
+dPIS_SDBS equ 1 shl 3 ; Bit-3 = Set Device Bits Interrupt
+dPIS_UFS equ 1 shl 4 ; Bit-4 = Unknown FIS Interrupt
+dPIS_DPS equ 1 shl 5 ; Bit-5 = Descriptor Processed
+dPIS_PCS equ 1 shl 6 ; Bit-6 = Port Connect Change Status
+dPIS_DIS equ 1 shl 7 ; Bit-7 = Device Interlock Status
+ ; Bit21-8..Reserved
+dPIS_PRCS equ 1 shl 22; Bit-22 = PhyRdy Change Status
+dPIS_IPMS equ 1 shl 23; Bit-23 = Incorrect Port Multiplier Status
+dPIS_OFS equ 1 shl 24; Bit-24 = Overflow Status
+dPIS_INFS equ 1 shl 26; Bit-26 = Interface Non-Fatal Error Status
+dPIS_IFS equ 1 shl 27; Bit-27 = Interface Fatal Error Status
+dPIS_HBDS equ 1 shl 28; Bit-28 = Host Bus Data Error Status
+dPIS_HBFS equ 1 shl 29; Bit-29 = Host Bus Fatal Error Status
+dPIS_TFES equ 1 shl 30; Bit-30 = Task File Error Status
+dPIS_CPDS equ 1 shl 31; Bit-31 = Cold Port Detect Status
+;
+; Details of dPIE field
+;
+dPIE_DHRE equ 1 shl 0 ; Bit-0 = Device to Host Register FIS Interrupt Enable
+dPIE_PSE equ 1 shl 1 ; Bit-1 = PIO Setup FIS Interrupt Enable
+dPIE_DSE equ 1 shl 2 ; Bit-2 = DMA Setup FIS Interrupt Enable
+dPIE_SDBE equ 1 shl 3 ; Bit-3 = Set Device Bits Interrupt Enable
+dPIE_UFE equ 1 shl 4 ; Bit-4 = Unknown FIS Interrupt Enable
+dPIE_DPE equ 1 shl 5 ; Bit-5 = Descriptor Processed Interrupt Enable
+dPIE_PCE equ 1 shl 6 ; Bit-6 = Port Connect Change Interrupt Enable
+dPIE_DIE equ 1 shl 7 ; Bit-7 = Device Interlock Interrupt Enable
+ ; Bit21-8..Reserved
+dPIE_PRCE equ 1 shl 22; Bit-22 = PhyRdy Change Interrupt Enable
+dPIE_IPME equ 1 shl 23; Bit-23 = Incorrect Port Multiplier Interrupt Enable
+dPIE_OFE equ 1 shl 24; Bit-24 = Overflow Interrupt Enable
+dPIE_INFE equ 1 shl 26; Bit-26 = Interface Non-Fatal Error Interrupt Enable
+dPIE_IFE equ 1 shl 27; Bit-27 = Interface Fatal Error Interrupt Enable
+dPIE_HBDE equ 1 shl 28; Bit-28 = Host Bus Data Error Interrupt Enable
+dPIE_HBFE equ 1 shl 29; Bit-29 = Host Bus Fatal Error Interrupt Enable
+dPIE_TFEE equ 1 shl 30; Bit-30 = Task File Error Interrupt Enable
+dPIE_CPDE equ 1 shl 31; Bit-31 = Cold Port Detect Interrupt Enable
+;
+; Details of dPCMD field
+;
+dPCMD_ST equ 1 shl 0 ; Bit-0 = Start process command list
+ PxCMD_ST0_AND_MASK equ 0FFFFFFFEh; AND Mask to set PxCMD.ST = 0
+ PxCMD_ST0_OR_MASK equ 000000000h; OR Mask to set PxCMD.ST = 0
+dPCMD_SUD equ 1 shl 1 ; Bit-1 = Spin-Up Device
+dPCMD_POD equ 1 shl 2 ; Bit-2 = Power On Device
+dPCMD_CLO equ 1 shl 3 ; Bit-3 = Command List Override
+dPCMD_FRE equ 1 shl 4 ; Bit-4 = FIS Receive Enable
+; ; Bit7-5....Reserved
+dPCMD_CCS_MASK equ 1Fh shl 8 ; Bit12-8 = Current Command Slot
+dPCMD_ISS equ 1 shl 13; Bit-13 = Interlock Switch State
+dPCMD_FR equ 1 shl 14; Bit-14 = FIS Receive Running
+dPCMD_CR equ 1 shl 15; Bit-15 = Command List Running
+dPCMD_CPS equ 1 shl 16; Bit-16 = Cold Presence State
+dPCMD_PMA equ 1 shl 17; Bit-17 = Port Multiplier Attached
+dPCMD_HPCP equ 1 shl 18; Bit-18 = Hot Plug Capable Port
+dPCMD_ISP equ 1 shl 19; Bit-19 = Interlock Switch Attached to Port
+dPCMD_CPD equ 1 shl 20; Bit-20 = Cold Presence Detect
+ ; Bit23-21..Reserved
+dPCMD_ATAPI equ 1 shl 24; Bit-24 = Device is ATAPI
+dPCMD_DLAE equ 1 shl 25; Bit-25 = Drive LED on ATAPI Enable
+dPCMD_ALPE equ 1 shl 26; Bit-26 = Aggressive Link Power Management Enable
+dPCMD_ASP equ 1 shl 27; Bit-27 = Aggressive Slumber/Partial
+dPCMD_ICC_MASK equ 0Fh shl 28; Bit31-28= Interface Communication Control
+dPCMD_ICC_MASK_ALIGN equ 28 ; #of bits to be shifted for Interface Communication Control alignment
+ ICC_NOP_IDLE equ 00h ; HBA ready to accept new interface control command
+ ICC_ACTIVE equ 01h ; Active
+ ICC_PARTIAL equ 02h ; Partial
+ ICC_SLUMBER equ 06h ; Slumber State
+;
+;
+; Details of dPTFD field
+;
+dPTFD_STS_MASK equ 0FFh shl 0 ; Bit7-0 = Copy of Task File Status Register
+ dPTFD_STS_ERR equ 1 shl 0 ; Bit-0 = Error
+ ; Bit2-1...Not applicable
+ dPTFD_STS_DRQ equ 1 shl 3 ; Bit-3 = Data Xfer Requested
+ ; Bit5-4...Not applicable
+ dPTFD_STS_DRDY equ 1 shl 6 ; Bit-6 = Device is ready
+ dPTFD_STS_BSY equ 1 shl 7 ; Bit-7 = Interface is busy
+dPTFD_ERR_MASK equ 0FFh shl 8 ; Bit15-8= Copy of Task File Error Register
+;
+; Details of dPSIG field
+; Contains the signature received from the device on first D2H register FIS. It
+; is updated once after a reset sequence.
+; Bit7-0 = Sector Count Register
+; Bit15-8 = LBA Low Register
+; Bit23-16 = LBA Mid Register
+; Bit31-24 = LBA High Register
+;
+; Details of dPSSTS field
+;
+dPSSTS_DET_MASK equ 0Fh shl 0 ; Bit3-0 = Device Detection
+ dPSSTS_DET_DEVICE_MASK equ 01h ; Bit-0 = 1, Device Detected
+ DET_NO_DEVICE_AND_NO_PHY_COMM equ 00h ; No device detected and no Phy communication
+ DET_DEVICE_BUT_NO_PHY_COMM equ 01h ; Device detected but no Phy communication
+ DET_DEVICE_AND_PHY_COMM equ 03h ; Device detected and Phy communication
+ DET_PHY_OFF_LINE equ 04h ; Phy in offline mode
+dPSSTS_SPD_MASK equ 0Fh shl 4 ; Bit7-4 = Current Interface Speed
+ SPD_NO_DEVICE_OR_NO_COMM equ 00h ; No device present or no communication
+ SPD_GEN_1_COMM equ 01h ; Generation 1 communication rate
+ SPD_GEN_2_COMM equ 02h ; Generation 2 communication rate
+dPSSTS_IPM_MASK equ 0Fh shl 8 ; Bit11-8 = Current Interface State
+ IPM_NO_DEVICE_OR_NO_COMM equ 00h ; No device present or no communication
+ IPM_ACTIVE equ 03h ; Interface in Active state(v1.07)
+ IPM_PARTIAL equ 02h ; Interface in Partial power management state
+ IPM_SLUMBER equ 01h ; Interface in Slumber power management state(v1.07)
+;
+; Details of dPSCTL field
+;
+dPSCTL_DET_MASK equ 0Fh shl 0 ; Bit3-0 = Device Detection Initialization
+ DET_NO_DET_AND_NO_INIT equ 00h ; No detection or initialization requested
+ DET_COMM_INIT equ 01h ; Perform Interface communication initialization
+ DET_DISABLE_SATA equ 04h ; Disable SATA interface and put Phy in offline mode
+dPSCTL_SPD_MASK equ 0Fh shl 4 ; Bit7-4 = Speed Allowed
+ SPD_NO_RESTRICTION equ 00h ; No speed negotiation restriction
+ SPD_LIMIT_TO_GEN1 equ 01h ; Limit speed negotiation to Gen 1 rate
+ SPD_LIMIT_TO_GEN2 equ 02h ; Limit speed negotiation to a rate
+ ; not greater than Gen 2 rate
+dPSCTL_IPM_MASK equ 0Fh shl 8 ; Bit11-8 = Interface Power Management Transition Allowed
+dPSCTL_IPM_MASK_ALIGN equ 8 ; #of bits to be shifted for Interface Power Management Transition alignment
+ IPM_NO_RESTRICTION equ 00h ; No interface restriction
+ IPM_PARTIAL_DISABLED equ 01h ; Transition to Partial state disabled
+ IPM_SLUMBER_DISABLED equ 02h ; Transition to Slumber state disabled
+ IPM_PARTIAL_SLUMBER_DISABLED equ 03h ; Transition to both Partial and Slumber states disabled
+
+dPSCTL_SPM_MASK equ 0Fh shl 12; Bit15-12 = The Select Power Management
+dPSCTL_SPM_MASK_ALIGN equ 12 ; #of bits to be shifted for Select Power Management alignment
+ SPM_NO_TRANSITION equ 00h ; No power management state transition
+ SPM_PARTIAL_INITIATED equ 01h ; Transition to Partial state initiated
+ SPM_SLUMBER_INITIATED equ 02h ; Transition to Slumber state initiated
+ SPM_ACTIVE_INITIATED equ 04h ; Transition to the active power management states initiated
+
+dPSCTL_PMP_MASK equ 0Fh shl 16; Bit19-16 = The Port Multiplier field
+dPSCTL_PMP_MASK_ALIGN equ 16 ; #of bits to be shifted for Port Multiplier alignment
+ PMP_CONTROL_PORT equ 0Fh ; Control port # of Port Multiplier
+;
+; Details of dPSERR field
+;
+dPSERR_ERR_MASK equ 0FFFFh shl 0; Bit15-0= Error
+ dPSERR_ERR_I equ 1 shl 0 ; Bit-0 = Recovered Data Integrity Error
+ dPSERR_ERR_M equ 1 shl 1 ; Bit-1 = Recovered Communications Error
+ ; Bit7-2.......Reserved
+ dPSERR_ERR_T equ 1 shl 8 ; Bit-8 = Transient Data Integrity Error
+ dPSERR_ERR_C equ 1 shl 9 ; Bit-9 = Persistent Communication or Data Integrity Error
+ dPSERR_ERR_P equ 1 shl 10; Bit-10 = Protocol Error
+ dPSERR_ERR_E equ 1 shl 11; Bit-11 = Master or Target Abort
+ ; Bit15-12.....Reserved
+dPSERR_DIAG_MASK equ 0FFFFh shl 16; Bit31-16 = Diagnostics
+ dPSERR_DIAG_N equ 1 shl 16; Bit-16 = PhyRdy Change
+ dPSERR_DIAG_I equ 1 shl 17; Bit-17 = Phy Internal Error
+ dPSERR_DIAG_W equ 1 shl 18; Bit-18 = Comm Wake
+ dPSERR_DIAG_B equ 1 shl 19; Bit-19 = 10B to 8B Decode Error
+ dPSERR_DIAG_D equ 1 shl 20; Bit-20 = Disparity Error
+ dPSERR_DIAG_C equ 1 shl 21; Bit-21 = CRC Error
+ dPSERR_DIAG_H equ 1 shl 22; Bit-22 = Handshake Error
+ dPSERR_DIAG_S equ 1 shl 23; Bit-23 = Link Sequence Error
+ dPSERR_DIAG_T equ 1 shl 24; Bit-24 = Transport State Transition Error
+ dPSERR_DIAG_F equ 1 shl 25; Bit-25 = Unknown FIS Type
+ dPSERR_DIAG_X equ 1 shl 26; Bit-26 = Exchanged
+ ; Bit31-27.....Reserved
+;
+;-------------------------------------------------------------------------
+;
+; Command List Structure
+;
+COMMAND_LIST_STRUC struc
+ dDW0 dd ? ; Description Information (details below)
+ dPRDBC dd ? ; Physical Region Descriptor Byte Count
+ dCTBA dd ? ; Command Table Base Address (lower 32bit)
+ dCTBAU dd ? ; Command Table Base Address (upper 32bit)
+ dReserved1 dd ? ; Reserved dword
+ dReserved2 dd ? ; Reserved dword
+ dReserved3 dd ? ; Reserved dword
+ dReserved4 dd ? ; Reserved dword
+COMMAND_LIST_STRUC ends
+;
+; Details of dDW0 field
+;
+dDW0_CFL_MASK equ 1Fh shl 0 ; Bit4-0 = Command FIS Length (1-based) in #of DWords
+dDW0_ATAPI equ 1 shl 5 ; Bit-5 = ATAPI
+dDW0_WRITE equ 1 shl 6 ; Bit-6 = Direction of data transfer
+ ; 0 = Device Read (data from device to host)
+ ; 1 = Device Write (data from host to device)
+dDW0_PREFETCHABLE equ 1 shl 7 ; Bit-7 = Prefetchable
+dDW0_RESET equ 1 shl 8 ; Bit-8 = Device Reset
+dDW0_BIST equ 1 shl 9 ; Bit-9 = BIST
+dDW0_CLEAR_BSY equ 1 shl 10; Bit-10 = Clear Busy after xmitting FIS and receiving R_OK
+ ; Bit-11....Reserved
+dDW0_PMP_MASK equ 0Fh shl 12; Bit15-12= Port multiplier number to be used
+
+dDW0_PRDTL_N equ 16 ; Bit-16 = Start bit of PRDTL
+dDW0_PRDTL_MASK equ 0FFFFh shl 16;Bit31-16= Physical Region Descriptor Table Length
+ ; in #of entries, each entry is 4 DWords
+;-------------------------------------------------------------------------
+; Command Table
+;
+COMMAND_TABLE_STRUC struc
+ aCFIS db 40h dup (?) ; Area for command FIS
+ aACMD db 10h dup (?) ; Area for ATAPI command
+ aReserved db 30h dup (?) ; Reserbed area
+ aPRDT db ? ; Start of Physical Region Descriptor Tables
+COMMAND_TABLE_STRUC ends
+;
+;-------------------------------------------------------------------------
+; PRDT: Physical Region Descriptor Table
+;
+PRDT_STRUC struc
+ dDBA dd ? ; Data Base Address (lower 32bit)
+ dDBAU dd ? ; Data Base Address (upper 32bit)
+ dReserved dd ? ; Reserved
+ dDW3 dd ? ; Description Information (details below)
+PRDT_STRUC ends
+;
+; Details of dDW3 field
+;
+dDW3_DBC_MASK equ 3FFFFFh shl 0; Bit21-0 = Data Byte Count (0-based)
+ ; Bit30-22...Reserved
+dDW3_INTERRUPT equ 1 shl 31; Bit-31 = Generate interrupt when data is xferred
+;
+;-------------------------------------------------------------------------
+; FIS: Frame Information Structure
+;
+; FIS Types and size in #of dwords
+H2D_REGISTER_FIS_TYPE equ 27h
+ H2D_REGISTER_FIS_LENGTH_DWORD equ 05h
+D2H_REGISTER_FIS_TYPE equ 34h
+ D2H_REGISTER_FIS_LENGTH_DWORD equ 05h
+DMA_SETUP_FIS_TYPE equ 41h
+ DMA_SETUP_FIS_LENGTH_DWORD equ 07h
+BIST_ACTIVATE_FIS_TYPE equ 58h
+ BIST_ACTIVATE_FIS_LENGTH_DWORD equ 03h
+PIO_SETUP_FIS_TYPE equ 5Fh
+ PIO_SETUP_FIS_LENGTH_DWORD equ 05h
+SET_DEVICE_BITS_FIS_TYPE equ 0A1h
+ SET_DEVICE_BITS_FIS_LENGTH_DWORD equ 02h
+ACMD_FIELD_LENGTH_DWORD equ 03h ;(V1.07+)
+;
+H2D_REGISTER_FIS_STRUC struc
+ bFisType db ? ; FIS Type
+ bXferReason db ? ; Cause of transfer
+ COMMAND_REGISTER_UPDATE equ 80h; Bit-7 = 1, xfer is due to an update of command register
+ ; Bit6-0=....Reserved
+ bCommand db ? ; Command
+ bFeatures db ? ; Features
+ bSectorNumber db ? ; Sector Number
+ bCylinderLow db ? ; Cylinder Low
+ bCylinderHigh db ? ; Cylinder High
+ bDeviceHead db ? ; Device Head
+ bSectorNumberExp db ? ; Sector Number Exp
+ bCylinderLowExp db ? ; Cylinder Low Exp
+ bCylinderHighExp db ? ; Cylinder High Exp
+ bFeaturesExp db ? ; Features Exp
+ bSectorCount db ? ; Sector Count
+ bSectorCountExp db ? ; Sector Count Exp
+ bReserved1 db ? ; Reserved
+ bControl db ? ; Control
+ bReserved2 db ? ; Reserved
+ bReserved3 db ? ; Reserved
+ bReserved4 db ? ; Reserved
+ bReserved5 db ? ; Reserved
+H2D_REGISTER_FIS_STRUC ends
+;
+D2H_REGISTER_FIS_STRUC struc
+ bFisType db ? ; FIS Type
+ bDeviceInterruptLine db ? ; Interrupt line of device
+ INTERRUPT_BIT equ 40h ; Bit-6 = it reflects interrupt bit line of the device
+ bStatus db ? ; Status
+ bError db ? ; Error
+ bSectorNumber db ? ; Sector Number
+ bCylinderLow db ? ; Cylinder Low
+ bCylinderHigh db ? ; Cylinder High
+ bDeviceHead db ? ; Device Head
+ bSectorNumberExp db ? ; Sector Number Exp
+ bCylinderLowExp db ? ; Cylinder Low Exp
+ bCylinderHighExp db ? ; Cylinder High Exp
+ bReserved1 db ? ; Features Exp
+ bSectorCount db ? ; Sector Count
+ bSectorCountExp db ? ; Sector Count Exp
+ bReserved2 db ? ; Reserved
+ bReserved3 db ? ; Control
+ bReserved4 db ? ; Reserved
+ bReserved5 db ? ; Reserved
+ bReserved6 db ? ; Reserved
+ bReserved7 db ? ; Reserved
+D2H_REGISTER_FIS_STRUC ends
+;
+DMA_SETUP_FIS_STRUC struc
+ bFisType db ? ; FIS Type
+ bXferDirnAndInt db ? ; Xfer direction and interrupt
+ XFER_D2H equ 20h ; Bit-5 = 1, D2H xfer
+ XFER_H2D equ 00h ; 0, H2D xfer
+ INTERRUPT_PENDING equ 40h ; Bit-6 = interrupt pending
+ bReserved1 db ? ; Reserved
+ bReserved2 db ? ; Reserved
+ dDmaBufferIdentifierLow dd ? ; DMA Buffer Identifier Low
+ dDmaBufferIdentifierHigh dd ? ; DMA Buffer Identifier High
+ dReserved3 dd ? ; Reserved
+ dDmaBufferOffset dd ? ; DMA Buffer offset
+ dDmaXferCount dd ? ; DMA Transfer Count in bytes
+ dReserved4 dd ? ; Reserved
+DMA_SETUP_FIS_STRUC ends
+;
+BIST_ACTIVATE_FIS_STRUC struc
+ bFisType db ? ; FIS Type
+ bReserved1 db ? ; Reserved
+ bPattern db ? ; Pattern Definition
+ bReserved2 db ? ; Reserved
+ dData1 dd ? ; Data1
+ dData2 dd ? ; Data2
+BIST_ACTIVATE_FIS_STRUC ends
+;
+PIO_SETUP_FIS_STRUC struc
+ bFisType db ? ; FIS Type
+ bXferDirnAndInt db ? ; Xfer direction and interrupt
+ ; (bit defintions same as DMA_SETUP_FIS)
+ bStatus db ? ; Status
+ bError db ? ; Error
+ bSectorNumber db ? ; Sector Number
+ bCylinderLow db ? ; Cylinder Low
+ bCylinderHigh db ? ; Cylinder High
+ bDeviceHead db ? ; Device Head
+ bSectorNumberExp db ? ; Sector Number Exp
+ bCylinderLowExp db ? ; Cylinder Low Exp
+ bCylinderHighExp db ? ; Cylinder High Exp
+ bReserved1 db ? ; Reserved
+ bSectorCount db ? ; Sector Count
+ bSectorCountExp db ? ; Sector Count Exp
+ bReserved2 db ? ; Reserved
+ bE_Status db ? ; Status
+ wXferCount dw ? ; Xfer count in bytes
+ wReserved dw ? ; Reserved
+PIO_SETUP_FIS_STRUC ends
+;
+SET_DEVICE_BITS_FIS_STRUC struc
+ bFisType db ? ; FIS Type
+ bFlags db ? ; Information flags
+ bStatus db ? ; Status
+ bError db ? ; Error
+ dReserved dd ? ; Reserved
+SET_DEVICE_BITS_FIS_STRUC ends
+;
+; Receive FIS structure
+FIS_RECEIVE_STRUC struc
+ aDSFIS DMA_SETUP_FIS_STRUC {?} ; DMA Setup FIS
+ bReserved1 db 04h dup (?) ; Reserved
+ aPSFIS PIO_SETUP_FIS_STRUC {?} ; PIO Setup FIS
+ bReserved2 db 0Ch dup (?) ; Reserved
+ aRFIS D2H_REGISTER_FIS_STRUC {?} ; D2H Register FIS
+ bReserved3 db 04h dup (?) ; Reserved
+ aSDBFIS SET_DEVICE_BITS_FIS_STRUC {?} ; Set Device Bits FIS
+ aUFIS db 40h dup (?) ; Unknown FIS
+ bReserved4 db 60h dup (?) ; Reserved
+FIS_RECEIVE_STRUC ends
+;
+;-------------------------------------------------------------------------
+;****************************************************************************
+;****************************************************************************
+;** **
+;** (C)Copyright 1985-2011, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone (770)-246-8600 **
+;** **
+;****************************************************************************
+;****************************************************************************
+
diff --git a/Chipset/eM/Ahci/AHCIACC.ASM b/Chipset/eM/Ahci/AHCIACC.ASM
new file mode 100644
index 0000000..1f93536
--- /dev/null
+++ b/Chipset/eM/Ahci/AHCIACC.ASM
@@ -0,0 +1,1181 @@
+
+ TITLE AHCIACC.ASM - AHCI Register/Memory Acccess Routines
+
+;****************************************************************************
+;****************************************************************************
+;** **
+;** (C)Copyright 1985-2014, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone (770)-246-8600 **
+;** **
+;****************************************************************************
+;****************************************************************************
+
+;****************************************************************************
+; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCIACC.ASM 14 12/08/14 5:58a Anbuprakashp $
+;
+; $Revision: 14 $
+;
+; $Date: 12/08/14 5:58a $
+;****************************************************************************
+; Revision History
+; ----------------
+; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AHCIACC.ASM $
+;
+; 14 12/08/14 5:58a Anbuprakashp
+; [TAG] EIP192297
+; [Category] Improvement
+; [Description] Replacing SmmGetMemoryType usage in AHCI driver with
+; AmiBufferValidationLib
+; [Files] AhciInt13Smm.c, AhciInt13Smm.mak, AHCIACC.ASM
+;
+; 13 11/24/14 11:54p Kapilporwal
+; [TAG] EIP191939
+; [Category] Improvement
+; [Description] Issue about BIG_REAL_MODE_MMIO_ACCESS of AHCI module
+; [Files] AI13.bin
+; AHCIACC.ASM
+; AhciInt13Dxe.c
+; AhciInt13Dxe.dxs
+; AhciInt13Smm.c
+; AhciInt13Smm.cif
+; AhciInt13Smm.dxs
+; AhciInt13Smm.h
+; AhciInt13Smm.mak
+; AhciInt13Smm.sdl
+; AInt13.c
+; Aint13.cif
+; AInt13.h
+; AhciSmm.c
+; AhciSmm.h
+; AhciSmmProtocol.h
+;
+; 12 7/01/14 2:23a Nagadineshk
+; [TAG] EIP172162
+; [Category] Bug Fix
+; [Severity] Important
+; [Symptom] Can't install legacy windows if achiacc.obj is not first
+; one of CSM_OEM16_OBJS elink
+; [RootCause] Wrong offset of Newly Hooked Interrupt(CPU Exception
+; Interrupt) address loaded in Interrupt vector table.
+; [Solution] Stored Correct Offset value in IVT
+; [Files] AHCIACC.ASM
+;
+; 11 6/20/14 6:54a Nimishsv
+; Recheck-in
+;
+; 10 12/17/13 7:06a Nimishsv
+; [TAG] EIP131322
+; [Category] Improvement
+; [Description] Improve S4 resume time with PCIE SSD
+; under Win7, reported that if enable AHCIMMIOSMM_SUPPORT,
+; and then S4 resume time is very long(about 50s) with win 7.
+; (Add support for accessing MMIO region using BIG real mode)
+; [Files] AhciMmioSmm.sdl, AHCIACC.asm
+;
+; 9 8/02/12 8:14a Deepthins
+; [TAG] EIP93480
+; [Category] Bug Fix
+; [Symptom] AHCI legacy support module is corrupting the memory.
+; [RootCause] AHCI legacy support module is corrupting the memory as it
+; was using wrong offset for storing the base address.
+; [Solution] Properly calculating offset for storing the base address.
+; [Files] AINT13.EQU, AInt13.c, AInt13.h and AHCIACC.ASM
+;
+; 8 1/13/12 12:20a Deepthins
+; [TAG] EIP78099
+; [Category] Improvement
+; [Description] Handle multiple AHCI controller in legacy.
+; [Files] Aint13.sdl , AInt13.c , AInt13.h , AHCIACC.ASM , AHCI.EQU ,
+; AINT13.bin (AHCIACC.ASM , AINT13.EQU)
+;
+; 7 2/10/11 10:52a Rameshr
+; [TAG] EIP53704
+; [Category] Improvement
+; [Description] AMI headers update for Alaska Ahci Driver
+; [Files] AHCIACC.ASM
+; HACCESS.EQU
+; AHCI.EQU
+; AINT13.EQU
+; AInt13Csp.c
+;
+; 6 6/21/10 5:34a Rameshr
+; AHCI Legacy booting through MMIO reg.
+; EIP 38444
+;
+; 5 5/28/08 9:43a Rameshraju
+; Updated the AMI Address.
+;
+; 4 3/28/08 10:03a Olegi
+;
+; 3 3/27/08 5:33p Olegi
+;
+; 2 19/12/07 4:28p Anandakrishnanl
+; Modified the relative offsets to be absolute.
+;
+; 1 12/07/07 11:17a Olegi
+;
+;****************************************************************************
+
+;----------------------------------------------------------------------------
+; INCLUDE FILES
+;----------------------------------------------------------------------------
+ include ahci.equ
+ include haccess.equ
+ include aint13.equ
+ include token.equ
+
+ FLAT_MODE_INDEX equ 08h
+ REAL_MODE_INDEX equ 10h
+;----------------------------------------------------------------------------
+; EXTERNS USED
+;----------------------------------------------------------------------------
+.586p
+OEM16_CSEG SEGMENT PARA PUBLIC 'CODE' USE16
+ ASSUME cs:OEM16_CSEG, ds:OEM16_CSEG
+;-------------------------------------------------------------------------
+ PUBLIC AhciApiModuleStart
+AhciApiModuleStart LABEL BYTE
+ jmp SHORT AhciCsm16Api
+ dw AhciDataStart - AhciApiModuleStart
+
+
+;----------------------------------------------------------------------------
+; IMPORTANT: Do not put any OEM/CHIPSET code above this, the above code and
+; and data are at fixed locations.
+;----------------------------------------------------------------------------
+
+;-------------------------------------------------------------------------
+; AHCI_CSM16_API_Start
+;----------------------------------------------------------------------------
+; This routine is implementation of the CSM16 API #7.
+; Input: CX 80h - ReadRegisterDword call
+; 00h - WriteRegisterDword call
+; 01h - WaitForFisRecRun call
+; For read/write functions:
+; SS:SP+3Eh (originally ESI) HBA Base Address
+; SS:SP+42h (originally EBX) Port#, Register Offset
+; Bit31-16 = Port# (0-based)
+; FFFF for Generic Host Control Register
+; Bit15-0 = Register offset
+; SS:SP+46h (originally EAX) Data to be written
+; For WaitForFisRecRun function:
+; No input
+; Output: NC Successful
+; EAX Data read
+; CY Error
+; Register Usage: Do not destroy any register except EAX
+;
+;----------------------------------------------------------------------------
+;
+AhciCsm16Api PROC FAR PUBLIC
+; Adjust current IP so that the data offsets are valid
+ call $+3 ; Push curent IP
+ pop bx ; Get current IP in BX
+ shr bx, 4
+ mov ax, cs ; Always x000h
+ add ax, bx ; New CS
+ push ax
+ push newOffset-AhciApiModuleStart
+ retf ; Execute from new CS:IP
+
+newOffset:
+ push bp
+ mov bp, sp
+ mov eax, ss:[bp+48h] ; Data to be written (ignored for Read function)
+ mov ebx, ss:[bp+44h] ; Port#
+ mov esi, ss:[bp+40h] ; HBA Base Address
+
+ cmp cx, 0
+ jz aca_WriteCall
+ cmp cx, 80h
+ jnz aca_WaitForFisRecRun
+ call ReadRegisterDword
+ jmp SHORT aca_Exit
+aca_WaitForFisRecRun:
+ call WaitForFisRecRun
+ jmp SHORT aca_Exit
+aca_WriteCall:
+ call WriteRegisterDword
+
+aca_Exit:
+ pop bp
+
+; Adjust sp as if we returned to csm16_func_ret
+ add sp, 4 ; cs:ip of F000:csm16_func_ret
+
+; Save EAX, restore it after popad
+ push eax
+ pop ds
+ pop gs
+;csm16_func_ret:
+ popad
+ push gs
+ push ds
+ pop eax
+
+ pop gs
+ pop fs
+ pop es
+ pop ds
+
+;csm16_exit:
+ popf
+ pop ds
+ pop si
+
+ add sp, 2 ; Do not "pop ax", preserving return code
+
+; Prepare for FAR return - fetch the CS and patch the segment for RETF
+ mov cx, WORD PTR ss:[bp+1ah]
+ mov WORD PTR ss:[bp+06h], cx
+; Restore CX
+ mov cx, WORD PTR ss:[bp+18h]
+ mov dx, WORD PTR ss:[bp+16h] ;Restore Dx
+
+ pop bp
+ add sp, 4
+ clc
+ retf 18
+
+AhciCsm16Api ENDP
+
+;
+;-------------------------------------------------------------------------
+; ReadRegisterDword
+;----------------------------------------------------------------------------
+; This routine reads the register.
+; Input: ESI HBA Base Address
+; EBX Port#, Register Offset
+; Bit31-16 = Port# (0-based)
+; FFFF for Generic Host Control Register
+; Bit15-0 = Register offset
+; Output: NC Successful
+; EAX Data read
+; CY Error
+; Register Usage: Do not destroy any register except EAX
+;
+;----------------------------------------------------------------------------
+;
+ReadRegisterDword_FAR PROC FAR PUBLIC
+ call ReadRegisterDword ; EAX = data read if read
+ ret
+ReadRegisterDword_FAR ENDP
+
+ReadRegisterDword PROC NEAR PUBLIC
+ push esi
+ call CalculateRegisterOffset ; ESI = register offset from base
+
+ push dx ; Dx has the controller number
+ cli
+ push bx ; Save bx value in stack
+ push ax ; Save ax value in stack
+ mov ax, 0
+ mov al, dl ; Move the controller no into al
+ mov bl, 8
+ mul bl ; Multiply it with 8 as AHCI_ACCESS\
+ ; structure size is 8
+ mov bx, ax ; Move the offset into bx
+ pop ax ; Restore ax
+IF (MKF_AHCI_INT13_SMM_SUPPORT)
+ push ebx
+ push ecx
+ mov ebx, dword ptr cs:[AhciDataStart - AhciApiModuleStart +4+bx] ;ebx=Data
+ add esi,ebx
+IF (MKF_BIG_REAL_MODE_MMIO_ACCESS)
+ call ReadDWORD
+ELSE
+ mov cx,1 ;Read Function
+ call AhciGenerateSwSMI
+ cmp ecx, 0 ; if ECX == 0, MMIO read is Success
+ jz Read_Success
+ stc
+ jmp Read_Return
+Read_Success:
+ clc
+Read_Return:
+ENDIF
+ pop ecx
+ pop ebx
+ jmp Read_done
+ENDIF
+ mov dx, cs:[AhciDataStart - AhciApiModuleStart +bx] ; DX = Index Port
+ push eax
+ mov eax, esi ; EAX = register address
+ out dx, eax ; Write Address
+ pop eax
+
+ mov dx, cs:[AhciDataStart - AhciApiModuleStart +2+bx] ; DX = Data Port
+ in eax, dx ; EAX = adat
+
+ clc ; NC, Successful
+Read_done:
+ pop bx
+ pop dx
+
+ pop esi
+ ret
+ReadRegisterDword ENDP
+;
+;----------------------------------------------------------------------------
+; WriteRegisterDword
+;----------------------------------------------------------------------------
+; This routine writes the register.
+; Input: ESI HBA Base Address
+; EBX Port#, Register Offset
+; Bit31-16 = Port# (0-based)
+; FFFF for Generic Host Control Register
+; Bit15-0 = Register offset
+; EAX Data to be written
+; Output: NC Successful
+; CY Error
+; Register Usage: Do not destroy any register
+;
+;----------------------------------------------------------------------------
+;
+WriteRegisterDword_FAR PROC FAR PUBLIC
+ call WriteRegisterDword
+ ret
+WriteRegisterDword_FAR ENDP
+
+WriteRegisterDword PROC NEAR PUBLIC
+ push esi
+ call CalculateRegisterOffset ; ESI = register offset from base
+
+ push dx ; Dx has the controller number
+ cli
+ push bx ; Save bx value in stack
+ push ax ; Save ax value in stack
+ mov ax, 0
+ mov al, dl ; Move the controller no into al
+ mov bl, 8
+ mul bl ; Multiply it with 8 as AHCI_ACCESS\
+ ; structure size is 8
+ mov bx, ax ; Move the offset into bx
+ pop ax ; Restore ax
+
+IF (MKF_AHCI_INT13_SMM_SUPPORT)
+ push ebx
+ push ecx
+ mov ebx, dword ptr cs:[AhciDataStart - AhciApiModuleStart +4+bx]
+ add esi,ebx
+IF (MKF_BIG_REAL_MODE_MMIO_ACCESS)
+ call WriteDWORD
+ELSE
+ mov ebx,eax ;Write Value
+ mov cx,2 ;Write Function
+ call AhciGenerateSwSMI
+ cmp ecx, 0 ; if ECX == 0, MMIO write is Success
+ jz Write_Success
+ stc
+ jmp Write_Return
+Write_Success:
+ clc
+Write_Return:
+ENDIF
+ pop ecx
+ pop ebx
+ jmp Write_done
+ENDIF
+ mov dx, cs:[AhciDataStart - AhciApiModuleStart +bx] ; DX = Index Port
+ push eax
+ mov eax, esi ; EAX = register address
+ out dx, eax ; Write Address
+ pop eax
+
+ mov dx, cs:[AhciDataStart - AhciApiModuleStart +2+bx] ; DX = Data Port
+ out dx, eax ; Write dword data
+ clc ; NC, Successful
+Write_done:
+ pop bx
+ pop dx
+
+ pop esi
+ ret
+WriteRegisterDword ENDP
+;
+;----------------------------------------------------------------------------
+; CalculateRegisterOffset
+;----------------------------------------------------------------------------
+; This routine calculates the register offset from HBA Base.
+; Input: EBX Port#, Register Offset within Port
+; Bit31-16 = Port# (0-based)
+; FFFF for Generic Host Control Register
+; Bit15-0 = Register offset
+; Output: ESI Register Offset from HBA Base
+; Register Usage: Do not destroy any register except ESI
+;
+;----------------------------------------------------------------------------
+;
+CalculateRegisterOffset PROC NEAR PRIVATE
+ push cx
+ push ebx
+ mov cx, bx ; CX = register offset
+ shr ebx, 16 ; BX = Port# (0-based)
+ inc bx ; Port# valid?
+ jz short cro_00 ; No
+ dec bx ; BX = Port# (0-based)
+ shl bx, PORT_REGISTER_SET_SIZE_N
+ add bx, PORT_REGISTER_START
+cro_00:
+ add bx, cx ; BX = Port register offset from HBA base address
+ movzx esi, bx ; ESI = Port register offset from HBA base address
+ pop ebx
+ pop cx
+ ret
+CalculateRegisterOffset ENDP
+
+;
+;----------------------------------------------------------------------------
+; WaitForFisRecRun
+;----------------------------------------------------------------------------
+; This routine executes HBA wait for FIS rec run code. If not
+; implemented (just ret), AHCI INT13 code will execute the default routine.
+; Implement this routine for different OEM/Chipset vendor and return 0 in AL
+; to override the default routine execution.
+;
+; Output: AH 0 if implemented
+;
+;----------------------------------------------------------------------------
+;
+WaitForFisRecRun PROC NEAR PUBLIC
+ ret
+WaitForFisRecRun ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: AhciGenerateSwSMI
+;
+; Description: Generate the Sw SMI to read the MMIO space.
+; if the system is in big real mode, read/write the MMIO space without
+; SwSMI
+;
+; Input: Cx = 1 - Read MMIO
+; Cx= 2 - Write MMIO
+; Eax= Value to write in MMIO for write MMIO
+;
+; Output: Eax- for Read MMIO
+;
+; Modified: Ds
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+IF (MKF_AHCI_INT13_SMM_SUPPORT)
+AhciGenerateSwSMI PROC NEAR PUBLIC
+ call Check_Big_Real_mode
+ jc NotBigReadMode
+ push es
+ push 0
+ pop es
+
+ cmp cx,1
+ je ReadMmio
+ mov dword ptr es:[esi],eax ;Write MMIO
+ pop es
+ ret
+ReadMmio:
+ mov eax,dword ptr es:[esi] ;Read MMIO
+ pop es
+ ret
+NotBigReadMode:
+
+ mov dx,MKF_SW_SMI_IO_ADDRESS
+ mov al,MKF_AHCI_INT13_SMM_SWSMI_VALUE
+ out dx,al ;Generate Sw SMI to Read/Write MMIO
+ jmp $+2
+ ret
+AhciGenerateSwSMI ENDP
+
+;-------------------------------------------------------------------------
+; ReadDWORD
+;-------------------------------------------------------------------------
+; This routine reads DWORD from MMIO.
+; Input: ESI HBA Base Address
+;
+; Output: NC Successful
+; EAX Data read
+; CY Error
+; Register Usage: Do not destroy any register except EAX
+;
+;-------------------------------------------------------------------------
+ReadDWORD PROC NEAR PUBLIC
+
+ push ds
+
+ push 0
+ pop ds
+
+ push esi
+
+; Save original values of registers in stack
+ push ebx
+ push es
+ push di
+
+; Save a dword from 5000h
+ mov bx, 5000h
+ mov es, bx
+ mov di, 00h
+ mov ebx, dword ptr es:[di]
+
+ push ebx
+
+ mov byte ptr es:[di], 00h
+; Switching to Big Real Mode
+ call Switch_Big_Real_Mode
+
+; Reading DWORD from Hba_base_address and store in EAX
+ mov eax, dword ptr ds:[esi]
+
+ push eax
+ movzx eax, byte ptr es:[di]
+ and eax, 01h
+ jz rdw_done
+; Switch back from Big Real mode
+ call Switch_Original_Mode
+
+rdw_done:
+ pop eax
+
+ push eax
+ movzx eax, byte ptr es:[di]
+ and eax, 10b
+ jz org_g20
+ call DisblGateA20
+org_g20:
+ pop eax
+
+ pop ebx
+; Restore the original values stored in stack
+ mov dword ptr es:[di], ebx
+
+ pop di
+ pop es
+ pop ebx
+
+ pop esi
+
+ pop ds
+ clc
+
+ ret
+ReadDWORD ENDP
+
+;-------------------------------------------------------------------------
+; WriteDWORD
+;-------------------------------------------------------------------------
+; This routine writes DWORD in MMIO space.
+; Input: EAX Data to be written
+;
+; Output: ESI HBA Base Address
+; NC Successful
+; CY Error
+;
+; Register Usage: Do not destroy any register except EAX
+;
+;-------------------------------------------------------------------------
+WriteDWORD PROC NEAR PUBLIC
+ push ds
+
+ push 0
+ pop ds
+
+ push esi
+
+; Save original values of registers in stack
+ push ebx
+ push es
+ push di
+
+; Save a dword from 5000h
+ mov bx, 5000h
+ mov es, bx
+ mov di, 00h
+ mov ebx, dword ptr es:[di]
+
+ push ebx
+
+ mov byte ptr es:[di], 00h
+; Switching to Big Real Mode
+ call Switch_Big_Real_Mode
+
+; Writing DWORD stored in EAX into Hba_base_address
+ mov dword ptr ds:[esi],eax
+
+ push eax
+ movzx eax, byte ptr es:[di]
+ and eax, 01h
+ jz wdw_done
+
+; Switch back from Big Real mode
+ call Switch_Original_Mode
+
+wdw_done:
+ pop eax
+
+ push eax
+ movzx eax, byte ptr es:[di]
+ and eax, 10b
+ jz org_g201
+ call DisblGateA20
+org_g201:
+ pop eax
+ pop ebx
+
+; Restore the original values stored in stack
+ mov dword ptr es:[di], ebx
+
+ pop di
+ pop es
+ pop ebx
+
+ pop esi
+
+ pop ds
+ clc
+
+ ret
+WriteDWORD ENDP
+
+;----------------------------------------------------------------------------
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: Switch_Big_Real_Mode
+;
+; Description: Switch to Big real Mode.
+;
+; Input: None
+;
+; Output:
+;
+; Modified: DS, ES
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+;----------------------------------------------------------------------------
+Switch_Big_Real_Mode PROC NEAR PUBLIC
+
+ push di
+ call Check_Big_Real_mode
+ jnc InBigRealMode
+ mov byte ptr es:[di], 01h
+
+InBigRealMode:
+
+ mov di, FLAT_MODE_INDEX ;Index for flat mode
+ call GotoProtectedMode
+
+ pop di
+ ret
+
+Switch_Big_Real_Mode ENDP
+
+;----------------------------------------------------------------------------
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: Switch_Original_Mode
+;
+; Description: Switch to Original Mode.
+;
+; Input: None
+;
+; Output:
+;
+; Modified: DS, ES
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+;----------------------------------------------------------------------------
+Switch_Original_Mode PROC NEAR PUBLIC
+
+ push di
+ mov di, REAL_MODE_INDEX ;Real mode index
+ call GotoProtectedMode
+ pop di
+
+ ret
+
+Switch_Original_Mode ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: GotoProtectedMode
+;
+; Description: This function jumps to protected mode for 4GB limit access
+;
+; Input: None
+;
+; Output: None
+;
+; Modified: None
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+GotoProtectedMode PROC NEAR PUBLIC
+ push es
+ pusha
+ cli ; Disable interrupts.
+; Check the GA20 status..
+; Compare 256bytes at 0:0 with FFFF:10
+; If match, GA20 is disabled else GA20 is enabled.
+ push di
+ push es
+ push ds
+ push 0000h
+ pop ds ; DS = 0000.
+ push 0FFFFh
+ pop es ; ES = FFFF.
+ mov cx, 100h / 4 ; Number of Dwords in 256bytes.
+ xor si, si
+ mov di, 0010h
+ repz cmpsd
+ pop ds
+ pop es
+ pop di ;Descriptor table index in di
+
+ pushf ; Save GA20 status
+ ; ZR/NZ = disabled/enabled.
+ jnz short gtbrm_00 ; GA20 is already enabled.
+
+ push di
+ mov di, 00h
+ or byte ptr es:[di], 10b
+ pop di
+ call EnblGateA20 ; Enable GateA20.
+
+gtbrm_00:
+ call go_big_mode ; Go to protected mode and comeback
+ ; to real mode.
+ popf ; ZR/NZ = GA20 status.
+ stc ; Routine went to big real mode.
+
+gtbrm_01:
+ popa
+ pop es
+ ret ; Return to caller.
+GotoProtectedMode ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: EnblGateA20
+;
+; Description: This function enables GateA20
+;
+; Input: None
+;
+; Output: None
+;
+; Modified: None
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+EnblGateA20 PROC NEAR PUBLIC
+
+ push ax
+ mov al,02h
+ out 92h, al
+
+; Check the GA20 status..
+; Compare 256bytes at 0:0 with FFFF:10
+; If match, GA20 is disabled else GA20 is enabled.
+ push di
+ push es
+ push ds
+ push 0000h
+ pop ds ; DS = 0000.
+ push 0FFFFh
+ pop es ; ES = FFFF.
+ mov cx, 100h / 4 ; Number of Dwords in 256bytes.
+ xor si, si
+ mov di, 0010h
+ repz cmpsd
+ pop ds
+ pop es
+ pop di ;Descriptor table index in di
+
+ jnz eg20_end
+
+ mov al, 0DFh ; Data for output port to enable A20.
+ out 60h, al
+ mov al, 0D1h
+ out 64h, al
+
+eg20_end:
+ pop ax
+
+ ret
+EnblGateA20 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: go_big_mode
+;
+; Description: This routine goes to protected mode, sets the DS, ES to the
+; given selector, comes back to real mode and sets DS, ES to 0000.
+;
+; Input: DX - Selector.
+;
+; Output: Selector 00 can be used to access 4GB.
+;
+; Modified: EAX.
+;
+; Referrals: big_gdt.
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+go_big_mode PROC NEAR PRIVATE
+
+ jmp Executable_code
+
+;<AMI_SHDR_START>
+;----------------------------------------------------------------------------
+; Name: big_gdt
+;
+; Type: BYTE Array
+;
+; Description: Global Descriptor Table to switch the system to/from FLAT Mode.
+; Since these routines will be called from non-shadowed system
+; ROM, the GDT must be on a QWORD boundary or else the bytes
+; will get CORRUPTED!
+;
+;----------------------------------------------------------------------------
+;<AMI_SHDR_END>
+
+ALIGN 8
+big_gdt LABEL WORD
+ db 8 dup (0) ;00 - Null descriptor
+ db 0FFh,0FFh,000h,000h,000h,093h,08Fh,000h ; 08h - DS descriptor for flat mode
+big_gdt_end LABEL WORD
+
+big_gdt_real LABEL WORD
+ db 8 dup (0) ;00 - Null descriptor
+ db 0FFh,0FFh,000h,000h,000h,093h,000h,000h ; 08h - DS descriptor for real mode
+big_gdt_real_end LABEL WORD
+
+GDT_DESC LABEL BYTE
+ dw 010h ; Length of GDT
+ db 00,00h ; ptr to GDT
+ db 05h,00h
+GDT_DESC_END LABEL BYTE
+
+Executable_code:
+
+ push ds
+ push es
+ push eax
+ push ebx
+ push ecx
+ push edx
+ push si
+ push di
+
+; Changed for CSM - need to save SS, reload SS Limit to 64K selector and restore it
+ push bp
+ mov bp, ss
+
+ mov al, 8Dh ; Disable NMI
+ out 70h, al
+
+;;; Copy contents from 5000:00(16 bytes) into registers
+ mov ax, 5000h
+ mov es, ax
+ mov si, 00h
+ mov eax, dword ptr es:[si]
+ add si, 4
+ mov ebx, dword ptr es:[si]
+ add si, 4
+ mov ecx, dword ptr es:[si]
+ add si, 4
+ mov edx, dword ptr es:[si]
+ push eax
+ push ebx
+ push ecx
+ push edx
+
+;;; Copy GDT to 5000h:00h
+ mov ax, cs
+ mov ds, ax
+ cmp di, 08h
+ jne gbm_real
+ mov si, offset cs:big_gdt
+ jmp gbm_flat
+gbm_real:
+ mov si, offset cs:big_gdt_real
+gbm_flat:
+ mov ax, 5000h
+ mov es, ax
+ mov di, 00h
+ xor cx, cx
+ mov cx, 08h
+ rep movsw
+
+ lgdt fword ptr cs:GDT_DESC
+ mov eax, cr0
+ or al, 01h
+ mov cr0, eax ; In protected mode.
+ jmp gbm_00 ; Flush instruction queue - JMP (NEAR)
+ ; to next instruction.
+
+gbm_00:
+ mov ax, 08h ; Selector
+ mov ds, ax ; DS = selector.
+ mov es, ax ; ES = selector.
+
+ mov eax, cr0 ; Come back into real mode with DS,ES
+ and al, 0FEh
+ mov cr0, eax
+ jmp gbm_01 ; Flush instruction queue - JMP (NEAR)
+ ; to next instruction.
+gbm_01:
+
+ xor ax, ax
+ mov ds, ax
+ mov es, ax
+
+ pop edx
+ pop ecx
+ pop ebx
+;;; Restore contents of 5000:00h(16 bytes) from registers
+ mov ax, 5000h
+ mov es, ax
+ mov si, 00h
+ pop eax
+ mov dword ptr es:[si], eax
+ add si, 4
+ mov dword ptr es:[si], ebx
+ add si, 4
+ mov dword ptr es:[si], ecx
+ add si, 4
+ mov dword ptr es:[si], edx
+
+ pop bp
+ pop di
+ pop si
+ pop edx
+ pop ecx
+ pop ebx
+ pop eax
+ pop es
+ pop ds
+ ret
+go_big_mode ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: DisblGateA20
+;
+; Description: This function disables GateA20
+;
+; Input: None
+;
+; Output: None
+;
+; Modified: None
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+
+DisblGateA20 PROC NEAR PUBLIC
+
+ push ax
+ mov al,00h
+ out 92h, al
+
+; Check the GA20 status..
+; Compare 256bytes at 0:0 with FFFF:10
+; If match, GA20 is disabled else GA20 is enabled.
+ push di
+ push es
+ push ds
+ push 0000h
+ pop ds ; DS = 0000.
+ push 0FFFFh
+ pop es ; ES = FFFF.
+ mov cx, 100h / 4 ; Number of Dwords in 256bytes.
+ xor si, si
+ mov di, 0010h
+ repz cmpsd
+ pop ds
+ pop es
+ pop di ;Descriptor table index in di
+
+ jz dg20_end
+
+ mov al, 0DDh ; Data for output port to disables A20.
+ out 60h, al
+ mov al, 0D1h
+ out 64h, al
+
+dg20_end:
+ pop ax
+
+ ret
+
+DisblGateA20 ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: Get_EBDA
+;
+; Description: Get the EBDA Segment Address
+;
+; Input: None
+;
+; Output: DS: Ebda Segment
+;
+; Modified: Ds
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+Get_EBDA PROC NEAR PUBLIC
+
+ push 40h
+ pop ds
+ mov ds, ds:[0Eh] ; DS - EBDA segment.
+ ret
+
+get_EBDA ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: Int0DHandler
+;
+; Description: Exception 0D handler
+;
+; Input: None
+;
+; Output: Exception_flag Set
+;
+; Modified: None
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+Int0DHandler PROC NEAR PUBLIC
+ push ds
+ call Get_EBDA
+ mov byte ptr ds:[102h],1 ;Set the Flag in Ebda:102
+ pop ds
+ pop ax
+ add ax, 5 ; Go to Next instruction that doesn't
+ ; cause Exception
+ push ax
+ iret
+Int0DHandler ENDP
+
+;<AMI_PHDR_START>
+;----------------------------------------------------------------------------
+;
+; Procedure: Check_Big_Real_mode
+;
+; Description: This function checks wheather system is in Big real mode
+;
+; Input: None
+;
+; Output: Carry Set - Not in Big Real mode
+; Carry Not Set- System is in Big Real mode
+;
+; Modified: None
+;
+;----------------------------------------------------------------------------
+;<AMI_PHDR_END>
+Check_Big_Real_mode PROC NEAR PUBLIC
+ push eax
+ push edi
+ push ebx
+ push es
+ push ds
+ pushf
+ cli
+
+ call Get_EBDA
+
+ mov byte ptr ds:[102h],0 ;EBDA:102
+
+ push 0
+ pop es
+
+ mov eax, dword ptr es:[0Dh*4]
+ push eax
+
+ push cs ; Runtime segment
+ push offset cs:Int0DHandler-AhciApiModuleStart
+ pop eax
+ mov dword ptr es:[0Dh*4], eax
+
+
+ mov edi,0100000h
+ mov eax,dword ptr es:[edi]
+ cmp byte ptr ds:[102h],1 ;Check the exception
+ je Real_mode
+
+ mov edi,0
+ mov ebx,dword ptr es:[edi]
+ cmp eax,ebx
+ je Real_mode
+
+ ;Read ,Write test for above 1Mb area
+ mov edi,0100000h
+ mov ebx,dword ptr es:[edi]
+ mov eax,055AA55AAh
+ mov dword ptr es:[edi],eax
+ mov eax,dword ptr es:[edi]
+ mov dword ptr es:[edi],ebx
+ cmp eax,055AA55AAh
+ jne Real_mode
+ pop eax
+ mov dword ptr es:[0Dh*4], eax
+ popf
+ clc ;System is in Big Real Mode
+ jmp Exit_Ret
+
+Real_mode:
+ pop eax
+ mov dword ptr es:[0Dh*4], eax
+ popf
+ stc ;System is in Real Mode
+Exit_Ret:
+ pop ds
+ pop es
+ pop ebx
+ pop edi
+ pop eax
+ ret
+Check_Big_Real_mode ENDP
+
+ENDIF
+
+AhciDataStart label word
+AhciAccess AHCI_ACCESS (MKF_AHCI_CONTROLLER_COUNT) dup (<>)
+
+OEM16_CSEG ENDS
+
+END
+;****************************************************************************
+;****************************************************************************
+;** **
+;** (C)Copyright 1985-2014, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone (770)-246-8600 **
+;** **
+;****************************************************************************
+;****************************************************************************
diff --git a/Chipset/eM/Ahci/AINT13.EQU b/Chipset/eM/Ahci/AINT13.EQU
new file mode 100644
index 0000000..f51aaf8
--- /dev/null
+++ b/Chipset/eM/Ahci/AINT13.EQU
@@ -0,0 +1,748 @@
+; TITLE aint13.equ - Equates and structures for AHCI INT13
+;****************************************************************************
+;****************************************************************************
+;** **
+;** (C)Copyright 1985-2011, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone (770)-246-8600 **
+;** **
+;****************************************************************************
+;****************************************************************************
+
+;****************************************************************************
+; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AINT13.EQU 5 8/02/12 8:17a Deepthins $
+;
+; $Revision: 5 $
+;
+; $Date: 8/02/12 8:17a $
+;
+;****************************************************************************
+; Revision History
+; ----------------
+; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AINT13.EQU $
+;
+; 5 8/02/12 8:17a Deepthins
+; [TAG] EIP93480
+; [Category] Bug Fix
+; [Severity] Normal
+; [Symptom] AHCI legacy support module is corrupting the memory.
+; [RootCause] AHCI legacy support module is corrupting the memory as it
+; was using wrong offset for storing the base address.
+; [Solution] Properly calculating offset for storing the base address.
+; [Files] AINT13.EQU, AInt13.c, AInt13.h and AHCIACC.ASM
+;
+; 4 1/13/12 12:21a Deepthins
+; [TAG] EIP78099
+; [Category] Improvement
+; [Description] Handle multiple AHCI controller in legacy.
+; [Files] Aint13.sdl , AInt13.c , AInt13.h , AHCIACC.ASM , AHCI.EQU ,
+; AINT13.bin (AHCIACC.ASM , AINT13.EQU)
+;
+; 3 2/10/11 10:52a Rameshr
+; [TAG] EIP53704
+; [Category] Improvement
+; [Description] AMI headers update for Alaska Ahci Driver
+; [Files] AHCIACC.ASM
+; HACCESS.EQU
+; AHCI.EQU
+; AINT13.EQU
+; AInt13Csp.c
+;
+; 2 5/28/08 9:44a Rameshraju
+; Updated the AMI Address.
+;
+; 1 12/07/07 11:17a Olegi
+;
+; 7 9/20/07 1:41a Davidhsieh
+;
+; 6 9/11/07 6:54a Chung
+; 1. Add Security Function.
+; 2. Modify AHCI Code.
+;
+; 5 6/06/07 2:06a Chung
+; Add AHCI HD Mode Information
+;
+; 4 5/03/07 4:02a Chung
+; EIP9321 - Add SMART function for self test.
+;
+; 2 1/29/07 1:25a Iminglin
+;
+; 1 1/25/07 1:21a Iminglin
+; Changed by James.
+;
+; 15 12/20/06 2:26a Iminglin
+; 1. Prepare Port Multiplier support.
+; 2. Display SMART status.
+;
+; 14 12/05/06 3:15a Iminglin
+; Remove useless equates.
+;
+; 13 11/09/06 3:47a Iminglin
+; Make code generic.
+;
+; 12 10/27/06 4:28a Iminglin
+; Rename Int13 function 48 structure.
+;
+; 11 10/24/06 11:25p Iminglin
+; Stylization.
+;
+; 10 9/13/06 1:58a Iminglin
+; Issue Freeze Lock Command.
+;
+; 9 7/14/06 4:28a Iminglin
+; Clearificatoin.
+;
+; 8 6/01/06 11:25p Iminglin
+; Enable SMART function.
+;
+; 7 5/19/06 2:09a Iminglin
+; Intel source v1.00 change.
+;
+; 6 3/27/06 12:49a Iminglin
+; Change Device Path length.
+;
+; 5 11/10/05 10:32p Iminglin
+; Add smart handle.
+;
+; 4 10/25/05 2:25a Iminglin
+; Remove CD structure.
+;
+; 3 10/20/05 4:35a Iminglin
+; Give a solution for byte alignment.
+;
+; 2 10/05/05 6:57a Iminglin
+; CDROM data structure
+;
+; 1 6/09/05 11:29p Iminglin
+; Initialized version
+;
+; 1 5/20/05 2:37a Iminglin
+; Intel AHCI source
+;
+;****************************************************************************
+;
+;************************************************************************;
+;* *;
+;* Intel(r) Restricted Secret *;
+;* *;
+;* Support for and Booting from SATA devices in AHCI mode *;
+;* *;
+;* Enterprise Software Technology *;
+;* *;
+;* Copyright (c) 2003-2005 Intel Corporation *;
+;* *;
+;* Version iSrc03x *;
+;* *;
+;* This information is provided in connection with Intel products. *;
+;* No license, express or implied, by estoppel or otherwise, to *;
+;* any intellectual property rights is granted by this information *;
+;* or by the sale of Intel products. Except as provided in Intel's *;
+;* Terms and Conditions of Sale for such products, Intel assumes *;
+;* no liability whatsoever, and Intel disclaims any express or *;
+;* implied warranty, relating to sale and/or use of Intel products *;
+;* including liability or warranties relating to fitness for a *;
+;* particular purpose, merchantability, or infringement of any *;
+;* patent, copyright or other intellectual property right. Intel *;
+;* products are not intended for use in medical, life saving, or *;
+;* life sustaining applications. *;
+;* Intel retains the right to make changes to specifications and *;
+;* product descriptions at any time, without notice and may choose *;
+;* to develop product based on these designs. *;
+;* *;
+;* *Third-party brands and names are the property of their *;
+;* respective owners. *;
+;* *;
+;************************************************************************;
+;* *;
+;* REFERENCES *;
+;* *;
+;* Revision Title *;
+;* ==================================================================== *;
+;* 1.0 Serial ATA Advanced Host Controller Interface (AHCI) *;
+;* *;
+;************************************************************************;
+;
+;-------------------------------------------------------------------------
+; IMPLEMENTATION RELATED EQUATES AND STRUCTURES
+;-------------------------------------------------------------------------
+; SATA Device Information Table
+; 1. Contains the AHCI related data for the device
+; 2. Built during POST
+; 3. Each device has its own table
+DEV_INFO_STRUC STRUC
+ bDetectType db ? ;Detected Device Type (Details Below)
+ bInstalledType db ? ;Device Installed Type (See Below)
+ wStatus dw ? ;Bit-mapped device Init Status (Details Below)
+ bInt13Num db ? ;Device# for INT13 (8xh)
+ bPMNum db ? ;Port Multipier Port #
+ bPortNum db ? ;SATA Port# (0-Based) where device is present
+ wBusDevFunc dw ? ;Bus#, Dev#, Func# of Controller
+ bControllerNo db ? ;Ahci Controller number
+ dHbaBase dd ? ;HBA Base Address of Generic Host Control Registers
+ dHbaCap dd ? ;HBA Capabilities
+ dPortBase dd ? ;Base Address of SATA port where device is present
+ bSelector db ? ;Device selector value
+ bIrq db ? ;IRQ used by this device
+ bInfoFlag db ? ;Information Flag (details below)
+ bSectorSizeN db ? ;N value of Sector size 2^N
+ ;For 512bytes sector, N = 9
+ wSmartInfo dw ? ;SMART info (details below)
+ qTotalSectors dq ? ;Total #of sectors in device (1-based)
+ wXferCount dw ? ;Device transfer count. Used for ATAPI packer size
+ bBlockInfo db ?
+ b32BitInfo db ?
+ bUDMAInfo db ?
+ bPIOInfo db ?
+DEV_INFO_STRUC ENDS
+
+; Details of bDetectType
+DETECT_NO EQU 00h ;Not detected
+DETECT_ATA EQU 01h ;device detected is ATA
+DETECT_ATAPI_CD EQU 02h ;device detected is ATAPI CDROM
+DETECT_ATAPI_ARMD EQU 03h ;device detected is ATAPI ARMD
+
+; Details of bInstalledType
+INSTALLED_NO EQU 00h ;Not installed
+INSTALLED_HDD EQU 01h ;device installed as ATA HDD
+INSTALLED_CDROM EQU 02h ;device installed as ATAPI CDROM
+INSTALLED_ARMD_FDD EQU 03h ;device installed as ATAPI ARMD FDD
+INSTALLED_ARMD_HDD EQU 04h ;device installed as ATAPI ARMD HDD
+
+; Details of wStatus
+ST_SUCCESS EQU 0001h ;Bit 0 = 1, successful (device is installed in this case)
+ST_ID_DEV_ERR EQU 0002h ;Bit 1 = 1, Identify Device Failed
+ST_DEV_GEOMETRY_ERR EQU 0004h ;Bit 2 = 1, Invalid Device Geometry
+ST_INIT_DEV_PARAM_ERR EQU 0008h ;Bit 3 = 1, Init device parameter failed
+ST_RECALI_ERR EQU 0010h ;Bit 4 = 1, Recalibrate failed
+ST_SMART_ERR EQU 0020h ;Bit 5 = 1, SMART failed
+ST_VERIFY_ERR EQU 0040h ;Bit 6 = 1, Verify failed
+ST_FREEZE_LOCK_ERR EQU 0080h ;Bit 7 = 1, Security Freeze Lock failed
+ST_PORT_RESET_ERR EQU 0100h ;Bit 8 = 1, Port Reset failed
+ST_SMART_EVENT EQU 0200h ;Bit 9 = 1, SMART Event was found
+ST_RAID_SUPPORT_ERR EQU 0400h ;Bit 10 = 1, Device will be supported by RIAD OROM, not AHCI OROM (ex. HDD)
+ ;Bit 14-11, Reserved for future use
+ST_NOT_SUPPORT_ERR EQU 8000h ;Bit 15 = 1, Device not supported
+
+; Details of bInfoFlag, a bit-mapped field
+INFO_REMOVABLE EQU 01h ;Bit 0 = 1, Device supports removable media
+INFO_LBA_48 EQU 02h ;Bit 1 = 1, 48bit LBA enabled
+INFO_IRQ EQU 04h ;Bit 2 = 1, Device uses IRQ
+ ; 0, Device uses DRQ
+ ;Bit 6-2, Reserved
+INFO_ATAPI EQU 80h ;Bit 7 = 1, ATAPI Device
+ ; 0, ATA Device
+
+; Details wSmartInfo
+AHCI_SMART_SUPPORT EQU 1 shl 0 ;Bit 0 = 0/1, SMART (Not Supported/Supported)
+AHCI_SMART_ENABLE EQU 1 shl 1 ;Bit 1 = 0/1, SMART (Disabled/Enabled)
+AHCI_SMART_EN EQU 1 shl 1 ;Bit 1 = 0/1, SMART (Disabled/Enabled)
+AHCI_SMART_STATUS EQU 1 shl 2 ;Bit 2 = 0/1, Device Status Good/Bad
+AHCI_SMART_COMMAND_STATUS EQU 1 shl 7 ;Bit 7 = 0/1, SMART Execution Successful/Error
+ ;Bit 15-8, Reserved
+
+; Details qTotalSectors
+; This contains the total #of sectors (1-based) in the device.
+
+;-------------------------------------------------------------------------
+; Table containing the pointers to different tables
+; 1. Initialized during POST
+DEV_PTR_STRUC struc
+ bInt13Num db ? ; INT13 Drive# for this Port
+ bPMnum db ? ; Port Multipier port #
+ bPortNum db ? ; Port# (0-based) on Controller
+ dParamTablePtr dd ? ; Ptr to device parameter table
+ dInfoTablePtr dd ? ; Ptr to device info table
+DEV_PTR_STRUC ends
+
+;-------------------------------------------------------------------------
+ ;(amiahcix-)>
+;;;;; INIT_DEV_FUNC_STRUC: Used in INIT_DEVICE_TABLE while initializing device.
+;;;;INIT_DEV_FUNC_STRUC struc
+;;;; wFunction dw ? ; Routine to be executed
+;;;; wStatus dw ? ; Bit-mapped status if error
+;;;; bAttrib db ? ; Attribute (details below)
+;;;;INIT_DEV_FUNC_STRUC ends
+;;;;
+;;;;; Details of bAttribute field
+;;;;ATTRIB_ERROR equ 01h ;Bit-0 = 0/1, Non-Fatal/Fatal Error
+;;;;; ;Bit7-1.....Reserved for future use
+ ;<(amiahcix-)
+;-------------------------------------------------------------------------
+; Device parameter table: Same to hdparam.equ
+DEV_PARAM_STRUC struc
+ wMAXCYL dw ? ; maximum no. of cylinders..INT13 interface. (logical)
+ bMAXHN db ? ; maximum no. of heads..INT13 interface. (logical)
+ bLBASIG db ? ; LBA signature
+ bLBASPT db ? ; #of sectors per track drive is configured for. (physical)
+ wWPCYL dw ? ; start write precomp cyl no.
+ bReserved db ? ; reserved
+ bCBYTE db ? ; bit 3 for more than 8 heads
+ wLBACYL dw ? ; #of cylinders drive is configured for. (physical)
+ bLBAHD db ? ; #of heads drive is configured for. (physical)
+ wLANDZ dw ? ; Landing zone
+ bMAXSN db ? ; no. of sectors per track..INT13 interface. (logical)
+ bLBACHK db ? ; checksum..LBA
+DEV_PARAM_STRUC ends
+
+; Details of bSignature field: A signature Axh indicates that the table is translated.
+DPTBL_SIG_MASK equ 0F0h
+lba_signature equ 0A0h ;A0h signature indicating LBA translation
+
+;-------------------------------------------------------------------------
+; Return codes from INT13
+R_SUCCESS EQU 00h ;No error (i.e. Successful)
+R_INVALID EQU 01h ;Invalid function request
+R_MARK_NOT_FOUND EQU 02h ;Address mark not found
+R_WRITE_PROTECT_ERR EQU 03h ;Write protect error
+R_SECTOR_NOT_FOUND EQU 04h ;Sector not found
+R_RESET_FAIL EQU 05h ;Reset failed
+R_MEDIA_CHANGED EQU 06h ;Media changed
+R_DRV_PARAM_ACT_FAIL EQU 07h ;Drive parameter activity failed
+R_DMA_OVERRUN EQU 08h ;DMA overrun on operation
+R_DATA_BOUNDARY_ERR EQU 09h ;Data boundary error
+R_BAD_SECTOR EQU 0Ah ;Bad sector flag detected
+R_BAD_CYL EQU 0Bh ;Bad cylinder detected
+R_INVALID_NUM_OF_SECTOR EQU 0Dh ;Invalid #of sectors on format
+R_CTRL_DATA_ADDR_MARK EQU 0Eh ;Control data address mark detected
+R_DMA_ARBIT_LEVEL EQU 0Fh ;DMA arbitration level out of range
+R_UNCORRECTABLE_ERR EQU 10h ;Uncorrectable ECC/CRC error
+R_CORRECTED_DATA_ERR EQU 11h ;ECC corrected data error
+R_GENERAL_CTRLER_FAIL EQU 20h ;General controller failure
+R_SEEK_FAIL EQU 40h ;Seek operation failed
+R_TIME_OUT EQU 80h ;Time out
+R_DRV_NOT_READY EQU 0AAh ;Drive not ready
+R_UNDEFINED_ERR EQU 0BBh ;Undefined error occurred
+R_WRITE_FAULT EQU 0CCh ;Write fault on selected drive
+R_STATUS_ERR EQU 0E0h ;Error Register = 0
+R_SENSE_FAIL EQU 0FFh ;Sense Operation failed
+
+;----------------------------------------------------------------------------
+; Timeout for different operations
+SEC_TIMES EQU 00h ;Count for 1sec using refresh signal
+MAX_TIMES EQU 05h ;Max time out in seconds
+
+;----------------------------------------------------------------------------
+IDENTIFY_BUFFER_LENGTH EQU 200h ;512 bytes for Identify device command
+SECTOR_LENGTH EQU 200h ;512 bytes sector size
+SECTOR_LENGTH_N EQU 9 ;2^n bytes sector size
+SELECTOR_NON_LBA EQU 0A0h ;Master without LBA
+SELECTOR_LBA EQU 0E0h ;Master with LBA
+MAX_STND_XFER_SECTOR EQU 080h ;#of sectors that can be xferred in stnd INT13 func
+MAX_EXTD_XFER_SECTOR EQU 07Fh ;#of sectors that can be xferred in extd INT13 func
+BLOCK_SIZE EQU 800h ;#of bytes of each transefer from CDROM
+BLOCK_SIZE_N EQU 00Bh ;N, block size 2^N
+
+;-------------------------------------------------------------------------
+; Different data area relevant to Hard Disk in BIOS DATA SEGMENT (0040h)
+;WINCH_STATUS EQU 74h ;40:74h = DB..Last operation status
+;WINCH_NUMBER EQU 75h ;40:75h = DB..#of HDD installed by BIOS
+;WINCH_STAT_REG EQU 8Ch ;40:8Ch = DB..Content of status register
+;WINCH_ERROR_REG EQU 8Dh ;40:8Dh = DB..Content of error register
+;WINCH_INT_FLAG EQU 8Eh ;40:8Eh = DB..Used for interrupt occurrence
+
+;-------------------------------------------------------------------------
+; ATA/ATAPI commands
+DEVICE_DIAG_CMD EQU 090h ;Execute device diagnostics command
+IDENTIFY_DEVICE_COMMAND EQU 0ECh
+ATAPI_IDENTIFY_DEV_CMD EQU 0A1h ;ATAPI identify device command
+ATAPI_SIGNATURE EQU 0EB14h ;ATAPI Signature
+MULTIPLIER_SIGNATURE EQU 9669h ;Port Multiplier Signature
+ATA_SIGNATURE EQU 0000h ;ATA Signature
+IDLE_IMMEDIATE EQU 0E2h ;IDLE IMMEDIATE Non-data
+
+READ_DMA_CMD EQU 0C8h ;Read DMA command
+READ_DMA_EXT_CMD EQU 025h ;Read DMA Ext command
+READ_MULTIPLE_CMD EQU 0C4h ;Read Multiple command
+READ_MULTIPLE_EXT_CMD EQU 029h ;Read Multiple Ext command
+READ_SECTORS_CMD EQU 020h ;Read Sector(s) command
+READ_EXT_CMD EQU 024h ;Read Sector(s) Ext command
+
+WRITE_DMA_CMD EQU 0CAh ;Write DMA command
+WRITE_DMA_EXT_CMD EQU 035h ;Write DMA Ext command
+WRITE_MULTIPLE_CMD EQU 0C5h ;Write Multiple command
+WRITE_MULTIPLE_EXT_CMD EQU 039h ;Write Multiple Ext command
+WRITE_SECTORS_CMD EQU 030h ;Write Sector(s) command
+WRITE_EXT_CMD EQU 034h ;Write Sector(s) Ext command
+
+READ_VERIFY_CMD EQU 040h ;Verify Sector(s) command
+EXTD_READ_VERIFY_CMD EQU 042h ;Verify Sector(s) Ext command
+
+SET_MULTIPLE_CMD EQU 0C6h ;Set multiple mode command
+
+ATAPI_RESET_COMMAND EQU 008h ;ATAPI reset command
+
+SMART_COMMAND EQU 0B0h ;SMART Enable Operations command
+ SMART_READ_DATA EQU 0D0h
+ SMART_ATTRIBUTE_AUTOSAVE EQU 0D2h
+ SMART_SAVE_ATTRIBUTE_VALUES EQU 0D3h
+ SMART_EXECUTE_OFFLINE_IMMEDIATE EQU 0D4h
+ SMART_READ_LOG EQU 0D5h
+ SMART_WRITE_LOG EQU 0D6h
+; SMART_ENABLE EQU 0D8h
+ SMART_DISABLE EQU 0D9h
+ SMART_RETURN_STATUS EQU 0DAh
+;AHCI_HDS -->
+SECURITY_SET_CMD equ 0F1h
+SECURITY_UNLOCK_CMD equ 0F2h
+SECURITY_DISABLE_CMD equ 0F6h
+;AHCI_HDS <--
+
+SECURITY_FREEZE_LOCK EQU 0F5h
+
+ATAPI_SOFT_PACKET_CMD EQU 0A0h ;ATAPI command packet value
+; Available Packet commands
+ATAPI_READ_10_CMD EQU 028h ;ATAPI read command packet value
+ATAPI_REQUEST_SENSE_CMD EQU 03h ;ATAPI Request sense
+ATAPI_NOP_CMD EQU 00h ;ATAPI Request sense
+; Size of "Request Sense Packet" buffer
+ATAPI_REQ_SENSE_DATA_SIZE EQU 18 ;ATAPI controller request sense data
+
+;-------------------------------------------------------------------------
+; Input packet structure used in Extended INT13 functions
+DISK_ADDRESS_PACKET_STRUC struc
+ bSize db ? ; Packet size in bytes
+ bReserved1 db ? ; Reserved (set to 0)
+ bBlockCount db ? ; #of blocks to be transferred
+ bReserved2 db ? ; Reserved (set to 0)
+ dPtrXferBuffer dd ? ; Segment:Offset of transfer buffer
+ qLBA dq ? ; Selected LBA
+DISK_ADDRESS_PACKET_STRUC ends
+
+DISK_ADDRESS_PACKET_SIZE equ size DISK_ADDRESS_PACKET_STRUC
+
+; Details of bSize
+; It contains size of the packet in bytes including this field. The size is
+; 16bytes. If size is less than 16bytes, the function should return error
+; with AH = 01h, and CF = 1. If packet size is greater than 16bytes, the
+; function ignores the additional information and executes.
+;
+; Details of bXferCount
+; On input, it contains #of sectors to be transferred. On output, it returns
+; #of sectors actually transferred. If the input value is 0, the function
+; returns successful without any data being transferred.
+;
+; Details dPtrXferBuffer
+; It contains address of the data xfer buffer in segment:offset format.
+;
+; Details qStartLba
+; It contains the absolute LBA of the device. The value can be from 0 to
+; (total #of sectors - 1).
+;-------------------------------------------------------------------------
+; Result Buffer in INT13 Function 48h
+;ExtI13DriveInfo STRUC
+; wBufferSize DW ? ;Input buffer size in bytes
+; wInfoFlags DW ? ;Information flags
+; dNumCyls DD ? ;#of cylinders (1-based)
+; dNumHeads DD ? ;#of heads (1-based)
+; dNumSecs DD ? ;#of sectors per track (1-based)
+; qTotalSecs DQ ? ;#of sectors on disk (1-based)
+; wSectorSize DW ? ;Sector size in bytes
+; pExtTable DD ? ;Ptr to extd parameter table
+; wDevPathID DW ? ;Key for Device Path Extension
+; bDevPathLength DB ? ;Device path info length (including key) in bytes
+; bReserved DB ? ;Reserved (set to 00h)
+; wReserved DW ? ;Reserved (set to 0000h)
+; dHostBus DD ? ;Host Bus Type in ASCII
+; aInterfaceType DB 8 DUP (?) ;Interface Type in ASCII
+; aInterfacePath DB 8 DUP (?) ;Interface Path
+; aDevPath DB 8 DUP (?) ;Device Path
+; bReserved1 DB ? ;Reserved (set to 00h)
+; bDevPathChksum DB ? ;Checksum of device path info including wKey field
+;ExtI13DriveInfo ENDS
+
+; Details of wSize field
+; It contains the maximum size of the supplied buffer in bytes.
+; If buffer size < 1E, function does not return dPtrDpte field.
+; If buffer size >= 1E, it should be set to 1E on exit.
+; If 1A <= buffer size <= 1D, it should be set to 1A on exit.
+; If buffer size < 1A, function returns error.
+; Details of wInfoFlag field
+; Bit-0 = 1, DMA boundary errors handled transparently
+; Bit-1 = 1, Device geometry (in dCylinder, dHead, dSpt fields) is valid
+; Bit-2 = 1, Removable Media (Bit6-4 are NOT valid if this Bit-2 = 0)
+; Bit-3 = 1, Device supports write with verify on
+; Bit-4 = 1, Device supports media change notification
+; Bit-5 = 1, Media can be locked
+; Bit-6 = 1, Device geometry is set to maximum and no media is present when
+; this Bit-6 is set to 1
+; Bit-7 = 1, INT13 Function 50h supported
+; Bit15-8....Reserved
+; Details of dCylinder field
+; It contains physical #of cylinders (1-based). INT13 Function 08h returns
+; logical #of cylinders.
+; Details of dHead field
+; It contains physical #of heads (1-based). INT13 Function 08h returns
+; logical #of heads.
+; Details of dSpt field
+; It contains physical #of sectors/track (1-based). INT13 Function 08h returns
+; logical #of sectors/track.
+; Details of qTotalSector field
+; It contains the total #of sectors (1-based) in the device. If total #of
+; sectors > 15482880 (decimal), then bit-1 of wInfoFlag should be set to 0
+; indicating device geometry is not valid.
+; Details dPtrDpte field
+; This field is present only when INT13 Function 41h returns a 1 in bit-2 of
+; output CX.
+; Details of wKey field
+; It contains BEDDh signature indicating presence of device path information.
+; Details of bDevicePathInfoLength
+; It contains the length of device path information. The length includes the
+; wKey field.
+; Details of bHostBusType field
+; It contains ASCII string identifying Host Bus.
+; 'PCI ' PCI Local Bus 50 43 49 20
+; 'ISA ' Legacy 16bit fixed bus 49 53 41 20
+; 'PCIX' PCI-X Bus 50 43 49 58
+; 'XPRS' PCI Express 58 50 52 53
+; Details of bInterfaceType field
+; It contains ASCII string identifying Interface
+; 'ATA ' Device using ATA command 41 54 41 20 20 20 20 20
+; 'ATAPI ' Device using ATAPI commands 41 54 41 50 49 20 20 20
+; 'USB ' USB Mass Storage device 55 53 42 20 20 20 20 20
+; 'SATA ' Serial ATA 53 41 54 41 20 20 20 20
+; Details of qInterfacePath field (offset 30h to 37h)
+; The content depends on Host Bus Type (bHostBusType field)
+; Host Bus Offset Type Content
+; ISA 30h Word 16bit base address
+; 32h Word Should be 0000h
+; 34h Dword Should be 00000000h
+; PCI 30h Byte PCI Bus Number
+; 31h Byte PCI Slot Number
+; 32h Byte PCI Function Number
+; 33h Byte Channel Number (FF if not used)
+; 34h Dword Should be 00000000h
+; Details of bDevicePath field (offset 38h to 47h)
+; The content depends on Interface Type (bInterfaceType field)
+; Interface Offset Type Content
+; SATA 38h Byte SATA Port# (0-based)
+; 39h-57h 15byte Set to 0
+; Details of bChecksum field (offset 49h)
+; It contains the checksum of device path information including wKey field.
+; The byte addition of all bytes in device path information including the
+; checksum (offset 1Eh-49h) is 00.
+;-------------------------------------------------------------------------
+; Extra Functions that are called using interface similar to INT13
+API_DEV_RESET_FUNC equ 00h ; Reset Device
+API_PORT_RESET_FUNC equ 01h ; Reset Port
+API_DEVICE_ID_FUNC equ 02h ; Identify device data
+API_ATAPI_READ_FUNC equ 03h ; Read ATAPI device
+API_SMART_ENABLE_FUNC equ 04h ; Enable SMART feature
+API_SMART_PROMPT_FUNC equ 05h ; Prop SMART events for errors
+API_FREEZE_LOCK_FUNC equ 06h
+API_SMART_DISABLE_FUNC equ 07h ;Disable SMART feature ;(EIP9252+)
+ ;(EIP9321+)>>> Add SMART Function
+API_RETURN_SMART_STATUS_FUNC equ 08h ;Return SMART status
+API_SMART_READ_DATA_FUNC equ 09h ;Read SMART Data
+API_SMART_SHORT_SELFTEST_FUNC equ 0Ah ;SMART Execute Off-Line Immediate
+API_SMART_EXTENDED_SELFTEST_FUNC equ 0Bh ;SMART Execute Off-Line Immediate
+ ;<<<(EIP9321+)
+
+;-------------------------------------------------------------------------
+; Runtime Attribute: bit-mapped information
+A_EBDA_USED equ 01h ; Bit-0 = 1, Use EBDA memory for CLCTFIS area
+ ; Bit-1...Reserved for internal use
+ ; Bit7-2..Reserved for future use
+
+;-------------------------------------------------------------------------
+; Equates and structures of Virtual DMA Services (VDS)
+;-------------------------------------------------------------------------
+; DDS (DMA Descriptor structure): Used to Lock/Unlock DMA region. The fields
+; namely, dRegionSize, dRegionOffset, wRegionSegment need to be
+; initialized with proper values before calling Lock function. The Lock
+; function fills wBufferId and dRegionPhysicalAddress fields. The same
+; DDS, as returned by Lock function, needs to be used while calling
+; UnLock function.
+DDS_STRUC struc
+ dRegionSize dd ? ; Region Size in bytes (filled by caller)
+ dRegionOffset dd ? ; Region Offset (filled by caller)
+ wRegionSegment dw ? ; Region Segment (filled by caller)
+ wBufferId dw ? ; Buffer ID (filled by VDS function)
+ dRegionPhysicalAddress dd ? ; Physical address of region (filled by VDS function)
+DDS_STRUC ends
+
+; EDDS (Extended DMA Descriptor structure): EDDS contains EDDS Header followed
+; by one or more EDDS entry. The maximum #of entries that EDDS can
+; accommodate is limited by the space available for EDDS. In this
+; implementation, space for maximum 16 entries are available in EDDS.
+MAX_NO_OF_EDDS_ENTRY equ 16 ; Max #of entries EDDS can accommodate
+
+EDDS_HEADER_STRUC struc
+ dRegionSize dd ? ; Region Size in bytes (filled by caller)
+ dRegionOffset dd ? ; Region Offset (filled by caller)
+ wRegionSegment dw ? ; Region Segment (filled by caller)
+ wReserved dw ? ; Reserved (filled by caller)
+ wNoOfAvailableEntry dw ? ; #of entries available in EDDS (filled by caller)
+ wNoOfUsedEntry dw ? ; #of entries used in EDDS (filled by VDS function)
+EDDS_HEADER_STRUC ends
+
+EDDS_ENTRY_STRUC struc
+ dRegionPhysicalAddress dd ? ; Physical address of region (filled by VDS function)
+ dRegionSize dd ? ; Region size in bytes (filled by VDS function)
+EDDS_ENTRY_STRUC ends
+
+;-------------------------------------------------------------------------
+; EQUATES FOR COMMAND LIST, COMMAND TABLE, FIS, DDS, EDDS
+; CLCTFIS area is in EBDA, both DDS and EDDS are in EBDA.
+;-------------------------------------------------------------------------
+SIZE_CMD_LIST equ 1024 ; 1kbytes for command list
+SIZE_FIS equ 0256 ; 256bytes for FIS
+SIZE_CMD_TABLE equ 0384 ; 384bytes for command table
+;
+SIZE_DDS equ size DDS_STRUC ; 16bytes for DDS
+SIZE_EDDS equ size EDDS_HEADER_STRUC + \
+ (MAX_NO_OF_EDDS_ENTRY * (size EDDS_ENTRY_STRUC)); 272bytes for EDDS
+
+SIZE_ALIGN_BUFFER equ BLOCK_SIZE+2 ;(v1.07)
+
+SIZE_CLCTFIS_AREA_K equ 4 ; CLCTFIS area in unit of 1k in system memory/EBDA
+SIZE_CLCTFIS_AREA_B equ SIZE_CLCTFIS_AREA_K*1024 ; CLCTFIS area in bytes in system memory/EBDA
+
+; Equates for start offset of different areas
+; Command List at offset 0000h, FIS at offset 0400h, Command Table at
+; offset 0500h.
+START_CMD_LIST equ 0000h ; Command List must be 1kbyte aligned
+START_FIS equ START_CMD_LIST+SIZE_CMD_LIST ; FIS must be 256byte aligned
+START_CMD_TABLE equ START_FIS+SIZE_FIS ; Command table must be 128byte aligned
+START_DDS equ START_CMD_TABLE+SIZE_CMD_TABLE ; Start of DDS
+START_EDDS equ START_DDS+SIZE_DDS ; Start of EDDS
+START_ALIGN_BUFFER equ START_EDDS+SIZE_EDDS ; Start of DMA Alignment Buffer
+START_LOCAL_BUFFER equ START_ALIGN_BUFFER+SIZE_ALIGN_BUFFER ; Start of Local Buffer(v1.07)
+
+;-------------------------------------------------------------------------
+; INT13 FUNCTION TABLE STRUCTURE
+;-------------------------------------------------------------------------
+AI13_FUNC_STRUC struc
+ bFuncNum db ? ; Function#
+ wFuncProc dw ? ; Offset of Execution routine
+AI13_FUNC_STRUC ends
+
+;-------------------------------------------------------------------------
+; EQUATES OF DIFFERENT PARAMETERS IN STACK
+;-------------------------------------------------------------------------
+;
+; Stack equates for PUSH GS/PUSH FS/PUSH ES/PUSH DS/PUSHAD
+; after allocating N bytes in stack
+;
+; GS, FS, ES, DS positions in stack PUSH GS
+; PUSH FS
+; PUSH ES
+; PUSH DS
+; PUSHAD
+; sub sp, SIZE_AHCI_INT13_MISC_STACK
+;
+TASKF_STRUC STRUC
+ CmdListBase dd ? ;32bit Command List base address
+ CmdTableBase dd ? ;32bit Command Table base address
+ FisRecBase dd ? ;32bit FIS Receive base address
+ HbaBase dd ? ;32bit HBA Base address
+ CmdListPtr dd ? ;Ptr (Seg:Off) to Command List
+ CmdTablePtr dd ? ;Ptr (Seg:Off) to Command Table
+ FisRecPtr dd ? ;Ptr (Seg:Off) to FIS Receive
+ DdsPtr dd ? ;Ptr (Seg:off) to DDS
+ EddsPtr dd ? ;Ptr (Seg:off) to EDDS
+ DevInfoTablePtr dd ? ;Ptr (Seg:off) to Device Info Table
+ PortNum db ? ;Port# (0-based) on Controller
+ bControllerNo db ?
+ Selector db ? ;Device Selector
+ InfoFlag db ? ;Device Info Flag
+ RequestedSectorCount db ? ;#of sector(s) access requested
+ AccessedSectorCount db ? ;#of sector(s) actually accessed
+ CmdSlotMask db ? ;Bit-mask of slot(s) used in command list
+ CmdSlotNum db ? ;Slot# (0-based) used in command list
+ Attribute db ? ;Bit-mapped attribute of misc information
+ Port21 db ? ;Content of Port21
+ PortA1 db ? ;Content of PortA1
+ ReservedDD1 dd ? ;Reserved
+ ReservedDD2 dd ? ;Reserved
+ ModUserBufferOfs dw ? ;Offset of modified user buffer
+ ModUserBufferSeg dw ? ;Segment of modified user buffer
+ ModUserBufferSize dw ? ;Size in Dwords (1-based) of modified user buffer
+ OrgUserBufferOfs dw ? ;Original segment of user buffer, to overcome unaligned user buffer
+ OrgUserBufferSeg dw ? ;Original Offset of user buffer, to overcome unaligned user buffer
+ AlignBufferOfs dw ? ;Offset to Alignment buffer, to be used for temp DMA alignment buffer
+ AlignBufferSeg dw ? ;Segment to Alignment buffer, to be used for temp DMA alignment buffer
+TASKF_STRUC ENDS
+
+PUSHAD_STRUC STRUC
+
+ StackFS dw ?
+ StackDS dw ?
+ StackES dw ?
+ StackGS dw ?
+
+ StackEDI dd ?
+ StackESI dd ?
+ StackEBP dd ?
+ StackESP dd ?
+ StackEBX dd ?
+ StackEDX dd ?
+ StackECX dd ?
+ StackEAX dd ?
+
+PUSHAD_STRUC ENDS
+
+;SIZE_AHCI_INT13_MISC_STACK equ AI13_STACK_BUFFER_STRUC.StackEDI ; EDI is the last in PUSHAD
+
+
+S_AHCI_STACK struc
+TaskFile TASKF_STRUC <>
+Stack PUSHAD_STRUC <>
+S_AHCI_STACK ends
+
+ ;(amiahcix+)>
+;----------------------------------------------------------------------------
+; AHCI error equates
+;----------------------------------------------------------------------------
+
+; 000h-03Fh : CIDs for CORE compnents.
+; Used for stBIOSError.wErrorCode[15:8]
+CID_AHCI EQU 004h
+
+;---------------------------------------;
+; AHCI_x_ERR
+;---------------------------------------;
+EQU_AHCI_ERR macro COUNT
+ AHCI_&COUNT&_ERR EQU (CID_AHCI SHL 8) + COUNT
+endm
+
+AHCI_ACCESS STRUCT
+ Index dw ?
+ Data dw ?
+ BaseAddress dd ?
+AHCI_ACCESS ENDS
+
+; builds 64 AHCI_x_ERR:
+
+; AHCI_0_ERR EQU (CID_AHCI SHL 8) + 0
+; AHCI_1_ERR EQU (CID_AHCI SHL 8) + 1
+; AHCI_2_ERR EQU (CID_AHCI SHL 8) + 2
+; AHCI_3_ERR EQU (CID_AHCI SHL 8) + 3
+; .
+; .
+ATA_COUNT = 0 ; starts from AHCI_0_err
+REPEAT 64 ; Max 64 AHCI errors
+ EQU_AHCI_ERR %ATA_COUNT
+ ATA_COUNT = ATA_COUNT+1
+ENDM
+;---------------------------------------;
+ ;<(amiahcix+)
+
+
+;-------------------------------------------------------------------------
+;****************************************************************************
+;****************************************************************************
+;** **
+;** (C)Copyright 1985-2011, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone (770)-246-8600 **
+;** **
+;****************************************************************************
+;****************************************************************************
diff --git a/Chipset/eM/Ahci/AInt13Csp.c b/Chipset/eM/Ahci/AInt13Csp.c
new file mode 100644
index 0000000..44365ba
--- /dev/null
+++ b/Chipset/eM/Ahci/AInt13Csp.c
@@ -0,0 +1,111 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+
+//****************************************************************************
+// $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AInt13Csp.c 3 2/10/11 10:52a Rameshr $
+//
+// $Revision: 3 $
+//
+// $Date: 2/10/11 10:52a $
+//
+//****************************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/AInt13Csp.c $
+//
+// 3 2/10/11 10:52a Rameshr
+// [TAG] EIP53704
+// [Category] Improvement
+// [Description] AMI headers update for Alaska Ahci Driver
+// [Files] AHCIACC.ASM
+// HACCESS.EQU
+// AHCI.EQU
+// AINT13.EQU
+// AInt13Csp.c
+//
+// 2 5/28/08 9:44a Rameshraju
+// Updated the AMI Address.
+//
+// 1 12/07/07 11:17a Olegi
+//
+//****************************************************************************
+
+//<AMI_FHDR_START>
+//----------------------------------------------------------------------------
+//
+// Name: AINT13CSP.C
+// Description: AHCI INT13 Support Chipset Configuration File
+//
+//----------------------------------------------------------------------------
+//<AMI_FHDR_END>
+
+#define LBAR_REGISTER 0x20
+#define LBAR_ADDRESS_MASK 0xFFFFFFE0
+#define INDEX_OFFSET_FROM_LBAR 0x10
+#define DATA_OFFSET_FROM_LBAR 0x14
+
+#include "AmiDxeLib.h"
+#include "Protocol\PciIo.h"
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Name: GetAccessInfo
+//
+// Description: This is chipset porting routine that returns index/data ports
+// to access memory-mapped registers.
+//
+// Input: PciIo
+//
+// Output: EFI_SUCCESS - Access information is collected
+// EFI_ACCESS_DENIED - No Access information avaliable
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS
+GetAccessInfo (
+ IN EFI_PCI_IO_PROTOCOL *PciIo,
+ OUT UINT16 *AccessIndexPort,
+ OUT UINT16 *AccessDataPort
+)
+{
+ EFI_STATUS Status;
+ UINT32 lbar;
+
+ Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, LBAR_REGISTER, 1, &lbar);
+ ASSERT_EFI_ERROR(Status);
+
+ lbar &= LBAR_ADDRESS_MASK; // Legacy Bus Master Base Address
+
+ *AccessIndexPort = (UINT16)lbar + INDEX_OFFSET_FROM_LBAR;
+ *AccessDataPort = (UINT16)lbar + DATA_OFFSET_FROM_LBAR;
+
+ return EFI_SUCCESS;
+
+}
+
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
diff --git a/Chipset/eM/Ahci/AhciAccess.c b/Chipset/eM/Ahci/AhciAccess.c
new file mode 100644
index 0000000..36ea264
--- /dev/null
+++ b/Chipset/eM/Ahci/AhciAccess.c
@@ -0,0 +1,252 @@
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//**********************************************************************
+
+//**********************************************************************
+// $Header: /Alaska/SOURCE/Modules/AHCI/AhciAccess.c 3 2/11/11 4:09a Rameshr $
+//
+// $Revision: 3 $
+//
+// $Date: 2/11/11 4:09a $
+//**********************************************************************
+// Revision History
+// ----------------
+// $Log: /Alaska/SOURCE/Modules/AHCI/AhciAccess.c $
+//
+// 3 2/11/11 4:09a Rameshr
+// [TAG] EIP53704
+// [Category] Improvement
+// [Description] AMI headers update for Alaska Ahci Driver
+// [Files] AhciAccess.c
+//
+// 2 5/07/10 11:51a Krishnakumarg
+// Update for coding standard.
+//
+// 1 5/28/08 9:49a Rameshraju
+// Initial Check-in for Index/Data access method.
+//
+//**********************************************************************
+//<AMI_FHDR_START>
+//
+// Name: AhciAccess.c
+//
+// Description: Provides Index Data Port Access to AHCI Controller
+//
+//<AMI_FHDR_END>
+//**********************************************************************
+//#include <AmiDxeLib.h>
+
+#define LBAR_REGISTER 0x20
+#define LBAR_ADDRESS_MASK 0xFFFFFFE0
+#define INDEX_OFFSET_FROM_LBAR 0x10
+#define DATA_OFFSET_FROM_LBAR 0x14
+
+#include "AmiDxeLib.h"
+#include "Protocol\PciIo.h"
+
+UINT16 IndexPort, DataPort;
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Name: InitilizeIndexDataPortAddress
+//
+// Description: This is chipset porting routine that returns index/data ports
+// to access memory-mapped registers.
+//
+// Input: PciIo
+//
+// Output: EFI_SUCCESS - Access information is collected
+// EFI_ACCESS_DENIED - No Access information avaliable
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+
+EFI_STATUS
+InitilizeIndexDataPortAddress (
+ IN EFI_PCI_IO_PROTOCOL *PciIo
+)
+{
+ EFI_STATUS Status;
+ UINT32 lbar;
+
+ Status = PciIo->Pci.Read(PciIo, EfiPciIoWidthUint32, LBAR_REGISTER, 1, &lbar);
+ ASSERT_EFI_ERROR(Status);
+
+ lbar &= LBAR_ADDRESS_MASK; // Legacy Bus Master Base Address
+
+ IndexPort = (UINT16)lbar + INDEX_OFFSET_FROM_LBAR;
+ DataPort = (UINT16)lbar + DATA_OFFSET_FROM_LBAR;
+
+ return EFI_SUCCESS;
+
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Name: ReadDataDword
+//
+// Description: Read the Dword Data using Index/Data access method
+//
+// Input: BaseAddress - BaseAddress of AHCI Controller
+// Index - Index address to read
+//
+// Output: Value Read
+//
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT32
+ReadDataDword(
+ IN UINTN BaseAddr,
+ IN UINTN Index
+)
+{
+ IoWrite32(IndexPort, (UINT32)Index);
+ return IoRead32(DataPort);
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Name: WriteDataDword
+//
+// Description: WriteRead the Dword Data using Index/Data access method
+//
+// Input: BaseAddress - BaseAddress of AHCI Controller
+// Index - Index address to Write
+// Data - Data to be written
+//
+// Output: Nothing
+//
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+WriteDataDword(
+ IN UINTN BaseAddr,
+ IN UINTN Index,
+ IN UINTN Data
+)
+{
+ IoWrite32(IndexPort, (UINT32)Index);
+ IoWrite32(DataPort, (UINT32)Data);
+}
+
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Name: ReadDataDword
+//
+// Description: Read the Word Data using Index/Data access method
+//
+// Input: BaseAddress - BaseAddress of AHCI Controller
+// Index - Index address to read
+//
+// Output: Value Read
+//
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT16
+ReadDataWord(
+ IN UINTN BaseAddr,
+ IN UINTN Index
+)
+{
+ IoWrite32(IndexPort, (UINT32)Index);
+ return (UINT16)IoRead32(DataPort);
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Name: WriteDataDword
+//
+// Description: WriteRead the word Data using Index/Data access method
+//
+// Input: BaseAddress - BaseAddress of AHCI Controller
+// Index - Index address to Write
+// Data - Data to be written
+//
+// Output: Nothing
+//
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+WriteDataWord(
+ IN UINTN BaseAddr,
+ IN UINTN Index,
+ IN UINTN Data
+)
+{
+ IoWrite32(IndexPort, (UINT32)Index);
+ IoWrite32(DataPort, (UINT16)Data);
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Name: ReadDataDword
+//
+// Description: Read the Byte Data using Index/Data access method
+//
+// Input: BaseAddress - BaseAddress of AHCI Controller
+// Index - Index address to read
+//
+// Output: Value Read
+//
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+UINT8
+ReadDataByte(
+ IN UINTN BaseAddr,
+ IN UINTN Index
+)
+{
+ IoWrite32(IndexPort, (UINT32)Index);
+ return (UINT8)IoRead32(DataPort);
+}
+//<AMI_PHDR_START>
+//----------------------------------------------------------------------------
+// Name: WriteDataByte
+//
+// Description: WriteRead the Dword Data using Index/Data access method
+//
+// Input: BaseAddress - BaseAddress of AHCI Controller
+// Index - Index address to Write
+// Data - Data to be written
+//
+// Output: Nothing
+//
+//
+//-------------------------------------------------------------------------
+//<AMI_PHDR_END>
+VOID
+WriteDataByte(
+ IN UINTN BaseAddr,
+ IN UINTN Index,
+ IN UINTN Data
+)
+{
+ IoWrite32(IndexPort, (UINT32)Index);
+ IoWrite8(DataPort, (UINT8)Data);
+}
+
+//**********************************************************************
+//**********************************************************************
+//** **
+//** (C)Copyright 1985-2011, American Megatrends, Inc. **
+//** **
+//** All Rights Reserved. **
+//** **
+//** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+//** **
+//** Phone: (770)-246-8600 **
+//** **
+//**********************************************************************
+//********************************************************************** \ No newline at end of file
diff --git a/Chipset/eM/Ahci/AhciAccess.cif b/Chipset/eM/Ahci/AhciAccess.cif
new file mode 100644
index 0000000..d5a2046
--- /dev/null
+++ b/Chipset/eM/Ahci/AhciAccess.cif
@@ -0,0 +1,8 @@
+<component>
+ name = "AHCI CSP-Template"
+ category = ModulePart
+ LocalRoot = "Chipset\eM\Ahci"
+ RefName = "ACSP"
+[files]
+"AhciAccess.c"
+<endComponent>
diff --git a/Chipset/eM/Ahci/AhciCsp.cif b/Chipset/eM/Ahci/AhciCsp.cif
new file mode 100644
index 0000000..1c12363
--- /dev/null
+++ b/Chipset/eM/Ahci/AhciCsp.cif
@@ -0,0 +1,12 @@
+<component>
+ name = "AHCI Int13 CSP-Template"
+ category = ModulePart
+ LocalRoot = "Chipset\eM\Ahci"
+ RefName = "AHCI_INT13_CSP"
+[files]
+"AHCIACC.ASM"
+"HACCESS.EQU"
+"AHCI.EQU"
+"AINT13.EQU"
+"AInt13Csp.c"
+<endComponent>
diff --git a/Chipset/eM/Ahci/HACCESS.EQU b/Chipset/eM/Ahci/HACCESS.EQU
new file mode 100644
index 0000000..53c2292
--- /dev/null
+++ b/Chipset/eM/Ahci/HACCESS.EQU
@@ -0,0 +1,108 @@
+; TITLE HACCESS.EQU - Accessing HBA memory-mapped register
+;****************************************************************************
+;****************************************************************************
+;** **
+;** (C)Copyright 1985-2011, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone (770)-246-8600 **
+;** **
+;****************************************************************************
+;****************************************************************************
+
+;****************************************************************************
+; $Header: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/HACCESS.EQU 3 2/10/11 10:52a Rameshr $
+;
+; $Revision: 3 $
+;
+; $Date: 2/10/11 10:52a $
+;
+;****************************************************************************
+; Revision History
+; ----------------
+; $Log: /Alaska/SOURCE/Modules/AHCI/INT13/CSP/HACCESS.EQU $
+;
+; 3 2/10/11 10:52a Rameshr
+; [TAG] EIP53704
+; [Category] Improvement
+; [Description] AMI headers update for Alaska Ahci Driver
+; [Files] AHCIACC.ASM
+; HACCESS.EQU
+; AHCI.EQU
+; AINT13.EQU
+; AInt13Csp.c
+;
+; 2 5/28/08 9:43a Rameshraju
+; Updated the AMI Address.
+;
+; 1 12/07/07 11:17a Olegi
+;
+; 4 12/05/06 3:16a Iminglin
+; Remove useless.
+;
+; 3 11/29/06 3:18a Iminglin
+; CSP modification.
+;
+; 2 11/23/06 10:12p Iminglin
+; Default is for ICH7.
+;
+; 1 6/09/05 11:29p Iminglin
+; Initialized version
+;
+; 1 5/20/05 2:37a Iminglin
+; Intel AHCI source
+;
+;****************************************************************************
+
+;-------------------------------------------------------------------------
+;
+; Input parameter in register CH to read/write memory-mapped registers.
+;
+;ACCESS_DATA equ 0ADh
+;
+; Output parameter in register CH from read/write memory-mapped registers.
+; This data is checked for determining whether access is successful.
+;
+;DATA_ACCESSED equ 0DAh ; Access is Successful
+ ; Any other value -> error
+;
+;-------------------------------------------------------------------------
+; Function number used for common control routine to access memory-mapped
+; registers using any access method
+;
+;READ_BYTE equ 00h ; Func# 00h for Read Byte Data
+;READ_WORD equ 01h ; Func# 01h for Read Word Data
+;READ_DWORD equ 02h ; Func# 02h for Read Dword Data
+;
+;WRITE_BYTE equ 10h ; Func# 10h for Write Byte Data
+;WRITE_WORD equ 11h ; Func# 11h for Write Word Data
+;WRITE_DWORD equ 12h ; Func# 12h for Write Dword Data
+;
+;INIT_BYTE_ARRAY equ 20h ; Func# 20h for Init Byte Array
+;INIT_WORD_ARRAY equ 21h ; Func# 21h for Init Word Array
+;INIT_DWORD_ARRAY equ 22h ; Func# 22h for Init Dword Array
+;
+;-------------------------------------------------------------------------
+;
+;RW_FUNC_STRUC struc
+; bFunction db ? ; Function#
+; wPtrToRoutine dw ? ; Offset of execution routine
+;RW_FUNC_STRUC ends
+;-------------------------------------------------------------------------
+;****************************************************************************
+;****************************************************************************
+;** **
+;** (C)Copyright 1985-2011, American Megatrends, Inc. **
+;** **
+;** All Rights Reserved. **
+;** **
+;** 5555 Oakbrook Pkwy, Suite 200, Norcross, GA 30093 **
+;** **
+;** Phone (770)-246-8600 **
+;** **
+;****************************************************************************
+;****************************************************************************
+
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